671 files changed, 83279 insertions, 27563 deletions

diff --git a/drivers/net/3c501.c b/drivers/net/3c501.c
index 1776ab61b05f..9e1c03eb97ae 100644
--- a/drivers/net/3c501.c
+++ b/drivers/net/3c501.c
@@ -158,8 +158,8 @@ static int mem_start;
 struct net_device * __init el1_probe(int unit)
 {
         struct net_device *dev = alloc_etherdev(sizeof(struct net_local));
-        static unsigned ports[] = { 0x280, 0x300, 0};
-        unsigned *port;
+        static const unsigned ports[] = { 0x280, 0x300, 0};
+        const unsigned *port;
         int err = 0;
 
         if (!dev)
diff --git a/drivers/net/3c503.c b/drivers/net/3c503.c
index 4777a1cbcd8d..d84f6e8903a5 100644
--- a/drivers/net/3c503.c
+++ b/drivers/net/3c503.c
@@ -392,8 +392,8 @@ el2_open(struct net_device *dev)
     int retval;
 
     if (dev->irq < 2) {
-        int irqlist[] = {5, 9, 3, 4, 0};
-        int *irqp = irqlist;
+        static const int irqlist[] = {5, 9, 3, 4, 0};
+        const int *irqp = irqlist;
 
         outb(EGACFR_NORM, E33G_GACFR);  /* Enable RAM and interrupts. */
         do {
diff --git a/drivers/net/3c507.c b/drivers/net/3c507.c
index ea9b7a098c9b..1e945551c144 100644
--- a/drivers/net/3c507.c
+++ b/drivers/net/3c507.c
@@ -201,7 +201,7 @@ struct net_local {
 #define RX_BUF_SIZE     (1518+14+18)    /* packet+header+RBD */
 #define RX_BUF_END              (dev->mem_end - dev->mem_start)
 
-#define TX_TIMEOUT 5
+#define TX_TIMEOUT (HZ/20)
 
 /*
   That's it: only 86 bytes to set up the beast, including every extra
@@ -311,8 +311,8 @@ static int mem_start;
 struct net_device * __init el16_probe(int unit)
 {
         struct net_device *dev = alloc_etherdev(sizeof(struct net_local));
-        static unsigned ports[] = { 0x300, 0x320, 0x340, 0x280, 0};
-        unsigned *port;
+        static const unsigned ports[] = { 0x300, 0x320, 0x340, 0x280, 0};
+        const unsigned *port;
         int err = -ENODEV;
 
         if (!dev)
diff --git a/drivers/net/3c515.c b/drivers/net/3c515.c
index cdf7226a7c43..d2bb4b254c57 100644
--- a/drivers/net/3c515.c
+++ b/drivers/net/3c515.c
@@ -98,7 +98,7 @@ static int rx_nocopy, rx_copy, queued_packet;
 #define WAIT_TX_AVAIL 200
 
 /* Operational parameter that usually are not changed. */
-#define TX_TIMEOUT  40          /* Time in jiffies before concluding Tx hung */
+#define TX_TIMEOUT  ((4*HZ)/10) /* Time in jiffies before concluding Tx hung */
 
 /* The size here is somewhat misleading: the Corkscrew also uses the ISA
    aliased registers at <base>+0x400.
diff --git a/drivers/net/3c527.c b/drivers/net/3c527.c
index 013b7c396663..8c094bae8bf3 100644
--- a/drivers/net/3c527.c
+++ b/drivers/net/3c527.c
@@ -317,13 +317,13 @@ static int __init mc32_probe1(struct net_device *dev, int slot)
         u8 POS;
         u32 base;
         struct mc32_local *lp = netdev_priv(dev);
-        static u16 mca_io_bases[]={
+        static const u16 mca_io_bases[] = {
                 0x7280,0x7290,
                 0x7680,0x7690,
                 0x7A80,0x7A90,
                 0x7E80,0x7E90
         };
-        static u32 mca_mem_bases[]={
+        static const u32 mca_mem_bases[] = {
                 0x00C0000,
                 0x00C4000,
                 0x00C8000,
@@ -333,7 +333,7 @@ static int __init mc32_probe1(struct net_device *dev, int slot)
                 0x00D8000,
                 0x00DC000
         };
-        static char *failures[]={
+        static const char * const failures[] = {
                 "Processor instruction",
                 "Processor data bus",
                 "Processor data bus",
diff --git a/drivers/net/8139too.c b/drivers/net/8139too.c
index f5166dccd8df..98517a373473 100644
--- a/drivers/net/8139too.c
+++ b/drivers/net/8139too.c
@@ -1092,10 +1092,11 @@ err_out:
 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
 {
         struct net_device *dev = pci_get_drvdata (pdev);
+        struct rtl8139_private *tp = netdev_priv(dev);
 
         assert (dev != NULL);
 
-        flush_scheduled_work();
+        cancel_delayed_work_sync(&tp->thread);
 
         unregister_netdev (dev);
 
diff --git a/drivers/net/82596.c b/drivers/net/82596.c
index e2c9c5b949f9..be1f1970c842 100644
--- a/drivers/net/82596.c
+++ b/drivers/net/82596.c
@@ -191,7 +191,7 @@ enum commands {
 #define  RX_SUSPEND     0x0030
 #define  RX_ABORT       0x0040
 
-#define TX_TIMEOUT      5
+#define TX_TIMEOUT      (HZ/20)
 
 
 struct i596_reg {
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4f1755bddf6b..4c8bfc97fb4c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1533,7 +1533,7 @@ config E100
 
           <http://support.intel.com/support/network/adapter/pro100/21397.htm>
 
-          to identify the adapter.
+          to identify the adapter.
 
           For the latest Intel PRO/100 network driver for Linux, see:
 
@@ -1786,17 +1786,17 @@ config KS8842
         tristate "Micrel KSZ8841/42 with generic bus interface"
         depends on HAS_IOMEM && DMA_ENGINE
         help
-         This platform driver is for KSZ8841(1-port) / KS8842(2-port)
-         ethernet switch chip (managed, VLAN, QoS) from Micrel or
-         Timberdale(FPGA).
+          This platform driver is for KSZ8841(1-port) / KS8842(2-port)
+          ethernet switch chip (managed, VLAN, QoS) from Micrel or
+          Timberdale(FPGA).
 
 config KS8851
-       tristate "Micrel KS8851 SPI"
-       depends on SPI
-       select MII
+        tristate "Micrel KS8851 SPI"
+        depends on SPI
+        select MII
         select CRC32
-       help
-         SPI driver for Micrel KS8851 SPI attached network chip.
+        help
+          SPI driver for Micrel KS8851 SPI attached network chip.
 
 config KS8851_MLL
         tristate "Micrel KS8851 MLL"
@@ -1944,19 +1944,12 @@ config 68360_ENET
 config FEC
         bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
         depends on M523x || M527x || M5272 || M528x || M520x || M532x || \
-                MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5
+                MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 || SOC_IMX28
         select PHYLIB
         help
           Say Y here if you want to use the built-in 10/100 Fast ethernet
           controller on some Motorola ColdFire and Freescale i.MX processors.
 
-config FEC2
-        bool "Second FEC ethernet controller (on some ColdFire CPUs)"
-        depends on FEC
-        help
-          Say Y here if you want to use the second built-in 10/100 Fast
-          ethernet controller on some Motorola ColdFire processors.
-
 config FEC_MPC52xx
         tristate "MPC52xx FEC driver"
         depends on PPC_MPC52xx && PPC_BESTCOMM
@@ -2133,25 +2126,25 @@ config IP1000
           will be called ipg.  This is recommended.
 
 config IGB
-       tristate "Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support"
-       depends on PCI
-       ---help---
-         This driver supports Intel(R) 82575/82576 gigabit ethernet family of
-         adapters.  For more information on how to identify your adapter, go
-         to the Adapter & Driver ID Guide at:
+        tristate "Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support"
+        depends on PCI
+        ---help---
+          This driver supports Intel(R) 82575/82576 gigabit ethernet family of
+          adapters.  For more information on how to identify your adapter, go
+          to the Adapter & Driver ID Guide at:
 
-         <http://support.intel.com/support/network/adapter/pro100/21397.htm>
+          <http://support.intel.com/support/network/adapter/pro100/21397.htm>
 
-         For general information and support, go to the Intel support
-         website at:
+          For general information and support, go to the Intel support
+          website at:
 
-         <http://support.intel.com>
+          <http://support.intel.com>
 
-         More specific information on configuring the driver is in
-         <file:Documentation/networking/e1000.txt>.
+          More specific information on configuring the driver is in
+          <file:Documentation/networking/e1000.txt>.
 
-         To compile this driver as a module, choose M here. The module
-         will be called igb.
+          To compile this driver as a module, choose M here. The module
+          will be called igb.
 
 config IGB_DCA
         bool "Direct Cache Access (DCA) Support"
@@ -2163,25 +2156,25 @@ config IGB_DCA
           is used, with the intent of lessening the impact of cache misses.
 
 config IGBVF
-       tristate "Intel(R) 82576 Virtual Function Ethernet support"
-       depends on PCI
-       ---help---
-         This driver supports Intel(R) 82576 virtual functions.  For more
-         information on how to identify your adapter, go to the Adapter &
-         Driver ID Guide at:
+        tristate "Intel(R) 82576 Virtual Function Ethernet support"
+        depends on PCI
+        ---help---
+          This driver supports Intel(R) 82576 virtual functions.  For more
+          information on how to identify your adapter, go to the Adapter &
+          Driver ID Guide at:
 
-         <http://support.intel.com/support/network/adapter/pro100/21397.htm>
+          <http://support.intel.com/support/network/adapter/pro100/21397.htm>
 
-         For general information and support, go to the Intel support
-         website at:
+          For general information and support, go to the Intel support
+          website at:
 
-         <http://support.intel.com>
+          <http://support.intel.com>
 
-         More specific information on configuring the driver is in
-         <file:Documentation/networking/e1000.txt>.
+          More specific information on configuring the driver is in
+          <file:Documentation/networking/e1000.txt>.
 
-         To compile this driver as a module, choose M here. The module
-         will be called igbvf.
+          To compile this driver as a module, choose M here. The module
+          will be called igbvf.
 
 source "drivers/net/ixp2000/Kconfig"
 
@@ -2233,6 +2226,7 @@ config YELLOWFIN
 config R8169
         tristate "Realtek 8169 gigabit ethernet support"
         depends on PCI
+        select FW_LOADER
         select CRC32
         select MII
         ---help---
@@ -2300,14 +2294,14 @@ config SKGE
           will be called skge.  This is recommended.
 
 config SKGE_DEBUG
-       bool "Debugging interface"
-       depends on SKGE && DEBUG_FS
-       help
-         This option adds the ability to dump driver state for debugging.
-         The file /sys/kernel/debug/skge/ethX displays the state of the internal
-         transmit and receive rings.
+        bool "Debugging interface"
+        depends on SKGE && DEBUG_FS
+        help
+          This option adds the ability to dump driver state for debugging.
+          The file /sys/kernel/debug/skge/ethX displays the state of the internal
+          transmit and receive rings.
 
-         If unsure, say N.
+          If unsure, say N.
 
 config SKY2
         tristate "SysKonnect Yukon2 support"
@@ -2326,14 +2320,14 @@ config SKY2
           will be called sky2.  This is recommended.
 
 config SKY2_DEBUG
-       bool "Debugging interface"
-       depends on SKY2 && DEBUG_FS
-       help
-         This option adds the ability to dump driver state for debugging.
-         The file /sys/kernel/debug/sky2/ethX displays the state of the internal
-         transmit and receive rings.
+        bool "Debugging interface"
+        depends on SKY2 && DEBUG_FS
+        help
+          This option adds the ability to dump driver state for debugging.
+          The file /sys/kernel/debug/sky2/ethX displays the state of the internal
+          transmit and receive rings.
 
-         If unsure, say N.
+          If unsure, say N.
 
 config VIA_VELOCITY
         tristate "VIA Velocity support"
@@ -2389,12 +2383,12 @@ config SPIDER_NET
           Cell Processor-Based Blades from IBM.
 
 config TSI108_ETH
-           tristate "Tundra TSI108 gigabit Ethernet support"
-           depends on TSI108_BRIDGE
-           help
-             This driver supports Tundra TSI108 gigabit Ethernet ports.
-             To compile this driver as a module, choose M here: the module
-             will be called tsi108_eth.
+        tristate "Tundra TSI108 gigabit Ethernet support"
+        depends on TSI108_BRIDGE
+        help
+          This driver supports Tundra TSI108 gigabit Ethernet ports.
+          To compile this driver as a module, choose M here: the module
+          will be called tsi108_eth.
 
 config GELIC_NET
         tristate "PS3 Gigabit Ethernet driver"
@@ -2573,32 +2567,32 @@ config MDIO
         tristate
 
 config CHELSIO_T1
-        tristate "Chelsio 10Gb Ethernet support"
-        depends on PCI
+        tristate "Chelsio 10Gb Ethernet support"
+        depends on PCI
         select CRC32
         select MDIO
-        help
-          This driver supports Chelsio gigabit and 10-gigabit
-          Ethernet cards. More information about adapter features and
+        help
+          This driver supports Chelsio gigabit and 10-gigabit
+          Ethernet cards. More information about adapter features and
           performance tuning is in <file:Documentation/networking/cxgb.txt>.
 
-          For general information about Chelsio and our products, visit
-          our website at <http://www.chelsio.com>.
+          For general information about Chelsio and our products, visit
+          our website at <http://www.chelsio.com>.
 
-          For customer support, please visit our customer support page at
-          <http://www.chelsio.com/support.html>.
+          For customer support, please visit our customer support page at
+          <http://www.chelsio.com/support.html>.
 
-          Please send feedback to <linux-bugs@chelsio.com>.
+          Please send feedback to <linux-bugs@chelsio.com>.
 
-          To compile this driver as a module, choose M here: the module
-          will be called cxgb.
+          To compile this driver as a module, choose M here: the module
+          will be called cxgb.
 
 config CHELSIO_T1_1G
-        bool "Chelsio gigabit Ethernet support"
-        depends on CHELSIO_T1
-        help
-          Enables support for Chelsio's gigabit Ethernet PCI cards.  If you
-          are using only 10G cards say 'N' here.
+        bool "Chelsio gigabit Ethernet support"
+        depends on CHELSIO_T1
+        help
+          Enables support for Chelsio's gigabit Ethernet PCI cards.  If you
+          are using only 10G cards say 'N' here.
 
 config CHELSIO_T3_DEPENDS
         tristate
@@ -2728,26 +2722,26 @@ config IXGBE_DCB
           If unsure, say N.
 
 config IXGBEVF
-       tristate "Intel(R) 82599 Virtual Function Ethernet support"
-       depends on PCI_MSI
-       ---help---
-         This driver supports Intel(R) 82599 virtual functions.  For more
-         information on how to identify your adapter, go to the Adapter &
-         Driver ID Guide at:
+        tristate "Intel(R) 82599 Virtual Function Ethernet support"
+        depends on PCI_MSI
+        ---help---
+          This driver supports Intel(R) 82599 virtual functions.  For more
+          information on how to identify your adapter, go to the Adapter &
+          Driver ID Guide at:
 
-         <http://support.intel.com/support/network/sb/CS-008441.htm>
+          <http://support.intel.com/support/network/sb/CS-008441.htm>
 
-         For general information and support, go to the Intel support
-         website at:
+          For general information and support, go to the Intel support
+          website at:
 
-         <http://support.intel.com>
+          <http://support.intel.com>
 
-         More specific information on configuring the driver is in
-         <file:Documentation/networking/ixgbevf.txt>.
+          More specific information on configuring the driver is in
+          <file:Documentation/networking/ixgbevf.txt>.
 
-         To compile this driver as a module, choose M here. The module
-         will be called ixgbevf.  MSI-X interrupt support is required
-         for this driver to work correctly.
+          To compile this driver as a module, choose M here. The module
+          will be called ixgbevf.  MSI-X interrupt support is required
+          for this driver to work correctly.
 
 config IXGB
         tristate "Intel(R) PRO/10GbE support"
@@ -2772,29 +2766,38 @@ config IXGB
           will be called ixgb.
 
 config S2IO
-        tristate "S2IO 10Gbe XFrame NIC"
+        tristate "Exar Xframe 10Gb Ethernet Adapter"
         depends on PCI
         ---help---
-          This driver supports the 10Gbe XFrame NIC of S2IO. 
+          This driver supports Exar Corp's Xframe Series 10Gb Ethernet Adapters.
+
           More specific information on configuring the driver is in 
           <file:Documentation/networking/s2io.txt>.
 
+          To compile this driver as a module, choose M here. The module
+          will be called s2io.
+
 config VXGE
-        tristate "Neterion X3100 Series 10GbE PCIe Server Adapter"
+        tristate "Exar X3100 Series 10GbE PCIe Server Adapter"
         depends on PCI && INET
         ---help---
-          This driver supports Neterion Inc's X3100 Series 10 GbE PCIe
+          This driver supports Exar Corp's X3100 Series 10 GbE PCIe
           I/O Virtualized Server Adapter.
+
           More specific information on configuring the driver is in
           <file:Documentation/networking/vxge.txt>.
 
+          To compile this driver as a module, choose M here. The module
+          will be called vxge.
+
 config VXGE_DEBUG_TRACE_ALL
         bool "Enabling All Debug trace statments in driver"
         default n
         depends on VXGE
         ---help---
           Say Y here if you want to enabling all the debug trace statements in
-          driver. By  default only few debug trace statements are enabled.
+          the vxge driver. By default only few debug trace statements are
+          enabled.
 
 config MYRI10GE
         tristate "Myricom Myri-10G Ethernet support"
@@ -2906,18 +2909,18 @@ config QLGE
           will be called qlge.
 
 config BNA
-        tristate "Brocade 1010/1020 10Gb Ethernet Driver support"
-        depends on PCI
-        ---help---
-          This driver supports Brocade 1010/1020 10Gb CEE capable Ethernet
-          cards.
-          To compile this driver as a module, choose M here: the module
-          will be called bna.
+        tristate "Brocade 1010/1020 10Gb Ethernet Driver support"
+        depends on PCI
+        ---help---
+          This driver supports Brocade 1010/1020 10Gb CEE capable Ethernet
+          cards.
+          To compile this driver as a module, choose M here: the module
+          will be called bna.
 
-          For general information and support, go to the Brocade support
-          website at:
+          For general information and support, go to the Brocade support
+          website at:
 
-          <http://support.brocade.com>
+          <http://support.brocade.com>
 
 source "drivers/net/sfc/Kconfig"
 
@@ -2960,6 +2963,7 @@ config TILE_NET
 config XEN_NETDEV_FRONTEND
         tristate "Xen network device frontend driver"
         depends on XEN
+        select XEN_XENBUS_FRONTEND
         default y
         help
           The network device frontend driver allows the kernel to
@@ -3239,18 +3243,18 @@ config PPP_BSDCOMP
           modules once you have said "make modules". If unsure, say N.
 
 config PPP_MPPE
-       tristate "PPP MPPE compression (encryption) (EXPERIMENTAL)"
-       depends on PPP && EXPERIMENTAL
-       select CRYPTO
-       select CRYPTO_SHA1
-       select CRYPTO_ARC4
-       select CRYPTO_ECB
-       ---help---
-         Support for the MPPE Encryption protocol, as employed by the
-         Microsoft Point-to-Point Tunneling Protocol.
-
-         See http://pptpclient.sourceforge.net/ for information on
-         configuring PPTP clients and servers to utilize this method.
+        tristate "PPP MPPE compression (encryption) (EXPERIMENTAL)"
+        depends on PPP && EXPERIMENTAL
+        select CRYPTO
+        select CRYPTO_SHA1
+        select CRYPTO_ARC4
+        select CRYPTO_ECB
+        ---help---
+          Support for the MPPE Encryption protocol, as employed by the
+          Microsoft Point-to-Point Tunneling Protocol.
+
+          See http://pptpclient.sourceforge.net/ for information on
+          configuring PPTP clients and servers to utilize this method.
 
 config PPPOE
         tristate "PPP over Ethernet (EXPERIMENTAL)"
@@ -3409,14 +3413,14 @@ config VIRTIO_NET
         depends on EXPERIMENTAL && VIRTIO
         ---help---
           This is the virtual network driver for virtio.  It can be used with
-          lguest or QEMU based VMMs (like KVM or Xen).  Say Y or M.
+          lguest or QEMU based VMMs (like KVM or Xen).  Say Y or M.
 
 config VMXNET3
-       tristate "VMware VMXNET3 ethernet driver"
-       depends on PCI && INET
-       help
-         This driver supports VMware's vmxnet3 virtual ethernet NIC.
-         To compile this driver as a module, choose M here: the
-         module will be called vmxnet3.
+        tristate "VMware VMXNET3 ethernet driver"
+        depends on PCI && INET
+        help
+          This driver supports VMware's vmxnet3 virtual ethernet NIC.
+          To compile this driver as a module, choose M here: the
+          module will be called vmxnet3.
 
 endif # NETDEVICES
diff --git a/drivers/net/Space.c b/drivers/net/Space.c
index 9bb405bd664e..068c3563e00f 100644
--- a/drivers/net/Space.c
+++ b/drivers/net/Space.c
@@ -55,8 +55,6 @@ extern struct net_device *eth16i_probe(int unit);
 extern struct net_device *i82596_probe(int unit);
 extern struct net_device *ewrk3_probe(int unit);
 extern struct net_device *el1_probe(int unit);
-extern struct net_device *wavelan_probe(int unit);
-extern struct net_device *arlan_probe(int unit);
 extern struct net_device *el16_probe(int unit);
 extern struct net_device *elmc_probe(int unit);
 extern struct net_device *elplus_probe(int unit);
@@ -68,7 +66,6 @@ extern struct net_device *ni5010_probe(int unit);
 extern struct net_device *ni52_probe(int unit);
 extern struct net_device *ni65_probe(int unit);
 extern struct net_device *sonic_probe(int unit);
-extern struct net_device *SK_init(int unit);
 extern struct net_device *seeq8005_probe(int unit);
 extern struct net_device *smc_init(int unit);
 extern struct net_device *atarilance_probe(int unit);
@@ -76,8 +73,6 @@ extern struct net_device *sun3lance_probe(int unit);
 extern struct net_device *sun3_82586_probe(int unit);
 extern struct net_device *apne_probe(int unit);
 extern struct net_device *cs89x0_probe(int unit);
-extern struct net_device *hplance_probe(int unit);
-extern struct net_device *bagetlance_probe(int unit);
 extern struct net_device *mvme147lance_probe(int unit);
 extern struct net_device *tc515_probe(int unit);
 extern struct net_device *lance_probe(int unit);
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c
index 62f21106efec..0c9217f48b72 100644
--- a/drivers/net/arm/am79c961a.c
+++ b/drivers/net/arm/am79c961a.c
@@ -340,14 +340,6 @@ am79c961_close(struct net_device *dev)
         return 0;
 }
 
-/*
- * Get the current statistics.
- */
-static struct net_device_stats *am79c961_getstats (struct net_device *dev)
-{
-        return &dev->stats;
-}
-
 static void am79c961_mc_hash(char *addr, unsigned short *hash)
 {
         if (addr[0] & 0x01) {
@@ -665,7 +657,6 @@ static const struct net_device_ops am79c961_netdev_ops = {
         .ndo_open               = am79c961_open,
         .ndo_stop               = am79c961_close,
         .ndo_start_xmit         = am79c961_sendpacket,
-        .ndo_get_stats          = am79c961_getstats,
         .ndo_set_multicast_list = am79c961_setmulticastlist,
         .ndo_tx_timeout         = am79c961_timeout,
         .ndo_validate_addr      = eth_validate_addr,
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 6028226a7270..9eb9b98a7ae3 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -1229,8 +1229,10 @@ static int __devinit eth_init_one(struct platform_device *pdev)
         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, "0", plat->phy);
         port->phydev = phy_connect(dev, phy_id, &ixp4xx_adjust_link, 0,
                                    PHY_INTERFACE_MODE_MII);
-        if ((err = IS_ERR(port->phydev)))
+        if (IS_ERR(port->phydev)) {
+                err = PTR_ERR(port->phydev);
                 goto err_free_mem;
+        }
 
         port->phydev->irq = PHY_POLL;
 
diff --git a/drivers/net/arm/w90p910_ether.c b/drivers/net/arm/w90p910_ether.c
index 4545d5a06c24..bfea499a3513 100644
--- a/drivers/net/arm/w90p910_ether.c
+++ b/drivers/net/arm/w90p910_ether.c
@@ -117,7 +117,7 @@
 #define TX_DESC_SIZE            10
 #define MAX_RBUFF_SZ            0x600
 #define MAX_TBUFF_SZ            0x600
-#define TX_TIMEOUT              50
+#define TX_TIMEOUT              (HZ/2)
 #define DELAY                   1000
 #define CAM0                    0x0
 
diff --git a/drivers/net/at1700.c b/drivers/net/at1700.c
index 89876897a6fe..f4744fc89768 100644
--- a/drivers/net/at1700.c
+++ b/drivers/net/at1700.c
@@ -150,7 +150,7 @@ struct net_local {
 #define PORT_OFFSET(o) (o)
 
 
-#define TX_TIMEOUT              10
+#define TX_TIMEOUT              (HZ/10)
 
 
 /* Index to functions, as function prototypes. */
@@ -270,9 +270,9 @@ static const struct net_device_ops at1700_netdev_ops = {
 
 static int __init at1700_probe1(struct net_device *dev, int ioaddr)
 {
-        char fmv_irqmap[4] = {3, 7, 10, 15};
-        char fmv_irqmap_pnp[8] = {3, 4, 5, 7, 9, 10, 11, 15};
-        char at1700_irqmap[8] = {3, 4, 5, 9, 10, 11, 14, 15};
+        static const char fmv_irqmap[4] = {3, 7, 10, 15};
+        static const char fmv_irqmap_pnp[8] = {3, 4, 5, 7, 9, 10, 11, 15};
+        static const char at1700_irqmap[8] = {3, 4, 5, 9, 10, 11, 14, 15};
         unsigned int i, irq, is_fmv18x = 0, is_at1700 = 0;
         int slot, ret = -ENODEV;
         struct net_local *lp = netdev_priv(dev);
diff --git a/drivers/net/atarilance.c b/drivers/net/atarilance.c
index 8cb27cb7bca1..ce0091eb06f5 100644
--- a/drivers/net/atarilance.c
+++ b/drivers/net/atarilance.c
@@ -116,7 +116,7 @@ MODULE_LICENSE("GPL");
 #define RX_RING_LEN_BITS                (RX_LOG_RING_SIZE << 5)
 #define RX_RING_MOD_MASK                (RX_RING_SIZE - 1)
 
-#define TX_TIMEOUT      20
+#define TX_TIMEOUT      (HZ/5)
 
 /* The LANCE Rx and Tx ring descriptors. */
 struct lance_rx_head {
diff --git a/drivers/net/atl1c/atl1c_main.c b/drivers/net/atl1c/atl1c_main.c
index 09b099bfab2b..a699bbf20eb5 100644
--- a/drivers/net/atl1c/atl1c_main.c
+++ b/drivers/net/atl1c/atl1c_main.c
@@ -702,6 +702,7 @@ static int __devinit atl1c_sw_init(struct atl1c_adapter *adapter)
 
 
         adapter->wol = 0;
+        device_set_wakeup_enable(&pdev->dev, false);
         adapter->link_speed = SPEED_0;
         adapter->link_duplex = FULL_DUPLEX;
         adapter->num_rx_queues = AT_DEF_RECEIVE_QUEUE;
@@ -2078,7 +2079,7 @@ static int atl1c_tso_csum(struct atl1c_adapter *adapter,
 check_sum:
         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
                 u8 css, cso;
-                cso = skb_transport_offset(skb);
+                cso = skb_checksum_start_offset(skb);
 
                 if (unlikely(cso & 0x1)) {
                         if (netif_msg_tx_err(adapter))
@@ -2444,8 +2445,9 @@ static int atl1c_close(struct net_device *netdev)
         return 0;
 }
 
-static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
+static int atl1c_suspend(struct device *dev)
 {
+        struct pci_dev *pdev = to_pci_dev(dev);
         struct net_device *netdev = pci_get_drvdata(pdev);
         struct atl1c_adapter *adapter = netdev_priv(netdev);
         struct atl1c_hw *hw = &adapter->hw;
@@ -2454,7 +2456,6 @@ static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
         u32 wol_ctrl_data = 0;
         u16 mii_intr_status_data = 0;
         u32 wufc = adapter->wol;
-        int retval = 0;
 
         atl1c_disable_l0s_l1(hw);
         if (netif_running(netdev)) {
@@ -2462,9 +2463,6 @@ static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
                 atl1c_down(adapter);
         }
         netif_device_detach(netdev);
-        retval = pci_save_state(pdev);
-        if (retval)
-                return retval;
 
         if (wufc)
                 if (atl1c_phy_power_saving(hw) != 0)
@@ -2525,12 +2523,8 @@ static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
                 AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl_data);
                 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
 
-                /* pcie patch */
-                device_set_wakeup_enable(&pdev->dev, 1);
-
                 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
                         GPHY_CTRL_EXT_RESET);
-                pci_prepare_to_sleep(pdev);
         } else {
                 AT_WRITE_REG(hw, REG_GPHY_CTRL, GPHY_CTRL_POWER_SAVING);
                 master_ctrl_data |= MASTER_CTRL_CLK_SEL_DIS;
@@ -2540,25 +2534,17 @@ static int atl1c_suspend(struct pci_dev *pdev, pm_message_t state)
                 AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl_data);
                 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
                 hw->phy_configured = false; /* re-init PHY when resume */
-                pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
         }
 
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, pci_choose_state(pdev, state));
-
         return 0;
 }
 
-static int atl1c_resume(struct pci_dev *pdev)
+static int atl1c_resume(struct device *dev)
 {
+        struct pci_dev *pdev = to_pci_dev(dev);
         struct net_device *netdev = pci_get_drvdata(pdev);
         struct atl1c_adapter *adapter = netdev_priv(netdev);
 
-        pci_set_power_state(pdev, PCI_D0);
-        pci_restore_state(pdev);
-        pci_enable_wake(pdev, PCI_D3hot, 0);
-        pci_enable_wake(pdev, PCI_D3cold, 0);
-
         AT_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
         atl1c_reset_pcie(&adapter->hw, ATL1C_PCIE_L0S_L1_DISABLE |
                         ATL1C_PCIE_PHY_RESET);
@@ -2582,7 +2568,12 @@ static int atl1c_resume(struct pci_dev *pdev)
 
 static void atl1c_shutdown(struct pci_dev *pdev)
 {
-        atl1c_suspend(pdev, PMSG_SUSPEND);
+        struct net_device *netdev = pci_get_drvdata(pdev);
+        struct atl1c_adapter *adapter = netdev_priv(netdev);
+
+        atl1c_suspend(&pdev->dev);
+        pci_wake_from_d3(pdev, adapter->wol);
+        pci_set_power_state(pdev, PCI_D3hot);
 }
 
 static const struct net_device_ops atl1c_netdev_ops = {
@@ -2886,16 +2877,16 @@ static struct pci_error_handlers atl1c_err_handler = {
         .resume = atl1c_io_resume,
 };
 
+static SIMPLE_DEV_PM_OPS(atl1c_pm_ops, atl1c_suspend, atl1c_resume);
+
 static struct pci_driver atl1c_driver = {
         .name     = atl1c_driver_name,
         .id_table = atl1c_pci_tbl,
         .probe    = atl1c_probe,
         .remove   = __devexit_p(atl1c_remove),
-        /* Power Managment Hooks */
-        .suspend  = atl1c_suspend,
-        .resume   = atl1c_resume,
         .shutdown = atl1c_shutdown,
-        .err_handler = &atl1c_err_handler
+        .err_handler = &atl1c_err_handler,
+        .driver.pm = &atl1c_pm_ops,
 };
 
 /*
diff --git a/drivers/net/atl1e/atl1e_main.c b/drivers/net/atl1e/atl1e_main.c
index ef6349bf3b33..e28f8baf394e 100644
--- a/drivers/net/atl1e/atl1e_main.c
+++ b/drivers/net/atl1e/atl1e_main.c
@@ -1649,7 +1649,7 @@ check_sum:
         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
                 u8 css, cso;
 
-                cso = skb_transport_offset(skb);
+                cso = skb_checksum_start_offset(skb);
                 if (unlikely(cso & 0x1)) {
                         netdev_err(adapter->netdev,
                                    "payload offset should not ant event number\n");
diff --git a/drivers/net/atlx/atl1.c b/drivers/net/atlx/atl1.c
index 53363108994e..3b527687c28f 100644
--- a/drivers/net/atlx/atl1.c
+++ b/drivers/net/atlx/atl1.c
@@ -2174,7 +2174,7 @@ static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
         u8 css, cso;
 
         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
-                css = (u8) (skb->csum_start - skb_headroom(skb));
+                css = skb_checksum_start_offset(skb);
                 cso = css + (u8) skb->csum_offset;
                 if (unlikely(css & 0x1)) {
                         /* L1 hardware requires an even number here */
@@ -3504,6 +3504,8 @@ static int atl1_set_ringparam(struct net_device *netdev,
         struct atl1_rfd_ring rfd_old, rfd_new;
         struct atl1_rrd_ring rrd_old, rrd_new;
         struct atl1_ring_header rhdr_old, rhdr_new;
+        struct atl1_smb smb;
+        struct atl1_cmb cmb;
         int err;
 
         tpd_old = adapter->tpd_ring;
@@ -3544,11 +3546,19 @@ static int atl1_set_ringparam(struct net_device *netdev,
                 adapter->rrd_ring = rrd_old;
                 adapter->tpd_ring = tpd_old;
                 adapter->ring_header = rhdr_old;
+                /*
+                 * Save SMB and CMB, since atl1_free_ring_resources
+                 * will clear them.
+                 */
+                smb = adapter->smb;
+                cmb = adapter->cmb;
                 atl1_free_ring_resources(adapter);
                 adapter->rfd_ring = rfd_new;
                 adapter->rrd_ring = rrd_new;
                 adapter->tpd_ring = tpd_new;
                 adapter->ring_header = rhdr_new;
+                adapter->smb = smb;
+                adapter->cmb = cmb;
 
                 err = atl1_up(adapter);
                 if (err)
diff --git a/drivers/net/atlx/atl2.c b/drivers/net/atlx/atl2.c
index 35b14bec1207..4e6f4e95a5a0 100644
--- a/drivers/net/atlx/atl2.c
+++ b/drivers/net/atlx/atl2.c
@@ -1504,8 +1504,8 @@ static void __devexit atl2_remove(struct pci_dev *pdev)
 
         del_timer_sync(&adapter->watchdog_timer);
         del_timer_sync(&adapter->phy_config_timer);
-
-        flush_scheduled_work();
+        cancel_work_sync(&adapter->reset_task);
+        cancel_work_sync(&adapter->link_chg_task);
 
         unregister_netdev(netdev);
 
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index 53eff9ba6e95..b9debcfb61a0 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -106,8 +106,6 @@ MODULE_VERSION(DRV_VERSION);
  * complete immediately.
  */
 
-struct au1000_private *au_macs[NUM_ETH_INTERFACES];
-
 /*
  * board-specific configurations
  *
diff --git a/drivers/net/ax88796.c b/drivers/net/ax88796.c
index b6da4cf3694b..4bebff3faeab 100644
--- a/drivers/net/ax88796.c
+++ b/drivers/net/ax88796.c
@@ -325,7 +325,7 @@ static void ax_block_output(struct net_device *dev, int count,
 static void
 ax_mii_ei_outbits(struct net_device *dev, unsigned int bits, int len)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         void __iomem *memr_addr = (void __iomem *)dev->base_addr + AX_MEMR;
         unsigned int memr;
 
@@ -364,7 +364,7 @@ ax_mii_ei_outbits(struct net_device *dev, unsigned int bits, int len)
 static unsigned int
 ax_phy_ei_inbits(struct net_device *dev, int no)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         void __iomem *memr_addr = (void __iomem *)dev->base_addr + AX_MEMR;
         unsigned int memr;
         unsigned int result = 0;
@@ -412,7 +412,7 @@ ax_phy_issueaddr(struct net_device *dev, int phy_addr, int reg, int opc)
 static int
 ax_phy_read(struct net_device *dev, int phy_addr, int reg)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned long flags;
         unsigned int result;
 
@@ -435,7 +435,7 @@ ax_phy_read(struct net_device *dev, int phy_addr, int reg)
 static void
 ax_phy_write(struct net_device *dev, int phy_addr, int reg, int value)
 {
-        struct ei_device *ei = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei = netdev_priv(dev);
         struct ax_device  *ax = to_ax_dev(dev);
         unsigned long flags;
 
diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c
index ecfef240a303..e94a966af418 100644
--- a/drivers/net/bcm63xx_enet.c
+++ b/drivers/net/bcm63xx_enet.c
@@ -1097,7 +1097,7 @@ static int bcm_enet_stop(struct net_device *dev)
         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 
         /* make sure no mib update is scheduled */
-        flush_scheduled_work();
+        cancel_work_sync(&priv->mib_update_task);
 
         /* disable dma & mac */
         bcm_enet_disable_dma(priv, priv->tx_chan);
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h
index 4594a28b1f66..add0b93350dd 100644
--- a/drivers/net/benet/be.h
+++ b/drivers/net/benet/be.h
@@ -38,14 +38,17 @@
 #define BE_NAME                 "ServerEngines BladeEngine2 10Gbps NIC"
 #define BE3_NAME                "ServerEngines BladeEngine3 10Gbps NIC"
 #define OC_NAME                 "Emulex OneConnect 10Gbps NIC"
-#define OC_NAME1                "Emulex OneConnect 10Gbps NIC (be3)"
+#define OC_NAME_BE              OC_NAME "(be3)"
+#define OC_NAME_LANCER          OC_NAME "(Lancer)"
 #define DRV_DESC                "ServerEngines BladeEngine 10Gbps NIC Driver"
 
 #define BE_VENDOR_ID            0x19a2
+#define EMULEX_VENDOR_ID        0x10df
 #define BE_DEVICE_ID1           0x211
 #define BE_DEVICE_ID2           0x221
-#define OC_DEVICE_ID1           0x700
-#define OC_DEVICE_ID2           0x710
+#define OC_DEVICE_ID1           0x700   /* Device Id for BE2 cards */
+#define OC_DEVICE_ID2           0x710   /* Device Id for BE3 cards */
+#define OC_DEVICE_ID3           0xe220  /* Device id for Lancer cards */
 
 static inline char *nic_name(struct pci_dev *pdev)
 {
@@ -53,7 +56,9 @@ static inline char *nic_name(struct pci_dev *pdev)
         case OC_DEVICE_ID1:
                 return OC_NAME;
         case OC_DEVICE_ID2:
-                return OC_NAME1;
+                return OC_NAME_BE;
+        case OC_DEVICE_ID3:
+                return OC_NAME_LANCER;
         case BE_DEVICE_ID2:
                 return BE3_NAME;
         default:
@@ -149,6 +154,7 @@ struct be_eq_obj {
         u16 min_eqd;            /* in usecs */
         u16 max_eqd;            /* in usecs */
         u16 cur_eqd;            /* in usecs */
+        u8  msix_vec_idx;
 
         struct napi_struct napi;
 };
@@ -214,7 +220,9 @@ struct be_rx_obj {
         struct be_rx_stats stats;
         u8 rss_id;
         bool rx_post_starved;   /* Zero rx frags have been posted to BE */
-        u32 cache_line_barrier[16];
+        u16 last_frag_index;
+        u16 rsvd;
+        u32 cache_line_barrier[15];
 };
 
 struct be_vf_cfg {
@@ -234,7 +242,7 @@ struct be_adapter {
         u8 __iomem *db;         /* Door Bell */
         u8 __iomem *pcicfg;     /* PCI config space */
 
-        spinlock_t mbox_lock;   /* For serializing mbox cmds to BE card */
+        struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
         struct be_dma_mem mbox_mem;
         /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
          * is stored for freeing purpose */
@@ -260,6 +268,8 @@ struct be_adapter {
         u32 num_rx_qs;
         u32 big_page_size;      /* Compounded page size shared by rx wrbs */
 
+        u8 msix_vec_next_idx;
+
         struct vlan_group *vlan_grp;
         u16 vlans_added;
         u16 max_vlans;  /* Number of vlans supported */
@@ -299,8 +309,8 @@ struct be_adapter {
 
         bool sriov_enabled;
         struct be_vf_cfg vf_cfg[BE_MAX_VF];
-        u8 base_eq_id;
         u8 is_virtfn;
+        u32 sli_family;
 };
 
 #define be_physfn(adapter) (!adapter->is_virtfn)
@@ -309,6 +319,8 @@ struct be_adapter {
 #define BE_GEN2 2
 #define BE_GEN3 3
 
+#define lancer_chip(adapter)            (adapter->pdev->device == OC_DEVICE_ID3)
+
 extern const struct ethtool_ops be_ethtool_ops;
 
 #define tx_stats(adapter)               (&adapter->tx_stats)
@@ -416,10 +428,17 @@ static inline u8 is_udp_pkt(struct sk_buff *skb)
 static inline void be_check_sriov_fn_type(struct be_adapter *adapter)
 {
         u8 data;
-
-        pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
-        pci_read_config_byte(adapter->pdev, 0xFE, &data);
-        adapter->is_virtfn = (data != 0xAA);
+        u32 sli_intf;
+
+        if (lancer_chip(adapter)) {
+                pci_read_config_dword(adapter->pdev, SLI_INTF_REG_OFFSET,
+                                                                &sli_intf);
+                adapter->is_virtfn = (sli_intf & SLI_INTF_FT_MASK) ? 1 : 0;
+        } else {
+                pci_write_config_byte(adapter->pdev, 0xFE, 0xAA);
+                pci_read_config_byte(adapter->pdev, 0xFE, &data);
+                adapter->is_virtfn = (data != 0xAA);
+        }
 }
 
 static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c
index e4465d222a7d..0c7811faf72c 100644
--- a/drivers/net/benet/be_cmds.c
+++ b/drivers/net/benet/be_cmds.c
@@ -323,7 +323,12 @@ static int be_mbox_notify_wait(struct be_adapter *adapter)
 
 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
 {
-        u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
+        u32 sem;
+
+        if (lancer_chip(adapter))
+                sem  = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
+        else
+                sem  = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
 
         *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
         if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
@@ -462,7 +467,8 @@ int be_cmd_fw_init(struct be_adapter *adapter)
         u8 *wrb;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = (u8 *)wrb_from_mbox(adapter);
         *wrb++ = 0xFF;
@@ -476,7 +482,7 @@ int be_cmd_fw_init(struct be_adapter *adapter)
 
         status = be_mbox_notify_wait(adapter);
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -491,7 +497,8 @@ int be_cmd_fw_clean(struct be_adapter *adapter)
         if (adapter->eeh_err)
                 return -EIO;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = (u8 *)wrb_from_mbox(adapter);
         *wrb++ = 0xFF;
@@ -505,7 +512,7 @@ int be_cmd_fw_clean(struct be_adapter *adapter)
 
         status = be_mbox_notify_wait(adapter);
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 int be_cmd_eq_create(struct be_adapter *adapter,
@@ -516,7 +523,8 @@ int be_cmd_eq_create(struct be_adapter *adapter,
         struct be_dma_mem *q_mem = &eq->dma_mem;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -546,7 +554,7 @@ int be_cmd_eq_create(struct be_adapter *adapter,
                 eq->created = true;
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -558,7 +566,8 @@ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
         struct be_cmd_req_mac_query *req;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -583,7 +592,7 @@ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -667,7 +676,8 @@ int be_cmd_cq_create(struct be_adapter *adapter,
         void *ctxt;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -680,16 +690,36 @@ int be_cmd_cq_create(struct be_adapter *adapter,
                 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
 
         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
+        if (lancer_chip(adapter)) {
+                req->hdr.version = 1;
+                req->page_size = 1; /* 1 for 4K */
+                AMAP_SET_BITS(struct amap_cq_context_lancer, coalescwm, ctxt,
+                                                                coalesce_wm);
+                AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
+                                                                no_delay);
+                AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
+                                                __ilog2_u32(cq->len/256));
+                AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
+                AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
+                                                                ctxt, 1);
+                AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
+                                                                ctxt, eq->id);
+                AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
+        } else {
+                AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
+                                                                coalesce_wm);
+                AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
+                                                                ctxt, no_delay);
+                AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
+                                                __ilog2_u32(cq->len/256));
+                AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
+                AMAP_SET_BITS(struct amap_cq_context_be, solevent,
+                                                                ctxt, sol_evts);
+                AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
+                AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
+                AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
+        }
 
-        AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
-        AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
-        AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
-                        __ilog2_u32(cq->len/256));
-        AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
-        AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
-        AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
-        AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
-        AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 
         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
@@ -701,7 +731,7 @@ int be_cmd_cq_create(struct be_adapter *adapter,
                 cq->created = true;
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
 
         return status;
 }
@@ -724,7 +754,8 @@ int be_cmd_mccq_create(struct be_adapter *adapter,
         void *ctxt;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -737,13 +768,27 @@ int be_cmd_mccq_create(struct be_adapter *adapter,
                         OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
 
         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
+        if (lancer_chip(adapter)) {
+                req->hdr.version = 1;
+                req->cq_id = cpu_to_le16(cq->id);
+
+                AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
+                                                be_encoded_q_len(mccq->len));
+                AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
+                AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
+                                                                ctxt, cq->id);
+                AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
+                                                                 ctxt, 1);
+
+        } else {
+                AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
+                AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
+                                                be_encoded_q_len(mccq->len));
+                AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
+        }
 
-        AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
-        AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
-                be_encoded_q_len(mccq->len));
-        AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
         /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
-        req->async_event_bitmap[0] |= 0x00000022;
+        req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
         be_dws_cpu_to_le(ctxt, sizeof(req->context));
 
         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
@@ -754,7 +799,7 @@ int be_cmd_mccq_create(struct be_adapter *adapter,
                 mccq->id = le16_to_cpu(resp->id);
                 mccq->created = true;
         }
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
 
         return status;
 }
@@ -769,7 +814,8 @@ int be_cmd_txq_create(struct be_adapter *adapter,
         void *ctxt;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -801,7 +847,7 @@ int be_cmd_txq_create(struct be_adapter *adapter,
                 txq->created = true;
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
 
         return status;
 }
@@ -816,7 +862,8 @@ int be_cmd_rxq_create(struct be_adapter *adapter,
         struct be_dma_mem *q_mem = &rxq->dma_mem;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -843,7 +890,7 @@ int be_cmd_rxq_create(struct be_adapter *adapter,
                 *rss_id = resp->rss_id;
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
 
         return status;
 }
@@ -862,7 +909,8 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
         if (adapter->eeh_err)
                 return -EIO;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -899,7 +947,7 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 
         status = be_mbox_notify_wait(adapter);
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
 
         return status;
 }
@@ -915,7 +963,8 @@ int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
         struct be_cmd_req_if_create *req;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -941,7 +990,7 @@ int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
                         *pmac_id = le32_to_cpu(resp->pmac_id);
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -955,7 +1004,8 @@ int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
         if (adapter->eeh_err)
                 return -EIO;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -970,7 +1020,7 @@ int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
 
         status = be_mbox_notify_wait(adapter);
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
 
         return status;
 }
@@ -1060,7 +1110,8 @@ int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
         struct be_cmd_req_get_fw_version *req;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -1077,7 +1128,7 @@ int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
                 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -1322,7 +1373,8 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
         struct be_cmd_req_query_fw_cfg *req;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -1341,7 +1393,7 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
                 *caps = le32_to_cpu(resp->function_caps);
         }
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -1352,7 +1404,8 @@ int be_cmd_reset_function(struct be_adapter *adapter)
         struct be_cmd_req_hdr *req;
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -1365,7 +1418,7 @@ int be_cmd_reset_function(struct be_adapter *adapter)
 
         status = be_mbox_notify_wait(adapter);
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
@@ -1376,7 +1429,8 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
         u32 myhash[10];
         int status;
 
-        spin_lock(&adapter->mbox_lock);
+        if (mutex_lock_interruptible(&adapter->mbox_lock))
+                return -1;
 
         wrb = wrb_from_mbox(adapter);
         req = embedded_payload(wrb);
@@ -1396,7 +1450,7 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
 
         status = be_mbox_notify_wait(adapter);
 
-        spin_unlock(&adapter->mbox_lock);
+        mutex_unlock(&adapter->mbox_lock);
         return status;
 }
 
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h
index 8469ff061f30..83d15c8a9fa3 100644
--- a/drivers/net/benet/be_cmds.h
+++ b/drivers/net/benet/be_cmds.h
@@ -309,7 +309,7 @@ struct be_cmd_req_pmac_del {
 /******************** Create CQ ***************************/
 /* Pseudo amap definition in which each bit of the actual structure is defined
  * as a byte: used to calculate offset/shift/mask of each field */
-struct amap_cq_context {
+struct amap_cq_context_be {
         u8 cidx[11];            /* dword 0*/
         u8 rsvd0;               /* dword 0*/
         u8 coalescwm[2];        /* dword 0*/
@@ -332,14 +332,32 @@ struct amap_cq_context {
         u8 rsvd5[32];           /* dword 3*/
 } __packed;
 
+struct amap_cq_context_lancer {
+        u8 rsvd0[12];           /* dword 0*/
+        u8 coalescwm[2];        /* dword 0*/
+        u8 nodelay;             /* dword 0*/
+        u8 rsvd1[12];           /* dword 0*/
+        u8 count[2];            /* dword 0*/
+        u8 valid;               /* dword 0*/
+        u8 rsvd2;               /* dword 0*/
+        u8 eventable;           /* dword 0*/
+        u8 eqid[16];            /* dword 1*/
+        u8 rsvd3[15];           /* dword 1*/
+        u8 armed;               /* dword 1*/
+        u8 rsvd4[32];           /* dword 2*/
+        u8 rsvd5[32];           /* dword 3*/
+} __packed;
+
 struct be_cmd_req_cq_create {
         struct be_cmd_req_hdr hdr;
         u16 num_pages;
-        u16 rsvd0;
-        u8 context[sizeof(struct amap_cq_context) / 8];
+        u8 page_size;
+        u8 rsvd0;
+        u8 context[sizeof(struct amap_cq_context_be) / 8];
         struct phys_addr pages[8];
 } __packed;
 
+
 struct be_cmd_resp_cq_create {
         struct be_cmd_resp_hdr hdr;
         u16 cq_id;
@@ -349,7 +367,7 @@ struct be_cmd_resp_cq_create {
 /******************** Create MCCQ ***************************/
 /* Pseudo amap definition in which each bit of the actual structure is defined
  * as a byte: used to calculate offset/shift/mask of each field */
-struct amap_mcc_context {
+struct amap_mcc_context_be {
         u8 con_index[14];
         u8 rsvd0[2];
         u8 ring_size[4];
@@ -364,12 +382,23 @@ struct amap_mcc_context {
         u8 rsvd2[32];
 } __packed;
 
+struct amap_mcc_context_lancer {
+        u8 async_cq_id[16];
+        u8 ring_size[4];
+        u8 rsvd0[12];
+        u8 rsvd1[31];
+        u8 valid;
+        u8 async_cq_valid[1];
+        u8 rsvd2[31];
+        u8 rsvd3[32];
+} __packed;
+
 struct be_cmd_req_mcc_create {
         struct be_cmd_req_hdr hdr;
         u16 num_pages;
-        u16 rsvd0;
+        u16 cq_id;
         u32 async_event_bitmap[1];
-        u8 context[sizeof(struct amap_mcc_context) / 8];
+        u8 context[sizeof(struct amap_mcc_context_be) / 8];
         struct phys_addr pages[8];
 } __packed;
 
@@ -605,6 +634,7 @@ struct be_hw_stats {
         struct be_rxf_stats rxf;
         u32 rsvd[48];
         struct be_erx_stats erx;
+        u32 rsvd1[6];
 };
 
 struct be_cmd_req_get_stats {
diff --git a/drivers/net/benet/be_ethtool.c b/drivers/net/benet/be_ethtool.c
index 0f46366ecc48..b4be0271efe0 100644
--- a/drivers/net/benet/be_ethtool.c
+++ b/drivers/net/benet/be_ethtool.c
@@ -549,7 +549,9 @@ be_test_ddr_dma(struct be_adapter *adapter)
 {
         int ret, i;
         struct be_dma_mem ddrdma_cmd;
-        u64 pattern[2] = {0x5a5a5a5a5a5a5a5aULL, 0xa5a5a5a5a5a5a5a5ULL};
+        static const u64 pattern[2] = {
+                0x5a5a5a5a5a5a5a5aULL, 0xa5a5a5a5a5a5a5a5ULL
+        };
 
         ddrdma_cmd.size = sizeof(struct be_cmd_req_ddrdma_test);
         ddrdma_cmd.va = pci_alloc_consistent(adapter->pdev, ddrdma_cmd.size,
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h
index a2ec5df0d733..4096d9778234 100644
--- a/drivers/net/benet/be_hw.h
+++ b/drivers/net/benet/be_hw.h
@@ -32,10 +32,12 @@
 #define MPU_EP_CONTROL          0
 
 /********** MPU semphore ******************/
-#define MPU_EP_SEMAPHORE_OFFSET         0xac
-#define EP_SEMAPHORE_POST_STAGE_MASK    0x0000FFFF
-#define EP_SEMAPHORE_POST_ERR_MASK      0x1
-#define EP_SEMAPHORE_POST_ERR_SHIFT     31
+#define MPU_EP_SEMAPHORE_OFFSET         0xac
+#define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET        0x400
+#define EP_SEMAPHORE_POST_STAGE_MASK            0x0000FFFF
+#define EP_SEMAPHORE_POST_ERR_MASK              0x1
+#define EP_SEMAPHORE_POST_ERR_SHIFT             31
+
 /* MPU semphore POST stage values */
 #define POST_STAGE_AWAITING_HOST_RDY    0x1 /* FW awaiting goahead from host */
 #define POST_STAGE_HOST_RDY             0x2 /* Host has given go-ahed to FW */
@@ -66,6 +68,28 @@
 #define PCICFG_UE_STATUS_LOW_MASK               0xA8
 #define PCICFG_UE_STATUS_HI_MASK                0xAC
 
+/******** SLI_INTF ***********************/
+#define SLI_INTF_REG_OFFSET                     0x58
+#define SLI_INTF_VALID_MASK                     0xE0000000
+#define SLI_INTF_VALID                          0xC0000000
+#define SLI_INTF_HINT2_MASK                     0x1F000000
+#define SLI_INTF_HINT2_SHIFT                    24
+#define SLI_INTF_HINT1_MASK                     0x00FF0000
+#define SLI_INTF_HINT1_SHIFT                    16
+#define SLI_INTF_FAMILY_MASK                    0x00000F00
+#define SLI_INTF_FAMILY_SHIFT                   8
+#define SLI_INTF_IF_TYPE_MASK                   0x0000F000
+#define SLI_INTF_IF_TYPE_SHIFT                  12
+#define SLI_INTF_REV_MASK                       0x000000F0
+#define SLI_INTF_REV_SHIFT                      4
+#define SLI_INTF_FT_MASK                        0x00000001
+
+
+/* SLI family */
+#define BE_SLI_FAMILY           0x0
+#define LANCER_A0_SLI_FAMILY    0xA
+
+
 /********* ISR0 Register offset **********/
 #define CEV_ISR0_OFFSET                         0xC18
 #define CEV_ISR_SIZE                            4
@@ -73,6 +97,9 @@
 /********* Event Q door bell *************/
 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
+#define DB_EQ_RING_ID_EXT_MASK          0x3e00  /* bits 9-13 */
+#define DB_EQ_RING_ID_EXT_MASK_SHIFT    (2) /* qid bits 9-13 placing at 11-15 */
+
 /* Clear the interrupt for this eq */
 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 /* Must be 1 */
@@ -85,6 +112,10 @@
 /********* Compl Q door bell *************/
 #define DB_CQ_OFFSET                    0x120
 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
+#define DB_CQ_RING_ID_EXT_MASK          0x7C00  /* bits 10-14 */
+#define DB_CQ_RING_ID_EXT_MASK_SHIFT    (1)     /* qid bits 10-14
+                                                 placing at 11-15 */
+
 /* Number of event entries processed */
 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 /* Rearm bit */
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c
index 93354eee2cfd..de40d3b7152f 100644
--- a/drivers/net/benet/be_main.c
+++ b/drivers/net/benet/be_main.c
@@ -41,6 +41,7 @@ static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
         { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
         { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
         { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
+        { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)},
         { 0 }
 };
 MODULE_DEVICE_TABLE(pci, be_dev_ids);
@@ -188,6 +189,8 @@ static void be_eq_notify(struct be_adapter *adapter, u16 qid,
 {
         u32 val = 0;
         val |= qid & DB_EQ_RING_ID_MASK;
+        val |= ((qid & DB_EQ_RING_ID_EXT_MASK) <<
+                        DB_EQ_RING_ID_EXT_MASK_SHIFT);
 
         if (adapter->eeh_err)
                 return;
@@ -205,6 +208,8 @@ void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
 {
         u32 val = 0;
         val |= qid & DB_CQ_RING_ID_MASK;
+        val |= ((qid & DB_CQ_RING_ID_EXT_MASK) <<
+                        DB_CQ_RING_ID_EXT_MASK_SHIFT);
 
         if (adapter->eeh_err)
                 return;
@@ -404,7 +409,8 @@ static void be_tx_stats_update(struct be_adapter *adapter,
 }
 
 /* Determine number of WRB entries needed to xmit data in an skb */
-static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
+static u32 wrb_cnt_for_skb(struct be_adapter *adapter, struct sk_buff *skb,
+                                                                bool *dummy)
 {
         int cnt = (skb->len > skb->data_len);
 
@@ -412,12 +418,13 @@ static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
 
         /* to account for hdr wrb */
         cnt++;
-        if (cnt & 1) {
+        if (lancer_chip(adapter) || !(cnt & 1)) {
+                *dummy = false;
+        } else {
                 /* add a dummy to make it an even num */
                 cnt++;
                 *dummy = true;
-        } else
-                *dummy = false;
+        }
         BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
         return cnt;
 }
@@ -443,8 +450,18 @@ static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
                 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
                 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
                         hdr, skb_shinfo(skb)->gso_size);
-                if (skb_is_gso_v6(skb))
+                if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
                         AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
+                if (lancer_chip(adapter) && adapter->sli_family  ==
+                                                        LANCER_A0_SLI_FAMILY) {
+                        AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
+                        if (is_tcp_pkt(skb))
+                                AMAP_SET_BITS(struct amap_eth_hdr_wrb,
+                                                                tcpcs, hdr, 1);
+                        else if (is_udp_pkt(skb))
+                                AMAP_SET_BITS(struct amap_eth_hdr_wrb,
+                                                                udpcs, hdr, 1);
+                }
         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
                 if (is_tcp_pkt(skb))
                         AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
@@ -566,7 +583,7 @@ static netdev_tx_t be_xmit(struct sk_buff *skb,
         u32 start = txq->head;
         bool dummy_wrb, stopped = false;
 
-        wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
+        wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb);
 
         copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
         if (copied) {
@@ -894,11 +911,17 @@ static void be_rx_compl_discard(struct be_adapter *adapter,
         rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
         num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
 
-        for (i = 0; i < num_rcvd; i++) {
-                page_info = get_rx_page_info(adapter, rxo, rxq_idx);
-                put_page(page_info->page);
-                memset(page_info, 0, sizeof(*page_info));
-                index_inc(&rxq_idx, rxq->len);
+         /* Skip out-of-buffer compl(lancer) or flush compl(BE) */
+        if (likely(rxq_idx != rxo->last_frag_index && num_rcvd != 0)) {
+
+                rxo->last_frag_index = rxq_idx;
+
+                for (i = 0; i < num_rcvd; i++) {
+                        page_info = get_rx_page_info(adapter, rxo, rxq_idx);
+                        put_page(page_info->page);
+                        memset(page_info, 0, sizeof(*page_info));
+                        index_inc(&rxq_idx, rxq->len);
+                }
         }
 }
 
@@ -999,9 +1022,6 @@ static void be_rx_compl_process(struct be_adapter *adapter,
         u8 vtm;
 
         num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
-        /* Is it a flush compl that has no data */
-        if (unlikely(num_rcvd == 0))
-                return;
 
         skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
         if (unlikely(!skb)) {
@@ -1035,7 +1055,8 @@ static void be_rx_compl_process(struct be_adapter *adapter,
                         return;
                 }
                 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
-                vid = swab16(vid);
+                if (!lancer_chip(adapter))
+                        vid = swab16(vid);
                 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
         } else {
                 netif_receive_skb(skb);
@@ -1057,10 +1078,6 @@ static void be_rx_compl_process_gro(struct be_adapter *adapter,
         u8 pkt_type;
 
         num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
-        /* Is it a flush compl that has no data */
-        if (unlikely(num_rcvd == 0))
-                return;
-
         pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
         vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
         rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
@@ -1113,7 +1130,8 @@ static void be_rx_compl_process_gro(struct be_adapter *adapter,
                 napi_gro_frags(&eq_obj->napi);
         } else {
                 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
-                vid = swab16(vid);
+                if (!lancer_chip(adapter))
+                        vid = swab16(vid);
 
                 if (!adapter->vlan_grp || adapter->vlans_added == 0)
                         return;
@@ -1330,7 +1348,7 @@ static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo)
         while ((rxcp = be_rx_compl_get(rxo)) != NULL) {
                 be_rx_compl_discard(adapter, rxo, rxcp);
                 be_rx_compl_reset(rxcp);
-                be_cq_notify(adapter, rx_cq->id, true, 1);
+                be_cq_notify(adapter, rx_cq->id, false, 1);
         }
 
         /* Then free posted rx buffer that were not used */
@@ -1381,7 +1399,8 @@ static void be_tx_compl_clean(struct be_adapter *adapter)
                 sent_skb = sent_skbs[txq->tail];
                 end_idx = txq->tail;
                 index_adv(&end_idx,
-                        wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
+                        wrb_cnt_for_skb(adapter, sent_skb, &dummy_wrb) - 1,
+                        txq->len);
                 be_tx_compl_process(adapter, end_idx);
         }
 }
@@ -1476,7 +1495,9 @@ static int be_tx_queues_create(struct be_adapter *adapter)
         /* Ask BE to create Tx Event queue */
         if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
                 goto tx_eq_free;
-        adapter->base_eq_id = adapter->tx_eq.q.id;
+
+        adapter->tx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
+
 
         /* Alloc TX eth compl queue */
         cq = &adapter->tx_obj.cq;
@@ -1554,6 +1575,9 @@ static int be_rx_queues_create(struct be_adapter *adapter)
         adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
         for_all_rx_queues(adapter, rxo, i) {
                 rxo->adapter = adapter;
+                /* Init last_frag_index so that the frag index in the first
+                 * completion will never match */
+                rxo->last_frag_index = 0xffff;
                 rxo->rx_eq.max_eqd = BE_MAX_EQD;
                 rxo->rx_eq.enable_aic = true;
 
@@ -1568,6 +1592,8 @@ static int be_rx_queues_create(struct be_adapter *adapter)
                 if (rc)
                         goto err;
 
+                rxo->rx_eq.msix_vec_idx = adapter->msix_vec_next_idx++;
+
                 /* CQ */
                 cq = &rxo->cq;
                 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
@@ -1578,7 +1604,6 @@ static int be_rx_queues_create(struct be_adapter *adapter)
                 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
                 if (rc)
                         goto err;
-
                 /* Rx Q */
                 q = &rxo->q;
                 rc = be_queue_alloc(adapter, q, RX_Q_LEN,
@@ -1611,29 +1636,45 @@ err:
         return -1;
 }
 
-/* There are 8 evt ids per func. Retruns the evt id's bit number */
-static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
+static bool event_peek(struct be_eq_obj *eq_obj)
 {
-        return eq_id - adapter->base_eq_id;
+        struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
+        if (!eqe->evt)
+                return false;
+        else
+                return true;
 }
 
 static irqreturn_t be_intx(int irq, void *dev)
 {
         struct be_adapter *adapter = dev;
         struct be_rx_obj *rxo;
-        int isr, i;
+        int isr, i, tx = 0 , rx = 0;
 
-        isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
-                (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
-        if (!isr)
-                return IRQ_NONE;
+        if (lancer_chip(adapter)) {
+                if (event_peek(&adapter->tx_eq))
+                        tx = event_handle(adapter, &adapter->tx_eq);
+                for_all_rx_queues(adapter, rxo, i) {
+                        if (event_peek(&rxo->rx_eq))
+                                rx |= event_handle(adapter, &rxo->rx_eq);
+                }
 
-        if ((1 << be_evt_bit_get(adapter, adapter->tx_eq.q.id) & isr))
-                event_handle(adapter, &adapter->tx_eq);
+                if (!(tx || rx))
+                        return IRQ_NONE;
 
-        for_all_rx_queues(adapter, rxo, i) {
-                if ((1 << be_evt_bit_get(adapter, rxo->rx_eq.q.id) & isr))
-                        event_handle(adapter, &rxo->rx_eq);
+        } else {
+                isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
+                        (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE);
+                if (!isr)
+                        return IRQ_NONE;
+
+                if ((1 << adapter->tx_eq.msix_vec_idx & isr))
+                        event_handle(adapter, &adapter->tx_eq);
+
+                for_all_rx_queues(adapter, rxo, i) {
+                        if ((1 << rxo->rx_eq.msix_vec_idx & isr))
+                                event_handle(adapter, &rxo->rx_eq);
+                }
         }
 
         return IRQ_HANDLED;
@@ -1658,10 +1699,9 @@ static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
         return IRQ_HANDLED;
 }
 
-static inline bool do_gro(struct be_adapter *adapter, struct be_rx_obj *rxo,
-                        struct be_eth_rx_compl *rxcp)
+static inline bool do_gro(struct be_rx_obj *rxo,
+                        struct be_eth_rx_compl *rxcp, u8 err)
 {
-        int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
         int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
 
         if (err)
@@ -1678,6 +1718,8 @@ static int be_poll_rx(struct napi_struct *napi, int budget)
         struct be_queue_info *rx_cq = &rxo->cq;
         struct be_eth_rx_compl *rxcp;
         u32 work_done;
+        u16 frag_index, num_rcvd;
+        u8 err;
 
         rxo->stats.rx_polls++;
         for (work_done = 0; work_done < budget; work_done++) {
@@ -1685,10 +1727,22 @@ static int be_poll_rx(struct napi_struct *napi, int budget)
                 if (!rxcp)
                         break;
 
-                if (do_gro(adapter, rxo, rxcp))
-                        be_rx_compl_process_gro(adapter, rxo, rxcp);
-                else
-                        be_rx_compl_process(adapter, rxo, rxcp);
+                err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
+                frag_index = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx,
+                                                                rxcp);
+                num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags,
+                                                                rxcp);
+
+                /* Skip out-of-buffer compl(lancer) or flush compl(BE) */
+                if (likely(frag_index != rxo->last_frag_index &&
+                                num_rcvd != 0)) {
+                        rxo->last_frag_index = frag_index;
+
+                        if (do_gro(rxo, rxcp, err))
+                                be_rx_compl_process_gro(adapter, rxo, rxcp);
+                        else
+                                be_rx_compl_process(adapter, rxo, rxcp);
+                }
 
                 be_rx_compl_reset(rxcp);
         }
@@ -1830,8 +1884,7 @@ static void be_worker(struct work_struct *work)
                         be_post_rx_frags(rxo);
                 }
         }
-
-        if (!adapter->ue_detected)
+        if (!adapter->ue_detected && !lancer_chip(adapter))
                 be_detect_dump_ue(adapter);
 
 reschedule:
@@ -1910,10 +1963,10 @@ static void be_sriov_disable(struct be_adapter *adapter)
 #endif
 }
 
-static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
+static inline int be_msix_vec_get(struct be_adapter *adapter,
+                                        struct be_eq_obj *eq_obj)
 {
-        return adapter->msix_entries[
-                        be_evt_bit_get(adapter, eq_id)].vector;
+        return adapter->msix_entries[eq_obj->msix_vec_idx].vector;
 }
 
 static int be_request_irq(struct be_adapter *adapter,
@@ -1924,14 +1977,14 @@ static int be_request_irq(struct be_adapter *adapter,
         int vec;
 
         sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
-        vec = be_msix_vec_get(adapter, eq_obj->q.id);
+        vec = be_msix_vec_get(adapter, eq_obj);
         return request_irq(vec, handler, 0, eq_obj->desc, context);
 }
 
 static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj,
                         void *context)
 {
-        int vec = be_msix_vec_get(adapter, eq_obj->q.id);
+        int vec = be_msix_vec_get(adapter, eq_obj);
         free_irq(vec, context);
 }
 
@@ -2036,14 +2089,15 @@ static int be_close(struct net_device *netdev)
         netif_carrier_off(netdev);
         adapter->link_up = false;
 
-        be_intr_set(adapter, false);
+        if (!lancer_chip(adapter))
+                be_intr_set(adapter, false);
 
         if (adapter->msix_enabled) {
-                vec = be_msix_vec_get(adapter, tx_eq->q.id);
+                vec = be_msix_vec_get(adapter, tx_eq);
                 synchronize_irq(vec);
 
                 for_all_rx_queues(adapter, rxo, i) {
-                        vec = be_msix_vec_get(adapter, rxo->rx_eq.q.id);
+                        vec = be_msix_vec_get(adapter, &rxo->rx_eq);
                         synchronize_irq(vec);
                 }
         } else {
@@ -2082,7 +2136,8 @@ static int be_open(struct net_device *netdev)
 
         be_irq_register(adapter);
 
-        be_intr_set(adapter, true);
+        if (!lancer_chip(adapter))
+                be_intr_set(adapter, true);
 
         /* The evt queues are created in unarmed state; arm them */
         for_all_rx_queues(adapter, rxo, i) {
@@ -2343,10 +2398,10 @@ static int be_flash_data(struct be_adapter *adapter,
         int num_bytes;
         const u8 *p = fw->data;
         struct be_cmd_write_flashrom *req = flash_cmd->va;
-        struct flash_comp *pflashcomp;
+        const struct flash_comp *pflashcomp;
         int num_comp;
 
-        struct flash_comp gen3_flash_types[9] = {
+        static const struct flash_comp gen3_flash_types[9] = {
                 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
                         FLASH_IMAGE_MAX_SIZE_g3},
                 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
@@ -2366,7 +2421,7 @@ static int be_flash_data(struct be_adapter *adapter,
                 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
                         FLASH_NCSI_IMAGE_MAX_SIZE_g3}
         };
-        struct flash_comp gen2_flash_types[8] = {
+        static const struct flash_comp gen2_flash_types[8] = {
                 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
                         FLASH_IMAGE_MAX_SIZE_g2},
                 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
@@ -2388,11 +2443,11 @@ static int be_flash_data(struct be_adapter *adapter,
         if (adapter->generation == BE_GEN3) {
                 pflashcomp = gen3_flash_types;
                 filehdr_size = sizeof(struct flash_file_hdr_g3);
-                num_comp = 9;
+                num_comp = ARRAY_SIZE(gen3_flash_types);
         } else {
                 pflashcomp = gen2_flash_types;
                 filehdr_size = sizeof(struct flash_file_hdr_g2);
-                num_comp = 8;
+                num_comp = ARRAY_SIZE(gen2_flash_types);
         }
         for (i = 0; i < num_comp; i++) {
                 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
@@ -2543,10 +2598,15 @@ static void be_netdev_init(struct net_device *netdev)
         int i;
 
         netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
-                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
+                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER |
+                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
                 NETIF_F_GRO | NETIF_F_TSO6;
 
-        netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
+        netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO |
+                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
+
+        if (lancer_chip(adapter))
+                netdev->vlan_features |= NETIF_F_TSO6;
 
         netdev->flags |= IFF_MULTICAST;
 
@@ -2587,6 +2647,15 @@ static int be_map_pci_bars(struct be_adapter *adapter)
         u8 __iomem *addr;
         int pcicfg_reg, db_reg;
 
+        if (lancer_chip(adapter)) {
+                addr = ioremap_nocache(pci_resource_start(adapter->pdev, 0),
+                        pci_resource_len(adapter->pdev, 0));
+                if (addr == NULL)
+                        return -ENOMEM;
+                adapter->db = addr;
+                return 0;
+        }
+
         if (be_physfn(adapter)) {
                 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
                                 pci_resource_len(adapter->pdev, 2));
@@ -2677,7 +2746,7 @@ static int be_ctrl_init(struct be_adapter *adapter)
         }
         memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
 
-        spin_lock_init(&adapter->mbox_lock);
+        mutex_init(&adapter->mbox_lock);
         spin_lock_init(&adapter->mcc_lock);
         spin_lock_init(&adapter->mcc_cq_lock);
 
@@ -2783,6 +2852,44 @@ static int be_get_config(struct be_adapter *adapter)
         return 0;
 }
 
+static int be_dev_family_check(struct be_adapter *adapter)
+{
+        struct pci_dev *pdev = adapter->pdev;
+        u32 sli_intf = 0, if_type;
+
+        switch (pdev->device) {
+        case BE_DEVICE_ID1:
+        case OC_DEVICE_ID1:
+                adapter->generation = BE_GEN2;
+                break;
+        case BE_DEVICE_ID2:
+        case OC_DEVICE_ID2:
+                adapter->generation = BE_GEN3;
+                break;
+        case OC_DEVICE_ID3:
+                pci_read_config_dword(pdev, SLI_INTF_REG_OFFSET, &sli_intf);
+                if_type = (sli_intf & SLI_INTF_IF_TYPE_MASK) >>
+                                                SLI_INTF_IF_TYPE_SHIFT;
+
+                if (((sli_intf & SLI_INTF_VALID_MASK) != SLI_INTF_VALID) ||
+                        if_type != 0x02) {
+                        dev_err(&pdev->dev, "SLI_INTF reg val is not valid\n");
+                        return -EINVAL;
+                }
+                if (num_vfs > 0) {
+                        dev_err(&pdev->dev, "VFs not supported\n");
+                        return -EINVAL;
+                }
+                adapter->sli_family = ((sli_intf & SLI_INTF_FAMILY_MASK) >>
+                                         SLI_INTF_FAMILY_SHIFT);
+                adapter->generation = BE_GEN3;
+                break;
+        default:
+                adapter->generation = 0;
+        }
+        return 0;
+}
+
 static int __devinit be_probe(struct pci_dev *pdev,
                         const struct pci_device_id *pdev_id)
 {
@@ -2805,22 +2912,13 @@ static int __devinit be_probe(struct pci_dev *pdev,
                 goto rel_reg;
         }
         adapter = netdev_priv(netdev);
-
-        switch (pdev->device) {
-        case BE_DEVICE_ID1:
-        case OC_DEVICE_ID1:
-                adapter->generation = BE_GEN2;
-                break;
-        case BE_DEVICE_ID2:
-        case OC_DEVICE_ID2:
-                adapter->generation = BE_GEN3;
-                break;
-        default:
-                adapter->generation = 0;
-        }
-
         adapter->pdev = pdev;
         pci_set_drvdata(pdev, adapter);
+
+        status = be_dev_family_check(adapter);
+        if (status)
+                goto free_netdev;
+
         adapter->netdev = netdev;
         SET_NETDEV_DEV(netdev, &pdev->dev);
 
@@ -2895,7 +2993,7 @@ ctrl_clean:
         be_ctrl_cleanup(adapter);
 free_netdev:
         be_sriov_disable(adapter);
-        free_netdev(adapter->netdev);
+        free_netdev(netdev);
         pci_set_drvdata(pdev, NULL);
 rel_reg:
         pci_release_regions(pdev);
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index ce1e5e9d06f6..0b9fc5173aef 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -8,6 +8,11 @@
  * Licensed under the GPL-2 or later.
  */
 
+#define DRV_VERSION     "1.1"
+#define DRV_DESC        "Blackfin on-chip Ethernet MAC driver"
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -41,12 +46,7 @@
 
 #include "bfin_mac.h"
 
-#define DRV_NAME        "bfin_mac"
-#define DRV_VERSION     "1.1"
-#define DRV_AUTHOR      "Bryan Wu, Luke Yang"
-#define DRV_DESC        "Blackfin on-chip Ethernet MAC driver"
-
-MODULE_AUTHOR(DRV_AUTHOR);
+MODULE_AUTHOR("Bryan Wu, Luke Yang");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION(DRV_DESC);
 MODULE_ALIAS("platform:bfin_mac");
@@ -189,8 +189,7 @@ static int desc_list_init(void)
                 /* allocate a new skb for next time receive */
                 new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
                 if (!new_skb) {
-                        printk(KERN_NOTICE DRV_NAME
-                               ": init: low on mem - packet dropped\n");
+                        pr_notice("init: low on mem - packet dropped\n");
                         goto init_error;
                 }
                 skb_reserve(new_skb, NET_IP_ALIGN);
@@ -240,7 +239,7 @@ static int desc_list_init(void)
 
 init_error:
         desc_list_free();
-        printk(KERN_ERR DRV_NAME ": kmalloc failed\n");
+        pr_err("kmalloc failed\n");
         return -ENOMEM;
 }
 
@@ -259,8 +258,7 @@ static int bfin_mdio_poll(void)
         while ((bfin_read_EMAC_STAADD()) & STABUSY) {
                 udelay(1);
                 if (timeout_cnt-- < 0) {
-                        printk(KERN_ERR DRV_NAME
-                        ": wait MDC/MDIO transaction to complete timeout\n");
+                        pr_err("wait MDC/MDIO transaction to complete timeout\n");
                         return -ETIMEDOUT;
                 }
         }
@@ -350,9 +348,9 @@ static void bfin_mac_adjust_link(struct net_device *dev)
                                         opmode &= ~RMII_10;
                                         break;
                                 default:
-                                        printk(KERN_WARNING
-                                                "%s: Ack!  Speed (%d) is not 10/100!\n",
-                                                DRV_NAME, phydev->speed);
+                                        netdev_warn(dev,
+                                                "Ack! Speed (%d) is not 10/100!\n",
+                                                phydev->speed);
                                         break;
                                 }
                                 bfin_write_EMAC_OPMODE(opmode);
@@ -417,14 +415,13 @@ static int mii_probe(struct net_device *dev, int phy_mode)
 
         /* now we are supposed to have a proper phydev, to attach to... */
         if (!phydev) {
-                printk(KERN_INFO "%s: Don't found any phy device at all\n",
-                        dev->name);
+                netdev_err(dev, "no phy device found\n");
                 return -ENODEV;
         }
 
         if (phy_mode != PHY_INTERFACE_MODE_RMII &&
                 phy_mode != PHY_INTERFACE_MODE_MII) {
-                printk(KERN_INFO "%s: Invalid phy interface mode\n", dev->name);
+                netdev_err(dev, "invalid phy interface mode\n");
                 return -EINVAL;
         }
 
@@ -432,7 +429,7 @@ static int mii_probe(struct net_device *dev, int phy_mode)
                         0, phy_mode);
 
         if (IS_ERR(phydev)) {
-                printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
+                netdev_err(dev, "could not attach PHY\n");
                 return PTR_ERR(phydev);
         }
 
@@ -453,11 +450,10 @@ static int mii_probe(struct net_device *dev, int phy_mode)
         lp->old_duplex = -1;
         lp->phydev = phydev;
 
-        printk(KERN_INFO "%s: attached PHY driver [%s] "
-               "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)"
-               "@sclk=%dMHz)\n",
-               DRV_NAME, phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
-               MDC_CLK, mdc_div, sclk/1000000);
+        pr_info("attached PHY driver [%s] "
+                "(mii_bus:phy_addr=%s, irq=%d, mdc_clk=%dHz(mdc_div=%d)@sclk=%dMHz)\n",
+                phydev->drv->name, dev_name(&phydev->dev), phydev->irq,
+                MDC_CLK, mdc_div, sclk/1000000);
 
         return 0;
 }
@@ -502,7 +498,7 @@ bfin_mac_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
 static void bfin_mac_ethtool_getdrvinfo(struct net_device *dev,
                                         struct ethtool_drvinfo *info)
 {
-        strcpy(info->driver, DRV_NAME);
+        strcpy(info->driver, KBUILD_MODNAME);
         strcpy(info->version, DRV_VERSION);
         strcpy(info->fw_version, "N/A");
         strcpy(info->bus_info, dev_name(&dev->dev));
@@ -562,7 +558,7 @@ static const struct ethtool_ops bfin_mac_ethtool_ops = {
 };
 
 /**************************************************************************/
-void setup_system_regs(struct net_device *dev)
+static void setup_system_regs(struct net_device *dev)
 {
         struct bfin_mac_local *lp = netdev_priv(dev);
         int i;
@@ -592,6 +588,10 @@ void setup_system_regs(struct net_device *dev)
 
         bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
 
+        /* Set vlan regs to let 1522 bytes long packets pass through */
+        bfin_write_EMAC_VLAN1(lp->vlan1_mask);
+        bfin_write_EMAC_VLAN2(lp->vlan2_mask);
+
         /* Initialize the TX DMA channel registers */
         bfin_write_DMA2_X_COUNT(0);
         bfin_write_DMA2_X_MODIFY(4);
@@ -827,8 +827,7 @@ static void bfin_tx_hwtstamp(struct net_device *netdev, struct sk_buff *skb)
                 while ((!(bfin_read_EMAC_PTP_ISTAT() & TXTL)) && (--timeout_cnt))
                         udelay(1);
                 if (timeout_cnt == 0)
-                        printk(KERN_ERR DRV_NAME
-                                        ": fails to timestamp the TX packet\n");
+                        netdev_err(netdev, "timestamp the TX packet failed\n");
                 else {
                         struct skb_shared_hwtstamps shhwtstamps;
                         u64 ns;
@@ -1083,8 +1082,7 @@ static void bfin_mac_rx(struct net_device *dev)
          * we which case we simply drop the packet
          */
         if (current_rx_ptr->status.status_word & RX_ERROR_MASK) {
-                printk(KERN_NOTICE DRV_NAME
-                       ": rx: receive error - packet dropped\n");
+                netdev_notice(dev, "rx: receive error - packet dropped\n");
                 dev->stats.rx_dropped++;
                 goto out;
         }
@@ -1094,8 +1092,7 @@ static void bfin_mac_rx(struct net_device *dev)
 
         new_skb = dev_alloc_skb(PKT_BUF_SZ + NET_IP_ALIGN);
         if (!new_skb) {
-                printk(KERN_NOTICE DRV_NAME
-                       ": rx: low on mem - packet dropped\n");
+                netdev_notice(dev, "rx: low on mem - packet dropped\n");
                 dev->stats.rx_dropped++;
                 goto out;
         }
@@ -1213,7 +1210,7 @@ static int bfin_mac_enable(struct phy_device *phydev)
         int ret;
         u32 opmode;
 
-        pr_debug("%s: %s\n", DRV_NAME, __func__);
+        pr_debug("%s\n", __func__);
 
         /* Set RX DMA */
         bfin_write_DMA1_NEXT_DESC_PTR(&(rx_list_head->desc_a));
@@ -1323,7 +1320,7 @@ static void bfin_mac_set_multicast_list(struct net_device *dev)
         u32 sysctl;
 
         if (dev->flags & IFF_PROMISC) {
-                printk(KERN_INFO "%s: set to promisc mode\n", dev->name);
+                netdev_info(dev, "set promisc mode\n");
                 sysctl = bfin_read_EMAC_OPMODE();
                 sysctl |= PR;
                 bfin_write_EMAC_OPMODE(sysctl);
@@ -1393,7 +1390,7 @@ static int bfin_mac_open(struct net_device *dev)
          * address using ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx
          */
         if (!is_valid_ether_addr(dev->dev_addr)) {
-                printk(KERN_WARNING DRV_NAME ": no valid ethernet hw addr\n");
+                netdev_warn(dev, "no valid ethernet hw addr\n");
                 return -EINVAL;
         }
 
@@ -1527,6 +1524,9 @@ static int __devinit bfin_mac_probe(struct platform_device *pdev)
                 goto out_err_mii_probe;
         }
 
+        lp->vlan1_mask = ETH_P_8021Q | mii_bus_data->vlan1_mask;
+        lp->vlan2_mask = ETH_P_8021Q | mii_bus_data->vlan2_mask;
+
         /* Fill in the fields of the device structure with ethernet values. */
         ether_setup(ndev);
 
@@ -1558,7 +1558,7 @@ static int __devinit bfin_mac_probe(struct platform_device *pdev)
         bfin_mac_hwtstamp_init(ndev);
 
         /* now, print out the card info, in a short format.. */
-        dev_info(&pdev->dev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
+        netdev_info(ndev, "%s, Version %s\n", DRV_DESC, DRV_VERSION);
 
         return 0;
 
@@ -1650,7 +1650,7 @@ static int __devinit bfin_mii_bus_probe(struct platform_device *pdev)
          * so set the GPIO pins to Ethernet mode
          */
         pin_req = mii_bus_pd->mac_peripherals;
-        rc = peripheral_request_list(pin_req, DRV_NAME);
+        rc = peripheral_request_list(pin_req, KBUILD_MODNAME);
         if (rc) {
                 dev_err(&pdev->dev, "Requesting peripherals failed!\n");
                 return rc;
@@ -1739,7 +1739,7 @@ static struct platform_driver bfin_mac_driver = {
         .resume = bfin_mac_resume,
         .suspend = bfin_mac_suspend,
         .driver = {
-                .name = DRV_NAME,
+                .name = KBUILD_MODNAME,
                 .owner  = THIS_MODULE,
         },
 };
diff --git a/drivers/net/bfin_mac.h b/drivers/net/bfin_mac.h
index aed68bed2365..f8559ac9a403 100644
--- a/drivers/net/bfin_mac.h
+++ b/drivers/net/bfin_mac.h
@@ -17,7 +17,14 @@
 #include <linux/etherdevice.h>
 #include <linux/bfin_mac.h>
 
+/*
+ * Disable hardware checksum for bug #5600 if writeback cache is
+ * enabled. Otherwize, corrupted RX packet will be sent up stack
+ * without error mark.
+ */
+#ifndef CONFIG_BFIN_EXTMEM_WRITEBACK
 #define BFIN_MAC_CSUM_OFFLOAD
+#endif
 
 #define TX_RECLAIM_JIFFIES (HZ / 5)
 
@@ -68,7 +75,6 @@ struct bfin_mac_local {
          */
         struct net_device_stats stats;
 
-        unsigned char Mac[6];   /* MAC address of the board */
         spinlock_t lock;
 
         int wol;                /* Wake On Lan */
@@ -76,6 +82,9 @@ struct bfin_mac_local {
         struct timer_list tx_reclaim_timer;
         struct net_device *ndev;
 
+        /* Data for EMAC_VLAN1 regs */
+        u16 vlan1_mask, vlan2_mask;
+
         /* MII and PHY stuffs */
         int old_link;          /* used by bf537_adjust_link */
         int old_speed;
diff --git a/drivers/net/bna/bfa_defs.h b/drivers/net/bna/bfa_defs.h
index 29c1b8de2c2d..2ea0dfe1cedc 100644
--- a/drivers/net/bna/bfa_defs.h
+++ b/drivers/net/bna/bfa_defs.h
@@ -112,16 +112,18 @@ struct bfa_ioc_pci_attr {
  * IOC states
  */
 enum bfa_ioc_state {
-        BFA_IOC_RESET           = 1,    /*!< IOC is in reset state */
-        BFA_IOC_SEMWAIT         = 2,    /*!< Waiting for IOC h/w semaphore */
-        BFA_IOC_HWINIT          = 3,    /*!< IOC h/w is being initialized */
-        BFA_IOC_GETATTR         = 4,    /*!< IOC is being configured */
-        BFA_IOC_OPERATIONAL     = 5,    /*!< IOC is operational */
-        BFA_IOC_INITFAIL        = 6,    /*!< IOC hardware failure */
-        BFA_IOC_HBFAIL          = 7,    /*!< IOC heart-beat failure */
-        BFA_IOC_DISABLING       = 8,    /*!< IOC is being disabled */
-        BFA_IOC_DISABLED        = 9,    /*!< IOC is disabled */
-        BFA_IOC_FWMISMATCH      = 10,   /*!< IOC f/w different from drivers */
+        BFA_IOC_UNINIT          = 1,    /*!< IOC is in uninit state */
+        BFA_IOC_RESET           = 2,    /*!< IOC is in reset state */
+        BFA_IOC_SEMWAIT         = 3,    /*!< Waiting for IOC h/w semaphore */
+        BFA_IOC_HWINIT          = 4,    /*!< IOC h/w is being initialized */
+        BFA_IOC_GETATTR         = 5,    /*!< IOC is being configured */
+        BFA_IOC_OPERATIONAL     = 6,    /*!< IOC is operational */
+        BFA_IOC_INITFAIL        = 7,    /*!< IOC hardware failure */
+        BFA_IOC_FAIL            = 8,    /*!< IOC heart-beat failure */
+        BFA_IOC_DISABLING       = 9,    /*!< IOC is being disabled */
+        BFA_IOC_DISABLED        = 10,   /*!< IOC is disabled */
+        BFA_IOC_FWMISMATCH      = 11,   /*!< IOC f/w different from drivers */
+        BFA_IOC_ENABLING        = 12,   /*!< IOC is being enabled */
 };
 
 /**
diff --git a/drivers/net/bna/bfa_defs_mfg_comm.h b/drivers/net/bna/bfa_defs_mfg_comm.h
index 987978fcb3fe..fdd677618361 100644
--- a/drivers/net/bna/bfa_defs_mfg_comm.h
+++ b/drivers/net/bna/bfa_defs_mfg_comm.h
@@ -95,28 +95,6 @@ enum {
         (type) == BFA_MFG_TYPE_CNA10P1 || \
         bfa_mfg_is_mezz(type)))
 
-/**
- * Check if the card having old wwn/mac handling
- */
-#define bfa_mfg_is_old_wwn_mac_model(type) (( \
-        (type) == BFA_MFG_TYPE_FC8P2 || \
-        (type) == BFA_MFG_TYPE_FC8P1 || \
-        (type) == BFA_MFG_TYPE_FC4P2 || \
-        (type) == BFA_MFG_TYPE_FC4P1 || \
-        (type) == BFA_MFG_TYPE_CNA10P2 || \
-        (type) == BFA_MFG_TYPE_CNA10P1 || \
-        (type) == BFA_MFG_TYPE_JAYHAWK || \
-        (type) == BFA_MFG_TYPE_WANCHESE))
-
-#define bfa_mfg_increment_wwn_mac(m, i)                         \
-do {                                                            \
-        u32 t = ((m)[0] << 16) | ((m)[1] << 8) | (m)[2];        \
-        t += (i);                                               \
-        (m)[0] = (t >> 16) & 0xFF;                              \
-        (m)[1] = (t >> 8) & 0xFF;                               \
-        (m)[2] = t & 0xFF;                                      \
-} while (0)
-
 #define bfa_mfg_adapter_prop_init_flash(card_type, prop)        \
 do {                                                            \
         switch ((card_type)) {                                  \
diff --git a/drivers/net/bna/bfa_ioc.c b/drivers/net/bna/bfa_ioc.c
index e94e5aa97515..34933cb9569f 100644
--- a/drivers/net/bna/bfa_ioc.c
+++ b/drivers/net/bna/bfa_ioc.c
@@ -26,25 +26,6 @@
  * IOC local definitions
  */
 
-#define bfa_ioc_timer_start(__ioc)                                      \
-        mod_timer(&(__ioc)->ioc_timer, jiffies +        \
-                        msecs_to_jiffies(BFA_IOC_TOV))
-#define bfa_ioc_timer_stop(__ioc)   del_timer(&(__ioc)->ioc_timer)
-
-#define bfa_ioc_recovery_timer_start(__ioc)                             \
-        mod_timer(&(__ioc)->ioc_timer, jiffies +        \
-                        msecs_to_jiffies(BFA_IOC_TOV_RECOVER))
-
-#define bfa_sem_timer_start(__ioc)                                      \
-        mod_timer(&(__ioc)->sem_timer, jiffies +        \
-                        msecs_to_jiffies(BFA_IOC_HWSEM_TOV))
-#define bfa_sem_timer_stop(__ioc)       del_timer(&(__ioc)->sem_timer)
-
-#define bfa_hb_timer_start(__ioc)                                       \
-        mod_timer(&(__ioc)->hb_timer, jiffies +         \
-                        msecs_to_jiffies(BFA_IOC_HB_TOV))
-#define bfa_hb_timer_stop(__ioc)        del_timer(&(__ioc)->hb_timer)
-
 /**
  * Asic specific macros : see bfa_hw_cb.c and bfa_hw_ct.c for details.
  */
@@ -55,11 +36,16 @@
                         ((__ioc)->ioc_hwif->ioc_firmware_unlock(__ioc))
 #define bfa_ioc_reg_init(__ioc) ((__ioc)->ioc_hwif->ioc_reg_init(__ioc))
 #define bfa_ioc_map_port(__ioc) ((__ioc)->ioc_hwif->ioc_map_port(__ioc))
-#define bfa_ioc_notify_hbfail(__ioc)                    \
-                        ((__ioc)->ioc_hwif->ioc_notify_hbfail(__ioc))
-
-#define bfa_ioc_is_optrom(__ioc)        \
-        (bfa_cb_image_get_size(BFA_IOC_FWIMG_TYPE(__ioc)) < BFA_IOC_FWIMG_MINSZ)
+#define bfa_ioc_notify_fail(__ioc)                      \
+                        ((__ioc)->ioc_hwif->ioc_notify_fail(__ioc))
+#define bfa_ioc_sync_join(__ioc)                        \
+                        ((__ioc)->ioc_hwif->ioc_sync_join(__ioc))
+#define bfa_ioc_sync_leave(__ioc)                       \
+                        ((__ioc)->ioc_hwif->ioc_sync_leave(__ioc))
+#define bfa_ioc_sync_ack(__ioc)                         \
+                        ((__ioc)->ioc_hwif->ioc_sync_ack(__ioc))
+#define bfa_ioc_sync_complete(__ioc)                    \
+                        ((__ioc)->ioc_hwif->ioc_sync_complete(__ioc))
 
 #define bfa_ioc_mbox_cmd_pending(__ioc)         \
                         (!list_empty(&((__ioc)->mbox_mod.cmd_q)) || \
@@ -85,6 +71,12 @@ static void bfa_ioc_recover(struct bfa_ioc *ioc);
 static void bfa_ioc_check_attr_wwns(struct bfa_ioc *ioc);
 static void bfa_ioc_disable_comp(struct bfa_ioc *ioc);
 static void bfa_ioc_lpu_stop(struct bfa_ioc *ioc);
+static void bfa_ioc_fail_notify(struct bfa_ioc *ioc);
+static void bfa_ioc_pf_enabled(struct bfa_ioc *ioc);
+static void bfa_ioc_pf_disabled(struct bfa_ioc *ioc);
+static void bfa_ioc_pf_initfailed(struct bfa_ioc *ioc);
+static void bfa_ioc_pf_failed(struct bfa_ioc *ioc);
+static void bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc);
 static void bfa_ioc_boot(struct bfa_ioc *ioc, u32 boot_type,
                          u32 boot_param);
 static u32 bfa_ioc_smem_pgnum(struct bfa_ioc *ioc, u32 fmaddr);
@@ -101,72 +93,173 @@ static void bfa_ioc_get_adapter_manufacturer(struct bfa_ioc *ioc,
                                                 char *manufacturer);
 static void bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model);
 static u64 bfa_ioc_get_pwwn(struct bfa_ioc *ioc);
-static mac_t bfa_ioc_get_mfg_mac(struct bfa_ioc *ioc);
 
 /**
- * IOC state machine events
+ * IOC state machine definitions/declarations
  */
 enum ioc_event {
-        IOC_E_ENABLE            = 1,    /*!< IOC enable request         */
-        IOC_E_DISABLE           = 2,    /*!< IOC disable request        */
-        IOC_E_TIMEOUT           = 3,    /*!< f/w response timeout       */
-        IOC_E_FWREADY           = 4,    /*!< f/w initialization done    */
-        IOC_E_FWRSP_GETATTR     = 5,    /*!< IOC get attribute response */
-        IOC_E_FWRSP_ENABLE      = 6,    /*!< enable f/w response        */
-        IOC_E_FWRSP_DISABLE     = 7,    /*!< disable f/w response       */
-        IOC_E_HBFAIL            = 8,    /*!< heartbeat failure          */
-        IOC_E_HWERROR           = 9,    /*!< hardware error interrupt   */
-        IOC_E_SEMLOCKED         = 10,   /*!< h/w semaphore is locked    */
-        IOC_E_DETACH            = 11,   /*!< driver detach cleanup      */
+        IOC_E_RESET             = 1,    /*!< IOC reset request          */
+        IOC_E_ENABLE            = 2,    /*!< IOC enable request         */
+        IOC_E_DISABLE           = 3,    /*!< IOC disable request        */
+        IOC_E_DETACH            = 4,    /*!< driver detach cleanup      */
+        IOC_E_ENABLED           = 5,    /*!< f/w enabled                */
+        IOC_E_FWRSP_GETATTR     = 6,    /*!< IOC get attribute response */
+        IOC_E_DISABLED          = 7,    /*!< f/w disabled               */
+        IOC_E_INITFAILED        = 8,    /*!< failure notice by iocpf sm */
+        IOC_E_PFAILED           = 9,    /*!< failure notice by iocpf sm */
+        IOC_E_HBFAIL            = 10,   /*!< heartbeat failure          */
+        IOC_E_HWERROR           = 11,   /*!< hardware error interrupt   */
+        IOC_E_TIMEOUT           = 12,   /*!< timeout                    */
 };
 
+bfa_fsm_state_decl(bfa_ioc, uninit, struct bfa_ioc, enum ioc_event);
 bfa_fsm_state_decl(bfa_ioc, reset, struct bfa_ioc, enum ioc_event);
-bfa_fsm_state_decl(bfa_ioc, fwcheck, struct bfa_ioc, enum ioc_event);
-bfa_fsm_state_decl(bfa_ioc, mismatch, struct bfa_ioc, enum ioc_event);
-bfa_fsm_state_decl(bfa_ioc, semwait, struct bfa_ioc, enum ioc_event);
-bfa_fsm_state_decl(bfa_ioc, hwinit, struct bfa_ioc, enum ioc_event);
 bfa_fsm_state_decl(bfa_ioc, enabling, struct bfa_ioc, enum ioc_event);
 bfa_fsm_state_decl(bfa_ioc, getattr, struct bfa_ioc, enum ioc_event);
 bfa_fsm_state_decl(bfa_ioc, op, struct bfa_ioc, enum ioc_event);
-bfa_fsm_state_decl(bfa_ioc, initfail, struct bfa_ioc, enum ioc_event);
-bfa_fsm_state_decl(bfa_ioc, hbfail, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, fail_retry, struct bfa_ioc, enum ioc_event);
+bfa_fsm_state_decl(bfa_ioc, fail, struct bfa_ioc, enum ioc_event);
 bfa_fsm_state_decl(bfa_ioc, disabling, struct bfa_ioc, enum ioc_event);
 bfa_fsm_state_decl(bfa_ioc, disabled, struct bfa_ioc, enum ioc_event);
 
 static struct bfa_sm_table ioc_sm_table[] = {
+        {BFA_SM(bfa_ioc_sm_uninit), BFA_IOC_UNINIT},
         {BFA_SM(bfa_ioc_sm_reset), BFA_IOC_RESET},
-        {BFA_SM(bfa_ioc_sm_fwcheck), BFA_IOC_FWMISMATCH},
-        {BFA_SM(bfa_ioc_sm_mismatch), BFA_IOC_FWMISMATCH},
-        {BFA_SM(bfa_ioc_sm_semwait), BFA_IOC_SEMWAIT},
-        {BFA_SM(bfa_ioc_sm_hwinit), BFA_IOC_HWINIT},
-        {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_HWINIT},
+        {BFA_SM(bfa_ioc_sm_enabling), BFA_IOC_ENABLING},
         {BFA_SM(bfa_ioc_sm_getattr), BFA_IOC_GETATTR},
         {BFA_SM(bfa_ioc_sm_op), BFA_IOC_OPERATIONAL},
-        {BFA_SM(bfa_ioc_sm_initfail), BFA_IOC_INITFAIL},
-        {BFA_SM(bfa_ioc_sm_hbfail), BFA_IOC_HBFAIL},
+        {BFA_SM(bfa_ioc_sm_fail_retry), BFA_IOC_INITFAIL},
+        {BFA_SM(bfa_ioc_sm_fail), BFA_IOC_FAIL},
         {BFA_SM(bfa_ioc_sm_disabling), BFA_IOC_DISABLING},
         {BFA_SM(bfa_ioc_sm_disabled), BFA_IOC_DISABLED},
 };
 
 /**
+ * IOCPF state machine definitions/declarations
+ */
+
+/*
+ * Forward declareations for iocpf state machine
+ */
+static void bfa_iocpf_enable(struct bfa_ioc *ioc);
+static void bfa_iocpf_disable(struct bfa_ioc *ioc);
+static void bfa_iocpf_fail(struct bfa_ioc *ioc);
+static void bfa_iocpf_initfail(struct bfa_ioc *ioc);
+static void bfa_iocpf_getattrfail(struct bfa_ioc *ioc);
+static void bfa_iocpf_stop(struct bfa_ioc *ioc);
+
+/**
+ * IOCPF state machine events
+ */
+enum iocpf_event {
+        IOCPF_E_ENABLE          = 1,    /*!< IOCPF enable request       */
+        IOCPF_E_DISABLE         = 2,    /*!< IOCPF disable request      */
+        IOCPF_E_STOP            = 3,    /*!< stop on driver detach      */
+        IOCPF_E_FWREADY         = 4,    /*!< f/w initialization done    */
+        IOCPF_E_FWRSP_ENABLE    = 5,    /*!< enable f/w response        */
+        IOCPF_E_FWRSP_DISABLE   = 6,    /*!< disable f/w response       */
+        IOCPF_E_FAIL            = 7,    /*!< failure notice by ioc sm   */
+        IOCPF_E_INITFAIL        = 8,    /*!< init fail notice by ioc sm */
+        IOCPF_E_GETATTRFAIL     = 9,    /*!< init fail notice by ioc sm */
+        IOCPF_E_SEMLOCKED       = 10,   /*!< h/w semaphore is locked    */
+        IOCPF_E_TIMEOUT         = 11,   /*!< f/w response timeout       */
+};
+
+/**
+ * IOCPF states
+ */
+enum bfa_iocpf_state {
+        BFA_IOCPF_RESET         = 1,    /*!< IOC is in reset state */
+        BFA_IOCPF_SEMWAIT       = 2,    /*!< Waiting for IOC h/w semaphore */
+        BFA_IOCPF_HWINIT        = 3,    /*!< IOC h/w is being initialized */
+        BFA_IOCPF_READY         = 4,    /*!< IOCPF is initialized */
+        BFA_IOCPF_INITFAIL      = 5,    /*!< IOCPF failed */
+        BFA_IOCPF_FAIL          = 6,    /*!< IOCPF failed */
+        BFA_IOCPF_DISABLING     = 7,    /*!< IOCPF is being disabled */
+        BFA_IOCPF_DISABLED      = 8,    /*!< IOCPF is disabled */
+        BFA_IOCPF_FWMISMATCH    = 9,    /*!< IOC f/w different from drivers */
+};
+
+bfa_fsm_state_decl(bfa_iocpf, reset, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, fwcheck, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, mismatch, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, semwait, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, hwinit, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, enabling, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, ready, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, initfail_sync, struct bfa_iocpf,
+                                                enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, initfail, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, fail_sync, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, fail, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, disabling, struct bfa_iocpf, enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, disabling_sync, struct bfa_iocpf,
+                                                enum iocpf_event);
+bfa_fsm_state_decl(bfa_iocpf, disabled, struct bfa_iocpf, enum iocpf_event);
+
+static struct bfa_sm_table iocpf_sm_table[] = {
+        {BFA_SM(bfa_iocpf_sm_reset), BFA_IOCPF_RESET},
+        {BFA_SM(bfa_iocpf_sm_fwcheck), BFA_IOCPF_FWMISMATCH},
+        {BFA_SM(bfa_iocpf_sm_mismatch), BFA_IOCPF_FWMISMATCH},
+        {BFA_SM(bfa_iocpf_sm_semwait), BFA_IOCPF_SEMWAIT},
+        {BFA_SM(bfa_iocpf_sm_hwinit), BFA_IOCPF_HWINIT},
+        {BFA_SM(bfa_iocpf_sm_enabling), BFA_IOCPF_HWINIT},
+        {BFA_SM(bfa_iocpf_sm_ready), BFA_IOCPF_READY},
+        {BFA_SM(bfa_iocpf_sm_initfail_sync), BFA_IOCPF_INITFAIL},
+        {BFA_SM(bfa_iocpf_sm_initfail), BFA_IOCPF_INITFAIL},
+        {BFA_SM(bfa_iocpf_sm_fail_sync), BFA_IOCPF_FAIL},
+        {BFA_SM(bfa_iocpf_sm_fail), BFA_IOCPF_FAIL},
+        {BFA_SM(bfa_iocpf_sm_disabling), BFA_IOCPF_DISABLING},
+        {BFA_SM(bfa_iocpf_sm_disabling_sync), BFA_IOCPF_DISABLING},
+        {BFA_SM(bfa_iocpf_sm_disabled), BFA_IOCPF_DISABLED},
+};
+
+/**
+ * IOC State Machine
+ */
+
+/**
+ * Beginning state. IOC uninit state.
+ */
+static void
+bfa_ioc_sm_uninit_entry(struct bfa_ioc *ioc)
+{
+}
+
+/**
+ * IOC is in uninit state.
+ */
+static void
+bfa_ioc_sm_uninit(struct bfa_ioc *ioc, enum ioc_event event)
+{
+        switch (event) {
+        case IOC_E_RESET:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+/**
  * Reset entry actions -- initialize state machine
  */
 static void
 bfa_ioc_sm_reset_entry(struct bfa_ioc *ioc)
 {
-        ioc->retry_count = 0;
-        ioc->auto_recover = bfa_nw_auto_recover;
+        bfa_fsm_set_state(&ioc->iocpf, bfa_iocpf_sm_reset);
 }
 
 /**
- * Beginning state. IOC is in reset state.
+ * IOC is in reset state.
  */
 static void
 bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
 {
         switch (event) {
         case IOC_E_ENABLE:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_fwcheck);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
                 break;
 
         case IOC_E_DISABLE:
@@ -174,6 +267,7 @@ bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
                 break;
 
         case IOC_E_DETACH:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
                 break;
 
         default:
@@ -181,42 +275,43 @@ bfa_ioc_sm_reset(struct bfa_ioc *ioc, enum ioc_event event)
         }
 }
 
-/**
- * Semaphore should be acquired for version check.
- */
 static void
-bfa_ioc_sm_fwcheck_entry(struct bfa_ioc *ioc)
+bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
 {
-        bfa_ioc_hw_sem_get(ioc);
+        bfa_iocpf_enable(ioc);
 }
 
 /**
- * Awaiting h/w semaphore to continue with version check.
+ * Host IOC function is being enabled, awaiting response from firmware.
+ * Semaphore is acquired.
  */
 static void
-bfa_ioc_sm_fwcheck(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
 {
         switch (event) {
-        case IOC_E_SEMLOCKED:
-                if (bfa_ioc_firmware_lock(ioc)) {
-                        ioc->retry_count = 0;
-                        bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
-                } else {
-                        bfa_nw_ioc_hw_sem_release(ioc);
-                        bfa_fsm_set_state(ioc, bfa_ioc_sm_mismatch);
-                }
+        case IOC_E_ENABLED:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
+                break;
+
+        case IOC_E_PFAILED:
+                /* !!! fall through !!! */
+        case IOC_E_HWERROR:
+                ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
+                if (event != IOC_E_PFAILED)
+                        bfa_iocpf_initfail(ioc);
                 break;
 
         case IOC_E_DISABLE:
-                bfa_ioc_disable_comp(ioc);
-                /* fall through */
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
+                break;
 
         case IOC_E_DETACH:
-                bfa_ioc_hw_sem_get_cancel(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
+                bfa_iocpf_stop(ioc);
                 break;
 
-        case IOC_E_FWREADY:
+        case IOC_E_ENABLE:
                 break;
 
         default:
@@ -225,41 +320,85 @@ bfa_ioc_sm_fwcheck(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 /**
- * Notify enable completion callback and generate mismatch AEN.
+ * Semaphore should be acquired for version check.
  */
 static void
-bfa_ioc_sm_mismatch_entry(struct bfa_ioc *ioc)
+bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
 {
-        /**
-         * Provide enable completion callback and AEN notification only once.
-         */
-        if (ioc->retry_count == 0)
-                ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
-        ioc->retry_count++;
-        bfa_ioc_timer_start(ioc);
+        mod_timer(&ioc->ioc_timer, jiffies +
+                msecs_to_jiffies(BFA_IOC_TOV));
+        bfa_ioc_send_getattr(ioc);
 }
 
 /**
- * Awaiting firmware version match.
+ * IOC configuration in progress. Timer is active.
  */
 static void
-bfa_ioc_sm_mismatch(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
 {
         switch (event) {
+        case IOC_E_FWRSP_GETATTR:
+                del_timer(&ioc->ioc_timer);
+                bfa_ioc_check_attr_wwns(ioc);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
+                break;
+
+        case IOC_E_PFAILED:
+        case IOC_E_HWERROR:
+                del_timer(&ioc->ioc_timer);
+                /* fall through */
         case IOC_E_TIMEOUT:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_fwcheck);
+                ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
+                if (event != IOC_E_PFAILED)
+                        bfa_iocpf_getattrfail(ioc);
                 break;
 
         case IOC_E_DISABLE:
-                bfa_ioc_disable_comp(ioc);
-                /* fall through */
+                del_timer(&ioc->ioc_timer);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
+                break;
 
-        case IOC_E_DETACH:
-                bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+        case IOC_E_ENABLE:
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+static void
+bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
+{
+        ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
+        bfa_ioc_hb_monitor(ioc);
+}
+
+static void
+bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
+{
+        switch (event) {
+        case IOC_E_ENABLE:
+                break;
+
+        case IOC_E_DISABLE:
+                bfa_ioc_hb_stop(ioc);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
                 break;
 
-        case IOC_E_FWREADY:
+        case IOC_E_PFAILED:
+        case IOC_E_HWERROR:
+                bfa_ioc_hb_stop(ioc);
+                /* !!! fall through !!! */
+        case IOC_E_HBFAIL:
+                bfa_ioc_fail_notify(ioc);
+                if (ioc->iocpf.auto_recover)
+                        bfa_fsm_set_state(ioc, bfa_ioc_sm_fail_retry);
+                else
+                        bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
+
+                if (event != IOC_E_PFAILED)
+                        bfa_iocpf_fail(ioc);
                 break;
 
         default:
@@ -267,30 +406,61 @@ bfa_ioc_sm_mismatch(struct bfa_ioc *ioc, enum ioc_event event)
         }
 }
 
+static void
+bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
+{
+        bfa_iocpf_disable(ioc);
+}
+
 /**
- * Request for semaphore.
+ * IOC is being desabled
  */
 static void
-bfa_ioc_sm_semwait_entry(struct bfa_ioc *ioc)
+bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
 {
-        bfa_ioc_hw_sem_get(ioc);
+        switch (event) {
+        case IOC_E_DISABLED:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+                break;
+
+        case IOC_E_HWERROR:
+                /*
+                 * No state change.  Will move to disabled state
+                 * after iocpf sm completes failure processing and
+                 * moves to disabled state.
+                 */
+                bfa_iocpf_fail(ioc);
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
+        }
 }
 
 /**
- * Awaiting semaphore for h/w initialzation.
+ * IOC desable completion entry.
  */
 static void
-bfa_ioc_sm_semwait(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
+{
+        bfa_ioc_disable_comp(ioc);
+}
+
+static void
+bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
 {
         switch (event) {
-        case IOC_E_SEMLOCKED:
-                ioc->retry_count = 0;
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
+        case IOC_E_ENABLE:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
                 break;
 
         case IOC_E_DISABLE:
-                bfa_ioc_hw_sem_get_cancel(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+                ioc->cbfn->disable_cbfn(ioc->bfa);
+                break;
+
+        case IOC_E_DETACH:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
+                bfa_iocpf_stop(ioc);
                 break;
 
         default:
@@ -299,46 +469,45 @@ bfa_ioc_sm_semwait(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 static void
-bfa_ioc_sm_hwinit_entry(struct bfa_ioc *ioc)
+bfa_ioc_sm_fail_retry_entry(struct bfa_ioc *ioc)
 {
-        bfa_ioc_timer_start(ioc);
-        bfa_ioc_reset(ioc, false);
 }
 
 /**
- * @brief
- * Hardware is being initialized. Interrupts are enabled.
- * Holding hardware semaphore lock.
+ * Hardware initialization retry.
  */
 static void
-bfa_ioc_sm_hwinit(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_ioc_sm_fail_retry(struct bfa_ioc *ioc, enum ioc_event event)
 {
         switch (event) {
-        case IOC_E_FWREADY:
-                bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_enabling);
+        case IOC_E_ENABLED:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
                 break;
 
+        case IOC_E_PFAILED:
         case IOC_E_HWERROR:
-                bfa_ioc_timer_stop(ioc);
-                /* fall through */
+                /**
+                 * Initialization retry failed.
+                 */
+                ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+                if (event != IOC_E_PFAILED)
+                        bfa_iocpf_initfail(ioc);
+                break;
 
-        case IOC_E_TIMEOUT:
-                ioc->retry_count++;
-                if (ioc->retry_count < BFA_IOC_HWINIT_MAX) {
-                        bfa_ioc_timer_start(ioc);
-                        bfa_ioc_reset(ioc, true);
-                        break;
-                }
+        case IOC_E_INITFAILED:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_fail);
+                break;
 
-                bfa_nw_ioc_hw_sem_release(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
+        case IOC_E_ENABLE:
                 break;
 
         case IOC_E_DISABLE:
-                bfa_nw_ioc_hw_sem_release(ioc);
-                bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
+                break;
+
+        case IOC_E_DETACH:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
+                bfa_iocpf_stop(ioc);
                 break;
 
         default:
@@ -347,51 +516,248 @@ bfa_ioc_sm_hwinit(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 static void
-bfa_ioc_sm_enabling_entry(struct bfa_ioc *ioc)
+bfa_ioc_sm_fail_entry(struct bfa_ioc *ioc)
 {
-        bfa_ioc_timer_start(ioc);
-        bfa_ioc_send_enable(ioc);
 }
 
 /**
- * Host IOC function is being enabled, awaiting response from firmware.
- * Semaphore is acquired.
+ * IOC failure.
  */
 static void
-bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_ioc_sm_fail(struct bfa_ioc *ioc, enum ioc_event event)
 {
         switch (event) {
-        case IOC_E_FWRSP_ENABLE:
-                bfa_ioc_timer_stop(ioc);
-                bfa_nw_ioc_hw_sem_release(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_getattr);
+        case IOC_E_ENABLE:
+                ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+                break;
+
+        case IOC_E_DISABLE:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
+                break;
+
+        case IOC_E_DETACH:
+                bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
+                bfa_iocpf_stop(ioc);
                 break;
 
         case IOC_E_HWERROR:
-                bfa_ioc_timer_stop(ioc);
-                /* fall through */
+                /* HB failure notification, ignore. */
+                break;
 
-        case IOC_E_TIMEOUT:
-                ioc->retry_count++;
-                if (ioc->retry_count < BFA_IOC_HWINIT_MAX) {
-                        writel(BFI_IOC_UNINIT,
-                                      ioc->ioc_regs.ioc_fwstate);
-                        bfa_fsm_set_state(ioc, bfa_ioc_sm_hwinit);
-                        break;
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+/**
+ * IOCPF State Machine
+ */
+
+/**
+ * Reset entry actions -- initialize state machine
+ */
+static void
+bfa_iocpf_sm_reset_entry(struct bfa_iocpf *iocpf)
+{
+        iocpf->retry_count = 0;
+        iocpf->auto_recover = bfa_nw_auto_recover;
+}
+
+/**
+ * Beginning state. IOC is in reset state.
+ */
+static void
+bfa_iocpf_sm_reset(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        switch (event) {
+        case IOCPF_E_ENABLE:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
+                break;
+
+        case IOCPF_E_STOP:
+                break;
+
+        default:
+                bfa_sm_fault(iocpf->ioc, event);
+        }
+}
+
+/**
+ * Semaphore should be acquired for version check.
+ */
+static void
+bfa_iocpf_sm_fwcheck_entry(struct bfa_iocpf *iocpf)
+{
+        bfa_ioc_hw_sem_get(iocpf->ioc);
+}
+
+/**
+ * Awaiting h/w semaphore to continue with version check.
+ */
+static void
+bfa_iocpf_sm_fwcheck(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        struct bfa_ioc *ioc = iocpf->ioc;
+
+        switch (event) {
+        case IOCPF_E_SEMLOCKED:
+                if (bfa_ioc_firmware_lock(ioc)) {
+                        if (bfa_ioc_sync_complete(ioc)) {
+                                iocpf->retry_count = 0;
+                                bfa_ioc_sync_join(ioc);
+                                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
+                        } else {
+                                bfa_ioc_firmware_unlock(ioc);
+                                bfa_nw_ioc_hw_sem_release(ioc);
+                                mod_timer(&ioc->sem_timer, jiffies +
+                                        msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
+                        }
+                } else {
+                        bfa_nw_ioc_hw_sem_release(ioc);
+                        bfa_fsm_set_state(iocpf, bfa_iocpf_sm_mismatch);
                 }
+                break;
 
-                bfa_nw_ioc_hw_sem_release(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
+        case IOCPF_E_DISABLE:
+                bfa_ioc_hw_sem_get_cancel(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
+                bfa_ioc_pf_disabled(ioc);
                 break;
 
-        case IOC_E_DISABLE:
-                bfa_ioc_timer_stop(ioc);
+        case IOCPF_E_STOP:
+                bfa_ioc_hw_sem_get_cancel(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+/**
+ * Notify enable completion callback
+ */
+static void
+bfa_iocpf_sm_mismatch_entry(struct bfa_iocpf *iocpf)
+{
+        /* Call only the first time sm enters fwmismatch state. */
+        if (iocpf->retry_count == 0)
+                bfa_ioc_pf_fwmismatch(iocpf->ioc);
+
+        iocpf->retry_count++;
+        mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
+                msecs_to_jiffies(BFA_IOC_TOV));
+}
+
+/**
+ * Awaiting firmware version match.
+ */
+static void
+bfa_iocpf_sm_mismatch(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        struct bfa_ioc *ioc = iocpf->ioc;
+
+        switch (event) {
+        case IOCPF_E_TIMEOUT:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fwcheck);
+                break;
+
+        case IOCPF_E_DISABLE:
+                del_timer(&ioc->iocpf_timer);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
+                bfa_ioc_pf_disabled(ioc);
+                break;
+
+        case IOCPF_E_STOP:
+                del_timer(&ioc->iocpf_timer);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+/**
+ * Request for semaphore.
+ */
+static void
+bfa_iocpf_sm_semwait_entry(struct bfa_iocpf *iocpf)
+{
+        bfa_ioc_hw_sem_get(iocpf->ioc);
+}
+
+/**
+ * Awaiting semaphore for h/w initialzation.
+ */
+static void
+bfa_iocpf_sm_semwait(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        struct bfa_ioc *ioc = iocpf->ioc;
+
+        switch (event) {
+        case IOCPF_E_SEMLOCKED:
+                if (bfa_ioc_sync_complete(ioc)) {
+                        bfa_ioc_sync_join(ioc);
+                        bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
+                } else {
+                        bfa_nw_ioc_hw_sem_release(ioc);
+                        mod_timer(&ioc->sem_timer, jiffies +
+                                msecs_to_jiffies(BFA_IOC_HWSEM_TOV));
+                }
+                break;
+
+        case IOCPF_E_DISABLE:
+                bfa_ioc_hw_sem_get_cancel(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+static void
+bfa_iocpf_sm_hwinit_entry(struct bfa_iocpf *iocpf)
+{
+        mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
+                msecs_to_jiffies(BFA_IOC_TOV));
+        bfa_ioc_reset(iocpf->ioc, 0);
+}
+
+/**
+ * Hardware is being initialized. Interrupts are enabled.
+ * Holding hardware semaphore lock.
+ */
+static void
+bfa_iocpf_sm_hwinit(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        struct bfa_ioc *ioc = iocpf->ioc;
+
+        switch (event) {
+        case IOCPF_E_FWREADY:
+                del_timer(&ioc->iocpf_timer);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_enabling);
+                break;
+
+        case IOCPF_E_INITFAIL:
+                del_timer(&ioc->iocpf_timer);
+                /*
+                 * !!! fall through !!!
+                 */
+
+        case IOCPF_E_TIMEOUT:
                 bfa_nw_ioc_hw_sem_release(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+                if (event == IOCPF_E_TIMEOUT)
+                        bfa_ioc_pf_failed(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
                 break;
 
-        case IOC_E_FWREADY:
-                bfa_ioc_send_enable(ioc);
+        case IOCPF_E_DISABLE:
+                del_timer(&ioc->iocpf_timer);
+                bfa_ioc_sync_leave(ioc);
+                bfa_nw_ioc_hw_sem_release(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
                 break;
 
         default:
@@ -400,37 +766,49 @@ bfa_ioc_sm_enabling(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 static void
-bfa_ioc_sm_getattr_entry(struct bfa_ioc *ioc)
+bfa_iocpf_sm_enabling_entry(struct bfa_iocpf *iocpf)
 {
-        bfa_ioc_timer_start(ioc);
-        bfa_ioc_send_getattr(ioc);
+        mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
+                msecs_to_jiffies(BFA_IOC_TOV));
+        bfa_ioc_send_enable(iocpf->ioc);
 }
 
 /**
- * @brief
- * IOC configuration in progress. Timer is active.
+ * Host IOC function is being enabled, awaiting response from firmware.
+ * Semaphore is acquired.
  */
 static void
-bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_iocpf_sm_enabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
 {
+        struct bfa_ioc *ioc = iocpf->ioc;
+
         switch (event) {
-        case IOC_E_FWRSP_GETATTR:
-                bfa_ioc_timer_stop(ioc);
-                bfa_ioc_check_attr_wwns(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_op);
+        case IOCPF_E_FWRSP_ENABLE:
+                del_timer(&ioc->iocpf_timer);
+                bfa_nw_ioc_hw_sem_release(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_ready);
                 break;
 
-        case IOC_E_HWERROR:
-                bfa_ioc_timer_stop(ioc);
-                /* fall through */
+        case IOCPF_E_INITFAIL:
+                del_timer(&ioc->iocpf_timer);
+                /*
+                 * !!! fall through !!!
+                 */
+        case IOCPF_E_TIMEOUT:
+                bfa_nw_ioc_hw_sem_release(ioc);
+                if (event == IOCPF_E_TIMEOUT)
+                        bfa_ioc_pf_failed(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
+                break;
 
-        case IOC_E_TIMEOUT:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_initfail);
+        case IOCPF_E_DISABLE:
+                del_timer(&ioc->iocpf_timer);
+                bfa_nw_ioc_hw_sem_release(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
                 break;
 
-        case IOC_E_DISABLE:
-                bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+        case IOCPF_E_FWREADY:
+                bfa_ioc_send_enable(ioc);
                 break;
 
         default:
@@ -438,36 +816,42 @@ bfa_ioc_sm_getattr(struct bfa_ioc *ioc, enum ioc_event event)
         }
 }
 
+static bool
+bfa_nw_ioc_is_operational(struct bfa_ioc *ioc)
+{
+        return bfa_fsm_cmp_state(ioc, bfa_ioc_sm_op);
+}
+
 static void
-bfa_ioc_sm_op_entry(struct bfa_ioc *ioc)
+bfa_iocpf_sm_ready_entry(struct bfa_iocpf *iocpf)
 {
-        ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_OK);
-        bfa_ioc_hb_monitor(ioc);
+        bfa_ioc_pf_enabled(iocpf->ioc);
 }
 
 static void
-bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_iocpf_sm_ready(struct bfa_iocpf *iocpf, enum iocpf_event event)
 {
+        struct bfa_ioc *ioc = iocpf->ioc;
+
         switch (event) {
-        case IOC_E_ENABLE:
+        case IOCPF_E_DISABLE:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling);
                 break;
 
-        case IOC_E_DISABLE:
-                bfa_ioc_hb_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabling);
+        case IOCPF_E_GETATTRFAIL:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
                 break;
 
-        case IOC_E_HWERROR:
-        case IOC_E_FWREADY:
-                /**
-                 * Hard error or IOC recovery by other function.
-                 * Treat it same as heartbeat failure.
-                 */
-                bfa_ioc_hb_stop(ioc);
-                /* !!! fall through !!! */
+        case IOCPF_E_FAIL:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync);
+                break;
 
-        case IOC_E_HBFAIL:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_hbfail);
+        case IOCPF_E_FWREADY:
+                bfa_ioc_pf_failed(ioc);
+                if (bfa_nw_ioc_is_operational(ioc))
+                        bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail_sync);
+                else
+                        bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail_sync);
                 break;
 
         default:
@@ -476,33 +860,40 @@ bfa_ioc_sm_op(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 static void
-bfa_ioc_sm_disabling_entry(struct bfa_ioc *ioc)
+bfa_iocpf_sm_disabling_entry(struct bfa_iocpf *iocpf)
 {
-        bfa_ioc_timer_start(ioc);
-        bfa_ioc_send_disable(ioc);
+        mod_timer(&(iocpf->ioc)->iocpf_timer, jiffies +
+                msecs_to_jiffies(BFA_IOC_TOV));
+        bfa_ioc_send_disable(iocpf->ioc);
 }
 
 /**
  * IOC is being disabled
  */
 static void
-bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_iocpf_sm_disabling(struct bfa_iocpf *iocpf, enum iocpf_event event)
 {
+        struct bfa_ioc *ioc = iocpf->ioc;
+
         switch (event) {
-        case IOC_E_FWRSP_DISABLE:
-                bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+        case IOCPF_E_FWRSP_DISABLE:
+        case IOCPF_E_FWREADY:
+                del_timer(&ioc->iocpf_timer);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
                 break;
 
-        case IOC_E_HWERROR:
-                bfa_ioc_timer_stop(ioc);
+        case IOCPF_E_FAIL:
+                del_timer(&ioc->iocpf_timer);
                 /*
                  * !!! fall through !!!
                  */
 
-        case IOC_E_TIMEOUT:
+        case IOCPF_E_TIMEOUT:
                 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
+                break;
+
+        case IOCPF_E_FWRSP_ENABLE:
                 break;
 
         default:
@@ -510,33 +901,58 @@ bfa_ioc_sm_disabling(struct bfa_ioc *ioc, enum ioc_event event)
         }
 }
 
-/**
- * IOC disable completion entry.
- */
 static void
-bfa_ioc_sm_disabled_entry(struct bfa_ioc *ioc)
+bfa_iocpf_sm_disabling_sync_entry(struct bfa_iocpf *iocpf)
 {
-        bfa_ioc_disable_comp(ioc);
+        bfa_ioc_hw_sem_get(iocpf->ioc);
 }
 
+/**
+ * IOC hb ack request is being removed.
+ */
 static void
-bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_iocpf_sm_disabling_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
 {
+        struct bfa_ioc *ioc = iocpf->ioc;
+
         switch (event) {
-        case IOC_E_ENABLE:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
+        case IOCPF_E_SEMLOCKED:
+                bfa_ioc_sync_leave(ioc);
+                bfa_nw_ioc_hw_sem_release(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
                 break;
 
-        case IOC_E_DISABLE:
-                ioc->cbfn->disable_cbfn(ioc->bfa);
+        case IOCPF_E_FAIL:
                 break;
 
-        case IOC_E_FWREADY:
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
+
+/**
+ * IOC disable completion entry.
+ */
+static void
+bfa_iocpf_sm_disabled_entry(struct bfa_iocpf *iocpf)
+{
+        bfa_ioc_pf_disabled(iocpf->ioc);
+}
+
+static void
+bfa_iocpf_sm_disabled(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        struct bfa_ioc *ioc = iocpf->ioc;
+
+        switch (event) {
+        case IOCPF_E_ENABLE:
+                iocpf->retry_count = 0;
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
                 break;
 
-        case IOC_E_DETACH:
+        case IOCPF_E_STOP:
                 bfa_ioc_firmware_unlock(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
                 break;
 
         default:
@@ -545,33 +961,50 @@ bfa_ioc_sm_disabled(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 static void
-bfa_ioc_sm_initfail_entry(struct bfa_ioc *ioc)
+bfa_iocpf_sm_initfail_sync_entry(struct bfa_iocpf *iocpf)
 {
-        ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
-        bfa_ioc_timer_start(ioc);
+        bfa_ioc_hw_sem_get(iocpf->ioc);
 }
 
 /**
- * @brief
  * Hardware initialization failed.
  */
 static void
-bfa_ioc_sm_initfail(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_iocpf_sm_initfail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
 {
+        struct bfa_ioc *ioc = iocpf->ioc;
+
         switch (event) {
-        case IOC_E_DISABLE:
-                bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+        case IOCPF_E_SEMLOCKED:
+                bfa_ioc_notify_fail(ioc);
+                bfa_ioc_sync_ack(ioc);
+                iocpf->retry_count++;
+                if (iocpf->retry_count >= BFA_IOC_HWINIT_MAX) {
+                        bfa_ioc_sync_leave(ioc);
+                        bfa_nw_ioc_hw_sem_release(ioc);
+                        bfa_fsm_set_state(iocpf, bfa_iocpf_sm_initfail);
+                } else {
+                        if (bfa_ioc_sync_complete(ioc))
+                                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
+                        else {
+                                bfa_nw_ioc_hw_sem_release(ioc);
+                                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
+                        }
+                }
                 break;
 
-        case IOC_E_DETACH:
-                bfa_ioc_timer_stop(ioc);
+        case IOCPF_E_DISABLE:
+                bfa_ioc_hw_sem_get_cancel(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
+                break;
+
+        case IOCPF_E_STOP:
+                bfa_ioc_hw_sem_get_cancel(ioc);
                 bfa_ioc_firmware_unlock(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
                 break;
 
-        case IOC_E_TIMEOUT:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
+        case IOCPF_E_FAIL:
                 break;
 
         default:
@@ -580,80 +1013,108 @@ bfa_ioc_sm_initfail(struct bfa_ioc *ioc, enum ioc_event event)
 }
 
 static void
-bfa_ioc_sm_hbfail_entry(struct bfa_ioc *ioc)
+bfa_iocpf_sm_initfail_entry(struct bfa_iocpf *iocpf)
 {
-        struct list_head                        *qe;
-        struct bfa_ioc_hbfail_notify *notify;
+        bfa_ioc_pf_initfailed(iocpf->ioc);
+}
 
-        /**
-         * Mark IOC as failed in hardware and stop firmware.
-         */
-        bfa_ioc_lpu_stop(ioc);
-        writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
+/**
+ * Hardware initialization failed.
+ */
+static void
+bfa_iocpf_sm_initfail(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        struct bfa_ioc *ioc = iocpf->ioc;
 
-        /**
-         * Notify other functions on HB failure.
-         */
-        bfa_ioc_notify_hbfail(ioc);
+        switch (event) {
+        case IOCPF_E_DISABLE:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
+                break;
 
-        /**
-         * Notify driver and common modules registered for notification.
-         */
-        ioc->cbfn->hbfail_cbfn(ioc->bfa);
-        list_for_each(qe, &ioc->hb_notify_q) {
-                notify = (struct bfa_ioc_hbfail_notify *) qe;
-                notify->cbfn(notify->cbarg);
+        case IOCPF_E_STOP:
+                bfa_ioc_firmware_unlock(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_reset);
+                break;
+
+        default:
+                bfa_sm_fault(ioc, event);
         }
+}
 
+static void
+bfa_iocpf_sm_fail_sync_entry(struct bfa_iocpf *iocpf)
+{
         /**
-         * Flush any queued up mailbox requests.
+         * Mark IOC as failed in hardware and stop firmware.
          */
-        bfa_ioc_mbox_hbfail(ioc);
+        bfa_ioc_lpu_stop(iocpf->ioc);
 
         /**
-         * Trigger auto-recovery after a delay.
+         * Flush any queued up mailbox requests.
          */
-        if (ioc->auto_recover)
-                mod_timer(&ioc->ioc_timer, jiffies +
-                        msecs_to_jiffies(BFA_IOC_TOV_RECOVER));
+        bfa_ioc_mbox_hbfail(iocpf->ioc);
+        bfa_ioc_hw_sem_get(iocpf->ioc);
 }
 
 /**
- * @brief
- * IOC heartbeat failure.
+ * IOC is in failed state.
  */
 static void
-bfa_ioc_sm_hbfail(struct bfa_ioc *ioc, enum ioc_event event)
+bfa_iocpf_sm_fail_sync(struct bfa_iocpf *iocpf, enum iocpf_event event)
 {
-        switch (event) {
+        struct bfa_ioc *ioc = iocpf->ioc;
 
-        case IOC_E_ENABLE:
-                ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+        switch (event) {
+        case IOCPF_E_SEMLOCKED:
+                iocpf->retry_count = 0;
+                bfa_ioc_sync_ack(ioc);
+                bfa_ioc_notify_fail(ioc);
+                if (!iocpf->auto_recover) {
+                        bfa_ioc_sync_leave(ioc);
+                        bfa_nw_ioc_hw_sem_release(ioc);
+                        bfa_fsm_set_state(iocpf, bfa_iocpf_sm_fail);
+                } else {
+                        if (bfa_ioc_sync_complete(ioc))
+                                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_hwinit);
+                        else {
+                                bfa_nw_ioc_hw_sem_release(ioc);
+                                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_semwait);
+                        }
+                }
                 break;
 
-        case IOC_E_DISABLE:
-                if (ioc->auto_recover)
-                        bfa_ioc_timer_stop(ioc);
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_disabled);
+        case IOCPF_E_DISABLE:
+                bfa_ioc_hw_sem_get_cancel(ioc);
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabling_sync);
                 break;
 
-        case IOC_E_TIMEOUT:
-                bfa_fsm_set_state(ioc, bfa_ioc_sm_semwait);
+        case IOCPF_E_FAIL:
                 break;
 
-        case IOC_E_FWREADY:
-                /**
-                 * Recovery is already initiated by other function.
-                 */
-                break;
+        default:
+                bfa_sm_fault(ioc, event);
+        }
+}
 
-        case IOC_E_HWERROR:
-                /*
-                 * HB failure notification, ignore.
-                 */
+static void
+bfa_iocpf_sm_fail_entry(struct bfa_iocpf *iocpf)
+{
+}
+
+/**
+ * @brief
+ * IOC is in failed state.
+ */
+static void
+bfa_iocpf_sm_fail(struct bfa_iocpf *iocpf, enum iocpf_event event)
+{
+        switch (event) {
+        case IOCPF_E_DISABLE:
+                bfa_fsm_set_state(iocpf, bfa_iocpf_sm_disabled);
                 break;
+
         default:
-                bfa_sm_fault(ioc, event);
+                bfa_sm_fault(iocpf->ioc, event);
         }
 }
 
@@ -678,14 +1139,6 @@ bfa_ioc_disable_comp(struct bfa_ioc *ioc)
         }
 }
 
-void
-bfa_nw_ioc_sem_timeout(void *ioc_arg)
-{
-        struct bfa_ioc *ioc = (struct bfa_ioc *) ioc_arg;
-
-        bfa_ioc_hw_sem_get(ioc);
-}
-
 bool
 bfa_nw_ioc_sem_get(void __iomem *sem_reg)
 {
@@ -725,7 +1178,7 @@ bfa_ioc_hw_sem_get(struct bfa_ioc *ioc)
          */
         r32 = readl(ioc->ioc_regs.ioc_sem_reg);
         if (r32 == 0) {
-                bfa_fsm_send_event(ioc, IOC_E_SEMLOCKED);
+                bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_SEMLOCKED);
                 return;
         }
 
@@ -865,12 +1318,6 @@ bfa_ioc_fwver_valid(struct bfa_ioc *ioc)
 {
         struct bfi_ioc_image_hdr fwhdr, *drv_fwhdr;
 
-        /**
-         * If bios/efi boot (flash based) -- return true
-         */
-        if (bfa_ioc_is_optrom(ioc))
-                return true;
-
         bfa_nw_ioc_fwver_get(ioc, &fwhdr);
         drv_fwhdr = (struct bfi_ioc_image_hdr *)
                 bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), 0);
@@ -934,20 +1381,15 @@ bfa_ioc_hwinit(struct bfa_ioc *ioc, bool force)
         /**
          * If IOC function is disabled and firmware version is same,
          * just re-enable IOC.
-         *
-         * If option rom, IOC must not be in operational state. With
-         * convergence, IOC will be in operational state when 2nd driver
-         * is loaded.
          */
-        if (ioc_fwstate == BFI_IOC_DISABLED ||
-            (!bfa_ioc_is_optrom(ioc) && ioc_fwstate == BFI_IOC_OP)) {
+        if (ioc_fwstate == BFI_IOC_DISABLED || ioc_fwstate == BFI_IOC_OP) {
                 /**
                  * When using MSI-X any pending firmware ready event should
                  * be flushed. Otherwise MSI-X interrupts are not delivered.
                  */
                 bfa_ioc_msgflush(ioc);
                 ioc->cbfn->reset_cbfn(ioc->bfa);
-                bfa_fsm_send_event(ioc, IOC_E_FWREADY);
+                bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FWREADY);
                 return;
         }
 
@@ -1033,7 +1475,6 @@ bfa_nw_ioc_hb_check(void *cbarg)
 
         hb_count = readl(ioc->ioc_regs.heartbeat);
         if (ioc->hb_count == hb_count) {
-                pr_crit("Firmware heartbeat failure at %d", hb_count);
                 bfa_ioc_recover(ioc);
                 return;
         } else {
@@ -1078,11 +1519,6 @@ bfa_ioc_download_fw(struct bfa_ioc *ioc, u32 boot_type,
          */
         bfa_ioc_lmem_init(ioc);
 
-        /**
-         * Flash based firmware boot
-         */
-        if (bfa_ioc_is_optrom(ioc))
-                boot_type = BFI_BOOT_TYPE_FLASH;
         fwimg = bfa_cb_image_get_chunk(BFA_IOC_FWIMG_TYPE(ioc), chunkno);
 
         pgnum = bfa_ioc_smem_pgnum(ioc, loff);
@@ -1209,6 +1645,55 @@ bfa_ioc_mbox_hbfail(struct bfa_ioc *ioc)
                 bfa_q_deq(&mod->cmd_q, &cmd);
 }
 
+static void
+bfa_ioc_fail_notify(struct bfa_ioc *ioc)
+{
+        struct list_head                *qe;
+        struct bfa_ioc_hbfail_notify    *notify;
+
+        /**
+         * Notify driver and common modules registered for notification.
+         */
+        ioc->cbfn->hbfail_cbfn(ioc->bfa);
+        list_for_each(qe, &ioc->hb_notify_q) {
+                notify = (struct bfa_ioc_hbfail_notify *) qe;
+                notify->cbfn(notify->cbarg);
+        }
+}
+
+static void
+bfa_ioc_pf_enabled(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(ioc, IOC_E_ENABLED);
+}
+
+static void
+bfa_ioc_pf_disabled(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(ioc, IOC_E_DISABLED);
+}
+
+static void
+bfa_ioc_pf_initfailed(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(ioc, IOC_E_INITFAILED);
+}
+
+static void
+bfa_ioc_pf_failed(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(ioc, IOC_E_PFAILED);
+}
+
+static void
+bfa_ioc_pf_fwmismatch(struct bfa_ioc *ioc)
+{
+        /**
+         * Provide enable completion callback and AEN notification.
+         */
+        ioc->cbfn->enable_cbfn(ioc->bfa, BFA_STATUS_IOC_FAILURE);
+}
+
 /**
  * IOC public
  */
@@ -1304,6 +1789,7 @@ static void
 bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
 {
         union bfi_ioc_i2h_msg_u *msg;
+        struct bfa_iocpf *iocpf = &ioc->iocpf;
 
         msg = (union bfi_ioc_i2h_msg_u *) m;
 
@@ -1314,15 +1800,15 @@ bfa_ioc_isr(struct bfa_ioc *ioc, struct bfi_mbmsg *m)
                 break;
 
         case BFI_IOC_I2H_READY_EVENT:
-                bfa_fsm_send_event(ioc, IOC_E_FWREADY);
+                bfa_fsm_send_event(iocpf, IOCPF_E_FWREADY);
                 break;
 
         case BFI_IOC_I2H_ENABLE_REPLY:
-                bfa_fsm_send_event(ioc, IOC_E_FWRSP_ENABLE);
+                bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_ENABLE);
                 break;
 
         case BFI_IOC_I2H_DISABLE_REPLY:
-                bfa_fsm_send_event(ioc, IOC_E_FWRSP_DISABLE);
+                bfa_fsm_send_event(iocpf, IOCPF_E_FWRSP_DISABLE);
                 break;
 
         case BFI_IOC_I2H_GETATTR_REPLY:
@@ -1348,11 +1834,13 @@ bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa, struct bfa_ioc_cbfn *cbfn)
         ioc->fcmode     = false;
         ioc->pllinit    = false;
         ioc->dbg_fwsave_once = true;
+        ioc->iocpf.ioc  = ioc;
 
         bfa_ioc_mbox_attach(ioc);
         INIT_LIST_HEAD(&ioc->hb_notify_q);
 
-        bfa_fsm_set_state(ioc, bfa_ioc_sm_reset);
+        bfa_fsm_set_state(ioc, bfa_ioc_sm_uninit);
+        bfa_fsm_send_event(ioc, IOC_E_RESET);
 }
 
 /**
@@ -1657,7 +2145,40 @@ bfa_ioc_get_adapter_model(struct bfa_ioc *ioc, char *model)
 static enum bfa_ioc_state
 bfa_ioc_get_state(struct bfa_ioc *ioc)
 {
-        return bfa_sm_to_state(ioc_sm_table, ioc->fsm);
+        enum bfa_iocpf_state iocpf_st;
+        enum bfa_ioc_state ioc_st = bfa_sm_to_state(ioc_sm_table, ioc->fsm);
+
+        if (ioc_st == BFA_IOC_ENABLING ||
+                ioc_st == BFA_IOC_FAIL || ioc_st == BFA_IOC_INITFAIL) {
+
+                iocpf_st = bfa_sm_to_state(iocpf_sm_table, ioc->iocpf.fsm);
+
+                switch (iocpf_st) {
+                case BFA_IOCPF_SEMWAIT:
+                        ioc_st = BFA_IOC_SEMWAIT;
+                        break;
+
+                case BFA_IOCPF_HWINIT:
+                        ioc_st = BFA_IOC_HWINIT;
+                        break;
+
+                case BFA_IOCPF_FWMISMATCH:
+                        ioc_st = BFA_IOC_FWMISMATCH;
+                        break;
+
+                case BFA_IOCPF_FAIL:
+                        ioc_st = BFA_IOC_FAIL;
+                        break;
+
+                case BFA_IOCPF_INITFAIL:
+                        ioc_st = BFA_IOC_INITFAIL;
+                        break;
+
+                default:
+                        break;
+                }
+        }
+        return ioc_st;
 }
 
 void
@@ -1689,28 +2210,7 @@ bfa_ioc_get_pwwn(struct bfa_ioc *ioc)
 mac_t
 bfa_nw_ioc_get_mac(struct bfa_ioc *ioc)
 {
-        /*
-         * Currently mfg mac is used as FCoE enode mac (not configured by PBC)
-         */
-        if (bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_FCoE)
-                return bfa_ioc_get_mfg_mac(ioc);
-        else
-                return ioc->attr->mac;
-}
-
-static mac_t
-bfa_ioc_get_mfg_mac(struct bfa_ioc *ioc)
-{
-        mac_t   m;
-
-        m = ioc->attr->mfg_mac;
-        if (bfa_mfg_is_old_wwn_mac_model(ioc->attr->card_type))
-                m.mac[MAC_ADDRLEN - 1] += bfa_ioc_pcifn(ioc);
-        else
-                bfa_mfg_increment_wwn_mac(&(m.mac[MAC_ADDRLEN-3]),
-                        bfa_ioc_pcifn(ioc));
-
-        return m;
+        return ioc->attr->mac;
 }
 
 /**
@@ -1719,8 +2219,13 @@ bfa_ioc_get_mfg_mac(struct bfa_ioc *ioc)
 static void
 bfa_ioc_recover(struct bfa_ioc *ioc)
 {
-        bfa_ioc_stats(ioc, ioc_hbfails);
-        bfa_fsm_send_event(ioc, IOC_E_HBFAIL);
+        u16 bdf;
+
+        bdf = (ioc->pcidev.pci_slot << 8 | ioc->pcidev.pci_func << 3 |
+                                        ioc->pcidev.device_id);
+
+        pr_crit("Firmware heartbeat failure at %d", bdf);
+        BUG_ON(1);
 }
 
 static void
@@ -1728,5 +2233,61 @@ bfa_ioc_check_attr_wwns(struct bfa_ioc *ioc)
 {
         if (bfa_ioc_get_type(ioc) == BFA_IOC_TYPE_LL)
                 return;
+}
+
+/**
+ * @dg hal_iocpf_pvt BFA IOC PF private functions
+ * @{
+ */
+
+static void
+bfa_iocpf_enable(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_ENABLE);
+}
+
+static void
+bfa_iocpf_disable(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_DISABLE);
+}
+
+static void
+bfa_iocpf_fail(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_FAIL);
+}
+
+static void
+bfa_iocpf_initfail(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_INITFAIL);
+}
+
+static void
+bfa_iocpf_getattrfail(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_GETATTRFAIL);
+}
+
+static void
+bfa_iocpf_stop(struct bfa_ioc *ioc)
+{
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_STOP);
+}
 
+void
+bfa_nw_iocpf_timeout(void *ioc_arg)
+{
+        struct bfa_ioc  *ioc = (struct bfa_ioc *) ioc_arg;
+
+        bfa_fsm_send_event(&ioc->iocpf, IOCPF_E_TIMEOUT);
+}
+
+void
+bfa_nw_iocpf_sem_timeout(void *ioc_arg)
+{
+        struct bfa_ioc  *ioc = (struct bfa_ioc *) ioc_arg;
+
+        bfa_ioc_hw_sem_get(ioc);
 }
diff --git a/drivers/net/bna/bfa_ioc.h b/drivers/net/bna/bfa_ioc.h
index a73d84ec808c..e4974bc24ef6 100644
--- a/drivers/net/bna/bfa_ioc.h
+++ b/drivers/net/bna/bfa_ioc.h
@@ -26,16 +26,7 @@
 #define BFA_IOC_TOV             3000    /* msecs */
 #define BFA_IOC_HWSEM_TOV       500     /* msecs */
 #define BFA_IOC_HB_TOV          500     /* msecs */
-#define BFA_IOC_HWINIT_MAX      2
-#define BFA_IOC_TOV_RECOVER     BFA_IOC_HB_TOV
-
-/**
- * Generic Scatter Gather Element used by driver
- */
-struct bfa_sge {
-        u32     sg_len;
-        void    *sg_addr;
-};
+#define BFA_IOC_HWINIT_MAX      5
 
 /**
  * PCI device information required by IOC
@@ -65,19 +56,6 @@ struct bfa_dma {
 #define BFI_SMEM_CT_SIZE        0x280000U       /* ! 2.5MB for catapult */
 
 /**
- * @brief BFA dma address assignment macro
- */
-#define bfa_dma_addr_set(dma_addr, pa)  \
-                __bfa_dma_addr_set(&dma_addr, (u64)pa)
-
-static inline void
-__bfa_dma_addr_set(union bfi_addr_u *dma_addr, u64 pa)
-{
-        dma_addr->a32.addr_lo = (u32) pa;
-        dma_addr->a32.addr_hi = (u32) (upper_32_bits(pa));
-}
-
-/**
  * @brief BFA dma address assignment macro. (big endian format)
  */
 #define bfa_dma_be_addr_set(dma_addr, pa)       \
@@ -105,8 +83,11 @@ struct bfa_ioc_regs {
         void __iomem *host_page_num_fn;
         void __iomem *heartbeat;
         void __iomem *ioc_fwstate;
+        void __iomem *alt_ioc_fwstate;
         void __iomem *ll_halt;
+        void __iomem *alt_ll_halt;
         void __iomem *err_set;
+        void __iomem *ioc_fail_sync;
         void __iomem *shirq_isr_next;
         void __iomem *shirq_msk_next;
         void __iomem *smem_page_start;
@@ -165,16 +146,22 @@ struct bfa_ioc_hbfail_notify {
         (__notify)->cbarg = (__cbarg);                          \
 } while (0)
 
+struct bfa_iocpf {
+        bfa_fsm_t               fsm;
+        struct bfa_ioc          *ioc;
+        u32                     retry_count;
+        bool                    auto_recover;
+};
+
 struct bfa_ioc {
         bfa_fsm_t               fsm;
         struct bfa              *bfa;
         struct bfa_pcidev       pcidev;
-        struct bfa_timer_mod    *timer_mod;
         struct timer_list       ioc_timer;
+        struct timer_list       iocpf_timer;
         struct timer_list       sem_timer;
         struct timer_list       hb_timer;
         u32                     hb_count;
-        u32                     retry_count;
         struct list_head        hb_notify_q;
         void                    *dbg_fwsave;
         int                     dbg_fwsave_len;
@@ -182,7 +169,6 @@ struct bfa_ioc {
         enum bfi_mclass         ioc_mc;
         struct bfa_ioc_regs     ioc_regs;
         struct bfa_ioc_drv_stats stats;
-        bool                    auto_recover;
         bool                    fcmode;
         bool                    ctdev;
         bool                    cna;
@@ -195,6 +181,7 @@ struct bfa_ioc {
         struct bfa_ioc_cbfn     *cbfn;
         struct bfa_ioc_mbox_mod mbox_mod;
         struct bfa_ioc_hwif     *ioc_hwif;
+        struct bfa_iocpf        iocpf;
 };
 
 struct bfa_ioc_hwif {
@@ -205,8 +192,12 @@ struct bfa_ioc_hwif {
         void            (*ioc_map_port) (struct bfa_ioc *ioc);
         void            (*ioc_isr_mode_set)     (struct bfa_ioc *ioc,
                                         bool msix);
-        void            (*ioc_notify_hbfail)    (struct bfa_ioc *ioc);
+        void            (*ioc_notify_fail)      (struct bfa_ioc *ioc);
         void            (*ioc_ownership_reset)  (struct bfa_ioc *ioc);
+        void            (*ioc_sync_join)        (struct bfa_ioc *ioc);
+        void            (*ioc_sync_leave)       (struct bfa_ioc *ioc);
+        void            (*ioc_sync_ack)         (struct bfa_ioc *ioc);
+        bool            (*ioc_sync_complete)    (struct bfa_ioc *ioc);
 };
 
 #define bfa_ioc_pcifn(__ioc)            ((__ioc)->pcidev.pci_func)
@@ -271,7 +262,6 @@ void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
 void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
 
 void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
-
 void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
 void bfa_nw_ioc_hbfail_register(struct bfa_ioc *ioc,
         struct bfa_ioc_hbfail_notify *notify);
@@ -289,7 +279,8 @@ mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
  */
 void bfa_nw_ioc_timeout(void *ioc);
 void bfa_nw_ioc_hb_check(void *ioc);
-void bfa_nw_ioc_sem_timeout(void *ioc);
+void bfa_nw_iocpf_timeout(void *ioc);
+void bfa_nw_iocpf_sem_timeout(void *ioc);
 
 /*
  * F/W Image Size & Chunk
diff --git a/drivers/net/bna/bfa_ioc_ct.c b/drivers/net/bna/bfa_ioc_ct.c
index 121cfd6d48b1..469997c4ffd1 100644
--- a/drivers/net/bna/bfa_ioc_ct.c
+++ b/drivers/net/bna/bfa_ioc_ct.c
@@ -22,6 +22,15 @@
 #include "bfi_ctreg.h"
 #include "bfa_defs.h"
 
+#define bfa_ioc_ct_sync_pos(__ioc)      \
+                ((u32) (1 << bfa_ioc_pcifn(__ioc)))
+#define BFA_IOC_SYNC_REQD_SH            16
+#define bfa_ioc_ct_get_sync_ackd(__val) (__val & 0x0000ffff)
+#define bfa_ioc_ct_clear_sync_ackd(__val) (__val & 0xffff0000)
+#define bfa_ioc_ct_get_sync_reqd(__val) (__val >> BFA_IOC_SYNC_REQD_SH)
+#define bfa_ioc_ct_sync_reqd_pos(__ioc) \
+                (bfa_ioc_ct_sync_pos(__ioc) << BFA_IOC_SYNC_REQD_SH)
+
 /*
  * forward declarations
  */
@@ -30,8 +39,12 @@ static void bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc);
 static void bfa_ioc_ct_reg_init(struct bfa_ioc *ioc);
 static void bfa_ioc_ct_map_port(struct bfa_ioc *ioc);
 static void bfa_ioc_ct_isr_mode_set(struct bfa_ioc *ioc, bool msix);
-static void bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc);
 static void bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_sync_join(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc);
+static void bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc);
+static bool bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc);
 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode);
 
 static struct bfa_ioc_hwif nw_hwif_ct;
@@ -48,8 +61,12 @@ bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc)
         nw_hwif_ct.ioc_reg_init = bfa_ioc_ct_reg_init;
         nw_hwif_ct.ioc_map_port = bfa_ioc_ct_map_port;
         nw_hwif_ct.ioc_isr_mode_set = bfa_ioc_ct_isr_mode_set;
-        nw_hwif_ct.ioc_notify_hbfail = bfa_ioc_ct_notify_hbfail;
+        nw_hwif_ct.ioc_notify_fail = bfa_ioc_ct_notify_fail;
         nw_hwif_ct.ioc_ownership_reset = bfa_ioc_ct_ownership_reset;
+        nw_hwif_ct.ioc_sync_join = bfa_ioc_ct_sync_join;
+        nw_hwif_ct.ioc_sync_leave = bfa_ioc_ct_sync_leave;
+        nw_hwif_ct.ioc_sync_ack = bfa_ioc_ct_sync_ack;
+        nw_hwif_ct.ioc_sync_complete = bfa_ioc_ct_sync_complete;
 
         ioc->ioc_hwif = &nw_hwif_ct;
 }
@@ -86,6 +103,7 @@ bfa_ioc_ct_firmware_lock(struct bfa_ioc *ioc)
         if (usecnt == 0) {
                 writel(1, ioc->ioc_regs.ioc_usage_reg);
                 bfa_nw_ioc_sem_release(ioc->ioc_regs.ioc_usage_sem_reg);
+                writel(0, ioc->ioc_regs.ioc_fail_sync);
                 return true;
         }
 
@@ -149,12 +167,14 @@ bfa_ioc_ct_firmware_unlock(struct bfa_ioc *ioc)
  * Notify other functions on HB failure.
  */
 static void
-bfa_ioc_ct_notify_hbfail(struct bfa_ioc *ioc)
+bfa_ioc_ct_notify_fail(struct bfa_ioc *ioc)
 {
         if (ioc->cna) {
                 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt);
+                writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt);
                 /* Wait for halt to take effect */
                 readl(ioc->ioc_regs.ll_halt);
+                readl(ioc->ioc_regs.alt_ll_halt);
         } else {
                 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set);
                 readl(ioc->ioc_regs.err_set);
@@ -206,15 +226,19 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
         if (ioc->port_id == 0) {
                 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
                 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
+                ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
                 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].hfn;
                 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p0[pcifn].lpu;
                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0;
+                ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1;
         } else {
                 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
                 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
+                ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG;
                 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].hfn;
                 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd_p1[pcifn].lpu;
                 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1;
+                ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0;
         }
 
         /*
@@ -232,6 +256,7 @@ bfa_ioc_ct_reg_init(struct bfa_ioc *ioc)
         ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG);
         ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
         ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT);
+        ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC);
 
         /**
          * sram memory access
@@ -317,6 +342,77 @@ bfa_ioc_ct_ownership_reset(struct bfa_ioc *ioc)
         bfa_nw_ioc_hw_sem_release(ioc);
 }
 
+/**
+ * Synchronized IOC failure processing routines
+ */
+static void
+bfa_ioc_ct_sync_join(struct bfa_ioc *ioc)
+{
+        u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
+        u32 sync_pos = bfa_ioc_ct_sync_reqd_pos(ioc);
+
+        writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync);
+}
+
+static void
+bfa_ioc_ct_sync_leave(struct bfa_ioc *ioc)
+{
+        u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
+        u32 sync_msk = bfa_ioc_ct_sync_reqd_pos(ioc) |
+                                        bfa_ioc_ct_sync_pos(ioc);
+
+        writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync);
+}
+
+static void
+bfa_ioc_ct_sync_ack(struct bfa_ioc *ioc)
+{
+        u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
+
+        writel((r32 | bfa_ioc_ct_sync_pos(ioc)), ioc->ioc_regs.ioc_fail_sync);
+}
+
+static bool
+bfa_ioc_ct_sync_complete(struct bfa_ioc *ioc)
+{
+        u32 r32 = readl(ioc->ioc_regs.ioc_fail_sync);
+        u32 sync_reqd = bfa_ioc_ct_get_sync_reqd(r32);
+        u32 sync_ackd = bfa_ioc_ct_get_sync_ackd(r32);
+        u32 tmp_ackd;
+
+        if (sync_ackd == 0)
+                return true;
+
+        /**
+         * The check below is to see whether any other PCI fn
+         * has reinitialized the ASIC (reset sync_ackd bits)
+         * and failed again while this IOC was waiting for hw
+         * semaphore (in bfa_iocpf_sm_semwait()).
+         */
+        tmp_ackd = sync_ackd;
+        if ((sync_reqd &  bfa_ioc_ct_sync_pos(ioc)) &&
+                        !(sync_ackd & bfa_ioc_ct_sync_pos(ioc)))
+                sync_ackd |= bfa_ioc_ct_sync_pos(ioc);
+
+        if (sync_reqd == sync_ackd) {
+                writel(bfa_ioc_ct_clear_sync_ackd(r32),
+                                ioc->ioc_regs.ioc_fail_sync);
+                writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate);
+                writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate);
+                return true;
+        }
+
+        /**
+         * If another PCI fn reinitialized and failed again while
+         * this IOC was waiting for hw sem, the sync_ackd bit for
+         * this IOC need to be set again to allow reinitialization.
+         */
+        if (tmp_ackd != sync_ackd)
+                writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync);
+
+        return false;
+}
+
 static enum bfa_status
 bfa_ioc_ct_pll_init(void __iomem *rb, bool fcmode)
 {
diff --git a/drivers/net/bna/bfi_ctreg.h b/drivers/net/bna/bfi_ctreg.h
index 404ea351d4a1..5130d7918660 100644
--- a/drivers/net/bna/bfi_ctreg.h
+++ b/drivers/net/bna/bfi_ctreg.h
@@ -535,6 +535,7 @@ enum {
 #define BFA_IOC1_HBEAT_REG              HOST_SEM2_INFO_REG
 #define BFA_IOC1_STATE_REG              HOST_SEM3_INFO_REG
 #define BFA_FW_USE_COUNT                 HOST_SEM4_INFO_REG
+#define BFA_IOC_FAIL_SYNC               HOST_SEM5_INFO_REG
 
 #define CPE_DEPTH_Q(__n) \
         (CPE_DEPTH_Q0 + (__n) * (CPE_DEPTH_Q1 - CPE_DEPTH_Q0))
@@ -552,22 +553,30 @@ enum {
         (RME_PI_PTR_Q0 + (__n) * (RME_PI_PTR_Q1 - RME_PI_PTR_Q0))
 #define RME_CI_PTR_Q(__n) \
         (RME_CI_PTR_Q0 + (__n) * (RME_CI_PTR_Q1 - RME_CI_PTR_Q0))
-#define HQM_QSET_RXQ_DRBL_P0(__n) (HQM_QSET0_RXQ_DRBL_P0 + (__n) \
-        * (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
-#define HQM_QSET_TXQ_DRBL_P0(__n) (HQM_QSET0_TXQ_DRBL_P0 + (__n) \
-        * (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
-#define HQM_QSET_IB_DRBL_1_P0(__n) (HQM_QSET0_IB_DRBL_1_P0 + (__n) \
-        * (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
-#define HQM_QSET_IB_DRBL_2_P0(__n) (HQM_QSET0_IB_DRBL_2_P0 + (__n) \
-        * (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
-#define HQM_QSET_RXQ_DRBL_P1(__n) (HQM_QSET0_RXQ_DRBL_P1 + (__n) \
-        * (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
-#define HQM_QSET_TXQ_DRBL_P1(__n) (HQM_QSET0_TXQ_DRBL_P1 + (__n) \
-        * (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
-#define HQM_QSET_IB_DRBL_1_P1(__n) (HQM_QSET0_IB_DRBL_1_P1 + (__n) \
-        * (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
-#define HQM_QSET_IB_DRBL_2_P1(__n) (HQM_QSET0_IB_DRBL_2_P1 + (__n) \
-        * (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
+#define HQM_QSET_RXQ_DRBL_P0(__n) \
+        (HQM_QSET0_RXQ_DRBL_P0 + (__n) * \
+                (HQM_QSET1_RXQ_DRBL_P0 - HQM_QSET0_RXQ_DRBL_P0))
+#define HQM_QSET_TXQ_DRBL_P0(__n) \
+        (HQM_QSET0_TXQ_DRBL_P0 + (__n) * \
+                (HQM_QSET1_TXQ_DRBL_P0 - HQM_QSET0_TXQ_DRBL_P0))
+#define HQM_QSET_IB_DRBL_1_P0(__n) \
+        (HQM_QSET0_IB_DRBL_1_P0 + (__n) * \
+                (HQM_QSET1_IB_DRBL_1_P0 - HQM_QSET0_IB_DRBL_1_P0))
+#define HQM_QSET_IB_DRBL_2_P0(__n) \
+        (HQM_QSET0_IB_DRBL_2_P0 + (__n) * \
+                (HQM_QSET1_IB_DRBL_2_P0 - HQM_QSET0_IB_DRBL_2_P0))
+#define HQM_QSET_RXQ_DRBL_P1(__n) \
+        (HQM_QSET0_RXQ_DRBL_P1 + (__n) * \
+                (HQM_QSET1_RXQ_DRBL_P1 - HQM_QSET0_RXQ_DRBL_P1))
+#define HQM_QSET_TXQ_DRBL_P1(__n) \
+        (HQM_QSET0_TXQ_DRBL_P1 + (__n) * \
+                (HQM_QSET1_TXQ_DRBL_P1 - HQM_QSET0_TXQ_DRBL_P1))
+#define HQM_QSET_IB_DRBL_1_P1(__n) \
+        (HQM_QSET0_IB_DRBL_1_P1 + (__n) * \
+                (HQM_QSET1_IB_DRBL_1_P1 - HQM_QSET0_IB_DRBL_1_P1))
+#define HQM_QSET_IB_DRBL_2_P1(__n) \
+        (HQM_QSET0_IB_DRBL_2_P1 + (__n) * \
+                (HQM_QSET1_IB_DRBL_2_P1 - HQM_QSET0_IB_DRBL_2_P1))
 
 #define CPE_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
 #define RME_Q_NUM(__fn, __q) (((__fn) << 2) + (__q))
diff --git a/drivers/net/bna/bna.h b/drivers/net/bna/bna.h
index df6676bbc84e..a287f89b0289 100644
--- a/drivers/net/bna/bna.h
+++ b/drivers/net/bna/bna.h
@@ -32,8 +32,6 @@ extern const u32 bna_napi_dim_vector[][BNA_BIAS_T_MAX];
 /* Log string size */
 #define BNA_MESSAGE_SIZE                256
 
-#define bna_device_timer(_dev)          bfa_timer_beat(&((_dev)->timer_mod))
-
 /* MBOX API for PORT, TX, RX */
 #define bna_mbox_qe_fill(_qe, _cmd, _cmd_len, _cbfn, _cbarg)            \
 do {                                                                    \
@@ -390,8 +388,8 @@ void bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe);
 
 /* API for RX */
 int bna_port_mtu_get(struct bna_port *port);
-void bna_llport_admin_up(struct bna_llport *llport);
-void bna_llport_admin_down(struct bna_llport *llport);
+void bna_llport_rx_started(struct bna_llport *llport);
+void bna_llport_rx_stopped(struct bna_llport *llport);
 
 /* API for BNAD */
 void bna_port_enable(struct bna_port *port);
diff --git a/drivers/net/bna/bna_ctrl.c b/drivers/net/bna/bna_ctrl.c
index 07b26598546e..e1527472b961 100644
--- a/drivers/net/bna/bna_ctrl.c
+++ b/drivers/net/bna/bna_ctrl.c
@@ -59,14 +59,70 @@ bna_port_cb_link_down(struct bna_port *port, int status)
         port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
 }
 
+static inline int
+llport_can_be_up(struct bna_llport *llport)
+{
+        int ready = 0;
+        if (llport->type == BNA_PORT_T_REGULAR)
+                ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
+                         (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
+                         (llport->flags & BNA_LLPORT_F_PORT_ENABLED));
+        else
+                ready = ((llport->flags & BNA_LLPORT_F_ADMIN_UP) &&
+                         (llport->flags & BNA_LLPORT_F_RX_STARTED) &&
+                         !(llport->flags & BNA_LLPORT_F_PORT_ENABLED));
+        return ready;
+}
+
+#define llport_is_up llport_can_be_up
+
+enum bna_llport_event {
+        LLPORT_E_START                  = 1,
+        LLPORT_E_STOP                   = 2,
+        LLPORT_E_FAIL                   = 3,
+        LLPORT_E_UP                     = 4,
+        LLPORT_E_DOWN                   = 5,
+        LLPORT_E_FWRESP_UP_OK           = 6,
+        LLPORT_E_FWRESP_UP_FAIL         = 7,
+        LLPORT_E_FWRESP_DOWN            = 8
+};
+
+static void
+bna_llport_cb_port_enabled(struct bna_llport *llport)
+{
+        llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
+
+        if (llport_can_be_up(llport))
+                bfa_fsm_send_event(llport, LLPORT_E_UP);
+}
+
+static void
+bna_llport_cb_port_disabled(struct bna_llport *llport)
+{
+        int llport_up = llport_is_up(llport);
+
+        llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
+
+        if (llport_up)
+                bfa_fsm_send_event(llport, LLPORT_E_DOWN);
+}
+
 /**
  * MBOX
  */
 static int
 bna_is_aen(u8 msg_id)
 {
-        return msg_id == BFI_LL_I2H_LINK_DOWN_AEN ||
-               msg_id == BFI_LL_I2H_LINK_UP_AEN;
+        switch (msg_id) {
+        case BFI_LL_I2H_LINK_DOWN_AEN:
+        case BFI_LL_I2H_LINK_UP_AEN:
+        case BFI_LL_I2H_PORT_ENABLE_AEN:
+        case BFI_LL_I2H_PORT_DISABLE_AEN:
+                return 1;
+
+        default:
+                return 0;
+        }
 }
 
 static void
@@ -81,6 +137,12 @@ bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
         case BFI_LL_I2H_LINK_DOWN_AEN:
                 bna_port_cb_link_down(&bna->port, aen->reason);
                 break;
+        case BFI_LL_I2H_PORT_ENABLE_AEN:
+                bna_llport_cb_port_enabled(&bna->port.llport);
+                break;
+        case BFI_LL_I2H_PORT_DISABLE_AEN:
+                bna_llport_cb_port_disabled(&bna->port.llport);
+                break;
         default:
                 break;
         }
@@ -251,16 +313,6 @@ static void bna_llport_start(struct bna_llport *llport);
 static void bna_llport_stop(struct bna_llport *llport);
 static void bna_llport_fail(struct bna_llport *llport);
 
-enum bna_llport_event {
-        LLPORT_E_START                  = 1,
-        LLPORT_E_STOP                   = 2,
-        LLPORT_E_FAIL                   = 3,
-        LLPORT_E_UP                     = 4,
-        LLPORT_E_DOWN                   = 5,
-        LLPORT_E_FWRESP_UP              = 6,
-        LLPORT_E_FWRESP_DOWN            = 7
-};
-
 enum bna_llport_state {
         BNA_LLPORT_STOPPED              = 1,
         BNA_LLPORT_DOWN                 = 2,
@@ -320,7 +372,7 @@ bna_llport_sm_stopped(struct bna_llport *llport,
                 /* No-op */
                 break;
 
-        case LLPORT_E_FWRESP_UP:
+        case LLPORT_E_FWRESP_UP_OK:
         case LLPORT_E_FWRESP_DOWN:
                 /**
                  * These events are received due to flushing of mbox when
@@ -366,6 +418,7 @@ bna_llport_sm_down(struct bna_llport *llport,
 static void
 bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
 {
+        BUG_ON(!llport_can_be_up(llport));
         /**
          * NOTE: Do not call bna_fw_llport_up() here. That will over step
          * mbox due to down_resp_wait -> up_resp_wait transition on event
@@ -390,10 +443,14 @@ bna_llport_sm_up_resp_wait(struct bna_llport *llport,
                 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
                 break;
 
-        case LLPORT_E_FWRESP_UP:
+        case LLPORT_E_FWRESP_UP_OK:
                 bfa_fsm_set_state(llport, bna_llport_sm_up);
                 break;
 
+        case LLPORT_E_FWRESP_UP_FAIL:
+                bfa_fsm_set_state(llport, bna_llport_sm_down);
+                break;
+
         case LLPORT_E_FWRESP_DOWN:
                 /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
                 bna_fw_llport_up(llport);
@@ -431,11 +488,12 @@ bna_llport_sm_down_resp_wait(struct bna_llport *llport,
                 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
                 break;
 
-        case LLPORT_E_FWRESP_UP:
+        case LLPORT_E_FWRESP_UP_OK:
                 /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
                 bna_fw_llport_down(llport);
                 break;
 
+        case LLPORT_E_FWRESP_UP_FAIL:
         case LLPORT_E_FWRESP_DOWN:
                 bfa_fsm_set_state(llport, bna_llport_sm_down);
                 break;
@@ -496,11 +554,12 @@ bna_llport_sm_last_resp_wait(struct bna_llport *llport,
                 /* No-op */
                 break;
 
-        case LLPORT_E_FWRESP_UP:
+        case LLPORT_E_FWRESP_UP_OK:
                 /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
                 bna_fw_llport_down(llport);
                 break;
 
+        case LLPORT_E_FWRESP_UP_FAIL:
         case LLPORT_E_FWRESP_DOWN:
                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
                 break;
@@ -541,7 +600,14 @@ bna_fw_cb_llport_up(void *arg, int status)
         struct bna_llport *llport = (struct bna_llport *)arg;
 
         bfa_q_qe_init(&llport->mbox_qe.qe);
-        bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP);
+        if (status == BFI_LL_CMD_FAIL) {
+                if (llport->type == BNA_PORT_T_REGULAR)
+                        llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
+                else
+                        llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
+                bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_FAIL);
+        } else
+                bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP_OK);
 }
 
 static void
@@ -588,13 +654,14 @@ bna_port_cb_llport_stopped(struct bna_port *port,
 static void
 bna_llport_init(struct bna_llport *llport, struct bna *bna)
 {
-        llport->flags |= BNA_LLPORT_F_ENABLED;
+        llport->flags |= BNA_LLPORT_F_ADMIN_UP;
+        llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
         llport->type = BNA_PORT_T_REGULAR;
         llport->bna = bna;
 
         llport->link_status = BNA_LINK_DOWN;
 
-        llport->admin_up_count = 0;
+        llport->rx_started_count = 0;
 
         llport->stop_cbfn = NULL;
 
@@ -606,7 +673,8 @@ bna_llport_init(struct bna_llport *llport, struct bna *bna)
 static void
 bna_llport_uninit(struct bna_llport *llport)
 {
-        llport->flags &= ~BNA_LLPORT_F_ENABLED;
+        llport->flags &= ~BNA_LLPORT_F_ADMIN_UP;
+        llport->flags &= ~BNA_LLPORT_F_PORT_ENABLED;
 
         llport->bna = NULL;
 }
@@ -628,6 +696,8 @@ bna_llport_stop(struct bna_llport *llport)
 static void
 bna_llport_fail(struct bna_llport *llport)
 {
+        /* Reset the physical port status to enabled */
+        llport->flags |= BNA_LLPORT_F_PORT_ENABLED;
         bfa_fsm_send_event(llport, LLPORT_E_FAIL);
 }
 
@@ -638,25 +708,31 @@ bna_llport_state_get(struct bna_llport *llport)
 }
 
 void
-bna_llport_admin_up(struct bna_llport *llport)
+bna_llport_rx_started(struct bna_llport *llport)
 {
-        llport->admin_up_count++;
+        llport->rx_started_count++;
 
-        if (llport->admin_up_count == 1) {
-                llport->flags |= BNA_LLPORT_F_RX_ENABLED;
-                if (llport->flags & BNA_LLPORT_F_ENABLED)
+        if (llport->rx_started_count == 1) {
+
+                llport->flags |= BNA_LLPORT_F_RX_STARTED;
+
+                if (llport_can_be_up(llport))
                         bfa_fsm_send_event(llport, LLPORT_E_UP);
         }
 }
 
 void
-bna_llport_admin_down(struct bna_llport *llport)
+bna_llport_rx_stopped(struct bna_llport *llport)
 {
-        llport->admin_up_count--;
+        int llport_up = llport_is_up(llport);
+
+        llport->rx_started_count--;
 
-        if (llport->admin_up_count == 0) {
-                llport->flags &= ~BNA_LLPORT_F_RX_ENABLED;
-                if (llport->flags & BNA_LLPORT_F_ENABLED)
+        if (llport->rx_started_count == 0) {
+
+                llport->flags &= ~BNA_LLPORT_F_RX_STARTED;
+
+                if (llport_up)
                         bfa_fsm_send_event(llport, LLPORT_E_DOWN);
         }
 }
@@ -2056,37 +2132,6 @@ rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
         bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
 }
 
-static void
-__rxf_default_function_config(struct bna_rxf *rxf, enum bna_status status)
-{
-        struct bna_rx_fndb_ram *rx_fndb_ram;
-        u32 ctrl_flags;
-        int i;
-
-        rx_fndb_ram = (struct bna_rx_fndb_ram *)
-                        BNA_GET_MEM_BASE_ADDR(rxf->rx->bna->pcidev.pci_bar_kva,
-                        RX_FNDB_RAM_BASE_OFFSET);
-
-        for (i = 0; i < BFI_MAX_RXF; i++) {
-                if (status == BNA_STATUS_T_ENABLED) {
-                        if (i == rxf->rxf_id)
-                                continue;
-
-                        ctrl_flags =
-                                readl(&rx_fndb_ram[i].control_flags);
-                        ctrl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
-                        writel(ctrl_flags,
-                                                &rx_fndb_ram[i].control_flags);
-                } else {
-                        ctrl_flags =
-                                readl(&rx_fndb_ram[i].control_flags);
-                        ctrl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
-                        writel(ctrl_flags,
-                                                &rx_fndb_ram[i].control_flags);
-                }
-        }
-}
-
 int
 rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
 {
@@ -2153,46 +2198,6 @@ rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
 }
 
 int
-rxf_process_packet_filter_default(struct bna_rxf *rxf)
-{
-        struct bna *bna = rxf->rx->bna;
-
-        /* Enable/disable default mode */
-        if (is_default_enable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask)) {
-                /* move default configuration from pending -> active */
-                default_inactive(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                rxf->rxmode_active |= BNA_RXMODE_DEFAULT;
-
-                /* Disable VLAN filter to allow all VLANs */
-                __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
-                /* Redirect all other RxF vlan filtering to this one */
-                __rxf_default_function_config(rxf, BNA_STATUS_T_ENABLED);
-                rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
-                                BNA_STATUS_T_ENABLED);
-                return 1;
-        } else if (is_default_disable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask)) {
-                /* move default configuration from pending -> active */
-                default_inactive(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
-                bna->rxf_default_id = BFI_MAX_RXF;
-
-                /* Revert VLAN filter */
-                __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
-                /* Stop RxF vlan filter table redirection */
-                __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
-                rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
-                                BNA_STATUS_T_DISABLED);
-                return 1;
-        }
-
-        return 0;
-}
-
-int
 rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
 {
         /* Enable/disable allmulti mode */
@@ -2289,48 +2294,6 @@ rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
 }
 
 int
-rxf_clear_packet_filter_default(struct bna_rxf *rxf)
-{
-        struct bna *bna = rxf->rx->bna;
-
-        /* 8. Execute pending default mode disable command */
-        if (is_default_disable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask)) {
-                /* move default configuration from pending -> active */
-                default_inactive(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
-                bna->rxf_default_id = BFI_MAX_RXF;
-
-                /* Revert VLAN filter */
-                __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
-                /* Stop RxF vlan filter table redirection */
-                __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
-                rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
-                                BNA_STATUS_T_DISABLED);
-                return 1;
-        }
-
-        /* 9. Clear active default mode; move it to pending enable */
-        if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
-                /* move default configuration from active -> pending */
-                default_enable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
-
-                /* Revert VLAN filter */
-                __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
-                /* Stop RxF vlan filter table redirection */
-                __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
-                rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
-                                BNA_STATUS_T_DISABLED);
-                return 1;
-        }
-
-        return 0;
-}
-
-int
 rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
 {
         /* 10. Execute pending allmulti mode disable command */
@@ -2405,28 +2368,6 @@ rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
 }
 
 void
-rxf_reset_packet_filter_default(struct bna_rxf *rxf)
-{
-        struct bna *bna = rxf->rx->bna;
-
-        /* 8. Clear pending default mode disable */
-        if (is_default_disable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask)) {
-                default_inactive(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
-                bna->rxf_default_id = BFI_MAX_RXF;
-        }
-
-        /* 9. Move default mode config from active -> pending */
-        if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
-                default_enable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
-        }
-}
-
-void
 rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
 {
         /* 10. Clear pending allmulti mode disable */
@@ -2523,76 +2464,6 @@ rxf_promisc_disable(struct bna_rxf *rxf)
  *      1 = need h/w change
  */
 static int
-rxf_default_enable(struct bna_rxf *rxf)
-{
-        struct bna *bna = rxf->rx->bna;
-        int ret = 0;
-
-        /* There can not be any pending disable command */
-
-        /* Do nothing if pending enable or already enabled */
-        if (is_default_enable(rxf->rxmode_pending,
-                rxf->rxmode_pending_bitmask) ||
-                (rxf->rxmode_active & BNA_RXMODE_DEFAULT)) {
-                /* Schedule enable */
-        } else {
-                /* Default mode should not be active in the system */
-                default_enable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                bna->rxf_default_id = rxf->rxf_id;
-                ret = 1;
-        }
-
-        return ret;
-}
-
-/**
- * Should only be called by bna_rxf_mode_set.
- * Helps deciding if h/w configuration is needed or not.
- *  Returns:
- *      0 = no h/w change
- *      1 = need h/w change
- */
-static int
-rxf_default_disable(struct bna_rxf *rxf)
-{
-        struct bna *bna = rxf->rx->bna;
-        int ret = 0;
-
-        /* There can not be any pending disable */
-
-        /* Turn off pending enable command , if any */
-        if (is_default_enable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask)) {
-                /* Promisc mode should not be active */
-                /* system default state should be pending */
-                default_inactive(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                /* Remove the default state from the system */
-                bna->rxf_default_id = BFI_MAX_RXF;
-
-        /* Schedule disable */
-        } else if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
-                /* Default mode should be active in the system */
-                default_disable(rxf->rxmode_pending,
-                                rxf->rxmode_pending_bitmask);
-                ret = 1;
-
-        /* Do nothing if already disabled */
-        } else {
-        }
-
-        return ret;
-}
-
-/**
- * Should only be called by bna_rxf_mode_set.
- * Helps deciding if h/w configuration is needed or not.
- *  Returns:
- *      0 = no h/w change
- *      1 = need h/w change
- */
-static int
 rxf_allmulti_enable(struct bna_rxf *rxf)
 {
         int ret = 0;
@@ -2654,38 +2525,13 @@ bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
         struct bna_rxf *rxf = &rx->rxf;
         int need_hw_config = 0;
 
-        /* Error checks */
+        /* Process the commands */
 
         if (is_promisc_enable(new_mode, bitmask)) {
                 /* If promisc mode is already enabled elsewhere in the system */
                 if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
                         (rx->bna->rxf_promisc_id != rxf->rxf_id))
                         goto err_return;
-
-                /* If default mode is already enabled in the system */
-                if (rx->bna->rxf_default_id != BFI_MAX_RXF)
-                        goto err_return;
-
-                /* Trying to enable promiscuous and default mode together */
-                if (is_default_enable(new_mode, bitmask))
-                        goto err_return;
-        }
-
-        if (is_default_enable(new_mode, bitmask)) {
-                /* If default mode is already enabled elsewhere in the system */
-                if ((rx->bna->rxf_default_id != BFI_MAX_RXF) &&
-                        (rx->bna->rxf_default_id != rxf->rxf_id)) {
-                                goto err_return;
-                }
-
-                /* If promiscuous mode is already enabled in the system */
-                if (rx->bna->rxf_promisc_id != BFI_MAX_RXF)
-                        goto err_return;
-        }
-
-        /* Process the commands */
-
-        if (is_promisc_enable(new_mode, bitmask)) {
                 if (rxf_promisc_enable(rxf))
                         need_hw_config = 1;
         } else if (is_promisc_disable(new_mode, bitmask)) {
@@ -2693,14 +2539,6 @@ bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
                         need_hw_config = 1;
         }
 
-        if (is_default_enable(new_mode, bitmask)) {
-                if (rxf_default_enable(rxf))
-                        need_hw_config = 1;
-        } else if (is_default_disable(new_mode, bitmask)) {
-                if (rxf_default_disable(rxf))
-                        need_hw_config = 1;
-        }
-
         if (is_allmulti_enable(new_mode, bitmask)) {
                 if (rxf_allmulti_enable(rxf))
                         need_hw_config = 1;
@@ -3126,7 +2964,6 @@ bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
 
         bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
 
-        bna->rxf_default_id = BFI_MAX_RXF;
         bna->rxf_promisc_id = BFI_MAX_RXF;
 
         /* Mbox q element for posting stat request to f/w */
diff --git a/drivers/net/bna/bna_txrx.c b/drivers/net/bna/bna_txrx.c
index ad93fdb0f427..58c7664040dc 100644
--- a/drivers/net/bna/bna_txrx.c
+++ b/drivers/net/bna/bna_txrx.c
@@ -1226,8 +1226,7 @@ rxf_process_packet_filter_vlan(struct bna_rxf *rxf)
         /* Apply the VLAN filter */
         if (rxf->rxf_flags & BNA_RXF_FL_VLAN_CONFIG_PENDING) {
                 rxf->rxf_flags &= ~BNA_RXF_FL_VLAN_CONFIG_PENDING;
-                if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC) &&
-                        !(rxf->rxmode_active & BNA_RXMODE_DEFAULT))
+                if (!(rxf->rxmode_active & BNA_RXMODE_PROMISC))
                         __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
         }
 
@@ -1276,9 +1275,6 @@ rxf_process_packet_filter(struct bna_rxf *rxf)
         if (rxf_process_packet_filter_promisc(rxf))
                 return 1;
 
-        if (rxf_process_packet_filter_default(rxf))
-                return 1;
-
         if (rxf_process_packet_filter_allmulti(rxf))
                 return 1;
 
@@ -1340,9 +1336,6 @@ rxf_clear_packet_filter(struct bna_rxf *rxf)
         if (rxf_clear_packet_filter_promisc(rxf))
                 return 1;
 
-        if (rxf_clear_packet_filter_default(rxf))
-                return 1;
-
         if (rxf_clear_packet_filter_allmulti(rxf))
                 return 1;
 
@@ -1389,8 +1382,6 @@ rxf_reset_packet_filter(struct bna_rxf *rxf)
 
         rxf_reset_packet_filter_promisc(rxf);
 
-        rxf_reset_packet_filter_default(rxf);
-
         rxf_reset_packet_filter_allmulti(rxf);
 }
 
@@ -1441,12 +1432,16 @@ bna_rxf_init(struct bna_rxf *rxf,
         memset(rxf->vlan_filter_table, 0,
                         (sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32)));
 
+        /* Set up VLAN 0 for pure priority tagged packets */
+        rxf->vlan_filter_table[0] |= 1;
+
         bfa_fsm_set_state(rxf, bna_rxf_sm_stopped);
 }
 
 static void
 bna_rxf_uninit(struct bna_rxf *rxf)
 {
+        struct bna *bna = rxf->rx->bna;
         struct bna_mac *mac;
 
         bna_rit_mod_seg_put(&rxf->rx->bna->rit_mod, rxf->rit_segment);
@@ -1473,6 +1468,27 @@ bna_rxf_uninit(struct bna_rxf *rxf)
                 bna_mcam_mod_mac_put(&rxf->rx->bna->mcam_mod, mac);
         }
 
+        /* Turn off pending promisc mode */
+        if (is_promisc_enable(rxf->rxmode_pending,
+                                rxf->rxmode_pending_bitmask)) {
+                /* system promisc state should be pending */
+                BUG_ON(!(bna->rxf_promisc_id == rxf->rxf_id));
+                promisc_inactive(rxf->rxmode_pending,
+                                rxf->rxmode_pending_bitmask);
+                 bna->rxf_promisc_id = BFI_MAX_RXF;
+        }
+        /* Promisc mode should not be active */
+        BUG_ON(rxf->rxmode_active & BNA_RXMODE_PROMISC);
+
+        /* Turn off pending all-multi mode */
+        if (is_allmulti_enable(rxf->rxmode_pending,
+                                rxf->rxmode_pending_bitmask)) {
+                allmulti_inactive(rxf->rxmode_pending,
+                                rxf->rxmode_pending_bitmask);
+        }
+        /* Allmulti mode should not be active */
+        BUG_ON(rxf->rxmode_active & BNA_RXMODE_ALLMULTI);
+
         rxf->rx = NULL;
 }
 
@@ -1947,7 +1963,7 @@ bna_rx_sm_started_entry(struct bna_rx *rx)
                 bna_ib_ack(&rxp->cq.ib->door_bell, 0);
         }
 
-        bna_llport_admin_up(&rx->bna->port.llport);
+        bna_llport_rx_started(&rx->bna->port.llport);
 }
 
 void
@@ -1955,13 +1971,13 @@ bna_rx_sm_started(struct bna_rx *rx, enum bna_rx_event event)
 {
         switch (event) {
         case RX_E_FAIL:
-                bna_llport_admin_down(&rx->bna->port.llport);
+                bna_llport_rx_stopped(&rx->bna->port.llport);
                 bfa_fsm_set_state(rx, bna_rx_sm_stopped);
                 rx_ib_fail(rx);
                 bna_rxf_fail(&rx->rxf);
                 break;
         case RX_E_STOP:
-                bna_llport_admin_down(&rx->bna->port.llport);
+                bna_llport_rx_stopped(&rx->bna->port.llport);
                 bfa_fsm_set_state(rx, bna_rx_sm_rxf_stop_wait);
                 break;
         default:
@@ -3373,7 +3389,7 @@ __bna_txq_start(struct bna_tx *tx, struct bna_txq *txq)
 
         txq_cfg.cns_ptr2_n_q_state = BNA_Q_IDLE_STATE;
         txq_cfg.nxt_qid_n_fid_n_pri = (((tx->txf.txf_id & 0x3f) << 3) |
-                        (txq->priority & 0x3));
+                        (txq->priority & 0x7));
         txq_cfg.wvc_n_cquota_n_rquota =
                         ((((u32)BFI_TX_MAX_WRR_QUOTA & 0xfff) << 12) |
                         (BFI_TX_MAX_WRR_QUOTA & 0xfff));
diff --git a/drivers/net/bna/bna_types.h b/drivers/net/bna/bna_types.h
index 6877310f6ef4..b9c134f7ad31 100644
--- a/drivers/net/bna/bna_types.h
+++ b/drivers/net/bna/bna_types.h
@@ -165,8 +165,7 @@ enum bna_rxp_type {
 
 enum bna_rxmode {
         BNA_RXMODE_PROMISC      = 1,
-        BNA_RXMODE_DEFAULT      = 2,
-        BNA_RXMODE_ALLMULTI     = 4
+        BNA_RXMODE_ALLMULTI     = 2
 };
 
 enum bna_rx_event {
@@ -249,8 +248,9 @@ enum bna_link_status {
 };
 
 enum bna_llport_flags {
-        BNA_LLPORT_F_ENABLED    = 1,
-        BNA_LLPORT_F_RX_ENABLED = 2
+        BNA_LLPORT_F_ADMIN_UP           = 1,
+        BNA_LLPORT_F_PORT_ENABLED       = 2,
+        BNA_LLPORT_F_RX_STARTED         = 4
 };
 
 enum bna_port_flags {
@@ -405,7 +405,7 @@ struct bna_llport {
 
         enum bna_link_status link_status;
 
-        int                     admin_up_count;
+        int                     rx_started_count;
 
         void (*stop_cbfn)(struct bna_port *, enum bna_cb_status);
 
@@ -1117,7 +1117,6 @@ struct bna {
 
         struct bna_rit_mod rit_mod;
 
-        int                     rxf_default_id;
         int                     rxf_promisc_id;
 
         struct bna_mbox_qe mbox_qe;
diff --git a/drivers/net/bna/bnad.c b/drivers/net/bna/bnad.c
index 7e839b9cec22..fad912656fe4 100644
--- a/drivers/net/bna/bnad.c
+++ b/drivers/net/bna/bnad.c
@@ -70,6 +70,8 @@ do {								\
         (sizeof(struct bnad_skb_unmap) * ((_depth) - 1));       \
 } while (0)
 
+#define BNAD_TXRX_SYNC_MDELAY   250     /* 250 msecs */
+
 /*
  * Reinitialize completions in CQ, once Rx is taken down
  */
@@ -107,7 +109,7 @@ static void
 bnad_free_all_txbufs(struct bnad *bnad,
                  struct bna_tcb *tcb)
 {
-        u16             unmap_cons;
+        u32             unmap_cons;
         struct bnad_unmap_q *unmap_q = tcb->unmap_q;
         struct bnad_skb_unmap *unmap_array;
         struct sk_buff          *skb = NULL;
@@ -130,7 +132,9 @@ bnad_free_all_txbufs(struct bnad *bnad,
                                                 PCI_DMA_TODEVICE);
 
                 pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr, 0);
-                unmap_cons++;
+                if (++unmap_cons >= unmap_q->q_depth)
+                        break;
+
                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
                         pci_unmap_page(bnad->pcidev,
                                        pci_unmap_addr(&unmap_array[unmap_cons],
@@ -139,7 +143,8 @@ bnad_free_all_txbufs(struct bnad *bnad,
                                        PCI_DMA_TODEVICE);
                         pci_unmap_addr_set(&unmap_array[unmap_cons], dma_addr,
                                            0);
-                        unmap_cons++;
+                        if (++unmap_cons >= unmap_q->q_depth)
+                                break;
                 }
                 dev_kfree_skb_any(skb);
         }
@@ -167,11 +172,11 @@ bnad_free_txbufs(struct bnad *bnad,
         /*
          * Just return if TX is stopped. This check is useful
          * when bnad_free_txbufs() runs out of a tasklet scheduled
-         * before bnad_cb_tx_cleanup() cleared BNAD_RF_TX_STARTED bit
+         * before bnad_cb_tx_cleanup() cleared BNAD_TXQ_TX_STARTED bit
          * but this routine runs actually after the cleanup has been
          * executed.
          */
-        if (!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))
+        if (!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
                 return 0;
 
         updated_hw_cons = *(tcb->hw_consumer_index);
@@ -239,7 +244,7 @@ bnad_tx_free_tasklet(unsigned long bnad_ptr)
 {
         struct bnad *bnad = (struct bnad *)bnad_ptr;
         struct bna_tcb *tcb;
-        u32             acked;
+        u32             acked = 0;
         int                     i, j;
 
         for (i = 0; i < bnad->num_tx; i++) {
@@ -252,10 +257,26 @@ bnad_tx_free_tasklet(unsigned long bnad_ptr)
                                 (!test_and_set_bit(BNAD_TXQ_FREE_SENT,
                                                   &tcb->flags))) {
                                 acked = bnad_free_txbufs(bnad, tcb);
-                                bna_ib_ack(tcb->i_dbell, acked);
+                                if (likely(test_bit(BNAD_TXQ_TX_STARTED,
+                                        &tcb->flags)))
+                                        bna_ib_ack(tcb->i_dbell, acked);
                                 smp_mb__before_clear_bit();
                                 clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
                         }
+                        if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED,
+                                                &tcb->flags)))
+                                continue;
+                        if (netif_queue_stopped(bnad->netdev)) {
+                                if (acked && netif_carrier_ok(bnad->netdev) &&
+                                        BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
+                                                BNAD_NETIF_WAKE_THRESHOLD) {
+                                        netif_wake_queue(bnad->netdev);
+                                        /* TODO */
+                                        /* Counters for individual TxQs? */
+                                        BNAD_UPDATE_CTR(bnad,
+                                                netif_queue_wakeup);
+                                }
+                        }
                 }
         }
 }
@@ -264,7 +285,7 @@ static u32
 bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
 {
         struct net_device *netdev = bnad->netdev;
-        u32 sent;
+        u32 sent = 0;
 
         if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
                 return 0;
@@ -275,12 +296,15 @@ bnad_tx(struct bnad *bnad, struct bna_tcb *tcb)
                     netif_carrier_ok(netdev) &&
                     BNA_QE_FREE_CNT(tcb, tcb->q_depth) >=
                                     BNAD_NETIF_WAKE_THRESHOLD) {
-                        netif_wake_queue(netdev);
-                        BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
+                        if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
+                                netif_wake_queue(netdev);
+                                BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
+                        }
                 }
+        }
+
+        if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
                 bna_ib_ack(tcb->i_dbell, sent);
-        } else
-                bna_ib_ack(tcb->i_dbell, 0);
 
         smp_mb__before_clear_bit();
         clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
@@ -313,25 +337,24 @@ bnad_reset_rcb(struct bnad *bnad, struct bna_rcb *rcb)
 }
 
 static void
-bnad_free_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
+bnad_free_all_rxbufs(struct bnad *bnad, struct bna_rcb *rcb)
 {
         struct bnad_unmap_q *unmap_q;
         struct sk_buff *skb;
+        int unmap_cons;
 
         unmap_q = rcb->unmap_q;
-        while (BNA_QE_IN_USE_CNT(unmap_q, unmap_q->q_depth)) {
-                skb = unmap_q->unmap_array[unmap_q->consumer_index].skb;
-                BUG_ON(!(skb));
-                unmap_q->unmap_array[unmap_q->consumer_index].skb = NULL;
+        for (unmap_cons = 0; unmap_cons < unmap_q->q_depth; unmap_cons++) {
+                skb = unmap_q->unmap_array[unmap_cons].skb;
+                if (!skb)
+                        continue;
+                unmap_q->unmap_array[unmap_cons].skb = NULL;
                 pci_unmap_single(bnad->pcidev, pci_unmap_addr(&unmap_q->
-                                        unmap_array[unmap_q->consumer_index],
-                                        dma_addr), rcb->rxq->buffer_size +
-                                        NET_IP_ALIGN, PCI_DMA_FROMDEVICE);
+                                        unmap_array[unmap_cons],
+                                        dma_addr), rcb->rxq->buffer_size,
+                                        PCI_DMA_FROMDEVICE);
                 dev_kfree_skb(skb);
-                BNA_QE_INDX_ADD(unmap_q->consumer_index, 1, unmap_q->q_depth);
-                BNA_QE_INDX_ADD(rcb->consumer_index, 1, rcb->q_depth);
         }
-
         bnad_reset_rcb(bnad, rcb);
 }
 
@@ -385,43 +408,11 @@ finishing:
                 unmap_q->producer_index = unmap_prod;
                 rcb->producer_index = unmap_prod;
                 smp_mb();
-                bna_rxq_prod_indx_doorbell(rcb);
+                if (likely(test_bit(BNAD_RXQ_STARTED, &rcb->flags)))
+                        bna_rxq_prod_indx_doorbell(rcb);
         }
 }
 
-/*
- * Locking is required in the enable path
- * because it is called from a napi poll
- * context, where the bna_lock is not held
- * unlike the IRQ context.
- */
-static void
-bnad_enable_txrx_irqs(struct bnad *bnad)
-{
-        struct bna_tcb *tcb;
-        struct bna_ccb *ccb;
-        int i, j;
-        unsigned long flags;
-
-        spin_lock_irqsave(&bnad->bna_lock, flags);
-        for (i = 0; i < bnad->num_tx; i++) {
-                for (j = 0; j < bnad->num_txq_per_tx; j++) {
-                        tcb = bnad->tx_info[i].tcb[j];
-                        bna_ib_coalescing_timer_set(tcb->i_dbell,
-                                tcb->txq->ib->ib_config.coalescing_timeo);
-                        bna_ib_ack(tcb->i_dbell, 0);
-                }
-        }
-
-        for (i = 0; i < bnad->num_rx; i++) {
-                for (j = 0; j < bnad->num_rxp_per_rx; j++) {
-                        ccb = bnad->rx_info[i].rx_ctrl[j].ccb;
-                        bnad_enable_rx_irq_unsafe(ccb);
-                }
-        }
-        spin_unlock_irqrestore(&bnad->bna_lock, flags);
-}
-
 static inline void
 bnad_refill_rxq(struct bnad *bnad, struct bna_rcb *rcb)
 {
@@ -448,6 +439,9 @@ bnad_poll_cq(struct bnad *bnad, struct bna_ccb *ccb, int budget)
         u32 qid0 = ccb->rcb[0]->rxq->rxq_id;
         struct bna_pkt_rate *pkt_rt = &ccb->pkt_rate;
 
+        if (!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))
+                return 0;
+
         prefetch(bnad->netdev);
         BNA_CQ_QPGE_PTR_GET(ccb->producer_index, ccb->sw_qpt, cmpl,
                             wi_range);
@@ -544,12 +538,15 @@ next:
         BNA_QE_INDX_ADD(ccb->producer_index, wis, ccb->q_depth);
 
         if (likely(ccb)) {
-                bna_ib_ack(ccb->i_dbell, packets);
+                if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
+                        bna_ib_ack(ccb->i_dbell, packets);
                 bnad_refill_rxq(bnad, ccb->rcb[0]);
                 if (ccb->rcb[1])
                         bnad_refill_rxq(bnad, ccb->rcb[1]);
-        } else
-                bna_ib_ack(ccb->i_dbell, 0);
+        } else {
+                if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
+                        bna_ib_ack(ccb->i_dbell, 0);
+        }
 
         return packets;
 }
@@ -557,6 +554,9 @@ next:
 static void
 bnad_disable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
 {
+        if (unlikely(!test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags)))
+                return;
+
         bna_ib_coalescing_timer_set(ccb->i_dbell, 0);
         bna_ib_ack(ccb->i_dbell, 0);
 }
@@ -566,7 +566,8 @@ bnad_enable_rx_irq(struct bnad *bnad, struct bna_ccb *ccb)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&bnad->bna_lock, flags); /* Because of polling context */
+        /* Because of polling context */
+        spin_lock_irqsave(&bnad->bna_lock, flags);
         bnad_enable_rx_irq_unsafe(ccb);
         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 }
@@ -575,9 +576,11 @@ static void
 bnad_netif_rx_schedule_poll(struct bnad *bnad, struct bna_ccb *ccb)
 {
         struct bnad_rx_ctrl *rx_ctrl = (struct bnad_rx_ctrl *)(ccb->ctrl);
-        if (likely(napi_schedule_prep((&rx_ctrl->napi)))) {
+        struct napi_struct *napi = &rx_ctrl->napi;
+
+        if (likely(napi_schedule_prep(napi))) {
                 bnad_disable_rx_irq(bnad, ccb);
-                __napi_schedule((&rx_ctrl->napi));
+                __napi_schedule(napi);
         }
         BNAD_UPDATE_CTR(bnad, netif_rx_schedule);
 }
@@ -602,12 +605,11 @@ bnad_msix_mbox_handler(int irq, void *data)
 {
         u32 intr_status;
         unsigned long flags;
-        struct net_device *netdev = data;
-        struct bnad *bnad;
+        struct bnad *bnad = (struct bnad *)data;
 
-        bnad = netdev_priv(netdev);
+        if (unlikely(test_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags)))
+                return IRQ_HANDLED;
 
-        /* BNA_ISR_GET(bnad); Inc Ref count */
         spin_lock_irqsave(&bnad->bna_lock, flags);
 
         bna_intr_status_get(&bnad->bna, intr_status);
@@ -617,7 +619,6 @@ bnad_msix_mbox_handler(int irq, void *data)
 
         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 
-        /* BNAD_ISR_PUT(bnad); Dec Ref count */
         return IRQ_HANDLED;
 }
 
@@ -627,8 +628,7 @@ bnad_isr(int irq, void *data)
         int i, j;
         u32 intr_status;
         unsigned long flags;
-        struct net_device *netdev = data;
-        struct bnad *bnad = netdev_priv(netdev);
+        struct bnad *bnad = (struct bnad *)data;
         struct bnad_rx_info *rx_info;
         struct bnad_rx_ctrl *rx_ctrl;
 
@@ -642,16 +642,21 @@ bnad_isr(int irq, void *data)
 
         spin_lock_irqsave(&bnad->bna_lock, flags);
 
-        if (BNA_IS_MBOX_ERR_INTR(intr_status)) {
+        if (BNA_IS_MBOX_ERR_INTR(intr_status))
                 bna_mbox_handler(&bnad->bna, intr_status);
-                if (!BNA_IS_INTX_DATA_INTR(intr_status)) {
-                        spin_unlock_irqrestore(&bnad->bna_lock, flags);
-                        goto done;
-                }
-        }
+
         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 
+        if (!BNA_IS_INTX_DATA_INTR(intr_status))
+                return IRQ_HANDLED;
+
         /* Process data interrupts */
+        /* Tx processing */
+        for (i = 0; i < bnad->num_tx; i++) {
+                for (j = 0; j < bnad->num_txq_per_tx; j++)
+                        bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
+        }
+        /* Rx processing */
         for (i = 0; i < bnad->num_rx; i++) {
                 rx_info = &bnad->rx_info[i];
                 if (!rx_info->rx)
@@ -663,7 +668,6 @@ bnad_isr(int irq, void *data)
                                                             rx_ctrl->ccb);
                 }
         }
-done:
         return IRQ_HANDLED;
 }
 
@@ -674,11 +678,7 @@ done:
 static void
 bnad_enable_mbox_irq(struct bnad *bnad)
 {
-        int irq = BNAD_GET_MBOX_IRQ(bnad);
-
-        if (test_and_clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))
-                if (bnad->cfg_flags & BNAD_CF_MSIX)
-                        enable_irq(irq);
+        clear_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
 
         BNAD_UPDATE_CTR(bnad, mbox_intr_enabled);
 }
@@ -690,14 +690,19 @@ bnad_enable_mbox_irq(struct bnad *bnad)
 static void
 bnad_disable_mbox_irq(struct bnad *bnad)
 {
-        int irq = BNAD_GET_MBOX_IRQ(bnad);
+        set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
 
+        BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
+}
 
-        if (!test_and_set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags))
-                if (bnad->cfg_flags & BNAD_CF_MSIX)
-                        disable_irq_nosync(irq);
+static void
+bnad_set_netdev_perm_addr(struct bnad *bnad)
+{
+        struct net_device *netdev = bnad->netdev;
 
-        BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
+        memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
+        if (is_zero_ether_addr(netdev->dev_addr))
+                memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
 }
 
 /* Control Path Handlers */
@@ -755,11 +760,14 @@ bnad_cb_port_link_status(struct bnad *bnad,
 
         if (link_up) {
                 if (!netif_carrier_ok(bnad->netdev)) {
+                        struct bna_tcb *tcb = bnad->tx_info[0].tcb[0];
+                        if (!tcb)
+                                return;
                         pr_warn("bna: %s link up\n",
                                 bnad->netdev->name);
                         netif_carrier_on(bnad->netdev);
                         BNAD_UPDATE_CTR(bnad, link_toggle);
-                        if (test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags)) {
+                        if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)) {
                                 /* Force an immediate Transmit Schedule */
                                 pr_info("bna: %s TX_STARTED\n",
                                         bnad->netdev->name);
@@ -807,6 +815,18 @@ bnad_cb_tcb_destroy(struct bnad *bnad, struct bna_tcb *tcb)
 {
         struct bnad_tx_info *tx_info =
                         (struct bnad_tx_info *)tcb->txq->tx->priv;
+        struct bnad_unmap_q *unmap_q = tcb->unmap_q;
+
+        while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
+                cpu_relax();
+
+        bnad_free_all_txbufs(bnad, tcb);
+
+        unmap_q->producer_index = 0;
+        unmap_q->consumer_index = 0;
+
+        smp_mb__before_clear_bit();
+        clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
 
         tx_info->tcb[tcb->id] = NULL;
 }
@@ -822,6 +842,12 @@ bnad_cb_rcb_setup(struct bnad *bnad, struct bna_rcb *rcb)
 }
 
 static void
+bnad_cb_rcb_destroy(struct bnad *bnad, struct bna_rcb *rcb)
+{
+        bnad_free_all_rxbufs(bnad, rcb);
+}
+
+static void
 bnad_cb_ccb_setup(struct bnad *bnad, struct bna_ccb *ccb)
 {
         struct bnad_rx_info *rx_info =
@@ -849,7 +875,7 @@ bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
         if (tx_info != &bnad->tx_info[0])
                 return;
 
-        clear_bit(BNAD_RF_TX_STARTED, &bnad->run_flags);
+        clear_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
         netif_stop_queue(bnad->netdev);
         pr_info("bna: %s TX_STOPPED\n", bnad->netdev->name);
 }
@@ -857,30 +883,15 @@ bnad_cb_tx_stall(struct bnad *bnad, struct bna_tcb *tcb)
 static void
 bnad_cb_tx_resume(struct bnad *bnad, struct bna_tcb *tcb)
 {
-        if (test_and_set_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))
-                return;
-
-        if (netif_carrier_ok(bnad->netdev)) {
-                pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
-                netif_wake_queue(bnad->netdev);
-                BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
-        }
-}
-
-static void
-bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
-{
-        struct bnad_unmap_q *unmap_q;
+        struct bnad_unmap_q *unmap_q = tcb->unmap_q;
 
-        if (!tcb || (!tcb->unmap_q))
+        if (test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))
                 return;
 
-        unmap_q = tcb->unmap_q;
-        if (!unmap_q->unmap_array)
-                return;
+        clear_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags);
 
-        if (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
-                return;
+        while (test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags))
+                cpu_relax();
 
         bnad_free_all_txbufs(bnad, tcb);
 
@@ -889,21 +900,45 @@ bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
 
         smp_mb__before_clear_bit();
         clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
+
+        /*
+         * Workaround for first device enable failure & we
+         * get a 0 MAC address. We try to get the MAC address
+         * again here.
+         */
+        if (is_zero_ether_addr(&bnad->perm_addr.mac[0])) {
+                bna_port_mac_get(&bnad->bna.port, &bnad->perm_addr);
+                bnad_set_netdev_perm_addr(bnad);
+        }
+
+        set_bit(BNAD_TXQ_TX_STARTED, &tcb->flags);
+
+        if (netif_carrier_ok(bnad->netdev)) {
+                pr_info("bna: %s TX_STARTED\n", bnad->netdev->name);
+                netif_wake_queue(bnad->netdev);
+                BNAD_UPDATE_CTR(bnad, netif_queue_wakeup);
+        }
+}
+
+static void
+bnad_cb_tx_cleanup(struct bnad *bnad, struct bna_tcb *tcb)
+{
+        /* Delay only once for the whole Tx Path Shutdown */
+        if (!test_and_set_bit(BNAD_RF_TX_SHUTDOWN_DELAYED, &bnad->run_flags))
+                mdelay(BNAD_TXRX_SYNC_MDELAY);
 }
 
 static void
 bnad_cb_rx_cleanup(struct bnad *bnad,
                         struct bna_ccb *ccb)
 {
-        bnad_cq_cmpl_init(bnad, ccb);
-
-        bnad_free_rxbufs(bnad, ccb->rcb[0]);
         clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags);
 
-        if (ccb->rcb[1]) {
-                bnad_free_rxbufs(bnad, ccb->rcb[1]);
+        if (ccb->rcb[1])
                 clear_bit(BNAD_RXQ_STARTED, &ccb->rcb[1]->flags);
-        }
+
+        if (!test_and_set_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags))
+                mdelay(BNAD_TXRX_SYNC_MDELAY);
 }
 
 static void
@@ -911,6 +946,13 @@ bnad_cb_rx_post(struct bnad *bnad, struct bna_rcb *rcb)
 {
         struct bnad_unmap_q *unmap_q = rcb->unmap_q;
 
+        clear_bit(BNAD_RF_RX_SHUTDOWN_DELAYED, &bnad->run_flags);
+
+        if (rcb == rcb->cq->ccb->rcb[0])
+                bnad_cq_cmpl_init(bnad, rcb->cq->ccb);
+
+        bnad_free_all_rxbufs(bnad, rcb);
+
         set_bit(BNAD_RXQ_STARTED, &rcb->flags);
 
         /* Now allocate & post buffers for this RCB */
@@ -1047,7 +1089,7 @@ bnad_mbox_irq_free(struct bnad *bnad,
         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 
         irq = BNAD_GET_MBOX_IRQ(bnad);
-        free_irq(irq, bnad->netdev);
+        free_irq(irq, bnad);
 
         kfree(intr_info->idl);
 }
@@ -1061,7 +1103,7 @@ static int
 bnad_mbox_irq_alloc(struct bnad *bnad,
                     struct bna_intr_info *intr_info)
 {
-        int             err;
+        int             err = 0;
         unsigned long   flags;
         u32     irq;
         irq_handler_t   irq_handler;
@@ -1096,22 +1138,17 @@ bnad_mbox_irq_alloc(struct bnad *bnad,
          */
         set_bit(BNAD_RF_MBOX_IRQ_DISABLED, &bnad->run_flags);
 
+        BNAD_UPDATE_CTR(bnad, mbox_intr_disabled);
+
         err = request_irq(irq, irq_handler, flags,
-                          bnad->mbox_irq_name, bnad->netdev);
+                          bnad->mbox_irq_name, bnad);
 
         if (err) {
                 kfree(intr_info->idl);
                 intr_info->idl = NULL;
-                return err;
         }
 
-        spin_lock_irqsave(&bnad->bna_lock, flags);
-
-        if (bnad->cfg_flags & BNAD_CF_MSIX)
-                disable_irq_nosync(irq);
-
-        spin_unlock_irqrestore(&bnad->bna_lock, flags);
-        return 0;
+        return err;
 }
 
 static void
@@ -1388,13 +1425,24 @@ bnad_ioc_hb_check(unsigned long data)
 }
 
 static void
-bnad_ioc_sem_timeout(unsigned long data)
+bnad_iocpf_timeout(unsigned long data)
+{
+        struct bnad *bnad = (struct bnad *)data;
+        unsigned long flags;
+
+        spin_lock_irqsave(&bnad->bna_lock, flags);
+        bfa_nw_iocpf_timeout((void *) &bnad->bna.device.ioc);
+        spin_unlock_irqrestore(&bnad->bna_lock, flags);
+}
+
+static void
+bnad_iocpf_sem_timeout(unsigned long data)
 {
         struct bnad *bnad = (struct bnad *)data;
         unsigned long flags;
 
         spin_lock_irqsave(&bnad->bna_lock, flags);
-        bfa_nw_ioc_sem_timeout((void *) &bnad->bna.device.ioc);
+        bfa_nw_iocpf_sem_timeout((void *) &bnad->bna.device.ioc);
         spin_unlock_irqrestore(&bnad->bna_lock, flags);
 }
 
@@ -1555,62 +1603,19 @@ poll_exit:
         return rcvd;
 }
 
-static int
-bnad_napi_poll_txrx(struct napi_struct *napi, int budget)
-{
-        struct bnad_rx_ctrl *rx_ctrl =
-                container_of(napi, struct bnad_rx_ctrl, napi);
-        struct bna_ccb *ccb;
-        struct bnad *bnad;
-        int                     rcvd = 0;
-        int                     i, j;
-
-        ccb = rx_ctrl->ccb;
-
-        bnad = ccb->bnad;
-
-        if (!netif_carrier_ok(bnad->netdev))
-                goto poll_exit;
-
-        /* Handle Tx Completions, if any */
-        for (i = 0; i < bnad->num_tx; i++) {
-                for (j = 0; j < bnad->num_txq_per_tx; j++)
-                        bnad_tx(bnad, bnad->tx_info[i].tcb[j]);
-        }
-
-        /* Handle Rx Completions */
-        rcvd = bnad_poll_cq(bnad, ccb, budget);
-        if (rcvd == budget)
-                return rcvd;
-poll_exit:
-        napi_complete((napi));
-
-        BNAD_UPDATE_CTR(bnad, netif_rx_complete);
-
-        bnad_enable_txrx_irqs(bnad);
-        return rcvd;
-}
-
 static void
 bnad_napi_enable(struct bnad *bnad, u32 rx_id)
 {
-        int (*napi_poll) (struct napi_struct *, int);
         struct bnad_rx_ctrl *rx_ctrl;
         int i;
-        unsigned long flags;
-
-        spin_lock_irqsave(&bnad->bna_lock, flags);
-        if (bnad->cfg_flags & BNAD_CF_MSIX)
-                napi_poll = bnad_napi_poll_rx;
-        else
-                napi_poll = bnad_napi_poll_txrx;
-        spin_unlock_irqrestore(&bnad->bna_lock, flags);
 
         /* Initialize & enable NAPI */
         for (i = 0; i < bnad->num_rxp_per_rx; i++) {
                 rx_ctrl = &bnad->rx_info[rx_id].rx_ctrl[i];
+
                 netif_napi_add(bnad->netdev, &rx_ctrl->napi,
-                               napi_poll, 64);
+                               bnad_napi_poll_rx, 64);
+
                 napi_enable(&rx_ctrl->napi);
         }
 }
@@ -1825,6 +1830,7 @@ bnad_setup_rx(struct bnad *bnad, uint rx_id)
 
         /* Initialize the Rx event handlers */
         rx_cbfn.rcb_setup_cbfn = bnad_cb_rcb_setup;
+        rx_cbfn.rcb_destroy_cbfn = bnad_cb_rcb_destroy;
         rx_cbfn.rcb_destroy_cbfn = NULL;
         rx_cbfn.ccb_setup_cbfn = bnad_cb_ccb_setup;
         rx_cbfn.ccb_destroy_cbfn = bnad_cb_ccb_destroy;
@@ -1968,6 +1974,27 @@ bnad_enable_default_bcast(struct bnad *bnad)
         return 0;
 }
 
+/* Called with bnad_conf_lock() held */
+static void
+bnad_restore_vlans(struct bnad *bnad, u32 rx_id)
+{
+        u16 vlan_id;
+        unsigned long flags;
+
+        if (!bnad->vlan_grp)
+                return;
+
+        BUG_ON(!(VLAN_N_VID == (BFI_MAX_VLAN + 1)));
+
+        for (vlan_id = 0; vlan_id < VLAN_N_VID; vlan_id++) {
+                if (!vlan_group_get_device(bnad->vlan_grp, vlan_id))
+                        continue;
+                spin_lock_irqsave(&bnad->bna_lock, flags);
+                bna_rx_vlan_add(bnad->rx_info[rx_id].rx, vlan_id);
+                spin_unlock_irqrestore(&bnad->bna_lock, flags);
+        }
+}
+
 /* Statistics utilities */
 void
 bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats)
@@ -2152,16 +2179,6 @@ bnad_q_num_adjust(struct bnad *bnad, int msix_vectors)
                 bnad->num_rxp_per_rx = 1;
 }
 
-static void
-bnad_set_netdev_perm_addr(struct bnad *bnad)
-{
-        struct net_device *netdev = bnad->netdev;
-
-        memcpy(netdev->perm_addr, &bnad->perm_addr, netdev->addr_len);
-        if (is_zero_ether_addr(netdev->dev_addr))
-                memcpy(netdev->dev_addr, &bnad->perm_addr, netdev->addr_len);
-}
-
 /* Enable / disable device */
 static void
 bnad_device_disable(struct bnad *bnad)
@@ -2353,6 +2370,9 @@ bnad_open(struct net_device *netdev)
         /* Enable broadcast */
         bnad_enable_default_bcast(bnad);
 
+        /* Restore VLANs, if any */
+        bnad_restore_vlans(bnad, 0);
+
         /* Set the UCAST address */
         spin_lock_irqsave(&bnad->bna_lock, flags);
         bnad_mac_addr_set_locked(bnad, netdev->dev_addr);
@@ -2433,21 +2453,21 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
                 return NETDEV_TX_OK;
         }
 
+        tx_id = 0;
+
+        tx_info = &bnad->tx_info[tx_id];
+        tcb = tx_info->tcb[tx_id];
+        unmap_q = tcb->unmap_q;
+
         /*
          * Takes care of the Tx that is scheduled between clearing the flag
          * and the netif_stop_queue() call.
          */
-        if (unlikely(!test_bit(BNAD_RF_TX_STARTED, &bnad->run_flags))) {
+        if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags))) {
                 dev_kfree_skb(skb);
                 return NETDEV_TX_OK;
         }
 
-        tx_id = 0;
-
-        tx_info = &bnad->tx_info[tx_id];
-        tcb = tx_info->tcb[tx_id];
-        unmap_q = tcb->unmap_q;
-
         vectors = 1 + skb_shinfo(skb)->nr_frags;
         if (vectors > BFI_TX_MAX_VECTORS_PER_PKT) {
                 dev_kfree_skb(skb);
@@ -2462,7 +2482,8 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
                     tcb->consumer_index &&
                     !test_and_set_bit(BNAD_TXQ_FREE_SENT, &tcb->flags)) {
                         acked = bnad_free_txbufs(bnad, tcb);
-                        bna_ib_ack(tcb->i_dbell, acked);
+                        if (likely(test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
+                                bna_ib_ack(tcb->i_dbell, acked);
                         smp_mb__before_clear_bit();
                         clear_bit(BNAD_TXQ_FREE_SENT, &tcb->flags);
                 } else {
@@ -2624,6 +2645,10 @@ bnad_start_xmit(struct sk_buff *skb, struct net_device *netdev)
         tcb->producer_index = txq_prod;
 
         smp_mb();
+
+        if (unlikely(!test_bit(BNAD_TXQ_TX_STARTED, &tcb->flags)))
+                return NETDEV_TX_OK;
+
         bna_txq_prod_indx_doorbell(tcb);
 
         if ((u16) (*tcb->hw_consumer_index) != tcb->consumer_index)
@@ -3032,7 +3057,7 @@ static int __devinit
 bnad_pci_probe(struct pci_dev *pdev,
                 const struct pci_device_id *pcidev_id)
 {
-        bool    using_dac;
+        bool    using_dac = false;
         int     err;
         struct bnad *bnad;
         struct bna *bna;
@@ -3066,7 +3091,7 @@ bnad_pci_probe(struct pci_dev *pdev,
         /*
          * PCI initialization
          *      Output : using_dac = 1 for 64 bit DMA
-         *                         = 0 for 32 bit DMA
+         *                         = 0 for 32 bit DMA
          */
         err = bnad_pci_init(bnad, pdev, &using_dac);
         if (err)
@@ -3084,6 +3109,9 @@ bnad_pci_probe(struct pci_dev *pdev,
         /* Initialize netdev structure, set up ethtool ops */
         bnad_netdev_init(bnad, using_dac);
 
+        /* Set link to down state */
+        netif_carrier_off(netdev);
+
         bnad_enable_msix(bnad);
 
         /* Get resource requirement form bna */
@@ -3115,11 +3143,13 @@ bnad_pci_probe(struct pci_dev *pdev,
                                 ((unsigned long)bnad));
         setup_timer(&bnad->bna.device.ioc.hb_timer, bnad_ioc_hb_check,
                                 ((unsigned long)bnad));
-        setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_ioc_sem_timeout,
+        setup_timer(&bnad->bna.device.ioc.iocpf_timer, bnad_iocpf_timeout,
+                                ((unsigned long)bnad));
+        setup_timer(&bnad->bna.device.ioc.sem_timer, bnad_iocpf_sem_timeout,
                                 ((unsigned long)bnad));
 
         /* Now start the timer before calling IOC */
-        mod_timer(&bnad->bna.device.ioc.ioc_timer,
+        mod_timer(&bnad->bna.device.ioc.iocpf_timer,
                   jiffies + msecs_to_jiffies(BNA_IOC_TIMER_FREQ));
 
         /*
@@ -3137,11 +3167,6 @@ bnad_pci_probe(struct pci_dev *pdev,
 
         mutex_unlock(&bnad->conf_mutex);
 
-        /*
-         * Make sure the link appears down to the stack
-         */
-        netif_carrier_off(netdev);
-
         /* Finally, reguister with net_device layer */
         err = register_netdev(netdev);
         if (err) {
diff --git a/drivers/net/bna/bnad.h b/drivers/net/bna/bnad.h
index ebc3a9078642..8b1d51557def 100644
--- a/drivers/net/bna/bnad.h
+++ b/drivers/net/bna/bnad.h
@@ -51,6 +51,7 @@
  */
 struct bnad_rx_ctrl {
         struct bna_ccb *ccb;
+        unsigned long  flags;
         struct napi_struct      napi;
 };
 
@@ -64,7 +65,7 @@ struct bnad_rx_ctrl {
 #define BNAD_NAME                       "bna"
 #define BNAD_NAME_LEN                   64
 
-#define BNAD_VERSION                    "2.3.2.0"
+#define BNAD_VERSION                    "2.3.2.3"
 
 #define BNAD_MAILBOX_MSIX_VECTORS       1
 
@@ -82,6 +83,7 @@ struct bnad_rx_ctrl {
 
 /* Bit positions for tcb->flags */
 #define BNAD_TXQ_FREE_SENT              0
+#define BNAD_TXQ_TX_STARTED             1
 
 /* Bit positions for rcb->flags */
 #define BNAD_RXQ_REFILL                 0
@@ -124,6 +126,7 @@ struct bnad_completion {
 struct bnad_drv_stats {
         u64             netif_queue_stop;
         u64             netif_queue_wakeup;
+        u64             netif_queue_stopped;
         u64             tso4;
         u64             tso6;
         u64             tso_err;
@@ -199,12 +202,12 @@ struct bnad_unmap_q {
 /* Set, tested & cleared using xxx_bit() functions */
 /* Values indicated bit positions */
 #define BNAD_RF_CEE_RUNNING             1
-#define BNAD_RF_HW_ERROR                2
-#define BNAD_RF_MBOX_IRQ_DISABLED       3
-#define BNAD_RF_TX_STARTED              4
-#define BNAD_RF_RX_STARTED              5
-#define BNAD_RF_DIM_TIMER_RUNNING       6
-#define BNAD_RF_STATS_TIMER_RUNNING     7
+#define BNAD_RF_MBOX_IRQ_DISABLED       2
+#define BNAD_RF_RX_STARTED              3
+#define BNAD_RF_DIM_TIMER_RUNNING       4
+#define BNAD_RF_STATS_TIMER_RUNNING     5
+#define BNAD_RF_TX_SHUTDOWN_DELAYED     6
+#define BNAD_RF_RX_SHUTDOWN_DELAYED     7
 
 struct bnad {
         struct net_device       *netdev;
@@ -306,8 +309,10 @@ extern void bnad_cleanup_rx(struct bnad *bnad, uint rx_id);
 extern void bnad_dim_timer_start(struct bnad *bnad);
 
 /* Statistics */
-extern void bnad_netdev_qstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats);
-extern void bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64 *stats);
+extern void bnad_netdev_qstats_fill(struct bnad *bnad,
+                struct rtnl_link_stats64 *stats);
+extern void bnad_netdev_hwstats_fill(struct bnad *bnad,
+                struct rtnl_link_stats64 *stats);
 
 /**
  * MACROS
@@ -320,9 +325,11 @@ extern void bnad_netdev_hwstats_fill(struct bnad *bnad, struct rtnl_link_stats64
 
 #define bnad_enable_rx_irq_unsafe(_ccb)                 \
 {                                                       \
-        bna_ib_coalescing_timer_set((_ccb)->i_dbell,    \
-                (_ccb)->rx_coalescing_timeo);           \
-        bna_ib_ack((_ccb)->i_dbell, 0);                 \
+        if (likely(test_bit(BNAD_RXQ_STARTED, &ccb->rcb[0]->flags))) {\
+                bna_ib_coalescing_timer_set((_ccb)->i_dbell,    \
+                        (_ccb)->rx_coalescing_timeo);           \
+                bna_ib_ack((_ccb)->i_dbell, 0);                 \
+        }                                                       \
 }
 
 #define bnad_dim_timer_running(_bnad)                           \
diff --git a/drivers/net/bna/bnad_ethtool.c b/drivers/net/bna/bnad_ethtool.c
index 11fa2ea842c1..99be5ae91991 100644
--- a/drivers/net/bna/bnad_ethtool.c
+++ b/drivers/net/bna/bnad_ethtool.c
@@ -68,6 +68,7 @@ static char *bnad_net_stats_strings[BNAD_ETHTOOL_STATS_NUM] = {
 
         "netif_queue_stop",
         "netif_queue_wakeup",
+        "netif_queue_stopped",
         "tso4",
         "tso6",
         "tso_err",
@@ -330,10 +331,6 @@ do {								\
 
         BNAD_GET_REG(PCIE_MISC_REG);
 
-        BNAD_GET_REG(HOST_SEM0_REG);
-        BNAD_GET_REG(HOST_SEM1_REG);
-        BNAD_GET_REG(HOST_SEM2_REG);
-        BNAD_GET_REG(HOST_SEM3_REG);
         BNAD_GET_REG(HOST_SEM0_INFO_REG);
         BNAD_GET_REG(HOST_SEM1_INFO_REG);
         BNAD_GET_REG(HOST_SEM2_INFO_REG);
@@ -1184,6 +1181,9 @@ bnad_get_ethtool_stats(struct net_device *netdev, struct ethtool_stats *stats,
 
         bi = sizeof(*net_stats64) / sizeof(u64);
 
+        /* Get netif_queue_stopped from stack */
+        bnad->stats.drv_stats.netif_queue_stopped = netif_queue_stopped(netdev);
+
         /* Fill driver stats into ethtool buffers */
         stats64 = (u64 *)&bnad->stats.drv_stats;
         for (i = 0; i < sizeof(struct bnad_drv_stats) / sizeof(u64); i++)
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 062600be073b..df99edf3464a 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -56,11 +56,11 @@
 #include "bnx2_fw.h"
 
 #define DRV_MODULE_NAME         "bnx2"
-#define DRV_MODULE_VERSION      "2.0.18"
-#define DRV_MODULE_RELDATE      "Oct 7, 2010"
-#define FW_MIPS_FILE_06         "bnx2/bnx2-mips-06-6.0.15.fw"
+#define DRV_MODULE_VERSION      "2.0.21"
+#define DRV_MODULE_RELDATE      "Dec 23, 2010"
+#define FW_MIPS_FILE_06         "bnx2/bnx2-mips-06-6.2.1.fw"
 #define FW_RV2P_FILE_06         "bnx2/bnx2-rv2p-06-6.0.15.fw"
-#define FW_MIPS_FILE_09         "bnx2/bnx2-mips-09-6.0.17.fw"
+#define FW_MIPS_FILE_09         "bnx2/bnx2-mips-09-6.2.1.fw"
 #define FW_RV2P_FILE_09_Ax      "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
 #define FW_RV2P_FILE_09         "bnx2/bnx2-rv2p-09-6.0.17.fw"
 
@@ -766,13 +766,10 @@ bnx2_alloc_rx_mem(struct bnx2 *bp)
                 int j;
 
                 rxr->rx_buf_ring =
-                        vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
+                        vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
                 if (rxr->rx_buf_ring == NULL)
                         return -ENOMEM;
 
-                memset(rxr->rx_buf_ring, 0,
-                       SW_RXBD_RING_SIZE * bp->rx_max_ring);
-
                 for (j = 0; j < bp->rx_max_ring; j++) {
                         rxr->rx_desc_ring[j] =
                                 dma_alloc_coherent(&bp->pdev->dev,
@@ -785,13 +782,11 @@ bnx2_alloc_rx_mem(struct bnx2 *bp)
                 }
 
                 if (bp->rx_pg_ring_size) {
-                        rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
+                        rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
                                                   bp->rx_max_pg_ring);
                         if (rxr->rx_pg_ring == NULL)
                                 return -ENOMEM;
 
-                        memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
-                               bp->rx_max_pg_ring);
                 }
 
                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
@@ -4645,13 +4640,28 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
 
         /* Wait for the current PCI transaction to complete before
          * issuing a reset. */
-        REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
-               BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
-               BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
-               BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
-               BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
-        val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
-        udelay(5);
+        if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
+            (CHIP_NUM(bp) == CHIP_NUM_5708)) {
+                REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
+                       BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
+                       BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
+                       BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
+                       BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
+                val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
+                udelay(5);
+        } else {  /* 5709 */
+                val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
+                val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
+                REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
+                val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
+
+                for (i = 0; i < 100; i++) {
+                        msleep(1);
+                        val = REG_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
+                        if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
+                                break;
+                }
+        }
 
         /* Wait for the firmware to tell us it is ok to issue a reset. */
         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
@@ -4673,7 +4683,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
 
-                pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
+                REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
 
         } else {
                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
@@ -6086,7 +6096,7 @@ bnx2_request_irq(struct bnx2 *bp)
 }
 
 static void
-bnx2_free_irq(struct bnx2 *bp)
+__bnx2_free_irq(struct bnx2 *bp)
 {
         struct bnx2_irq *irq;
         int i;
@@ -6097,6 +6107,13 @@ bnx2_free_irq(struct bnx2 *bp)
                         free_irq(irq->vector, &bp->bnx2_napi[i]);
                 irq->requested = 0;
         }
+}
+
+static void
+bnx2_free_irq(struct bnx2 *bp)
+{
+
+        __bnx2_free_irq(bp);
         if (bp->flags & BNX2_FLAG_USING_MSI)
                 pci_disable_msi(bp->pdev);
         else if (bp->flags & BNX2_FLAG_USING_MSIX)
@@ -6801,28 +6818,30 @@ bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
         u32 *p = _p, i, offset;
         u8 *orig_p = _p;
         struct bnx2 *bp = netdev_priv(dev);
-        u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
-                                 0x0800, 0x0880, 0x0c00, 0x0c10,
-                                 0x0c30, 0x0d08, 0x1000, 0x101c,
-                                 0x1040, 0x1048, 0x1080, 0x10a4,
-                                 0x1400, 0x1490, 0x1498, 0x14f0,
-                                 0x1500, 0x155c, 0x1580, 0x15dc,
-                                 0x1600, 0x1658, 0x1680, 0x16d8,
-                                 0x1800, 0x1820, 0x1840, 0x1854,
-                                 0x1880, 0x1894, 0x1900, 0x1984,
-                                 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
-                                 0x1c80, 0x1c94, 0x1d00, 0x1d84,
-                                 0x2000, 0x2030, 0x23c0, 0x2400,
-                                 0x2800, 0x2820, 0x2830, 0x2850,
-                                 0x2b40, 0x2c10, 0x2fc0, 0x3058,
-                                 0x3c00, 0x3c94, 0x4000, 0x4010,
-                                 0x4080, 0x4090, 0x43c0, 0x4458,
-                                 0x4c00, 0x4c18, 0x4c40, 0x4c54,
-                                 0x4fc0, 0x5010, 0x53c0, 0x5444,
-                                 0x5c00, 0x5c18, 0x5c80, 0x5c90,
-                                 0x5fc0, 0x6000, 0x6400, 0x6428,
-                                 0x6800, 0x6848, 0x684c, 0x6860,
-                                 0x6888, 0x6910, 0x8000 };
+        static const u32 reg_boundaries[] = {
+                0x0000, 0x0098, 0x0400, 0x045c,
+                0x0800, 0x0880, 0x0c00, 0x0c10,
+                0x0c30, 0x0d08, 0x1000, 0x101c,
+                0x1040, 0x1048, 0x1080, 0x10a4,
+                0x1400, 0x1490, 0x1498, 0x14f0,
+                0x1500, 0x155c, 0x1580, 0x15dc,
+                0x1600, 0x1658, 0x1680, 0x16d8,
+                0x1800, 0x1820, 0x1840, 0x1854,
+                0x1880, 0x1894, 0x1900, 0x1984,
+                0x1c00, 0x1c0c, 0x1c40, 0x1c54,
+                0x1c80, 0x1c94, 0x1d00, 0x1d84,
+                0x2000, 0x2030, 0x23c0, 0x2400,
+                0x2800, 0x2820, 0x2830, 0x2850,
+                0x2b40, 0x2c10, 0x2fc0, 0x3058,
+                0x3c00, 0x3c94, 0x4000, 0x4010,
+                0x4080, 0x4090, 0x43c0, 0x4458,
+                0x4c00, 0x4c18, 0x4c40, 0x4c54,
+                0x4fc0, 0x5010, 0x53c0, 0x5444,
+                0x5c00, 0x5c18, 0x5c80, 0x5c90,
+                0x5fc0, 0x6000, 0x6400, 0x6428,
+                0x6800, 0x6848, 0x684c, 0x6860,
+                0x6888, 0x6910, 0x8000
+        };
 
         regs->version = 0;
 
@@ -7080,6 +7099,7 @@ bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
 
                 bnx2_netif_stop(bp, true);
                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
+                __bnx2_free_irq(bp);
                 bnx2_free_skbs(bp);
                 bnx2_free_mem(bp);
         }
@@ -7092,6 +7112,9 @@ bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
 
                 rc = bnx2_alloc_mem(bp);
                 if (!rc)
+                        rc = bnx2_request_irq(bp);
+
+                if (!rc)
                         rc = bnx2_init_nic(bp, 0);
 
                 if (rc) {
@@ -7914,15 +7937,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                 goto err_out_release;
         }
 
+        bnx2_set_power_state(bp, PCI_D0);
+
         /* Configure byte swap and enable write to the reg_window registers.
          * Rely on CPU to do target byte swapping on big endian systems
          * The chip's target access swapping will not swap all accesses
          */
-        pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
-                               BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
-                               BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
-
-        bnx2_set_power_state(bp, PCI_D0);
+        REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
+                   BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
+                   BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
 
         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
 
@@ -8383,8 +8406,6 @@ bnx2_remove_one(struct pci_dev *pdev)
         struct net_device *dev = pci_get_drvdata(pdev);
         struct bnx2 *bp = netdev_priv(dev);
 
-        flush_scheduled_work();
-
         unregister_netdev(dev);
 
         if (bp->mips_firmware)
@@ -8421,7 +8442,7 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
         if (!netif_running(dev))
                 return 0;
 
-        flush_scheduled_work();
+        cancel_work_sync(&bp->reset_task);
         bnx2_netif_stop(bp, true);
         netif_device_detach(dev);
         del_timer_sync(&bp->timer);
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index bf4c3421067d..5488a2e82fe9 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -461,6 +461,8 @@ struct l2_fhdr {
 #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR                  0x00000090
 #define BNX2_PCICFG_MAILBOX_QUEUE_DATA                  0x00000094
 
+#define BNX2_PCICFG_DEVICE_CONTROL                      0x000000b4
+#define BNX2_PCICFG_DEVICE_STATUS_NO_PEND                ((1L<<5)<<16)
 
 /*
  *  pci_reg definition
diff --git a/drivers/net/bnx2x/Makefile b/drivers/net/bnx2x/Makefile
index 084afce89ae9..bb83a2961273 100644
--- a/drivers/net/bnx2x/Makefile
+++ b/drivers/net/bnx2x/Makefile
@@ -4,4 +4,4 @@
 
 obj-$(CONFIG_BNX2X) += bnx2x.o
 
-bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o
+bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index d255428122fc..a6cd335c9436 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -13,6 +13,8 @@
 
 #ifndef BNX2X_H
 #define BNX2X_H
+#include <linux/netdevice.h>
+#include <linux/types.h>
 
 /* compilation time flags */
 
@@ -20,15 +22,17 @@
  * (you will need to reboot afterwards) */
 /* #define BNX2X_STOP_ON_ERROR */
 
-#define DRV_MODULE_VERSION      "1.60.01-0"
-#define DRV_MODULE_RELDATE      "2010/11/12"
+#define DRV_MODULE_VERSION      "1.62.00-3"
+#define DRV_MODULE_RELDATE      "2010/12/21"
 #define BNX2X_BC_VER            0x040200
 
 #define BNX2X_MULTI_QUEUE
 
 #define BNX2X_NEW_NAPI
 
-
+#if defined(CONFIG_DCB)
+#define BCM_DCB
+#endif
 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
 #define BCM_CNIC 1
 #include "../cnic_if.h"
@@ -48,6 +52,7 @@
 #include "bnx2x_fw_defs.h"
 #include "bnx2x_hsi.h"
 #include "bnx2x_link.h"
+#include "bnx2x_dcb.h"
 #include "bnx2x_stats.h"
 
 /* error/debug prints */
@@ -199,10 +204,25 @@ void bnx2x_panic_dump(struct bnx2x *bp);
 /* EQ completions */
 #define HC_SP_INDEX_EQ_CONS                     7
 
+/* FCoE L2 connection completions */
+#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS         6
+#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS         4
 /* iSCSI L2 */
 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS           5
 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS        1
 
+/* Special clients parameters */
+
+/* SB indices */
+/* FCoE L2 */
+#define BNX2X_FCOE_L2_RX_INDEX \
+        (&bp->def_status_blk->sp_sb.\
+        index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
+
+#define BNX2X_FCOE_L2_TX_INDEX \
+        (&bp->def_status_blk->sp_sb.\
+        index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
+
 /**
  *  CIDs and CLIDs:
  *  CLIDs below is a CLID for func 0, then the CLID for other
@@ -215,12 +235,19 @@ void bnx2x_panic_dump(struct bnx2x *bp);
 #define BNX2X_ISCSI_ETH_CL_ID           17
 #define BNX2X_ISCSI_ETH_CID             17
 
+/* FCoE L2 */
+#define BNX2X_FCOE_ETH_CL_ID            18
+#define BNX2X_FCOE_ETH_CID              18
+
 /** Additional rings budgeting */
 #ifdef BCM_CNIC
 #define CNIC_CONTEXT_USE                1
+#define FCOE_CONTEXT_USE                1
 #else
 #define CNIC_CONTEXT_USE                0
+#define FCOE_CONTEXT_USE                0
 #endif /* BCM_CNIC */
+#define NONE_ETH_CONTEXT_USE    (FCOE_CONTEXT_USE)
 
 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
         AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
@@ -401,6 +428,17 @@ struct bnx2x_fastpath {
 };
 
 #define bnx2x_fp(bp, nr, var)           (bp->fp[nr].var)
+#ifdef BCM_CNIC
+/* FCoE L2 `fastpath' is right after the eth entries */
+#define FCOE_IDX                        BNX2X_NUM_ETH_QUEUES(bp)
+#define bnx2x_fcoe_fp(bp)               (&bp->fp[FCOE_IDX])
+#define bnx2x_fcoe(bp, var)             (bnx2x_fcoe_fp(bp)->var)
+#define IS_FCOE_FP(fp)                  (fp->index == FCOE_IDX)
+#define IS_FCOE_IDX(idx)                ((idx) == FCOE_IDX)
+#else
+#define IS_FCOE_FP(fp)          false
+#define IS_FCOE_IDX(idx)        false
+#endif
 
 
 /* MC hsi */
@@ -598,6 +636,7 @@ struct bnx2x_common {
 
 #define CHIP_METAL(bp)                  (bp->common.chip_id & 0x00000ff0)
 #define CHIP_BOND_ID(bp)                (bp->common.chip_id & 0x0000000f)
+#define CHIP_PARITY_ENABLED(bp) (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
 
         int                     flash_size;
 #define NVRAM_1MB_SIZE                  0x20000 /* 1M bit in bytes */
@@ -669,8 +708,14 @@ struct bnx2x_port {
 enum {
         CAM_ETH_LINE = 0,
         CAM_ISCSI_ETH_LINE,
-        CAM_MAX_PF_LINE = CAM_ISCSI_ETH_LINE
+        CAM_FIP_ETH_LINE,
+        CAM_FIP_MCAST_LINE,
+        CAM_MAX_PF_LINE = CAM_FIP_MCAST_LINE
 };
+/* number of MACs per function in NIG memory - used for SI mode */
+#define NIG_LLH_FUNC_MEM_SIZE           16
+/* number of entries in NIG_REG_LLHX_FUNC_MEM */
+#define NIG_LLH_FUNC_MEM_MAX_OFFSET     8
 
 #define BNX2X_VF_ID_INVALID     0xFF
 
@@ -710,6 +755,14 @@ enum {
  */
 #define L2_FP_COUNT(cid_cnt)    ((cid_cnt) - CNIC_CONTEXT_USE)
 
+/*
+ * The number of FP-SB allocated by the driver == max number of regular L2
+ * queues + 1 for the CNIC which also consumes an FP-SB
+ */
+#define FP_SB_COUNT(cid_cnt)    ((cid_cnt) - FCOE_CONTEXT_USE)
+#define NUM_IGU_SB_REQUIRED(cid_cnt) \
+                                (FP_SB_COUNT(cid_cnt) - NONE_ETH_CONTEXT_USE)
+
 union cdu_context {
         struct eth_context eth;
         char pad[1024];
@@ -722,7 +775,8 @@ union cdu_context {
 
 #ifdef BCM_CNIC
 #define CNIC_ISCSI_CID_MAX      256
-#define CNIC_CID_MAX            (CNIC_ISCSI_CID_MAX)
+#define CNIC_FCOE_CID_MAX       2048
+#define CNIC_CID_MAX            (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
 #define CNIC_ILT_LINES          DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
 #endif
 
@@ -770,6 +824,8 @@ struct bnx2x_slowpath {
 
         u32                             wb_comp;
         u32                             wb_data[4];
+        /* pfc configuration for DCBX ramrod */
+        struct flow_control_configuration pfc_config;
 };
 
 #define bnx2x_sp(bp, var)               (&bp->slowpath->var)
@@ -918,6 +974,10 @@ struct bnx2x {
 #define DISABLE_MSI_FLAG                0x200
 #define BP_NOMCP(bp)                    (bp->flags & NO_MCP_FLAG)
 #define MF_FUNC_DIS                     0x1000
+#define FCOE_MACS_SET                   0x2000
+#define NO_FCOE_FLAG                    0x4000
+
+#define NO_FCOE(bp)             ((bp)->flags & NO_FCOE_FLAG)
 
         int                     pf_num; /* absolute PF number */
         int                     pfid;   /* per-path PF number */
@@ -967,6 +1027,8 @@ struct bnx2x {
         u16                     mf_ov;
         u8                      mf_mode;
 #define IS_MF(bp)               (bp->mf_mode != 0)
+#define IS_MF_SI(bp)            (bp->mf_mode == MULTI_FUNCTION_SI)
+#define IS_MF_SD(bp)            (bp->mf_mode == MULTI_FUNCTION_SD)
 
         u8                      wol;
 
@@ -1010,6 +1072,7 @@ struct bnx2x {
 #define BNX2X_ACCEPT_ALL_UNICAST        0x0004
 #define BNX2X_ACCEPT_ALL_MULTICAST      0x0008
 #define BNX2X_ACCEPT_BROADCAST          0x0010
+#define BNX2X_ACCEPT_UNMATCHED_UCAST    0x0020
 #define BNX2X_PROMISCUOUS_MODE          0x10000
 
         u32                     rx_mode;
@@ -1062,7 +1125,8 @@ struct bnx2x {
         u16                     cnic_kwq_pending;
         u16                     cnic_spq_pending;
         struct mutex            cnic_mutex;
-        u8                      iscsi_mac[6];
+        u8                      iscsi_mac[ETH_ALEN];
+        u8                      fip_mac[ETH_ALEN];
 #endif
 
         int                     dmae_ready;
@@ -1122,6 +1186,31 @@ struct bnx2x {
 
         char                    fw_ver[32];
         const struct firmware   *firmware;
+        /* LLDP params */
+        struct bnx2x_config_lldp_params         lldp_config_params;
+
+        /* DCB support on/off */
+        u16 dcb_state;
+#define BNX2X_DCB_STATE_OFF                     0
+#define BNX2X_DCB_STATE_ON                      1
+
+        /* DCBX engine mode */
+        int dcbx_enabled;
+#define BNX2X_DCBX_ENABLED_OFF                  0
+#define BNX2X_DCBX_ENABLED_ON_NEG_OFF           1
+#define BNX2X_DCBX_ENABLED_ON_NEG_ON            2
+#define BNX2X_DCBX_ENABLED_INVALID              (-1)
+
+        bool dcbx_mode_uset;
+
+        struct bnx2x_config_dcbx_params         dcbx_config_params;
+
+        struct bnx2x_dcbx_port_params           dcbx_port_params;
+        int                                     dcb_version;
+
+        /* DCBX Negotation results */
+        struct dcbx_features                    dcbx_local_feat;
+        u32                                     dcbx_error;
 };
 
 /**
@@ -1152,10 +1241,17 @@ struct bnx2x {
 #define RSS_IPV6_TCP_CAP        0x0008
 
 #define BNX2X_NUM_QUEUES(bp)    (bp->num_queues)
+#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NONE_ETH_CONTEXT_USE)
+
+/* ethtool statistics are displayed for all regular ethernet queues and the
+ * fcoe L2 queue if not disabled
+ */
+#define BNX2X_NUM_STAT_QUEUES(bp) (NO_FCOE(bp) ? BNX2X_NUM_ETH_QUEUES(bp) : \
+                           (BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE))
+
 #define is_multi(bp)            (BNX2X_NUM_QUEUES(bp) > 1)
 
 #define BNX2X_MAX_QUEUES(bp)    (bp->igu_sb_cnt - CNIC_CONTEXT_USE)
-#define is_eth_multi(bp)        (BNX2X_NUM_ETH_QUEUES(bp) > 1)
 
 #define RSS_IPV4_CAP_MASK                                               \
         TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
@@ -1248,6 +1344,7 @@ struct bnx2x_client_ramrod_params {
         u16 cl_id;
         u32 cid;
         u8 poll;
+#define CLIENT_IS_FCOE                  0x01
 #define CLIENT_IS_LEADING_RSS           0x02
         u8 flags;
 };
@@ -1280,11 +1377,54 @@ struct bnx2x_func_init_params {
         u16             spq_prod;       /* valid iff FUNC_FLG_SPQ */
 };
 
+#define for_each_eth_queue(bp, var) \
+                        for (var = 0; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
+
+#define for_each_nondefault_eth_queue(bp, var) \
+                        for (var = 1; var < BNX2X_NUM_ETH_QUEUES(bp); var++)
+
+#define for_each_napi_queue(bp, var) \
+        for (var = 0; \
+                var < BNX2X_NUM_ETH_QUEUES(bp) + FCOE_CONTEXT_USE; var++) \
+                if (skip_queue(bp, var))        \
+                        continue;               \
+                else
+
 #define for_each_queue(bp, var) \
-                        for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++)
+        for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
+                if (skip_queue(bp, var))        \
+                        continue;               \
+                else
+
+#define for_each_rx_queue(bp, var) \
+        for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
+                if (skip_rx_queue(bp, var))     \
+                        continue;               \
+                else
+
+#define for_each_tx_queue(bp, var) \
+        for (var = 0; var < BNX2X_NUM_QUEUES(bp); var++) \
+                if (skip_tx_queue(bp, var))     \
+                        continue;               \
+                else
+
 #define for_each_nondefault_queue(bp, var) \
-                        for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++)
+        for (var = 1; var < BNX2X_NUM_QUEUES(bp); var++) \
+                if (skip_queue(bp, var))        \
+                        continue;               \
+                else
+
+/* skip rx queue
+ * if FCOE l2 support is disabled and this is the fcoe L2 queue
+ */
+#define skip_rx_queue(bp, idx)  (NO_FCOE(bp) && IS_FCOE_IDX(idx))
 
+/* skip tx queue
+ * if FCOE l2 support is disabled and this is the fcoe L2 queue
+ */
+#define skip_tx_queue(bp, idx)  (NO_FCOE(bp) && IS_FCOE_IDX(idx))
+
+#define skip_queue(bp, idx)     (NO_FCOE(bp) && IS_FCOE_IDX(idx))
 
 #define WAIT_RAMROD_POLL        0x01
 #define WAIT_RAMROD_COMMON      0x02
@@ -1329,7 +1469,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 
 #define BNX2X_ILT_ZALLOC(x, y, size) \
         do { \
-                x = pci_alloc_consistent(bp->pdev, size, y); \
+                x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
                 if (x) \
                         memset(x, 0, size); \
         } while (0)
@@ -1337,7 +1477,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
 #define BNX2X_ILT_FREE(x, y, size) \
         do { \
                 if (x) { \
-                        pci_free_consistent(bp->pdev, size, x, y); \
+                        dma_free_coherent(&bp->pdev->dev, size, x, y); \
                         x = NULL; \
                         y = 0; \
                 } \
@@ -1608,10 +1748,6 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
         MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
         (T_ETH_MAC_COMMAND_INVALIDATE))
 
-#define CAM_INVALIDATE(x) \
-        (x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
-
-
 /* Number of u32 elements in MC hash array */
 #define MC_HASH_SIZE                    8
 #define MC_HASH_OFFSET(bp, i)           (BAR_TSTRORM_INTMEM + \
diff --git a/drivers/net/bnx2x/bnx2x_cmn.c b/drivers/net/bnx2x/bnx2x_cmn.c
index 0af361e4e3d1..710ce5d04c53 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/bnx2x/bnx2x_cmn.c
@@ -698,6 +698,29 @@ void bnx2x_release_phy_lock(struct bnx2x *bp)
         mutex_unlock(&bp->port.phy_mutex);
 }
 
+/* calculates MF speed according to current linespeed and MF configuration */
+u16 bnx2x_get_mf_speed(struct bnx2x *bp)
+{
+        u16 line_speed = bp->link_vars.line_speed;
+        if (IS_MF(bp)) {
+                u16 maxCfg = (bp->mf_config[BP_VN(bp)] &
+                                                FUNC_MF_CFG_MAX_BW_MASK) >>
+                                                FUNC_MF_CFG_MAX_BW_SHIFT;
+                /* Calculate the current MAX line speed limit for the DCC
+                 * capable devices
+                 */
+                if (IS_MF_SD(bp)) {
+                        u16 vn_max_rate = maxCfg * 100;
+
+                        if (vn_max_rate < line_speed)
+                                line_speed = vn_max_rate;
+                } else /* IS_MF_SI(bp)) */
+                        line_speed = (line_speed * maxCfg) / 100;
+        }
+
+        return line_speed;
+}
+
 void bnx2x_link_report(struct bnx2x *bp)
 {
         if (bp->flags & MF_FUNC_DIS) {
@@ -713,17 +736,8 @@ void bnx2x_link_report(struct bnx2x *bp)
                         netif_carrier_on(bp->dev);
                 netdev_info(bp->dev, "NIC Link is Up, ");
 
-                line_speed = bp->link_vars.line_speed;
-                if (IS_MF(bp)) {
-                        u16 vn_max_rate;
+                line_speed = bnx2x_get_mf_speed(bp);
 
-                        vn_max_rate =
-                                ((bp->mf_config[BP_VN(bp)] &
-                                  FUNC_MF_CFG_MAX_BW_MASK) >>
-                                                FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
-                        if (vn_max_rate < line_speed)
-                                line_speed = vn_max_rate;
-                }
                 pr_cont("%d Mbps ", line_speed);
 
                 if (bp->link_vars.duplex == DUPLEX_FULL)
@@ -813,7 +827,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
         DP(NETIF_MSG_IFUP,
            "mtu %d  rx_buf_size %d\n", bp->dev->mtu, bp->rx_buf_size);
 
-        for_each_queue(bp, j) {
+        for_each_rx_queue(bp, j) {
                 struct bnx2x_fastpath *fp = &bp->fp[j];
 
                 if (!fp->disable_tpa) {
@@ -866,7 +880,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
                 }
         }
 
-        for_each_queue(bp, j) {
+        for_each_rx_queue(bp, j) {
                 struct bnx2x_fastpath *fp = &bp->fp[j];
 
                 fp->rx_bd_cons = 0;
@@ -897,7 +911,7 @@ static void bnx2x_free_tx_skbs(struct bnx2x *bp)
 {
         int i;
 
-        for_each_queue(bp, i) {
+        for_each_tx_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
 
                 u16 bd_cons = fp->tx_bd_cons;
@@ -915,7 +929,7 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp)
 {
         int i, j;
 
-        for_each_queue(bp, j) {
+        for_each_rx_queue(bp, j) {
                 struct bnx2x_fastpath *fp = &bp->fp[j];
 
                 for (i = 0; i < NUM_RX_BD; i++) {
@@ -956,7 +970,7 @@ static void bnx2x_free_msix_irqs(struct bnx2x *bp)
 #ifdef BCM_CNIC
         offset++;
 #endif
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq  "
                    "state %x\n", i, bp->msix_table[i + offset].vector,
                    bnx2x_fp(bp, i, state));
@@ -990,14 +1004,14 @@ int bnx2x_enable_msix(struct bnx2x *bp)
            bp->msix_table[msix_vec].entry, bp->msix_table[msix_vec].entry);
         msix_vec++;
 #endif
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 bp->msix_table[msix_vec].entry = msix_vec;
                 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d "
                    "(fastpath #%u)\n", msix_vec, msix_vec, i);
                 msix_vec++;
         }
 
-        req_cnt = BNX2X_NUM_QUEUES(bp) + CNIC_CONTEXT_USE + 1;
+        req_cnt = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_CONTEXT_USE + 1;
 
         rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], req_cnt);
 
@@ -1053,7 +1067,7 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
 #ifdef BCM_CNIC
         offset++;
 #endif
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
                          bp->dev->name, i);
@@ -1070,7 +1084,7 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
                 fp->state = BNX2X_FP_STATE_IRQ;
         }
 
-        i = BNX2X_NUM_QUEUES(bp);
+        i = BNX2X_NUM_ETH_QUEUES(bp);
         offset = 1 + CNIC_CONTEXT_USE;
         netdev_info(bp->dev, "using MSI-X  IRQs: sp %d  fp[%d] %d"
                " ... fp[%d] %d\n",
@@ -1117,7 +1131,7 @@ static void bnx2x_napi_enable(struct bnx2x *bp)
 {
         int i;
 
-        for_each_queue(bp, i)
+        for_each_napi_queue(bp, i)
                 napi_enable(&bnx2x_fp(bp, i, napi));
 }
 
@@ -1125,7 +1139,7 @@ static void bnx2x_napi_disable(struct bnx2x *bp)
 {
         int i;
 
-        for_each_queue(bp, i)
+        for_each_napi_queue(bp, i)
                 napi_disable(&bnx2x_fp(bp, i, napi));
 }
 
@@ -1153,6 +1167,35 @@ void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
         netif_tx_disable(bp->dev);
 }
 
+u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
+{
+#ifdef BCM_CNIC
+        struct bnx2x *bp = netdev_priv(dev);
+        if (NO_FCOE(bp))
+                return skb_tx_hash(dev, skb);
+        else {
+                struct ethhdr *hdr = (struct ethhdr *)skb->data;
+                u16 ether_type = ntohs(hdr->h_proto);
+
+                /* Skip VLAN tag if present */
+                if (ether_type == ETH_P_8021Q) {
+                        struct vlan_ethhdr *vhdr =
+                                (struct vlan_ethhdr *)skb->data;
+
+                        ether_type = ntohs(vhdr->h_vlan_encapsulated_proto);
+                }
+
+                /* If ethertype is FCoE or FIP - use FCoE ring */
+                if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
+                        return bnx2x_fcoe(bp, index);
+        }
+#endif
+        /* Select a none-FCoE queue:  if FCoE is enabled, exclude FCoE L2 ring
+         */
+        return __skb_tx_hash(dev, skb,
+                        dev->real_num_tx_queues - FCOE_CONTEXT_USE);
+}
+
 void bnx2x_set_num_queues(struct bnx2x *bp)
 {
         switch (bp->multi_mode) {
@@ -1167,7 +1210,22 @@ void bnx2x_set_num_queues(struct bnx2x *bp)
                 bp->num_queues = 1;
                 break;
         }
+
+        /* Add special queues */
+        bp->num_queues += NONE_ETH_CONTEXT_USE;
+}
+
+#ifdef BCM_CNIC
+static inline void bnx2x_set_fcoe_eth_macs(struct bnx2x *bp)
+{
+        if (!NO_FCOE(bp)) {
+                if (!IS_MF_SD(bp))
+                        bnx2x_set_fip_eth_mac_addr(bp, 1);
+                bnx2x_set_all_enode_macs(bp, 1);
+                bp->flags |= FCOE_MACS_SET;
+        }
 }
+#endif
 
 static void bnx2x_release_firmware(struct bnx2x *bp)
 {
@@ -1177,6 +1235,20 @@ static void bnx2x_release_firmware(struct bnx2x *bp)
         release_firmware(bp->firmware);
 }
 
+static inline int bnx2x_set_real_num_queues(struct bnx2x *bp)
+{
+        int rc, num = bp->num_queues;
+
+#ifdef BCM_CNIC
+        if (NO_FCOE(bp))
+                num -= FCOE_CONTEXT_USE;
+
+#endif
+        netif_set_real_num_tx_queues(bp->dev, num);
+        rc = netif_set_real_num_rx_queues(bp->dev, num);
+        return rc;
+}
+
 /* must be called with rtnl_lock */
 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
 {
@@ -1203,10 +1275,9 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
         if (bnx2x_alloc_mem(bp))
                 return -ENOMEM;
 
-        netif_set_real_num_tx_queues(bp->dev, bp->num_queues);
-        rc = netif_set_real_num_rx_queues(bp->dev, bp->num_queues);
+        rc = bnx2x_set_real_num_queues(bp);
         if (rc) {
-                BNX2X_ERR("Unable to update real_num_rx_queues\n");
+                BNX2X_ERR("Unable to set real_num_queues\n");
                 goto load_error0;
         }
 
@@ -1214,6 +1285,10 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
                 bnx2x_fp(bp, i, disable_tpa) =
                                         ((bp->flags & TPA_ENABLE_FLAG) == 0);
 
+#ifdef BCM_CNIC
+        /* We don't want TPA on FCoE L2 ring */
+        bnx2x_fcoe(bp, disable_tpa) = 1;
+#endif
         bnx2x_napi_enable(bp);
 
         /* Send LOAD_REQUEST command to MCP
@@ -1296,6 +1371,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
                 }
         }
 
+        bnx2x_dcbx_init(bp);
+
         bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
 
         rc = bnx2x_func_start(bp);
@@ -1344,6 +1421,10 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
         /* Now when Clients are configured we are ready to work */
         bp->state = BNX2X_STATE_OPEN;
 
+#ifdef BCM_CNIC
+        bnx2x_set_fcoe_eth_macs(bp);
+#endif
+
         bnx2x_set_eth_mac(bp, 1);
 
         if (bp->port.pmf)
@@ -1402,7 +1483,7 @@ load_error3:
 
         /* Free SKBs, SGEs, TPA pool and driver internals */
         bnx2x_free_skbs(bp);
-        for_each_queue(bp, i)
+        for_each_rx_queue(bp, i)
                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
 
         /* Release IRQs */
@@ -1473,7 +1554,7 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
 
         /* Free SKBs, SGEs, TPA pool and driver internals */
         bnx2x_free_skbs(bp);
-        for_each_queue(bp, i)
+        for_each_rx_queue(bp, i)
                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
 
         bnx2x_free_mem(bp);
@@ -1577,6 +1658,17 @@ int bnx2x_poll(struct napi_struct *napi, int budget)
 
                 /* Fall out from the NAPI loop if needed */
                 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
+#ifdef BCM_CNIC
+                        /* No need to update SB for FCoE L2 ring as long as
+                         * it's connected to the default SB and the SB
+                         * has been updated when NAPI was scheduled.
+                         */
+                        if (IS_FCOE_FP(fp)) {
+                                napi_complete(napi);
+                                break;
+                        }
+#endif
+
                         bnx2x_update_fpsb_idx(fp);
                         /* bnx2x_has_rx_work() reads the status block,
                          * thus we need to ensure that status block indices
@@ -1692,11 +1784,10 @@ static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
                 }
         }
 
-        if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4)
-                rc |= (XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP);
-
-        else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
-                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6);
+        if (skb_is_gso_v6(skb))
+                rc |= XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6;
+        else if (skb_is_gso(skb))
+                rc |= XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP;
 
         return rc;
 }
@@ -2242,7 +2333,7 @@ int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp)
         bp->fp = fp;
 
         /* msix table */
-        tbl = kzalloc((bp->l2_cid_count + 1) * sizeof(*tbl),
+        tbl = kzalloc((FP_SB_COUNT(bp->l2_cid_count) + 1) * sizeof(*tbl),
                                   GFP_KERNEL);
         if (!tbl)
                 goto alloc_err;
diff --git a/drivers/net/bnx2x/bnx2x_cmn.h b/drivers/net/bnx2x/bnx2x_cmn.h
index 6b28739c5302..03eb4d68e6bb 100644
--- a/drivers/net/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/bnx2x/bnx2x_cmn.h
@@ -73,6 +73,16 @@ void bnx2x__link_status_update(struct bnx2x *bp);
 void bnx2x_link_report(struct bnx2x *bp);
 
 /**
+ * calculates MF speed according to current linespeed and MF
+ * configuration
+ *
+ * @param bp
+ *
+ * @return u16
+ */
+u16 bnx2x_get_mf_speed(struct bnx2x *bp);
+
+/**
  * MSI-X slowpath interrupt handler
  *
  * @param irq
@@ -232,6 +242,30 @@ int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource);
  */
 void bnx2x_set_eth_mac(struct bnx2x *bp, int set);
 
+#ifdef BCM_CNIC
+/**
+ * Set/Clear FIP MAC(s) at the next enties in the CAM after the ETH
+ * MAC(s). This function will wait until the ramdord completion
+ * returns.
+ *
+ * @param bp driver handle
+ * @param set set or clear the CAM entry
+ *
+ * @return 0 if cussess, -ENODEV if ramrod doesn't return.
+ */
+int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set);
+
+/**
+ * Set/Clear ALL_ENODE mcast MAC.
+ *
+ * @param bp
+ * @param set
+ *
+ * @return int
+ */
+int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set);
+#endif
+
 /**
  * Set MAC filtering configurations.
  *
@@ -290,6 +324,13 @@ int bnx2x_func_start(struct bnx2x *bp);
 void bnx2x_ilt_set_info(struct bnx2x *bp);
 
 /**
+ * Inintialize dcbx protocol
+ *
+ * @param bp
+ */
+void bnx2x_dcbx_init(struct bnx2x *bp);
+
+/**
  * Set power state to the requested value. Currently only D0 and
  * D3hot are supported.
  *
@@ -309,6 +350,9 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode);
 /* hard_xmit callback */
 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev);
 
+/* select_queue callback */
+u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb);
+
 int bnx2x_change_mac_addr(struct net_device *dev, void *p);
 
 /* NAPI poll Rx part */
@@ -685,7 +729,7 @@ static inline void bnx2x_add_all_napi(struct bnx2x *bp)
         int i;
 
         /* Add NAPI objects */
-        for_each_queue(bp, i)
+        for_each_napi_queue(bp, i)
                 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi),
                                bnx2x_poll, BNX2X_NAPI_WEIGHT);
 }
@@ -694,7 +738,7 @@ static inline void bnx2x_del_all_napi(struct bnx2x *bp)
 {
         int i;
 
-        for_each_queue(bp, i)
+        for_each_napi_queue(bp, i)
                 netif_napi_del(&bnx2x_fp(bp, i, napi));
 }
 
@@ -860,7 +904,7 @@ static inline void bnx2x_init_tx_rings(struct bnx2x *bp)
 {
         int i, j;
 
-        for_each_queue(bp, j) {
+        for_each_tx_queue(bp, j) {
                 struct bnx2x_fastpath *fp = &bp->fp[j];
 
                 for (i = 1; i <= NUM_TX_RINGS; i++) {
@@ -939,7 +983,30 @@ static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
         }
 }
 
+#ifdef BCM_CNIC
+static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
+{
+        bnx2x_fcoe(bp, cl_id) = BNX2X_FCOE_ETH_CL_ID +
+                BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
+        bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID;
+        bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
+        bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
+        bnx2x_fcoe(bp, bp) = bp;
+        bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
+        bnx2x_fcoe(bp, index) = FCOE_IDX;
+        bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
+        bnx2x_fcoe(bp, tx_cons_sb) = BNX2X_FCOE_L2_TX_INDEX;
+        /* qZone id equals to FW (per path) client id */
+        bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fcoe(bp, cl_id) +
+                BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
+                                ETH_MAX_RX_CLIENTS_E1H);
+        /* init shortcut */
+        bnx2x_fcoe(bp, ustorm_rx_prods_offset) = CHIP_IS_E2(bp) ?
+            USTORM_RX_PRODS_E2_OFFSET(bnx2x_fcoe(bp, cl_qzone_id)) :
+            USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), bnx2x_fcoe_fp(bp)->cl_id);
 
+}
+#endif
 
 static inline void __storm_memset_struct(struct bnx2x *bp,
                                          u32 addr, size_t size, u32 *data)
diff --git a/drivers/net/bnx2x/bnx2x_dcb.c b/drivers/net/bnx2x/bnx2x_dcb.c
new file mode 100644
index 000000000000..fb60021f81fb
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_dcb.c
@@ -0,0 +1,2118 @@
+/* bnx2x_dcb.c: Broadcom Everest network driver.
+ *
+ * Copyright 2009-2010 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Dmitry Kravkov
+ *
+ */
+#include <linux/netdevice.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+
+#include "bnx2x.h"
+#include "bnx2x_cmn.h"
+#include "bnx2x_dcb.h"
+
+
+/* forward declarations of dcbx related functions */
+static void bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp);
+static void bnx2x_pfc_set_pfc(struct bnx2x *bp);
+static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp);
+static void bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp);
+static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
+                                          u32 *set_configuration_ets_pg,
+                                          u32 *pri_pg_tbl);
+static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
+                                            u32 *pg_pri_orginal_spread,
+                                            struct pg_help_data *help_data);
+static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
+                                       struct pg_help_data *help_data,
+                                       struct dcbx_ets_feature *ets,
+                                       u32 *pg_pri_orginal_spread);
+static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
+                                struct cos_help_data *cos_data,
+                                u32 *pg_pri_orginal_spread,
+                                struct dcbx_ets_feature *ets);
+static void bnx2x_pfc_fw_struct_e2(struct bnx2x *bp);
+
+
+static void bnx2x_pfc_set(struct bnx2x *bp)
+{
+        struct bnx2x_nig_brb_pfc_port_params pfc_params = {0};
+        u32 pri_bit, val = 0;
+        u8 pri;
+
+        /* Tx COS configuration */
+        if (bp->dcbx_port_params.ets.cos_params[0].pauseable)
+                pfc_params.rx_cos0_priority_mask =
+                        bp->dcbx_port_params.ets.cos_params[0].pri_bitmask;
+        if (bp->dcbx_port_params.ets.cos_params[1].pauseable)
+                pfc_params.rx_cos1_priority_mask =
+                        bp->dcbx_port_params.ets.cos_params[1].pri_bitmask;
+
+
+        /**
+         * Rx COS configuration
+         * Changing PFC RX configuration .
+         * In RX COS0 will always be configured to lossy and COS1 to lossless
+         */
+        for (pri = 0 ; pri < MAX_PFC_PRIORITIES ; pri++) {
+                pri_bit = 1 << pri;
+
+                if (pri_bit & DCBX_PFC_PRI_PAUSE_MASK(bp))
+                        val |= 1 << (pri * 4);
+        }
+
+        pfc_params.pkt_priority_to_cos = val;
+
+        /* RX COS0 */
+        pfc_params.llfc_low_priority_classes = 0;
+        /* RX COS1 */
+        pfc_params.llfc_high_priority_classes = DCBX_PFC_PRI_PAUSE_MASK(bp);
+
+        /* BRB configuration */
+        pfc_params.cos0_pauseable = false;
+        pfc_params.cos1_pauseable = true;
+
+        bnx2x_acquire_phy_lock(bp);
+        bp->link_params.feature_config_flags |= FEATURE_CONFIG_PFC_ENABLED;
+        bnx2x_update_pfc(&bp->link_params, &bp->link_vars, &pfc_params);
+        bnx2x_release_phy_lock(bp);
+}
+
+static void bnx2x_pfc_clear(struct bnx2x *bp)
+{
+        struct bnx2x_nig_brb_pfc_port_params nig_params = {0};
+        nig_params.pause_enable = 1;
+#ifdef BNX2X_SAFC
+        if (bp->flags & SAFC_TX_FLAG) {
+                u32 high = 0, low = 0;
+                int i;
+
+                for (i = 0; i < BNX2X_MAX_PRIORITY; i++) {
+                        if (bp->pri_map[i] == 1)
+                                high |= (1 << i);
+                        if (bp->pri_map[i] == 0)
+                                low |= (1 << i);
+                }
+
+                nig_params.llfc_low_priority_classes = high;
+                nig_params.llfc_low_priority_classes = low;
+
+                nig_params.pause_enable = 0;
+                nig_params.llfc_enable = 1;
+                nig_params.llfc_out_en = 1;
+        }
+#endif /* BNX2X_SAFC */
+        bnx2x_acquire_phy_lock(bp);
+        bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_PFC_ENABLED;
+        bnx2x_update_pfc(&bp->link_params, &bp->link_vars, &nig_params);
+        bnx2x_release_phy_lock(bp);
+}
+
+static void  bnx2x_dump_dcbx_drv_param(struct bnx2x *bp,
+                                       struct dcbx_features *features,
+                                       u32 error)
+{
+        u8 i = 0;
+        DP(NETIF_MSG_LINK, "local_mib.error %x\n", error);
+
+        /* PG */
+        DP(NETIF_MSG_LINK,
+           "local_mib.features.ets.enabled %x\n", features->ets.enabled);
+        for (i = 0; i < DCBX_MAX_NUM_PG_BW_ENTRIES; i++)
+                DP(NETIF_MSG_LINK,
+                   "local_mib.features.ets.pg_bw_tbl[%d] %d\n", i,
+                   DCBX_PG_BW_GET(features->ets.pg_bw_tbl, i));
+        for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++)
+                DP(NETIF_MSG_LINK,
+                   "local_mib.features.ets.pri_pg_tbl[%d] %d\n", i,
+                   DCBX_PRI_PG_GET(features->ets.pri_pg_tbl, i));
+
+        /* pfc */
+        DP(NETIF_MSG_LINK, "dcbx_features.pfc.pri_en_bitmap %x\n",
+                                        features->pfc.pri_en_bitmap);
+        DP(NETIF_MSG_LINK, "dcbx_features.pfc.pfc_caps %x\n",
+                                        features->pfc.pfc_caps);
+        DP(NETIF_MSG_LINK, "dcbx_features.pfc.enabled %x\n",
+                                        features->pfc.enabled);
+
+        DP(NETIF_MSG_LINK, "dcbx_features.app.default_pri %x\n",
+                                        features->app.default_pri);
+        DP(NETIF_MSG_LINK, "dcbx_features.app.tc_supported %x\n",
+                                        features->app.tc_supported);
+        DP(NETIF_MSG_LINK, "dcbx_features.app.enabled %x\n",
+                                        features->app.enabled);
+        for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
+                DP(NETIF_MSG_LINK,
+                   "dcbx_features.app.app_pri_tbl[%x].app_id %x\n",
+                   i, features->app.app_pri_tbl[i].app_id);
+                DP(NETIF_MSG_LINK,
+                   "dcbx_features.app.app_pri_tbl[%x].pri_bitmap %x\n",
+                   i, features->app.app_pri_tbl[i].pri_bitmap);
+                DP(NETIF_MSG_LINK,
+                   "dcbx_features.app.app_pri_tbl[%x].appBitfield %x\n",
+                   i, features->app.app_pri_tbl[i].appBitfield);
+        }
+}
+
+static void bnx2x_dcbx_get_ap_priority(struct bnx2x *bp,
+                                       u8 pri_bitmap,
+                                       u8 llfc_traf_type)
+{
+        u32 pri = MAX_PFC_PRIORITIES;
+        u32 index = MAX_PFC_PRIORITIES - 1;
+        u32 pri_mask;
+        u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+
+        /* Choose the highest priority */
+        while ((MAX_PFC_PRIORITIES == pri) && (0 != index)) {
+                pri_mask = 1 << index;
+                if (GET_FLAGS(pri_bitmap, pri_mask))
+                        pri = index ;
+                index--;
+        }
+
+        if (pri < MAX_PFC_PRIORITIES)
+                ttp[llfc_traf_type] = max_t(u32, ttp[llfc_traf_type], pri);
+}
+
+static void bnx2x_dcbx_get_ap_feature(struct bnx2x *bp,
+                                   struct dcbx_app_priority_feature *app,
+                                   u32 error) {
+        u8 index;
+        u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+
+        if (GET_FLAGS(error, DCBX_LOCAL_APP_ERROR))
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_ERROR\n");
+
+        if (app->enabled && !GET_FLAGS(error, DCBX_LOCAL_APP_ERROR)) {
+
+                bp->dcbx_port_params.app.enabled = true;
+
+                for (index = 0 ; index < LLFC_DRIVER_TRAFFIC_TYPE_MAX; index++)
+                        ttp[index] = 0;
+
+                if (app->default_pri < MAX_PFC_PRIORITIES)
+                        ttp[LLFC_TRAFFIC_TYPE_NW] = app->default_pri;
+
+                for (index = 0 ; index < DCBX_MAX_APP_PROTOCOL; index++) {
+                        struct dcbx_app_priority_entry *entry =
+                                                        app->app_pri_tbl;
+
+                        if (GET_FLAGS(entry[index].appBitfield,
+                                     DCBX_APP_SF_ETH_TYPE) &&
+                           ETH_TYPE_FCOE == entry[index].app_id)
+                                bnx2x_dcbx_get_ap_priority(bp,
+                                                entry[index].pri_bitmap,
+                                                LLFC_TRAFFIC_TYPE_FCOE);
+
+                        if (GET_FLAGS(entry[index].appBitfield,
+                                     DCBX_APP_SF_PORT) &&
+                           TCP_PORT_ISCSI == entry[index].app_id)
+                                bnx2x_dcbx_get_ap_priority(bp,
+                                                entry[index].pri_bitmap,
+                                                LLFC_TRAFFIC_TYPE_ISCSI);
+                }
+        } else {
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_DISABLED\n");
+                bp->dcbx_port_params.app.enabled = false;
+                for (index = 0 ; index < LLFC_DRIVER_TRAFFIC_TYPE_MAX; index++)
+                        ttp[index] = INVALID_TRAFFIC_TYPE_PRIORITY;
+        }
+}
+
+static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
+                                       struct dcbx_ets_feature *ets,
+                                       u32 error) {
+        int i = 0;
+        u32 pg_pri_orginal_spread[DCBX_MAX_NUM_PG_BW_ENTRIES] = {0};
+        struct pg_help_data pg_help_data;
+        struct bnx2x_dcbx_cos_params *cos_params =
+                        bp->dcbx_port_params.ets.cos_params;
+
+        memset(&pg_help_data, 0, sizeof(struct pg_help_data));
+
+
+        if (GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR))
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_ERROR\n");
+
+
+        /* Clean up old settings of ets on COS */
+        for (i = 0; i < E2_NUM_OF_COS ; i++) {
+
+                cos_params[i].pauseable = false;
+                cos_params[i].strict = BNX2X_DCBX_COS_NOT_STRICT;
+                cos_params[i].bw_tbl = DCBX_INVALID_COS_BW;
+                cos_params[i].pri_bitmask = DCBX_PFC_PRI_GET_NON_PAUSE(bp, 0);
+        }
+
+        if (bp->dcbx_port_params.app.enabled &&
+           !GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR) &&
+           ets->enabled) {
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_ENABLE\n");
+                bp->dcbx_port_params.ets.enabled = true;
+
+                bnx2x_dcbx_get_ets_pri_pg_tbl(bp,
+                                              pg_pri_orginal_spread,
+                                              ets->pri_pg_tbl);
+
+                bnx2x_dcbx_get_num_pg_traf_type(bp,
+                                                pg_pri_orginal_spread,
+                                                &pg_help_data);
+
+                bnx2x_dcbx_fill_cos_params(bp, &pg_help_data,
+                                           ets, pg_pri_orginal_spread);
+
+        } else {
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_DISABLED\n");
+                bp->dcbx_port_params.ets.enabled = false;
+                ets->pri_pg_tbl[0] = 0;
+
+                for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES ; i++)
+                        DCBX_PG_BW_SET(ets->pg_bw_tbl, i, 1);
+        }
+}
+
+static void  bnx2x_dcbx_get_pfc_feature(struct bnx2x *bp,
+                                        struct dcbx_pfc_feature *pfc, u32 error)
+{
+
+        if (GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR))
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_PFC_ERROR\n");
+
+        if (bp->dcbx_port_params.app.enabled &&
+           !GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR) &&
+           pfc->enabled) {
+                bp->dcbx_port_params.pfc.enabled = true;
+                bp->dcbx_port_params.pfc.priority_non_pauseable_mask =
+                        ~(pfc->pri_en_bitmap);
+        } else {
+                DP(NETIF_MSG_LINK, "DCBX_LOCAL_PFC_DISABLED\n");
+                bp->dcbx_port_params.pfc.enabled = false;
+                bp->dcbx_port_params.pfc.priority_non_pauseable_mask = 0;
+        }
+}
+
+static void bnx2x_get_dcbx_drv_param(struct bnx2x *bp,
+                                     struct dcbx_features *features,
+                                     u32 error)
+{
+        bnx2x_dcbx_get_ap_feature(bp, &features->app, error);
+
+        bnx2x_dcbx_get_pfc_feature(bp, &features->pfc, error);
+
+        bnx2x_dcbx_get_ets_feature(bp, &features->ets, error);
+}
+
+#define DCBX_LOCAL_MIB_MAX_TRY_READ             (100)
+static int bnx2x_dcbx_read_mib(struct bnx2x *bp,
+                               u32 *base_mib_addr,
+                               u32 offset,
+                               int read_mib_type)
+{
+        int max_try_read = 0, i;
+        u32 *buff, mib_size, prefix_seq_num, suffix_seq_num;
+        struct lldp_remote_mib *remote_mib ;
+        struct lldp_local_mib  *local_mib;
+
+
+        switch (read_mib_type) {
+        case DCBX_READ_LOCAL_MIB:
+                mib_size = sizeof(struct lldp_local_mib);
+                break;
+        case DCBX_READ_REMOTE_MIB:
+                mib_size = sizeof(struct lldp_remote_mib);
+                break;
+        default:
+                return 1; /*error*/
+        }
+
+        offset += BP_PORT(bp) * mib_size;
+
+        do {
+                buff = base_mib_addr;
+                for (i = 0; i < mib_size; i += 4, buff++)
+                        *buff = REG_RD(bp, offset + i);
+
+                max_try_read++;
+
+                switch (read_mib_type) {
+                case DCBX_READ_LOCAL_MIB:
+                        local_mib = (struct lldp_local_mib *) base_mib_addr;
+                        prefix_seq_num = local_mib->prefix_seq_num;
+                        suffix_seq_num = local_mib->suffix_seq_num;
+                        break;
+                case DCBX_READ_REMOTE_MIB:
+                        remote_mib = (struct lldp_remote_mib *) base_mib_addr;
+                        prefix_seq_num = remote_mib->prefix_seq_num;
+                        suffix_seq_num = remote_mib->suffix_seq_num;
+                        break;
+                default:
+                        return 1; /*error*/
+                }
+        } while ((prefix_seq_num != suffix_seq_num) &&
+               (max_try_read < DCBX_LOCAL_MIB_MAX_TRY_READ));
+
+        if (max_try_read >= DCBX_LOCAL_MIB_MAX_TRY_READ) {
+                BNX2X_ERR("MIB could not be read\n");
+                return 1;
+        }
+
+        return 0;
+}
+
+static void bnx2x_pfc_set_pfc(struct bnx2x *bp)
+{
+        if (CHIP_IS_E2(bp)) {
+                if (BP_PORT(bp)) {
+                        BNX2X_ERR("4 port mode is not supported");
+                        return;
+                }
+
+                if (bp->dcbx_port_params.pfc.enabled)
+
+                        /* 1. Fills up common PFC structures if required.*/
+                        /* 2. Configure NIG, MAC and BRB via the elink:
+                         *    elink must first check if BMAC is not in reset
+                         *    and only then configures the BMAC
+                         *    Or, configure EMAC.
+                         */
+                        bnx2x_pfc_set(bp);
+
+                else
+                        bnx2x_pfc_clear(bp);
+        }
+}
+
+static void bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp)
+{
+        DP(NETIF_MSG_LINK, "sending STOP TRAFFIC\n");
+        bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
+                      0 /* connectionless */,
+                      0 /* dataHi is zero */,
+                      0 /* dataLo is zero */,
+                      1 /* common */);
+}
+
+static void bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp)
+{
+        bnx2x_pfc_fw_struct_e2(bp);
+        DP(NETIF_MSG_LINK, "sending START TRAFFIC\n");
+        bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_START_TRAFFIC,
+                      0, /* connectionless */
+                      U64_HI(bnx2x_sp_mapping(bp, pfc_config)),
+                      U64_LO(bnx2x_sp_mapping(bp, pfc_config)),
+                      1  /* commmon */);
+}
+
+static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp)
+{
+        struct bnx2x_dcbx_pg_params *ets = &(bp->dcbx_port_params.ets);
+        u8      status = 0;
+
+        bnx2x_ets_disabled(&bp->link_params);
+
+        if (!ets->enabled)
+                return;
+
+        if ((ets->num_of_cos == 0) || (ets->num_of_cos > E2_NUM_OF_COS)) {
+                BNX2X_ERR("illegal num of cos= %x", ets->num_of_cos);
+                return;
+        }
+
+        /* valid COS entries */
+        if (ets->num_of_cos == 1)   /* no ETS */
+                return;
+
+        /* sanity */
+        if (((BNX2X_DCBX_COS_NOT_STRICT == ets->cos_params[0].strict) &&
+             (DCBX_INVALID_COS_BW == ets->cos_params[0].bw_tbl)) ||
+            ((BNX2X_DCBX_COS_NOT_STRICT == ets->cos_params[1].strict) &&
+             (DCBX_INVALID_COS_BW == ets->cos_params[1].bw_tbl))) {
+                BNX2X_ERR("all COS should have at least bw_limit or strict"
+                            "ets->cos_params[0].strict= %x"
+                            "ets->cos_params[0].bw_tbl= %x"
+                            "ets->cos_params[1].strict= %x"
+                            "ets->cos_params[1].bw_tbl= %x",
+                          ets->cos_params[0].strict,
+                          ets->cos_params[0].bw_tbl,
+                          ets->cos_params[1].strict,
+                          ets->cos_params[1].bw_tbl);
+                return;
+        }
+        /* If we join a group and there is bw_tbl and strict then bw rules */
+        if ((DCBX_INVALID_COS_BW != ets->cos_params[0].bw_tbl) &&
+            (DCBX_INVALID_COS_BW != ets->cos_params[1].bw_tbl)) {
+                u32 bw_tbl_0 = ets->cos_params[0].bw_tbl;
+                u32 bw_tbl_1 = ets->cos_params[1].bw_tbl;
+                /* Do not allow 0-100 configuration
+                 * since PBF does not support it
+                 * force 1-99 instead
+                 */
+                if (bw_tbl_0 == 0) {
+                        bw_tbl_0 = 1;
+                        bw_tbl_1 = 99;
+                } else if (bw_tbl_1 == 0) {
+                        bw_tbl_1 = 1;
+                        bw_tbl_0 = 99;
+                }
+
+                bnx2x_ets_bw_limit(&bp->link_params, bw_tbl_0, bw_tbl_1);
+        } else {
+                if (ets->cos_params[0].strict == BNX2X_DCBX_COS_HIGH_STRICT)
+                        status = bnx2x_ets_strict(&bp->link_params, 0);
+                else if (ets->cos_params[1].strict
+                                                == BNX2X_DCBX_COS_HIGH_STRICT)
+                        status = bnx2x_ets_strict(&bp->link_params, 1);
+
+                if (status)
+                        BNX2X_ERR("update_ets_params failed\n");
+        }
+}
+
+static int bnx2x_dcbx_read_shmem_neg_results(struct bnx2x *bp)
+{
+        struct lldp_local_mib local_mib = {0};
+        u32 dcbx_neg_res_offset = SHMEM2_RD(bp, dcbx_neg_res_offset);
+        int rc;
+
+        DP(NETIF_MSG_LINK, "dcbx_neg_res_offset 0x%x\n", dcbx_neg_res_offset);
+
+        if (SHMEM_DCBX_NEG_RES_NONE == dcbx_neg_res_offset) {
+                BNX2X_ERR("FW doesn't support dcbx_neg_res_offset\n");
+                return -EINVAL;
+        }
+        rc = bnx2x_dcbx_read_mib(bp, (u32 *)&local_mib, dcbx_neg_res_offset,
+                                 DCBX_READ_LOCAL_MIB);
+
+        if (rc) {
+                BNX2X_ERR("Faild to read local mib from FW\n");
+                return rc;
+        }
+
+        /* save features and error */
+        bp->dcbx_local_feat = local_mib.features;
+        bp->dcbx_error = local_mib.error;
+        return 0;
+}
+
+void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
+{
+        switch (state) {
+        case BNX2X_DCBX_STATE_NEG_RECEIVED:
+                {
+                        DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_NEG_RECEIVED\n");
+
+                        /* Read neg results if dcbx is in the FW */
+                        if (bnx2x_dcbx_read_shmem_neg_results(bp))
+                                return;
+
+                        bnx2x_dump_dcbx_drv_param(bp, &bp->dcbx_local_feat,
+                                                  bp->dcbx_error);
+
+                        bnx2x_get_dcbx_drv_param(bp, &bp->dcbx_local_feat,
+                                                 bp->dcbx_error);
+
+                        if (bp->state != BNX2X_STATE_OPENING_WAIT4_LOAD) {
+                                bnx2x_dcbx_stop_hw_tx(bp);
+                                return;
+                        }
+                        /* fall through */
+                }
+        case BNX2X_DCBX_STATE_TX_PAUSED:
+                DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_TX_PAUSED\n");
+                bnx2x_pfc_set_pfc(bp);
+
+                bnx2x_dcbx_update_ets_params(bp);
+                if (bp->state != BNX2X_STATE_OPENING_WAIT4_LOAD) {
+                        bnx2x_dcbx_resume_hw_tx(bp);
+                        return;
+                }
+                /* fall through */
+        case BNX2X_DCBX_STATE_TX_RELEASED:
+                DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_TX_RELEASED\n");
+                if (bp->state != BNX2X_STATE_OPENING_WAIT4_LOAD)
+                        bnx2x_fw_command(bp, DRV_MSG_CODE_DCBX_PMF_DRV_OK, 0);
+
+                return;
+        default:
+                BNX2X_ERR("Unknown DCBX_STATE\n");
+        }
+}
+
+
+#define LLDP_STATS_OFFSET(bp)           (BP_PORT(bp)*\
+                                        sizeof(struct lldp_dcbx_stat))
+
+/* calculate struct offset in array according to chip information */
+#define LLDP_PARAMS_OFFSET(bp)          (BP_PORT(bp)*sizeof(struct lldp_params))
+
+#define LLDP_ADMIN_MIB_OFFSET(bp)       (PORT_MAX*sizeof(struct lldp_params) + \
+                                      BP_PORT(bp)*sizeof(struct lldp_admin_mib))
+
+static void bnx2x_dcbx_lldp_updated_params(struct bnx2x *bp,
+                                           u32 dcbx_lldp_params_offset)
+{
+        struct lldp_params lldp_params = {0};
+        u32 i = 0, *buff = NULL;
+        u32 offset = dcbx_lldp_params_offset + LLDP_PARAMS_OFFSET(bp);
+
+        DP(NETIF_MSG_LINK, "lldp_offset 0x%x\n", offset);
+
+        if ((bp->lldp_config_params.overwrite_settings ==
+                                BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE)) {
+                /* Read the data first */
+                buff = (u32 *)&lldp_params;
+                for (i = 0; i < sizeof(struct lldp_params); i += 4,  buff++)
+                        *buff = REG_RD(bp, (offset + i));
+
+                lldp_params.msg_tx_hold =
+                        (u8)bp->lldp_config_params.msg_tx_hold;
+                lldp_params.msg_fast_tx_interval =
+                        (u8)bp->lldp_config_params.msg_fast_tx;
+                lldp_params.tx_crd_max =
+                        (u8)bp->lldp_config_params.tx_credit_max;
+                lldp_params.msg_tx_interval =
+                        (u8)bp->lldp_config_params.msg_tx_interval;
+                lldp_params.tx_fast =
+                        (u8)bp->lldp_config_params.tx_fast;
+
+                /* Write the data.*/
+                buff = (u32 *)&lldp_params;
+                for (i = 0; i < sizeof(struct lldp_params); i += 4, buff++)
+                        REG_WR(bp, (offset + i) , *buff);
+
+
+        } else if (BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE ==
+                                bp->lldp_config_params.overwrite_settings)
+                bp->lldp_config_params.overwrite_settings =
+                                BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID;
+}
+
+static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
+                                u32 dcbx_lldp_params_offset)
+{
+        struct lldp_admin_mib admin_mib;
+        u32 i, other_traf_type = PREDEFINED_APP_IDX_MAX, traf_type = 0;
+        u32 *buff;
+        u32 offset = dcbx_lldp_params_offset + LLDP_ADMIN_MIB_OFFSET(bp);
+
+        /*shortcuts*/
+        struct dcbx_features *af = &admin_mib.features;
+        struct bnx2x_config_dcbx_params *dp = &bp->dcbx_config_params;
+
+        memset(&admin_mib, 0, sizeof(struct lldp_admin_mib));
+        buff = (u32 *)&admin_mib;
+        /* Read the data first */
+        for (i = 0; i < sizeof(struct lldp_admin_mib); i += 4, buff++)
+                *buff = REG_RD(bp, (offset + i));
+
+        if (bp->dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_ON)
+                SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_DCBX_ENABLED);
+        else
+                RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_DCBX_ENABLED);
+
+        if ((BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE ==
+                                dp->overwrite_settings)) {
+                RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_CEE_VERSION_MASK);
+                admin_mib.ver_cfg_flags |=
+                        (dp->admin_dcbx_version << DCBX_CEE_VERSION_SHIFT) &
+                         DCBX_CEE_VERSION_MASK;
+
+                af->ets.enabled = (u8)dp->admin_ets_enable;
+
+                af->pfc.enabled = (u8)dp->admin_pfc_enable;
+
+                /* FOR IEEE dp->admin_tc_supported_tx_enable */
+                if (dp->admin_ets_configuration_tx_enable)
+                        SET_FLAGS(admin_mib.ver_cfg_flags,
+                                  DCBX_ETS_CONFIG_TX_ENABLED);
+                else
+                        RESET_FLAGS(admin_mib.ver_cfg_flags,
+                                    DCBX_ETS_CONFIG_TX_ENABLED);
+                /* For IEEE admin_ets_recommendation_tx_enable */
+                if (dp->admin_pfc_tx_enable)
+                        SET_FLAGS(admin_mib.ver_cfg_flags,
+                                  DCBX_PFC_CONFIG_TX_ENABLED);
+                else
+                        RESET_FLAGS(admin_mib.ver_cfg_flags,
+                                  DCBX_PFC_CONFIG_TX_ENABLED);
+
+                if (dp->admin_application_priority_tx_enable)
+                        SET_FLAGS(admin_mib.ver_cfg_flags,
+                                  DCBX_APP_CONFIG_TX_ENABLED);
+                else
+                        RESET_FLAGS(admin_mib.ver_cfg_flags,
+                                  DCBX_APP_CONFIG_TX_ENABLED);
+
+                if (dp->admin_ets_willing)
+                        SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_ETS_WILLING);
+                else
+                        RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_ETS_WILLING);
+                /* For IEEE admin_ets_reco_valid */
+                if (dp->admin_pfc_willing)
+                        SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_PFC_WILLING);
+                else
+                        RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_PFC_WILLING);
+
+                if (dp->admin_app_priority_willing)
+                        SET_FLAGS(admin_mib.ver_cfg_flags, DCBX_APP_WILLING);
+                else
+                        RESET_FLAGS(admin_mib.ver_cfg_flags, DCBX_APP_WILLING);
+
+                for (i = 0 ; i < DCBX_MAX_NUM_PG_BW_ENTRIES; i++) {
+                        DCBX_PG_BW_SET(af->ets.pg_bw_tbl, i,
+                                (u8)dp->admin_configuration_bw_precentage[i]);
+
+                        DP(NETIF_MSG_LINK, "pg_bw_tbl[%d] = %02x\n",
+                           i, DCBX_PG_BW_GET(af->ets.pg_bw_tbl, i));
+                }
+
+                for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) {
+                        DCBX_PRI_PG_SET(af->ets.pri_pg_tbl, i,
+                                        (u8)dp->admin_configuration_ets_pg[i]);
+
+                        DP(NETIF_MSG_LINK, "pri_pg_tbl[%d] = %02x\n",
+                           i, DCBX_PRI_PG_GET(af->ets.pri_pg_tbl, i));
+                }
+
+                /*For IEEE admin_recommendation_bw_precentage
+                 *For IEEE admin_recommendation_ets_pg */
+                af->pfc.pri_en_bitmap = (u8)dp->admin_pfc_bitmap;
+                for (i = 0; i < 4; i++) {
+                        if (dp->admin_priority_app_table[i].valid) {
+                                struct bnx2x_admin_priority_app_table *table =
+                                        dp->admin_priority_app_table;
+                                if ((ETH_TYPE_FCOE == table[i].app_id) &&
+                                   (TRAFFIC_TYPE_ETH == table[i].traffic_type))
+                                        traf_type = FCOE_APP_IDX;
+                                else if ((TCP_PORT_ISCSI == table[i].app_id) &&
+                                   (TRAFFIC_TYPE_PORT == table[i].traffic_type))
+                                        traf_type = ISCSI_APP_IDX;
+                                else
+                                        traf_type = other_traf_type++;
+
+                                af->app.app_pri_tbl[traf_type].app_id =
+                                        table[i].app_id;
+
+                                af->app.app_pri_tbl[traf_type].pri_bitmap =
+                                        (u8)(1 << table[i].priority);
+
+                                af->app.app_pri_tbl[traf_type].appBitfield =
+                                    (DCBX_APP_ENTRY_VALID);
+
+                                af->app.app_pri_tbl[traf_type].appBitfield |=
+                                   (TRAFFIC_TYPE_ETH == table[i].traffic_type) ?
+                                        DCBX_APP_SF_ETH_TYPE : DCBX_APP_SF_PORT;
+                        }
+                }
+
+                af->app.default_pri = (u8)dp->admin_default_priority;
+
+        } else if (BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE ==
+                                                dp->overwrite_settings)
+                dp->overwrite_settings = BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID;
+
+        /* Write the data. */
+        buff = (u32 *)&admin_mib;
+        for (i = 0; i < sizeof(struct lldp_admin_mib); i += 4, buff++)
+                REG_WR(bp, (offset + i), *buff);
+}
+
+void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on, u32 dcbx_enabled)
+{
+        if (CHIP_IS_E2(bp) && !CHIP_MODE_IS_4_PORT(bp)) {
+                bp->dcb_state = dcb_on;
+                bp->dcbx_enabled = dcbx_enabled;
+        } else {
+                bp->dcb_state = false;
+                bp->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
+        }
+        DP(NETIF_MSG_LINK, "DCB state [%s:%s]\n",
+           dcb_on ? "ON" : "OFF",
+           dcbx_enabled == BNX2X_DCBX_ENABLED_OFF ? "user-mode" :
+           dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_OFF ? "on-chip static" :
+           dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_ON ?
+           "on-chip with negotiation" : "invalid");
+}
+
+void bnx2x_dcbx_init_params(struct bnx2x *bp)
+{
+        bp->dcbx_config_params.admin_dcbx_version = 0x0; /* 0 - CEE; 1 - IEEE */
+        bp->dcbx_config_params.admin_ets_willing = 1;
+        bp->dcbx_config_params.admin_pfc_willing = 1;
+        bp->dcbx_config_params.overwrite_settings = 1;
+        bp->dcbx_config_params.admin_ets_enable = 1;
+        bp->dcbx_config_params.admin_pfc_enable = 1;
+        bp->dcbx_config_params.admin_tc_supported_tx_enable = 1;
+        bp->dcbx_config_params.admin_ets_configuration_tx_enable = 1;
+        bp->dcbx_config_params.admin_pfc_tx_enable = 1;
+        bp->dcbx_config_params.admin_application_priority_tx_enable = 1;
+        bp->dcbx_config_params.admin_ets_reco_valid = 1;
+        bp->dcbx_config_params.admin_app_priority_willing = 1;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[0] = 00;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[1] = 50;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[2] = 50;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[3] = 0;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[4] = 0;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[5] = 0;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[6] = 0;
+        bp->dcbx_config_params.admin_configuration_bw_precentage[7] = 0;
+        bp->dcbx_config_params.admin_configuration_ets_pg[0] = 1;
+        bp->dcbx_config_params.admin_configuration_ets_pg[1] = 0;
+        bp->dcbx_config_params.admin_configuration_ets_pg[2] = 0;
+        bp->dcbx_config_params.admin_configuration_ets_pg[3] = 2;
+        bp->dcbx_config_params.admin_configuration_ets_pg[4] = 0;
+        bp->dcbx_config_params.admin_configuration_ets_pg[5] = 0;
+        bp->dcbx_config_params.admin_configuration_ets_pg[6] = 0;
+        bp->dcbx_config_params.admin_configuration_ets_pg[7] = 0;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[0] = 0;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[1] = 1;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[2] = 2;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[3] = 0;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[4] = 7;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[5] = 5;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[6] = 6;
+        bp->dcbx_config_params.admin_recommendation_bw_precentage[7] = 7;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[0] = 0;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[1] = 1;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[2] = 2;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[3] = 3;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[4] = 4;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[5] = 5;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[6] = 6;
+        bp->dcbx_config_params.admin_recommendation_ets_pg[7] = 7;
+        bp->dcbx_config_params.admin_pfc_bitmap = 0x8; /* FCoE(3) enable */
+        bp->dcbx_config_params.admin_priority_app_table[0].valid = 1;
+        bp->dcbx_config_params.admin_priority_app_table[1].valid = 1;
+        bp->dcbx_config_params.admin_priority_app_table[2].valid = 0;
+        bp->dcbx_config_params.admin_priority_app_table[3].valid = 0;
+        bp->dcbx_config_params.admin_priority_app_table[0].priority = 3;
+        bp->dcbx_config_params.admin_priority_app_table[1].priority = 0;
+        bp->dcbx_config_params.admin_priority_app_table[2].priority = 0;
+        bp->dcbx_config_params.admin_priority_app_table[3].priority = 0;
+        bp->dcbx_config_params.admin_priority_app_table[0].traffic_type = 0;
+        bp->dcbx_config_params.admin_priority_app_table[1].traffic_type = 1;
+        bp->dcbx_config_params.admin_priority_app_table[2].traffic_type = 0;
+        bp->dcbx_config_params.admin_priority_app_table[3].traffic_type = 0;
+        bp->dcbx_config_params.admin_priority_app_table[0].app_id = 0x8906;
+        bp->dcbx_config_params.admin_priority_app_table[1].app_id = 3260;
+        bp->dcbx_config_params.admin_priority_app_table[2].app_id = 0;
+        bp->dcbx_config_params.admin_priority_app_table[3].app_id = 0;
+        bp->dcbx_config_params.admin_default_priority =
+                bp->dcbx_config_params.admin_priority_app_table[1].priority;
+}
+
+void bnx2x_dcbx_init(struct bnx2x *bp)
+{
+        u32 dcbx_lldp_params_offset = SHMEM_LLDP_DCBX_PARAMS_NONE;
+
+        if (bp->dcbx_enabled <= 0)
+                return;
+
+        /* validate:
+         * chip of good for dcbx version,
+         * dcb is wanted
+         * the function is pmf
+         * shmem2 contains DCBX support fields
+         */
+        DP(NETIF_MSG_LINK, "dcb_state %d bp->port.pmf %d\n",
+           bp->dcb_state, bp->port.pmf);
+
+        if (bp->dcb_state ==  BNX2X_DCB_STATE_ON && bp->port.pmf &&
+            SHMEM2_HAS(bp, dcbx_lldp_params_offset)) {
+                dcbx_lldp_params_offset =
+                        SHMEM2_RD(bp, dcbx_lldp_params_offset);
+
+                DP(NETIF_MSG_LINK, "dcbx_lldp_params_offset 0x%x\n",
+                   dcbx_lldp_params_offset);
+
+                if (SHMEM_LLDP_DCBX_PARAMS_NONE != dcbx_lldp_params_offset) {
+                        bnx2x_dcbx_lldp_updated_params(bp,
+                                                       dcbx_lldp_params_offset);
+
+                        bnx2x_dcbx_admin_mib_updated_params(bp,
+                                dcbx_lldp_params_offset);
+
+                        /* set default configuration BC has */
+                        bnx2x_dcbx_set_params(bp,
+                                              BNX2X_DCBX_STATE_NEG_RECEIVED);
+
+                        bnx2x_fw_command(bp,
+                                         DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG, 0);
+                }
+        }
+}
+
+void bnx2x_dcb_init_intmem_pfc(struct bnx2x *bp)
+{
+        struct priority_cos pricos[MAX_PFC_TRAFFIC_TYPES];
+        u32 i = 0, addr;
+        memset(pricos, 0, sizeof(pricos));
+        /* Default initialization */
+        for (i = 0; i < MAX_PFC_TRAFFIC_TYPES; i++)
+                pricos[i].priority = LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED;
+
+        /* Store per port struct to internal memory */
+        addr = BAR_XSTRORM_INTMEM +
+                        XSTORM_CMNG_PER_PORT_VARS_OFFSET(BP_PORT(bp)) +
+                        offsetof(struct cmng_struct_per_port,
+                                 traffic_type_to_priority_cos);
+        __storm_memset_struct(bp, addr, sizeof(pricos), (u32 *)pricos);
+
+
+        /* LLFC disabled.*/
+        REG_WR8(bp , BAR_XSTRORM_INTMEM +
+                    XSTORM_CMNG_PER_PORT_VARS_OFFSET(BP_PORT(bp)) +
+                    offsetof(struct cmng_struct_per_port, llfc_mode),
+                        LLFC_MODE_NONE);
+
+        /* DCBX disabled.*/
+        REG_WR8(bp , BAR_XSTRORM_INTMEM +
+                    XSTORM_CMNG_PER_PORT_VARS_OFFSET(BP_PORT(bp)) +
+                    offsetof(struct cmng_struct_per_port, dcb_enabled),
+                        DCB_DISABLED);
+}
+
+static void
+bnx2x_dcbx_print_cos_params(struct bnx2x *bp,
+                            struct flow_control_configuration *pfc_fw_cfg)
+{
+        u8 pri = 0;
+        u8 cos = 0;
+
+        DP(NETIF_MSG_LINK,
+           "pfc_fw_cfg->dcb_version %x\n", pfc_fw_cfg->dcb_version);
+        DP(NETIF_MSG_LINK,
+           "pdev->params.dcbx_port_params.pfc."
+           "priority_non_pauseable_mask %x\n",
+           bp->dcbx_port_params.pfc.priority_non_pauseable_mask);
+
+        for (cos = 0 ; cos < bp->dcbx_port_params.ets.num_of_cos ; cos++) {
+                DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
+                   "cos_params[%d].pri_bitmask %x\n", cos,
+                   bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask);
+
+                DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
+                   "cos_params[%d].bw_tbl %x\n", cos,
+                   bp->dcbx_port_params.ets.cos_params[cos].bw_tbl);
+
+                DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
+                   "cos_params[%d].strict %x\n", cos,
+                   bp->dcbx_port_params.ets.cos_params[cos].strict);
+
+                DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets."
+                   "cos_params[%d].pauseable %x\n", cos,
+                   bp->dcbx_port_params.ets.cos_params[cos].pauseable);
+        }
+
+        for (pri = 0; pri < LLFC_DRIVER_TRAFFIC_TYPE_MAX; pri++) {
+                DP(NETIF_MSG_LINK,
+                   "pfc_fw_cfg->traffic_type_to_priority_cos[%d]."
+                   "priority %x\n", pri,
+                   pfc_fw_cfg->traffic_type_to_priority_cos[pri].priority);
+
+                DP(NETIF_MSG_LINK,
+                   "pfc_fw_cfg->traffic_type_to_priority_cos[%d].cos %x\n",
+                   pri, pfc_fw_cfg->traffic_type_to_priority_cos[pri].cos);
+        }
+}
+
+/* fills help_data according to pg_info */
+static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
+                                            u32 *pg_pri_orginal_spread,
+                                            struct pg_help_data *help_data)
+{
+        bool pg_found  = false;
+        u32 i, traf_type, add_traf_type, add_pg;
+        u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+        struct pg_entry_help_data *data = help_data->data; /*shotcut*/
+
+        /* Set to invalid */
+        for (i = 0; i < LLFC_DRIVER_TRAFFIC_TYPE_MAX; i++)
+                data[i].pg = DCBX_ILLEGAL_PG;
+
+        for (add_traf_type = 0;
+             add_traf_type < LLFC_DRIVER_TRAFFIC_TYPE_MAX; add_traf_type++) {
+                pg_found = false;
+                if (ttp[add_traf_type] < MAX_PFC_PRIORITIES) {
+                        add_pg = (u8)pg_pri_orginal_spread[ttp[add_traf_type]];
+                        for (traf_type = 0;
+                             traf_type < LLFC_DRIVER_TRAFFIC_TYPE_MAX;
+                             traf_type++) {
+                                if (data[traf_type].pg == add_pg) {
+                                        if (!(data[traf_type].pg_priority &
+                                             (1 << ttp[add_traf_type])))
+                                                data[traf_type].
+                                                        num_of_dif_pri++;
+                                        data[traf_type].pg_priority |=
+                                                (1 << ttp[add_traf_type]);
+                                        pg_found = true;
+                                        break;
+                                }
+                        }
+                        if (false == pg_found) {
+                                data[help_data->num_of_pg].pg = add_pg;
+                                data[help_data->num_of_pg].pg_priority =
+                                                (1 << ttp[add_traf_type]);
+                                data[help_data->num_of_pg].num_of_dif_pri = 1;
+                                help_data->num_of_pg++;
+                        }
+                }
+                DP(NETIF_MSG_LINK,
+                   "add_traf_type %d pg_found %s num_of_pg %d\n",
+                   add_traf_type, (false == pg_found) ? "NO" : "YES",
+                   help_data->num_of_pg);
+        }
+}
+
+
+/*******************************************************************************
+ * Description: single priority group
+ *
+ * Return:
+ ******************************************************************************/
+static void bnx2x_dcbx_ets_disabled_entry_data(struct bnx2x *bp,
+                                               struct cos_help_data *cos_data,
+                                               u32 pri_join_mask)
+{
+        /* Only one priority than only one COS */
+        cos_data->data[0].pausable =
+                IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
+        cos_data->data[0].pri_join_mask = pri_join_mask;
+        cos_data->data[0].cos_bw = 100;
+        cos_data->num_of_cos = 1;
+}
+
+/*******************************************************************************
+ * Description: updating the cos bw
+ *
+ * Return:
+ ******************************************************************************/
+static inline void bnx2x_dcbx_add_to_cos_bw(struct bnx2x *bp,
+                                            struct cos_entry_help_data *data,
+                                            u8 pg_bw)
+{
+        if (data->cos_bw == DCBX_INVALID_COS_BW)
+                data->cos_bw = pg_bw;
+        else
+                data->cos_bw += pg_bw;
+}
+
+/*******************************************************************************
+ * Description: single priority group
+ *
+ * Return:
+ ******************************************************************************/
+static void bnx2x_dcbx_separate_pauseable_from_non(struct bnx2x *bp,
+                        struct cos_help_data *cos_data,
+                        u32 *pg_pri_orginal_spread,
+                        struct dcbx_ets_feature *ets)
+{
+        u32     pri_tested      = 0;
+        u8      i               = 0;
+        u8      entry           = 0;
+        u8      pg_entry        = 0;
+        u8      num_of_pri      = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
+
+        cos_data->data[0].pausable = true;
+        cos_data->data[1].pausable = false;
+        cos_data->data[0].pri_join_mask = cos_data->data[1].pri_join_mask = 0;
+
+        for (i = 0 ; i < num_of_pri ; i++) {
+                pri_tested = 1 << bp->dcbx_port_params.
+                                        app.traffic_type_priority[i];
+
+                if (pri_tested & DCBX_PFC_PRI_NON_PAUSE_MASK(bp)) {
+                        cos_data->data[1].pri_join_mask |= pri_tested;
+                        entry = 1;
+                } else {
+                        cos_data->data[0].pri_join_mask |= pri_tested;
+                        entry = 0;
+                }
+                pg_entry = (u8)pg_pri_orginal_spread[bp->dcbx_port_params.
+                                                app.traffic_type_priority[i]];
+                /* There can be only one strict pg */
+                if (pg_entry < DCBX_MAX_NUM_PG_BW_ENTRIES)
+                        bnx2x_dcbx_add_to_cos_bw(bp, &cos_data->data[entry],
+                                DCBX_PG_BW_GET(ets->pg_bw_tbl, pg_entry));
+                else
+                        /* If we join a group and one is strict
+                         * than the bw rulls */
+                        cos_data->data[entry].strict =
+                                                BNX2X_DCBX_COS_HIGH_STRICT;
+        }
+        if ((0 == cos_data->data[0].pri_join_mask) &&
+            (0 == cos_data->data[1].pri_join_mask))
+                BNX2X_ERR("dcbx error: Both groups must have priorities\n");
+}
+
+
+#ifndef POWER_OF_2
+#define POWER_OF_2(x)   ((0 != x) && (0 == (x & (x-1))))
+#endif
+
+static void bxn2x_dcbx_single_pg_to_cos_params(struct bnx2x *bp,
+                                              struct pg_help_data *pg_help_data,
+                                              struct cos_help_data *cos_data,
+                                              u32 pri_join_mask,
+                                              u8 num_of_dif_pri)
+{
+        u8 i = 0;
+        u32 pri_tested = 0;
+        u32 pri_mask_without_pri = 0;
+        u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+        /*debug*/
+        if (num_of_dif_pri == 1) {
+                bnx2x_dcbx_ets_disabled_entry_data(bp, cos_data, pri_join_mask);
+                return;
+        }
+        /* single priority group */
+        if (pg_help_data->data[0].pg < DCBX_MAX_NUM_PG_BW_ENTRIES) {
+                /* If there are both pauseable and non-pauseable priorities,
+                 * the pauseable priorities go to the first queue and
+                 * the non-pauseable priorities go to the second queue.
+                 */
+                if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask)) {
+                        /* Pauseable */
+                        cos_data->data[0].pausable = true;
+                        /* Non pauseable.*/
+                        cos_data->data[1].pausable = false;
+
+                        if (2 == num_of_dif_pri) {
+                                cos_data->data[0].cos_bw = 50;
+                                cos_data->data[1].cos_bw = 50;
+                        }
+
+                        if (3 == num_of_dif_pri) {
+                                if (POWER_OF_2(DCBX_PFC_PRI_GET_PAUSE(bp,
+                                                        pri_join_mask))) {
+                                        cos_data->data[0].cos_bw = 33;
+                                        cos_data->data[1].cos_bw = 67;
+                                } else {
+                                        cos_data->data[0].cos_bw = 67;
+                                        cos_data->data[1].cos_bw = 33;
+                                }
+                        }
+
+                } else if (IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask)) {
+                        /* If there are only pauseable priorities,
+                         * then one/two priorities go to the first queue
+                         * and one priority goes to the second queue.
+                         */
+                        if (2 == num_of_dif_pri) {
+                                cos_data->data[0].cos_bw = 50;
+                                cos_data->data[1].cos_bw = 50;
+                        } else {
+                                cos_data->data[0].cos_bw = 67;
+                                cos_data->data[1].cos_bw = 33;
+                        }
+                        cos_data->data[1].pausable = true;
+                        cos_data->data[0].pausable = true;
+                        /* All priorities except FCOE */
+                        cos_data->data[0].pri_join_mask = (pri_join_mask &
+                                ((u8)~(1 << ttp[LLFC_TRAFFIC_TYPE_FCOE])));
+                        /* Only FCOE priority.*/
+                        cos_data->data[1].pri_join_mask =
+                                (1 << ttp[LLFC_TRAFFIC_TYPE_FCOE]);
+                } else
+                        /* If there are only non-pauseable priorities,
+                         * they will all go to the same queue.
+                         */
+                        bnx2x_dcbx_ets_disabled_entry_data(bp,
+                                                cos_data, pri_join_mask);
+        } else {
+                /* priority group which is not BW limited (PG#15):*/
+                if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask)) {
+                        /* If there are both pauseable and non-pauseable
+                         * priorities, the pauseable priorities go to the first
+                         * queue and the non-pauseable priorities
+                         * go to the second queue.
+                         */
+                        if (DCBX_PFC_PRI_GET_PAUSE(bp, pri_join_mask) >
+                            DCBX_PFC_PRI_GET_NON_PAUSE(bp, pri_join_mask)) {
+                                cos_data->data[0].strict =
+                                        BNX2X_DCBX_COS_HIGH_STRICT;
+                                cos_data->data[1].strict =
+                                        BNX2X_DCBX_COS_LOW_STRICT;
+                        } else {
+                                cos_data->data[0].strict =
+                                        BNX2X_DCBX_COS_LOW_STRICT;
+                                cos_data->data[1].strict =
+                                        BNX2X_DCBX_COS_HIGH_STRICT;
+                        }
+                        /* Pauseable */
+                        cos_data->data[0].pausable = true;
+                        /* Non pause-able.*/
+                        cos_data->data[1].pausable = false;
+                } else {
+                        /* If there are only pauseable priorities or
+                         * only non-pauseable,* the lower priorities go
+                         * to the first queue and the higherpriorities go
+                         * to the second queue.
+                         */
+                        cos_data->data[0].pausable =
+                                cos_data->data[1].pausable =
+                                IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
+
+                        for (i = 0 ; i < LLFC_DRIVER_TRAFFIC_TYPE_MAX; i++) {
+                                pri_tested = 1 << bp->dcbx_port_params.
+                                        app.traffic_type_priority[i];
+                                /* Remove priority tested */
+                                pri_mask_without_pri =
+                                        (pri_join_mask & ((u8)(~pri_tested)));
+                                if (pri_mask_without_pri < pri_tested)
+                                        break;
+                        }
+
+                        if (i == LLFC_DRIVER_TRAFFIC_TYPE_MAX)
+                                BNX2X_ERR("Invalid value for pri_join_mask -"
+                                          " could not find a priority\n");
+
+                        cos_data->data[0].pri_join_mask = pri_mask_without_pri;
+                        cos_data->data[1].pri_join_mask = pri_tested;
+                        /* Both queues are strict priority,
+                         * and that with the highest priority
+                         * gets the highest strict priority in the arbiter.
+                         */
+                        cos_data->data[0].strict = BNX2X_DCBX_COS_LOW_STRICT;
+                        cos_data->data[1].strict = BNX2X_DCBX_COS_HIGH_STRICT;
+                }
+        }
+}
+
+static void bnx2x_dcbx_two_pg_to_cos_params(
+                            struct bnx2x                *bp,
+                            struct  pg_help_data        *pg_help_data,
+                            struct dcbx_ets_feature     *ets,
+                            struct cos_help_data        *cos_data,
+                            u32                 *pg_pri_orginal_spread,
+                            u32                         pri_join_mask,
+                            u8                          num_of_dif_pri)
+{
+        u8 i = 0;
+        u8 pg[E2_NUM_OF_COS] = {0};
+
+        /* If there are both pauseable and non-pauseable priorities,
+         * the pauseable priorities go to the first queue and
+         * the non-pauseable priorities go to the second queue.
+         */
+        if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask)) {
+                if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp,
+                                         pg_help_data->data[0].pg_priority) ||
+                    IS_DCBX_PFC_PRI_MIX_PAUSE(bp,
+                                         pg_help_data->data[1].pg_priority)) {
+                        /* If one PG contains both pauseable and
+                         * non-pauseable priorities then ETS is disabled.
+                         */
+                        bnx2x_dcbx_separate_pauseable_from_non(bp, cos_data,
+                                        pg_pri_orginal_spread, ets);
+                        bp->dcbx_port_params.ets.enabled = false;
+                        return;
+                }
+
+                /* Pauseable */
+                cos_data->data[0].pausable = true;
+                /* Non pauseable. */
+                cos_data->data[1].pausable = false;
+                if (IS_DCBX_PFC_PRI_ONLY_PAUSE(bp,
+                                pg_help_data->data[0].pg_priority)) {
+                        /* 0 is pauseable */
+                        cos_data->data[0].pri_join_mask =
+                                pg_help_data->data[0].pg_priority;
+                        pg[0] = pg_help_data->data[0].pg;
+                        cos_data->data[1].pri_join_mask =
+                                pg_help_data->data[1].pg_priority;
+                        pg[1] = pg_help_data->data[1].pg;
+                } else {/* 1 is pauseable */
+                        cos_data->data[0].pri_join_mask =
+                                pg_help_data->data[1].pg_priority;
+                        pg[0] = pg_help_data->data[1].pg;
+                        cos_data->data[1].pri_join_mask =
+                                pg_help_data->data[0].pg_priority;
+                        pg[1] = pg_help_data->data[0].pg;
+                }
+        } else {
+                /* If there are only pauseable priorities or
+                 * only non-pauseable, each PG goes to a queue.
+                 */
+                cos_data->data[0].pausable = cos_data->data[1].pausable =
+                        IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
+                cos_data->data[0].pri_join_mask =
+                        pg_help_data->data[0].pg_priority;
+                pg[0] = pg_help_data->data[0].pg;
+                cos_data->data[1].pri_join_mask =
+                        pg_help_data->data[1].pg_priority;
+                pg[1] = pg_help_data->data[1].pg;
+        }
+
+        /* There can be only one strict pg */
+        for (i = 0 ; i < E2_NUM_OF_COS; i++) {
+                if (pg[i] < DCBX_MAX_NUM_PG_BW_ENTRIES)
+                        cos_data->data[i].cos_bw =
+                                DCBX_PG_BW_GET(ets->pg_bw_tbl, pg[i]);
+                else
+                        cos_data->data[i].strict = BNX2X_DCBX_COS_HIGH_STRICT;
+        }
+}
+
+/*******************************************************************************
+ * Description: Still
+ *
+ * Return:
+ ******************************************************************************/
+static void bnx2x_dcbx_three_pg_to_cos_params(
+                              struct bnx2x              *bp,
+                              struct pg_help_data       *pg_help_data,
+                              struct dcbx_ets_feature   *ets,
+                              struct cos_help_data      *cos_data,
+                              u32                       *pg_pri_orginal_spread,
+                              u32                       pri_join_mask,
+                              u8                        num_of_dif_pri)
+{
+        u8 i = 0;
+        u32 pri_tested = 0;
+        u8 entry = 0;
+        u8 pg_entry = 0;
+        bool b_found_strict = false;
+        u8 num_of_pri = LLFC_DRIVER_TRAFFIC_TYPE_MAX;
+
+        cos_data->data[0].pri_join_mask = cos_data->data[1].pri_join_mask = 0;
+        /* If there are both pauseable and non-pauseable priorities,
+         * the pauseable priorities go to the first queue and the
+         * non-pauseable priorities go to the second queue.
+         */
+        if (IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pri_join_mask))
+                bnx2x_dcbx_separate_pauseable_from_non(bp,
+                                cos_data, pg_pri_orginal_spread, ets);
+        else {
+                /* If two BW-limited PG-s were combined to one queue,
+                 * the BW is their sum.
+                 *
+                 * If there are only pauseable priorities or only non-pauseable,
+                 * and there are both BW-limited and non-BW-limited PG-s,
+                 * the BW-limited PG/s go to one queue and the non-BW-limited
+                 * PG/s go to the second queue.
+                 *
+                 * If there are only pauseable priorities or only non-pauseable
+                 * and all are BW limited, then two priorities go to the first
+                 * queue and one priority goes to the second queue.
+                 *
+                 * We will join this two cases:
+                 * if one is BW limited it will go to the secoend queue
+                 * otherwise the last priority will get it
+                 */
+
+                cos_data->data[0].pausable = cos_data->data[1].pausable =
+                        IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pri_join_mask);
+
+                for (i = 0 ; i < num_of_pri; i++) {
+                        pri_tested = 1 << bp->dcbx_port_params.
+                                app.traffic_type_priority[i];
+                        pg_entry = (u8)pg_pri_orginal_spread[bp->
+                                dcbx_port_params.app.traffic_type_priority[i]];
+
+                        if (pg_entry < DCBX_MAX_NUM_PG_BW_ENTRIES) {
+                                entry = 0;
+
+                                if (i == (num_of_pri-1) &&
+                                    false == b_found_strict)
+                                        /* last entry will be handled separately
+                                         * If no priority is strict than last
+                                         * enty goes to last queue.*/
+                                        entry = 1;
+                                cos_data->data[entry].pri_join_mask |=
+                                                                pri_tested;
+                                bnx2x_dcbx_add_to_cos_bw(bp,
+                                        &cos_data->data[entry],
+                                        DCBX_PG_BW_GET(ets->pg_bw_tbl,
+                                                       pg_entry));
+                        } else {
+                                b_found_strict = true;
+                                cos_data->data[1].pri_join_mask |= pri_tested;
+                                /* If we join a group and one is strict
+                                 * than the bw rulls */
+                                cos_data->data[1].strict =
+                                        BNX2X_DCBX_COS_HIGH_STRICT;
+                        }
+                }
+        }
+}
+
+
+static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
+                                       struct pg_help_data *help_data,
+                                       struct dcbx_ets_feature *ets,
+                                       u32 *pg_pri_orginal_spread)
+{
+        struct cos_help_data         cos_data ;
+        u8                    i                           = 0;
+        u32                   pri_join_mask               = 0;
+        u8                    num_of_dif_pri              = 0;
+
+        memset(&cos_data, 0, sizeof(cos_data));
+        /* Validate the pg value */
+        for (i = 0; i < help_data->num_of_pg ; i++) {
+                if (DCBX_STRICT_PRIORITY != help_data->data[i].pg &&
+                    DCBX_MAX_NUM_PG_BW_ENTRIES <= help_data->data[i].pg)
+                        BNX2X_ERR("Invalid pg[%d] data %x\n", i,
+                                  help_data->data[i].pg);
+                pri_join_mask   |=  help_data->data[i].pg_priority;
+                num_of_dif_pri  += help_data->data[i].num_of_dif_pri;
+        }
+
+        /* default settings */
+        cos_data.num_of_cos = 2;
+        for (i = 0; i < E2_NUM_OF_COS ; i++) {
+                cos_data.data[i].pri_join_mask    = pri_join_mask;
+                cos_data.data[i].pausable         = false;
+                cos_data.data[i].strict           = BNX2X_DCBX_COS_NOT_STRICT;
+                cos_data.data[i].cos_bw           = DCBX_INVALID_COS_BW;
+        }
+
+        switch (help_data->num_of_pg) {
+        case 1:
+
+                bxn2x_dcbx_single_pg_to_cos_params(
+                                               bp,
+                                               help_data,
+                                               &cos_data,
+                                               pri_join_mask,
+                                               num_of_dif_pri);
+                break;
+        case 2:
+                bnx2x_dcbx_two_pg_to_cos_params(
+                                            bp,
+                                            help_data,
+                                            ets,
+                                            &cos_data,
+                                            pg_pri_orginal_spread,
+                                            pri_join_mask,
+                                            num_of_dif_pri);
+                break;
+
+        case 3:
+                bnx2x_dcbx_three_pg_to_cos_params(
+                                              bp,
+                                              help_data,
+                                              ets,
+                                              &cos_data,
+                                              pg_pri_orginal_spread,
+                                              pri_join_mask,
+                                              num_of_dif_pri);
+
+                break;
+        default:
+                BNX2X_ERR("Wrong pg_help_data.num_of_pg\n");
+                bnx2x_dcbx_ets_disabled_entry_data(bp,
+                                                   &cos_data, pri_join_mask);
+        }
+
+        for (i = 0; i < cos_data.num_of_cos ; i++) {
+                struct bnx2x_dcbx_cos_params *params =
+                        &bp->dcbx_port_params.ets.cos_params[i];
+
+                params->pauseable = cos_data.data[i].pausable;
+                params->strict = cos_data.data[i].strict;
+                params->bw_tbl = cos_data.data[i].cos_bw;
+                if (params->pauseable) {
+                        params->pri_bitmask =
+                        DCBX_PFC_PRI_GET_PAUSE(bp,
+                                        cos_data.data[i].pri_join_mask);
+                        DP(NETIF_MSG_LINK, "COS %d PAUSABLE prijoinmask 0x%x\n",
+                                  i, cos_data.data[i].pri_join_mask);
+                } else {
+                        params->pri_bitmask =
+                        DCBX_PFC_PRI_GET_NON_PAUSE(bp,
+                                        cos_data.data[i].pri_join_mask);
+                        DP(NETIF_MSG_LINK, "COS %d NONPAUSABLE prijoinmask "
+                                          "0x%x\n",
+                                  i, cos_data.data[i].pri_join_mask);
+                }
+        }
+
+        bp->dcbx_port_params.ets.num_of_cos = cos_data.num_of_cos ;
+}
+
+static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
+                                u32 *set_configuration_ets_pg,
+                                u32 *pri_pg_tbl)
+{
+        int i;
+
+        for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) {
+                set_configuration_ets_pg[i] = DCBX_PRI_PG_GET(pri_pg_tbl, i);
+
+                DP(NETIF_MSG_LINK, "set_configuration_ets_pg[%d] = 0x%x\n",
+                   i, set_configuration_ets_pg[i]);
+        }
+}
+
+/*******************************************************************************
+ * Description: Fill pfc_config struct that will be sent in DCBX start ramrod
+ *
+ * Return:
+ ******************************************************************************/
+static void bnx2x_pfc_fw_struct_e2(struct bnx2x *bp)
+{
+        struct flow_control_configuration   *pfc_fw_cfg = NULL;
+        u16 pri_bit = 0;
+        u8 cos = 0, pri = 0;
+        struct priority_cos *tt2cos;
+        u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
+
+        pfc_fw_cfg = (struct flow_control_configuration *)
+                                        bnx2x_sp(bp, pfc_config);
+        memset(pfc_fw_cfg, 0, sizeof(struct flow_control_configuration));
+
+        /*shortcut*/
+        tt2cos = pfc_fw_cfg->traffic_type_to_priority_cos;
+
+        /* Fw version should be incremented each update */
+        pfc_fw_cfg->dcb_version = ++bp->dcb_version;
+        pfc_fw_cfg->dcb_enabled = DCB_ENABLED;
+
+        /* Default initialization */
+        for (pri = 0; pri < MAX_PFC_TRAFFIC_TYPES ; pri++) {
+                tt2cos[pri].priority = LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED;
+                tt2cos[pri].cos = 0;
+        }
+
+        /* Fill priority parameters */
+        for (pri = 0; pri < LLFC_DRIVER_TRAFFIC_TYPE_MAX; pri++) {
+                tt2cos[pri].priority = ttp[pri];
+                pri_bit = 1 << tt2cos[pri].priority;
+
+                /* Fill COS parameters based on COS calculated to
+                 * make it more generally for future use */
+                for (cos = 0; cos < bp->dcbx_port_params.ets.num_of_cos; cos++)
+                        if (bp->dcbx_port_params.ets.cos_params[cos].
+                                                pri_bitmask & pri_bit)
+                                        tt2cos[pri].cos = cos;
+        }
+        bnx2x_dcbx_print_cos_params(bp, pfc_fw_cfg);
+}
+/* DCB netlink */
+#ifdef BCM_DCB
+#include <linux/dcbnl.h>
+
+#define BNX2X_DCBX_CAPS         (DCB_CAP_DCBX_LLD_MANAGED | \
+                                DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_STATIC)
+
+static inline bool bnx2x_dcbnl_set_valid(struct bnx2x *bp)
+{
+        /* validate dcbnl call that may change HW state:
+         * DCB is on and DCBX mode was SUCCESSFULLY set by the user.
+         */
+        return bp->dcb_state && bp->dcbx_mode_uset;
+}
+
+static u8 bnx2x_dcbnl_get_state(struct net_device *netdev)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "state = %d\n", bp->dcb_state);
+        return bp->dcb_state;
+}
+
+static u8 bnx2x_dcbnl_set_state(struct net_device *netdev, u8 state)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "state = %s\n", state ? "on" : "off");
+
+        bnx2x_dcbx_set_state(bp, (state ? true : false), bp->dcbx_enabled);
+        return 0;
+}
+
+static void bnx2x_dcbnl_get_perm_hw_addr(struct net_device *netdev,
+                                         u8 *perm_addr)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "GET-PERM-ADDR\n");
+
+        /* first the HW mac address */
+        memcpy(perm_addr, netdev->dev_addr, netdev->addr_len);
+
+#ifdef BCM_CNIC
+        /* second SAN address */
+        memcpy(perm_addr+netdev->addr_len, bp->fip_mac, netdev->addr_len);
+#endif
+}
+
+static void bnx2x_dcbnl_set_pg_tccfg_tx(struct net_device *netdev, int prio,
+                                        u8 prio_type, u8 pgid, u8 bw_pct,
+                                        u8 up_map)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+
+        DP(NETIF_MSG_LINK, "prio[%d] = %d\n", prio, pgid);
+        if (!bnx2x_dcbnl_set_valid(bp) || prio >= DCBX_MAX_NUM_PRI_PG_ENTRIES)
+                return;
+
+        /**
+         * bw_pct ingnored -    band-width percentage devision between user
+         *                      priorities within the same group is not
+         *                      standard and hence not supported
+         *
+         * prio_type igonred -  priority levels within the same group are not
+         *                      standard and hence are not supported. According
+         *                      to the standard pgid 15 is dedicated to strict
+         *                      prioirty traffic (on the port level).
+         *
+         * up_map ignored
+         */
+
+        bp->dcbx_config_params.admin_configuration_ets_pg[prio] = pgid;
+        bp->dcbx_config_params.admin_ets_configuration_tx_enable = 1;
+}
+
+static void bnx2x_dcbnl_set_pg_bwgcfg_tx(struct net_device *netdev,
+                                         int pgid, u8 bw_pct)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "pgid[%d] = %d\n", pgid, bw_pct);
+
+        if (!bnx2x_dcbnl_set_valid(bp) || pgid >= DCBX_MAX_NUM_PG_BW_ENTRIES)
+                return;
+
+        bp->dcbx_config_params.admin_configuration_bw_precentage[pgid] = bw_pct;
+        bp->dcbx_config_params.admin_ets_configuration_tx_enable = 1;
+}
+
+static void bnx2x_dcbnl_set_pg_tccfg_rx(struct net_device *netdev, int prio,
+                                        u8 prio_type, u8 pgid, u8 bw_pct,
+                                        u8 up_map)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "Nothing to set; No RX support\n");
+}
+
+static void bnx2x_dcbnl_set_pg_bwgcfg_rx(struct net_device *netdev,
+                                         int pgid, u8 bw_pct)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "Nothing to set; No RX support\n");
+}
+
+static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio,
+                                        u8 *prio_type, u8 *pgid, u8 *bw_pct,
+                                        u8 *up_map)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "prio = %d\n", prio);
+
+        /**
+         * bw_pct ingnored -    band-width percentage devision between user
+         *                      priorities within the same group is not
+         *                      standard and hence not supported
+         *
+         * prio_type igonred -  priority levels within the same group are not
+         *                      standard and hence are not supported. According
+         *                      to the standard pgid 15 is dedicated to strict
+         *                      prioirty traffic (on the port level).
+         *
+         * up_map ignored
+         */
+        *up_map = *bw_pct = *prio_type = *pgid = 0;
+
+        if (!bp->dcb_state || prio >= DCBX_MAX_NUM_PRI_PG_ENTRIES)
+                return;
+
+        *pgid = DCBX_PRI_PG_GET(bp->dcbx_local_feat.ets.pri_pg_tbl, prio);
+}
+
+static void bnx2x_dcbnl_get_pg_bwgcfg_tx(struct net_device *netdev,
+                                         int pgid, u8 *bw_pct)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "pgid = %d\n", pgid);
+
+        *bw_pct = 0;
+
+        if (!bp->dcb_state || pgid >= DCBX_MAX_NUM_PG_BW_ENTRIES)
+                return;
+
+        *bw_pct = DCBX_PG_BW_GET(bp->dcbx_local_feat.ets.pg_bw_tbl, pgid);
+}
+
+static void bnx2x_dcbnl_get_pg_tccfg_rx(struct net_device *netdev, int prio,
+                                        u8 *prio_type, u8 *pgid, u8 *bw_pct,
+                                        u8 *up_map)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "Nothing to get; No RX support\n");
+
+        *prio_type = *pgid = *bw_pct = *up_map = 0;
+}
+
+static void bnx2x_dcbnl_get_pg_bwgcfg_rx(struct net_device *netdev,
+                                         int pgid, u8 *bw_pct)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "Nothing to get; No RX support\n");
+
+        *bw_pct = 0;
+}
+
+static void bnx2x_dcbnl_set_pfc_cfg(struct net_device *netdev, int prio,
+                                    u8 setting)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "prio[%d] = %d\n", prio, setting);
+
+        if (!bnx2x_dcbnl_set_valid(bp) || prio >= MAX_PFC_PRIORITIES)
+                return;
+
+        bp->dcbx_config_params.admin_pfc_bitmap |= ((setting ? 1 : 0) << prio);
+
+        if (setting)
+                bp->dcbx_config_params.admin_pfc_tx_enable = 1;
+}
+
+static void bnx2x_dcbnl_get_pfc_cfg(struct net_device *netdev, int prio,
+                                    u8 *setting)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "prio = %d\n", prio);
+
+        *setting = 0;
+
+        if (!bp->dcb_state || prio >= MAX_PFC_PRIORITIES)
+                return;
+
+        *setting = (bp->dcbx_local_feat.pfc.pri_en_bitmap >> prio) & 0x1;
+}
+
+static u8 bnx2x_dcbnl_set_all(struct net_device *netdev)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        int rc = 0;
+
+        DP(NETIF_MSG_LINK, "SET-ALL\n");
+
+        if (!bnx2x_dcbnl_set_valid(bp))
+                return 1;
+
+        if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
+                netdev_err(bp->dev, "Handling parity error recovery. "
+                                "Try again later\n");
+                return 1;
+        }
+        if (netif_running(bp->dev)) {
+                bnx2x_nic_unload(bp, UNLOAD_NORMAL);
+                rc = bnx2x_nic_load(bp, LOAD_NORMAL);
+        }
+        DP(NETIF_MSG_LINK, "set_dcbx_params done (%d)\n", rc);
+        if (rc)
+                return 1;
+
+        return 0;
+}
+
+static u8 bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        u8 rval = 0;
+
+        if (bp->dcb_state) {
+                switch (capid) {
+                case DCB_CAP_ATTR_PG:
+                        *cap = true;
+                        break;
+                case DCB_CAP_ATTR_PFC:
+                        *cap = true;
+                        break;
+                case DCB_CAP_ATTR_UP2TC:
+                        *cap = false;
+                        break;
+                case DCB_CAP_ATTR_PG_TCS:
+                        *cap = 0x80;    /* 8 priorities for PGs */
+                        break;
+                case DCB_CAP_ATTR_PFC_TCS:
+                        *cap = 0x80;    /* 8 priorities for PFC */
+                        break;
+                case DCB_CAP_ATTR_GSP:
+                        *cap = true;
+                        break;
+                case DCB_CAP_ATTR_BCN:
+                        *cap = false;
+                        break;
+                case DCB_CAP_ATTR_DCBX:
+                        *cap = BNX2X_DCBX_CAPS;
+                default:
+                        rval = -EINVAL;
+                        break;
+                }
+        } else
+                rval = -EINVAL;
+
+        DP(NETIF_MSG_LINK, "capid %d:%x\n", capid, *cap);
+        return rval;
+}
+
+static u8 bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid, u8 *num)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        u8 rval = 0;
+
+        DP(NETIF_MSG_LINK, "tcid %d\n", tcid);
+
+        if (bp->dcb_state) {
+                switch (tcid) {
+                case DCB_NUMTCS_ATTR_PG:
+                        *num = E2_NUM_OF_COS;
+                        break;
+                case DCB_NUMTCS_ATTR_PFC:
+                        *num = E2_NUM_OF_COS;
+                        break;
+                default:
+                        rval = -EINVAL;
+                        break;
+                }
+        } else
+                rval = -EINVAL;
+
+        return rval;
+}
+
+static u8 bnx2x_dcbnl_set_numtcs(struct net_device *netdev, int tcid, u8 num)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "num tcs = %d; Not supported\n", num);
+        return -EINVAL;
+}
+
+static u8  bnx2x_dcbnl_get_pfc_state(struct net_device *netdev)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "state = %d\n", bp->dcbx_local_feat.pfc.enabled);
+
+        if (!bp->dcb_state)
+                return 0;
+
+        return bp->dcbx_local_feat.pfc.enabled;
+}
+
+static void bnx2x_dcbnl_set_pfc_state(struct net_device *netdev, u8 state)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "state = %s\n", state ? "on" : "off");
+
+        if (!bnx2x_dcbnl_set_valid(bp))
+                return;
+
+        bp->dcbx_config_params.admin_pfc_tx_enable =
+        bp->dcbx_config_params.admin_pfc_enable = (state ? 1 : 0);
+}
+
+static bool bnx2x_app_is_equal(struct dcbx_app_priority_entry *app_ent,
+                               u8 idtype, u16 idval)
+{
+        if (!(app_ent->appBitfield & DCBX_APP_ENTRY_VALID))
+                return false;
+
+        switch (idtype) {
+        case DCB_APP_IDTYPE_ETHTYPE:
+                if ((app_ent->appBitfield & DCBX_APP_ENTRY_SF_MASK) !=
+                        DCBX_APP_SF_ETH_TYPE)
+                        return false;
+                break;
+        case DCB_APP_IDTYPE_PORTNUM:
+                if ((app_ent->appBitfield & DCBX_APP_ENTRY_SF_MASK) !=
+                        DCBX_APP_SF_PORT)
+                        return false;
+                break;
+        default:
+                return false;
+        }
+        if (app_ent->app_id != idval)
+                return false;
+
+        return true;
+}
+
+static void bnx2x_admin_app_set_ent(
+        struct bnx2x_admin_priority_app_table *app_ent,
+        u8 idtype, u16 idval, u8 up)
+{
+        app_ent->valid = 1;
+
+        switch (idtype) {
+        case DCB_APP_IDTYPE_ETHTYPE:
+                app_ent->traffic_type = TRAFFIC_TYPE_ETH;
+                break;
+        case DCB_APP_IDTYPE_PORTNUM:
+                app_ent->traffic_type = TRAFFIC_TYPE_PORT;
+                break;
+        default:
+                break; /* never gets here */
+        }
+        app_ent->app_id = idval;
+        app_ent->priority = up;
+}
+
+static bool bnx2x_admin_app_is_equal(
+        struct bnx2x_admin_priority_app_table *app_ent,
+        u8 idtype, u16 idval)
+{
+        if (!app_ent->valid)
+                return false;
+
+        switch (idtype) {
+        case DCB_APP_IDTYPE_ETHTYPE:
+                if (app_ent->traffic_type != TRAFFIC_TYPE_ETH)
+                        return false;
+                break;
+        case DCB_APP_IDTYPE_PORTNUM:
+                if (app_ent->traffic_type != TRAFFIC_TYPE_PORT)
+                        return false;
+                break;
+        default:
+                return false;
+        }
+        if (app_ent->app_id != idval)
+                return false;
+
+        return true;
+}
+
+static int bnx2x_set_admin_app_up(struct bnx2x *bp, u8 idtype, u16 idval, u8 up)
+{
+        int i, ff;
+
+        /* iterate over the app entries looking for idtype and idval */
+        for (i = 0, ff = -1; i < 4; i++) {
+                struct bnx2x_admin_priority_app_table *app_ent =
+                        &bp->dcbx_config_params.admin_priority_app_table[i];
+                if (bnx2x_admin_app_is_equal(app_ent, idtype, idval))
+                        break;
+
+                if (ff < 0 && !app_ent->valid)
+                        ff = i;
+        }
+        if (i < 4)
+                /* if found overwrite up */
+                bp->dcbx_config_params.
+                        admin_priority_app_table[i].priority = up;
+        else if (ff >= 0)
+                /* not found use first-free */
+                bnx2x_admin_app_set_ent(
+                        &bp->dcbx_config_params.admin_priority_app_table[ff],
+                        idtype, idval, up);
+        else
+                /* app table is full */
+                return -EBUSY;
+
+        /* up configured, if not 0 make sure feature is enabled */
+        if (up)
+                bp->dcbx_config_params.admin_application_priority_tx_enable = 1;
+
+        return 0;
+}
+
+static u8 bnx2x_dcbnl_set_app_up(struct net_device *netdev, u8 idtype,
+                                 u16 idval, u8 up)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+
+        DP(NETIF_MSG_LINK, "app_type %d, app_id %x, prio bitmap %d\n",
+           idtype, idval, up);
+
+        if (!bnx2x_dcbnl_set_valid(bp))
+                return -EINVAL;
+
+        /* verify idtype */
+        switch (idtype) {
+        case DCB_APP_IDTYPE_ETHTYPE:
+        case DCB_APP_IDTYPE_PORTNUM:
+                break;
+        default:
+                return -EINVAL;
+        }
+        return bnx2x_set_admin_app_up(bp, idtype, idval, up);
+}
+
+static u8 bnx2x_dcbnl_get_app_up(struct net_device *netdev, u8 idtype,
+                                 u16 idval)
+{
+        int i;
+        u8 up = 0;
+
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "app_type %d, app_id 0x%x\n", idtype, idval);
+
+        /* iterate over the app entries looking for idtype and idval */
+        for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++)
+                if (bnx2x_app_is_equal(&bp->dcbx_local_feat.app.app_pri_tbl[i],
+                                       idtype, idval))
+                        break;
+
+        if (i < DCBX_MAX_APP_PROTOCOL)
+                /* if found return up */
+                up = bp->dcbx_local_feat.app.app_pri_tbl[i].pri_bitmap;
+        else
+                DP(NETIF_MSG_LINK, "app not found\n");
+
+        return up;
+}
+
+static u8 bnx2x_dcbnl_get_dcbx(struct net_device *netdev)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        u8 state;
+
+        state = DCB_CAP_DCBX_LLD_MANAGED | DCB_CAP_DCBX_VER_CEE;
+
+        if (bp->dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_OFF)
+                state |= DCB_CAP_DCBX_STATIC;
+
+        return state;
+}
+
+static u8 bnx2x_dcbnl_set_dcbx(struct net_device *netdev, u8 state)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        DP(NETIF_MSG_LINK, "state = %02x\n", state);
+
+        /* set dcbx mode */
+
+        if ((state & BNX2X_DCBX_CAPS) != state) {
+                BNX2X_ERR("Requested DCBX mode %x is beyond advertised "
+                          "capabilities\n", state);
+                return 1;
+        }
+
+        if (bp->dcb_state != BNX2X_DCB_STATE_ON) {
+                BNX2X_ERR("DCB turned off, DCBX configuration is invalid\n");
+                return 1;
+        }
+
+        if (state & DCB_CAP_DCBX_STATIC)
+                bp->dcbx_enabled = BNX2X_DCBX_ENABLED_ON_NEG_OFF;
+        else
+                bp->dcbx_enabled = BNX2X_DCBX_ENABLED_ON_NEG_ON;
+
+        bp->dcbx_mode_uset = true;
+        return 0;
+}
+
+
+static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
+                                  u8 *flags)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        u8 rval = 0;
+
+        DP(NETIF_MSG_LINK, "featid %d\n", featid);
+
+        if (bp->dcb_state) {
+                *flags = 0;
+                switch (featid) {
+                case DCB_FEATCFG_ATTR_PG:
+                        if (bp->dcbx_local_feat.ets.enabled)
+                                *flags |= DCB_FEATCFG_ENABLE;
+                        if (bp->dcbx_error & DCBX_LOCAL_ETS_ERROR)
+                                *flags |= DCB_FEATCFG_ERROR;
+                        break;
+                case DCB_FEATCFG_ATTR_PFC:
+                        if (bp->dcbx_local_feat.pfc.enabled)
+                                *flags |= DCB_FEATCFG_ENABLE;
+                        if (bp->dcbx_error & (DCBX_LOCAL_PFC_ERROR |
+                            DCBX_LOCAL_PFC_MISMATCH))
+                                *flags |= DCB_FEATCFG_ERROR;
+                        break;
+                case DCB_FEATCFG_ATTR_APP:
+                        if (bp->dcbx_local_feat.app.enabled)
+                                *flags |= DCB_FEATCFG_ENABLE;
+                        if (bp->dcbx_error & (DCBX_LOCAL_APP_ERROR |
+                            DCBX_LOCAL_APP_MISMATCH))
+                                *flags |= DCB_FEATCFG_ERROR;
+                        break;
+                default:
+                        rval = -EINVAL;
+                        break;
+                }
+        } else
+                rval = -EINVAL;
+
+        return rval;
+}
+
+static u8 bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
+                                  u8 flags)
+{
+        struct bnx2x *bp = netdev_priv(netdev);
+        u8 rval = 0;
+
+        DP(NETIF_MSG_LINK, "featid = %d flags = %02x\n", featid, flags);
+
+        /* ignore the 'advertise' flag */
+        if (bnx2x_dcbnl_set_valid(bp)) {
+                switch (featid) {
+                case DCB_FEATCFG_ATTR_PG:
+                        bp->dcbx_config_params.admin_ets_enable =
+                                flags & DCB_FEATCFG_ENABLE ? 1 : 0;
+                        bp->dcbx_config_params.admin_ets_willing =
+                                flags & DCB_FEATCFG_WILLING ? 1 : 0;
+                        break;
+                case DCB_FEATCFG_ATTR_PFC:
+                        bp->dcbx_config_params.admin_pfc_enable =
+                                flags & DCB_FEATCFG_ENABLE ? 1 : 0;
+                        bp->dcbx_config_params.admin_pfc_willing =
+                                flags & DCB_FEATCFG_WILLING ? 1 : 0;
+                        break;
+                case DCB_FEATCFG_ATTR_APP:
+                        /* ignore enable, always enabled */
+                        bp->dcbx_config_params.admin_app_priority_willing =
+                                flags & DCB_FEATCFG_WILLING ? 1 : 0;
+                        break;
+                default:
+                        rval = -EINVAL;
+                        break;
+                }
+        } else
+                rval = -EINVAL;
+
+        return rval;
+}
+
+const struct dcbnl_rtnl_ops bnx2x_dcbnl_ops = {
+        .getstate       = bnx2x_dcbnl_get_state,
+        .setstate       = bnx2x_dcbnl_set_state,
+        .getpermhwaddr  = bnx2x_dcbnl_get_perm_hw_addr,
+        .setpgtccfgtx   = bnx2x_dcbnl_set_pg_tccfg_tx,
+        .setpgbwgcfgtx  = bnx2x_dcbnl_set_pg_bwgcfg_tx,
+        .setpgtccfgrx   = bnx2x_dcbnl_set_pg_tccfg_rx,
+        .setpgbwgcfgrx  = bnx2x_dcbnl_set_pg_bwgcfg_rx,
+        .getpgtccfgtx   = bnx2x_dcbnl_get_pg_tccfg_tx,
+        .getpgbwgcfgtx  = bnx2x_dcbnl_get_pg_bwgcfg_tx,
+        .getpgtccfgrx   = bnx2x_dcbnl_get_pg_tccfg_rx,
+        .getpgbwgcfgrx  = bnx2x_dcbnl_get_pg_bwgcfg_rx,
+        .setpfccfg      = bnx2x_dcbnl_set_pfc_cfg,
+        .getpfccfg      = bnx2x_dcbnl_get_pfc_cfg,
+        .setall         = bnx2x_dcbnl_set_all,
+        .getcap         = bnx2x_dcbnl_get_cap,
+        .getnumtcs      = bnx2x_dcbnl_get_numtcs,
+        .setnumtcs      = bnx2x_dcbnl_set_numtcs,
+        .getpfcstate    = bnx2x_dcbnl_get_pfc_state,
+        .setpfcstate    = bnx2x_dcbnl_set_pfc_state,
+        .getapp         = bnx2x_dcbnl_get_app_up,
+        .setapp         = bnx2x_dcbnl_set_app_up,
+        .getdcbx        = bnx2x_dcbnl_get_dcbx,
+        .setdcbx        = bnx2x_dcbnl_set_dcbx,
+        .getfeatcfg     = bnx2x_dcbnl_get_featcfg,
+        .setfeatcfg     = bnx2x_dcbnl_set_featcfg,
+};
+
+#endif /* BCM_DCB */
diff --git a/drivers/net/bnx2x/bnx2x_dcb.h b/drivers/net/bnx2x/bnx2x_dcb.h
new file mode 100644
index 000000000000..f650f98e4092
--- /dev/null
+++ b/drivers/net/bnx2x/bnx2x_dcb.h
@@ -0,0 +1,196 @@
+/* bnx2x_dcb.h: Broadcom Everest network driver.
+ *
+ * Copyright 2009-2010 Broadcom Corporation
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
+ *
+ * Maintained by: Eilon Greenstein <eilong@broadcom.com>
+ * Written by: Dmitry Kravkov
+ *
+ */
+#ifndef BNX2X_DCB_H
+#define BNX2X_DCB_H
+
+#include "bnx2x_hsi.h"
+
+#define LLFC_DRIVER_TRAFFIC_TYPE_MAX 3 /* NW, iSCSI, FCoE */
+struct bnx2x_dcbx_app_params {
+        u32 enabled;
+        u32 traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
+};
+
+#define E2_NUM_OF_COS                   2
+#define BNX2X_DCBX_COS_NOT_STRICT       0
+#define BNX2X_DCBX_COS_LOW_STRICT       1
+#define BNX2X_DCBX_COS_HIGH_STRICT      2
+
+struct bnx2x_dcbx_cos_params {
+        u32     bw_tbl;
+        u32     pri_bitmask;
+        u8      strict;
+        u8      pauseable;
+};
+
+struct bnx2x_dcbx_pg_params {
+        u32 enabled;
+        u8 num_of_cos; /* valid COS entries */
+        struct bnx2x_dcbx_cos_params    cos_params[E2_NUM_OF_COS];
+};
+
+struct bnx2x_dcbx_pfc_params {
+        u32 enabled;
+        u32 priority_non_pauseable_mask;
+};
+
+struct bnx2x_dcbx_port_params {
+        struct bnx2x_dcbx_pfc_params pfc;
+        struct bnx2x_dcbx_pg_params  ets;
+        struct bnx2x_dcbx_app_params app;
+};
+
+#define BNX2X_DCBX_CONFIG_INV_VALUE                     (0xFFFFFFFF)
+#define BNX2X_DCBX_OVERWRITE_SETTINGS_DISABLE           0
+#define BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE            1
+#define BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID   (BNX2X_DCBX_CONFIG_INV_VALUE)
+
+/*******************************************************************************
+ * LLDP protocol configuration parameters.
+ ******************************************************************************/
+struct bnx2x_config_lldp_params {
+        u32 overwrite_settings;
+        u32 msg_tx_hold;
+        u32 msg_fast_tx;
+        u32 tx_credit_max;
+        u32 msg_tx_interval;
+        u32 tx_fast;
+};
+
+struct bnx2x_admin_priority_app_table {
+                u32 valid;
+                u32 priority;
+#define INVALID_TRAFFIC_TYPE_PRIORITY   (0xFFFFFFFF)
+                u32 traffic_type;
+#define TRAFFIC_TYPE_ETH                0
+#define TRAFFIC_TYPE_PORT               1
+                u32 app_id;
+};
+
+/*******************************************************************************
+ * DCBX protocol configuration parameters.
+ ******************************************************************************/
+struct bnx2x_config_dcbx_params {
+        u32 overwrite_settings;
+        u32 admin_dcbx_version;
+        u32 admin_ets_enable;
+        u32 admin_pfc_enable;
+        u32 admin_tc_supported_tx_enable;
+        u32 admin_ets_configuration_tx_enable;
+        u32 admin_ets_recommendation_tx_enable;
+        u32 admin_pfc_tx_enable;
+        u32 admin_application_priority_tx_enable;
+        u32 admin_ets_willing;
+        u32 admin_ets_reco_valid;
+        u32 admin_pfc_willing;
+        u32 admin_app_priority_willing;
+        u32 admin_configuration_bw_precentage[8];
+        u32 admin_configuration_ets_pg[8];
+        u32 admin_recommendation_bw_precentage[8];
+        u32 admin_recommendation_ets_pg[8];
+        u32 admin_pfc_bitmap;
+        struct bnx2x_admin_priority_app_table admin_priority_app_table[4];
+        u32 admin_default_priority;
+};
+
+#define GET_FLAGS(flags, bits)          ((flags) & (bits))
+#define SET_FLAGS(flags, bits)          ((flags) |= (bits))
+#define RESET_FLAGS(flags, bits)        ((flags) &= ~(bits))
+
+enum {
+        DCBX_READ_LOCAL_MIB,
+        DCBX_READ_REMOTE_MIB
+};
+
+#define ETH_TYPE_FCOE           (0x8906)
+#define TCP_PORT_ISCSI          (0xCBC)
+
+#define PFC_VALUE_FRAME_SIZE                            (512)
+#define PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA(mega_speed)  \
+                                ((1000 * PFC_VALUE_FRAME_SIZE)/(mega_speed))
+
+#define PFC_BRB1_REG_HIGH_LLFC_LOW_THRESHOLD                    130
+#define PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD                   170
+
+
+
+struct cos_entry_help_data {
+        u32                     pri_join_mask;
+        u32                     cos_bw;
+        u8                      strict;
+        bool                    pausable;
+};
+
+struct cos_help_data {
+        struct cos_entry_help_data      data[E2_NUM_OF_COS];
+        u8                              num_of_cos;
+};
+
+#define DCBX_ILLEGAL_PG                         (0xFF)
+#define DCBX_PFC_PRI_MASK                       (0xFF)
+#define DCBX_STRICT_PRIORITY                    (15)
+#define DCBX_INVALID_COS_BW                     (0xFFFFFFFF)
+#define DCBX_PFC_PRI_NON_PAUSE_MASK(bp)         \
+                        ((bp)->dcbx_port_params.pfc.priority_non_pauseable_mask)
+#define DCBX_PFC_PRI_PAUSE_MASK(bp)             \
+                                        ((u8)~DCBX_PFC_PRI_NON_PAUSE_MASK(bp))
+#define DCBX_PFC_PRI_GET_PAUSE(bp, pg_pri)      \
+                                ((pg_pri) & (DCBX_PFC_PRI_PAUSE_MASK(bp)))
+#define DCBX_PFC_PRI_GET_NON_PAUSE(bp, pg_pri)  \
+                        (DCBX_PFC_PRI_NON_PAUSE_MASK(bp) & (pg_pri))
+#define IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pg_pri)  \
+                        (pg_pri == DCBX_PFC_PRI_GET_PAUSE((bp), (pg_pri)))
+#define IS_DCBX_PFC_PRI_ONLY_NON_PAUSE(bp, pg_pri)\
+                        ((pg_pri) == DCBX_PFC_PRI_GET_NON_PAUSE((bp), (pg_pri)))
+#define IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pg_pri)   \
+                        (!(IS_DCBX_PFC_PRI_ONLY_NON_PAUSE((bp), (pg_pri)) || \
+                         IS_DCBX_PFC_PRI_ONLY_PAUSE((bp), (pg_pri))))
+
+
+struct pg_entry_help_data {
+        u8      num_of_dif_pri;
+        u8      pg;
+        u32     pg_priority;
+};
+
+struct pg_help_data {
+        struct pg_entry_help_data       data[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
+        u8                              num_of_pg;
+};
+
+/* forward DCB/PFC related declarations */
+struct bnx2x;
+void bnx2x_dcb_init_intmem_pfc(struct bnx2x *bp);
+void bnx2x_dcbx_update(struct work_struct *work);
+void bnx2x_dcbx_init_params(struct bnx2x *bp);
+void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on, u32 dcbx_enabled);
+
+enum {
+        BNX2X_DCBX_STATE_NEG_RECEIVED = 0x1,
+        BNX2X_DCBX_STATE_TX_PAUSED = 0x2,
+        BNX2X_DCBX_STATE_TX_RELEASED = 0x4
+};
+void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state);
+
+/* DCB netlink */
+#ifdef BCM_DCB
+extern const struct dcbnl_rtnl_ops bnx2x_dcbnl_ops;
+#endif /* BCM_DCB */
+
+#endif /* BNX2X_DCB_H */
diff --git a/drivers/net/bnx2x/bnx2x_dump.h b/drivers/net/bnx2x/bnx2x_dump.h
index dc18c25ca9e5..fb3ff7c4d7ca 100644
--- a/drivers/net/bnx2x/bnx2x_dump.h
+++ b/drivers/net/bnx2x/bnx2x_dump.h
@@ -1,10 +1,16 @@
 /* bnx2x_dump.h: Broadcom Everest network driver.
  *
- * Copyright (c) 2009 Broadcom Corporation
+ * Copyright (c) 2011 Broadcom Corporation
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation.
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License version 2, available
+ * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
+ *
+ * Notwithstanding the above, under no circumstances may you combine this
+ * software in any way with any other Broadcom software provided under a
+ * license other than the GPL, without Broadcom's express prior written
+ * consent.
  */
 
 
@@ -17,53 +23,53 @@
 #define BNX2X_DUMP_H
 
 
-struct dump_sign {
-        u32 time_stamp;
-        u32 diag_ver;
-        u32 grc_dump_ver;
-};
 
-#define TSTORM_WAITP_ADDR               0x1b8a80
-#define CSTORM_WAITP_ADDR               0x238a80
-#define XSTORM_WAITP_ADDR               0x2b8a80
-#define USTORM_WAITP_ADDR               0x338a80
-#define TSTORM_CAM_MODE                 0x1b1440
+/*definitions */
+#define XSTORM_WAITP_ADDR    0x2b8a80
+#define TSTORM_WAITP_ADDR    0x1b8a80
+#define USTORM_WAITP_ADDR    0x338a80
+#define CSTORM_WAITP_ADDR    0x238a80
+#define TSTORM_CAM_MODE         0x1B1440
 
-#define RI_E1                           0x1
-#define RI_E1H                          0x2
+#define MAX_TIMER_PENDING      200
+#define TIMER_SCAN_DONT_CARE   0xFF
+#define RI_E1                   0x1
+#define RI_E1H                  0x2
 #define RI_E2                   0x4
-#define RI_ONLINE                       0x100
+#define RI_ONLINE               0x100
 #define RI_PATH0_DUMP           0x200
 #define RI_PATH1_DUMP           0x400
-#define RI_E1_OFFLINE                   (RI_E1)
-#define RI_E1_ONLINE                    (RI_E1 | RI_ONLINE)
-#define RI_E1H_OFFLINE                  (RI_E1H)
-#define RI_E1H_ONLINE                   (RI_E1H | RI_ONLINE)
-#define RI_E2_OFFLINE                   (RI_E2)
-#define RI_E2_ONLINE                    (RI_E2 | RI_ONLINE)
-#define RI_E1E1H_OFFLINE                (RI_E1 | RI_E1H)
-#define RI_E1E1H_ONLINE                 (RI_E1 | RI_E1H | RI_ONLINE)
-#define RI_E1HE2_OFFLINE                (RI_E2 | RI_E1H)
-#define RI_E1HE2_ONLINE                 (RI_E2 | RI_E1H | RI_ONLINE)
-#define RI_E1E2_OFFLINE                 (RI_E2 | RI_E1)
-#define RI_E1E2_ONLINE                  (RI_E2 | RI_E1 | RI_ONLINE)
-#define RI_ALL_OFFLINE                  (RI_E1 | RI_E1H | RI_E2)
-#define RI_ALL_ONLINE                   (RI_E1 | RI_E1H | RI_E2 | RI_ONLINE)
-
-#define MAX_TIMER_PENDING               200
-#define TIMER_SCAN_DONT_CARE            0xFF
+#define RI_E1_OFFLINE           (RI_E1)
+#define RI_E1_ONLINE            (RI_E1 | RI_ONLINE)
+#define RI_E1H_OFFLINE          (RI_E1H)
+#define RI_E1H_ONLINE           (RI_E1H | RI_ONLINE)
+#define RI_E2_OFFLINE           (RI_E2)
+#define RI_E2_ONLINE            (RI_E2 | RI_ONLINE)
+#define RI_E1E1H_OFFLINE        (RI_E1 | RI_E1H)
+#define RI_E1E1H_ONLINE         (RI_E1 | RI_E1H | RI_ONLINE)
+#define RI_E1HE2_OFFLINE        (RI_E2 | RI_E1H)
+#define RI_E1HE2_ONLINE         (RI_E2 | RI_E1H | RI_ONLINE)
+#define RI_E1E2_OFFLINE         (RI_E2 | RI_E1)
+#define RI_E1E2_ONLINE          (RI_E2 | RI_E1 | RI_ONLINE)
+#define RI_ALL_OFFLINE         (RI_E1 | RI_E1H | RI_E2)
+#define RI_ALL_ONLINE          (RI_E1 | RI_E1H | RI_E2 | RI_ONLINE)
 
+struct dump_sign {
+        u32 time_stamp;
+        u32 diag_ver;
+        u32 grc_dump_ver;
+};
 
 struct dump_hdr {
-        u32              hdr_size;      /* in dwords, excluding this field */
-        struct dump_sign dump_sign;
-        u32              xstorm_waitp;
-        u32              tstorm_waitp;
-        u32              ustorm_waitp;
-        u32              cstorm_waitp;
-        u16              info;
-        u8               idle_chk;
-        u8               reserved;
+        u32  hdr_size;  /* in dwords, excluding this field */
+        struct dump_sign        dump_sign;
+        u32  xstorm_waitp;
+        u32  tstorm_waitp;
+        u32  ustorm_waitp;
+        u32  cstorm_waitp;
+        u16  info;
+        u8   idle_chk;
+        u8   reserved;
 };
 
 struct reg_addr {
@@ -80,202 +86,185 @@ struct wreg_addr {
         u16 info;
 };
 
-
-#define REGS_COUNT                      558
+#define REGS_COUNT                      834
 static const struct reg_addr reg_addrs[REGS_COUNT] = {
         { 0x2000, 341, RI_ALL_ONLINE }, { 0x2800, 103, RI_ALL_ONLINE },
         { 0x3000, 287, RI_ALL_ONLINE }, { 0x3800, 331, RI_ALL_ONLINE },
-        { 0x8800, 6, RI_E1_ONLINE }, { 0xa000, 223, RI_ALL_ONLINE },
-        { 0xa388, 1, RI_ALL_ONLINE }, { 0xa398, 1, RI_ALL_ONLINE },
-        { 0xa39c, 7, RI_E1H_ONLINE }, { 0xa3c0, 3, RI_E1H_ONLINE },
-        { 0xa3d0, 1, RI_E1H_ONLINE }, { 0xa3d8, 1, RI_E1H_ONLINE },
-        { 0xa3e0, 1, RI_E1H_ONLINE }, { 0xa3e8, 1, RI_E1H_ONLINE },
-        { 0xa3f0, 1, RI_E1H_ONLINE }, { 0xa3f8, 1, RI_E1H_ONLINE },
-        { 0xa400, 69, RI_ALL_ONLINE }, { 0xa518, 1, RI_ALL_ONLINE },
-        { 0xa520, 1, RI_ALL_ONLINE }, { 0xa528, 1, RI_ALL_ONLINE },
-        { 0xa530, 1, RI_ALL_ONLINE }, { 0xa538, 1, RI_ALL_ONLINE },
-        { 0xa540, 1, RI_ALL_ONLINE }, { 0xa548, 1, RI_ALL_ONLINE },
-        { 0xa550, 1, RI_ALL_ONLINE }, { 0xa558, 1, RI_ALL_ONLINE },
-        { 0xa560, 1, RI_ALL_ONLINE }, { 0xa568, 1, RI_ALL_ONLINE },
-        { 0xa570, 1, RI_ALL_ONLINE }, { 0xa580, 1, RI_ALL_ONLINE },
-        { 0xa590, 1, RI_ALL_ONLINE }, { 0xa5a0, 1, RI_ALL_ONLINE },
-        { 0xa5c0, 1, RI_ALL_ONLINE }, { 0xa5e0, 1, RI_E1H_ONLINE },
-        { 0xa5e8, 1, RI_E1H_ONLINE }, { 0xa5f0, 1, RI_E1H_ONLINE },
-        { 0xa5f8, 10, RI_E1H_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE },
-        { 0x103bc, 1, RI_ALL_ONLINE }, { 0x103cc, 1, RI_ALL_ONLINE },
-        { 0x103dc, 1, RI_ALL_ONLINE }, { 0x10400, 57, RI_ALL_ONLINE },
-        { 0x104e8, 2, RI_ALL_ONLINE }, { 0x104f4, 2, RI_ALL_ONLINE },
-        { 0x10500, 146, RI_ALL_ONLINE }, { 0x10750, 2, RI_ALL_ONLINE },
-        { 0x10760, 2, RI_ALL_ONLINE }, { 0x10770, 2, RI_ALL_ONLINE },
-        { 0x10780, 2, RI_ALL_ONLINE }, { 0x10790, 2, RI_ALL_ONLINE },
-        { 0x107a0, 2, RI_ALL_ONLINE }, { 0x107b0, 2, RI_ALL_ONLINE },
-        { 0x107c0, 2, RI_ALL_ONLINE }, { 0x107d0, 2, RI_ALL_ONLINE },
-        { 0x107e0, 2, RI_ALL_ONLINE }, { 0x10880, 2, RI_ALL_ONLINE },
-        { 0x10900, 2, RI_ALL_ONLINE }, { 0x12000, 1, RI_ALL_ONLINE },
-        { 0x14000, 1, RI_ALL_ONLINE }, { 0x16000, 26, RI_E1H_ONLINE },
-        { 0x16070, 18, RI_E1H_ONLINE }, { 0x160c0, 27, RI_E1H_ONLINE },
-        { 0x16140, 1, RI_E1H_ONLINE }, { 0x16160, 1, RI_E1H_ONLINE },
-        { 0x16180, 2, RI_E1H_ONLINE }, { 0x161c0, 2, RI_E1H_ONLINE },
-        { 0x16204, 5, RI_E1H_ONLINE }, { 0x18000, 1, RI_E1H_ONLINE },
-        { 0x18008, 1, RI_E1H_ONLINE }, { 0x20000, 24, RI_ALL_ONLINE },
-        { 0x20060, 8, RI_ALL_ONLINE }, { 0x20080, 138, RI_ALL_ONLINE },
-        { 0x202b4, 1, RI_ALL_ONLINE }, { 0x202c4, 1, RI_ALL_ONLINE },
-        { 0x20400, 2, RI_ALL_ONLINE }, { 0x2040c, 8, RI_ALL_ONLINE },
-        { 0x2042c, 18, RI_E1H_ONLINE }, { 0x20480, 1, RI_ALL_ONLINE },
-        { 0x20500, 1, RI_ALL_ONLINE }, { 0x20600, 1, RI_ALL_ONLINE },
-        { 0x28000, 1, RI_ALL_ONLINE }, { 0x28004, 8191, RI_ALL_OFFLINE },
-        { 0x30000, 1, RI_ALL_ONLINE }, { 0x30004, 16383, RI_ALL_OFFLINE },
-        { 0x40000, 98, RI_ALL_ONLINE }, { 0x40194, 1, RI_ALL_ONLINE },
-        { 0x401a4, 1, RI_ALL_ONLINE }, { 0x401a8, 11, RI_E1H_ONLINE },
-        { 0x40200, 4, RI_ALL_ONLINE }, { 0x40400, 43, RI_ALL_ONLINE },
-        { 0x404b8, 1, RI_ALL_ONLINE }, { 0x404c8, 1, RI_ALL_ONLINE },
-        { 0x404cc, 3, RI_E1H_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE },
+        { 0x8800, 6, RI_ALL_ONLINE }, { 0x8818, 1, RI_E1HE2_ONLINE },
+        { 0x9000, 164, RI_E2_ONLINE }, { 0x9400, 33, RI_E2_ONLINE },
+        { 0xa000, 27, RI_ALL_ONLINE }, { 0xa06c, 1, RI_E1E1H_ONLINE },
+        { 0xa070, 71, RI_ALL_ONLINE }, { 0xa18c, 4, RI_E1E1H_ONLINE },
+        { 0xa19c, 62, RI_ALL_ONLINE }, { 0xa294, 2, RI_E1E1H_ONLINE },
+        { 0xa29c, 56, RI_ALL_ONLINE }, { 0xa39c, 7, RI_E1HE2_ONLINE },
+        { 0xa3c0, 3, RI_E1HE2_ONLINE }, { 0xa3d0, 1, RI_E1HE2_ONLINE },
+        { 0xa3d8, 1, RI_E1HE2_ONLINE }, { 0xa3e0, 1, RI_E1HE2_ONLINE },
+        { 0xa3e8, 1, RI_E1HE2_ONLINE }, { 0xa3f0, 1, RI_E1HE2_ONLINE },
+        { 0xa3f8, 1, RI_E1HE2_ONLINE }, { 0xa400, 43, RI_ALL_ONLINE },
+        { 0xa4ac, 2, RI_E1E1H_ONLINE }, { 0xa4b4, 1, RI_ALL_ONLINE },
+        { 0xa4b8, 2, RI_E1E1H_ONLINE }, { 0xa4c0, 3, RI_ALL_ONLINE },
+        { 0xa4cc, 5, RI_E1E1H_ONLINE }, { 0xa4e0, 9, RI_ALL_ONLINE },
+        { 0xa504, 1, RI_E1E1H_ONLINE }, { 0xa508, 3, RI_ALL_ONLINE },
+        { 0xa518, 1, RI_ALL_ONLINE }, { 0xa520, 1, RI_ALL_ONLINE },
+        { 0xa528, 1, RI_ALL_ONLINE }, { 0xa530, 1, RI_ALL_ONLINE },
+        { 0xa538, 1, RI_ALL_ONLINE }, { 0xa540, 1, RI_ALL_ONLINE },
+        { 0xa548, 1, RI_E1E1H_ONLINE }, { 0xa550, 1, RI_E1E1H_ONLINE },
+        { 0xa558, 1, RI_E1E1H_ONLINE }, { 0xa560, 1, RI_E1E1H_ONLINE },
+        { 0xa568, 1, RI_E1E1H_ONLINE }, { 0xa570, 1, RI_ALL_ONLINE },
+        { 0xa580, 1, RI_ALL_ONLINE }, { 0xa590, 1, RI_ALL_ONLINE },
+        { 0xa5a0, 1, RI_ALL_ONLINE }, { 0xa5c0, 1, RI_ALL_ONLINE },
+        { 0xa5e0, 1, RI_E1HE2_ONLINE }, { 0xa5e8, 1, RI_E1HE2_ONLINE },
+        { 0xa5f0, 1, RI_E1HE2_ONLINE }, { 0xa5f8, 10, RI_E1HE2_ONLINE },
+        { 0xa620, 111, RI_E2_ONLINE }, { 0xa800, 51, RI_E2_ONLINE },
+        { 0xa8d4, 4, RI_E2_ONLINE }, { 0xa8e8, 1, RI_E2_ONLINE },
+        { 0xa8f0, 1, RI_E2_ONLINE }, { 0x10000, 236, RI_ALL_ONLINE },
+        { 0x10400, 57, RI_ALL_ONLINE }, { 0x104e8, 2, RI_ALL_ONLINE },
+        { 0x104f4, 2, RI_ALL_ONLINE }, { 0x10500, 146, RI_ALL_ONLINE },
+        { 0x10750, 2, RI_ALL_ONLINE }, { 0x10760, 2, RI_ALL_ONLINE },
+        { 0x10770, 2, RI_ALL_ONLINE }, { 0x10780, 2, RI_ALL_ONLINE },
+        { 0x10790, 2, RI_ALL_ONLINE }, { 0x107a0, 2, RI_ALL_ONLINE },
+        { 0x107b0, 2, RI_ALL_ONLINE }, { 0x107c0, 2, RI_ALL_ONLINE },
+        { 0x107d0, 2, RI_ALL_ONLINE }, { 0x107e0, 2, RI_ALL_ONLINE },
+        { 0x10880, 2, RI_ALL_ONLINE }, { 0x10900, 2, RI_ALL_ONLINE },
+        { 0x16000, 26, RI_E1HE2_ONLINE }, { 0x16070, 18, RI_E1HE2_ONLINE },
+        { 0x160c0, 27, RI_E1HE2_ONLINE }, { 0x16140, 1, RI_E1HE2_ONLINE },
+        { 0x16160, 1, RI_E1HE2_ONLINE }, { 0x16180, 2, RI_E1HE2_ONLINE },
+        { 0x161c0, 2, RI_E1HE2_ONLINE }, { 0x16204, 5, RI_E1HE2_ONLINE },
+        { 0x18000, 1, RI_E1HE2_ONLINE }, { 0x18008, 1, RI_E1HE2_ONLINE },
+        { 0x18010, 35, RI_E2_ONLINE }, { 0x180a4, 2, RI_E2_ONLINE },
+        { 0x180c0, 191, RI_E2_ONLINE }, { 0x18440, 1, RI_E2_ONLINE },
+        { 0x18460, 1, RI_E2_ONLINE }, { 0x18480, 2, RI_E2_ONLINE },
+        { 0x184c0, 2, RI_E2_ONLINE }, { 0x18500, 15, RI_E2_ONLINE },
+        { 0x20000, 24, RI_ALL_ONLINE }, { 0x20060, 8, RI_ALL_ONLINE },
+        { 0x20080, 94, RI_ALL_ONLINE }, { 0x201f8, 1, RI_E1E1H_ONLINE },
+        { 0x201fc, 1, RI_ALL_ONLINE }, { 0x20200, 1, RI_E1E1H_ONLINE },
+        { 0x20204, 1, RI_ALL_ONLINE }, { 0x20208, 1, RI_E1E1H_ONLINE },
+        { 0x2020c, 39, RI_ALL_ONLINE }, { 0x202c8, 1, RI_E2_ONLINE },
+        { 0x202d8, 4, RI_E2_ONLINE }, { 0x20400, 2, RI_ALL_ONLINE },
+        { 0x2040c, 8, RI_ALL_ONLINE }, { 0x2042c, 18, RI_E1HE2_ONLINE },
+        { 0x20480, 1, RI_ALL_ONLINE }, { 0x20500, 1, RI_ALL_ONLINE },
+        { 0x20600, 1, RI_ALL_ONLINE }, { 0x28000, 1, RI_ALL_ONLINE },
+        { 0x28004, 8191, RI_ALL_OFFLINE }, { 0x30000, 1, RI_ALL_ONLINE },
+        { 0x30004, 16383, RI_ALL_OFFLINE }, { 0x40000, 98, RI_ALL_ONLINE },
+        { 0x401a8, 8, RI_E1HE2_ONLINE }, { 0x401c8, 1, RI_E1H_ONLINE },
+        { 0x401cc, 2, RI_E1HE2_ONLINE }, { 0x401d4, 2, RI_E2_ONLINE },
+        { 0x40200, 4, RI_ALL_ONLINE }, { 0x40220, 18, RI_E2_ONLINE },
+        { 0x40400, 43, RI_ALL_ONLINE }, { 0x404cc, 3, RI_E1HE2_ONLINE },
+        { 0x404e0, 1, RI_E2_ONLINE }, { 0x40500, 2, RI_ALL_ONLINE },
         { 0x40510, 2, RI_ALL_ONLINE }, { 0x40520, 2, RI_ALL_ONLINE },
         { 0x40530, 2, RI_ALL_ONLINE }, { 0x40540, 2, RI_ALL_ONLINE },
-        { 0x42000, 164, RI_ALL_ONLINE }, { 0x4229c, 1, RI_ALL_ONLINE },
-        { 0x422ac, 1, RI_ALL_ONLINE }, { 0x422bc, 1, RI_ALL_ONLINE },
-        { 0x422d4, 5, RI_E1H_ONLINE }, { 0x42400, 49, RI_ALL_ONLINE },
-        { 0x424c8, 38, RI_ALL_ONLINE }, { 0x42568, 2, RI_ALL_ONLINE },
-        { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 20, RI_ALL_ONLINE },
-        { 0x50050, 8, RI_ALL_ONLINE }, { 0x50070, 88, RI_ALL_ONLINE },
-        { 0x501dc, 1, RI_ALL_ONLINE }, { 0x501ec, 1, RI_ALL_ONLINE },
-        { 0x501f0, 4, RI_E1H_ONLINE }, { 0x50200, 2, RI_ALL_ONLINE },
-        { 0x5020c, 7, RI_ALL_ONLINE }, { 0x50228, 6, RI_E1H_ONLINE },
-        { 0x50240, 1, RI_ALL_ONLINE }, { 0x50280, 1, RI_ALL_ONLINE },
+        { 0x40550, 10, RI_E2_ONLINE }, { 0x40610, 2, RI_E2_ONLINE },
+        { 0x42000, 164, RI_ALL_ONLINE }, { 0x422c0, 4, RI_E2_ONLINE },
+        { 0x422d4, 5, RI_E1HE2_ONLINE }, { 0x422e8, 1, RI_E2_ONLINE },
+        { 0x42400, 49, RI_ALL_ONLINE }, { 0x424c8, 38, RI_ALL_ONLINE },
+        { 0x42568, 2, RI_ALL_ONLINE }, { 0x42640, 5, RI_E2_ONLINE },
+        { 0x42800, 1, RI_ALL_ONLINE }, { 0x50000, 1, RI_ALL_ONLINE },
+        { 0x50004, 19, RI_ALL_ONLINE }, { 0x50050, 8, RI_ALL_ONLINE },
+        { 0x50070, 88, RI_ALL_ONLINE }, { 0x501f0, 4, RI_E1HE2_ONLINE },
+        { 0x50200, 2, RI_ALL_ONLINE }, { 0x5020c, 7, RI_ALL_ONLINE },
+        { 0x50228, 6, RI_E1HE2_ONLINE }, { 0x50240, 1, RI_ALL_ONLINE },
+        { 0x50280, 1, RI_ALL_ONLINE }, { 0x50300, 1, RI_E2_ONLINE },
+        { 0x5030c, 1, RI_E2_ONLINE }, { 0x50318, 1, RI_E2_ONLINE },
+        { 0x5031c, 1, RI_E2_ONLINE }, { 0x50320, 2, RI_E2_ONLINE },
         { 0x52000, 1, RI_ALL_ONLINE }, { 0x54000, 1, RI_ALL_ONLINE },
         { 0x54004, 3327, RI_ALL_OFFLINE }, { 0x58000, 1, RI_ALL_ONLINE },
-        { 0x58004, 8191, RI_ALL_OFFLINE }, { 0x60000, 71, RI_ALL_ONLINE },
-        { 0x60128, 1, RI_ALL_ONLINE }, { 0x60138, 1, RI_ALL_ONLINE },
-        { 0x6013c, 24, RI_E1H_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE },
+        { 0x58004, 8191, RI_E1E1H_OFFLINE }, { 0x60000, 26, RI_ALL_ONLINE },
+        { 0x60068, 8, RI_E1E1H_ONLINE }, { 0x60088, 12, RI_ALL_ONLINE },
+        { 0x600b8, 9, RI_E1E1H_ONLINE }, { 0x600dc, 1, RI_ALL_ONLINE },
+        { 0x600e0, 5, RI_E1E1H_ONLINE }, { 0x600f4, 1, RI_ALL_ONLINE },
+        { 0x600f8, 1, RI_E1E1H_ONLINE }, { 0x600fc, 8, RI_ALL_ONLINE },
+        { 0x6013c, 24, RI_E1H_ONLINE }, { 0x6019c, 2, RI_E2_ONLINE },
+        { 0x601ac, 18, RI_E2_ONLINE }, { 0x60200, 1, RI_ALL_ONLINE },
+        { 0x60204, 2, RI_ALL_OFFLINE }, { 0x60210, 13, RI_E2_ONLINE },
         { 0x61000, 1, RI_ALL_ONLINE }, { 0x61004, 511, RI_ALL_OFFLINE },
-        { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 21496, RI_ALL_OFFLINE },
-        { 0x85000, 3, RI_ALL_ONLINE }, { 0x8500c, 4, RI_ALL_OFFLINE },
-        { 0x8501c, 7, RI_ALL_ONLINE }, { 0x85038, 4, RI_ALL_OFFLINE },
-        { 0x85048, 1, RI_ALL_ONLINE }, { 0x8504c, 109, RI_ALL_OFFLINE },
-        { 0x85200, 32, RI_ALL_ONLINE }, { 0x85280, 11104, RI_ALL_OFFLINE },
-        { 0xa0000, 16384, RI_ALL_ONLINE }, { 0xb0000, 16384, RI_E1H_ONLINE },
-        { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc1028, 1, RI_ALL_ONLINE },
-        { 0xc1038, 1, RI_ALL_ONLINE }, { 0xc1800, 2, RI_ALL_ONLINE },
-        { 0xc2000, 164, RI_ALL_ONLINE }, { 0xc229c, 1, RI_ALL_ONLINE },
-        { 0xc22ac, 1, RI_ALL_ONLINE }, { 0xc22bc, 1, RI_ALL_ONLINE },
+        { 0x70000, 8, RI_ALL_ONLINE }, { 0x70020, 8184, RI_ALL_OFFLINE },
+        { 0x85000, 3, RI_ALL_ONLINE }, { 0x8501c, 7, RI_ALL_ONLINE },
+        { 0x85048, 1, RI_ALL_ONLINE }, { 0x85200, 32, RI_ALL_ONLINE },
+        { 0xc1000, 7, RI_ALL_ONLINE }, { 0xc103c, 2, RI_E2_ONLINE },
+        { 0xc1800, 2, RI_ALL_ONLINE }, { 0xc2000, 164, RI_ALL_ONLINE },
+        { 0xc22c0, 5, RI_E2_ONLINE }, { 0xc22d8, 4, RI_E2_ONLINE },
         { 0xc2400, 49, RI_ALL_ONLINE }, { 0xc24c8, 38, RI_ALL_ONLINE },
         { 0xc2568, 2, RI_ALL_ONLINE }, { 0xc2600, 1, RI_ALL_ONLINE },
-        { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42a0, 1, RI_ALL_ONLINE },
-        { 0xc42b0, 1, RI_ALL_ONLINE }, { 0xc42c0, 1, RI_ALL_ONLINE },
-        { 0xc42e0, 7, RI_E1H_ONLINE }, { 0xc4400, 51, RI_ALL_ONLINE },
-        { 0xc44d0, 38, RI_ALL_ONLINE }, { 0xc4570, 2, RI_ALL_ONLINE },
+        { 0xc4000, 165, RI_ALL_ONLINE }, { 0xc42d8, 2, RI_E2_ONLINE },
+        { 0xc42e0, 7, RI_E1HE2_ONLINE }, { 0xc42fc, 1, RI_E2_ONLINE },
+        { 0xc4400, 51, RI_ALL_ONLINE }, { 0xc44d0, 38, RI_ALL_ONLINE },
+        { 0xc4570, 2, RI_ALL_ONLINE }, { 0xc4578, 5, RI_E2_ONLINE },
         { 0xc4600, 1, RI_ALL_ONLINE }, { 0xd0000, 19, RI_ALL_ONLINE },
         { 0xd004c, 8, RI_ALL_ONLINE }, { 0xd006c, 91, RI_ALL_ONLINE },
-        { 0xd01e4, 1, RI_ALL_ONLINE }, { 0xd01f4, 1, RI_ALL_ONLINE },
-        { 0xd0200, 2, RI_ALL_ONLINE }, { 0xd020c, 7, RI_ALL_ONLINE },
-        { 0xd0228, 18, RI_E1H_ONLINE }, { 0xd0280, 1, RI_ALL_ONLINE },
-        { 0xd0300, 1, RI_ALL_ONLINE }, { 0xd0400, 1, RI_ALL_ONLINE },
-        { 0xd4000, 1, RI_ALL_ONLINE }, { 0xd4004, 2559, RI_ALL_OFFLINE },
-        { 0xd8000, 1, RI_ALL_ONLINE }, { 0xd8004, 8191, RI_ALL_OFFLINE },
-        { 0xe0000, 21, RI_ALL_ONLINE }, { 0xe0054, 8, RI_ALL_ONLINE },
-        { 0xe0074, 85, RI_ALL_ONLINE }, { 0xe01d4, 1, RI_ALL_ONLINE },
-        { 0xe01e4, 1, RI_ALL_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE },
-        { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1H_ONLINE },
+        { 0xd01fc, 1, RI_E2_ONLINE }, { 0xd0200, 2, RI_ALL_ONLINE },
+        { 0xd020c, 7, RI_ALL_ONLINE }, { 0xd0228, 18, RI_E1HE2_ONLINE },
+        { 0xd0280, 1, RI_ALL_ONLINE }, { 0xd0300, 1, RI_ALL_ONLINE },
+        { 0xd0400, 1, RI_ALL_ONLINE }, { 0xd4000, 1, RI_ALL_ONLINE },
+        { 0xd4004, 2559, RI_ALL_OFFLINE }, { 0xd8000, 1, RI_ALL_ONLINE },
+        { 0xd8004, 8191, RI_ALL_OFFLINE }, { 0xe0000, 21, RI_ALL_ONLINE },
+        { 0xe0054, 8, RI_ALL_ONLINE }, { 0xe0074, 49, RI_ALL_ONLINE },
+        { 0xe0138, 1, RI_E1E1H_ONLINE }, { 0xe013c, 35, RI_ALL_ONLINE },
+        { 0xe01f4, 2, RI_E2_ONLINE }, { 0xe0200, 2, RI_ALL_ONLINE },
+        { 0xe020c, 8, RI_ALL_ONLINE }, { 0xe022c, 18, RI_E1HE2_ONLINE },
         { 0xe0280, 1, RI_ALL_ONLINE }, { 0xe0300, 1, RI_ALL_ONLINE },
         { 0xe1000, 1, RI_ALL_ONLINE }, { 0xe2000, 1, RI_ALL_ONLINE },
         { 0xe2004, 2047, RI_ALL_OFFLINE }, { 0xf0000, 1, RI_ALL_ONLINE },
         { 0xf0004, 16383, RI_ALL_OFFLINE }, { 0x101000, 12, RI_ALL_ONLINE },
-        { 0x10103c, 1, RI_ALL_ONLINE }, { 0x10104c, 1, RI_ALL_ONLINE },
-        { 0x101050, 1, RI_E1H_ONLINE }, { 0x101100, 1, RI_ALL_ONLINE },
-        { 0x101800, 8, RI_ALL_ONLINE }, { 0x102000, 18, RI_ALL_ONLINE },
-        { 0x102054, 1, RI_ALL_ONLINE }, { 0x102064, 1, RI_ALL_ONLINE },
+        { 0x101050, 1, RI_E1HE2_ONLINE }, { 0x101054, 3, RI_E2_ONLINE },
+        { 0x101100, 1, RI_ALL_ONLINE }, { 0x101800, 8, RI_ALL_ONLINE },
+        { 0x102000, 18, RI_ALL_ONLINE }, { 0x102068, 6, RI_E2_ONLINE },
         { 0x102080, 17, RI_ALL_ONLINE }, { 0x1020c8, 8, RI_E1H_ONLINE },
-        { 0x102400, 1, RI_ALL_ONLINE }, { 0x103000, 26, RI_ALL_ONLINE },
-        { 0x103074, 1, RI_ALL_ONLINE }, { 0x103084, 1, RI_ALL_ONLINE },
-        { 0x103094, 1, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1H_ONLINE },
+        { 0x1020e8, 9, RI_E2_ONLINE }, { 0x102400, 1, RI_ALL_ONLINE },
+        { 0x103000, 26, RI_ALL_ONLINE }, { 0x103098, 5, RI_E1HE2_ONLINE },
+        { 0x1030ac, 10, RI_E2_ONLINE }, { 0x1030d8, 8, RI_E2_ONLINE },
+        { 0x103400, 1, RI_E2_ONLINE }, { 0x103404, 135, RI_E2_OFFLINE },
         { 0x103800, 8, RI_ALL_ONLINE }, { 0x104000, 63, RI_ALL_ONLINE },
-        { 0x104108, 1, RI_ALL_ONLINE }, { 0x104118, 1, RI_ALL_ONLINE },
-        { 0x104200, 17, RI_ALL_ONLINE }, { 0x104400, 64, RI_ALL_ONLINE },
-        { 0x104500, 192, RI_ALL_OFFLINE }, { 0x104800, 64, RI_ALL_ONLINE },
-        { 0x104900, 192, RI_ALL_OFFLINE }, { 0x105000, 7, RI_ALL_ONLINE },
-        { 0x10501c, 1, RI_ALL_OFFLINE }, { 0x105020, 3, RI_ALL_ONLINE },
-        { 0x10502c, 1, RI_ALL_OFFLINE }, { 0x105030, 3, RI_ALL_ONLINE },
-        { 0x10503c, 1, RI_ALL_OFFLINE }, { 0x105040, 3, RI_ALL_ONLINE },
-        { 0x10504c, 1, RI_ALL_OFFLINE }, { 0x105050, 3, RI_ALL_ONLINE },
-        { 0x10505c, 1, RI_ALL_OFFLINE }, { 0x105060, 3, RI_ALL_ONLINE },
-        { 0x10506c, 1, RI_ALL_OFFLINE }, { 0x105070, 3, RI_ALL_ONLINE },
-        { 0x10507c, 1, RI_ALL_OFFLINE }, { 0x105080, 3, RI_ALL_ONLINE },
-        { 0x10508c, 1, RI_ALL_OFFLINE }, { 0x105090, 3, RI_ALL_ONLINE },
-        { 0x10509c, 1, RI_ALL_OFFLINE }, { 0x1050a0, 3, RI_ALL_ONLINE },
-        { 0x1050ac, 1, RI_ALL_OFFLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
-        { 0x1050bc, 1, RI_ALL_OFFLINE }, { 0x1050c0, 3, RI_ALL_ONLINE },
-        { 0x1050cc, 1, RI_ALL_OFFLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
-        { 0x1050dc, 1, RI_ALL_OFFLINE }, { 0x1050e0, 3, RI_ALL_ONLINE },
-        { 0x1050ec, 1, RI_ALL_OFFLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
-        { 0x1050fc, 1, RI_ALL_OFFLINE }, { 0x105100, 3, RI_ALL_ONLINE },
-        { 0x10510c, 1, RI_ALL_OFFLINE }, { 0x105110, 3, RI_ALL_ONLINE },
-        { 0x10511c, 1, RI_ALL_OFFLINE }, { 0x105120, 3, RI_ALL_ONLINE },
-        { 0x10512c, 1, RI_ALL_OFFLINE }, { 0x105130, 3, RI_ALL_ONLINE },
-        { 0x10513c, 1, RI_ALL_OFFLINE }, { 0x105140, 3, RI_ALL_ONLINE },
-        { 0x10514c, 1, RI_ALL_OFFLINE }, { 0x105150, 3, RI_ALL_ONLINE },
-        { 0x10515c, 1, RI_ALL_OFFLINE }, { 0x105160, 3, RI_ALL_ONLINE },
-        { 0x10516c, 1, RI_ALL_OFFLINE }, { 0x105170, 3, RI_ALL_ONLINE },
-        { 0x10517c, 1, RI_ALL_OFFLINE }, { 0x105180, 3, RI_ALL_ONLINE },
-        { 0x10518c, 1, RI_ALL_OFFLINE }, { 0x105190, 3, RI_ALL_ONLINE },
-        { 0x10519c, 1, RI_ALL_OFFLINE }, { 0x1051a0, 3, RI_ALL_ONLINE },
-        { 0x1051ac, 1, RI_ALL_OFFLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
-        { 0x1051bc, 1, RI_ALL_OFFLINE }, { 0x1051c0, 3, RI_ALL_ONLINE },
-        { 0x1051cc, 1, RI_ALL_OFFLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
-        { 0x1051dc, 1, RI_ALL_OFFLINE }, { 0x1051e0, 3, RI_ALL_ONLINE },
-        { 0x1051ec, 1, RI_ALL_OFFLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
-        { 0x1051fc, 1, RI_ALL_OFFLINE }, { 0x105200, 3, RI_ALL_ONLINE },
-        { 0x10520c, 1, RI_ALL_OFFLINE }, { 0x105210, 3, RI_ALL_ONLINE },
-        { 0x10521c, 1, RI_ALL_OFFLINE }, { 0x105220, 3, RI_ALL_ONLINE },
-        { 0x10522c, 1, RI_ALL_OFFLINE }, { 0x105230, 3, RI_ALL_ONLINE },
-        { 0x10523c, 1, RI_ALL_OFFLINE }, { 0x105240, 3, RI_ALL_ONLINE },
-        { 0x10524c, 1, RI_ALL_OFFLINE }, { 0x105250, 3, RI_ALL_ONLINE },
-        { 0x10525c, 1, RI_ALL_OFFLINE }, { 0x105260, 3, RI_ALL_ONLINE },
-        { 0x10526c, 1, RI_ALL_OFFLINE }, { 0x105270, 3, RI_ALL_ONLINE },
-        { 0x10527c, 1, RI_ALL_OFFLINE }, { 0x105280, 3, RI_ALL_ONLINE },
-        { 0x10528c, 1, RI_ALL_OFFLINE }, { 0x105290, 3, RI_ALL_ONLINE },
-        { 0x10529c, 1, RI_ALL_OFFLINE }, { 0x1052a0, 3, RI_ALL_ONLINE },
-        { 0x1052ac, 1, RI_ALL_OFFLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
-        { 0x1052bc, 1, RI_ALL_OFFLINE }, { 0x1052c0, 3, RI_ALL_ONLINE },
-        { 0x1052cc, 1, RI_ALL_OFFLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
-        { 0x1052dc, 1, RI_ALL_OFFLINE }, { 0x1052e0, 3, RI_ALL_ONLINE },
-        { 0x1052ec, 1, RI_ALL_OFFLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
-        { 0x1052fc, 1, RI_ALL_OFFLINE }, { 0x105300, 3, RI_ALL_ONLINE },
-        { 0x10530c, 1, RI_ALL_OFFLINE }, { 0x105310, 3, RI_ALL_ONLINE },
-        { 0x10531c, 1, RI_ALL_OFFLINE }, { 0x105320, 3, RI_ALL_ONLINE },
-        { 0x10532c, 1, RI_ALL_OFFLINE }, { 0x105330, 3, RI_ALL_ONLINE },
-        { 0x10533c, 1, RI_ALL_OFFLINE }, { 0x105340, 3, RI_ALL_ONLINE },
-        { 0x10534c, 1, RI_ALL_OFFLINE }, { 0x105350, 3, RI_ALL_ONLINE },
-        { 0x10535c, 1, RI_ALL_OFFLINE }, { 0x105360, 3, RI_ALL_ONLINE },
-        { 0x10536c, 1, RI_ALL_OFFLINE }, { 0x105370, 3, RI_ALL_ONLINE },
-        { 0x10537c, 1, RI_ALL_OFFLINE }, { 0x105380, 3, RI_ALL_ONLINE },
-        { 0x10538c, 1, RI_ALL_OFFLINE }, { 0x105390, 3, RI_ALL_ONLINE },
-        { 0x10539c, 1, RI_ALL_OFFLINE }, { 0x1053a0, 3, RI_ALL_ONLINE },
-        { 0x1053ac, 1, RI_ALL_OFFLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
-        { 0x1053bc, 1, RI_ALL_OFFLINE }, { 0x1053c0, 3, RI_ALL_ONLINE },
-        { 0x1053cc, 1, RI_ALL_OFFLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
-        { 0x1053dc, 1, RI_ALL_OFFLINE }, { 0x1053e0, 3, RI_ALL_ONLINE },
-        { 0x1053ec, 1, RI_ALL_OFFLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
-        { 0x1053fc, 769, RI_ALL_OFFLINE }, { 0x108000, 33, RI_ALL_ONLINE },
-        { 0x108090, 1, RI_ALL_ONLINE }, { 0x1080a0, 1, RI_ALL_ONLINE },
-        { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_ALL_ONLINE },
-        { 0x108120, 5, RI_ALL_ONLINE }, { 0x108200, 74, RI_ALL_ONLINE },
-        { 0x108400, 74, RI_ALL_ONLINE }, { 0x108800, 152, RI_ALL_ONLINE },
-        { 0x109000, 1, RI_ALL_ONLINE }, { 0x120000, 347, RI_ALL_ONLINE },
-        { 0x120578, 1, RI_ALL_ONLINE }, { 0x120588, 1, RI_ALL_ONLINE },
-        { 0x120598, 1, RI_ALL_ONLINE }, { 0x12059c, 23, RI_E1H_ONLINE },
-        { 0x120614, 1, RI_E1H_ONLINE }, { 0x12061c, 30, RI_E1H_ONLINE },
-        { 0x12080c, 65, RI_ALL_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE },
-        { 0x122000, 2, RI_ALL_ONLINE }, { 0x128000, 2, RI_E1H_ONLINE },
-        { 0x140000, 114, RI_ALL_ONLINE }, { 0x1401d4, 1, RI_ALL_ONLINE },
-        { 0x1401e4, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
-        { 0x144000, 4, RI_ALL_ONLINE }, { 0x148000, 4, RI_ALL_ONLINE },
-        { 0x14c000, 4, RI_ALL_ONLINE }, { 0x150000, 4, RI_ALL_ONLINE },
-        { 0x154000, 4, RI_ALL_ONLINE }, { 0x158000, 4, RI_ALL_ONLINE },
-        { 0x15c000, 7, RI_E1H_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE },
-        { 0x161028, 1, RI_ALL_ONLINE }, { 0x161038, 1, RI_ALL_ONLINE },
-        { 0x161800, 2, RI_ALL_ONLINE }, { 0x164000, 60, RI_ALL_ONLINE },
-        { 0x1640fc, 1, RI_ALL_ONLINE }, { 0x16410c, 1, RI_ALL_ONLINE },
-        { 0x164110, 2, RI_E1H_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE },
+        { 0x10411c, 16, RI_E2_ONLINE }, { 0x104200, 17, RI_ALL_ONLINE },
+        { 0x104400, 64, RI_ALL_ONLINE }, { 0x104500, 192, RI_ALL_OFFLINE },
+        { 0x104800, 64, RI_ALL_ONLINE }, { 0x104900, 192, RI_ALL_OFFLINE },
+        { 0x105000, 256, RI_ALL_ONLINE }, { 0x105400, 768, RI_ALL_OFFLINE },
+        { 0x107000, 7, RI_E2_ONLINE }, { 0x108000, 33, RI_E1E1H_ONLINE },
+        { 0x1080ac, 5, RI_E1H_ONLINE }, { 0x108100, 5, RI_E1E1H_ONLINE },
+        { 0x108120, 5, RI_E1E1H_ONLINE }, { 0x108200, 74, RI_E1E1H_ONLINE },
+        { 0x108400, 74, RI_E1E1H_ONLINE }, { 0x108800, 152, RI_E1E1H_ONLINE },
+        { 0x110000, 111, RI_E2_ONLINE }, { 0x110200, 4, RI_E2_ONLINE },
+        { 0x120000, 2, RI_ALL_ONLINE }, { 0x120008, 4, RI_ALL_ONLINE },
+        { 0x120018, 3, RI_ALL_ONLINE }, { 0x120024, 4, RI_ALL_ONLINE },
+        { 0x120034, 3, RI_ALL_ONLINE }, { 0x120040, 4, RI_ALL_ONLINE },
+        { 0x120050, 3, RI_ALL_ONLINE }, { 0x12005c, 4, RI_ALL_ONLINE },
+        { 0x12006c, 3, RI_ALL_ONLINE }, { 0x120078, 4, RI_ALL_ONLINE },
+        { 0x120088, 3, RI_ALL_ONLINE }, { 0x120094, 4, RI_ALL_ONLINE },
+        { 0x1200a4, 3, RI_ALL_ONLINE }, { 0x1200b0, 4, RI_ALL_ONLINE },
+        { 0x1200c0, 3, RI_ALL_ONLINE }, { 0x1200cc, 4, RI_ALL_ONLINE },
+        { 0x1200dc, 3, RI_ALL_ONLINE }, { 0x1200e8, 4, RI_ALL_ONLINE },
+        { 0x1200f8, 3, RI_ALL_ONLINE }, { 0x120104, 4, RI_ALL_ONLINE },
+        { 0x120114, 1, RI_ALL_ONLINE }, { 0x120118, 22, RI_ALL_ONLINE },
+        { 0x120170, 2, RI_E1E1H_ONLINE }, { 0x120178, 243, RI_ALL_ONLINE },
+        { 0x120544, 4, RI_E1E1H_ONLINE }, { 0x120554, 7, RI_ALL_ONLINE },
+        { 0x12059c, 6, RI_E1HE2_ONLINE }, { 0x1205b4, 1, RI_E1HE2_ONLINE },
+        { 0x1205b8, 16, RI_E1HE2_ONLINE }, { 0x1205f8, 4, RI_E2_ONLINE },
+        { 0x120618, 1, RI_E2_ONLINE }, { 0x12061c, 20, RI_E1HE2_ONLINE },
+        { 0x12066c, 11, RI_E1HE2_ONLINE }, { 0x120698, 5, RI_E2_ONLINE },
+        { 0x1206b0, 76, RI_E2_ONLINE }, { 0x1207fc, 1, RI_E2_ONLINE },
+        { 0x120808, 66, RI_ALL_ONLINE }, { 0x120910, 7, RI_E2_ONLINE },
+        { 0x120930, 9, RI_E2_ONLINE }, { 0x120a00, 2, RI_ALL_ONLINE },
+        { 0x122000, 2, RI_ALL_ONLINE }, { 0x122008, 2046, RI_E1_OFFLINE },
+        { 0x128000, 2, RI_E1HE2_ONLINE }, { 0x128008, 6142, RI_E1HE2_OFFLINE },
+        { 0x130000, 35, RI_E2_ONLINE }, { 0x130100, 29, RI_E2_ONLINE },
+        { 0x130180, 1, RI_E2_ONLINE }, { 0x130200, 1, RI_E2_ONLINE },
+        { 0x130280, 1, RI_E2_ONLINE }, { 0x130300, 5, RI_E2_ONLINE },
+        { 0x130380, 1, RI_E2_ONLINE }, { 0x130400, 1, RI_E2_ONLINE },
+        { 0x130480, 5, RI_E2_ONLINE }, { 0x130800, 72, RI_E2_ONLINE },
+        { 0x131000, 136, RI_E2_ONLINE }, { 0x132000, 148, RI_E2_ONLINE },
+        { 0x134000, 544, RI_E2_ONLINE }, { 0x140000, 64, RI_ALL_ONLINE },
+        { 0x140100, 5, RI_E1E1H_ONLINE }, { 0x140114, 45, RI_ALL_ONLINE },
+        { 0x140200, 6, RI_ALL_ONLINE }, { 0x140220, 4, RI_E2_ONLINE },
+        { 0x140240, 4, RI_E2_ONLINE }, { 0x140260, 4, RI_E2_ONLINE },
+        { 0x140280, 4, RI_E2_ONLINE }, { 0x1402a0, 4, RI_E2_ONLINE },
+        { 0x1402c0, 4, RI_E2_ONLINE }, { 0x1402e0, 13, RI_E2_ONLINE },
+        { 0x144000, 4, RI_E1E1H_ONLINE }, { 0x148000, 4, RI_E1E1H_ONLINE },
+        { 0x14c000, 4, RI_E1E1H_ONLINE }, { 0x150000, 4, RI_E1E1H_ONLINE },
+        { 0x154000, 4, RI_E1E1H_ONLINE }, { 0x158000, 4, RI_E1E1H_ONLINE },
+        { 0x15c000, 2, RI_E1HE2_ONLINE }, { 0x15c008, 5, RI_E1H_ONLINE },
+        { 0x15c020, 27, RI_E2_ONLINE }, { 0x15c090, 13, RI_E2_ONLINE },
+        { 0x15c0c8, 34, RI_E2_ONLINE }, { 0x161000, 7, RI_ALL_ONLINE },
+        { 0x16103c, 2, RI_E2_ONLINE }, { 0x161800, 2, RI_ALL_ONLINE },
+        { 0x164000, 60, RI_ALL_ONLINE }, { 0x164110, 2, RI_E1HE2_ONLINE },
+        { 0x164118, 15, RI_E2_ONLINE }, { 0x164200, 1, RI_ALL_ONLINE },
         { 0x164208, 1, RI_ALL_ONLINE }, { 0x164210, 1, RI_ALL_ONLINE },
         { 0x164218, 1, RI_ALL_ONLINE }, { 0x164220, 1, RI_ALL_ONLINE },
         { 0x164228, 1, RI_ALL_ONLINE }, { 0x164230, 1, RI_ALL_ONLINE },
@@ -284,169 +273,298 @@ static const struct reg_addr reg_addrs[REGS_COUNT] = {
         { 0x164258, 1, RI_ALL_ONLINE }, { 0x164260, 1, RI_ALL_ONLINE },
         { 0x164270, 2, RI_ALL_ONLINE }, { 0x164280, 2, RI_ALL_ONLINE },
         { 0x164800, 2, RI_ALL_ONLINE }, { 0x165000, 2, RI_ALL_ONLINE },
-        { 0x166000, 164, RI_ALL_ONLINE }, { 0x16629c, 1, RI_ALL_ONLINE },
-        { 0x1662ac, 1, RI_ALL_ONLINE }, { 0x1662bc, 1, RI_ALL_ONLINE },
+        { 0x166000, 164, RI_ALL_ONLINE }, { 0x1662cc, 7, RI_E2_ONLINE },
         { 0x166400, 49, RI_ALL_ONLINE }, { 0x1664c8, 38, RI_ALL_ONLINE },
-        { 0x166568, 2, RI_ALL_ONLINE }, { 0x166800, 1, RI_ALL_ONLINE },
-        { 0x168000, 270, RI_ALL_ONLINE }, { 0x168444, 1, RI_ALL_ONLINE },
-        { 0x168454, 1, RI_ALL_ONLINE }, { 0x168800, 19, RI_ALL_ONLINE },
-        { 0x168900, 1, RI_ALL_ONLINE }, { 0x168a00, 128, RI_ALL_ONLINE },
-        { 0x16a000, 1, RI_ALL_ONLINE }, { 0x16a004, 1535, RI_ALL_OFFLINE },
-        { 0x16c000, 1, RI_ALL_ONLINE }, { 0x16c004, 1535, RI_ALL_OFFLINE },
-        { 0x16e000, 16, RI_E1H_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE },
-        { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 183, RI_E1H_ONLINE },
-        { 0x170000, 93, RI_ALL_ONLINE }, { 0x170180, 1, RI_ALL_ONLINE },
-        { 0x170190, 1, RI_ALL_ONLINE }, { 0x170200, 4, RI_ALL_ONLINE },
-        { 0x170214, 1, RI_ALL_ONLINE }, { 0x178000, 1, RI_ALL_ONLINE },
-        { 0x180000, 61, RI_ALL_ONLINE }, { 0x180100, 1, RI_ALL_ONLINE },
-        { 0x180110, 1, RI_ALL_ONLINE }, { 0x180120, 1, RI_ALL_ONLINE },
-        { 0x180130, 1, RI_ALL_ONLINE }, { 0x18013c, 2, RI_E1H_ONLINE },
-        { 0x180200, 58, RI_ALL_ONLINE }, { 0x180340, 4, RI_ALL_ONLINE },
-        { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_ALL_OFFLINE },
+        { 0x166568, 2, RI_ALL_ONLINE }, { 0x166570, 5, RI_E2_ONLINE },
+        { 0x166800, 1, RI_ALL_ONLINE }, { 0x168000, 137, RI_ALL_ONLINE },
+        { 0x168224, 2, RI_E1E1H_ONLINE }, { 0x16822c, 29, RI_ALL_ONLINE },
+        { 0x1682a0, 12, RI_E1E1H_ONLINE }, { 0x1682d0, 12, RI_ALL_ONLINE },
+        { 0x168300, 2, RI_E1E1H_ONLINE }, { 0x168308, 68, RI_ALL_ONLINE },
+        { 0x168418, 2, RI_E1E1H_ONLINE }, { 0x168420, 6, RI_ALL_ONLINE },
+        { 0x168800, 19, RI_ALL_ONLINE }, { 0x168900, 1, RI_ALL_ONLINE },
+        { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16a000, 1, RI_ALL_ONLINE },
+        { 0x16a004, 1535, RI_ALL_OFFLINE }, { 0x16c000, 1, RI_ALL_ONLINE },
+        { 0x16c004, 1535, RI_ALL_OFFLINE }, { 0x16e000, 16, RI_E1H_ONLINE },
+        { 0x16e040, 8, RI_E2_ONLINE }, { 0x16e100, 1, RI_E1H_ONLINE },
+        { 0x16e200, 2, RI_E1H_ONLINE }, { 0x16e400, 161, RI_E1H_ONLINE },
+        { 0x16e684, 2, RI_E1HE2_ONLINE }, { 0x16e68c, 12, RI_E1H_ONLINE },
+        { 0x16e6bc, 4, RI_E1HE2_ONLINE }, { 0x16e6cc, 4, RI_E1H_ONLINE },
+        { 0x16e6e0, 12, RI_E2_ONLINE }, { 0x16e768, 17, RI_E2_ONLINE },
+        { 0x170000, 24, RI_ALL_ONLINE }, { 0x170060, 4, RI_E1E1H_ONLINE },
+        { 0x170070, 65, RI_ALL_ONLINE }, { 0x170194, 11, RI_E2_ONLINE },
+        { 0x1701c4, 1, RI_E2_ONLINE }, { 0x1701cc, 7, RI_E2_ONLINE },
+        { 0x1701ec, 1, RI_E2_ONLINE }, { 0x1701f4, 1, RI_E2_ONLINE },
+        { 0x170200, 4, RI_ALL_ONLINE }, { 0x170214, 1, RI_ALL_ONLINE },
+        { 0x170218, 77, RI_E2_ONLINE }, { 0x170400, 64, RI_E2_ONLINE },
+        { 0x178000, 1, RI_ALL_ONLINE }, { 0x180000, 61, RI_ALL_ONLINE },
+        { 0x18013c, 2, RI_E1HE2_ONLINE }, { 0x180200, 58, RI_ALL_ONLINE },
+        { 0x180340, 4, RI_ALL_ONLINE }, { 0x180380, 1, RI_E2_ONLINE },
+        { 0x180388, 1, RI_E2_ONLINE }, { 0x180390, 1, RI_E2_ONLINE },
+        { 0x180398, 1, RI_E2_ONLINE }, { 0x1803a0, 5, RI_E2_ONLINE },
+        { 0x180400, 1, RI_ALL_ONLINE }, { 0x180404, 255, RI_E1E1H_OFFLINE },
         { 0x181000, 4, RI_ALL_ONLINE }, { 0x181010, 1020, RI_ALL_OFFLINE },
-        { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 1023, RI_ALL_OFFLINE },
-        { 0x1a1000, 1, RI_ALL_ONLINE }, { 0x1a1004, 4607, RI_ALL_OFFLINE },
-        { 0x1a5800, 2560, RI_E1H_OFFLINE }, { 0x1a8000, 64, RI_ALL_OFFLINE },
-        { 0x1a8100, 1984, RI_E1H_OFFLINE }, { 0x1aa000, 1, RI_E1H_ONLINE },
-        { 0x1aa004, 6655, RI_E1H_OFFLINE }, { 0x1b1800, 128, RI_ALL_OFFLINE },
-        { 0x1b1c00, 128, RI_ALL_OFFLINE }, { 0x1b2000, 1, RI_ALL_OFFLINE },
-        { 0x1b2400, 64, RI_E1H_OFFLINE }, { 0x1b8200, 1, RI_ALL_ONLINE },
+        { 0x1a0000, 1, RI_ALL_ONLINE }, { 0x1a0004, 5631, RI_ALL_OFFLINE },
+        { 0x1a5800, 2560, RI_E1HE2_OFFLINE }, { 0x1a8000, 1, RI_ALL_ONLINE },
+        { 0x1a8004, 8191, RI_E1HE2_OFFLINE }, { 0x1b0000, 1, RI_ALL_ONLINE },
+        { 0x1b0004, 15, RI_E1H_OFFLINE }, { 0x1b0040, 1, RI_E1HE2_ONLINE },
+        { 0x1b0044, 239, RI_E1H_OFFLINE }, { 0x1b0400, 1, RI_ALL_ONLINE },
+        { 0x1b0404, 255, RI_E1H_OFFLINE }, { 0x1b0800, 1, RI_ALL_ONLINE },
+        { 0x1b0840, 1, RI_E1HE2_ONLINE }, { 0x1b0c00, 1, RI_ALL_ONLINE },
+        { 0x1b1000, 1, RI_ALL_ONLINE }, { 0x1b1040, 1, RI_E1HE2_ONLINE },
+        { 0x1b1400, 1, RI_ALL_ONLINE }, { 0x1b1440, 1, RI_E1HE2_ONLINE },
+        { 0x1b1480, 1, RI_E1HE2_ONLINE }, { 0x1b14c0, 1, RI_E1HE2_ONLINE },
+        { 0x1b1800, 128, RI_ALL_OFFLINE }, { 0x1b1c00, 128, RI_ALL_OFFLINE },
+        { 0x1b2000, 1, RI_ALL_ONLINE }, { 0x1b2400, 1, RI_E1HE2_ONLINE },
+        { 0x1b2404, 5631, RI_E2_OFFLINE }, { 0x1b8000, 1, RI_ALL_ONLINE },
+        { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE },
+        { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x1b8100, 1, RI_ALL_ONLINE },
+        { 0x1b8140, 1, RI_ALL_ONLINE }, { 0x1b8180, 1, RI_ALL_ONLINE },
+        { 0x1b81c0, 1, RI_ALL_ONLINE }, { 0x1b8200, 1, RI_ALL_ONLINE },
         { 0x1b8240, 1, RI_ALL_ONLINE }, { 0x1b8280, 1, RI_ALL_ONLINE },
-        { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE },
-        { 0x1b8a80, 1, RI_ALL_ONLINE }, { 0x1c0000, 2, RI_ALL_ONLINE },
-        { 0x200000, 65, RI_ALL_ONLINE }, { 0x200110, 1, RI_ALL_ONLINE },
-        { 0x200120, 1, RI_ALL_ONLINE }, { 0x200130, 1, RI_ALL_ONLINE },
-        { 0x200140, 1, RI_ALL_ONLINE }, { 0x20014c, 2, RI_E1H_ONLINE },
-        { 0x200200, 58, RI_ALL_ONLINE }, { 0x200340, 4, RI_ALL_ONLINE },
-        { 0x200400, 1, RI_ALL_ONLINE }, { 0x200404, 255, RI_ALL_OFFLINE },
-        { 0x202000, 4, RI_ALL_ONLINE }, { 0x202010, 2044, RI_ALL_OFFLINE },
-        { 0x220000, 1, RI_ALL_ONLINE }, { 0x220004, 1023, RI_ALL_OFFLINE },
-        { 0x221000, 1, RI_ALL_ONLINE }, { 0x221004, 4607, RI_ALL_OFFLINE },
-        { 0x225800, 1536, RI_E1H_OFFLINE }, { 0x227000, 1, RI_E1H_ONLINE },
-        { 0x227004, 1023, RI_E1H_OFFLINE }, { 0x228000, 64, RI_ALL_OFFLINE },
-        { 0x228100, 8640, RI_E1H_OFFLINE }, { 0x231800, 128, RI_ALL_OFFLINE },
-        { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_OFFLINE },
-        { 0x232400, 64, RI_E1H_OFFLINE }, { 0x238200, 1, RI_ALL_ONLINE },
-        { 0x238240, 1, RI_ALL_ONLINE }, { 0x238280, 1, RI_ALL_ONLINE },
-        { 0x2382c0, 1, RI_ALL_ONLINE }, { 0x238a00, 1, RI_ALL_ONLINE },
-        { 0x238a80, 1, RI_ALL_ONLINE }, { 0x240000, 2, RI_ALL_ONLINE },
-        { 0x280000, 65, RI_ALL_ONLINE }, { 0x280110, 1, RI_ALL_ONLINE },
-        { 0x280120, 1, RI_ALL_ONLINE }, { 0x280130, 1, RI_ALL_ONLINE },
-        { 0x280140, 1, RI_ALL_ONLINE }, { 0x28014c, 2, RI_E1H_ONLINE },
-        { 0x280200, 58, RI_ALL_ONLINE }, { 0x280340, 4, RI_ALL_ONLINE },
-        { 0x280400, 1, RI_ALL_ONLINE }, { 0x280404, 255, RI_ALL_OFFLINE },
-        { 0x282000, 4, RI_ALL_ONLINE }, { 0x282010, 2044, RI_ALL_OFFLINE },
-        { 0x2a0000, 1, RI_ALL_ONLINE }, { 0x2a0004, 1023, RI_ALL_OFFLINE },
-        { 0x2a1000, 1, RI_ALL_ONLINE }, { 0x2a1004, 4607, RI_ALL_OFFLINE },
-        { 0x2a5800, 2560, RI_E1H_OFFLINE }, { 0x2a8000, 64, RI_ALL_OFFLINE },
-        { 0x2a8100, 960, RI_E1H_OFFLINE }, { 0x2a9000, 1, RI_E1H_ONLINE },
-        { 0x2a9004, 7679, RI_E1H_OFFLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE },
-        { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_OFFLINE },
-        { 0x2b2400, 64, RI_E1H_OFFLINE }, { 0x2b8200, 1, RI_ALL_ONLINE },
-        { 0x2b8240, 1, RI_ALL_ONLINE }, { 0x2b8280, 1, RI_ALL_ONLINE },
-        { 0x2b82c0, 1, RI_ALL_ONLINE }, { 0x2b8a00, 1, RI_ALL_ONLINE },
-        { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE },
-        { 0x300000, 65, RI_ALL_ONLINE }, { 0x300110, 1, RI_ALL_ONLINE },
-        { 0x300120, 1, RI_ALL_ONLINE }, { 0x300130, 1, RI_ALL_ONLINE },
-        { 0x300140, 1, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1H_ONLINE },
+        { 0x1b82c0, 1, RI_ALL_ONLINE }, { 0x1b8300, 1, RI_ALL_ONLINE },
+        { 0x1b8340, 1, RI_ALL_ONLINE }, { 0x1b8380, 1, RI_ALL_ONLINE },
+        { 0x1b83c0, 1, RI_ALL_ONLINE }, { 0x1b8400, 1, RI_ALL_ONLINE },
+        { 0x1b8440, 1, RI_ALL_ONLINE }, { 0x1b8480, 1, RI_ALL_ONLINE },
+        { 0x1b84c0, 1, RI_ALL_ONLINE }, { 0x1b8500, 1, RI_ALL_ONLINE },
+        { 0x1b8540, 1, RI_ALL_ONLINE }, { 0x1b8580, 1, RI_ALL_ONLINE },
+        { 0x1b85c0, 19, RI_E2_ONLINE }, { 0x1b8800, 1, RI_ALL_ONLINE },
+        { 0x1b8840, 1, RI_ALL_ONLINE }, { 0x1b8880, 1, RI_ALL_ONLINE },
+        { 0x1b88c0, 1, RI_ALL_ONLINE }, { 0x1b8900, 1, RI_ALL_ONLINE },
+        { 0x1b8940, 1, RI_ALL_ONLINE }, { 0x1b8980, 1, RI_ALL_ONLINE },
+        { 0x1b89c0, 1, RI_ALL_ONLINE }, { 0x1b8a00, 1, RI_ALL_ONLINE },
+        { 0x1b8a40, 1, RI_ALL_ONLINE }, { 0x1b8a80, 1, RI_ALL_ONLINE },
+        { 0x1b8ac0, 1, RI_ALL_ONLINE }, { 0x1b8b00, 1, RI_ALL_ONLINE },
+        { 0x1b8b40, 1, RI_ALL_ONLINE }, { 0x1b8b80, 1, RI_ALL_ONLINE },
+        { 0x1b8bc0, 1, RI_ALL_ONLINE }, { 0x1b8c00, 1, RI_ALL_ONLINE },
+        { 0x1b8c40, 1, RI_ALL_ONLINE }, { 0x1b8c80, 1, RI_ALL_ONLINE },
+        { 0x1b8cc0, 1, RI_ALL_ONLINE }, { 0x1b8cc4, 1, RI_E2_ONLINE },
+        { 0x1b8d00, 1, RI_ALL_ONLINE }, { 0x1b8d40, 1, RI_ALL_ONLINE },
+        { 0x1b8d80, 1, RI_ALL_ONLINE }, { 0x1b8dc0, 1, RI_ALL_ONLINE },
+        { 0x1b8e00, 1, RI_ALL_ONLINE }, { 0x1b8e40, 1, RI_ALL_ONLINE },
+        { 0x1b8e80, 1, RI_ALL_ONLINE }, { 0x1b8e84, 1, RI_E2_ONLINE },
+        { 0x1b8ec0, 1, RI_E1HE2_ONLINE }, { 0x1b8f00, 1, RI_E1HE2_ONLINE },
+        { 0x1b8f40, 1, RI_E1HE2_ONLINE }, { 0x1b8f80, 1, RI_E1HE2_ONLINE },
+        { 0x1b8fc0, 1, RI_E1HE2_ONLINE }, { 0x1b8fc4, 2, RI_E2_ONLINE },
+        { 0x1b8fd0, 6, RI_E2_ONLINE }, { 0x1b9000, 1, RI_E2_ONLINE },
+        { 0x1b9040, 3, RI_E2_ONLINE }, { 0x1b9400, 14, RI_E2_ONLINE },
+        { 0x1b943c, 19, RI_E2_ONLINE }, { 0x1b9490, 10, RI_E2_ONLINE },
+        { 0x1c0000, 2, RI_ALL_ONLINE }, { 0x200000, 65, RI_ALL_ONLINE },
+        { 0x20014c, 2, RI_E1HE2_ONLINE }, { 0x200200, 58, RI_ALL_ONLINE },
+        { 0x200340, 4, RI_ALL_ONLINE }, { 0x200380, 1, RI_E2_ONLINE },
+        { 0x200388, 1, RI_E2_ONLINE }, { 0x200390, 1, RI_E2_ONLINE },
+        { 0x200398, 1, RI_E2_ONLINE }, { 0x2003a0, 1, RI_E2_ONLINE },
+        { 0x2003a8, 2, RI_E2_ONLINE }, { 0x200400, 1, RI_ALL_ONLINE },
+        { 0x200404, 255, RI_E1E1H_OFFLINE }, { 0x202000, 4, RI_ALL_ONLINE },
+        { 0x202010, 2044, RI_ALL_OFFLINE }, { 0x220000, 1, RI_ALL_ONLINE },
+        { 0x220004, 5631, RI_ALL_OFFLINE }, { 0x225800, 2560, RI_E1HE2_OFFLINE},
+        { 0x228000, 1, RI_ALL_ONLINE }, { 0x228004, 8191, RI_E1HE2_OFFLINE },
+        { 0x230000, 1, RI_ALL_ONLINE }, { 0x230004, 15, RI_E1H_OFFLINE },
+        { 0x230040, 1, RI_E1HE2_ONLINE }, { 0x230044, 239, RI_E1H_OFFLINE },
+        { 0x230400, 1, RI_ALL_ONLINE }, { 0x230404, 255, RI_E1H_OFFLINE },
+        { 0x230800, 1, RI_ALL_ONLINE }, { 0x230840, 1, RI_E1HE2_ONLINE },
+        { 0x230c00, 1, RI_ALL_ONLINE }, { 0x231000, 1, RI_ALL_ONLINE },
+        { 0x231040, 1, RI_E1HE2_ONLINE }, { 0x231400, 1, RI_ALL_ONLINE },
+        { 0x231440, 1, RI_E1HE2_ONLINE }, { 0x231480, 1, RI_E1HE2_ONLINE },
+        { 0x2314c0, 1, RI_E1HE2_ONLINE }, { 0x231800, 128, RI_ALL_OFFLINE },
+        { 0x231c00, 128, RI_ALL_OFFLINE }, { 0x232000, 1, RI_ALL_ONLINE },
+        { 0x232400, 1, RI_E1HE2_ONLINE }, { 0x232404, 5631, RI_E2_OFFLINE },
+        { 0x238000, 1, RI_ALL_ONLINE }, { 0x238040, 1, RI_ALL_ONLINE },
+        { 0x238080, 1, RI_ALL_ONLINE }, { 0x2380c0, 1, RI_ALL_ONLINE },
+        { 0x238100, 1, RI_ALL_ONLINE }, { 0x238140, 1, RI_ALL_ONLINE },
+        { 0x238180, 1, RI_ALL_ONLINE }, { 0x2381c0, 1, RI_ALL_ONLINE },
+        { 0x238200, 1, RI_ALL_ONLINE }, { 0x238240, 1, RI_ALL_ONLINE },
+        { 0x238280, 1, RI_ALL_ONLINE }, { 0x2382c0, 1, RI_ALL_ONLINE },
+        { 0x238300, 1, RI_ALL_ONLINE }, { 0x238340, 1, RI_ALL_ONLINE },
+        { 0x238380, 1, RI_ALL_ONLINE }, { 0x2383c0, 1, RI_ALL_ONLINE },
+        { 0x238400, 1, RI_ALL_ONLINE }, { 0x238440, 1, RI_ALL_ONLINE },
+        { 0x238480, 1, RI_ALL_ONLINE }, { 0x2384c0, 1, RI_ALL_ONLINE },
+        { 0x238500, 1, RI_ALL_ONLINE }, { 0x238540, 1, RI_ALL_ONLINE },
+        { 0x238580, 1, RI_ALL_ONLINE }, { 0x2385c0, 19, RI_E2_ONLINE },
+        { 0x238800, 1, RI_ALL_ONLINE }, { 0x238840, 1, RI_ALL_ONLINE },
+        { 0x238880, 1, RI_ALL_ONLINE }, { 0x2388c0, 1, RI_ALL_ONLINE },
+        { 0x238900, 1, RI_ALL_ONLINE }, { 0x238940, 1, RI_ALL_ONLINE },
+        { 0x238980, 1, RI_ALL_ONLINE }, { 0x2389c0, 1, RI_ALL_ONLINE },
+        { 0x238a00, 1, RI_ALL_ONLINE }, { 0x238a40, 1, RI_ALL_ONLINE },
+        { 0x238a80, 1, RI_ALL_ONLINE }, { 0x238ac0, 1, RI_ALL_ONLINE },
+        { 0x238b00, 1, RI_ALL_ONLINE }, { 0x238b40, 1, RI_ALL_ONLINE },
+        { 0x238b80, 1, RI_ALL_ONLINE }, { 0x238bc0, 1, RI_ALL_ONLINE },
+        { 0x238c00, 1, RI_ALL_ONLINE }, { 0x238c40, 1, RI_ALL_ONLINE },
+        { 0x238c80, 1, RI_ALL_ONLINE }, { 0x238cc0, 1, RI_ALL_ONLINE },
+        { 0x238cc4, 1, RI_E2_ONLINE }, { 0x238d00, 1, RI_ALL_ONLINE },
+        { 0x238d40, 1, RI_ALL_ONLINE }, { 0x238d80, 1, RI_ALL_ONLINE },
+        { 0x238dc0, 1, RI_ALL_ONLINE }, { 0x238e00, 1, RI_ALL_ONLINE },
+        { 0x238e40, 1, RI_ALL_ONLINE }, { 0x238e80, 1, RI_ALL_ONLINE },
+        { 0x238e84, 1, RI_E2_ONLINE }, { 0x238ec0, 1, RI_E1HE2_ONLINE },
+        { 0x238f00, 1, RI_E1HE2_ONLINE }, { 0x238f40, 1, RI_E1HE2_ONLINE },
+        { 0x238f80, 1, RI_E1HE2_ONLINE }, { 0x238fc0, 1, RI_E1HE2_ONLINE },
+        { 0x238fc4, 2, RI_E2_ONLINE }, { 0x238fd0, 6, RI_E2_ONLINE },
+        { 0x239000, 1, RI_E2_ONLINE }, { 0x239040, 3, RI_E2_ONLINE },
+        { 0x240000, 2, RI_ALL_ONLINE }, { 0x280000, 65, RI_ALL_ONLINE },
+        { 0x28014c, 2, RI_E1HE2_ONLINE }, { 0x280200, 58, RI_ALL_ONLINE },
+        { 0x280340, 4, RI_ALL_ONLINE }, { 0x280380, 1, RI_E2_ONLINE },
+        { 0x280388, 1, RI_E2_ONLINE }, { 0x280390, 1, RI_E2_ONLINE },
+        { 0x280398, 1, RI_E2_ONLINE }, { 0x2803a0, 1, RI_E2_ONLINE },
+        { 0x2803a8, 2, RI_E2_ONLINE }, { 0x280400, 1, RI_ALL_ONLINE },
+        { 0x280404, 255, RI_E1E1H_OFFLINE }, { 0x282000, 4, RI_ALL_ONLINE },
+        { 0x282010, 2044, RI_ALL_OFFLINE }, { 0x2a0000, 1, RI_ALL_ONLINE },
+        { 0x2a0004, 5631, RI_ALL_OFFLINE }, { 0x2a5800, 2560, RI_E1HE2_OFFLINE},
+        { 0x2a8000, 1, RI_ALL_ONLINE }, { 0x2a8004, 8191, RI_E1HE2_OFFLINE },
+        { 0x2b0000, 1, RI_ALL_ONLINE }, { 0x2b0004, 15, RI_E1H_OFFLINE },
+        { 0x2b0040, 1, RI_E1HE2_ONLINE }, { 0x2b0044, 239, RI_E1H_OFFLINE },
+        { 0x2b0400, 1, RI_ALL_ONLINE }, { 0x2b0404, 255, RI_E1H_OFFLINE },
+        { 0x2b0800, 1, RI_ALL_ONLINE }, { 0x2b0840, 1, RI_E1HE2_ONLINE },
+        { 0x2b0c00, 1, RI_ALL_ONLINE }, { 0x2b1000, 1, RI_ALL_ONLINE },
+        { 0x2b1040, 1, RI_E1HE2_ONLINE }, { 0x2b1400, 1, RI_ALL_ONLINE },
+        { 0x2b1440, 1, RI_E1HE2_ONLINE }, { 0x2b1480, 1, RI_E1HE2_ONLINE },
+        { 0x2b14c0, 1, RI_E1HE2_ONLINE }, { 0x2b1800, 128, RI_ALL_OFFLINE },
+        { 0x2b1c00, 128, RI_ALL_OFFLINE }, { 0x2b2000, 1, RI_ALL_ONLINE },
+        { 0x2b2400, 1, RI_E1HE2_ONLINE }, { 0x2b2404, 5631, RI_E2_OFFLINE },
+        { 0x2b8000, 1, RI_ALL_ONLINE }, { 0x2b8040, 1, RI_ALL_ONLINE },
+        { 0x2b8080, 1, RI_ALL_ONLINE }, { 0x2b80c0, 1, RI_ALL_ONLINE },
+        { 0x2b8100, 1, RI_ALL_ONLINE }, { 0x2b8140, 1, RI_ALL_ONLINE },
+        { 0x2b8180, 1, RI_ALL_ONLINE }, { 0x2b81c0, 1, RI_ALL_ONLINE },
+        { 0x2b8200, 1, RI_ALL_ONLINE }, { 0x2b8240, 1, RI_ALL_ONLINE },
+        { 0x2b8280, 1, RI_ALL_ONLINE }, { 0x2b82c0, 1, RI_ALL_ONLINE },
+        { 0x2b8300, 1, RI_ALL_ONLINE }, { 0x2b8340, 1, RI_ALL_ONLINE },
+        { 0x2b8380, 1, RI_ALL_ONLINE }, { 0x2b83c0, 1, RI_ALL_ONLINE },
+        { 0x2b8400, 1, RI_ALL_ONLINE }, { 0x2b8440, 1, RI_ALL_ONLINE },
+        { 0x2b8480, 1, RI_ALL_ONLINE }, { 0x2b84c0, 1, RI_ALL_ONLINE },
+        { 0x2b8500, 1, RI_ALL_ONLINE }, { 0x2b8540, 1, RI_ALL_ONLINE },
+        { 0x2b8580, 1, RI_ALL_ONLINE }, { 0x2b85c0, 19, RI_E2_ONLINE },
+        { 0x2b8800, 1, RI_ALL_ONLINE }, { 0x2b8840, 1, RI_ALL_ONLINE },
+        { 0x2b8880, 1, RI_ALL_ONLINE }, { 0x2b88c0, 1, RI_ALL_ONLINE },
+        { 0x2b8900, 1, RI_ALL_ONLINE }, { 0x2b8940, 1, RI_ALL_ONLINE },
+        { 0x2b8980, 1, RI_ALL_ONLINE }, { 0x2b89c0, 1, RI_ALL_ONLINE },
+        { 0x2b8a00, 1, RI_ALL_ONLINE }, { 0x2b8a40, 1, RI_ALL_ONLINE },
+        { 0x2b8a80, 1, RI_ALL_ONLINE }, { 0x2b8ac0, 1, RI_ALL_ONLINE },
+        { 0x2b8b00, 1, RI_ALL_ONLINE }, { 0x2b8b40, 1, RI_ALL_ONLINE },
+        { 0x2b8b80, 1, RI_ALL_ONLINE }, { 0x2b8bc0, 1, RI_ALL_ONLINE },
+        { 0x2b8c00, 1, RI_ALL_ONLINE }, { 0x2b8c40, 1, RI_ALL_ONLINE },
+        { 0x2b8c80, 1, RI_ALL_ONLINE }, { 0x2b8cc0, 1, RI_ALL_ONLINE },
+        { 0x2b8cc4, 1, RI_E2_ONLINE }, { 0x2b8d00, 1, RI_ALL_ONLINE },
+        { 0x2b8d40, 1, RI_ALL_ONLINE }, { 0x2b8d80, 1, RI_ALL_ONLINE },
+        { 0x2b8dc0, 1, RI_ALL_ONLINE }, { 0x2b8e00, 1, RI_ALL_ONLINE },
+        { 0x2b8e40, 1, RI_ALL_ONLINE }, { 0x2b8e80, 1, RI_ALL_ONLINE },
+        { 0x2b8e84, 1, RI_E2_ONLINE }, { 0x2b8ec0, 1, RI_E1HE2_ONLINE },
+        { 0x2b8f00, 1, RI_E1HE2_ONLINE }, { 0x2b8f40, 1, RI_E1HE2_ONLINE },
+        { 0x2b8f80, 1, RI_E1HE2_ONLINE }, { 0x2b8fc0, 1, RI_E1HE2_ONLINE },
+        { 0x2b8fc4, 2, RI_E2_ONLINE }, { 0x2b8fd0, 6, RI_E2_ONLINE },
+        { 0x2b9000, 1, RI_E2_ONLINE }, { 0x2b9040, 3, RI_E2_ONLINE },
+        { 0x2b9400, 14, RI_E2_ONLINE }, { 0x2b943c, 19, RI_E2_ONLINE },
+        { 0x2b9490, 10, RI_E2_ONLINE }, { 0x2c0000, 2, RI_ALL_ONLINE },
+        { 0x300000, 65, RI_ALL_ONLINE }, { 0x30014c, 2, RI_E1HE2_ONLINE },
         { 0x300200, 58, RI_ALL_ONLINE }, { 0x300340, 4, RI_ALL_ONLINE },
-        { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_ALL_OFFLINE },
+        { 0x300380, 1, RI_E2_ONLINE }, { 0x300388, 1, RI_E2_ONLINE },
+        { 0x300390, 1, RI_E2_ONLINE }, { 0x300398, 1, RI_E2_ONLINE },
+        { 0x3003a0, 1, RI_E2_ONLINE }, { 0x3003a8, 2, RI_E2_ONLINE },
+        { 0x300400, 1, RI_ALL_ONLINE }, { 0x300404, 255, RI_E1E1H_OFFLINE },
         { 0x302000, 4, RI_ALL_ONLINE }, { 0x302010, 2044, RI_ALL_OFFLINE },
-        { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 1023, RI_ALL_OFFLINE },
-        { 0x321000, 1, RI_ALL_ONLINE }, { 0x321004, 4607, RI_ALL_OFFLINE },
-        { 0x325800, 2560, RI_E1H_OFFLINE }, { 0x328000, 64, RI_ALL_OFFLINE },
-        { 0x328100, 536, RI_E1H_OFFLINE }, { 0x328960, 1, RI_E1H_ONLINE },
-        { 0x328964, 8103, RI_E1H_OFFLINE }, { 0x331800, 128, RI_ALL_OFFLINE },
-        { 0x331c00, 128, RI_ALL_OFFLINE }, { 0x332000, 1, RI_ALL_OFFLINE },
-        { 0x332400, 64, RI_E1H_OFFLINE }, { 0x338200, 1, RI_ALL_ONLINE },
+        { 0x320000, 1, RI_ALL_ONLINE }, { 0x320004, 5631, RI_ALL_OFFLINE },
+        { 0x325800, 2560, RI_E1HE2_OFFLINE }, { 0x328000, 1, RI_ALL_ONLINE },
+        { 0x328004, 8191, RI_E1HE2_OFFLINE }, { 0x330000, 1, RI_ALL_ONLINE },
+        { 0x330004, 15, RI_E1H_OFFLINE }, { 0x330040, 1, RI_E1HE2_ONLINE },
+        { 0x330044, 239, RI_E1H_OFFLINE }, { 0x330400, 1, RI_ALL_ONLINE },
+        { 0x330404, 255, RI_E1H_OFFLINE }, { 0x330800, 1, RI_ALL_ONLINE },
+        { 0x330840, 1, RI_E1HE2_ONLINE }, { 0x330c00, 1, RI_ALL_ONLINE },
+        { 0x331000, 1, RI_ALL_ONLINE }, { 0x331040, 1, RI_E1HE2_ONLINE },
+        { 0x331400, 1, RI_ALL_ONLINE }, { 0x331440, 1, RI_E1HE2_ONLINE },
+        { 0x331480, 1, RI_E1HE2_ONLINE }, { 0x3314c0, 1, RI_E1HE2_ONLINE },
+        { 0x331800, 128, RI_ALL_OFFLINE }, { 0x331c00, 128, RI_ALL_OFFLINE },
+        { 0x332000, 1, RI_ALL_ONLINE }, { 0x332400, 1, RI_E1HE2_ONLINE },
+        { 0x332404, 5631, RI_E2_OFFLINE }, { 0x338000, 1, RI_ALL_ONLINE },
+        { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE },
+        { 0x3380c0, 1, RI_ALL_ONLINE }, { 0x338100, 1, RI_ALL_ONLINE },
+        { 0x338140, 1, RI_ALL_ONLINE }, { 0x338180, 1, RI_ALL_ONLINE },
+        { 0x3381c0, 1, RI_ALL_ONLINE }, { 0x338200, 1, RI_ALL_ONLINE },
         { 0x338240, 1, RI_ALL_ONLINE }, { 0x338280, 1, RI_ALL_ONLINE },
-        { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE },
-        { 0x338a80, 1, RI_ALL_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE }
+        { 0x3382c0, 1, RI_ALL_ONLINE }, { 0x338300, 1, RI_ALL_ONLINE },
+        { 0x338340, 1, RI_ALL_ONLINE }, { 0x338380, 1, RI_ALL_ONLINE },
+        { 0x3383c0, 1, RI_ALL_ONLINE }, { 0x338400, 1, RI_ALL_ONLINE },
+        { 0x338440, 1, RI_ALL_ONLINE }, { 0x338480, 1, RI_ALL_ONLINE },
+        { 0x3384c0, 1, RI_ALL_ONLINE }, { 0x338500, 1, RI_ALL_ONLINE },
+        { 0x338540, 1, RI_ALL_ONLINE }, { 0x338580, 1, RI_ALL_ONLINE },
+        { 0x3385c0, 19, RI_E2_ONLINE }, { 0x338800, 1, RI_ALL_ONLINE },
+        { 0x338840, 1, RI_ALL_ONLINE }, { 0x338880, 1, RI_ALL_ONLINE },
+        { 0x3388c0, 1, RI_ALL_ONLINE }, { 0x338900, 1, RI_ALL_ONLINE },
+        { 0x338940, 1, RI_ALL_ONLINE }, { 0x338980, 1, RI_ALL_ONLINE },
+        { 0x3389c0, 1, RI_ALL_ONLINE }, { 0x338a00, 1, RI_ALL_ONLINE },
+        { 0x338a40, 1, RI_ALL_ONLINE }, { 0x338a80, 1, RI_ALL_ONLINE },
+        { 0x338ac0, 1, RI_ALL_ONLINE }, { 0x338b00, 1, RI_ALL_ONLINE },
+        { 0x338b40, 1, RI_ALL_ONLINE }, { 0x338b80, 1, RI_ALL_ONLINE },
+        { 0x338bc0, 1, RI_ALL_ONLINE }, { 0x338c00, 1, RI_ALL_ONLINE },
+        { 0x338c40, 1, RI_ALL_ONLINE }, { 0x338c80, 1, RI_ALL_ONLINE },
+        { 0x338cc0, 1, RI_ALL_ONLINE }, { 0x338cc4, 1, RI_E2_ONLINE },
+        { 0x338d00, 1, RI_ALL_ONLINE }, { 0x338d40, 1, RI_ALL_ONLINE },
+        { 0x338d80, 1, RI_ALL_ONLINE }, { 0x338dc0, 1, RI_ALL_ONLINE },
+        { 0x338e00, 1, RI_ALL_ONLINE }, { 0x338e40, 1, RI_ALL_ONLINE },
+        { 0x338e80, 1, RI_ALL_ONLINE }, { 0x338e84, 1, RI_E2_ONLINE },
+        { 0x338ec0, 1, RI_E1HE2_ONLINE }, { 0x338f00, 1, RI_E1HE2_ONLINE },
+        { 0x338f40, 1, RI_E1HE2_ONLINE }, { 0x338f80, 1, RI_E1HE2_ONLINE },
+        { 0x338fc0, 1, RI_E1HE2_ONLINE }, { 0x338fc4, 2, RI_E2_ONLINE },
+        { 0x338fd0, 6, RI_E2_ONLINE }, { 0x339000, 1, RI_E2_ONLINE },
+        { 0x339040, 3, RI_E2_ONLINE }, { 0x340000, 2, RI_ALL_ONLINE },
 };
 
-
-#define IDLE_REGS_COUNT                 277
+#define IDLE_REGS_COUNT                 237
 static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = {
-        { 0x2114, 1, RI_ALL_ONLINE }, { 0x2120, 1, RI_ALL_ONLINE },
-        { 0x212c, 4, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE },
-        { 0x281c, 2, RI_ALL_ONLINE }, { 0xa38c, 1, RI_ALL_ONLINE },
+        { 0x2104, 1, RI_ALL_ONLINE }, { 0x2110, 2, RI_ALL_ONLINE },
+        { 0x211c, 8, RI_ALL_ONLINE }, { 0x2814, 1, RI_ALL_ONLINE },
+        { 0x281c, 2, RI_ALL_ONLINE }, { 0x2854, 1, RI_ALL_ONLINE },
+        { 0x285c, 1, RI_ALL_ONLINE }, { 0x9010, 7, RI_E2_ONLINE },
+        { 0x9030, 1, RI_E2_ONLINE }, { 0x9068, 16, RI_E2_ONLINE },
+        { 0x9230, 2, RI_E2_ONLINE }, { 0x9244, 1, RI_E2_ONLINE },
+        { 0x9298, 1, RI_E2_ONLINE }, { 0x92a8, 1, RI_E2_ONLINE },
+        { 0xa38c, 1, RI_ALL_ONLINE }, { 0xa3c4, 1, RI_E1HE2_ONLINE },
         { 0xa408, 1, RI_ALL_ONLINE }, { 0xa42c, 12, RI_ALL_ONLINE },
-        { 0xa600, 5, RI_E1H_ONLINE }, { 0xa618, 1, RI_E1H_ONLINE },
-        { 0xc09c, 1, RI_ALL_ONLINE }, { 0x103b0, 1, RI_ALL_ONLINE },
-        { 0x103c0, 1, RI_ALL_ONLINE }, { 0x103d0, 1, RI_E1H_ONLINE },
-        { 0x2021c, 11, RI_ALL_ONLINE }, { 0x202a8, 1, RI_ALL_ONLINE },
-        { 0x202b8, 1, RI_ALL_ONLINE }, { 0x20404, 1, RI_ALL_ONLINE },
-        { 0x2040c, 2, RI_ALL_ONLINE }, { 0x2041c, 2, RI_ALL_ONLINE },
-        { 0x40154, 14, RI_ALL_ONLINE }, { 0x40198, 1, RI_ALL_ONLINE },
-        { 0x404ac, 1, RI_ALL_ONLINE }, { 0x404bc, 1, RI_ALL_ONLINE },
-        { 0x42290, 1, RI_ALL_ONLINE }, { 0x422a0, 1, RI_ALL_ONLINE },
-        { 0x422b0, 1, RI_ALL_ONLINE }, { 0x42548, 1, RI_ALL_ONLINE },
-        { 0x42550, 1, RI_ALL_ONLINE }, { 0x42558, 1, RI_ALL_ONLINE },
-        { 0x50160, 8, RI_ALL_ONLINE }, { 0x501d0, 1, RI_ALL_ONLINE },
-        { 0x501e0, 1, RI_ALL_ONLINE }, { 0x50204, 1, RI_ALL_ONLINE },
-        { 0x5020c, 2, RI_ALL_ONLINE }, { 0x5021c, 1, RI_ALL_ONLINE },
-        { 0x60090, 1, RI_ALL_ONLINE }, { 0x6011c, 1, RI_ALL_ONLINE },
-        { 0x6012c, 1, RI_ALL_ONLINE }, { 0xc101c, 1, RI_ALL_ONLINE },
-        { 0xc102c, 1, RI_ALL_ONLINE }, { 0xc2290, 1, RI_ALL_ONLINE },
-        { 0xc22a0, 1, RI_ALL_ONLINE }, { 0xc22b0, 1, RI_ALL_ONLINE },
-        { 0xc2548, 1, RI_ALL_ONLINE }, { 0xc2550, 1, RI_ALL_ONLINE },
-        { 0xc2558, 1, RI_ALL_ONLINE }, { 0xc4294, 1, RI_ALL_ONLINE },
-        { 0xc42a4, 1, RI_ALL_ONLINE }, { 0xc42b4, 1, RI_ALL_ONLINE },
-        { 0xc4550, 1, RI_ALL_ONLINE }, { 0xc4558, 1, RI_ALL_ONLINE },
-        { 0xc4560, 1, RI_ALL_ONLINE }, { 0xd016c, 8, RI_ALL_ONLINE },
-        { 0xd01d8, 1, RI_ALL_ONLINE }, { 0xd01e8, 1, RI_ALL_ONLINE },
-        { 0xd0204, 1, RI_ALL_ONLINE }, { 0xd020c, 3, RI_ALL_ONLINE },
-        { 0xe0154, 8, RI_ALL_ONLINE }, { 0xe01c8, 1, RI_ALL_ONLINE },
-        { 0xe01d8, 1, RI_ALL_ONLINE }, { 0xe0204, 1, RI_ALL_ONLINE },
-        { 0xe020c, 2, RI_ALL_ONLINE }, { 0xe021c, 2, RI_ALL_ONLINE },
-        { 0x101014, 1, RI_ALL_ONLINE }, { 0x101030, 1, RI_ALL_ONLINE },
-        { 0x101040, 1, RI_ALL_ONLINE }, { 0x102058, 1, RI_ALL_ONLINE },
-        { 0x102080, 16, RI_ALL_ONLINE }, { 0x103004, 2, RI_ALL_ONLINE },
-        { 0x103068, 1, RI_ALL_ONLINE }, { 0x103078, 1, RI_ALL_ONLINE },
-        { 0x103088, 1, RI_ALL_ONLINE }, { 0x10309c, 2, RI_E1H_ONLINE },
+        { 0xa600, 5, RI_E1HE2_ONLINE }, { 0xa618, 1, RI_E1HE2_ONLINE },
+        { 0xa714, 1, RI_E2_ONLINE }, { 0xa720, 1, RI_E2_ONLINE },
+        { 0xa750, 1, RI_E2_ONLINE }, { 0xc09c, 1, RI_E1E1H_ONLINE },
+        { 0x103b0, 1, RI_ALL_ONLINE }, { 0x103c0, 1, RI_ALL_ONLINE },
+        { 0x103d0, 1, RI_E1H_ONLINE }, { 0x183bc, 1, RI_E2_ONLINE },
+        { 0x183cc, 1, RI_E2_ONLINE }, { 0x2021c, 11, RI_ALL_ONLINE },
+        { 0x202a8, 1, RI_ALL_ONLINE }, { 0x202b8, 1, RI_ALL_ONLINE },
+        { 0x20404, 1, RI_ALL_ONLINE }, { 0x2040c, 2, RI_ALL_ONLINE },
+        { 0x2041c, 2, RI_ALL_ONLINE }, { 0x40154, 14, RI_ALL_ONLINE },
+        { 0x40198, 1, RI_ALL_ONLINE }, { 0x404ac, 1, RI_ALL_ONLINE },
+        { 0x404bc, 1, RI_ALL_ONLINE }, { 0x42290, 1, RI_ALL_ONLINE },
+        { 0x422a0, 1, RI_ALL_ONLINE }, { 0x422b0, 1, RI_ALL_ONLINE },
+        { 0x42548, 1, RI_ALL_ONLINE }, { 0x42550, 1, RI_ALL_ONLINE },
+        { 0x42558, 1, RI_ALL_ONLINE }, { 0x50160, 8, RI_ALL_ONLINE },
+        { 0x501d0, 1, RI_ALL_ONLINE }, { 0x501e0, 1, RI_ALL_ONLINE },
+        { 0x50204, 1, RI_ALL_ONLINE }, { 0x5020c, 2, RI_ALL_ONLINE },
+        { 0x5021c, 1, RI_ALL_ONLINE }, { 0x60090, 1, RI_ALL_ONLINE },
+        { 0x6011c, 1, RI_ALL_ONLINE }, { 0x6012c, 1, RI_ALL_ONLINE },
+        { 0xc101c, 1, RI_ALL_ONLINE }, { 0xc102c, 1, RI_ALL_ONLINE },
+        { 0xc2290, 1, RI_ALL_ONLINE }, { 0xc22a0, 1, RI_ALL_ONLINE },
+        { 0xc22b0, 1, RI_ALL_ONLINE }, { 0xc2548, 1, RI_ALL_ONLINE },
+        { 0xc2550, 1, RI_ALL_ONLINE }, { 0xc2558, 1, RI_ALL_ONLINE },
+        { 0xc4294, 1, RI_ALL_ONLINE }, { 0xc42a4, 1, RI_ALL_ONLINE },
+        { 0xc42b4, 1, RI_ALL_ONLINE }, { 0xc4550, 1, RI_ALL_ONLINE },
+        { 0xc4558, 1, RI_ALL_ONLINE }, { 0xc4560, 1, RI_ALL_ONLINE },
+        { 0xd016c, 8, RI_ALL_ONLINE }, { 0xd01d8, 1, RI_ALL_ONLINE },
+        { 0xd01e8, 1, RI_ALL_ONLINE }, { 0xd0204, 1, RI_ALL_ONLINE },
+        { 0xd020c, 3, RI_ALL_ONLINE }, { 0xe0154, 8, RI_ALL_ONLINE },
+        { 0xe01c8, 1, RI_ALL_ONLINE }, { 0xe01d8, 1, RI_ALL_ONLINE },
+        { 0xe0204, 1, RI_ALL_ONLINE }, { 0xe020c, 2, RI_ALL_ONLINE },
+        { 0xe021c, 2, RI_ALL_ONLINE }, { 0x101014, 1, RI_ALL_ONLINE },
+        { 0x101030, 1, RI_ALL_ONLINE }, { 0x101040, 1, RI_ALL_ONLINE },
+        { 0x102058, 1, RI_ALL_ONLINE }, { 0x102080, 16, RI_ALL_ONLINE },
+        { 0x103004, 2, RI_ALL_ONLINE }, { 0x103068, 1, RI_ALL_ONLINE },
+        { 0x103078, 1, RI_ALL_ONLINE }, { 0x103088, 1, RI_ALL_ONLINE },
+        { 0x10309c, 2, RI_E1HE2_ONLINE }, { 0x1030b8, 2, RI_E2_ONLINE },
+        { 0x1030cc, 1, RI_E2_ONLINE }, { 0x1030e0, 1, RI_E2_ONLINE },
         { 0x104004, 1, RI_ALL_ONLINE }, { 0x104018, 1, RI_ALL_ONLINE },
         { 0x104020, 1, RI_ALL_ONLINE }, { 0x10403c, 1, RI_ALL_ONLINE },
         { 0x1040fc, 1, RI_ALL_ONLINE }, { 0x10410c, 1, RI_ALL_ONLINE },
         { 0x104400, 64, RI_ALL_ONLINE }, { 0x104800, 64, RI_ALL_ONLINE },
-        { 0x105000, 3, RI_ALL_ONLINE }, { 0x105010, 3, RI_ALL_ONLINE },
-        { 0x105020, 3, RI_ALL_ONLINE }, { 0x105030, 3, RI_ALL_ONLINE },
-        { 0x105040, 3, RI_ALL_ONLINE }, { 0x105050, 3, RI_ALL_ONLINE },
-        { 0x105060, 3, RI_ALL_ONLINE }, { 0x105070, 3, RI_ALL_ONLINE },
-        { 0x105080, 3, RI_ALL_ONLINE }, { 0x105090, 3, RI_ALL_ONLINE },
-        { 0x1050a0, 3, RI_ALL_ONLINE }, { 0x1050b0, 3, RI_ALL_ONLINE },
-        { 0x1050c0, 3, RI_ALL_ONLINE }, { 0x1050d0, 3, RI_ALL_ONLINE },
-        { 0x1050e0, 3, RI_ALL_ONLINE }, { 0x1050f0, 3, RI_ALL_ONLINE },
-        { 0x105100, 3, RI_ALL_ONLINE }, { 0x105110, 3, RI_ALL_ONLINE },
-        { 0x105120, 3, RI_ALL_ONLINE }, { 0x105130, 3, RI_ALL_ONLINE },
-        { 0x105140, 3, RI_ALL_ONLINE }, { 0x105150, 3, RI_ALL_ONLINE },
-        { 0x105160, 3, RI_ALL_ONLINE }, { 0x105170, 3, RI_ALL_ONLINE },
-        { 0x105180, 3, RI_ALL_ONLINE }, { 0x105190, 3, RI_ALL_ONLINE },
-        { 0x1051a0, 3, RI_ALL_ONLINE }, { 0x1051b0, 3, RI_ALL_ONLINE },
-        { 0x1051c0, 3, RI_ALL_ONLINE }, { 0x1051d0, 3, RI_ALL_ONLINE },
-        { 0x1051e0, 3, RI_ALL_ONLINE }, { 0x1051f0, 3, RI_ALL_ONLINE },
-        { 0x105200, 3, RI_ALL_ONLINE }, { 0x105210, 3, RI_ALL_ONLINE },
-        { 0x105220, 3, RI_ALL_ONLINE }, { 0x105230, 3, RI_ALL_ONLINE },
-        { 0x105240, 3, RI_ALL_ONLINE }, { 0x105250, 3, RI_ALL_ONLINE },
-        { 0x105260, 3, RI_ALL_ONLINE }, { 0x105270, 3, RI_ALL_ONLINE },
-        { 0x105280, 3, RI_ALL_ONLINE }, { 0x105290, 3, RI_ALL_ONLINE },
-        { 0x1052a0, 3, RI_ALL_ONLINE }, { 0x1052b0, 3, RI_ALL_ONLINE },
-        { 0x1052c0, 3, RI_ALL_ONLINE }, { 0x1052d0, 3, RI_ALL_ONLINE },
-        { 0x1052e0, 3, RI_ALL_ONLINE }, { 0x1052f0, 3, RI_ALL_ONLINE },
-        { 0x105300, 3, RI_ALL_ONLINE }, { 0x105310, 3, RI_ALL_ONLINE },
-        { 0x105320, 3, RI_ALL_ONLINE }, { 0x105330, 3, RI_ALL_ONLINE },
-        { 0x105340, 3, RI_ALL_ONLINE }, { 0x105350, 3, RI_ALL_ONLINE },
-        { 0x105360, 3, RI_ALL_ONLINE }, { 0x105370, 3, RI_ALL_ONLINE },
-        { 0x105380, 3, RI_ALL_ONLINE }, { 0x105390, 3, RI_ALL_ONLINE },
-        { 0x1053a0, 3, RI_ALL_ONLINE }, { 0x1053b0, 3, RI_ALL_ONLINE },
-        { 0x1053c0, 3, RI_ALL_ONLINE }, { 0x1053d0, 3, RI_ALL_ONLINE },
-        { 0x1053e0, 3, RI_ALL_ONLINE }, { 0x1053f0, 3, RI_ALL_ONLINE },
-        { 0x108094, 1, RI_ALL_ONLINE }, { 0x1201b0, 2, RI_ALL_ONLINE },
-        { 0x12032c, 1, RI_ALL_ONLINE }, { 0x12036c, 3, RI_ALL_ONLINE },
-        { 0x120408, 2, RI_ALL_ONLINE }, { 0x120414, 15, RI_ALL_ONLINE },
-        { 0x120478, 2, RI_ALL_ONLINE }, { 0x12052c, 1, RI_ALL_ONLINE },
-        { 0x120564, 3, RI_ALL_ONLINE }, { 0x12057c, 1, RI_ALL_ONLINE },
-        { 0x12058c, 1, RI_ALL_ONLINE }, { 0x120608, 1, RI_E1H_ONLINE },
-        { 0x120808, 1, RI_E1_ONLINE }, { 0x12080c, 2, RI_ALL_ONLINE },
+        { 0x105000, 256, RI_ALL_ONLINE }, { 0x108094, 1, RI_E1E1H_ONLINE },
+        { 0x1201b0, 2, RI_ALL_ONLINE }, { 0x12032c, 1, RI_ALL_ONLINE },
+        { 0x12036c, 3, RI_ALL_ONLINE }, { 0x120408, 2, RI_ALL_ONLINE },
+        { 0x120414, 15, RI_ALL_ONLINE }, { 0x120478, 2, RI_ALL_ONLINE },
+        { 0x12052c, 1, RI_ALL_ONLINE }, { 0x120564, 3, RI_ALL_ONLINE },
+        { 0x12057c, 1, RI_ALL_ONLINE }, { 0x12058c, 1, RI_ALL_ONLINE },
+        { 0x120608, 1, RI_E1HE2_ONLINE }, { 0x120738, 1, RI_E2_ONLINE },
+        { 0x120778, 2, RI_E2_ONLINE }, { 0x120808, 3, RI_ALL_ONLINE },
         { 0x120818, 1, RI_ALL_ONLINE }, { 0x120820, 1, RI_ALL_ONLINE },
         { 0x120828, 1, RI_ALL_ONLINE }, { 0x120830, 1, RI_ALL_ONLINE },
         { 0x120838, 1, RI_ALL_ONLINE }, { 0x120840, 1, RI_ALL_ONLINE },
@@ -462,48 +580,50 @@ static const struct reg_addr idle_addrs[IDLE_REGS_COUNT] = {
         { 0x1208d8, 1, RI_ALL_ONLINE }, { 0x1208e0, 1, RI_ALL_ONLINE },
         { 0x1208e8, 1, RI_ALL_ONLINE }, { 0x1208f0, 1, RI_ALL_ONLINE },
         { 0x1208f8, 1, RI_ALL_ONLINE }, { 0x120900, 1, RI_ALL_ONLINE },
-        { 0x120908, 1, RI_ALL_ONLINE }, { 0x14005c, 2, RI_ALL_ONLINE },
-        { 0x1400d0, 2, RI_ALL_ONLINE }, { 0x1400e0, 1, RI_ALL_ONLINE },
-        { 0x1401c8, 1, RI_ALL_ONLINE }, { 0x140200, 6, RI_ALL_ONLINE },
-        { 0x16101c, 1, RI_ALL_ONLINE }, { 0x16102c, 1, RI_ALL_ONLINE },
-        { 0x164014, 2, RI_ALL_ONLINE }, { 0x1640f0, 1, RI_ALL_ONLINE },
-        { 0x166290, 1, RI_ALL_ONLINE }, { 0x1662a0, 1, RI_ALL_ONLINE },
-        { 0x1662b0, 1, RI_ALL_ONLINE }, { 0x166548, 1, RI_ALL_ONLINE },
-        { 0x166550, 1, RI_ALL_ONLINE }, { 0x166558, 1, RI_ALL_ONLINE },
-        { 0x168000, 1, RI_ALL_ONLINE }, { 0x168008, 1, RI_ALL_ONLINE },
-        { 0x168010, 1, RI_ALL_ONLINE }, { 0x168018, 1, RI_ALL_ONLINE },
-        { 0x168028, 2, RI_ALL_ONLINE }, { 0x168058, 4, RI_ALL_ONLINE },
-        { 0x168070, 1, RI_ALL_ONLINE }, { 0x168238, 1, RI_ALL_ONLINE },
-        { 0x1682d0, 2, RI_ALL_ONLINE }, { 0x1682e0, 1, RI_ALL_ONLINE },
-        { 0x168300, 67, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE },
+        { 0x120908, 1, RI_ALL_ONLINE }, { 0x120940, 5, RI_E2_ONLINE },
+        { 0x130030, 1, RI_E2_ONLINE }, { 0x13004c, 3, RI_E2_ONLINE },
+        { 0x130064, 2, RI_E2_ONLINE }, { 0x13009c, 1, RI_E2_ONLINE },
+        { 0x130130, 1, RI_E2_ONLINE }, { 0x13016c, 1, RI_E2_ONLINE },
+        { 0x130300, 1, RI_E2_ONLINE }, { 0x130480, 1, RI_E2_ONLINE },
+        { 0x14005c, 2, RI_ALL_ONLINE }, { 0x1400d0, 2, RI_ALL_ONLINE },
+        { 0x1400e0, 1, RI_ALL_ONLINE }, { 0x1401c8, 1, RI_ALL_ONLINE },
+        { 0x140200, 6, RI_ALL_ONLINE }, { 0x16101c, 1, RI_ALL_ONLINE },
+        { 0x16102c, 1, RI_ALL_ONLINE }, { 0x164014, 2, RI_ALL_ONLINE },
+        { 0x1640f0, 1, RI_ALL_ONLINE }, { 0x166290, 1, RI_ALL_ONLINE },
+        { 0x1662a0, 1, RI_ALL_ONLINE }, { 0x1662b0, 1, RI_ALL_ONLINE },
+        { 0x166548, 1, RI_ALL_ONLINE }, { 0x166550, 1, RI_ALL_ONLINE },
+        { 0x166558, 1, RI_ALL_ONLINE }, { 0x168000, 1, RI_ALL_ONLINE },
+        { 0x168008, 1, RI_ALL_ONLINE }, { 0x168010, 1, RI_ALL_ONLINE },
+        { 0x168018, 1, RI_ALL_ONLINE }, { 0x168028, 2, RI_ALL_ONLINE },
+        { 0x168058, 4, RI_ALL_ONLINE }, { 0x168070, 1, RI_ALL_ONLINE },
+        { 0x168238, 1, RI_ALL_ONLINE }, { 0x1682d0, 2, RI_ALL_ONLINE },
+        { 0x1682e0, 1, RI_ALL_ONLINE }, { 0x168300, 2, RI_E1E1H_ONLINE },
+        { 0x168308, 65, RI_ALL_ONLINE }, { 0x168410, 2, RI_ALL_ONLINE },
         { 0x168438, 1, RI_ALL_ONLINE }, { 0x168448, 1, RI_ALL_ONLINE },
         { 0x168a00, 128, RI_ALL_ONLINE }, { 0x16e200, 128, RI_E1H_ONLINE },
-        { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 70, RI_E1H_ONLINE },
-        { 0x1700a4, 1, RI_ALL_ONLINE }, { 0x1700ac, 2, RI_ALL_ONLINE },
-        { 0x1700c0, 1, RI_ALL_ONLINE }, { 0x170174, 1, RI_ALL_ONLINE },
-        { 0x170184, 1, RI_ALL_ONLINE }, { 0x1800f4, 1, RI_ALL_ONLINE },
-        { 0x180104, 1, RI_ALL_ONLINE }, { 0x180114, 1, RI_ALL_ONLINE },
-        { 0x180124, 1, RI_ALL_ONLINE }, { 0x18026c, 1, RI_ALL_ONLINE },
-        { 0x1802a0, 1, RI_ALL_ONLINE }, { 0x1a1000, 1, RI_ALL_ONLINE },
-        { 0x1aa000, 1, RI_E1H_ONLINE }, { 0x1b8000, 1, RI_ALL_ONLINE },
-        { 0x1b8040, 1, RI_ALL_ONLINE }, { 0x1b8080, 1, RI_ALL_ONLINE },
-        { 0x1b80c0, 1, RI_ALL_ONLINE }, { 0x200104, 1, RI_ALL_ONLINE },
-        { 0x200114, 1, RI_ALL_ONLINE }, { 0x200124, 1, RI_ALL_ONLINE },
-        { 0x200134, 1, RI_ALL_ONLINE }, { 0x20026c, 1, RI_ALL_ONLINE },
-        { 0x2002a0, 1, RI_ALL_ONLINE }, { 0x221000, 1, RI_ALL_ONLINE },
-        { 0x227000, 1, RI_E1H_ONLINE }, { 0x238000, 1, RI_ALL_ONLINE },
-        { 0x238040, 1, RI_ALL_ONLINE }, { 0x238080, 1, RI_ALL_ONLINE },
-        { 0x2380c0, 1, RI_ALL_ONLINE }, { 0x280104, 1, RI_ALL_ONLINE },
-        { 0x280114, 1, RI_ALL_ONLINE }, { 0x280124, 1, RI_ALL_ONLINE },
-        { 0x280134, 1, RI_ALL_ONLINE }, { 0x28026c, 1, RI_ALL_ONLINE },
-        { 0x2802a0, 1, RI_ALL_ONLINE }, { 0x2a1000, 1, RI_ALL_ONLINE },
-        { 0x2a9000, 1, RI_E1H_ONLINE }, { 0x2b8000, 1, RI_ALL_ONLINE },
-        { 0x2b8040, 1, RI_ALL_ONLINE }, { 0x2b8080, 1, RI_ALL_ONLINE },
-        { 0x2b80c0, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE },
+        { 0x16e404, 2, RI_E1H_ONLINE }, { 0x16e584, 64, RI_E1H_ONLINE },
+        { 0x16e684, 2, RI_E1HE2_ONLINE }, { 0x16e68c, 4, RI_E1H_ONLINE },
+        { 0x16e6fc, 4, RI_E2_ONLINE }, { 0x1700a4, 1, RI_ALL_ONLINE },
+        { 0x1700ac, 2, RI_ALL_ONLINE }, { 0x1700c0, 1, RI_ALL_ONLINE },
+        { 0x170174, 1, RI_ALL_ONLINE }, { 0x170184, 1, RI_ALL_ONLINE },
+        { 0x1800f4, 1, RI_ALL_ONLINE }, { 0x180104, 1, RI_ALL_ONLINE },
+        { 0x180114, 1, RI_ALL_ONLINE }, { 0x180124, 1, RI_ALL_ONLINE },
+        { 0x18026c, 1, RI_ALL_ONLINE }, { 0x1802a0, 1, RI_ALL_ONLINE },
+        { 0x1b8000, 1, RI_ALL_ONLINE }, { 0x1b8040, 1, RI_ALL_ONLINE },
+        { 0x1b8080, 1, RI_ALL_ONLINE }, { 0x1b80c0, 1, RI_ALL_ONLINE },
+        { 0x200104, 1, RI_ALL_ONLINE }, { 0x200114, 1, RI_ALL_ONLINE },
+        { 0x200124, 1, RI_ALL_ONLINE }, { 0x200134, 1, RI_ALL_ONLINE },
+        { 0x20026c, 1, RI_ALL_ONLINE }, { 0x2002a0, 1, RI_ALL_ONLINE },
+        { 0x238000, 1, RI_ALL_ONLINE }, { 0x238040, 1, RI_ALL_ONLINE },
+        { 0x238080, 1, RI_ALL_ONLINE }, { 0x2380c0, 1, RI_ALL_ONLINE },
+        { 0x280104, 1, RI_ALL_ONLINE }, { 0x280114, 1, RI_ALL_ONLINE },
+        { 0x280124, 1, RI_ALL_ONLINE }, { 0x280134, 1, RI_ALL_ONLINE },
+        { 0x28026c, 1, RI_ALL_ONLINE }, { 0x2802a0, 1, RI_ALL_ONLINE },
+        { 0x2b8000, 1, RI_ALL_ONLINE }, { 0x2b8040, 1, RI_ALL_ONLINE },
+        { 0x2b8080, 1, RI_ALL_ONLINE }, { 0x300104, 1, RI_ALL_ONLINE },
         { 0x300114, 1, RI_ALL_ONLINE }, { 0x300124, 1, RI_ALL_ONLINE },
         { 0x300134, 1, RI_ALL_ONLINE }, { 0x30026c, 1, RI_ALL_ONLINE },
-        { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x321000, 1, RI_ALL_ONLINE },
-        { 0x328960, 1, RI_E1H_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE },
+        { 0x3002a0, 1, RI_ALL_ONLINE }, { 0x338000, 1, RI_ALL_ONLINE },
         { 0x338040, 1, RI_ALL_ONLINE }, { 0x338080, 1, RI_ALL_ONLINE },
         { 0x3380c0, 1, RI_ALL_ONLINE }
 };
@@ -515,7 +635,6 @@ static const struct wreg_addr wreg_addrs_e1[WREGS_COUNT_E1] = {
         { 0x1b0c00, 192, 1, read_reg_e1_0, RI_E1_OFFLINE }
 };
 
-
 #define WREGS_COUNT_E1H                 1
 static const u32 read_reg_e1h_0[] = { 0x1b1040, 0x1b1000 };
 
@@ -530,22 +649,53 @@ static const struct wreg_addr wreg_addrs_e2[WREGS_COUNT_E2] = {
         { 0x1b0c00, 128, 2, read_reg_e2_0, RI_E2_OFFLINE }
 };
 
-static const struct dump_sign dump_sign_all = { 0x49aa93ee, 0x40835, 0x22 };
-
+static const struct dump_sign dump_sign_all = { 0x4d18b0a4, 0x60010, 0x3a };
 
 #define TIMER_REGS_COUNT_E1             2
-static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] =
-        { 0x164014, 0x164018 };
-static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] =
-        { 0x1640d0, 0x1640d4 };
 
+static const u32 timer_status_regs_e1[TIMER_REGS_COUNT_E1] = {
+        0x164014, 0x164018 };
+static const u32 timer_scan_regs_e1[TIMER_REGS_COUNT_E1] = {
+        0x1640d0, 0x1640d4 };
 
 #define TIMER_REGS_COUNT_E1H            2
-static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] =
-        { 0x164014, 0x164018 };
-static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] =
-        { 0x1640d0, 0x1640d4 };
 
+static const u32 timer_status_regs_e1h[TIMER_REGS_COUNT_E1H] = {
+        0x164014, 0x164018 };
+static const u32 timer_scan_regs_e1h[TIMER_REGS_COUNT_E1H] = {
+        0x1640d0, 0x1640d4 };
+
+#define TIMER_REGS_COUNT_E2             2
+
+static const u32 timer_status_regs_e2[TIMER_REGS_COUNT_E2] = {
+        0x164014, 0x164018 };
+static const u32 timer_scan_regs_e2[TIMER_REGS_COUNT_E2] = {
+        0x1640d0, 0x1640d4 };
+
+#define PAGE_MODE_VALUES_E1 0
+
+#define PAGE_READ_REGS_E1 0
+
+#define PAGE_WRITE_REGS_E1 0
+
+static const u32 page_vals_e1[] = { 0 };
+
+static const u32 page_write_regs_e1[] = { 0 };
+
+static const struct reg_addr page_read_regs_e1[] = { { 0x0, 0, RI_E1_ONLINE } };
+
+#define PAGE_MODE_VALUES_E1H 0
+
+#define PAGE_READ_REGS_E1H 0
+
+#define PAGE_WRITE_REGS_E1H 0
+
+static const u32 page_vals_e1h[] = { 0 };
+
+static const u32 page_write_regs_e1h[] = { 0 };
+
+static const struct reg_addr page_read_regs_e1h[] = {
+        { 0x0, 0, RI_E1H_ONLINE } };
 
 #define PAGE_MODE_VALUES_E2 2
 
diff --git a/drivers/net/bnx2x/bnx2x_ethtool.c b/drivers/net/bnx2x/bnx2x_ethtool.c
index d02ffbdc9f0e..5b44a8b48509 100644
--- a/drivers/net/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/bnx2x/bnx2x_ethtool.c
@@ -24,6 +24,144 @@
 #include "bnx2x.h"
 #include "bnx2x_cmn.h"
 #include "bnx2x_dump.h"
+#include "bnx2x_init.h"
+
+/* Note: in the format strings below %s is replaced by the queue-name which is
+ * either its index or 'fcoe' for the fcoe queue. Make sure the format string
+ * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
+ */
+#define MAX_QUEUE_NAME_LEN      4
+static const struct {
+        long offset;
+        int size;
+        char string[ETH_GSTRING_LEN];
+} bnx2x_q_stats_arr[] = {
+/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
+        { Q_STATS_OFFSET32(error_bytes_received_hi),
+                                                8, "[%s]: rx_error_bytes" },
+        { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
+                                                8, "[%s]: rx_ucast_packets" },
+        { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
+                                                8, "[%s]: rx_mcast_packets" },
+        { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
+                                                8, "[%s]: rx_bcast_packets" },
+        { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
+        { Q_STATS_OFFSET32(rx_err_discard_pkt),
+                                         4, "[%s]: rx_phy_ip_err_discards"},
+        { Q_STATS_OFFSET32(rx_skb_alloc_failed),
+                                         4, "[%s]: rx_skb_alloc_discard" },
+        { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
+
+/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
+        { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
+                                                8, "[%s]: tx_ucast_packets" },
+        { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
+                                                8, "[%s]: tx_mcast_packets" },
+        { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
+                                                8, "[%s]: tx_bcast_packets" }
+};
+
+#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
+
+static const struct {
+        long offset;
+        int size;
+        u32 flags;
+#define STATS_FLAGS_PORT                1
+#define STATS_FLAGS_FUNC                2
+#define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
+        char string[ETH_GSTRING_LEN];
+} bnx2x_stats_arr[] = {
+/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
+                                8, STATS_FLAGS_BOTH, "rx_bytes" },
+        { STATS_OFFSET32(error_bytes_received_hi),
+                                8, STATS_FLAGS_BOTH, "rx_error_bytes" },
+        { STATS_OFFSET32(total_unicast_packets_received_hi),
+                                8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
+        { STATS_OFFSET32(total_multicast_packets_received_hi),
+                                8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
+        { STATS_OFFSET32(total_broadcast_packets_received_hi),
+                                8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
+        { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
+                                8, STATS_FLAGS_PORT, "rx_crc_errors" },
+        { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
+                                8, STATS_FLAGS_PORT, "rx_align_errors" },
+        { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
+                                8, STATS_FLAGS_PORT, "rx_undersize_packets" },
+        { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
+                                8, STATS_FLAGS_PORT, "rx_oversize_packets" },
+/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
+                                8, STATS_FLAGS_PORT, "rx_fragments" },
+        { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
+                                8, STATS_FLAGS_PORT, "rx_jabbers" },
+        { STATS_OFFSET32(no_buff_discard_hi),
+                                8, STATS_FLAGS_BOTH, "rx_discards" },
+        { STATS_OFFSET32(mac_filter_discard),
+                                4, STATS_FLAGS_PORT, "rx_filtered_packets" },
+        { STATS_OFFSET32(xxoverflow_discard),
+                                4, STATS_FLAGS_PORT, "rx_fw_discards" },
+        { STATS_OFFSET32(brb_drop_hi),
+                                8, STATS_FLAGS_PORT, "rx_brb_discard" },
+        { STATS_OFFSET32(brb_truncate_hi),
+                                8, STATS_FLAGS_PORT, "rx_brb_truncate" },
+        { STATS_OFFSET32(pause_frames_received_hi),
+                                8, STATS_FLAGS_PORT, "rx_pause_frames" },
+        { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
+                                8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
+        { STATS_OFFSET32(nig_timer_max),
+                        4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
+/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
+                                4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
+        { STATS_OFFSET32(rx_skb_alloc_failed),
+                                4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
+        { STATS_OFFSET32(hw_csum_err),
+                                4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
+
+        { STATS_OFFSET32(total_bytes_transmitted_hi),
+                                8, STATS_FLAGS_BOTH, "tx_bytes" },
+        { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
+                                8, STATS_FLAGS_PORT, "tx_error_bytes" },
+        { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
+                                8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
+        { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
+                                8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
+        { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
+                                8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
+        { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
+                                8, STATS_FLAGS_PORT, "tx_mac_errors" },
+        { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
+                                8, STATS_FLAGS_PORT, "tx_carrier_errors" },
+/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
+                                8, STATS_FLAGS_PORT, "tx_single_collisions" },
+        { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
+                                8, STATS_FLAGS_PORT, "tx_multi_collisions" },
+        { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
+                                8, STATS_FLAGS_PORT, "tx_deferred" },
+        { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
+                                8, STATS_FLAGS_PORT, "tx_excess_collisions" },
+        { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
+                                8, STATS_FLAGS_PORT, "tx_late_collisions" },
+        { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
+                                8, STATS_FLAGS_PORT, "tx_total_collisions" },
+        { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
+                                8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
+        { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
+                        8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
+        { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
+                        8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
+        { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
+                        8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
+/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
+                        8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
+        { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
+                        8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
+        { STATS_OFFSET32(etherstatspktsover1522octets_hi),
+                        8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
+        { STATS_OFFSET32(pause_frames_sent_hi),
+                                8, STATS_FLAGS_PORT, "tx_pause_frames" }
+};
+
+#define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 
 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
@@ -45,14 +183,9 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
                 cmd->speed = bp->link_params.req_line_speed[cfg_idx];
                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
         }
-        if (IS_MF(bp)) {
-                u16 vn_max_rate = ((bp->mf_config[BP_VN(bp)] &
-                        FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT) *
-                        100;
 
-                if (vn_max_rate < cmd->speed)
-                        cmd->speed = vn_max_rate;
-        }
+        if (IS_MF(bp))
+                cmd->speed = bnx2x_get_mf_speed(bp);
 
         if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
                 cmd->port = PORT_TP;
@@ -87,18 +220,57 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 {
         struct bnx2x *bp = netdev_priv(dev);
         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
+        u32 speed;
 
-        if (IS_MF(bp))
+        if (IS_MF_SD(bp))
                 return 0;
 
         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
-           DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %d\n"
-           DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
-           DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
+           "  supported 0x%x  advertising 0x%x  speed %d speed_hi %d\n"
+           "  duplex %d  port %d  phy_address %d  transceiver %d\n"
+           "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
            cmd->cmd, cmd->supported, cmd->advertising, cmd->speed,
+           cmd->speed_hi,
            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 
+        speed = cmd->speed;
+        speed |= (cmd->speed_hi << 16);
+
+        if (IS_MF_SI(bp)) {
+                u32 param = 0;
+                u32 line_speed = bp->link_vars.line_speed;
+
+                /* use 10G if no link detected */
+                if (!line_speed)
+                        line_speed = 10000;
+
+                if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
+                        BNX2X_DEV_INFO("To set speed BC %X or higher "
+                                       "is required, please upgrade BC\n",
+                                       REQ_BC_VER_4_SET_MF_BW);
+                        return -EINVAL;
+                }
+                if (line_speed < speed) {
+                        BNX2X_DEV_INFO("New speed should be less or equal "
+                                       "to actual line speed\n");
+                        return -EINVAL;
+                }
+                /* load old values */
+                param = bp->mf_config[BP_VN(bp)];
+
+                /* leave only MIN value */
+                param &= FUNC_MF_CFG_MIN_BW_MASK;
+
+                /* set new MAX value */
+                param |= (((speed * 100) / line_speed)
+                                 << FUNC_MF_CFG_MAX_BW_SHIFT)
+                                  & FUNC_MF_CFG_MAX_BW_MASK;
+
+                bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, param);
+                return 0;
+        }
+
         cfg_idx = bnx2x_get_link_cfg_idx(bp);
         old_multi_phy_config = bp->link_params.multi_phy_config;
         switch (cmd->port) {
@@ -168,8 +340,6 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 
         } else { /* forced speed */
                 /* advertise the requested speed and duplex if supported */
-                u32 speed = cmd->speed;
-                speed |= (cmd->speed_hi << 16);
                 switch (speed) {
                 case SPEED_10:
                         if (cmd->duplex == DUPLEX_FULL) {
@@ -303,7 +473,7 @@ static int bnx2x_get_regs_len(struct net_device *dev)
 {
         struct bnx2x *bp = netdev_priv(dev);
         int regdump_len = 0;
-        int i;
+        int i, j, k;
 
         if (CHIP_IS_E1(bp)) {
                 for (i = 0; i < REGS_COUNT; i++)
@@ -333,6 +503,15 @@ static int bnx2x_get_regs_len(struct net_device *dev)
                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
                                 regdump_len += wreg_addrs_e2[i].size *
                                         (1 + wreg_addrs_e2[i].read_regs_count);
+
+                for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
+                        for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
+                                for (k = 0; k < PAGE_READ_REGS_E2; k++)
+                                        if (IS_E2_ONLINE(page_read_regs_e2[k].
+                                                         info))
+                                                regdump_len +=
+                                                page_read_regs_e2[k].size;
+                        }
         }
         regdump_len *= 4;
         regdump_len += sizeof(struct dump_hdr);
@@ -370,6 +549,12 @@ static void bnx2x_get_regs(struct net_device *dev,
         if (!netif_running(bp->dev))
                 return;
 
+        /* Disable parity attentions as long as following dump may
+         * cause false alarms by reading never written registers. We
+         * will re-enable parity attentions right after the dump.
+         */
+        bnx2x_disable_blocks_parity(bp);
+
         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
         dump_hdr.dump_sign = dump_sign_all;
         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
@@ -411,6 +596,10 @@ static void bnx2x_get_regs(struct net_device *dev,
 
                 bnx2x_read_pages_regs_e2(bp, p);
         }
+        /* Re-enable parity attentions */
+        bnx2x_clear_blocks_parity(bp);
+        if (CHIP_PARITY_ENABLED(bp))
+                bnx2x_enable_blocks_parity(bp);
 }
 
 #define PHY_FW_VER_LEN                  20
@@ -1286,7 +1475,7 @@ static int bnx2x_test_registers(struct bnx2x *bp)
 
                         save_val = REG_RD(bp, offset);
 
-                        REG_WR(bp, offset, (wr_val & mask));
+                        REG_WR(bp, offset, wr_val & mask);
 
                         val = REG_RD(bp, offset);
 
@@ -1499,8 +1688,15 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
          * updates that have been performed while interrupts were
          * disabled.
          */
-        if (bp->common.int_block == INT_BLOCK_IGU)
+        if (bp->common.int_block == INT_BLOCK_IGU) {
+                /* Disable local BHes to prevent a dead-lock situation between
+                 * sch_direct_xmit() and bnx2x_run_loopback() (calling
+                 * bnx2x_tx_int()), as both are taking netif_tx_lock().
+                 */
+                local_bh_disable();
                 bnx2x_tx_int(fp_tx);
+                local_bh_enable();
+        }
 
         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
         if (rx_idx != rx_start_idx + num_pkts)
@@ -1650,7 +1846,7 @@ static int bnx2x_test_intr(struct bnx2x *bp)
         config->hdr.client_id = bp->fp->cl_id;
         config->hdr.reserved1 = 0;
 
-        bp->set_mac_pending++;
+        bp->set_mac_pending = 1;
         smp_wmb();
         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
@@ -1748,134 +1944,6 @@ static void bnx2x_self_test(struct net_device *dev,
 #endif
 }
 
-static const struct {
-        long offset;
-        int size;
-        u8 string[ETH_GSTRING_LEN];
-} bnx2x_q_stats_arr[BNX2X_NUM_Q_STATS] = {
-/* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%d]: rx_bytes" },
-        { Q_STATS_OFFSET32(error_bytes_received_hi),
-                                                8, "[%d]: rx_error_bytes" },
-        { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
-                                                8, "[%d]: rx_ucast_packets" },
-        { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
-                                                8, "[%d]: rx_mcast_packets" },
-        { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
-                                                8, "[%d]: rx_bcast_packets" },
-        { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%d]: rx_discards" },
-        { Q_STATS_OFFSET32(rx_err_discard_pkt),
-                                         4, "[%d]: rx_phy_ip_err_discards"},
-        { Q_STATS_OFFSET32(rx_skb_alloc_failed),
-                                         4, "[%d]: rx_skb_alloc_discard" },
-        { Q_STATS_OFFSET32(hw_csum_err), 4, "[%d]: rx_csum_offload_errors" },
-
-/* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%d]: tx_bytes" },
-        { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
-                                                8, "[%d]: tx_ucast_packets" },
-        { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
-                                                8, "[%d]: tx_mcast_packets" },
-        { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
-                                                8, "[%d]: tx_bcast_packets" }
-};
-
-static const struct {
-        long offset;
-        int size;
-        u32 flags;
-#define STATS_FLAGS_PORT                1
-#define STATS_FLAGS_FUNC                2
-#define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
-        u8 string[ETH_GSTRING_LEN];
-} bnx2x_stats_arr[BNX2X_NUM_STATS] = {
-/* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
-                                8, STATS_FLAGS_BOTH, "rx_bytes" },
-        { STATS_OFFSET32(error_bytes_received_hi),
-                                8, STATS_FLAGS_BOTH, "rx_error_bytes" },
-        { STATS_OFFSET32(total_unicast_packets_received_hi),
-                                8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
-        { STATS_OFFSET32(total_multicast_packets_received_hi),
-                                8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
-        { STATS_OFFSET32(total_broadcast_packets_received_hi),
-                                8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
-        { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
-                                8, STATS_FLAGS_PORT, "rx_crc_errors" },
-        { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
-                                8, STATS_FLAGS_PORT, "rx_align_errors" },
-        { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
-                                8, STATS_FLAGS_PORT, "rx_undersize_packets" },
-        { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
-                                8, STATS_FLAGS_PORT, "rx_oversize_packets" },
-/* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
-                                8, STATS_FLAGS_PORT, "rx_fragments" },
-        { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
-                                8, STATS_FLAGS_PORT, "rx_jabbers" },
-        { STATS_OFFSET32(no_buff_discard_hi),
-                                8, STATS_FLAGS_BOTH, "rx_discards" },
-        { STATS_OFFSET32(mac_filter_discard),
-                                4, STATS_FLAGS_PORT, "rx_filtered_packets" },
-        { STATS_OFFSET32(xxoverflow_discard),
-                                4, STATS_FLAGS_PORT, "rx_fw_discards" },
-        { STATS_OFFSET32(brb_drop_hi),
-                                8, STATS_FLAGS_PORT, "rx_brb_discard" },
-        { STATS_OFFSET32(brb_truncate_hi),
-                                8, STATS_FLAGS_PORT, "rx_brb_truncate" },
-        { STATS_OFFSET32(pause_frames_received_hi),
-                                8, STATS_FLAGS_PORT, "rx_pause_frames" },
-        { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
-                                8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
-        { STATS_OFFSET32(nig_timer_max),
-                        4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
-/* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
-                                4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
-        { STATS_OFFSET32(rx_skb_alloc_failed),
-                                4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
-        { STATS_OFFSET32(hw_csum_err),
-                                4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
-
-        { STATS_OFFSET32(total_bytes_transmitted_hi),
-                                8, STATS_FLAGS_BOTH, "tx_bytes" },
-        { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
-                                8, STATS_FLAGS_PORT, "tx_error_bytes" },
-        { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
-                                8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
-        { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
-                                8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
-        { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
-                                8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
-        { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
-                                8, STATS_FLAGS_PORT, "tx_mac_errors" },
-        { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
-                                8, STATS_FLAGS_PORT, "tx_carrier_errors" },
-/* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
-                                8, STATS_FLAGS_PORT, "tx_single_collisions" },
-        { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
-                                8, STATS_FLAGS_PORT, "tx_multi_collisions" },
-        { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
-                                8, STATS_FLAGS_PORT, "tx_deferred" },
-        { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
-                                8, STATS_FLAGS_PORT, "tx_excess_collisions" },
-        { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
-                                8, STATS_FLAGS_PORT, "tx_late_collisions" },
-        { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
-                                8, STATS_FLAGS_PORT, "tx_total_collisions" },
-        { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
-                                8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
-        { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
-                        8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
-        { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
-                        8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
-        { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
-                        8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
-/* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
-                        8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
-        { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
-                        8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
-        { STATS_OFFSET32(etherstatspktsover1522octets_hi),
-                        8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
-        { STATS_OFFSET32(pause_frames_sent_hi),
-                                8, STATS_FLAGS_PORT, "tx_pause_frames" }
-};
-
 #define IS_PORT_STAT(i) \
         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
@@ -1890,7 +1958,8 @@ static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
         switch (stringset) {
         case ETH_SS_STATS:
                 if (is_multi(bp)) {
-                        num_stats = BNX2X_NUM_Q_STATS * bp->num_queues;
+                        num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
+                                BNX2X_NUM_Q_STATS;
                         if (!IS_MF_MODE_STAT(bp))
                                 num_stats += BNX2X_NUM_STATS;
                 } else {
@@ -1916,15 +1985,25 @@ static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
 {
         struct bnx2x *bp = netdev_priv(dev);
         int i, j, k;
+        char queue_name[MAX_QUEUE_NAME_LEN+1];
 
         switch (stringset) {
         case ETH_SS_STATS:
                 if (is_multi(bp)) {
                         k = 0;
-                        for_each_queue(bp, i) {
+                        for_each_napi_queue(bp, i) {
+                                memset(queue_name, 0, sizeof(queue_name));
+
+                                if (IS_FCOE_IDX(i))
+                                        sprintf(queue_name, "fcoe");
+                                else
+                                        sprintf(queue_name, "%d", i);
+
                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
-                                        sprintf(buf + (k + j)*ETH_GSTRING_LEN,
-                                                bnx2x_q_stats_arr[j].string, i);
+                                        snprintf(buf + (k + j)*ETH_GSTRING_LEN,
+                                                ETH_GSTRING_LEN,
+                                                bnx2x_q_stats_arr[j].string,
+                                                queue_name);
                                 k += BNX2X_NUM_Q_STATS;
                         }
                         if (IS_MF_MODE_STAT(bp))
@@ -1958,7 +2037,7 @@ static void bnx2x_get_ethtool_stats(struct net_device *dev,
 
         if (is_multi(bp)) {
                 k = 0;
-                for_each_queue(bp, i) {
+                for_each_napi_queue(bp, i) {
                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
                                 if (bnx2x_q_stats_arr[j].size == 0) {
diff --git a/drivers/net/bnx2x/bnx2x_hsi.h b/drivers/net/bnx2x/bnx2x_hsi.h
index 4cfd4e9b5586..6238d4f63989 100644
--- a/drivers/net/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/bnx2x/bnx2x_hsi.h
@@ -434,7 +434,12 @@ struct shared_feat_cfg {				 /* NVRAM Offset */
 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED     0x00000000
 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED      0x00000002
 
-#define SHARED_FEATURE_MF_MODE_DISABLED             0x00000100
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK                    0x00000700
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT                   8
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED              0x00000000
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF               0x00000100
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4                   0x00000200
+#define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT           0x00000300
 
 };
 
@@ -679,7 +684,7 @@ struct shm_dev_info {						    /* size */
 #define E1VN_MAX                        1
 #define E1HVN_MAX                       4
 
-
+#define E2_VF_MAX                       64
 /* This value (in milliseconds) determines the frequency of the driver
  * issuing the PULSE message code.  The firmware monitors this periodic
  * pulse to determine when to switch to an OS-absent mode. */
@@ -815,6 +820,11 @@ struct drv_func_mb {
 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL      0xa1000000
 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL      0x00050234
 
+#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG                 0xb0000000
+#define DRV_MSG_CODE_DCBX_PMF_DRV_OK                    0xb2000000
+#define DRV_MSG_CODE_SET_MF_BW                          0xe0000000
+#define REQ_BC_VER_4_SET_MF_BW                          0x00060202
+#define DRV_MSG_CODE_SET_MF_BW_ACK                      0xe1000000
 #define BIOS_MSG_CODE_LIC_CHALLENGE                     0xff010000
 #define BIOS_MSG_CODE_LIC_RESPONSE                      0xff020000
 #define BIOS_MSG_CODE_VIRT_MAC_PRIM                     0xff030000
@@ -888,6 +898,7 @@ struct drv_func_mb {
 
         u32 drv_status;
 #define DRV_STATUS_PMF                                  0x00000001
+#define DRV_STATUS_SET_MF_BW                            0x00000004
 
 #define DRV_STATUS_DCC_EVENT_MASK                       0x0000ff00
 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF                0x00000100
@@ -896,6 +907,8 @@ struct drv_func_mb {
 #define DRV_STATUS_DCC_RESERVED1                        0x00000800
 #define DRV_STATUS_DCC_SET_PROTOCOL                     0x00001000
 #define DRV_STATUS_DCC_SET_PRIORITY                     0x00002000
+#define DRV_STATUS_DCBX_EVENT_MASK                      0x000f0000
+#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS             0x00010000
 
         u32 virt_mac_upper;
 #define VIRT_MAC_SIGN_MASK                              0xffff0000
@@ -988,12 +1001,43 @@ struct func_mf_cfg {
 
 };
 
+/* This structure is not applicable and should not be accessed on 57711 */
+struct func_ext_cfg {
+        u32 func_cfg;
+#define MACP_FUNC_CFG_FLAGS_MASK                              0x000000FF
+#define MACP_FUNC_CFG_FLAGS_SHIFT                             0
+#define MACP_FUNC_CFG_FLAGS_ENABLED                           0x00000001
+#define MACP_FUNC_CFG_FLAGS_ETHERNET                          0x00000002
+#define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD                     0x00000004
+#define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD                      0x00000008
+
+        u32 iscsi_mac_addr_upper;
+        u32 iscsi_mac_addr_lower;
+
+        u32 fcoe_mac_addr_upper;
+        u32 fcoe_mac_addr_lower;
+
+        u32 fcoe_wwn_port_name_upper;
+        u32 fcoe_wwn_port_name_lower;
+
+        u32 fcoe_wwn_node_name_upper;
+        u32 fcoe_wwn_node_name_lower;
+
+        u32 preserve_data;
+#define MF_FUNC_CFG_PRESERVE_L2_MAC                          (1<<0)
+#define MF_FUNC_CFG_PRESERVE_ISCSI_MAC                       (1<<1)
+#define MF_FUNC_CFG_PRESERVE_FCOE_MAC                        (1<<2)
+#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P                      (1<<3)
+#define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N                      (1<<4)
+};
+
 struct mf_cfg {
 
         struct shared_mf_cfg    shared_mf_config;
         struct port_mf_cfg      port_mf_config[PORT_MAX];
         struct func_mf_cfg      func_mf_config[E1H_FUNC_MAX];
 
+        struct func_ext_cfg func_ext_config[E1H_FUNC_MAX];
 };
 
 
@@ -1049,6 +1093,251 @@ struct fw_flr_mb {
         struct  fw_flr_ack ack;
 };
 
+/**** SUPPORT FOR SHMEM ARRRAYS ***
+ * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
+ * define arrays with storage types smaller then unsigned dwords.
+ * The macros below add generic support for SHMEM arrays with numeric elements
+ * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
+ * array with individual bit-filed elements accessed using shifts and masks.
+ *
+ */
+
+/* eb is the bitwidth of a single element */
+#define SHMEM_ARRAY_MASK(eb)            ((1<<(eb))-1)
+#define SHMEM_ARRAY_ENTRY(i, eb)        ((i)/(32/(eb)))
+
+/* the bit-position macro allows the used to flip the order of the arrays
+ * elements on a per byte or word boundary.
+ *
+ * example: an array with 8 entries each 4 bit wide. This array will fit into
+ * a single dword. The diagrmas below show the array order of the nibbles.
+ *
+ * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
+ *
+ *              |               |               |               |
+ *   0  |   1   |   2   |   3   |   4   |   5   |   6   |   7   |
+ *              |               |               |               |
+ *
+ * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
+ *
+ *              |               |               |               |
+ *   1  |   0   |   3   |   2   |   5   |   4   |   7   |   6   |
+ *              |               |               |               |
+ *
+ * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
+ *
+ *              |               |               |               |
+ *   3  |   2   |   1   |   0   |   7   |   6   |   5   |   4   |
+ *              |               |               |               |
+ */
+#define SHMEM_ARRAY_BITPOS(i, eb, fb)   \
+        ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
+        (((i)%((fb)/(eb))) * (eb)))
+
+#define SHMEM_ARRAY_GET(a, i, eb, fb)                                      \
+        ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) &  \
+        SHMEM_ARRAY_MASK(eb))
+
+#define SHMEM_ARRAY_SET(a, i, eb, fb, val)                                 \
+do {                                                                       \
+        a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) <<           \
+        SHMEM_ARRAY_BITPOS(i, eb, fb));                            \
+        a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) <<  \
+        SHMEM_ARRAY_BITPOS(i, eb, fb));                            \
+} while (0)
+
+
+/****START OF DCBX STRUCTURES DECLARATIONS****/
+#define DCBX_MAX_NUM_PRI_PG_ENTRIES     8
+#define DCBX_PRI_PG_BITWIDTH            4
+#define DCBX_PRI_PG_FBITS               8
+#define DCBX_PRI_PG_GET(a, i)           \
+        SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
+#define DCBX_PRI_PG_SET(a, i, val)      \
+        SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
+#define DCBX_MAX_NUM_PG_BW_ENTRIES      8
+#define DCBX_BW_PG_BITWIDTH             8
+#define DCBX_PG_BW_GET(a, i)            \
+        SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
+#define DCBX_PG_BW_SET(a, i, val)       \
+        SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
+#define DCBX_STRICT_PRI_PG              15
+#define DCBX_MAX_APP_PROTOCOL           16
+#define FCOE_APP_IDX                    0
+#define ISCSI_APP_IDX                   1
+#define PREDEFINED_APP_IDX_MAX          2
+
+struct dcbx_ets_feature {
+        u32 enabled;
+        u32  pg_bw_tbl[2];
+        u32  pri_pg_tbl[1];
+};
+
+struct dcbx_pfc_feature {
+#ifdef __BIG_ENDIAN
+        u8 pri_en_bitmap;
+#define DCBX_PFC_PRI_0 0x01
+#define DCBX_PFC_PRI_1 0x02
+#define DCBX_PFC_PRI_2 0x04
+#define DCBX_PFC_PRI_3 0x08
+#define DCBX_PFC_PRI_4 0x10
+#define DCBX_PFC_PRI_5 0x20
+#define DCBX_PFC_PRI_6 0x40
+#define DCBX_PFC_PRI_7 0x80
+        u8 pfc_caps;
+        u8 reserved;
+        u8 enabled;
+#elif defined(__LITTLE_ENDIAN)
+        u8 enabled;
+        u8 reserved;
+        u8 pfc_caps;
+        u8 pri_en_bitmap;
+#define DCBX_PFC_PRI_0 0x01
+#define DCBX_PFC_PRI_1 0x02
+#define DCBX_PFC_PRI_2 0x04
+#define DCBX_PFC_PRI_3 0x08
+#define DCBX_PFC_PRI_4 0x10
+#define DCBX_PFC_PRI_5 0x20
+#define DCBX_PFC_PRI_6 0x40
+#define DCBX_PFC_PRI_7 0x80
+#endif
+};
+
+struct dcbx_app_priority_entry {
+#ifdef __BIG_ENDIAN
+        u16     app_id;
+        u8      pri_bitmap;
+        u8      appBitfield;
+#define DCBX_APP_ENTRY_VALID         0x01
+#define DCBX_APP_ENTRY_SF_MASK       0x30
+#define DCBX_APP_ENTRY_SF_SHIFT      4
+#define DCBX_APP_SF_ETH_TYPE         0x10
+#define DCBX_APP_SF_PORT             0x20
+#elif defined(__LITTLE_ENDIAN)
+        u8 appBitfield;
+#define DCBX_APP_ENTRY_VALID         0x01
+#define DCBX_APP_ENTRY_SF_MASK       0x30
+#define DCBX_APP_ENTRY_SF_SHIFT      4
+#define DCBX_APP_SF_ETH_TYPE         0x10
+#define DCBX_APP_SF_PORT             0x20
+        u8      pri_bitmap;
+        u16     app_id;
+#endif
+};
+
+struct dcbx_app_priority_feature {
+#ifdef __BIG_ENDIAN
+        u8 reserved;
+        u8 default_pri;
+        u8 tc_supported;
+        u8 enabled;
+#elif defined(__LITTLE_ENDIAN)
+        u8 enabled;
+        u8 tc_supported;
+        u8 default_pri;
+        u8 reserved;
+#endif
+        struct dcbx_app_priority_entry  app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
+};
+
+struct dcbx_features {
+        struct dcbx_ets_feature ets;
+        struct dcbx_pfc_feature pfc;
+        struct dcbx_app_priority_feature app;
+};
+
+struct lldp_params {
+#ifdef __BIG_ENDIAN
+        u8      msg_fast_tx_interval;
+        u8      msg_tx_hold;
+        u8      msg_tx_interval;
+        u8      admin_status;
+#define LLDP_TX_ONLY  0x01
+#define LLDP_RX_ONLY  0x02
+#define LLDP_TX_RX    0x03
+#define LLDP_DISABLED 0x04
+        u8      reserved1;
+        u8      tx_fast;
+        u8      tx_crd_max;
+        u8      tx_crd;
+#elif defined(__LITTLE_ENDIAN)
+        u8      admin_status;
+#define LLDP_TX_ONLY  0x01
+#define LLDP_RX_ONLY  0x02
+#define LLDP_TX_RX    0x03
+#define LLDP_DISABLED 0x04
+        u8      msg_tx_interval;
+        u8      msg_tx_hold;
+        u8      msg_fast_tx_interval;
+        u8      tx_crd;
+        u8      tx_crd_max;
+        u8      tx_fast;
+        u8      reserved1;
+#endif
+#define REM_CHASSIS_ID_STAT_LEN 4
+#define REM_PORT_ID_STAT_LEN 4
+        u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
+        u32 peer_port_id[REM_PORT_ID_STAT_LEN];
+};
+
+struct lldp_dcbx_stat {
+#define LOCAL_CHASSIS_ID_STAT_LEN 2
+#define LOCAL_PORT_ID_STAT_LEN 2
+        u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
+        u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
+        u32 num_tx_dcbx_pkts;
+        u32 num_rx_dcbx_pkts;
+};
+
+struct lldp_admin_mib {
+        u32     ver_cfg_flags;
+#define DCBX_ETS_CONFIG_TX_ENABLED      0x00000001
+#define DCBX_PFC_CONFIG_TX_ENABLED      0x00000002
+#define DCBX_APP_CONFIG_TX_ENABLED      0x00000004
+#define DCBX_ETS_RECO_TX_ENABLED        0x00000008
+#define DCBX_ETS_RECO_VALID             0x00000010
+#define DCBX_ETS_WILLING                0x00000020
+#define DCBX_PFC_WILLING                0x00000040
+#define DCBX_APP_WILLING                0x00000080
+#define DCBX_VERSION_CEE                0x00000100
+#define DCBX_VERSION_IEEE               0x00000200
+#define DCBX_DCBX_ENABLED               0x00000400
+#define DCBX_CEE_VERSION_MASK           0x0000f000
+#define DCBX_CEE_VERSION_SHIFT          12
+#define DCBX_CEE_MAX_VERSION_MASK       0x000f0000
+#define DCBX_CEE_MAX_VERSION_SHIFT      16
+        struct dcbx_features    features;
+};
+
+struct lldp_remote_mib {
+        u32 prefix_seq_num;
+        u32 flags;
+#define DCBX_ETS_TLV_RX     0x00000001
+#define DCBX_PFC_TLV_RX     0x00000002
+#define DCBX_APP_TLV_RX     0x00000004
+#define DCBX_ETS_RX_ERROR   0x00000010
+#define DCBX_PFC_RX_ERROR   0x00000020
+#define DCBX_APP_RX_ERROR   0x00000040
+#define DCBX_ETS_REM_WILLING    0x00000100
+#define DCBX_PFC_REM_WILLING    0x00000200
+#define DCBX_APP_REM_WILLING    0x00000400
+#define DCBX_REMOTE_ETS_RECO_VALID  0x00001000
+        struct dcbx_features features;
+        u32 suffix_seq_num;
+};
+
+struct lldp_local_mib {
+        u32 prefix_seq_num;
+        u32 error;
+#define DCBX_LOCAL_ETS_ERROR     0x00000001
+#define DCBX_LOCAL_PFC_ERROR     0x00000002
+#define DCBX_LOCAL_APP_ERROR     0x00000004
+#define DCBX_LOCAL_PFC_MISMATCH  0x00000010
+#define DCBX_LOCAL_APP_MISMATCH  0x00000020
+        struct dcbx_features   features;
+        u32 suffix_seq_num;
+};
+/***END OF DCBX STRUCTURES DECLARATIONS***/
 
 struct shmem2_region {
 
@@ -1072,7 +1361,12 @@ struct shmem2_region {
 #define SHMEM_MF_CFG_ADDR_NONE                      0x00000000
 
         struct fw_flr_mb flr_mb;
-        u32     reserved[3];
+        u32     dcbx_lldp_params_offset;
+#define SHMEM_LLDP_DCBX_PARAMS_NONE                 0x00000000
+        u32     dcbx_neg_res_offset;
+#define SHMEM_DCBX_NEG_RES_NONE                     0x00000000
+        u32     dcbx_remote_mib_offset;
+#define SHMEM_DCBX_REMOTE_MIB_NONE                  0x00000000
         /*
          * The other shmemX_base_addr holds the other path's shmem address
          * required for example in case of common phy init, or for path1 to know
@@ -1081,6 +1375,10 @@ struct shmem2_region {
          */
         u32 other_shmem_base_addr;
         u32 other_shmem2_base_addr;
+        u32     reserved1[E2_VF_MAX / 32];
+        u32     reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
+        u32     dcbx_lldp_dcbx_stat_offset;
+#define SHMEM_LLDP_DCBX_STAT_NONE                  0x00000000
 };
 
 
@@ -1534,8 +1832,8 @@ struct host_func_stats {
 
 
 #define BCM_5710_FW_MAJOR_VERSION                       6
-#define BCM_5710_FW_MINOR_VERSION                       0
-#define BCM_5710_FW_REVISION_VERSION                    34
+#define BCM_5710_FW_MINOR_VERSION                       2
+#define BCM_5710_FW_REVISION_VERSION                    5
 #define BCM_5710_FW_ENGINEERING_VERSION                 0
 #define BCM_5710_FW_COMPILE_FLAGS                       1
 
@@ -2983,6 +3281,25 @@ struct fairness_vars_per_vn {
 
 
 /*
+ * The data for flow control configuration
+ */
+struct flow_control_configuration {
+        struct priority_cos
+                traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
+#if defined(__BIG_ENDIAN)
+        u16 reserved1;
+        u8 dcb_version;
+        u8 dcb_enabled;
+#elif defined(__LITTLE_ENDIAN)
+        u8 dcb_enabled;
+        u8 dcb_version;
+        u16 reserved1;
+#endif
+        u32 reserved2;
+};
+
+
+/*
  * FW version stored in the Xstorm RAM
  */
 struct fw_version {
diff --git a/drivers/net/bnx2x/bnx2x_init.h b/drivers/net/bnx2x/bnx2x_init.h
index a9d54874a559..5a268e9a0895 100644
--- a/drivers/net/bnx2x/bnx2x_init.h
+++ b/drivers/net/bnx2x/bnx2x_init.h
@@ -192,5 +192,225 @@ struct src_ent {
         u64 next;
 };
 
+/****************************************************************************
+* Parity configuration
+****************************************************************************/
+#define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
+{ \
+        block##_REG_##block##_PRTY_MASK, \
+        block##_REG_##block##_PRTY_STS_CLR, \
+        en_mask, {m1, m1h, m2}, #block \
+}
+
+#define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
+{ \
+        block##_REG_##block##_PRTY_MASK_0, \
+        block##_REG_##block##_PRTY_STS_CLR_0, \
+        en_mask, {m1, m1h, m2}, #block"_0" \
+}
+
+#define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
+{ \
+        block##_REG_##block##_PRTY_MASK_1, \
+        block##_REG_##block##_PRTY_STS_CLR_1, \
+        en_mask, {m1, m1h, m2}, #block"_1" \
+}
+
+static const struct {
+        u32 mask_addr;
+        u32 sts_clr_addr;
+        u32 en_mask;            /* Mask to enable parity attentions */
+        struct {
+                u32 e1;         /* 57710 */
+                u32 e1h;        /* 57711 */
+                u32 e2;         /* 57712 */
+        } reg_mask;             /* Register mask (all valid bits) */
+        char name[7];           /* Block's longest name is 6 characters long
+                                 * (name + suffix)
+                                 */
+} bnx2x_blocks_parity_data[] = {
+        /* bit 19 masked */
+        /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
+        /* bit 5,18,20-31 */
+        /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
+        /* bit 5 */
+        /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
+        /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
+        /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
+
+        /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
+         * want to handle "system kill" flow at the moment.
+         */
+        BLOCK_PRTY_INFO(PXP, 0x3ffffff, 0x3ffffff, 0x3ffffff, 0x3ffffff),
+        BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
+        BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
+        BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
+        BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
+        BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
+        BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
+        {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
+                GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,
+                {0xf, 0xf, 0xf}, "UPB"},
+        {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
+                GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
+                {0xf, 0xf, 0xf}, "XPB"},
+        BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
+        BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
+        BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
+        BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
+        BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
+        BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
+        BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
+        BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
+        BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
+        BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
+        BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
+        BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
+        BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
+};
+
+
+/* [28] MCP Latched rom_parity
+ * [29] MCP Latched ump_rx_parity
+ * [30] MCP Latched ump_tx_parity
+ * [31] MCP Latched scpad_parity
+ */
+#define MISC_AEU_ENABLE_MCP_PRTY_BITS   \
+        (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
+         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
+         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
+         AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
+
+/* Below registers control the MCP parity attention output. When
+ * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
+ * enabled, when cleared - disabled.
+ */
+static const u32 mcp_attn_ctl_regs[] = {
+        MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
+        MISC_REG_AEU_ENABLE4_NIG_0,
+        MISC_REG_AEU_ENABLE4_PXP_0,
+        MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
+        MISC_REG_AEU_ENABLE4_NIG_1,
+        MISC_REG_AEU_ENABLE4_PXP_1
+};
+
+static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
+{
+        int i;
+        u32 reg_val;
+
+        for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
+                reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
+
+                if (enable)
+                        reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
+                else
+                        reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
+
+                REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
+        }
+}
+
+static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
+{
+        if (CHIP_IS_E1(bp))
+                return bnx2x_blocks_parity_data[idx].reg_mask.e1;
+        else if (CHIP_IS_E1H(bp))
+                return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
+        else
+                return bnx2x_blocks_parity_data[idx].reg_mask.e2;
+}
+
+static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
+                u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
+
+                if (dis_mask) {
+                        REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
+                               dis_mask);
+                        DP(NETIF_MSG_HW, "Setting parity mask "
+                                                 "for %s to\t\t0x%x\n",
+                                    bnx2x_blocks_parity_data[i].name, dis_mask);
+                }
+        }
+
+        /* Disable MCP parity attentions */
+        bnx2x_set_mcp_parity(bp, false);
+}
+
+/**
+ * Clear the parity error status registers.
+ */
+static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
+{
+        int i;
+        u32 reg_val, mcp_aeu_bits =
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
+                AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
+
+        /* Clear SEM_FAST parities */
+        REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+        REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+        REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+        REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
+
+        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
+                u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
+
+                if (reg_mask) {
+                        reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
+                                         sts_clr_addr);
+                        if (reg_val & reg_mask)
+                                DP(NETIF_MSG_HW,
+                                            "Parity errors in %s: 0x%x\n",
+                                            bnx2x_blocks_parity_data[i].name,
+                                            reg_val & reg_mask);
+                }
+        }
+
+        /* Check if there were parity attentions in MCP */
+        reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
+        if (reg_val & mcp_aeu_bits)
+                DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
+                   reg_val & mcp_aeu_bits);
+
+        /* Clear parity attentions in MCP:
+         * [7]  clears Latched rom_parity
+         * [8]  clears Latched ump_rx_parity
+         * [9]  clears Latched ump_tx_parity
+         * [10] clears Latched scpad_parity (both ports)
+         */
+        REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
+}
+
+static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
+                u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
+
+                if (reg_mask)
+                        REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
+                                bnx2x_blocks_parity_data[i].en_mask & reg_mask);
+        }
+
+        /* Enable MCP parity attentions */
+        bnx2x_set_mcp_parity(bp, true);
+}
+
+
 #endif /* BNX2X_INIT_H */
 
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c
index 580919619252..43b0de24f391 100644
--- a/drivers/net/bnx2x/bnx2x_link.c
+++ b/drivers/net/bnx2x/bnx2x_link.c
@@ -164,7 +164,8 @@
 #define EDC_MODE_PASSIVE_DAC                    0x0055
 
 
-
+#define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
+#define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 /**********************************************************/
 /*                     INTERFACE                          */
 /**********************************************************/
@@ -205,6 +206,270 @@ static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
         return val;
 }
 
+/******************************************************************/
+/*                              ETS section                       */
+/******************************************************************/
+void bnx2x_ets_disabled(struct link_params *params)
+{
+        /* ETS disabled configuration*/
+        struct bnx2x *bp = params->bp;
+
+        DP(NETIF_MSG_LINK, "ETS disabled configuration\n");
+
+        /**
+         * mapping between entry  priority to client number (0,1,2 -debug and
+         * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
+         * 3bits client num.
+         *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
+         * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
+         */
+
+        REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
+        /**
+         * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+         * as strict.  Bits 0,1,2 - debug and management entries, 3 -
+         * COS0 entry, 4 - COS1 entry.
+         * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
+         * bit4   bit3    bit2   bit1     bit0
+         * MCP and debug are strict
+         */
+
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
+        /* defines which entries (clients) are subjected to WFQ arbitration */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
+        /**
+        * For strict priority entries defines the number of consecutive
+        * slots for the highest priority.
+        */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+        /**
+         * mapping between the CREDIT_WEIGHT registers and actual client
+         * numbers
+         */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
+
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
+        REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
+        /* ETS mode disable */
+        REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
+        /**
+         * If ETS mode is enabled (there is no strict priority) defines a WFQ
+         * weight for COS0/COS1.
+         */
+        REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
+        REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
+        /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
+        REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
+        REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
+        /* Defines the number of consecutive slots for the strict priority */
+        REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
+}
+
+void bnx2x_ets_bw_limit_common(const struct link_params *params)
+{
+        /* ETS disabled configuration */
+        struct bnx2x *bp = params->bp;
+        DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
+        /**
+        * defines which entries (clients) are subjected to WFQ arbitration
+        * COS0 0x8
+        * COS1 0x10
+        */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
+        /**
+        * mapping between the ARB_CREDIT_WEIGHT registers and actual
+        * client numbers (WEIGHT_0 does not actually have to represent
+        * client 0)
+        *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
+        *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
+        */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
+
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
+               ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
+               ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+
+        /* ETS mode enabled*/
+        REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
+
+        /* Defines the number of consecutive slots for the strict priority */
+        REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
+        /**
+        * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+        * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
+        * entry, 4 - COS1 entry.
+        * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
+        * bit4   bit3     bit2     bit1    bit0
+        * MCP and debug are strict
+        */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
+
+        /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
+        REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
+               ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+        REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
+               ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
+}
+
+void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
+                        const u32 cos1_bw)
+{
+        /* ETS disabled configuration*/
+        struct bnx2x *bp = params->bp;
+        const u32 total_bw = cos0_bw + cos1_bw;
+        u32 cos0_credit_weight = 0;
+        u32 cos1_credit_weight = 0;
+
+        DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
+
+        if ((0 == total_bw) ||
+            (0 == cos0_bw) ||
+            (0 == cos1_bw)) {
+                DP(NETIF_MSG_LINK,
+                   "bnx2x_ets_bw_limit: Total BW can't be zero\n");
+                return;
+        }
+
+        cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
+                total_bw;
+        cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
+                total_bw;
+
+        bnx2x_ets_bw_limit_common(params);
+
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
+
+        REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
+        REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
+}
+
+u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
+{
+        /* ETS disabled configuration*/
+        struct bnx2x *bp = params->bp;
+        u32 val = 0;
+
+        DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
+        /**
+         * Bitmap of 5bits length. Each bit specifies whether the entry behaves
+         * as strict.  Bits 0,1,2 - debug and management entries,
+         * 3 - COS0 entry, 4 - COS1 entry.
+         *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
+         *  bit4   bit3   bit2      bit1     bit0
+         * MCP and debug are strict
+         */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
+        /**
+         * For strict priority entries defines the number of consecutive slots
+         * for the highest priority.
+         */
+        REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
+        /* ETS mode disable */
+        REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
+        /* Defines the number of consecutive slots for the strict priority */
+        REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
+
+        /* Defines the number of consecutive slots for the strict priority */
+        REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
+
+        /**
+        * mapping between entry  priority to client number (0,1,2 -debug and
+        * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
+        * 3bits client num.
+        *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
+        * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
+        * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
+        */
+        val = (0 == strict_cos) ? 0x2318 : 0x22E0;
+        REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
+
+        return 0;
+}
+/******************************************************************/
+/*                      ETS section                               */
+/******************************************************************/
+
+static void bnx2x_bmac2_get_pfc_stat(struct link_params *params,
+                                     u32 pfc_frames_sent[2],
+                                     u32 pfc_frames_received[2])
+{
+        /* Read pfc statistic */
+        struct bnx2x *bp = params->bp;
+        u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
+                NIG_REG_INGRESS_BMAC0_MEM;
+
+        DP(NETIF_MSG_LINK, "pfc statistic read from BMAC\n");
+
+        REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_STAT_GTPP,
+                                        pfc_frames_sent, 2);
+
+        REG_RD_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_STAT_GRPP,
+                                        pfc_frames_received, 2);
+
+}
+static void bnx2x_emac_get_pfc_stat(struct link_params *params,
+                                    u32 pfc_frames_sent[2],
+                                    u32 pfc_frames_received[2])
+{
+        /* Read pfc statistic */
+        struct bnx2x *bp = params->bp;
+        u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
+        u32 val_xon = 0;
+        u32 val_xoff = 0;
+
+        DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
+
+        /* PFC received frames */
+        val_xoff = REG_RD(bp, emac_base +
+                                EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
+        val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
+        val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
+        val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
+
+        pfc_frames_received[0] = val_xon + val_xoff;
+
+        /* PFC received sent */
+        val_xoff = REG_RD(bp, emac_base +
+                                EMAC_REG_RX_PFC_STATS_XOFF_SENT);
+        val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
+        val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
+        val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
+
+        pfc_frames_sent[0] = val_xon + val_xoff;
+}
+
+void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
+                         u32 pfc_frames_sent[2],
+                         u32 pfc_frames_received[2])
+{
+        /* Read pfc statistic */
+        struct bnx2x *bp = params->bp;
+        u32 val = 0;
+        DP(NETIF_MSG_LINK, "pfc statistic\n");
+
+        if (!vars->link_up)
+                return;
+
+        val = REG_RD(bp, MISC_REG_RESET_REG_2);
+        if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
+            == 0) {
+                DP(NETIF_MSG_LINK, "About to read stats from EMAC\n");
+                bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
+                                        pfc_frames_received);
+        } else {
+                DP(NETIF_MSG_LINK, "About to read stats from BMAC\n");
+                bnx2x_bmac2_get_pfc_stat(params, pfc_frames_sent,
+                                         pfc_frames_received);
+        }
+}
+/******************************************************************/
+/*                      MAC/PBF section                           */
+/******************************************************************/
 static void bnx2x_emac_init(struct link_params *params,
                            struct link_vars *vars)
 {
@@ -315,24 +580,55 @@ static u8 bnx2x_emac_enable(struct link_params *params,
                 /* pause enable/disable */
                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
                                EMAC_RX_MODE_FLOW_EN);
-                if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
-                        bnx2x_bits_en(bp, emac_base +
-                                    EMAC_REG_EMAC_RX_MODE,
-                                    EMAC_RX_MODE_FLOW_EN);
 
                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
-                             (EMAC_TX_MODE_EXT_PAUSE_EN |
-                              EMAC_TX_MODE_FLOW_EN));
-                if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
-                        bnx2x_bits_en(bp, emac_base +
-                                    EMAC_REG_EMAC_TX_MODE,
-                                   (EMAC_TX_MODE_EXT_PAUSE_EN |
-                                    EMAC_TX_MODE_FLOW_EN));
+                               (EMAC_TX_MODE_EXT_PAUSE_EN |
+                                EMAC_TX_MODE_FLOW_EN));
+                if (!(params->feature_config_flags &
+                      FEATURE_CONFIG_PFC_ENABLED)) {
+                        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
+                                bnx2x_bits_en(bp, emac_base +
+                                              EMAC_REG_EMAC_RX_MODE,
+                                              EMAC_RX_MODE_FLOW_EN);
+
+                        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+                                bnx2x_bits_en(bp, emac_base +
+                                              EMAC_REG_EMAC_TX_MODE,
+                                              (EMAC_TX_MODE_EXT_PAUSE_EN |
+                                               EMAC_TX_MODE_FLOW_EN));
+                } else
+                        bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
+                                      EMAC_TX_MODE_FLOW_EN);
         }
 
         /* KEEP_VLAN_TAG, promiscuous */
         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
+
+        /**
+        * Setting this bit causes MAC control frames (except for pause
+        * frames) to be passed on for processing. This setting has no
+        * affect on the operation of the pause frames. This bit effects
+        * all packets regardless of RX Parser packet sorting logic.
+        * Turn the PFC off to make sure we are in Xon state before
+        * enabling it.
+        */
+        EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
+        if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
+                DP(NETIF_MSG_LINK, "PFC is enabled\n");
+                /* Enable PFC again */
+                EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
+                        EMAC_REG_RX_PFC_MODE_RX_EN |
+                        EMAC_REG_RX_PFC_MODE_TX_EN |
+                        EMAC_REG_RX_PFC_MODE_PRIORITIES);
+
+                EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
+                        ((0x0101 <<
+                          EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
+                         (0x00ff <<
+                          EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
+                val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
+        }
         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
 
         /* Set Loopback */
@@ -362,7 +658,9 @@ static u8 bnx2x_emac_enable(struct link_params *params,
         /* enable the NIG in/out to the emac */
         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
         val = 0;
-        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+        if ((params->feature_config_flags &
+              FEATURE_CONFIG_PFC_ENABLED) ||
+            (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
                 val = 1;
 
         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
@@ -383,9 +681,38 @@ static u8 bnx2x_emac_enable(struct link_params *params,
         return 0;
 }
 
-static void bnx2x_update_bmac2(struct link_params *params,
-                               struct link_vars *vars,
-                               u8 is_lb)
+static void bnx2x_update_pfc_bmac1(struct link_params *params,
+                                   struct link_vars *vars)
+{
+        u32 wb_data[2];
+        struct bnx2x *bp = params->bp;
+        u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
+                NIG_REG_INGRESS_BMAC0_MEM;
+
+        u32 val = 0x14;
+        if ((!(params->feature_config_flags &
+              FEATURE_CONFIG_PFC_ENABLED)) &&
+                (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
+                /* Enable BigMAC to react on received Pause packets */
+                val |= (1<<5);
+        wb_data[0] = val;
+        wb_data[1] = 0;
+        REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
+
+        /* tx control */
+        val = 0xc0;
+        if (!(params->feature_config_flags &
+              FEATURE_CONFIG_PFC_ENABLED) &&
+                (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
+                val |= 0x800000;
+        wb_data[0] = val;
+        wb_data[1] = 0;
+        REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
+}
+
+static void bnx2x_update_pfc_bmac2(struct link_params *params,
+                                   struct link_vars *vars,
+                                   u8 is_lb)
 {
         /*
          * Set rx control: Strip CRC and enable BigMAC to relay
@@ -397,7 +724,9 @@ static void bnx2x_update_bmac2(struct link_params *params,
                 NIG_REG_INGRESS_BMAC0_MEM;
         u32 val = 0x14;
 
-        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
+        if ((!(params->feature_config_flags &
+              FEATURE_CONFIG_PFC_ENABLED)) &&
+                (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
                 /* Enable BigMAC to react on received Pause packets */
                 val |= (1<<5);
         wb_data[0] = val;
@@ -408,14 +737,47 @@ static void bnx2x_update_bmac2(struct link_params *params,
 
         /* Tx control */
         val = 0xc0;
-        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+        if (!(params->feature_config_flags &
+                                FEATURE_CONFIG_PFC_ENABLED) &&
+            (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
                 val |= 0x800000;
         wb_data[0] = val;
         wb_data[1] = 0;
-        REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL,
-                        wb_data, 2);
+        REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
+
+        if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
+                DP(NETIF_MSG_LINK, "PFC is enabled\n");
+                /* Enable PFC RX & TX & STATS and set 8 COS  */
+                wb_data[0] = 0x0;
+                wb_data[0] |= (1<<0);  /* RX */
+                wb_data[0] |= (1<<1);  /* TX */
+                wb_data[0] |= (1<<2);  /* Force initial Xon */
+                wb_data[0] |= (1<<3);  /* 8 cos */
+                wb_data[0] |= (1<<5);  /* STATS */
+                wb_data[1] = 0;
+                REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
+                            wb_data, 2);
+                /* Clear the force Xon */
+                wb_data[0] &= ~(1<<2);
+        } else {
+                DP(NETIF_MSG_LINK, "PFC is disabled\n");
+                /* disable PFC RX & TX & STATS and set 8 COS */
+                wb_data[0] = 0x8;
+                wb_data[1] = 0;
+        }
+
+        REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
 
+        /**
+        * Set Time (based unit is 512 bit time) between automatic
+        * re-sending of PP packets amd enable automatic re-send of
+        * Per-Priroity Packet as long as pp_gen is asserted and
+        * pp_disable is low.
+        */
         val = 0x8000;
+        if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
+                val |= (1<<16); /* enable automatic re-send */
+
         wb_data[0] = val;
         wb_data[1] = 0;
         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
@@ -427,6 +789,9 @@ static void bnx2x_update_bmac2(struct link_params *params,
                 val |= 0x4; /* Local loopback */
                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
         }
+        /* When PFC enabled, Pass pause frames towards the NIG. */
+        if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
+                val |= ((1<<6)|(1<<5));
 
         wb_data[0] = val;
         wb_data[1] = 0;
@@ -434,6 +799,239 @@ static void bnx2x_update_bmac2(struct link_params *params,
                         wb_data, 2);
 }
 
+static void bnx2x_update_pfc_brb(struct link_params *params,
+                struct link_vars *vars,
+                struct bnx2x_nig_brb_pfc_port_params *pfc_params)
+{
+        struct bnx2x *bp = params->bp;
+        int set_pfc = params->feature_config_flags &
+                FEATURE_CONFIG_PFC_ENABLED;
+
+        /* default - pause configuration */
+        u32 pause_xoff_th = PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
+        u32 pause_xon_th = PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
+        u32 full_xoff_th = PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
+        u32 full_xon_th = PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
+
+        if (set_pfc && pfc_params)
+                /* First COS */
+                if (!pfc_params->cos0_pauseable) {
+                        pause_xoff_th =
+                          PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
+                        pause_xon_th =
+                          PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
+                        full_xoff_th =
+                          PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
+                        full_xon_th =
+                          PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
+                }
+        /* The number of free blocks below which the pause signal to class 0
+           of MAC #n is asserted. n=0,1 */
+        REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , pause_xoff_th);
+        /* The number of free blocks above which the pause signal to class 0
+           of MAC #n is de-asserted. n=0,1 */
+        REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , pause_xon_th);
+        /* The number of free blocks below which the full signal to class 0
+           of MAC #n is asserted. n=0,1 */
+        REG_WR(bp, BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , full_xoff_th);
+        /* The number of free blocks above which the full signal to class 0
+           of MAC #n is de-asserted. n=0,1 */
+        REG_WR(bp, BRB1_REG_FULL_0_XON_THRESHOLD_0 , full_xon_th);
+
+        if (set_pfc && pfc_params) {
+                /* Second COS */
+                if (pfc_params->cos1_pauseable) {
+                        pause_xoff_th =
+                          PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE;
+                        pause_xon_th =
+                          PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE;
+                        full_xoff_th =
+                          PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE;
+                        full_xon_th =
+                          PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE;
+                } else {
+                        pause_xoff_th =
+                          PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE;
+                        pause_xon_th =
+                          PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE;
+                        full_xoff_th =
+                          PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE;
+                        full_xon_th =
+                          PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE;
+                }
+                /**
+                 * The number of free blocks below which the pause signal to
+                 * class 1 of MAC #n is asserted. n=0,1
+                 **/
+                REG_WR(bp, BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, pause_xoff_th);
+                /**
+                 * The number of free blocks above which the pause signal to
+                 * class 1 of MAC #n is de-asserted. n=0,1
+                 **/
+                REG_WR(bp, BRB1_REG_PAUSE_1_XON_THRESHOLD_0, pause_xon_th);
+                /**
+                 * The number of free blocks below which the full signal to
+                 * class 1 of MAC #n is asserted. n=0,1
+                 **/
+                REG_WR(bp, BRB1_REG_FULL_1_XOFF_THRESHOLD_0, full_xoff_th);
+                /**
+                 * The number of free blocks above which the full signal to
+                 * class 1 of MAC #n is de-asserted. n=0,1
+                 **/
+                REG_WR(bp, BRB1_REG_FULL_1_XON_THRESHOLD_0, full_xon_th);
+        }
+}
+
+static void bnx2x_update_pfc_nig(struct link_params *params,
+                struct link_vars *vars,
+                struct bnx2x_nig_brb_pfc_port_params *nig_params)
+{
+        u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
+        u32 llfc_enable = 0, xcm0_out_en = 0, p0_hwpfc_enable = 0;
+        u32 pkt_priority_to_cos = 0;
+        u32 val;
+        struct bnx2x *bp = params->bp;
+        int port = params->port;
+        int set_pfc = params->feature_config_flags &
+                FEATURE_CONFIG_PFC_ENABLED;
+        DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
+
+        /**
+         * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
+         * MAC control frames (that are not pause packets)
+         * will be forwarded to the XCM.
+         */
+        xcm_mask = REG_RD(bp,
+                                port ? NIG_REG_LLH1_XCM_MASK :
+                                NIG_REG_LLH0_XCM_MASK);
+        /**
+         * nig params will override non PFC params, since it's possible to
+         * do transition from PFC to SAFC
+         */
+        if (set_pfc) {
+                pause_enable = 0;
+                llfc_out_en = 0;
+                llfc_enable = 0;
+                ppp_enable = 1;
+                xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
+                                     NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
+                xcm0_out_en = 0;
+                p0_hwpfc_enable = 1;
+        } else  {
+                if (nig_params) {
+                        llfc_out_en = nig_params->llfc_out_en;
+                        llfc_enable = nig_params->llfc_enable;
+                        pause_enable = nig_params->pause_enable;
+                } else  /*defaul non PFC mode - PAUSE */
+                        pause_enable = 1;
+
+                xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
+                        NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
+                xcm0_out_en = 1;
+        }
+
+        REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
+               NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
+        REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
+               NIG_REG_LLFC_ENABLE_0, llfc_enable);
+        REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
+               NIG_REG_PAUSE_ENABLE_0, pause_enable);
+
+        REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
+               NIG_REG_PPP_ENABLE_0, ppp_enable);
+
+        REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
+               NIG_REG_LLH0_XCM_MASK, xcm_mask);
+
+        REG_WR(bp,  NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
+
+        /* output enable for RX_XCM # IF */
+        REG_WR(bp, NIG_REG_XCM0_OUT_EN, xcm0_out_en);
+
+        /* HW PFC TX enable */
+        REG_WR(bp, NIG_REG_P0_HWPFC_ENABLE, p0_hwpfc_enable);
+
+        /* 0x2 = BMAC, 0x1= EMAC */
+        switch (vars->mac_type) {
+        case MAC_TYPE_EMAC:
+                val = 1;
+                break;
+        case MAC_TYPE_BMAC:
+                val = 0;
+                break;
+        default:
+                val = 0;
+                break;
+        }
+        REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT, val);
+
+        if (nig_params) {
+                pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
+
+                REG_WR(bp, port ? NIG_REG_P1_RX_COS0_PRIORITY_MASK :
+                       NIG_REG_P0_RX_COS0_PRIORITY_MASK,
+                       nig_params->rx_cos0_priority_mask);
+
+                REG_WR(bp, port ? NIG_REG_P1_RX_COS1_PRIORITY_MASK :
+                       NIG_REG_P0_RX_COS1_PRIORITY_MASK,
+                       nig_params->rx_cos1_priority_mask);
+
+                REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
+                       NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
+                       nig_params->llfc_high_priority_classes);
+
+                REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
+                       NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
+                       nig_params->llfc_low_priority_classes);
+        }
+        REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
+               NIG_REG_P0_PKT_PRIORITY_TO_COS,
+               pkt_priority_to_cos);
+}
+
+
+void bnx2x_update_pfc(struct link_params *params,
+                      struct link_vars *vars,
+                      struct bnx2x_nig_brb_pfc_port_params *pfc_params)
+{
+        /**
+         * The PFC and pause are orthogonal to one another, meaning when
+         * PFC is enabled, the pause are disabled, and when PFC is
+         * disabled, pause are set according to the pause result.
+         */
+        u32 val;
+        struct bnx2x *bp = params->bp;
+
+        /* update NIG params */
+        bnx2x_update_pfc_nig(params, vars, pfc_params);
+
+        /* update BRB params */
+        bnx2x_update_pfc_brb(params, vars, pfc_params);
+
+        if (!vars->link_up)
+                return;
+
+        val = REG_RD(bp, MISC_REG_RESET_REG_2);
+        if ((val & (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
+            == 0) {
+                DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
+                bnx2x_emac_enable(params, vars, 0);
+                return;
+        }
+
+        DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
+        if (CHIP_IS_E2(bp))
+                bnx2x_update_pfc_bmac2(params, vars, 0);
+        else
+                bnx2x_update_pfc_bmac1(params, vars);
+
+        val = 0;
+        if ((params->feature_config_flags &
+              FEATURE_CONFIG_PFC_ENABLED) ||
+            (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
+                val = 1;
+        REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
+}
 
 static u8 bnx2x_bmac1_enable(struct link_params *params,
                              struct link_vars *vars,
@@ -465,15 +1063,6 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
                     wb_data, 2);
 
-        /* tx control */
-        val = 0xc0;
-        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
-                val |= 0x800000;
-        wb_data[0] = val;
-        wb_data[1] = 0;
-        REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
-                        wb_data, 2);
-
         /* mac control */
         val = 0x3;
         if (is_lb) {
@@ -491,14 +1080,7 @@ static u8 bnx2x_bmac1_enable(struct link_params *params,
         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
                         wb_data, 2);
 
-        /* rx control set to don't strip crc */
-        val = 0x14;
-        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
-                val |= 0x20;
-        wb_data[0] = val;
-        wb_data[1] = 0;
-        REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
-                        wb_data, 2);
+        bnx2x_update_pfc_bmac1(params, vars);
 
         /* set tx mtu */
         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
@@ -595,7 +1177,7 @@ static u8 bnx2x_bmac2_enable(struct link_params *params,
         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE,
                         wb_data, 2);
         udelay(30);
-        bnx2x_update_bmac2(params, vars, is_lb);
+        bnx2x_update_pfc_bmac2(params, vars, is_lb);
 
         return 0;
 }
@@ -627,7 +1209,9 @@ static u8 bnx2x_bmac_enable(struct link_params *params,
         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
         val = 0;
-        if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
+        if ((params->feature_config_flags &
+              FEATURE_CONFIG_PFC_ENABLED) ||
+            (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
                 val = 1;
         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
@@ -3904,7 +4488,7 @@ static u8 bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
-                        return 0;;
+                        return 0;
                 msleep(1);
         }
         return -EINVAL;
@@ -3988,7 +4572,7 @@ static u8 bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
                               MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
-                        return 0;;
+                        return 0;
                 msleep(1);
         }
 
diff --git a/drivers/net/bnx2x/bnx2x_link.h b/drivers/net/bnx2x/bnx2x_link.h
index 171abf8097ee..bedab1a942c4 100644
--- a/drivers/net/bnx2x/bnx2x_link.h
+++ b/drivers/net/bnx2x/bnx2x_link.h
@@ -65,6 +65,22 @@
 #define FW_PARAM_MDIO_CTRL_OFFSET 16
 #define FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
         (phy_addr | phy_type | mdio_access << FW_PARAM_MDIO_CTRL_OFFSET)
+
+#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_PAUSEABLE              170
+#define PFC_BRB_MAC_PAUSE_XOFF_THRESHOLD_NON_PAUSEABLE          0
+
+#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_PAUSEABLE                       250
+#define PFC_BRB_MAC_PAUSE_XON_THRESHOLD_NON_PAUSEABLE           0
+
+#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_PAUSEABLE                       10
+#define PFC_BRB_MAC_FULL_XOFF_THRESHOLD_NON_PAUSEABLE           90
+
+#define PFC_BRB_MAC_FULL_XON_THRESHOLD_PAUSEABLE                        50
+#define PFC_BRB_MAC_FULL_XON_THRESHOLD_NON_PAUSEABLE            250
+
+#define PFC_BRB_FULL_LB_XOFF_THRESHOLD                          170
+#define PFC_BRB_FULL_LB_XON_THRESHOLD                           250
+
 /***********************************************************/
 /*                         Structs                         */
 /***********************************************************/
@@ -216,6 +232,7 @@ struct link_params {
 
         u32 feature_config_flags;
 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
+#define FEATURE_CONFIG_PFC_ENABLED              (1<<1)
 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
 #define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY        (1<<3)
         /* Will be populated during common init */
@@ -332,4 +349,43 @@ u8 bnx2x_phy_probe(struct link_params *params);
 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
                              u32 shmem2_base, u8 port);
 
+/* PFC port configuration params */
+struct bnx2x_nig_brb_pfc_port_params {
+        /* NIG */
+        u32 pause_enable;
+        u32 llfc_out_en;
+        u32 llfc_enable;
+        u32 pkt_priority_to_cos;
+        u32 rx_cos0_priority_mask;
+        u32 rx_cos1_priority_mask;
+        u32 llfc_high_priority_classes;
+        u32 llfc_low_priority_classes;
+        /* BRB */
+        u32 cos0_pauseable;
+        u32 cos1_pauseable;
+};
+
+/**
+ * Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
+ * when link is already up
+ */
+void bnx2x_update_pfc(struct link_params *params,
+                      struct link_vars *vars,
+                      struct bnx2x_nig_brb_pfc_port_params *pfc_params);
+
+
+/* Used to configure the ETS to disable */
+void bnx2x_ets_disabled(struct link_params *params);
+
+/* Used to configure the ETS to BW limited */
+void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
+                                                const u32 cos1_bw);
+
+/* Used to configure the ETS to strict */
+u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
+
+/* Read pfc statistic*/
+void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
+                                                 u32 pfc_frames_sent[2],
+                                                 u32 pfc_frames_received[2]);
 #endif /* BNX2X_LINK_H */
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index be52edcf8346..8cdcf5b39d1e 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -55,6 +55,7 @@
 #include "bnx2x_init.h"
 #include "bnx2x_init_ops.h"
 #include "bnx2x_cmn.h"
+#include "bnx2x_dcb.h"
 
 #include <linux/firmware.h>
 #include "bnx2x_fw_file_hdr.h"
@@ -121,6 +122,10 @@ MODULE_PARM_DESC(debug, " Default debug msglevel");
 
 static struct workqueue_struct *bnx2x_wq;
 
+#ifdef BCM_CNIC
+static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
+#endif
+
 enum bnx2x_board_type {
         BCM57710 = 0,
         BCM57711 = 1,
@@ -921,7 +926,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
                sp_sb_data.p_func.vf_valid);
 
 
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
                 int loop;
                 struct hc_status_block_data_e2 sb_data_e2;
@@ -961,6 +966,10 @@ void bnx2x_panic_dump(struct bnx2x *bp)
 
                 /* host sb data */
 
+#ifdef BCM_CNIC
+                if (IS_FCOE_FP(fp))
+                        continue;
+#endif
                 BNX2X_ERR("     run indexes (");
                 for (j = 0; j < HC_SB_MAX_SM; j++)
                         pr_cont("0x%x%s",
@@ -1029,7 +1038,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
 #ifdef BNX2X_STOP_ON_ERROR
         /* Rings */
         /* Rx */
-        for_each_queue(bp, i) {
+        for_each_rx_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
 
                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
@@ -1063,7 +1072,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
         }
 
         /* Tx */
-        for_each_queue(bp, i) {
+        for_each_tx_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
 
                 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
@@ -1298,7 +1307,7 @@ void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
 #ifdef BCM_CNIC
                 offset++;
 #endif
-                for_each_queue(bp, i)
+                for_each_eth_queue(bp, i)
                         synchronize_irq(bp->msix_table[i + offset].vector);
         } else
                 synchronize_irq(bp->pdev->irq);
@@ -1420,7 +1429,7 @@ irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
                 return IRQ_HANDLED;
 #endif
 
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
 
                 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
@@ -2026,13 +2035,28 @@ static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
 
 static void bnx2x_read_mf_cfg(struct bnx2x *bp)
 {
-        int vn;
+        int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
 
         if (BP_NOMCP(bp))
                 return; /* what should be the default bvalue in this case */
 
+        /* For 2 port configuration the absolute function number formula
+         * is:
+         *      abs_func = 2 * vn + BP_PORT + BP_PATH
+         *
+         *      and there are 4 functions per port
+         *
+         * For 4 port configuration it is
+         *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
+         *
+         *      and there are 2 functions per port
+         */
         for (vn = VN_0; vn < E1HVN_MAX; vn++) {
-                int /*abs*/func = 2*vn + BP_PORT(bp);
+                int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
+
+                if (func >= E1H_FUNC_MAX)
+                        break;
+
                 bp->mf_config[vn] =
                         MF_CFG_RD(bp, func_mf_config[func].config);
         }
@@ -2238,6 +2262,15 @@ u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
         return rc;
 }
 
+static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
+{
+#ifdef BCM_CNIC
+        if (IS_FCOE_FP(fp) && IS_MF(bp))
+                return false;
+#endif
+        return true;
+}
+
 /* must be called under rtnl_lock */
 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
 {
@@ -2248,10 +2281,21 @@ static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
         u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
         u8 unmatched_unicast = 0;
 
+        if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
+                unmatched_unicast = 1;
+
         if (filters & BNX2X_PROMISCUOUS_MODE) {
                 /* promiscious - accept all, drop none */
                 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
                 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
+                if (IS_MF_SI(bp)) {
+                        /*
+                         * SI mode defines to accept in promiscuos mode
+                         * only unmatched packets
+                         */
+                        unmatched_unicast = 1;
+                        accp_all_ucast = 0;
+                }
         }
         if (filters & BNX2X_ACCEPT_UNICAST) {
                 /* accept matched ucast */
@@ -2260,6 +2304,11 @@ static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
         if (filters & BNX2X_ACCEPT_MULTICAST) {
                 /* accept matched mcast */
                 drop_all_mcast = 0;
+                if (IS_MF_SI(bp))
+                        /* since mcast addresses won't arrive with ovlan,
+                         * fw needs to accept all of them in
+                         * switch-independent mode */
+                        accp_all_mcast = 1;
         }
         if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
                 /* accept all mcast */
@@ -2372,7 +2421,7 @@ static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
         /* calculate queue flags */
         flags |= QUEUE_FLG_CACHE_ALIGN;
         flags |= QUEUE_FLG_HC;
-        flags |= IS_MF(bp) ? QUEUE_FLG_OV : 0;
+        flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
 
         flags |= QUEUE_FLG_VLAN;
         DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
@@ -2380,7 +2429,8 @@ static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
         if (!fp->disable_tpa)
                 flags |= QUEUE_FLG_TPA;
 
-        flags |= QUEUE_FLG_STATS;
+        flags = stat_counter_valid(bp, fp) ?
+                        (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
 
         return flags;
 }
@@ -2440,7 +2490,10 @@ static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
         rxq_init->fw_sb_id = fp->fw_sb_id;
 
-        rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
+        if (IS_FCOE_FP(fp))
+                rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
+        else
+                rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
 
         rxq_init->cid = HW_CID(bp, fp->cid);
 
@@ -2460,6 +2513,12 @@ static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
         txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
         txq_init->fw_sb_id = fp->fw_sb_id;
+
+        if (IS_FCOE_FP(fp)) {
+                txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
+                txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
+        }
+
         txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
 }
 
@@ -2573,6 +2632,26 @@ static void bnx2x_e1h_enable(struct bnx2x *bp)
          */
 }
 
+/* called due to MCP event (on pmf):
+ *      reread new bandwidth configuration
+ *      configure FW
+ *      notify others function about the change
+ */
+static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
+{
+        if (bp->link_vars.link_up) {
+                bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
+                bnx2x_link_sync_notify(bp);
+        }
+        storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
+}
+
+static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
+{
+        bnx2x_config_mf_bw(bp);
+        bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
+}
+
 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
 {
         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
@@ -2598,10 +2677,7 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
         }
         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
-
-                bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
-                bnx2x_link_sync_notify(bp);
-                storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
+                bnx2x_config_mf_bw(bp);
                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
         }
 
@@ -3022,10 +3098,20 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
                         if (val & DRV_STATUS_DCC_EVENT_MASK)
                                 bnx2x_dcc_event(bp,
                                             (val & DRV_STATUS_DCC_EVENT_MASK));
+
+                        if (val & DRV_STATUS_SET_MF_BW)
+                                bnx2x_set_mf_bw(bp);
+
                         bnx2x__link_status_update(bp);
                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
                                 bnx2x_pmf_update(bp);
 
+                        if (bp->port.pmf &&
+                            (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
+                                bp->dcbx_enabled > 0)
+                                /* start dcbx state machine */
+                                bnx2x_dcbx_set_params(bp,
+                                        BNX2X_DCBX_STATE_NEG_RECEIVED);
                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
 
                         BNX2X_ERR("MC assert!\n");
@@ -3066,7 +3152,6 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
 #define LOAD_COUNTER_MASK       (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
 #define RESET_DONE_FLAG_MASK    (~LOAD_COUNTER_MASK)
 #define RESET_DONE_FLAG_SHIFT   LOAD_COUNTER_BITS
-#define CHIP_PARITY_SUPPORTED(bp)   (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp))
 
 /*
  * should be run under rtnl lock
@@ -3441,7 +3526,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
            try to handle this event */
         bnx2x_acquire_alr(bp);
 
-        if (bnx2x_chk_parity_attn(bp)) {
+        if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
                 bp->recovery_state = BNX2X_RECOVERY_INIT;
                 bnx2x_set_reset_in_progress(bp);
                 schedule_delayed_work(&bp->reset_task, 0);
@@ -3637,11 +3722,23 @@ static void bnx2x_eq_int(struct bnx2x *bp)
 #ifdef BCM_CNIC
                         if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
                                 goto next_spqe;
+                        if (cid == BNX2X_FCOE_ETH_CID)
+                                bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
+                        else
 #endif
-                        bnx2x_fp(bp, cid, state) =
+                                bnx2x_fp(bp, cid, state) =
                                                 BNX2X_FP_STATE_CLOSED;
 
                         goto next_spqe;
+
+                case EVENT_RING_OPCODE_STOP_TRAFFIC:
+                        DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
+                        bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
+                        goto next_spqe;
+                case EVENT_RING_OPCODE_START_TRAFFIC:
+                        DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
+                        bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
+                        goto next_spqe;
                 }
 
                 switch (opcode | bp->state) {
@@ -3714,7 +3811,13 @@ static void bnx2x_sp_task(struct work_struct *work)
 
         /* SP events: STAT_QUERY and others */
         if (status & BNX2X_DEF_SB_IDX) {
+#ifdef BCM_CNIC
+                struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
 
+                if ((!NO_FCOE(bp)) &&
+                        (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
+                        napi_schedule(&bnx2x_fcoe(bp, napi));
+#endif
                 /* Handle EQ completions */
                 bnx2x_eq_int(bp);
 
@@ -4097,7 +4200,7 @@ void bnx2x_update_coalesce(struct bnx2x *bp)
 {
         int i;
 
-        for_each_queue(bp, i)
+        for_each_eth_queue(bp, i)
                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
                                          bp->rx_ticks, bp->tx_ticks);
 }
@@ -4145,13 +4248,16 @@ static void bnx2x_init_ind_table(struct bnx2x *bp)
         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
                         TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
-                        bp->fp->cl_id + (i % bp->num_queues));
+                        bp->fp->cl_id + (i % (bp->num_queues -
+                                NONE_ETH_CONTEXT_USE)));
 }
 
 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
 {
         int mode = bp->rx_mode;
+        int port = BP_PORT(bp);
         u16 cl_id;
+        u32 def_q_filters = 0;
 
         /* All but management unicast packets should pass to the host as well */
         u32 llh_mask =
@@ -4162,30 +4268,42 @@ void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
 
         switch (mode) {
         case BNX2X_RX_MODE_NONE: /* no Rx */
-                cl_id = BP_L_ID(bp);
-                bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
+                def_q_filters = BNX2X_ACCEPT_NONE;
+#ifdef BCM_CNIC
+                if (!NO_FCOE(bp)) {
+                        cl_id = bnx2x_fcoe(bp, cl_id);
+                        bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
+                }
+#endif
                 break;
 
         case BNX2X_RX_MODE_NORMAL:
-                cl_id = BP_L_ID(bp);
-                bnx2x_rxq_set_mac_filters(bp, cl_id,
-                        BNX2X_ACCEPT_UNICAST |
-                        BNX2X_ACCEPT_BROADCAST |
-                        BNX2X_ACCEPT_MULTICAST);
+                def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
+                                BNX2X_ACCEPT_MULTICAST;
+#ifdef BCM_CNIC
+                cl_id = bnx2x_fcoe(bp, cl_id);
+                bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
+                                          BNX2X_ACCEPT_MULTICAST);
+#endif
                 break;
 
         case BNX2X_RX_MODE_ALLMULTI:
-                cl_id = BP_L_ID(bp);
-                bnx2x_rxq_set_mac_filters(bp, cl_id,
-                        BNX2X_ACCEPT_UNICAST |
-                        BNX2X_ACCEPT_BROADCAST |
-                        BNX2X_ACCEPT_ALL_MULTICAST);
+                def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
+                                BNX2X_ACCEPT_ALL_MULTICAST;
+#ifdef BCM_CNIC
+                cl_id = bnx2x_fcoe(bp, cl_id);
+                bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
+                                          BNX2X_ACCEPT_MULTICAST);
+#endif
                 break;
 
         case BNX2X_RX_MODE_PROMISC:
-                cl_id = BP_L_ID(bp);
-                bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_PROMISCUOUS_MODE);
-
+                def_q_filters |= BNX2X_PROMISCUOUS_MODE;
+#ifdef BCM_CNIC
+                cl_id = bnx2x_fcoe(bp, cl_id);
+                bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_UNICAST |
+                                          BNX2X_ACCEPT_MULTICAST);
+#endif
                 /* pass management unicast packets as well */
                 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
                 break;
@@ -4195,20 +4313,24 @@ void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
                 break;
         }
 
+        cl_id = BP_L_ID(bp);
+        bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
+
         REG_WR(bp,
-               BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
-                             NIG_REG_LLH0_BRB1_DRV_MASK,
-               llh_mask);
+               (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
+                       NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
 
         DP(NETIF_MSG_IFUP, "rx mode %d\n"
                 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
-                "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n", mode,
+                "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
+                "unmatched_ucast 0x%x\n", mode,
                 bp->mac_filters.ucast_drop_all,
                 bp->mac_filters.mcast_drop_all,
                 bp->mac_filters.bcast_drop_all,
                 bp->mac_filters.ucast_accept_all,
                 bp->mac_filters.mcast_accept_all,
-                bp->mac_filters.bcast_accept_all
+                bp->mac_filters.bcast_accept_all,
+                bp->mac_filters.unmatched_unicast
         );
 
         storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
@@ -4232,6 +4354,15 @@ static void bnx2x_init_internal_common(struct bnx2x *bp)
                         bp->mf_mode);
         }
 
+        if (IS_MF_SI(bp))
+                /*
+                 * In switch independent mode, the TSTORM needs to accept
+                 * packets that failed classification, since approximate match
+                 * mac addresses aren't written to NIG LLH
+                 */
+                REG_WR8(bp, BAR_TSTRORM_INTMEM +
+                            TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
+
         /* Zero this manually as its initialization is
            currently missing in the initTool */
         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
@@ -4247,6 +4378,7 @@ static void bnx2x_init_internal_common(struct bnx2x *bp)
 static void bnx2x_init_internal_port(struct bnx2x *bp)
 {
         /* port */
+        bnx2x_dcb_init_intmem_pfc(bp);
 }
 
 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
@@ -4308,9 +4440,11 @@ void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
 {
         int i;
 
-        for_each_queue(bp, i)
+        for_each_eth_queue(bp, i)
                 bnx2x_init_fp_sb(bp, i);
 #ifdef BCM_CNIC
+        if (!NO_FCOE(bp))
+                bnx2x_init_fcoe_fp(bp);
 
         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
                       BNX2X_VF_ID_INVALID, false,
@@ -4619,7 +4753,7 @@ static int bnx2x_int_mem_test(struct bnx2x *bp)
         return 0; /* OK */
 }
 
-static void enable_blocks_attention(struct bnx2x *bp)
+static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
 {
         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
         if (CHIP_IS_E2(bp))
@@ -4673,53 +4807,9 @@ static void enable_blocks_attention(struct bnx2x *bp)
         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
-        REG_WR(bp, PBF_REG_PBF_INT_MASK, 0X18);         /* bit 3,4 masked */
-}
-
-static const struct {
-        u32 addr;
-        u32 mask;
-} bnx2x_parity_mask[] = {
-        {PXP_REG_PXP_PRTY_MASK,         0x3ffffff},
-        {PXP2_REG_PXP2_PRTY_MASK_0,     0xffffffff},
-        {PXP2_REG_PXP2_PRTY_MASK_1,     0x7f},
-        {HC_REG_HC_PRTY_MASK,           0x7},
-        {MISC_REG_MISC_PRTY_MASK,       0x1},
-        {QM_REG_QM_PRTY_MASK,           0x0},
-        {DORQ_REG_DORQ_PRTY_MASK,       0x0},
-        {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 0x0},
-        {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 0x0},
-        {SRC_REG_SRC_PRTY_MASK,         0x4}, /* bit 2 */
-        {CDU_REG_CDU_PRTY_MASK,         0x0},
-        {CFC_REG_CFC_PRTY_MASK,         0x0},
-        {DBG_REG_DBG_PRTY_MASK,         0x0},
-        {DMAE_REG_DMAE_PRTY_MASK,       0x0},
-        {BRB1_REG_BRB1_PRTY_MASK,       0x0},
-        {PRS_REG_PRS_PRTY_MASK,         (1<<6)},/* bit 6 */
-        {TSDM_REG_TSDM_PRTY_MASK,       0x18},  /* bit 3,4 */
-        {CSDM_REG_CSDM_PRTY_MASK,       0x8},   /* bit 3 */
-        {USDM_REG_USDM_PRTY_MASK,       0x38},  /* bit 3,4,5 */
-        {XSDM_REG_XSDM_PRTY_MASK,       0x8},   /* bit 3 */
-        {TSEM_REG_TSEM_PRTY_MASK_0,     0x0},
-        {TSEM_REG_TSEM_PRTY_MASK_1,     0x0},
-        {USEM_REG_USEM_PRTY_MASK_0,     0x0},
-        {USEM_REG_USEM_PRTY_MASK_1,     0x0},
-        {CSEM_REG_CSEM_PRTY_MASK_0,     0x0},
-        {CSEM_REG_CSEM_PRTY_MASK_1,     0x0},
-        {XSEM_REG_XSEM_PRTY_MASK_0,     0x0},
-        {XSEM_REG_XSEM_PRTY_MASK_1,     0x0}
-};
-
-static void enable_blocks_parity(struct bnx2x *bp)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(bnx2x_parity_mask); i++)
-                REG_WR(bp, bnx2x_parity_mask[i].addr,
-                        bnx2x_parity_mask[i].mask);
+        REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
 }
 
-
 static void bnx2x_reset_common(struct bnx2x *bp)
 {
         /* reset_common */
@@ -5048,12 +5138,12 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
         REG_WR(bp, PRS_REG_NIC_MODE, 1);
 #endif
         if (!CHIP_IS_E1(bp))
-                REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF(bp));
+                REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
 
         if (CHIP_IS_E2(bp)) {
                 /* Bit-map indicating which L2 hdrs may appear after the
                    basic Ethernet header */
-                int has_ovlan = IS_MF(bp);
+                int has_ovlan = IS_MF_SD(bp);
                 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
                 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
         }
@@ -5087,7 +5177,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
         bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
 
         if (CHIP_IS_E2(bp)) {
-                int has_ovlan = IS_MF(bp);
+                int has_ovlan = IS_MF_SD(bp);
                 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
                 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
         }
@@ -5164,12 +5254,12 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
         bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
         if (!CHIP_IS_E1(bp)) {
                 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
-                REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF(bp));
+                REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
         }
         if (CHIP_IS_E2(bp)) {
                 /* Bit-map indicating which L2 hdrs may appear after the
                    basic Ethernet header */
-                REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF(bp) ? 7 : 6));
+                REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
         }
 
         if (CHIP_REV_IS_SLOW(bp))
@@ -5215,9 +5305,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
         /* clear PXP2 attentions */
         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
 
-        enable_blocks_attention(bp);
-        if (CHIP_PARITY_SUPPORTED(bp))
-                enable_blocks_parity(bp);
+        bnx2x_enable_blocks_attention(bp);
+        if (CHIP_PARITY_ENABLED(bp))
+                bnx2x_enable_blocks_parity(bp);
 
         if (!BP_NOMCP(bp)) {
                 /* In E2 2-PORT mode, same ext phy is used for the two paths */
@@ -5370,8 +5460,10 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
          *  - SF mode: bits 3-7 are masked. only bits 0-2 are in use
          *  - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
          *             bits 4-7 are used for "per vn group attention" */
-        REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
-               (IS_MF(bp) ? 0xF7 : 0x7));
+        val = IS_MF(bp) ? 0xF7 : 0x7;
+        /* Enable DCBX attention for all but E1 */
+        val |= CHIP_IS_E1(bp) ? 0 : 0x10;
+        REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
 
         bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
         bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
@@ -5386,7 +5478,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
         if (!CHIP_IS_E1(bp)) {
                 /* 0x2 disable mf_ov, 0x1 enable */
                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
-                       (IS_MF(bp) ? 0x1 : 0x2));
+                       (IS_MF_SD(bp) ? 0x1 : 0x2));
 
                 if (CHIP_IS_E2(bp)) {
                         val = 0;
@@ -5816,6 +5908,15 @@ void bnx2x_free_mem(struct bnx2x *bp)
         /* fastpath */
         /* Common */
         for_each_queue(bp, i) {
+#ifdef BCM_CNIC
+                /* FCoE client uses default status block */
+                if (IS_FCOE_IDX(i)) {
+                        union host_hc_status_block *sb =
+                                &bnx2x_fp(bp, i, status_blk);
+                        memset(sb, 0, sizeof(union host_hc_status_block));
+                        bnx2x_fp(bp, i, status_blk_mapping) = 0;
+                } else {
+#endif
                 /* status blocks */
                 if (CHIP_IS_E2(bp))
                         BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e2_sb),
@@ -5825,9 +5926,12 @@ void bnx2x_free_mem(struct bnx2x *bp)
                         BNX2X_PCI_FREE(bnx2x_fp(bp, i, status_blk.e1x_sb),
                                        bnx2x_fp(bp, i, status_blk_mapping),
                                        sizeof(struct host_hc_status_block_e1x));
+#ifdef BCM_CNIC
+                }
+#endif
         }
         /* Rx */
-        for_each_queue(bp, i) {
+        for_each_rx_queue(bp, i) {
 
                 /* fastpath rx rings: rx_buf rx_desc rx_comp */
                 BNX2X_FREE(bnx2x_fp(bp, i, rx_buf_ring));
@@ -5847,7 +5951,7 @@ void bnx2x_free_mem(struct bnx2x *bp)
                                BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
         }
         /* Tx */
-        for_each_queue(bp, i) {
+        for_each_tx_queue(bp, i) {
 
                 /* fastpath tx rings: tx_buf tx_desc */
                 BNX2X_FREE(bnx2x_fp(bp, i, tx_buf_ring));
@@ -5931,15 +6035,20 @@ int bnx2x_alloc_mem(struct bnx2x *bp)
                 union host_hc_status_block *sb = &bnx2x_fp(bp, i, status_blk);
                 bnx2x_fp(bp, i, bp) = bp;
                 /* status blocks */
-                if (CHIP_IS_E2(bp))
-                        BNX2X_PCI_ALLOC(sb->e2_sb,
-                                &bnx2x_fp(bp, i, status_blk_mapping),
-                                sizeof(struct host_hc_status_block_e2));
-                else
-                        BNX2X_PCI_ALLOC(sb->e1x_sb,
-                                &bnx2x_fp(bp, i, status_blk_mapping),
-                                sizeof(struct host_hc_status_block_e1x));
-
+#ifdef BCM_CNIC
+                if (!IS_FCOE_IDX(i)) {
+#endif
+                        if (CHIP_IS_E2(bp))
+                                BNX2X_PCI_ALLOC(sb->e2_sb,
+                                    &bnx2x_fp(bp, i, status_blk_mapping),
+                                    sizeof(struct host_hc_status_block_e2));
+                        else
+                                BNX2X_PCI_ALLOC(sb->e1x_sb,
+                                    &bnx2x_fp(bp, i, status_blk_mapping),
+                                    sizeof(struct host_hc_status_block_e1x));
+#ifdef BCM_CNIC
+                }
+#endif
                 set_sb_shortcuts(bp, i);
         }
         /* Rx */
@@ -6055,7 +6164,7 @@ static int bnx2x_func_stop(struct bnx2x *bp)
  * @param cam_offset offset in a CAM to use
  * @param is_bcast is the set MAC a broadcast address (for E1 only)
  */
-static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, u8 *mac,
+static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
                                    u32 cl_bit_vec, u8 cam_offset,
                                    u8 is_bcast)
 {
@@ -6170,6 +6279,70 @@ static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
                 return BP_VN(bp) * 32  + rel_offset;
 }
 
+/**
+ *  LLH CAM line allocations: currently only iSCSI and ETH macs are
+ *  relevant. In addition, current implementation is tuned for a
+ *  single ETH MAC.
+ *
+ *  When multiple unicast ETH MACs PF configuration in switch
+ *  independent mode is required (NetQ, multiple netdev MACs,
+ *  etc.), consider better utilisation of 16 per function MAC
+ *  entries in the LLH memory.
+ */
+enum {
+        LLH_CAM_ISCSI_ETH_LINE = 0,
+        LLH_CAM_ETH_LINE,
+        LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
+};
+
+static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
+                          int set,
+                          unsigned char *dev_addr,
+                          int index)
+{
+        u32 wb_data[2];
+        u32 mem_offset, ena_offset, mem_index;
+        /**
+         * indexes mapping:
+         * 0..7 - goes to MEM
+         * 8..15 - goes to MEM2
+         */
+
+        if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
+                return;
+
+        /* calculate memory start offset according to the mapping
+         * and index in the memory */
+        if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
+                mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
+                                           NIG_REG_LLH0_FUNC_MEM;
+                ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
+                                           NIG_REG_LLH0_FUNC_MEM_ENABLE;
+                mem_index = index;
+        } else {
+                mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
+                                           NIG_REG_P0_LLH_FUNC_MEM2;
+                ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
+                                           NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
+                mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
+        }
+
+        if (set) {
+                /* LLH_FUNC_MEM is a u64 WB register */
+                mem_offset += 8*mem_index;
+
+                wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
+                              (dev_addr[4] <<  8) |  dev_addr[5]);
+                wb_data[1] = ((dev_addr[0] <<  8) |  dev_addr[1]);
+
+                REG_WR_DMAE(bp, mem_offset, wb_data, 2);
+        }
+
+        /* enable/disable the entry */
+        REG_WR(bp, ena_offset + 4*mem_index, set);
+
+}
+
 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
 {
         u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
@@ -6179,9 +6352,13 @@ void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
         bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
                                (1 << bp->fp->cl_id), cam_offset , 0);
 
+        bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
+
         if (CHIP_IS_E1(bp)) {
                 /* broadcast MAC */
-                u8 bcast[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+                static const u8 bcast[ETH_ALEN] = {
+                        0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+                };
                 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
         }
 }
@@ -6283,12 +6460,59 @@ static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
 {
         u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
                          bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
-        u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID;
+        u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
+                BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
         u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
 
         /* Send a SET_MAC ramrod */
         bnx2x_set_mac_addr_gen(bp, set, bp->iscsi_mac, cl_bit_vec,
                                cam_offset, 0);
+
+        bnx2x_set_mac_in_nig(bp, set, bp->iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
+
+        return 0;
+}
+
+/**
+ * Set FCoE L2 MAC(s) at the next enties in the CAM after the
+ * ETH MAC(s). This function will wait until the ramdord
+ * completion returns.
+ *
+ * @param bp driver handle
+ * @param set set or clear the CAM entry
+ *
+ * @return 0 if cussess, -ENODEV if ramrod doesn't return.
+ */
+int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
+{
+        u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
+        /**
+         * CAM allocation for E1H
+         * eth unicasts: by func number
+         * iscsi: by func number
+         * fip unicast: by func number
+         * fip multicast: by func number
+         */
+        bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
+                cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
+
+        return 0;
+}
+
+int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
+{
+        u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
+
+        /**
+         * CAM allocation for E1H
+         * eth unicasts: by func number
+         * iscsi: by func number
+         * fip unicast: by func number
+         * fip multicast: by func number
+         */
+        bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
+                bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
+
         return 0;
 }
 #endif
@@ -6306,6 +6530,8 @@ static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
         data->general.statistics_counter_id = params->rxq_params.stat_id;
         data->general.statistics_en_flg =
                 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
+        data->general.is_fcoe_flg =
+                (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
         data->general.activate_flg = activate;
         data->general.sp_client_id = params->rxq_params.spcl_id;
 
@@ -6374,7 +6600,9 @@ static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
         data->fc.safc_group_num = params->txq_params.cos;
         data->fc.safc_group_en_flg =
                 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
-        data->fc.traffic_type = LLFC_TRAFFIC_TYPE_NW;
+        data->fc.traffic_type =
+                (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
+                LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
 }
 
 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
@@ -6473,7 +6701,7 @@ static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
                 bnx2x_enable_msi(bp);
                 /* falling through... */
         case INT_MODE_INTx:
-                bp->num_queues = 1;
+                bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
                 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
                 break;
         default:
@@ -6496,8 +6724,8 @@ static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
                                           "enable MSI-X (%d), "
                                           "set number of queues to %d\n",
                                    bp->num_queues,
-                                   1);
-                        bp->num_queues = 1;
+                                   1 + NONE_ETH_CONTEXT_USE);
+                        bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
 
                         if (!(bp->flags & DISABLE_MSI_FLAG))
                                 bnx2x_enable_msi(bp);
@@ -6618,7 +6846,9 @@ int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
         struct bnx2x_client_init_params params = { {0} };
         int rc;
 
-        bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
+        /* reset IGU state skip FCoE L2 queue */
+        if (!IS_FCOE_FP(fp))
+                bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
                              IGU_INT_ENABLE, 0);
 
         params.ramrod_params.pstate = &fp->state;
@@ -6626,6 +6856,12 @@ int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
         params.ramrod_params.index = fp->index;
         params.ramrod_params.cid = fp->cid;
 
+#ifdef BCM_CNIC
+        if (IS_FCOE_FP(fp))
+                params.ramrod_params.flags |= CLIENT_IS_FCOE;
+
+#endif
+
         if (is_leading)
                 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
 
@@ -6710,7 +6946,7 @@ static void bnx2x_reset_func(struct bnx2x *bp)
         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
 
         /* FP SBs */
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
                 REG_WR8(bp,
                         BAR_CSTRORM_INTMEM +
@@ -6830,6 +7066,20 @@ static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
         }
 }
 
+#ifdef BCM_CNIC
+static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
+{
+        if (bp->flags & FCOE_MACS_SET) {
+                if (!IS_MF_SD(bp))
+                        bnx2x_set_fip_eth_mac_addr(bp, 0);
+
+                bnx2x_set_all_enode_macs(bp, 0);
+
+                bp->flags &= ~FCOE_MACS_SET;
+        }
+}
+#endif
+
 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
 {
         int port = BP_PORT(bp);
@@ -6837,7 +7087,7 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
         int i, cnt, rc;
 
         /* Wait until tx fastpath tasks complete */
-        for_each_queue(bp, i) {
+        for_each_tx_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
 
                 cnt = 1000;
@@ -6877,13 +7127,7 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
         }
 
 #ifdef BCM_CNIC
-        /* Clear iSCSI L2 MAC */
-        mutex_lock(&bp->cnic_mutex);
-        if (bp->cnic_flags & BNX2X_CNIC_FLAG_MAC_SET) {
-                bnx2x_set_iscsi_eth_mac_addr(bp, 0);
-                bp->cnic_flags &= ~BNX2X_CNIC_FLAG_MAC_SET;
-        }
-        mutex_unlock(&bp->cnic_mutex);
+        bnx2x_del_fcoe_eth_macs(bp);
 #endif
 
         if (unload_mode == UNLOAD_NORMAL)
@@ -7736,7 +7980,7 @@ static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
         bp->igu_sb_cnt = 0;
         if (CHIP_INT_MODE_IS_BC(bp)) {
                 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
-                                       bp->l2_cid_count);
+                                       NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
 
                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
                         FP_SB_MAX_E1x;
@@ -7767,7 +8011,8 @@ static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
                         }
                 }
         }
-        bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, bp->l2_cid_count);
+        bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
+                                   NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
         if (bp->igu_sb_cnt == 0)
                 BNX2X_ERR("CAM configuration error\n");
 }
@@ -8076,9 +8321,8 @@ static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
 {
         int port = BP_PORT(bp);
-        u32 val, val2;
         u32 config;
-        u32 ext_phy_type, ext_phy_config;;
+        u32 ext_phy_type, ext_phy_config;
 
         bp->link_params.bp = bp;
         bp->link_params.port = port;
@@ -8135,25 +8379,73 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
                 bp->mdio.prtad =
                         XGXS_EXT_PHY_ADDR(ext_phy_config);
+}
+
+static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
+{
+        u32 val, val2;
+        int func = BP_ABS_FUNC(bp);
+        int port = BP_PORT(bp);
+
+        if (BP_NOMCP(bp)) {
+                BNX2X_ERROR("warning: random MAC workaround active\n");
+                random_ether_addr(bp->dev->dev_addr);
+        } else if (IS_MF(bp)) {
+                val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
+                val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
+                if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
+                    (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
+                        bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
+
+#ifdef BCM_CNIC
+                /* iSCSI NPAR MAC */
+                if (IS_MF_SI(bp)) {
+                        u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
+                        if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
+                                val2 = MF_CFG_RD(bp, func_ext_config[func].
+                                                     iscsi_mac_addr_upper);
+                                val = MF_CFG_RD(bp, func_ext_config[func].
+                                                    iscsi_mac_addr_lower);
+                                bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
+                        }
+                }
+#endif
+        } else {
+                /* in SF read MACs from port configuration */
+                val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
+                val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
+                bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
+
+#ifdef BCM_CNIC
+                val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
+                                    iscsi_mac_upper);
+                val = SHMEM_RD(bp, dev_info.port_hw_config[port].
+                                   iscsi_mac_lower);
+                bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
+#endif
+        }
 
-        val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
-        val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
-        bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
         memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
 
 #ifdef BCM_CNIC
-        val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].iscsi_mac_upper);
-        val = SHMEM_RD(bp, dev_info.port_hw_config[port].iscsi_mac_lower);
-        bnx2x_set_mac_buf(bp->iscsi_mac, val, val2);
+        /* Inform the upper layers about FCoE MAC */
+        if (!CHIP_IS_E1x(bp)) {
+                if (IS_MF_SD(bp))
+                        memcpy(bp->fip_mac, bp->dev->dev_addr,
+                               sizeof(bp->fip_mac));
+                else
+                        memcpy(bp->fip_mac, bp->iscsi_mac,
+                               sizeof(bp->fip_mac));
+        }
 #endif
 }
 
 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
 {
-        int func = BP_ABS_FUNC(bp);
-        int vn;
-        u32 val, val2;
+        int /*abs*/func = BP_ABS_FUNC(bp);
+        int vn, port;
+        u32 val = 0;
         int rc = 0;
 
         bnx2x_get_common_hwinfo(bp);
@@ -8163,7 +8455,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
 
                 bp->igu_dsb_id = DEF_SB_IGU_ID;
                 bp->igu_base_sb = 0;
-                bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x, bp->l2_cid_count);
+                bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
+                                       NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
         } else {
                 bp->common.int_block = INT_BLOCK_IGU;
                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
@@ -8186,44 +8479,99 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
         bp->mf_ov = 0;
         bp->mf_mode = 0;
         vn = BP_E1HVN(bp);
+        port = BP_PORT(bp);
+
         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
+                DP(NETIF_MSG_PROBE,
+                            "shmem2base 0x%x, size %d, mfcfg offset %d\n",
+                            bp->common.shmem2_base, SHMEM2_RD(bp, size),
+                            (u32)offsetof(struct shmem2_region, mf_cfg_addr));
                 if (SHMEM2_HAS(bp, mf_cfg_addr))
                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
                 else
                         bp->common.mf_cfg_base = bp->common.shmem_base +
                                 offsetof(struct shmem_region, func_mb) +
                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
-                bp->mf_config[vn] =
-                        MF_CFG_RD(bp, func_mf_config[func].config);
+                /*
+                 * get mf configuration:
+                 * 1. existance of MF configuration
+                 * 2. MAC address must be legal (check only upper bytes)
+                 *    for  Switch-Independent mode;
+                 *    OVLAN must be legal for Switch-Dependent mode
+                 * 3. SF_MODE configures specific MF mode
+                 */
+                if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
+                        /* get mf configuration */
+                        val = SHMEM_RD(bp,
+                                       dev_info.shared_feature_config.config);
+                        val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
+
+                        switch (val) {
+                        case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
+                                val = MF_CFG_RD(bp, func_mf_config[func].
+                                                mac_upper);
+                                /* check for legal mac (upper bytes)*/
+                                if (val != 0xffff) {
+                                        bp->mf_mode = MULTI_FUNCTION_SI;
+                                        bp->mf_config[vn] = MF_CFG_RD(bp,
+                                                   func_mf_config[func].config);
+                                } else
+                                        DP(NETIF_MSG_PROBE, "illegal MAC "
+                                                            "address for SI\n");
+                                break;
+                        case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
+                                /* get OV configuration */
+                                val = MF_CFG_RD(bp,
+                                        func_mf_config[FUNC_0].e1hov_tag);
+                                val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
+
+                                if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
+                                        bp->mf_mode = MULTI_FUNCTION_SD;
+                                        bp->mf_config[vn] = MF_CFG_RD(bp,
+                                                func_mf_config[func].config);
+                                } else
+                                        DP(NETIF_MSG_PROBE, "illegal OV for "
+                                                            "SD\n");
+                                break;
+                        default:
+                                /* Unknown configuration: reset mf_config */
+                                bp->mf_config[vn] = 0;
+                                DP(NETIF_MSG_PROBE, "Unkown MF mode 0x%x\n",
+                                   val);
+                        }
+                }
 
-                val = (MF_CFG_RD(bp, func_mf_config[FUNC_0].e1hov_tag) &
-                       FUNC_MF_CFG_E1HOV_TAG_MASK);
-                if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
-                        bp->mf_mode = 1;
                 BNX2X_DEV_INFO("%s function mode\n",
                                IS_MF(bp) ? "multi" : "single");
 
-                if (IS_MF(bp)) {
-                        val = (MF_CFG_RD(bp, func_mf_config[func].
-                                                                e1hov_tag) &
-                               FUNC_MF_CFG_E1HOV_TAG_MASK);
+                switch (bp->mf_mode) {
+                case MULTI_FUNCTION_SD:
+                        val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
+                              FUNC_MF_CFG_E1HOV_TAG_MASK;
                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
                                 bp->mf_ov = val;
-                                BNX2X_DEV_INFO("MF OV for func %d is %d "
-                                               "(0x%04x)\n",
-                                               func, bp->mf_ov, bp->mf_ov);
+                                BNX2X_DEV_INFO("MF OV for func %d is %d"
+                                               " (0x%04x)\n", func,
+                                               bp->mf_ov, bp->mf_ov);
                         } else {
-                                BNX2X_ERROR("No valid MF OV for func %d,"
-                                            "  aborting\n", func);
+                                BNX2X_ERR("No valid MF OV for func %d,"
+                                          "  aborting\n", func);
                                 rc = -EPERM;
                         }
-                } else {
-                        if (BP_VN(bp)) {
-                                BNX2X_ERROR("VN %d in single function mode,"
-                                            "  aborting\n", BP_E1HVN(bp));
+                        break;
+                case MULTI_FUNCTION_SI:
+                        BNX2X_DEV_INFO("func %d is in MF "
+                                       "switch-independent mode\n", func);
+                        break;
+                default:
+                        if (vn) {
+                                BNX2X_ERR("VN %d in single function mode,"
+                                          "  aborting\n", vn);
                                 rc = -EPERM;
                         }
+                        break;
                 }
+
         }
 
         /* adjust igu_sb_cnt to MF for E1x */
@@ -8248,32 +8596,8 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
         }
 
-        if (IS_MF(bp)) {
-                val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
-                val = MF_CFG_RD(bp,  func_mf_config[func].mac_lower);
-                if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
-                    (val != FUNC_MF_CFG_LOWERMAC_DEFAULT)) {
-                        bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
-                        bp->dev->dev_addr[1] = (u8)(val2 & 0xff);
-                        bp->dev->dev_addr[2] = (u8)(val >> 24 & 0xff);
-                        bp->dev->dev_addr[3] = (u8)(val >> 16 & 0xff);
-                        bp->dev->dev_addr[4] = (u8)(val >> 8  & 0xff);
-                        bp->dev->dev_addr[5] = (u8)(val & 0xff);
-                        memcpy(bp->link_params.mac_addr, bp->dev->dev_addr,
-                               ETH_ALEN);
-                        memcpy(bp->dev->perm_addr, bp->dev->dev_addr,
-                               ETH_ALEN);
-                }
-
-                return rc;
-        }
-
-        if (BP_NOMCP(bp)) {
-                /* only supposed to happen on emulation/FPGA */
-                BNX2X_ERROR("warning: random MAC workaround active\n");
-                random_ether_addr(bp->dev->dev_addr);
-                memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
-        }
+        /* Get MAC addresses */
+        bnx2x_get_mac_hwinfo(bp);
 
         return rc;
 }
@@ -8382,13 +8706,6 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
                 dev_err(&bp->pdev->dev, "MCP disabled, "
                                         "must load devices in order!\n");
 
-        /* Set multi queue mode */
-        if ((multi_mode != ETH_RSS_MODE_DISABLED) &&
-            ((int_mode == INT_MODE_INTx) || (int_mode == INT_MODE_MSI))) {
-                dev_err(&bp->pdev->dev, "Multi disabled since int_mode "
-                                        "requested is not MSI-X\n");
-                multi_mode = ETH_RSS_MODE_DISABLED;
-        }
         bp->multi_mode = multi_mode;
         bp->int_mode = int_mode;
 
@@ -8427,6 +8744,9 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
         bp->timer.data = (unsigned long) bp;
         bp->timer.function = bnx2x_timer;
 
+        bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
+        bnx2x_dcbx_init_params(bp);
+
         return rc;
 }
 
@@ -8629,6 +8949,7 @@ static const struct net_device_ops bnx2x_netdev_ops = {
         .ndo_open               = bnx2x_open,
         .ndo_stop               = bnx2x_close,
         .ndo_start_xmit         = bnx2x_start_xmit,
+        .ndo_select_queue       = bnx2x_select_queue,
         .ndo_set_multicast_list = bnx2x_set_rx_mode,
         .ndo_set_mac_address    = bnx2x_change_mac_addr,
         .ndo_validate_addr      = eth_validate_addr,
@@ -8761,7 +9082,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
         dev->netdev_ops = &bnx2x_netdev_ops;
         bnx2x_set_ethtool_ops(dev);
         dev->features |= NETIF_F_SG;
-        dev->features |= NETIF_F_HW_CSUM;
+        dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
         if (bp->flags & USING_DAC_FLAG)
                 dev->features |= NETIF_F_HIGHDMA;
         dev->features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
@@ -8769,12 +9090,16 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
         dev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
 
         dev->vlan_features |= NETIF_F_SG;
-        dev->vlan_features |= NETIF_F_HW_CSUM;
+        dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
         if (bp->flags & USING_DAC_FLAG)
                 dev->vlan_features |= NETIF_F_HIGHDMA;
         dev->vlan_features |= (NETIF_F_TSO | NETIF_F_TSO_ECN);
         dev->vlan_features |= NETIF_F_TSO6;
 
+#ifdef BCM_DCB
+        dev->dcbnl_ops = &bnx2x_dcbnl_ops;
+#endif
+
         /* get_port_hwinfo() will set prtad and mmds properly */
         bp->mdio.prtad = MDIO_PRTAD_NONE;
         bp->mdio.mmds = 0;
@@ -9067,7 +9392,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
                 return -ENODEV;
         }
 
-        cid_count += CNIC_CONTEXT_USE;
+        cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
 
         /* dev zeroed in init_etherdev */
         dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
@@ -9096,11 +9421,12 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
         /* calc qm_cid_count */
         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
 
-        rc = register_netdev(dev);
-        if (rc) {
-                dev_err(&pdev->dev, "Cannot register net device\n");
-                goto init_one_exit;
-        }
+#ifdef BCM_CNIC
+        /* disable FCOE L2 queue for E1x*/
+        if (CHIP_IS_E1x(bp))
+                bp->flags |= NO_FCOE_FLAG;
+
+#endif
 
         /* Configure interupt mode: try to enable MSI-X/MSI if
          * needed, set bp->num_queues appropriately.
@@ -9110,6 +9436,21 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
         /* Add all NAPI objects */
         bnx2x_add_all_napi(bp);
 
+        rc = register_netdev(dev);
+        if (rc) {
+                dev_err(&pdev->dev, "Cannot register net device\n");
+                goto init_one_exit;
+        }
+
+#ifdef BCM_CNIC
+        if (!NO_FCOE(bp)) {
+                /* Add storage MAC address */
+                rtnl_lock();
+                dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
+                rtnl_unlock();
+        }
+#endif
+
         bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
 
         netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
@@ -9153,14 +9494,29 @@ static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
         }
         bp = netdev_priv(dev);
 
+#ifdef BCM_CNIC
+        /* Delete storage MAC address */
+        if (!NO_FCOE(bp)) {
+                rtnl_lock();
+                dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
+                rtnl_unlock();
+        }
+#endif
+
         unregister_netdev(dev);
 
         /* Delete all NAPI objects */
         bnx2x_del_all_napi(bp);
 
+        /* Power on: we can't let PCI layer write to us while we are in D3 */
+        bnx2x_set_power_state(bp, PCI_D0);
+
         /* Disable MSI/MSI-X */
         bnx2x_disable_msi(bp);
 
+        /* Power off */
+        bnx2x_set_power_state(bp, PCI_D3hot);
+
         /* Make sure RESET task is not scheduled before continuing */
         cancel_delayed_work_sync(&bp->reset_task);
 
@@ -9202,7 +9558,7 @@ static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
         /* Free SKBs, SGEs, TPA pool and driver internals */
         bnx2x_free_skbs(bp);
 
-        for_each_queue(bp, i)
+        for_each_rx_queue(bp, i)
                 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
 
         bnx2x_free_mem(bp);
@@ -9429,7 +9785,8 @@ static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
                                 break;
                         else
                                 atomic_dec(&bp->spq_left);
-                } else if (type == ISCSI_CONNECTION_TYPE) {
+                } else if ((type == ISCSI_CONNECTION_TYPE) ||
+                           (type == FCOE_CONNECTION_TYPE)) {
                         if (bp->cnic_spq_pending >=
                             bp->cnic_eth_dev.max_kwqe_pending)
                                 break;
@@ -9576,6 +9933,9 @@ static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
         case DRV_CTL_START_L2_CMD: {
                 u32 cli = ctl->data.ring.client_id;
 
+                /* Clear FCoE FIP and ALL ENODE MACs addresses first */
+                bnx2x_del_fcoe_eth_macs(bp);
+
                 /* Set iSCSI MAC address */
                 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
 
@@ -9697,10 +10057,6 @@ static int bnx2x_unregister_cnic(struct net_device *dev)
         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 
         mutex_lock(&bp->cnic_mutex);
-        if (bp->cnic_flags & BNX2X_CNIC_FLAG_MAC_SET) {
-                bp->cnic_flags &= ~BNX2X_CNIC_FLAG_MAC_SET;
-                bnx2x_set_iscsi_eth_mac_addr(bp, 0);
-        }
         cp->drv_state = 0;
         rcu_assign_pointer(bp->cnic_ops, NULL);
         mutex_unlock(&bp->cnic_mutex);
@@ -9731,7 +10087,9 @@ struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
         cp->drv_ctl = bnx2x_drv_ctl;
         cp->drv_register_cnic = bnx2x_register_cnic;
         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
-        cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID;
+        cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
+        cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
+                BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
 
         DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h
index 245220af9feb..c939683e3d61 100644
--- a/drivers/net/bnx2x/bnx2x_reg.h
+++ b/drivers/net/bnx2x/bnx2x_reg.h
@@ -18,6 +18,8 @@
  * WR - Write Clear (write 1 to clear the bit)
  *
  */
+#ifndef BNX2X_REG_H
+#define BNX2X_REG_H
 
 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR                        (0x1<<0)
 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS                (0x1<<2)
@@ -39,6 +41,8 @@
 #define BRB1_REG_BRB1_PRTY_MASK                                  0x60138
 /* [R 4] Parity register #0 read */
 #define BRB1_REG_BRB1_PRTY_STS                                   0x6012c
+/* [RC 4] Parity register #0 read clear */
+#define BRB1_REG_BRB1_PRTY_STS_CLR                               0x60130
 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
  * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
  * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
@@ -132,8 +136,12 @@
 #define CCM_REG_CCM_INT_MASK                                     0xd01e4
 /* [R 11] Interrupt register #0 read */
 #define CCM_REG_CCM_INT_STS                                      0xd01d8
+/* [RW 27] Parity mask register #0 read/write */
+#define CCM_REG_CCM_PRTY_MASK                                    0xd01f4
 /* [R 27] Parity register #0 read */
 #define CCM_REG_CCM_PRTY_STS                                     0xd01e8
+/* [RC 27] Parity register #0 read clear */
+#define CCM_REG_CCM_PRTY_STS_CLR                                 0xd01ec
 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -350,6 +358,8 @@
 #define CDU_REG_CDU_PRTY_MASK                                    0x10104c
 /* [R 5] Parity register #0 read */
 #define CDU_REG_CDU_PRTY_STS                                     0x101040
+/* [RC 5] Parity register #0 read clear */
+#define CDU_REG_CDU_PRTY_STS_CLR                                 0x101044
 /* [RC 32] logging of error data in case of a CDU load error:
    {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
    ype_error; ctual_active; ctual_compressed_context}; */
@@ -381,6 +391,8 @@
 #define CFC_REG_CFC_PRTY_MASK                                    0x104118
 /* [R 4] Parity register #0 read */
 #define CFC_REG_CFC_PRTY_STS                                     0x10410c
+/* [RC 4] Parity register #0 read clear */
+#define CFC_REG_CFC_PRTY_STS_CLR                                 0x104110
 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
 #define CFC_REG_CID_CAM                                          0x104800
 #define CFC_REG_CONTROL0                                         0x104028
@@ -466,6 +478,8 @@
 #define CSDM_REG_CSDM_PRTY_MASK                                  0xc22bc
 /* [R 11] Parity register #0 read */
 #define CSDM_REG_CSDM_PRTY_STS                                   0xc22b0
+/* [RC 11] Parity register #0 read clear */
+#define CSDM_REG_CSDM_PRTY_STS_CLR                               0xc22b4
 #define CSDM_REG_ENABLE_IN1                                      0xc2238
 #define CSDM_REG_ENABLE_IN2                                      0xc223c
 #define CSDM_REG_ENABLE_OUT1                                     0xc2240
@@ -556,6 +570,9 @@
 /* [R 32] Parity register #0 read */
 #define CSEM_REG_CSEM_PRTY_STS_0                                 0x200124
 #define CSEM_REG_CSEM_PRTY_STS_1                                 0x200134
+/* [RC 32] Parity register #0 read clear */
+#define CSEM_REG_CSEM_PRTY_STS_CLR_0                             0x200128
+#define CSEM_REG_CSEM_PRTY_STS_CLR_1                             0x200138
 #define CSEM_REG_ENABLE_IN                                       0x2000a4
 #define CSEM_REG_ENABLE_OUT                                      0x2000a8
 /* [RW 32] This address space contains all registers and memories that are
@@ -648,6 +665,8 @@
 #define DBG_REG_DBG_PRTY_MASK                                    0xc0a8
 /* [R 1] Parity register #0 read */
 #define DBG_REG_DBG_PRTY_STS                                     0xc09c
+/* [RC 1] Parity register #0 read clear */
+#define DBG_REG_DBG_PRTY_STS_CLR                                 0xc0a0
 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
  * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
  * 4.Completion function=0; 5.Error handling=0 */
@@ -668,6 +687,8 @@
 #define DMAE_REG_DMAE_PRTY_MASK                                  0x102064
 /* [R 4] Parity register #0 read */
 #define DMAE_REG_DMAE_PRTY_STS                                   0x102058
+/* [RC 4] Parity register #0 read clear */
+#define DMAE_REG_DMAE_PRTY_STS_CLR                               0x10205c
 /* [RW 1] Command 0 go. */
 #define DMAE_REG_GO_C0                                           0x102080
 /* [RW 1] Command 1 go. */
@@ -734,6 +755,8 @@
 #define DORQ_REG_DORQ_PRTY_MASK                                  0x170190
 /* [R 2] Parity register #0 read */
 #define DORQ_REG_DORQ_PRTY_STS                                   0x170184
+/* [RC 2] Parity register #0 read clear */
+#define DORQ_REG_DORQ_PRTY_STS_CLR                               0x170188
 /* [RW 8] The address to write the DPM CID to STORM. */
 #define DORQ_REG_DPM_CID_ADDR                                    0x170044
 /* [RW 5] The DPM mode CID extraction offset. */
@@ -842,8 +865,12 @@
 /* [R 1] data availble for error memory. If this bit is clear do not red
  * from error_handling_memory. */
 #define IGU_REG_ERROR_HANDLING_DATA_VALID                        0x130130
+/* [RW 11] Parity mask register #0 read/write */
+#define IGU_REG_IGU_PRTY_MASK                                    0x1300a8
 /* [R 11] Parity register #0 read */
 #define IGU_REG_IGU_PRTY_STS                                     0x13009c
+/* [RC 11] Parity register #0 read clear */
+#define IGU_REG_IGU_PRTY_STS_CLR                                 0x1300a0
 /* [R 4] Debug: int_handle_fsm */
 #define IGU_REG_INT_HANDLE_FSM                                   0x130050
 #define IGU_REG_LEADING_EDGE_LATCH                               0x130134
@@ -1501,6 +1528,8 @@
 #define MISC_REG_MISC_PRTY_MASK                                  0xa398
 /* [R 1] Parity register #0 read */
 #define MISC_REG_MISC_PRTY_STS                                   0xa38c
+/* [RC 1] Parity register #0 read clear */
+#define MISC_REG_MISC_PRTY_STS_CLR                               0xa390
 #define MISC_REG_NIG_WOL_P0                                      0xa270
 #define MISC_REG_NIG_WOL_P1                                      0xa274
 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst
@@ -1615,6 +1644,8 @@
 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN    (0x1<<4)
 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST      (0x1<<2)
 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN       (0x1<<3)
+#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN                  (0x1<<0)
+#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN                  (0x1<<0)
 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT      (0x1<<0)
 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS    (0x1<<9)
 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G          (0x1<<15)
@@ -1744,12 +1775,16 @@
    ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
    port */
 #define NIG_REG_LLFC_ENABLE_0                                    0x16208
+#define NIG_REG_LLFC_ENABLE_1                                    0x1620c
 /* [RW 16] classes are high-priority for port0 */
 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0                     0x16058
+#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1                     0x1605c
 /* [RW 16] classes are low-priority for port0 */
 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0                      0x16060
+#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1                      0x16064
 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
 #define NIG_REG_LLFC_OUT_EN_0                                    0x160c8
+#define NIG_REG_LLFC_OUT_EN_1                                    0x160cc
 #define NIG_REG_LLH0_ACPI_PAT_0_CRC                              0x1015c
 #define NIG_REG_LLH0_ACPI_PAT_6_LEN                              0x10154
 #define NIG_REG_LLH0_BRB1_DRV_MASK                               0x10244
@@ -1774,6 +1809,8 @@
 /* [RW 8] event id for llh0 */
 #define NIG_REG_LLH0_EVENT_ID                                    0x10084
 #define NIG_REG_LLH0_FUNC_EN                                     0x160fc
+#define NIG_REG_LLH0_FUNC_MEM                                    0x16180
+#define NIG_REG_LLH0_FUNC_MEM_ENABLE                             0x16140
 #define NIG_REG_LLH0_FUNC_VLAN_ID                                0x16100
 /* [RW 1] Determine the IP version to look for in
    ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
@@ -1797,6 +1834,9 @@
 #define NIG_REG_LLH1_ERROR_MASK                                  0x10090
 /* [RW 8] event id for llh1 */
 #define NIG_REG_LLH1_EVENT_ID                                    0x10088
+#define NIG_REG_LLH1_FUNC_MEM                                    0x161c0
+#define NIG_REG_LLH1_FUNC_MEM_ENABLE                             0x16160
+#define NIG_REG_LLH1_FUNC_MEM_SIZE                               16
 /* [RW 8] init credit counter for port1 in LLH */
 #define NIG_REG_LLH1_XCM_INIT_CREDIT                             0x10564
 #define NIG_REG_LLH1_XCM_MASK                                    0x10134
@@ -1907,11 +1947,17 @@
    ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
    port */
 #define NIG_REG_PAUSE_ENABLE_0                                   0x160c0
+#define NIG_REG_PAUSE_ENABLE_1                                   0x160c4
 /* [RW 1] Input enable for RX PBF LP IF */
 #define NIG_REG_PBF_LB_IN_EN                                     0x100b4
 /* [RW 1] Value of this register will be transmitted to port swap when
    ~nig_registers_strap_override.strap_override =1 */
 #define NIG_REG_PORT_SWAP                                        0x10394
+/* [RW 1] PPP enable for port0. This register may get 1 only when
+ * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
+ * same port */
+#define NIG_REG_PPP_ENABLE_0                                     0x160b0
+#define NIG_REG_PPP_ENABLE_1                                     0x160b4
 /* [RW 1] output enable for RX parser descriptor IF */
 #define NIG_REG_PRS_EOP_OUT_EN                                   0x10104
 /* [RW 1] Input enable for RX parser request IF */
@@ -1978,6 +2024,14 @@
 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G      (0x1<<15)
 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS  (0xf<<18)
 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
+/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
+#define PBF_REG_COS0_UPPER_BOUND                                 0x15c05c
+/* [RW 31] The weight of COS0 in the ETS command arbiter. */
+#define PBF_REG_COS0_WEIGHT                                      0x15c054
+/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
+#define PBF_REG_COS1_UPPER_BOUND                                 0x15c060
+/* [RW 31] The weight of COS1 in the ETS command arbiter. */
+#define PBF_REG_COS1_WEIGHT                                      0x15c058
 /* [RW 1] Disable processing further tasks from port 0 (after ending the
    current task in process). */
 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0                         0x14005c
@@ -1988,9 +2042,16 @@
    current task in process). */
 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4                         0x14006c
 #define PBF_REG_DISABLE_PF                                       0x1402e8
+/* [RW 1] Indicates that ETS is performed between the COSes in the command
+ * arbiter. If reset strict priority w/ anti-starvation will be performed
+ * w/o WFQ. */
+#define PBF_REG_ETS_ENABLED                                      0x15c050
 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
  * Ethernet header. */
 #define PBF_REG_HDRS_AFTER_BASIC                                 0x15c0a8
+/* [RW 1] Indicates which COS is conncted to the highest priority in the
+ * command arbiter. */
+#define PBF_REG_HIGH_PRIORITY_COS_NUM                            0x15c04c
 #define PBF_REG_IF_ENABLE_REG                                    0x140044
 /* [RW 1] Init bit. When set the initial credits are copied to the credit
    registers (except the port credits). Should be set and then reset after
@@ -2016,6 +2077,10 @@
 #define PBF_REG_MAC_LB_ENABLE                                    0x140040
 /* [RW 6] Bit-map indicating which headers must appear in the packet */
 #define PBF_REG_MUST_HAVE_HDRS                                   0x15c0c4
+/* [RW 16] The number of strict priority arbitration slots between 2 RR
+ * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
+ * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
+#define PBF_REG_NUM_STRICT_ARB_SLOTS                             0x15c064
 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
    not suppoterd. */
 #define PBF_REG_P0_ARB_THRSH                                     0x1400e4
@@ -2046,6 +2111,10 @@
 #define PBF_REG_PBF_INT_MASK                                     0x1401d4
 /* [R 5] Interrupt register #0 read */
 #define PBF_REG_PBF_INT_STS                                      0x1401c8
+/* [RW 20] Parity mask register #0 read/write */
+#define PBF_REG_PBF_PRTY_MASK                                    0x1401e4
+/* [RC 20] Parity register #0 read clear */
+#define PBF_REG_PBF_PRTY_STS_CLR                                 0x1401dc
 #define PB_REG_CONTROL                                           0
 /* [RW 2] Interrupt mask register #0 read/write */
 #define PB_REG_PB_INT_MASK                                       0x28
@@ -2055,6 +2124,8 @@
 #define PB_REG_PB_PRTY_MASK                                      0x38
 /* [R 4] Parity register #0 read */
 #define PB_REG_PB_PRTY_STS                                       0x2c
+/* [RC 4] Parity register #0 read clear */
+#define PB_REG_PB_PRTY_STS_CLR                                   0x30
 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR                (0x1<<0)
 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW        (0x1<<8)
 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR       (0x1<<1)
@@ -2410,6 +2481,8 @@
 #define PRS_REG_PRS_PRTY_MASK                                    0x401a4
 /* [R 8] Parity register #0 read */
 #define PRS_REG_PRS_PRTY_STS                                     0x40198
+/* [RC 8] Parity register #0 read clear */
+#define PRS_REG_PRS_PRTY_STS_CLR                                 0x4019c
 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
    request message */
 #define PRS_REG_PURE_REGIONS                                     0x40024
@@ -2563,6 +2636,9 @@
 /* [R 32] Parity register #0 read */
 #define PXP2_REG_PXP2_PRTY_STS_0                                 0x12057c
 #define PXP2_REG_PXP2_PRTY_STS_1                                 0x12058c
+/* [RC 32] Parity register #0 read clear */
+#define PXP2_REG_PXP2_PRTY_STS_CLR_0                             0x120580
+#define PXP2_REG_PXP2_PRTY_STS_CLR_1                             0x120590
 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
    indication about backpressure) */
 #define PXP2_REG_RD_ALMOST_FULL_0                                0x120424
@@ -2965,6 +3041,8 @@
 #define PXP_REG_PXP_PRTY_MASK                                    0x103094
 /* [R 26] Parity register #0 read */
 #define PXP_REG_PXP_PRTY_STS                                     0x103088
+/* [RC 27] Parity register #0 read clear */
+#define PXP_REG_PXP_PRTY_STS_CLR                                 0x10308c
 /* [RW 4] The activity counter initial increment value sent in the load
    request */
 #define QM_REG_ACTCTRINITVAL_0                                   0x168040
@@ -3121,6 +3199,8 @@
 #define QM_REG_QM_PRTY_MASK                                      0x168454
 /* [R 12] Parity register #0 read */
 #define QM_REG_QM_PRTY_STS                                       0x168448
+/* [RC 12] Parity register #0 read clear */
+#define QM_REG_QM_PRTY_STS_CLR                                   0x16844c
 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
 #define QM_REG_QSTATUS_HIGH                                      0x16802c
 /* [R 32] Current queues in pipeline: Queues from 96 to 127 */
@@ -3406,6 +3486,8 @@
 #define QM_REG_WRRWEIGHTS_9                                      0x168848
 /* [R 6] Keep the fill level of the fifo from write client 1 */
 #define QM_REG_XQM_WRC_FIFOLVL                                   0x168000
+/* [W 1] reset to parity interrupt */
+#define SEM_FAST_REG_PARITY_RST                                  0x18840
 #define SRC_REG_COUNTFREE0                                       0x40500
 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
    ports. If set the searcher support 8 functions. */
@@ -3434,6 +3516,8 @@
 #define SRC_REG_SRC_PRTY_MASK                                    0x404c8
 /* [R 3] Parity register #0 read */
 #define SRC_REG_SRC_PRTY_STS                                     0x404bc
+/* [RC 3] Parity register #0 read clear */
+#define SRC_REG_SRC_PRTY_STS_CLR                                 0x404c0
 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
 #define TCM_REG_CAM_OCCUP                                        0x5017c
 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
@@ -3560,8 +3644,12 @@
 #define TCM_REG_TCM_INT_MASK                                     0x501dc
 /* [R 11] Interrupt register #0 read */
 #define TCM_REG_TCM_INT_STS                                      0x501d0
+/* [RW 27] Parity mask register #0 read/write */
+#define TCM_REG_TCM_PRTY_MASK                                    0x501ec
 /* [R 27] Parity register #0 read */
 #define TCM_REG_TCM_PRTY_STS                                     0x501e0
+/* [RC 27] Parity register #0 read clear */
+#define TCM_REG_TCM_PRTY_STS_CLR                                 0x501e4
 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -3719,6 +3807,10 @@
 #define TM_REG_TM_INT_MASK                                       0x1640fc
 /* [R 1] Interrupt register #0 read */
 #define TM_REG_TM_INT_STS                                        0x1640f0
+/* [RW 7] Parity mask register #0 read/write */
+#define TM_REG_TM_PRTY_MASK                                      0x16410c
+/* [RC 7] Parity register #0 read clear */
+#define TM_REG_TM_PRTY_STS_CLR                                   0x164104
 /* [RW 8] The event id for aggregated interrupt 0 */
 #define TSDM_REG_AGG_INT_EVENT_0                                 0x42038
 #define TSDM_REG_AGG_INT_EVENT_1                                 0x4203c
@@ -3799,6 +3891,8 @@
 #define TSDM_REG_TSDM_PRTY_MASK                                  0x422bc
 /* [R 11] Parity register #0 read */
 #define TSDM_REG_TSDM_PRTY_STS                                   0x422b0
+/* [RC 11] Parity register #0 read clear */
+#define TSDM_REG_TSDM_PRTY_STS_CLR                               0x422b4
 /* [RW 5] The number of time_slots in the arbitration cycle */
 #define TSEM_REG_ARB_CYCLE_SIZE                                  0x180034
 /* [RW 3] The source that is associated with arbitration element 0. Source
@@ -3878,6 +3972,9 @@
 #define TSEM_REG_SLOW_EXT_STORE_EMPTY                            0x1802a0
 /* [RW 8] List of free threads . There is a bit per thread. */
 #define TSEM_REG_THREADS_LIST                                    0x1802e4
+/* [RC 32] Parity register #0 read clear */
+#define TSEM_REG_TSEM_PRTY_STS_CLR_0                             0x180118
+#define TSEM_REG_TSEM_PRTY_STS_CLR_1                             0x180128
 /* [RW 3] The arbitration scheme of time_slot 0 */
 #define TSEM_REG_TS_0_AS                                         0x180038
 /* [RW 3] The arbitration scheme of time_slot 10 */
@@ -4080,6 +4177,8 @@
 #define UCM_REG_UCM_INT_STS                                      0xe01c8
 /* [R 27] Parity register #0 read */
 #define UCM_REG_UCM_PRTY_STS                                     0xe01d8
+/* [RC 27] Parity register #0 read clear */
+#define UCM_REG_UCM_PRTY_STS_CLR                                 0xe01dc
 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
    REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
    Is used to determine the number of the AG context REG-pairs written back;
@@ -4256,6 +4355,8 @@
 #define USDM_REG_USDM_PRTY_MASK                                  0xc42c0
 /* [R 11] Parity register #0 read */
 #define USDM_REG_USDM_PRTY_STS                                   0xc42b4
+/* [RC 11] Parity register #0 read clear */
+#define USDM_REG_USDM_PRTY_STS_CLR                               0xc42b8
 /* [RW 5] The number of time_slots in the arbitration cycle */
 #define USEM_REG_ARB_CYCLE_SIZE                                  0x300034
 /* [RW 3] The source that is associated with arbitration element 0. Source
@@ -4385,6 +4486,9 @@
 /* [R 32] Parity register #0 read */
 #define USEM_REG_USEM_PRTY_STS_0                                 0x300124
 #define USEM_REG_USEM_PRTY_STS_1                                 0x300134
+/* [RC 32] Parity register #0 read clear */
+#define USEM_REG_USEM_PRTY_STS_CLR_0                             0x300128
+#define USEM_REG_USEM_PRTY_STS_CLR_1                             0x300138
 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
  * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
 #define USEM_REG_VFPF_ERR_NUM                                    0x300380
@@ -4761,6 +4865,8 @@
 #define XSDM_REG_XSDM_PRTY_MASK                                  0x1662bc
 /* [R 11] Parity register #0 read */
 #define XSDM_REG_XSDM_PRTY_STS                                   0x1662b0
+/* [RC 11] Parity register #0 read clear */
+#define XSDM_REG_XSDM_PRTY_STS_CLR                               0x1662b4
 /* [RW 5] The number of time_slots in the arbitration cycle */
 #define XSEM_REG_ARB_CYCLE_SIZE                                  0x280034
 /* [RW 3] The source that is associated with arbitration element 0. Source
@@ -4893,6 +4999,9 @@
 /* [R 32] Parity register #0 read */
 #define XSEM_REG_XSEM_PRTY_STS_0                                 0x280124
 #define XSEM_REG_XSEM_PRTY_STS_1                                 0x280134
+/* [RC 32] Parity register #0 read clear */
+#define XSEM_REG_XSEM_PRTY_STS_CLR_0                             0x280128
+#define XSEM_REG_XSEM_PRTY_STS_CLR_1                             0x280138
 #define MCPR_NVM_ACCESS_ENABLE_EN                                (1L<<0)
 #define MCPR_NVM_ACCESS_ENABLE_WR_EN                             (1L<<1)
 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE                             (0xffffffL<<0)
@@ -4970,7 +5079,23 @@
 #define EMAC_REG_EMAC_TX_MODE                                    0xbc
 #define EMAC_REG_EMAC_TX_STAT_AC                                 0x280
 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT                           22
+#define EMAC_REG_RX_PFC_MODE                                     0x320
+#define EMAC_REG_RX_PFC_MODE_PRIORITIES                          (1L<<2)
+#define EMAC_REG_RX_PFC_MODE_RX_EN                               (1L<<1)
+#define EMAC_REG_RX_PFC_MODE_TX_EN                               (1L<<0)
+#define EMAC_REG_RX_PFC_PARAM                                    0x324
+#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT                    0
+#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT               16
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD                          0x328
+#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT                    (0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT                          0x330
+#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT                    (0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD                           0x32c
+#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT                     (0xffff<<0)
+#define EMAC_REG_RX_PFC_STATS_XON_SENT                           0x334
+#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT                     (0xffff<<0)
 #define EMAC_RX_MODE_FLOW_EN                                     (1L<<2)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL                            (1L<<3)
 #define EMAC_RX_MODE_KEEP_VLAN_TAG                               (1L<<10)
 #define EMAC_RX_MODE_PROMISCUOUS                                 (1L<<8)
 #define EMAC_RX_MODE_RESET                                       (1L<<0)
@@ -6264,3 +6389,4 @@ static inline u8 calc_crc8(u32 data, u8 crc)
 }
 
 
+#endif /* BNX2X_REG_H */
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c
index 4733c835dad9..bda60d590fa8 100644
--- a/drivers/net/bnx2x/bnx2x_stats.c
+++ b/drivers/net/bnx2x/bnx2x_stats.c
@@ -158,9 +158,14 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
 
                 spin_lock_bh(&bp->stats_lock);
 
+                if (bp->stats_pending) {
+                        spin_unlock_bh(&bp->stats_lock);
+                        return;
+                }
+
                 ramrod_data.drv_counter = bp->stats_counter++;
                 ramrod_data.collect_port = bp->port.pmf ? 1 : 0;
-                for_each_queue(bp, i)
+                for_each_eth_queue(bp, i)
                         ramrod_data.ctr_id_vector |= (1 << bp->fp[i].cl_id);
 
                 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
@@ -766,7 +771,7 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
         estats->no_buff_discard_hi = 0;
         estats->no_buff_discard_lo = 0;
 
-        for_each_queue(bp, i) {
+        for_each_eth_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
                 int cl_id = fp->cl_id;
                 struct tstorm_per_client_stats *tclient =
@@ -996,7 +1001,7 @@ static void bnx2x_net_stats_update(struct bnx2x *bp)
         nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
 
         tmp = estats->mac_discard;
-        for_each_queue(bp, i)
+        for_each_rx_queue(bp, i)
                 tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
         nstats->rx_dropped = tmp;
 
@@ -1087,7 +1092,7 @@ static void bnx2x_stats_update(struct bnx2x *bp)
                        bp->dev->name,
                        estats->brb_drop_lo, estats->brb_truncate_lo);
 
-                for_each_queue(bp, i) {
+                for_each_eth_queue(bp, i) {
                         struct bnx2x_fastpath *fp = &bp->fp[i];
                         struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
 
@@ -1101,7 +1106,7 @@ static void bnx2x_stats_update(struct bnx2x *bp)
                                fp->rx_calls, fp->rx_pkt);
                 }
 
-                for_each_queue(bp, i) {
+                for_each_eth_queue(bp, i) {
                         struct bnx2x_fastpath *fp = &bp->fp[i];
                         struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
                         struct netdev_queue *txq =
@@ -1381,7 +1386,8 @@ void bnx2x_stats_init(struct bnx2x *bp)
                 memset(&fp->eth_q_stats, 0, sizeof(struct bnx2x_eth_q_stats));
         }
 
-        for_each_queue(bp, i) {
+        /* FW stats are currently collected for ETH clients only */
+        for_each_eth_queue(bp, i) {
                 /* Set initial stats counter in the stats ramrod data to -1 */
                 int cl_id = bp->fp[i].cl_id;
 
diff --git a/drivers/net/bnx2x/bnx2x_stats.h b/drivers/net/bnx2x/bnx2x_stats.h
index afd15efa429a..596798c47452 100644
--- a/drivers/net/bnx2x/bnx2x_stats.h
+++ b/drivers/net/bnx2x/bnx2x_stats.h
@@ -53,7 +53,6 @@ struct bnx2x_eth_q_stats {
         u32 hw_csum_err;
 };
 
-#define BNX2X_NUM_Q_STATS               13
 #define Q_STATS_OFFSET32(stat_name) \
                         (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
 
@@ -225,7 +224,6 @@ struct bnx2x_eth_stats {
         u32 nig_timer_max;
 };
 
-#define BNX2X_NUM_STATS                 43
 #define STATS_OFFSET32(stat_name) \
                         (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
 
diff --git a/drivers/net/bonding/Makefile b/drivers/net/bonding/Makefile
index 6f9c6faef24c..0e2737eac8b7 100644
--- a/drivers/net/bonding/Makefile
+++ b/drivers/net/bonding/Makefile
@@ -4,7 +4,7 @@
 
 obj-$(CONFIG_BONDING) += bonding.o
 
-bonding-objs := bond_main.o bond_3ad.o bond_alb.o bond_sysfs.o
+bonding-objs := bond_main.o bond_3ad.o bond_alb.o bond_sysfs.o bond_debugfs.o
 
 ipv6-$(subst m,y,$(CONFIG_IPV6)) += bond_ipv6.o
 bonding-objs += $(ipv6-y)
diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c
index 106718c1be5b..171782e2bb39 100644
--- a/drivers/net/bonding/bond_3ad.c
+++ b/drivers/net/bonding/bond_3ad.c
@@ -2474,8 +2474,7 @@ int bond_3ad_lacpdu_recv(struct sk_buff *skb, struct net_device *dev, struct pac
                 goto out;
 
         read_lock(&bond->lock);
-        slave = bond_get_slave_by_dev((struct bonding *)netdev_priv(dev),
-                                        orig_dev);
+        slave = bond_get_slave_by_dev(netdev_priv(dev), orig_dev);
         if (!slave)
                 goto out_unlock;
 
diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
index 26bb118c4533..f4e638c65129 100644
--- a/drivers/net/bonding/bond_alb.c
+++ b/drivers/net/bonding/bond_alb.c
@@ -44,42 +44,6 @@
 #include "bond_alb.h"
 
 
-#define ALB_TIMER_TICKS_PER_SEC     10  /* should be a divisor of HZ */
-#define BOND_TLB_REBALANCE_INTERVAL 10  /* In seconds, periodic re-balancing.
-                                         * Used for division - never set
-                                         * to zero !!!
-                                         */
-#define BOND_ALB_LP_INTERVAL        1   /* In seconds, periodic send of
-                                         * learning packets to the switch
-                                         */
-
-#define BOND_TLB_REBALANCE_TICKS (BOND_TLB_REBALANCE_INTERVAL \
-                                  * ALB_TIMER_TICKS_PER_SEC)
-
-#define BOND_ALB_LP_TICKS (BOND_ALB_LP_INTERVAL \
-                           * ALB_TIMER_TICKS_PER_SEC)
-
-#define TLB_HASH_TABLE_SIZE 256 /* The size of the clients hash table.
-                                 * Note that this value MUST NOT be smaller
-                                 * because the key hash table is BYTE wide !
-                                 */
-
-
-#define TLB_NULL_INDEX          0xffffffff
-#define MAX_LP_BURST            3
-
-/* rlb defs */
-#define RLB_HASH_TABLE_SIZE     256
-#define RLB_NULL_INDEX          0xffffffff
-#define RLB_UPDATE_DELAY        2*ALB_TIMER_TICKS_PER_SEC /* 2 seconds */
-#define RLB_ARP_BURST_SIZE      2
-#define RLB_UPDATE_RETRY        3       /* 3-ticks - must be smaller than the rlb
-                                         * rebalance interval (5 min).
-                                         */
-/* RLB_PROMISC_TIMEOUT = 10 sec equals the time that the current slave is
- * promiscuous after failover
- */
-#define RLB_PROMISC_TIMEOUT     10*ALB_TIMER_TICKS_PER_SEC
 
 #ifndef __long_aligned
 #define __long_aligned __attribute__((aligned((sizeof(long)))))
diff --git a/drivers/net/bonding/bond_alb.h b/drivers/net/bonding/bond_alb.h
index 50968f8196cf..118c28aa471e 100644
--- a/drivers/net/bonding/bond_alb.h
+++ b/drivers/net/bonding/bond_alb.h
@@ -31,6 +31,44 @@ struct slave;
 #define BOND_ALB_INFO(bond)   ((bond)->alb_info)
 #define SLAVE_TLB_INFO(slave) ((slave)->tlb_info)
 
+#define ALB_TIMER_TICKS_PER_SEC     10  /* should be a divisor of HZ */
+#define BOND_TLB_REBALANCE_INTERVAL 10  /* In seconds, periodic re-balancing.
+                                         * Used for division - never set
+                                         * to zero !!!
+                                         */
+#define BOND_ALB_LP_INTERVAL        1   /* In seconds, periodic send of
+                                         * learning packets to the switch
+                                         */
+
+#define BOND_TLB_REBALANCE_TICKS (BOND_TLB_REBALANCE_INTERVAL \
+                                  * ALB_TIMER_TICKS_PER_SEC)
+
+#define BOND_ALB_LP_TICKS (BOND_ALB_LP_INTERVAL \
+                           * ALB_TIMER_TICKS_PER_SEC)
+
+#define TLB_HASH_TABLE_SIZE 256 /* The size of the clients hash table.
+                                 * Note that this value MUST NOT be smaller
+                                 * because the key hash table is BYTE wide !
+                                 */
+
+
+#define TLB_NULL_INDEX          0xffffffff
+#define MAX_LP_BURST            3
+
+/* rlb defs */
+#define RLB_HASH_TABLE_SIZE     256
+#define RLB_NULL_INDEX          0xffffffff
+#define RLB_UPDATE_DELAY        (2*ALB_TIMER_TICKS_PER_SEC) /* 2 seconds */
+#define RLB_ARP_BURST_SIZE      2
+#define RLB_UPDATE_RETRY        3 /* 3-ticks - must be smaller than the rlb
+                                   * rebalance interval (5 min).
+                                   */
+/* RLB_PROMISC_TIMEOUT = 10 sec equals the time that the current slave is
+ * promiscuous after failover
+ */
+#define RLB_PROMISC_TIMEOUT     (10*ALB_TIMER_TICKS_PER_SEC)
+
+
 struct tlb_client_info {
         struct slave *tx_slave; /* A pointer to slave used for transmiting
                                  * packets to a Client that the Hash function
diff --git a/drivers/net/bonding/bond_debugfs.c b/drivers/net/bonding/bond_debugfs.c
new file mode 100644
index 000000000000..3680aa251dea
--- /dev/null
+++ b/drivers/net/bonding/bond_debugfs.c
@@ -0,0 +1,146 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/netdevice.h>
+
+#include "bonding.h"
+#include "bond_alb.h"
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static struct dentry *bonding_debug_root;
+
+/*
+ *  Show RLB hash table
+ */
+static int bond_debug_rlb_hash_show(struct seq_file *m, void *v)
+{
+        struct bonding *bond = m->private;
+        struct alb_bond_info *bond_info = &(BOND_ALB_INFO(bond));
+        struct rlb_client_info *client_info;
+        u32 hash_index;
+
+        if (bond->params.mode != BOND_MODE_ALB)
+                return 0;
+
+        seq_printf(m, "SourceIP        DestinationIP   "
+                        "Destination MAC   DEV\n");
+
+        spin_lock_bh(&(BOND_ALB_INFO(bond).rx_hashtbl_lock));
+
+        hash_index = bond_info->rx_hashtbl_head;
+        for (; hash_index != RLB_NULL_INDEX; hash_index = client_info->next) {
+                client_info = &(bond_info->rx_hashtbl[hash_index]);
+                seq_printf(m, "%-15pI4 %-15pI4 %-17pM %s\n",
+                        &client_info->ip_src,
+                        &client_info->ip_dst,
+                        &client_info->mac_dst,
+                        client_info->slave->dev->name);
+        }
+
+        spin_unlock_bh(&(BOND_ALB_INFO(bond).rx_hashtbl_lock));
+
+        return 0;
+}
+
+static int bond_debug_rlb_hash_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, bond_debug_rlb_hash_show, inode->i_private);
+}
+
+static const struct file_operations bond_debug_rlb_hash_fops = {
+        .owner          = THIS_MODULE,
+        .open           = bond_debug_rlb_hash_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+void bond_debug_register(struct bonding *bond)
+{
+        if (!bonding_debug_root)
+                return;
+
+        bond->debug_dir =
+                debugfs_create_dir(bond->dev->name, bonding_debug_root);
+
+        if (!bond->debug_dir) {
+                pr_warning("%s: Warning: failed to register to debugfs\n",
+                        bond->dev->name);
+                return;
+        }
+
+        debugfs_create_file("rlb_hash_table", 0400, bond->debug_dir,
+                                bond, &bond_debug_rlb_hash_fops);
+}
+
+void bond_debug_unregister(struct bonding *bond)
+{
+        if (!bonding_debug_root)
+                return;
+
+        debugfs_remove_recursive(bond->debug_dir);
+}
+
+void bond_debug_reregister(struct bonding *bond)
+{
+        struct dentry *d;
+
+        if (!bonding_debug_root)
+                return;
+
+        d = debugfs_rename(bonding_debug_root, bond->debug_dir,
+                           bonding_debug_root, bond->dev->name);
+        if (d) {
+                bond->debug_dir = d;
+        } else {
+                pr_warning("%s: Warning: failed to reregister, "
+                                "so just unregister old one\n",
+                                bond->dev->name);
+                bond_debug_unregister(bond);
+        }
+}
+
+void bond_create_debugfs(void)
+{
+        bonding_debug_root = debugfs_create_dir("bonding", NULL);
+
+        if (!bonding_debug_root) {
+                pr_warning("Warning: Cannot create bonding directory"
+                                " in debugfs\n");
+        }
+}
+
+void bond_destroy_debugfs(void)
+{
+        debugfs_remove_recursive(bonding_debug_root);
+        bonding_debug_root = NULL;
+}
+
+
+#else /* !CONFIG_DEBUG_FS */
+
+void bond_debug_register(struct bonding *bond)
+{
+}
+
+void bond_debug_unregister(struct bonding *bond)
+{
+}
+
+void bond_debug_reregister(struct bonding *bond)
+{
+}
+
+void bond_create_debugfs(void)
+{
+}
+
+void bond_destroy_debugfs(void)
+{
+}
+
+#endif /* CONFIG_DEBUG_FS */
diff --git a/drivers/net/bonding/bond_ipv6.c b/drivers/net/bonding/bond_ipv6.c
index 121b073a6c3f..84fbd4ebd778 100644
--- a/drivers/net/bonding/bond_ipv6.c
+++ b/drivers/net/bonding/bond_ipv6.c
@@ -88,7 +88,12 @@ static void bond_na_send(struct net_device *slave_dev,
         }
 
         if (vlan_id) {
-                skb = vlan_put_tag(skb, vlan_id);
+                /* The Ethernet header is not present yet, so it is
+                 * too early to insert a VLAN tag.  Force use of an
+                 * out-of-line tag here and let dev_hard_start_xmit()
+                 * insert it if the slave hardware can't.
+                 */
+                skb = __vlan_hwaccel_put_tag(skb, vlan_id);
                 if (!skb) {
                         pr_err("failed to insert VLAN tag\n");
                         return;
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index d0ea760ce419..b1025b85acf1 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -418,36 +418,11 @@ struct vlan_entry *bond_next_vlan(struct bonding *bond, struct vlan_entry *curr)
  * @bond: bond device that got this skb for tx.
  * @skb: hw accel VLAN tagged skb to transmit
  * @slave_dev: slave that is supposed to xmit this skbuff
- *
- * When the bond gets an skb to transmit that is
- * already hardware accelerated VLAN tagged, and it
- * needs to relay this skb to a slave that is not
- * hw accel capable, the skb needs to be "unaccelerated",
- * i.e. strip the hwaccel tag and re-insert it as part
- * of the payload.
  */
 int bond_dev_queue_xmit(struct bonding *bond, struct sk_buff *skb,
                         struct net_device *slave_dev)
 {
-        unsigned short uninitialized_var(vlan_id);
-
-        /* Test vlan_list not vlgrp to catch and handle 802.1p tags */
-        if (!list_empty(&bond->vlan_list) &&
-            !(slave_dev->features & NETIF_F_HW_VLAN_TX) &&
-            vlan_get_tag(skb, &vlan_id) == 0) {
-                skb->dev = slave_dev;
-                skb = vlan_put_tag(skb, vlan_id);
-                if (!skb) {
-                        /* vlan_put_tag() frees the skb in case of error,
-                         * so return success here so the calling functions
-                         * won't attempt to free is again.
-                         */
-                        return 0;
-                }
-        } else {
-                skb->dev = slave_dev;
-        }
-
+        skb->dev = slave_dev;
         skb->priority = 1;
 #ifdef CONFIG_NET_POLL_CONTROLLER
         if (unlikely(bond->dev->priv_flags & IFF_IN_NETPOLL)) {
@@ -873,17 +848,11 @@ static void bond_mc_del(struct bonding *bond, void *addr)
 static void __bond_resend_igmp_join_requests(struct net_device *dev)
 {
         struct in_device *in_dev;
-        struct ip_mc_list *im;
 
         rcu_read_lock();
         in_dev = __in_dev_get_rcu(dev);
-        if (in_dev) {
-                read_lock(&in_dev->mc_list_lock);
-                for (im = in_dev->mc_list; im; im = im->next)
-                        ip_mc_rejoin_group(im);
-                read_unlock(&in_dev->mc_list_lock);
-        }
-
+        if (in_dev)
+                ip_mc_rejoin_groups(in_dev);
         rcu_read_unlock();
 }
 
@@ -1203,11 +1172,13 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
                                 bond_do_fail_over_mac(bond, new_active,
                                                       old_active);
 
-                        bond->send_grat_arp = bond->params.num_grat_arp;
-                        bond_send_gratuitous_arp(bond);
+                        if (netif_running(bond->dev)) {
+                                bond->send_grat_arp = bond->params.num_grat_arp;
+                                bond_send_gratuitous_arp(bond);
 
-                        bond->send_unsol_na = bond->params.num_unsol_na;
-                        bond_send_unsolicited_na(bond);
+                                bond->send_unsol_na = bond->params.num_unsol_na;
+                                bond_send_unsolicited_na(bond);
+                        }
 
                         write_unlock_bh(&bond->curr_slave_lock);
                         read_unlock(&bond->lock);
@@ -1221,8 +1192,9 @@ void bond_change_active_slave(struct bonding *bond, struct slave *new_active)
 
         /* resend IGMP joins since active slave has changed or
          * all were sent on curr_active_slave */
-        if ((USES_PRIMARY(bond->params.mode) && new_active) ||
-            bond->params.mode == BOND_MODE_ROUNDROBIN) {
+        if (((USES_PRIMARY(bond->params.mode) && new_active) ||
+             bond->params.mode == BOND_MODE_ROUNDROBIN) &&
+            netif_running(bond->dev)) {
                 bond->igmp_retrans = bond->params.resend_igmp;
                 queue_delayed_work(bond->wq, &bond->mcast_work, 0);
         }
@@ -3211,7 +3183,7 @@ out:
 #ifdef CONFIG_PROC_FS
 
 static void *bond_info_seq_start(struct seq_file *seq, loff_t *pos)
-        __acquires(&dev_base_lock)
+        __acquires(RCU)
         __acquires(&bond->lock)
 {
         struct bonding *bond = seq->private;
@@ -3220,7 +3192,7 @@ static void *bond_info_seq_start(struct seq_file *seq, loff_t *pos)
         int i;
 
         /* make sure the bond won't be taken away */
-        read_lock(&dev_base_lock);
+        rcu_read_lock();
         read_lock(&bond->lock);
 
         if (*pos == 0)
@@ -3250,12 +3222,12 @@ static void *bond_info_seq_next(struct seq_file *seq, void *v, loff_t *pos)
 
 static void bond_info_seq_stop(struct seq_file *seq, void *v)
         __releases(&bond->lock)
-        __releases(&dev_base_lock)
+        __releases(RCU)
 {
         struct bonding *bond = seq->private;
 
         read_unlock(&bond->lock);
-        read_unlock(&dev_base_lock);
+        rcu_read_unlock();
 }
 
 static void bond_info_show_master(struct seq_file *seq)
@@ -3509,6 +3481,8 @@ static int bond_event_changename(struct bonding *bond)
         bond_remove_proc_entry(bond);
         bond_create_proc_entry(bond);
 
+        bond_debug_reregister(bond);
+
         return NOTIFY_DONE;
 }
 
@@ -4791,6 +4765,8 @@ static void bond_uninit(struct net_device *bond_dev)
 
         bond_remove_proc_entry(bond);
 
+        bond_debug_unregister(bond);
+
         __hw_addr_flush(&bond->mc_list);
 
         list_for_each_entry_safe(vlan, tmp, &bond->vlan_list, vlan_list) {
@@ -5193,6 +5169,8 @@ static int bond_init(struct net_device *bond_dev)
 
         bond_prepare_sysfs_group(bond);
 
+        bond_debug_register(bond);
+
         __hw_addr_init(&bond->mc_list);
         return 0;
 }
@@ -5307,6 +5285,8 @@ static int __init bonding_init(void)
         if (res)
                 goto err_link;
 
+        bond_create_debugfs();
+
         for (i = 0; i < max_bonds; i++) {
                 res = bond_create(&init_net, NULL);
                 if (res)
@@ -5317,7 +5297,6 @@ static int __init bonding_init(void)
         if (res)
                 goto err;
 
-
         register_netdevice_notifier(&bond_netdev_notifier);
         register_inetaddr_notifier(&bond_inetaddr_notifier);
         bond_register_ipv6_notifier();
@@ -5338,6 +5317,7 @@ static void __exit bonding_exit(void)
         bond_unregister_ipv6_notifier();
 
         bond_destroy_sysfs();
+        bond_destroy_debugfs();
 
         rtnl_link_unregister(&bond_link_ops);
         unregister_pernet_subsys(&bond_net_ops);
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index c2f081352a03..31fe980e4e28 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -18,7 +18,6 @@
 #include <linux/timer.h>
 #include <linux/proc_fs.h>
 #include <linux/if_bonding.h>
-#include <linux/kobject.h>
 #include <linux/cpumask.h>
 #include <linux/in6.h>
 #include "bond_3ad.h"
@@ -255,6 +254,10 @@ struct bonding {
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
         struct   in6_addr master_ipv6;
 #endif
+#ifdef CONFIG_DEBUG_FS
+        /* debugging suport via debugfs */
+        struct   dentry *debug_dir;
+#endif /* CONFIG_DEBUG_FS */
 };
 
 /**
@@ -269,11 +272,11 @@ static inline struct slave *bond_get_slave_by_dev(struct bonding *bond, struct n
 
         bond_for_each_slave(bond, slave, i) {
                 if (slave->dev == slave_dev) {
-                        break;
+                        return slave;
                 }
         }
 
-        return slave;
+        return 0;
 }
 
 static inline struct bonding *bond_get_bond_by_slave(struct slave *slave)
@@ -282,7 +285,7 @@ static inline struct bonding *bond_get_bond_by_slave(struct slave *slave)
                 return NULL;
         }
 
-        return (struct bonding *)netdev_priv(slave->dev->master);
+        return netdev_priv(slave->dev->master);
 }
 
 static inline bool bond_is_lb(const struct bonding *bond)
@@ -376,6 +379,11 @@ void bond_select_active_slave(struct bonding *bond);
 void bond_change_active_slave(struct bonding *bond, struct slave *new_active);
 void bond_register_arp(struct bonding *);
 void bond_unregister_arp(struct bonding *);
+void bond_create_debugfs(void);
+void bond_destroy_debugfs(void);
+void bond_debug_register(struct bonding *bond);
+void bond_debug_unregister(struct bonding *bond);
+void bond_debug_reregister(struct bonding *bond);
 
 struct bond_net {
         struct net *            net;    /* Associated network namespace */
diff --git a/drivers/net/caif/caif_shm_u5500.c b/drivers/net/caif/caif_shm_u5500.c
index 32b1c6fb2de1..5f771ab712c4 100644
--- a/drivers/net/caif/caif_shm_u5500.c
+++ b/drivers/net/caif/caif_shm_u5500.c
@@ -11,7 +11,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/netdevice.h>
-#include <mach/mbox.h>
+#include <mach/mbox-db5500.h>
 #include <net/caif/caif_shm.h>
 
 MODULE_LICENSE("GPL");
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 080574b0fff0..d5a9db60ade9 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -12,6 +12,27 @@ config CAN_VCAN
           This driver can also be built as a module.  If so, the module
           will be called vcan.
 
+config CAN_SLCAN
+        tristate "Serial / USB serial CAN Adaptors (slcan)"
+        depends on CAN
+        default N
+        ---help---
+          CAN driver for several 'low cost' CAN interfaces that are attached
+          via serial lines or via USB-to-serial adapters using the LAWICEL
+          ASCII protocol. The driver implements the tty linediscipline N_SLCAN.
+
+          As only the sending and receiving of CAN frames is implemented, this
+          driver should work with the (serial/USB) CAN hardware from:
+          www.canusb.com / www.can232.com / www.mictronic.com / www.canhack.de
+
+          Userspace tools to attach the SLCAN line discipline (slcan_attach,
+          slcand) can be found in the can-utils at the SocketCAN SVN, see
+          http://developer.berlios.de/projects/socketcan for details.
+
+          The slcan driver supports up to 10 CAN netdevices by default which
+          can be changed by the 'maxdev=xx' module option. This driver can
+          also be built as a module. If so, the module will be called slcan.
+
 config CAN_DEV
         tristate "Platform CAN drivers with Netlink support"
         depends on CAN
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 90af15a4f106..07ca159ba3f9 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_CAN_VCAN)          += vcan.o
+obj-$(CONFIG_CAN_SLCAN)         += slcan.o
 
 obj-$(CONFIG_CAN_DEV)           += can-dev.o
 can-dev-y                       := dev.o
diff --git a/drivers/net/can/janz-ican3.c b/drivers/net/can/janz-ican3.c
index 6e533dcc36c0..b9a6d7a5a739 100644
--- a/drivers/net/can/janz-ican3.c
+++ b/drivers/net/can/janz-ican3.c
@@ -1114,11 +1114,6 @@ static bool ican3_txok(struct ican3_dev *mod)
 /*
  * Recieve one CAN frame from the hardware
  *
- * This works like the core of a NAPI function, but is intended to be called
- * from workqueue context instead. This driver already needs a workqueue to
- * process control messages, so we use the workqueue instead of using NAPI.
- * This was done to simplify locking.
- *
  * CONTEXT: must be called from user context
  */
 static int ican3_recv_skb(struct ican3_dev *mod)
@@ -1251,7 +1246,6 @@ static irqreturn_t ican3_irq(int irq, void *dev_id)
  * Reset an ICAN module to its power-on state
  *
  * CONTEXT: no network device registered
- * LOCKING: work function disabled
  */
 static int ican3_reset_module(struct ican3_dev *mod)
 {
@@ -1262,9 +1256,6 @@ static int ican3_reset_module(struct ican3_dev *mod)
         /* disable interrupts so no more work is scheduled */
         iowrite8(1 << mod->num, &mod->ctrl->int_disable);
 
-        /* flush any pending work */
-        flush_scheduled_work();
-
         /* the first unallocated page in the DPM is #9 */
         mod->free_page = DPM_FREE_START;
 
diff --git a/drivers/net/can/mscan/mscan.c b/drivers/net/can/mscan/mscan.c
index 64c378cd0c34..74cd880c7e06 100644
--- a/drivers/net/can/mscan/mscan.c
+++ b/drivers/net/can/mscan/mscan.c
@@ -182,7 +182,7 @@ static int mscan_restart(struct net_device *dev)
 
                 priv->can.state = CAN_STATE_ERROR_ACTIVE;
                 WARN(!(in_8(&regs->canmisc) & MSCAN_BOHOLD),
-                     "bus-off state expected");
+                     "bus-off state expected\n");
                 out_8(&regs->canmisc, MSCAN_BOHOLD);
                 /* Re-enable receive interrupts. */
                 out_8(&regs->canrier, MSCAN_RX_INTS_ENABLE);
diff --git a/drivers/net/can/pch_can.c b/drivers/net/can/pch_can.c
index 672718261c68..c42e97268248 100644
--- a/drivers/net/can/pch_can.c
+++ b/drivers/net/can/pch_can.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 1999 - 2010 Intel Corporation.
- * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
+ * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -32,106 +32,115 @@
 #include <linux/can/dev.h>
 #include <linux/can/error.h>
 
-#define MAX_MSG_OBJ             32
-#define MSG_OBJ_RX              0 /* The receive message object flag. */
-#define MSG_OBJ_TX              1 /* The transmit message object flag. */
-
-#define ENABLE                  1 /* The enable flag */
-#define DISABLE                 0 /* The disable flag */
-#define CAN_CTRL_INIT           0x0001 /* The INIT bit of CANCONT register. */
-#define CAN_CTRL_IE             0x0002 /* The IE bit of CAN control register */
-#define CAN_CTRL_IE_SIE_EIE     0x000e
-#define CAN_CTRL_CCE            0x0040
-#define CAN_CTRL_OPT            0x0080 /* The OPT bit of CANCONT register. */
-#define CAN_OPT_SILENT          0x0008 /* The Silent bit of CANOPT reg. */
-#define CAN_OPT_LBACK           0x0010 /* The LoopBack bit of CANOPT reg. */
-#define CAN_CMASK_RX_TX_SET     0x00f3
-#define CAN_CMASK_RX_TX_GET     0x0073
-#define CAN_CMASK_ALL           0xff
-#define CAN_CMASK_RDWR          0x80
-#define CAN_CMASK_ARB           0x20
-#define CAN_CMASK_CTRL          0x10
-#define CAN_CMASK_MASK          0x40
-#define CAN_CMASK_NEWDAT        0x04
-#define CAN_CMASK_CLRINTPND     0x08
-
-#define CAN_IF_MCONT_NEWDAT     0x8000
-#define CAN_IF_MCONT_INTPND     0x2000
-#define CAN_IF_MCONT_UMASK      0x1000
-#define CAN_IF_MCONT_TXIE       0x0800
-#define CAN_IF_MCONT_RXIE       0x0400
-#define CAN_IF_MCONT_RMTEN      0x0200
-#define CAN_IF_MCONT_TXRQXT     0x0100
-#define CAN_IF_MCONT_EOB        0x0080
-#define CAN_IF_MCONT_DLC        0x000f
-#define CAN_IF_MCONT_MSGLOST    0x4000
-#define CAN_MASK2_MDIR_MXTD     0xc000
-#define CAN_ID2_DIR             0x2000
-#define CAN_ID_MSGVAL           0x8000
-
-#define CAN_STATUS_INT          0x8000
-#define CAN_IF_CREQ_BUSY        0x8000
-#define CAN_ID2_XTD             0x4000
-
-#define CAN_REC                 0x00007f00
-#define CAN_TEC                 0x000000ff
-
-#define PCH_RX_OK               0x00000010
-#define PCH_TX_OK               0x00000008
-#define PCH_BUS_OFF             0x00000080
-#define PCH_EWARN               0x00000040
-#define PCH_EPASSIV             0x00000020
-#define PCH_LEC0                0x00000001
-#define PCH_LEC1                0x00000002
-#define PCH_LEC2                0x00000004
-#define PCH_LEC_ALL             (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
-#define PCH_STUF_ERR            PCH_LEC0
-#define PCH_FORM_ERR            PCH_LEC1
-#define PCH_ACK_ERR             (PCH_LEC0 | PCH_LEC1)
-#define PCH_BIT1_ERR            PCH_LEC2
-#define PCH_BIT0_ERR            (PCH_LEC0 | PCH_LEC2)
-#define PCH_CRC_ERR             (PCH_LEC1 | PCH_LEC2)
+#define PCH_CTRL_INIT           BIT(0) /* The INIT bit of CANCONT register. */
+#define PCH_CTRL_IE             BIT(1) /* The IE bit of CAN control register */
+#define PCH_CTRL_IE_SIE_EIE     (BIT(3) | BIT(2) | BIT(1))
+#define PCH_CTRL_CCE            BIT(6)
+#define PCH_CTRL_OPT            BIT(7) /* The OPT bit of CANCONT register. */
+#define PCH_OPT_SILENT          BIT(3) /* The Silent bit of CANOPT reg. */
+#define PCH_OPT_LBACK           BIT(4) /* The LoopBack bit of CANOPT reg. */
+
+#define PCH_CMASK_RX_TX_SET     0x00f3
+#define PCH_CMASK_RX_TX_GET     0x0073
+#define PCH_CMASK_ALL           0xff
+#define PCH_CMASK_NEWDAT        BIT(2)
+#define PCH_CMASK_CLRINTPND     BIT(3)
+#define PCH_CMASK_CTRL          BIT(4)
+#define PCH_CMASK_ARB           BIT(5)
+#define PCH_CMASK_MASK          BIT(6)
+#define PCH_CMASK_RDWR          BIT(7)
+#define PCH_IF_MCONT_NEWDAT     BIT(15)
+#define PCH_IF_MCONT_MSGLOST    BIT(14)
+#define PCH_IF_MCONT_INTPND     BIT(13)
+#define PCH_IF_MCONT_UMASK      BIT(12)
+#define PCH_IF_MCONT_TXIE       BIT(11)
+#define PCH_IF_MCONT_RXIE       BIT(10)
+#define PCH_IF_MCONT_RMTEN      BIT(9)
+#define PCH_IF_MCONT_TXRQXT     BIT(8)
+#define PCH_IF_MCONT_EOB        BIT(7)
+#define PCH_IF_MCONT_DLC        (BIT(0) | BIT(1) | BIT(2) | BIT(3))
+#define PCH_MASK2_MDIR_MXTD     (BIT(14) | BIT(15))
+#define PCH_ID2_DIR             BIT(13)
+#define PCH_ID2_XTD             BIT(14)
+#define PCH_ID_MSGVAL           BIT(15)
+#define PCH_IF_CREQ_BUSY        BIT(15)
+
+#define PCH_STATUS_INT          0x8000
+#define PCH_REC                 0x00007f00
+#define PCH_TEC                 0x000000ff
+
+#define PCH_TX_OK               BIT(3)
+#define PCH_RX_OK               BIT(4)
+#define PCH_EPASSIV             BIT(5)
+#define PCH_EWARN               BIT(6)
+#define PCH_BUS_OFF             BIT(7)
 
 /* bit position of certain controller bits. */
-#define BIT_BITT_BRP            0
-#define BIT_BITT_SJW            6
-#define BIT_BITT_TSEG1          8
-#define BIT_BITT_TSEG2          12
-#define BIT_IF1_MCONT_RXIE      10
-#define BIT_IF2_MCONT_TXIE      11
-#define BIT_BRPE_BRPE           6
-#define BIT_ES_TXERRCNT         0
-#define BIT_ES_RXERRCNT         8
-#define MSK_BITT_BRP            0x3f
-#define MSK_BITT_SJW            0xc0
-#define MSK_BITT_TSEG1          0xf00
-#define MSK_BITT_TSEG2          0x7000
-#define MSK_BRPE_BRPE           0x3c0
-#define MSK_BRPE_GET            0x0f
-#define MSK_CTRL_IE_SIE_EIE     0x07
-#define MSK_MCONT_TXIE          0x08
-#define MSK_MCONT_RXIE          0x10
-#define PCH_CAN_NO_TX_BUFF      1
-#define COUNTER_LIMIT           10
+#define PCH_BIT_BRP_SHIFT       0
+#define PCH_BIT_SJW_SHIFT       6
+#define PCH_BIT_TSEG1_SHIFT     8
+#define PCH_BIT_TSEG2_SHIFT     12
+#define PCH_BIT_BRPE_BRPE_SHIFT 6
+
+#define PCH_MSK_BITT_BRP        0x3f
+#define PCH_MSK_BRPE_BRPE       0x3c0
+#define PCH_MSK_CTRL_IE_SIE_EIE 0x07
+#define PCH_COUNTER_LIMIT       10
 
 #define PCH_CAN_CLK             50000000        /* 50MHz */
 
-/* Define the number of message object.
+/*
+ * Define the number of message object.
  * PCH CAN communications are done via Message RAM.
- * The Message RAM consists of 32 message objects. */
-#define PCH_RX_OBJ_NUM          26  /* 1~ PCH_RX_OBJ_NUM is Rx*/
-#define PCH_TX_OBJ_NUM          6  /* PCH_RX_OBJ_NUM is RX ~ Tx*/
-#define PCH_OBJ_NUM             (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
+ * The Message RAM consists of 32 message objects.
+ */
+#define PCH_RX_OBJ_NUM          26
+#define PCH_TX_OBJ_NUM          6
+#define PCH_RX_OBJ_START        1
+#define PCH_RX_OBJ_END          PCH_RX_OBJ_NUM
+#define PCH_TX_OBJ_START        (PCH_RX_OBJ_END + 1)
+#define PCH_TX_OBJ_END          (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
 
 #define PCH_FIFO_THRESH         16
 
+/* TxRqst2 show status of MsgObjNo.17~32 */
+#define PCH_TREQ2_TX_MASK       (((1 << PCH_TX_OBJ_NUM) - 1) <<\
+                                                        (PCH_RX_OBJ_END - 16))
+
+enum pch_ifreg {
+        PCH_RX_IFREG,
+        PCH_TX_IFREG,
+};
+
+enum pch_can_err {
+        PCH_STUF_ERR = 1,
+        PCH_FORM_ERR,
+        PCH_ACK_ERR,
+        PCH_BIT1_ERR,
+        PCH_BIT0_ERR,
+        PCH_CRC_ERR,
+        PCH_LEC_ALL,
+};
+
 enum pch_can_mode {
         PCH_CAN_ENABLE,
         PCH_CAN_DISABLE,
         PCH_CAN_ALL,
         PCH_CAN_NONE,
         PCH_CAN_STOP,
-        PCH_CAN_RUN
+        PCH_CAN_RUN,
+};
+
+struct pch_can_if_regs {
+        u32 creq;
+        u32 cmask;
+        u32 mask1;
+        u32 mask2;
+        u32 id1;
+        u32 id2;
+        u32 mcont;
+        u32 data[4];
+        u32 rsv[13];
 };
 
 struct pch_can_regs {
@@ -142,57 +151,36 @@ struct pch_can_regs {
         u32 intr;
         u32 opt;
         u32 brpe;
-        u32 reserve1;
-        u32 if1_creq;
-        u32 if1_cmask;
-        u32 if1_mask1;
-        u32 if1_mask2;
-        u32 if1_id1;
-        u32 if1_id2;
-        u32 if1_mcont;
-        u32 if1_dataa1;
-        u32 if1_dataa2;
-        u32 if1_datab1;
-        u32 if1_datab2;
-        u32 reserve2;
-        u32 reserve3[12];
-        u32 if2_creq;
-        u32 if2_cmask;
-        u32 if2_mask1;
-        u32 if2_mask2;
-        u32 if2_id1;
-        u32 if2_id2;
-        u32 if2_mcont;
-        u32 if2_dataa1;
-        u32 if2_dataa2;
-        u32 if2_datab1;
-        u32 if2_datab2;
-        u32 reserve4;
-        u32 reserve5[20];
+        u32 reserve;
+        struct pch_can_if_regs ifregs[2]; /* [0]=if1  [1]=if2 */
+        u32 reserve1[8];
         u32 treq1;
         u32 treq2;
-        u32 reserve6[2];
-        u32 reserve7[56];
-        u32 reserve8[3];
+        u32 reserve2[6];
+        u32 data1;
+        u32 data2;
+        u32 reserve3[6];
+        u32 canipend1;
+        u32 canipend2;
+        u32 reserve4[6];
+        u32 canmval1;
+        u32 canmval2;
+        u32 reserve5[37];
         u32 srst;
 };
 
 struct pch_can_priv {
         struct can_priv can;
-        unsigned int can_num;
         struct pci_dev *dev;
-        unsigned int tx_enable[MAX_MSG_OBJ];
-        unsigned int rx_enable[MAX_MSG_OBJ];
-        unsigned int rx_link[MAX_MSG_OBJ];
-        unsigned int int_enables;
-        unsigned int int_stat;
+        u32 tx_enable[PCH_TX_OBJ_END];
+        u32 rx_enable[PCH_TX_OBJ_END];
+        u32 rx_link[PCH_TX_OBJ_END];
+        u32 int_enables;
         struct net_device *ndev;
-        spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
-        unsigned int msg_obj[MAX_MSG_OBJ];
         struct pch_can_regs __iomem *regs;
         struct napi_struct napi;
-        unsigned int tx_obj;    /* Point next Tx Obj index */
-        unsigned int use_msi;
+        int tx_obj;     /* Point next Tx Obj index */
+        int use_msi;
 };
 
 static struct can_bittiming_const pch_can_bittiming_const = {
@@ -228,15 +216,15 @@ static void pch_can_set_run_mode(struct pch_can_priv *priv,
 {
         switch (mode) {
         case PCH_CAN_RUN:
-                pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_INIT);
+                pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
                 break;
 
         case PCH_CAN_STOP:
-                pch_can_bit_set(&priv->regs->cont, CAN_CTRL_INIT);
+                pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
                 break;
 
         default:
-                dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
+                netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
                 break;
         }
 }
@@ -246,357 +234,184 @@ static void pch_can_set_optmode(struct pch_can_priv *priv)
         u32 reg_val = ioread32(&priv->regs->opt);
 
         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
-                reg_val |= CAN_OPT_SILENT;
+                reg_val |= PCH_OPT_SILENT;
 
         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
-                reg_val |= CAN_OPT_LBACK;
+                reg_val |= PCH_OPT_LBACK;
 
-        pch_can_bit_set(&priv->regs->cont, CAN_CTRL_OPT);
+        pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
         iowrite32(reg_val, &priv->regs->opt);
 }
 
-static void pch_can_set_int_custom(struct pch_can_priv *priv)
+static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
 {
-        /* Clearing the IE, SIE and EIE bits of Can control register. */
-        pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
-
-        /* Appropriately setting them. */
-        pch_can_bit_set(&priv->regs->cont,
-                        ((priv->int_enables & MSK_CTRL_IE_SIE_EIE) << 1));
-}
+        int counter = PCH_COUNTER_LIMIT;
+        u32 ifx_creq;
 
-/* This function retrieves interrupt enabled for the CAN device. */
-static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
-{
-        /* Obtaining the status of IE, SIE and EIE interrupt bits. */
-        *enables = ((ioread32(&priv->regs->cont) & CAN_CTRL_IE_SIE_EIE) >> 1);
+        iowrite32(num, creq_addr);
+        while (counter) {
+                ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
+                if (!ifx_creq)
+                        break;
+                counter--;
+                udelay(1);
+        }
+        if (!counter)
+                pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
 }
 
 static void pch_can_set_int_enables(struct pch_can_priv *priv,
                                     enum pch_can_mode interrupt_no)
 {
         switch (interrupt_no) {
-        case PCH_CAN_ENABLE:
-                pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE);
-                break;
-
         case PCH_CAN_DISABLE:
-                pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE);
+                pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
                 break;
 
         case PCH_CAN_ALL:
-                pch_can_bit_set(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+                pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
                 break;
 
         case PCH_CAN_NONE:
-                pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_IE_SIE_EIE);
+                pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
                 break;
 
         default:
-                dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
+                netdev_err(priv->ndev, "Invalid interrupt number.\n");
                 break;
         }
 }
 
-static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
-{
-        u32 counter = COUNTER_LIMIT;
-        u32 ifx_creq;
-
-        iowrite32(num, creq_addr);
-        while (counter) {
-                ifx_creq = ioread32(creq_addr) & CAN_IF_CREQ_BUSY;
-                if (!ifx_creq)
-                        break;
-                counter--;
-                udelay(1);
-        }
-        if (!counter)
-                pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
-}
-
-static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
-                                  u32 set)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-        /* Reading the receive buffer data from RAM to Interface1 registers */
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
-        pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
-
-        /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
-        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
-                  &priv->regs->if1_cmask);
-
-        if (set == ENABLE) {
-                /* Setting the MsgVal and RxIE bits */
-                pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
-                pch_can_bit_set(&priv->regs->if1_id2, CAN_ID_MSGVAL);
-
-        } else if (set == DISABLE) {
-                /* Resetting the MsgVal and RxIE bits */
-                pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_RXIE);
-                pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID_MSGVAL);
-        }
-
-        pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-}
-
-static void pch_can_rx_enable_all(struct pch_can_priv *priv)
+static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
+                             int set, enum pch_ifreg dir)
 {
-        int i;
+        u32 ie;
 
-        /* Traversing to obtain the object configured as receivers. */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_RX)
-                        pch_can_set_rx_enable(priv, i + 1, ENABLE);
-        }
-}
+        if (dir)
+                ie = PCH_IF_MCONT_TXIE;
+        else
+                ie = PCH_IF_MCONT_RXIE;
 
-static void pch_can_rx_disable_all(struct pch_can_priv *priv)
-{
-        int i;
+        /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
+        iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
 
-        /* Traversing to obtain the object configured as receivers. */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_RX)
-                        pch_can_set_rx_enable(priv, i + 1, DISABLE);
-        }
-}
+        /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
+        iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
+                  &priv->regs->ifregs[dir].cmask);
 
-static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
-                                 u32 set)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-        /* Reading the Msg buffer from Message RAM to Interface2 registers. */
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
-        pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
-
-        /* Setting the IF2CMASK register for accessing the
-                MsgVal and TxIE bits */
-        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_ARB | CAN_CMASK_CTRL,
-                 &priv->regs->if2_cmask);
-
-        if (set == ENABLE) {
-                /* Setting the MsgVal and TxIE bits */
-                pch_can_bit_set(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
-                pch_can_bit_set(&priv->regs->if2_id2, CAN_ID_MSGVAL);
-        } else if (set == DISABLE) {
-                /* Resetting the MsgVal and TxIE bits. */
-                pch_can_bit_clear(&priv->regs->if2_mcont, CAN_IF_MCONT_TXIE);
-                pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID_MSGVAL);
+        if (set) {
+                /* Setting the MsgVal and RxIE/TxIE bits */
+                pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
+                pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
+        } else {
+                /* Clearing the MsgVal and RxIE/TxIE bits */
+                pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
+                pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
         }
 
-        pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
 }
 
-static void pch_can_tx_enable_all(struct pch_can_priv *priv)
+static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
 {
         int i;
 
-        /* Traversing to obtain the object configured as transmit object. */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_TX)
-                        pch_can_set_tx_enable(priv, i + 1, ENABLE);
-        }
+        /* Traversing to obtain the object configured as receivers. */
+        for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
+                pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
 }
 
-static void pch_can_tx_disable_all(struct pch_can_priv *priv)
+static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
 {
         int i;
 
         /* Traversing to obtain the object configured as transmit object. */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_TX)
-                        pch_can_set_tx_enable(priv, i + 1, DISABLE);
-        }
-}
-
-static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num,
-                                 u32 *enable)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
-        pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
-
-        if (((ioread32(&priv->regs->if1_id2)) & CAN_ID_MSGVAL) &&
-                        ((ioread32(&priv->regs->if1_mcont)) &
-                        CAN_IF_MCONT_RXIE))
-                *enable = ENABLE;
-        else
-                *enable = DISABLE;
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-}
-
-static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num,
-                                 u32 *enable)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
-        pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
-
-        if (((ioread32(&priv->regs->if2_id2)) & CAN_ID_MSGVAL) &&
-                        ((ioread32(&priv->regs->if2_mcont)) &
-                        CAN_IF_MCONT_TXIE)) {
-                *enable = ENABLE;
-        } else {
-                *enable = DISABLE;
-        }
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+        for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
+                pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
 }
 
-static int pch_can_int_pending(struct pch_can_priv *priv)
+static u32 pch_can_int_pending(struct pch_can_priv *priv)
 {
         return ioread32(&priv->regs->intr) & 0xffff;
 }
 
-static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
-                                       u32 buffer_num, u32 set)
+static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
 {
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
-        pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
-        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL, &priv->regs->if1_cmask);
-        if (set == ENABLE)
-                pch_can_bit_clear(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
-        else
-                pch_can_bit_set(&priv->regs->if1_mcont, CAN_IF_MCONT_EOB);
-
-        pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-}
-
-static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
-                                       u32 buffer_num, u32 *link)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
-        pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
-
-        if (ioread32(&priv->regs->if1_mcont) & CAN_IF_MCONT_EOB)
-                *link = DISABLE;
-        else
-                *link = ENABLE;
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-}
-
-static void pch_can_clear_buffers(struct pch_can_priv *priv)
-{
-        int i;
-
-        for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
-                iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
-                iowrite32(0xffff, &priv->regs->if1_mask1);
-                iowrite32(0xffff, &priv->regs->if1_mask2);
-                iowrite32(0x0, &priv->regs->if1_id1);
-                iowrite32(0x0, &priv->regs->if1_id2);
-                iowrite32(0x0, &priv->regs->if1_mcont);
-                iowrite32(0x0, &priv->regs->if1_dataa1);
-                iowrite32(0x0, &priv->regs->if1_dataa2);
-                iowrite32(0x0, &priv->regs->if1_datab1);
-                iowrite32(0x0, &priv->regs->if1_datab2);
-                iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
-                          CAN_CMASK_ARB | CAN_CMASK_CTRL,
-                          &priv->regs->if1_cmask);
-                pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
-        }
-
-        for (i = i;  i < PCH_OBJ_NUM; i++) {
-                iowrite32(CAN_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
-                iowrite32(0xffff, &priv->regs->if2_mask1);
-                iowrite32(0xffff, &priv->regs->if2_mask2);
-                iowrite32(0x0, &priv->regs->if2_id1);
-                iowrite32(0x0, &priv->regs->if2_id2);
-                iowrite32(0x0, &priv->regs->if2_mcont);
-                iowrite32(0x0, &priv->regs->if2_dataa1);
-                iowrite32(0x0, &priv->regs->if2_dataa2);
-                iowrite32(0x0, &priv->regs->if2_datab1);
-                iowrite32(0x0, &priv->regs->if2_datab2);
-                iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
-                          CAN_CMASK_ARB | CAN_CMASK_CTRL,
-                          &priv->regs->if2_cmask);
-                pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
+        int i; /* Msg Obj ID (1~32) */
+
+        for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
+                iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
+                iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
+                iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
+                iowrite32(0x0, &priv->regs->ifregs[0].id1);
+                iowrite32(0x0, &priv->regs->ifregs[0].id2);
+                iowrite32(0x0, &priv->regs->ifregs[0].mcont);
+                iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
+                iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
+                iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
+                iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
+                iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
+                          PCH_CMASK_ARB | PCH_CMASK_CTRL,
+                          &priv->regs->ifregs[0].cmask);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
         }
 }
 
 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
 {
         int i;
-        unsigned long flags;
 
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
+        for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
+                iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
 
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_RX) {
-                        iowrite32(CAN_CMASK_RX_TX_GET,
-                                &priv->regs->if1_cmask);
-                        pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
+                iowrite32(0x0, &priv->regs->ifregs[0].id1);
+                iowrite32(0x0, &priv->regs->ifregs[0].id2);
 
-                        iowrite32(0x0, &priv->regs->if1_id1);
-                        iowrite32(0x0, &priv->regs->if1_id2);
+                pch_can_bit_set(&priv->regs->ifregs[0].mcont,
+                                PCH_IF_MCONT_UMASK);
 
-                        pch_can_bit_set(&priv->regs->if1_mcont,
-                                        CAN_IF_MCONT_UMASK);
+                /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
+                if (i == PCH_RX_OBJ_END)
+                        pch_can_bit_set(&priv->regs->ifregs[0].mcont,
+                                        PCH_IF_MCONT_EOB);
+                else
+                        pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+                                          PCH_IF_MCONT_EOB);
 
-                        /* Set FIFO mode set to 0 except last Rx Obj*/
-                        pch_can_bit_clear(&priv->regs->if1_mcont,
-                                          CAN_IF_MCONT_EOB);
-                        /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
-                        if (i == (PCH_RX_OBJ_NUM - 1))
-                                pch_can_bit_set(&priv->regs->if1_mcont,
-                                                  CAN_IF_MCONT_EOB);
+                iowrite32(0, &priv->regs->ifregs[0].mask1);
+                pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
+                                  0x1fff | PCH_MASK2_MDIR_MXTD);
 
-                        iowrite32(0, &priv->regs->if1_mask1);
-                        pch_can_bit_clear(&priv->regs->if1_mask2,
-                                          0x1fff | CAN_MASK2_MDIR_MXTD);
+                /* Setting CMASK for writing */
+                iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
+                          PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
 
-                        /* Setting CMASK for writing */
-                        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
-                                  CAN_CMASK_ARB | CAN_CMASK_CTRL,
-                                  &priv->regs->if1_cmask);
-
-                        pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
-                } else if (priv->msg_obj[i] == MSG_OBJ_TX) {
-                        iowrite32(CAN_CMASK_RX_TX_GET,
-                                &priv->regs->if2_cmask);
-                        pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
+        }
 
-                        /* Resetting DIR bit for reception */
-                        iowrite32(0x0, &priv->regs->if2_id1);
-                        iowrite32(0x0, &priv->regs->if2_id2);
-                        pch_can_bit_set(&priv->regs->if2_id2, CAN_ID2_DIR);
+        for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
+                iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
 
-                        /* Setting EOB bit for transmitter */
-                        iowrite32(CAN_IF_MCONT_EOB, &priv->regs->if2_mcont);
+                /* Resetting DIR bit for reception */
+                iowrite32(0x0, &priv->regs->ifregs[1].id1);
+                iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
 
-                        pch_can_bit_set(&priv->regs->if2_mcont,
-                                        CAN_IF_MCONT_UMASK);
+                /* Setting EOB bit for transmitter */
+                iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
+                          &priv->regs->ifregs[1].mcont);
 
-                        iowrite32(0, &priv->regs->if2_mask1);
-                        pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
+                iowrite32(0, &priv->regs->ifregs[1].mask1);
+                pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
 
-                        /* Setting CMASK for writing */
-                        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_MASK |
-                                  CAN_CMASK_ARB | CAN_CMASK_CTRL,
-                                  &priv->regs->if2_cmask);
+                /* Setting CMASK for writing */
+                iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
+                          PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
 
-                        pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
-                }
+                pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
         }
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 }
 
 static void pch_can_init(struct pch_can_priv *priv)
@@ -605,7 +420,7 @@ static void pch_can_init(struct pch_can_priv *priv)
         pch_can_set_run_mode(priv, PCH_CAN_STOP);
 
         /* Clearing all the message object buffers. */
-        pch_can_clear_buffers(priv);
+        pch_can_clear_if_buffers(priv);
 
         /* Configuring the respective message object as either rx/tx object. */
         pch_can_config_rx_tx_buffers(priv);
@@ -623,57 +438,47 @@ static void pch_can_release(struct pch_can_priv *priv)
         pch_can_set_int_enables(priv, PCH_CAN_NONE);
 
         /* Disabling all the receive object. */
-        pch_can_rx_disable_all(priv);
+        pch_can_set_rx_all(priv, 0);
 
         /* Disabling all the transmit object. */
-        pch_can_tx_disable_all(priv);
+        pch_can_set_tx_all(priv, 0);
 }
 
 /* This function clears interrupt(s) from the CAN device. */
 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
 {
-        if (mask == CAN_STATUS_INT) {
-                ioread32(&priv->regs->stat);
-                return;
-        }
-
         /* Clear interrupt for transmit object */
-        if (priv->msg_obj[mask - 1] == MSG_OBJ_TX) {
-                /* Setting CMASK for clearing interrupts for
-                                         frame transmission. */
-                iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
-                          &priv->regs->if2_cmask);
-
-                /* Resetting the ID registers. */
-                pch_can_bit_set(&priv->regs->if2_id2,
-                               CAN_ID2_DIR | (0x7ff << 2));
-                iowrite32(0x0, &priv->regs->if2_id1);
-
-                /* Claring NewDat, TxRqst & IntPnd */
-                pch_can_bit_clear(&priv->regs->if2_mcont,
-                                  CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
-                                  CAN_IF_MCONT_TXRQXT);
-                pch_can_check_if_busy(&priv->regs->if2_creq, mask);
-        } else if (priv->msg_obj[mask - 1] == MSG_OBJ_RX) {
+        if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
                 /* Setting CMASK for clearing the reception interrupts. */
-                iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL | CAN_CMASK_ARB,
-                          &priv->regs->if1_cmask);
+                iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
+                          &priv->regs->ifregs[0].cmask);
 
                 /* Clearing the Dir bit. */
-                pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
+                pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
 
                 /* Clearing NewDat & IntPnd */
-                pch_can_bit_clear(&priv->regs->if1_mcont,
-                                  CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND);
+                pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+                                  PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
 
-                pch_can_check_if_busy(&priv->regs->if1_creq, mask);
-        }
-}
+                pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
+        } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
+                /*
+                 * Setting CMASK for clearing interrupts for frame transmission.
+                 */
+                iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
+                          &priv->regs->ifregs[1].cmask);
 
-static int pch_can_get_buffer_status(struct pch_can_priv *priv)
-{
-        return (ioread32(&priv->regs->treq1) & 0xffff) |
-               ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
+                /* Resetting the ID registers. */
+                pch_can_bit_set(&priv->regs->ifregs[1].id2,
+                               PCH_ID2_DIR | (0x7ff << 2));
+                iowrite32(0x0, &priv->regs->ifregs[1].id1);
+
+                /* Claring NewDat, TxRqst & IntPnd */
+                pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
+                                  PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
+                                  PCH_IF_MCONT_TXRQXT);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
+        }
 }
 
 static void pch_can_reset(struct pch_can_priv *priv)
@@ -688,7 +493,7 @@ static void pch_can_error(struct net_device *ndev, u32 status)
         struct sk_buff *skb;
         struct pch_can_priv *priv = netdev_priv(ndev);
         struct can_frame *cf;
-        u32 errc;
+        u32 errc, lec;
         struct net_device_stats *stats = &(priv->ndev->stats);
         enum can_state state = priv->can.state;
 
@@ -697,26 +502,24 @@ static void pch_can_error(struct net_device *ndev, u32 status)
                 return;
 
         if (status & PCH_BUS_OFF) {
-                pch_can_tx_disable_all(priv);
-                pch_can_rx_disable_all(priv);
+                pch_can_set_tx_all(priv, 0);
+                pch_can_set_rx_all(priv, 0);
                 state = CAN_STATE_BUS_OFF;
                 cf->can_id |= CAN_ERR_BUSOFF;
                 can_bus_off(ndev);
-                pch_can_set_run_mode(priv, PCH_CAN_RUN);
-                dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
         }
 
+        errc = ioread32(&priv->regs->errc);
         /* Warning interrupt. */
         if (status & PCH_EWARN) {
                 state = CAN_STATE_ERROR_WARNING;
                 priv->can.can_stats.error_warning++;
                 cf->can_id |= CAN_ERR_CRTL;
-                errc = ioread32(&priv->regs->errc);
-                if (((errc & CAN_REC) >> 8) > 96)
+                if (((errc & PCH_REC) >> 8) > 96)
                         cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
-                if ((errc & CAN_TEC) > 96)
+                if ((errc & PCH_TEC) > 96)
                         cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
-                dev_warn(&ndev->dev,
+                netdev_dbg(ndev,
                         "%s -> Error Counter is more than 96.\n", __func__);
         }
         /* Error passive interrupt. */
@@ -724,46 +527,52 @@ static void pch_can_error(struct net_device *ndev, u32 status)
                 priv->can.can_stats.error_passive++;
                 state = CAN_STATE_ERROR_PASSIVE;
                 cf->can_id |= CAN_ERR_CRTL;
-                errc = ioread32(&priv->regs->errc);
-                if (((errc & CAN_REC) >> 8) > 127)
+                if (((errc & PCH_REC) >> 8) > 127)
                         cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
-                if ((errc & CAN_TEC) > 127)
+                if ((errc & PCH_TEC) > 127)
                         cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
-                dev_err(&ndev->dev,
+                netdev_dbg(ndev,
                         "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
         }
 
-        if (status & PCH_LEC_ALL) {
+        lec = status & PCH_LEC_ALL;
+        switch (lec) {
+        case PCH_STUF_ERR:
+                cf->data[2] |= CAN_ERR_PROT_STUFF;
                 priv->can.can_stats.bus_error++;
                 stats->rx_errors++;
-                switch (status & PCH_LEC_ALL) {
-                case PCH_STUF_ERR:
-                        cf->data[2] |= CAN_ERR_PROT_STUFF;
-                        break;
-                case PCH_FORM_ERR:
-                        cf->data[2] |= CAN_ERR_PROT_FORM;
-                        break;
-                case PCH_ACK_ERR:
-                        cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
-                                       CAN_ERR_PROT_LOC_ACK_DEL;
-                        break;
-                case PCH_BIT1_ERR:
-                case PCH_BIT0_ERR:
-                        cf->data[2] |= CAN_ERR_PROT_BIT;
-                        break;
-                case PCH_CRC_ERR:
-                        cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
-                                       CAN_ERR_PROT_LOC_CRC_DEL;
-                        break;
-                default:
-                        iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
-                        break;
-                }
-
+                break;
+        case PCH_FORM_ERR:
+                cf->data[2] |= CAN_ERR_PROT_FORM;
+                priv->can.can_stats.bus_error++;
+                stats->rx_errors++;
+                break;
+        case PCH_ACK_ERR:
+                cf->can_id |= CAN_ERR_ACK;
+                priv->can.can_stats.bus_error++;
+                stats->rx_errors++;
+                break;
+        case PCH_BIT1_ERR:
+        case PCH_BIT0_ERR:
+                cf->data[2] |= CAN_ERR_PROT_BIT;
+                priv->can.can_stats.bus_error++;
+                stats->rx_errors++;
+                break;
+        case PCH_CRC_ERR:
+                cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
+                               CAN_ERR_PROT_LOC_CRC_DEL;
+                priv->can.can_stats.bus_error++;
+                stats->rx_errors++;
+                break;
+        case PCH_LEC_ALL: /* Written by CPU. No error status */
+                break;
         }
 
+        cf->data[6] = errc & PCH_TEC;
+        cf->data[7] = (errc & PCH_REC) >> 8;
+
         priv->can.state = state;
-        netif_rx(skb);
+        netif_receive_skb(skb);
 
         stats->rx_packets++;
         stats->rx_bytes += cf->can_dlc;
@@ -774,204 +583,202 @@ static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
         struct net_device *ndev = (struct net_device *)dev_id;
         struct pch_can_priv *priv = netdev_priv(ndev);
 
-        pch_can_set_int_enables(priv, PCH_CAN_NONE);
+        if (!pch_can_int_pending(priv))
+                return IRQ_NONE;
 
+        pch_can_set_int_enables(priv, PCH_CAN_NONE);
         napi_schedule(&priv->napi);
-
         return IRQ_HANDLED;
 }
 
-static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
+static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
+{
+        if (obj_id < PCH_FIFO_THRESH) {
+                iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
+                          PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
+
+                /* Clearing the Dir bit. */
+                pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
+
+                /* Clearing NewDat & IntPnd */
+                pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+                                  PCH_IF_MCONT_INTPND);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
+        } else if (obj_id > PCH_FIFO_THRESH) {
+                pch_can_int_clr(priv, obj_id);
+        } else if (obj_id == PCH_FIFO_THRESH) {
+                int cnt;
+                for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
+                        pch_can_int_clr(priv, cnt + 1);
+        }
+}
+
+static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
+{
+        struct pch_can_priv *priv = netdev_priv(ndev);
+        struct net_device_stats *stats = &(priv->ndev->stats);
+        struct sk_buff *skb;
+        struct can_frame *cf;
+
+        netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
+        pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+                          PCH_IF_MCONT_MSGLOST);
+        iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
+                  &priv->regs->ifregs[0].cmask);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
+
+        skb = alloc_can_err_skb(ndev, &cf);
+        if (!skb)
+                return;
+
+        cf->can_id |= CAN_ERR_CRTL;
+        cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
+        stats->rx_over_errors++;
+        stats->rx_errors++;
+
+        netif_receive_skb(skb);
+}
+
+static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
 {
         u32 reg;
         canid_t id;
-        u32 ide;
-        u32 rtr;
-        int i, j, k;
         int rcv_pkts = 0;
         struct sk_buff *skb;
         struct can_frame *cf;
         struct pch_can_priv *priv = netdev_priv(ndev);
         struct net_device_stats *stats = &(priv->ndev->stats);
+        int i;
+        u32 id2;
+        u16 data_reg;
+
+        do {
+                /* Reading the messsage object from the Message RAM */
+                iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+                pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
 
-        /* Reading the messsage object from the Message RAM */
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
-        pch_can_check_if_busy(&priv->regs->if1_creq, int_stat);
+                /* Reading the MCONT register. */
+                reg = ioread32(&priv->regs->ifregs[0].mcont);
 
-        /* Reading the MCONT register. */
-        reg = ioread32(&priv->regs->if1_mcont);
-        reg &= 0xffff;
+                if (reg & PCH_IF_MCONT_EOB)
+                        break;
 
-        for (k = int_stat; !(reg & CAN_IF_MCONT_EOB); k++) {
                 /* If MsgLost bit set. */
-                if (reg & CAN_IF_MCONT_MSGLOST) {
-                        dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
-                        pch_can_bit_clear(&priv->regs->if1_mcont,
-                                          CAN_IF_MCONT_MSGLOST);
-                        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL,
-                                  &priv->regs->if1_cmask);
-                        pch_can_check_if_busy(&priv->regs->if1_creq, k);
-
-                        skb = alloc_can_err_skb(ndev, &cf);
-                        if (!skb)
-                                return -ENOMEM;
-
-                        priv->can.can_stats.error_passive++;
-                        priv->can.state = CAN_STATE_ERROR_PASSIVE;
-                        cf->can_id |= CAN_ERR_CRTL;
-                        cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
-                        cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
-                        stats->rx_packets++;
-                        stats->rx_bytes += cf->can_dlc;
-
-                        netif_receive_skb(skb);
+                if (reg & PCH_IF_MCONT_MSGLOST) {
+                        pch_can_rx_msg_lost(ndev, obj_num);
                         rcv_pkts++;
-                        goto RX_NEXT;
+                        quota--;
+                        obj_num++;
+                        continue;
+                } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
+                        obj_num++;
+                        continue;
                 }
-                if (!(reg & CAN_IF_MCONT_NEWDAT))
-                        goto RX_NEXT;
 
                 skb = alloc_can_skb(priv->ndev, &cf);
-                if (!skb)
-                        return -ENOMEM;
+                if (!skb) {
+                        netdev_err(ndev, "alloc_can_skb Failed\n");
+                        return rcv_pkts;
+                }
 
                 /* Get Received data */
-                ide = ((ioread32(&priv->regs->if1_id2)) & CAN_ID2_XTD) >> 14;
-                if (ide) {
-                        id = (ioread32(&priv->regs->if1_id1) & 0xffff);
-                        id |= (((ioread32(&priv->regs->if1_id2)) &
-                                            0x1fff) << 16);
-                        cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+                id2 = ioread32(&priv->regs->ifregs[0].id2);
+                if (id2 & PCH_ID2_XTD) {
+                        id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
+                        id |= (((id2) & 0x1fff) << 16);
+                        cf->can_id = id | CAN_EFF_FLAG;
                 } else {
-                        id = (((ioread32(&priv->regs->if1_id2)) &
-                                          (CAN_SFF_MASK << 2)) >> 2);
-                        cf->can_id = (id & CAN_SFF_MASK);
+                        id = (id2 >> 2) & CAN_SFF_MASK;
+                        cf->can_id = id;
                 }
 
-                rtr = (ioread32(&priv->regs->if1_id2) &  CAN_ID2_DIR);
-                if (rtr) {
-                        cf->can_dlc = 0;
+                if (id2 & PCH_ID2_DIR)
                         cf->can_id |= CAN_RTR_FLAG;
-                } else {
-                        cf->can_dlc = ((ioread32(&priv->regs->if1_mcont)) &
-                                                   0x0f);
-                }
 
-                for (i = 0, j = 0; i < cf->can_dlc; j++) {
-                        reg = ioread32(&priv->regs->if1_dataa1 + j*4);
-                        cf->data[i++] = cpu_to_le32(reg & 0xff);
-                        if (i == cf->can_dlc)
-                                break;
-                        cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff);
+                cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
+                                                    ifregs[0].mcont)) & 0xF);
+
+                for (i = 0; i < cf->can_dlc; i += 2) {
+                        data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
+                        cf->data[i] = data_reg;
+                        cf->data[i + 1] = data_reg >> 8;
                 }
 
                 netif_receive_skb(skb);
                 rcv_pkts++;
                 stats->rx_packets++;
+                quota--;
                 stats->rx_bytes += cf->can_dlc;
 
-                if (k < PCH_FIFO_THRESH) {
-                        iowrite32(CAN_CMASK_RDWR | CAN_CMASK_CTRL |
-                                  CAN_CMASK_ARB, &priv->regs->if1_cmask);
-
-                        /* Clearing the Dir bit. */
-                        pch_can_bit_clear(&priv->regs->if1_id2, CAN_ID2_DIR);
-
-                        /* Clearing NewDat & IntPnd */
-                        pch_can_bit_clear(&priv->regs->if1_mcont,
-                                          CAN_IF_MCONT_INTPND);
-                        pch_can_check_if_busy(&priv->regs->if1_creq, k);
-                } else if (k > PCH_FIFO_THRESH) {
-                        pch_can_int_clr(priv, k);
-                } else if (k == PCH_FIFO_THRESH) {
-                        int cnt;
-                        for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
-                                pch_can_int_clr(priv, cnt+1);
-                }
-RX_NEXT:
-                /* Reading the messsage object from the Message RAM */
-                iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
-                pch_can_check_if_busy(&priv->regs->if1_creq, k + 1);
-                reg = ioread32(&priv->regs->if1_mcont);
-        }
+                pch_fifo_thresh(priv, obj_num);
+                obj_num++;
+        } while (quota > 0);
 
         return rcv_pkts;
 }
-static int pch_can_rx_poll(struct napi_struct *napi, int quota)
+
+static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
 {
-        struct net_device *ndev = napi->dev;
         struct pch_can_priv *priv = netdev_priv(ndev);
         struct net_device_stats *stats = &(priv->ndev->stats);
         u32 dlc;
+
+        can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
+        iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
+                  &priv->regs->ifregs[1].cmask);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
+        dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
+                          PCH_IF_MCONT_DLC);
+        stats->tx_bytes += dlc;
+        stats->tx_packets++;
+        if (int_stat == PCH_TX_OBJ_END)
+                netif_wake_queue(ndev);
+}
+
+static int pch_can_poll(struct napi_struct *napi, int quota)
+{
+        struct net_device *ndev = napi->dev;
+        struct pch_can_priv *priv = netdev_priv(ndev);
         u32 int_stat;
-        int rcv_pkts = 0;
         u32 reg_stat;
-        unsigned long flags;
+        int quota_save = quota;
 
         int_stat = pch_can_int_pending(priv);
         if (!int_stat)
-                return 0;
+                goto end;
 
-INT_STAT:
-        if (int_stat == CAN_STATUS_INT) {
+        if (int_stat == PCH_STATUS_INT) {
                 reg_stat = ioread32(&priv->regs->stat);
-                if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
-                        if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
-                                pch_can_error(ndev, reg_stat);
-                }
 
-                if (reg_stat & PCH_TX_OK) {
-                        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-                        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
-                        pch_can_check_if_busy(&priv->regs->if2_creq,
-                                               ioread32(&priv->regs->intr));
-                        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-                        pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
+                if ((reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) &&
+                   ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)) {
+                        pch_can_error(ndev, reg_stat);
+                        quota--;
                 }
 
-                if (reg_stat & PCH_RX_OK)
-                        pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
+                if (reg_stat & (PCH_TX_OK | PCH_RX_OK))
+                        pch_can_bit_clear(&priv->regs->stat,
+                                          reg_stat & (PCH_TX_OK | PCH_RX_OK));
 
                 int_stat = pch_can_int_pending(priv);
-                if (int_stat == CAN_STATUS_INT)
-                        goto INT_STAT;
         }
 
-MSG_OBJ:
-        if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
-                spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-                rcv_pkts = pch_can_rx_normal(ndev, int_stat);
-                spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-                if (rcv_pkts < 0)
-                        return 0;
-        } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
-                if (priv->msg_obj[int_stat - 1] == MSG_OBJ_TX) {
-                        /* Handle transmission interrupt */
-                        can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
-                        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-                        iowrite32(CAN_CMASK_RX_TX_GET | CAN_CMASK_CLRINTPND,
-                                  &priv->regs->if2_cmask);
-                        dlc = ioread32(&priv->regs->if2_mcont) &
-                                       CAN_IF_MCONT_DLC;
-                        pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
-                        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
-                        if (dlc > 8)
-                                dlc = 8;
-                        stats->tx_bytes += dlc;
-                        stats->tx_packets++;
-                }
-        }
+        if (quota == 0)
+                goto end;
 
-        int_stat = pch_can_int_pending(priv);
-        if (int_stat == CAN_STATUS_INT)
-                goto INT_STAT;
-        else if (int_stat >= 1 && int_stat <= 32)
-                goto MSG_OBJ;
+        if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
+                quota -= pch_can_rx_normal(ndev, int_stat, quota);
+        } else if ((int_stat >= PCH_TX_OBJ_START) &&
+                   (int_stat <= PCH_TX_OBJ_END)) {
+                /* Handle transmission interrupt */
+                pch_can_tx_complete(ndev, int_stat);
+        }
 
+end:
         napi_complete(napi);
         pch_can_set_int_enables(priv, PCH_CAN_ALL);
 
-        return rcv_pkts;
+        return quota_save - quota;
 }
 
 static int pch_set_bittiming(struct net_device *ndev)
@@ -980,20 +787,18 @@ static int pch_set_bittiming(struct net_device *ndev)
         const struct can_bittiming *bt = &priv->can.bittiming;
         u32 canbit;
         u32 bepe;
-        u32 brp;
 
         /* Setting the CCE bit for accessing the Can Timing register. */
-        pch_can_bit_set(&priv->regs->cont, CAN_CTRL_CCE);
-
-        brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
-        canbit = brp & MSK_BITT_BRP;
-        canbit |= (bt->sjw - 1) << BIT_BITT_SJW;
-        canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << BIT_BITT_TSEG1;
-        canbit |= (bt->phase_seg2 - 1) << BIT_BITT_TSEG2;
-        bepe = (brp & MSK_BRPE_BRPE) >> BIT_BRPE_BRPE;
+        pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
+
+        canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
+        canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
+        canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
+        canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
+        bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
         iowrite32(canbit, &priv->regs->bitt);
         iowrite32(bepe, &priv->regs->brpe);
-        pch_can_bit_clear(&priv->regs->cont, CAN_CTRL_CCE);
+        pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
 
         return 0;
 }
@@ -1008,8 +813,8 @@ static void pch_can_start(struct net_device *ndev)
         pch_set_bittiming(ndev);
         pch_can_set_optmode(priv);
 
-        pch_can_tx_enable_all(priv);
-        pch_can_rx_enable_all(priv);
+        pch_can_set_tx_all(priv, 1);
+        pch_can_set_rx_all(priv, 1);
 
         /* Setting the CAN to run mode. */
         pch_can_set_run_mode(priv, PCH_CAN_RUN);
@@ -1041,27 +846,18 @@ static int pch_can_open(struct net_device *ndev)
         struct pch_can_priv *priv = netdev_priv(ndev);
         int retval;
 
-        retval = pci_enable_msi(priv->dev);
-        if (retval) {
-                dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
-                priv->use_msi = 0;
-        } else {
-                dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
-                priv->use_msi = 1;
-        }
-
-        /* Regsitering the interrupt. */
+        /* Regstering the interrupt. */
         retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
                              ndev->name, ndev);
         if (retval) {
-                dev_err(&ndev->dev, "request_irq failed.\n");
+                netdev_err(ndev, "request_irq failed.\n");
                 goto req_irq_err;
         }
 
         /* Open common can device */
         retval = open_candev(ndev);
         if (retval) {
-                dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
+                netdev_err(ndev, "open_candev() failed %d\n", retval);
                 goto err_open_candev;
         }
 
@@ -1075,9 +871,6 @@ static int pch_can_open(struct net_device *ndev)
 err_open_candev:
         free_irq(priv->dev->irq, ndev);
 req_irq_err:
-        if (priv->use_msi)
-                pci_disable_msi(priv->dev);
-
         pch_can_release(priv);
 
         return retval;
@@ -1091,102 +884,65 @@ static int pch_close(struct net_device *ndev)
         napi_disable(&priv->napi);
         pch_can_release(priv);
         free_irq(priv->dev->irq, ndev);
-        if (priv->use_msi)
-                pci_disable_msi(priv->dev);
         close_candev(ndev);
         priv->can.state = CAN_STATE_STOPPED;
         return 0;
 }
 
-static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id)
-{
-        u32 buffer_status = 0;
-        struct pch_can_priv *priv = netdev_priv(ndev);
-
-        /* Getting the message object status. */
-        buffer_status = (u32) pch_can_get_buffer_status(priv);
-
-        return buffer_status & obj_id;
-}
-
-
 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
 {
-        int i, j;
-        unsigned long flags;
         struct pch_can_priv *priv = netdev_priv(ndev);
         struct can_frame *cf = (struct can_frame *)skb->data;
-        int tx_buffer_avail = 0;
+        int tx_obj_no;
+        int i;
+        u32 id2;
 
         if (can_dropped_invalid_skb(ndev, skb))
                 return NETDEV_TX_OK;
 
-        if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */
-                while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) <<
-                                           PCH_RX_OBJ_NUM)))
-                        udelay(500);
+        tx_obj_no = priv->tx_obj;
+        if (priv->tx_obj == PCH_TX_OBJ_END) {
+                if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
+                        netif_stop_queue(ndev);
 
-                priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
-                tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */
+                priv->tx_obj = PCH_TX_OBJ_START;
         } else {
-                tx_buffer_avail = priv->tx_obj;
+                priv->tx_obj++;
         }
-        priv->tx_obj++;
-
-        /* Attaining the lock. */
-        spin_lock_irqsave(&priv->msgif_reg_lock, flags);
-
-        /* Reading the Msg Obj from the Msg RAM to the Interface register. */
-        iowrite32(CAN_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
-        pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
 
         /* Setting the CMASK register. */
-        pch_can_bit_set(&priv->regs->if2_cmask, CAN_CMASK_ALL);
+        pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
 
         /* If ID extended is set. */
-        pch_can_bit_clear(&priv->regs->if2_id1, 0xffff);
-        pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | CAN_ID2_XTD);
         if (cf->can_id & CAN_EFF_FLAG) {
-                pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff);
-                pch_can_bit_set(&priv->regs->if2_id2,
-                                ((cf->can_id >> 16) & 0x1fff) | CAN_ID2_XTD);
+                iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
+                id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
         } else {
-                pch_can_bit_set(&priv->regs->if2_id1, 0);
-                pch_can_bit_set(&priv->regs->if2_id2,
-                                (cf->can_id & CAN_SFF_MASK) << 2);
+                iowrite32(0, &priv->regs->ifregs[1].id1);
+                id2 = (cf->can_id & CAN_SFF_MASK) << 2;
         }
 
-        /* If remote frame has to be transmitted.. */
-        if (cf->can_id & CAN_RTR_FLAG)
-                pch_can_bit_clear(&priv->regs->if2_id2, CAN_ID2_DIR);
+        id2 |= PCH_ID_MSGVAL;
 
-        for (i = 0, j = 0; i < cf->can_dlc; j++) {
-                iowrite32(le32_to_cpu(cf->data[i++]),
-                         (&priv->regs->if2_dataa1) + j*4);
-                if (i == cf->can_dlc)
-                        break;
-                iowrite32(le32_to_cpu(cf->data[i++] << 8),
-                         (&priv->regs->if2_dataa1) + j*4);
-        }
-
-        can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
+        /* If remote frame has to be transmitted.. */
+        if (!(cf->can_id & CAN_RTR_FLAG))
+                id2 |= PCH_ID2_DIR;
 
-        /* Updating the size of the data. */
-        pch_can_bit_clear(&priv->regs->if2_mcont, 0x0f);
-        pch_can_bit_set(&priv->regs->if2_mcont, cf->can_dlc);
+        iowrite32(id2, &priv->regs->ifregs[1].id2);
 
-        /* Clearing IntPend, NewDat & TxRqst */
-        pch_can_bit_clear(&priv->regs->if2_mcont,
-                          CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_INTPND |
-                          CAN_IF_MCONT_TXRQXT);
+        /* Copy data to register */
+        for (i = 0; i < cf->can_dlc; i += 2) {
+                iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
+                          &priv->regs->ifregs[1].data[i / 2]);
+        }
 
-        /* Setting NewDat, TxRqst bits */
-        pch_can_bit_set(&priv->regs->if2_mcont,
-                        CAN_IF_MCONT_NEWDAT | CAN_IF_MCONT_TXRQXT);
+        can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
 
-        pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
+        /* Set the size of the data. Update if2_mcont */
+        iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
+                  PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
 
-        spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
 
         return NETDEV_TX_OK;
 }
@@ -1203,21 +959,98 @@ static void __devexit pch_can_remove(struct pci_dev *pdev)
         struct pch_can_priv *priv = netdev_priv(ndev);
 
         unregister_candev(priv->ndev);
-        free_candev(priv->ndev);
         pci_iounmap(pdev, priv->regs);
+        if (priv->use_msi)
+                pci_disable_msi(priv->dev);
         pci_release_regions(pdev);
         pci_disable_device(pdev);
         pci_set_drvdata(pdev, NULL);
         pch_can_reset(priv);
+        free_candev(priv->ndev);
 }
 
 #ifdef CONFIG_PM
+static void pch_can_set_int_custom(struct pch_can_priv *priv)
+{
+        /* Clearing the IE, SIE and EIE bits of Can control register. */
+        pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
+
+        /* Appropriately setting them. */
+        pch_can_bit_set(&priv->regs->cont,
+                        ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
+}
+
+/* This function retrieves interrupt enabled for the CAN device. */
+static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
+{
+        /* Obtaining the status of IE, SIE and EIE interrupt bits. */
+        return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
+}
+
+static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
+                               enum pch_ifreg dir)
+{
+        u32 ie, enable;
+
+        if (dir)
+                ie = PCH_IF_MCONT_RXIE;
+        else
+                ie = PCH_IF_MCONT_TXIE;
+
+        iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
+
+        if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
+                        ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
+                enable = 1;
+        else
+                enable = 0;
+
+        return enable;
+}
+
+static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
+                                       u32 buffer_num, int set)
+{
+        iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
+        iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
+                  &priv->regs->ifregs[0].cmask);
+        if (set)
+                pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
+                                  PCH_IF_MCONT_EOB);
+        else
+                pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
+
+        pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
+}
+
+static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
+{
+        u32 link;
+
+        iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
+        pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
+
+        if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
+                link = 0;
+        else
+                link = 1;
+        return link;
+}
+
+static int pch_can_get_buffer_status(struct pch_can_priv *priv)
+{
+        return (ioread32(&priv->regs->treq1) & 0xffff) |
+               (ioread32(&priv->regs->treq2) << 16);
+}
+
 static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
 {
-        int i;                  /* Counter variable. */
-        int retval;             /* Return value. */
+        int i;
+        int retval;
         u32 buf_stat;   /* Variable for reading the transmit buffer status. */
-        u32 counter = 0xFFFFFF;
+        int counter = PCH_COUNTER_LIMIT;
 
         struct net_device *dev = pci_get_drvdata(pdev);
         struct pch_can_priv *priv = netdev_priv(dev);
@@ -1226,7 +1059,7 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
         pch_can_set_run_mode(priv, PCH_CAN_STOP);
 
         /* Indicate that we are aboutto/in suspend */
-        priv->can.state = CAN_STATE_SLEEPING;
+        priv->can.state = CAN_STATE_STOPPED;
 
         /* Waiting for all transmission to complete. */
         while (counter) {
@@ -1240,31 +1073,26 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
                 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
 
         /* Save interrupt configuration and then disable them */
-        pch_can_get_int_enables(priv, &(priv->int_enables));
+        priv->int_enables = pch_can_get_int_enables(priv);
         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
 
         /* Save Tx buffer enable state */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_TX)
-                        pch_can_get_tx_enable(priv, i + 1,
-                                              &(priv->tx_enable[i]));
-        }
+        for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
+                priv->tx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
+                                                             PCH_TX_IFREG);
 
         /* Disable all Transmit buffers */
-        pch_can_tx_disable_all(priv);
+        pch_can_set_tx_all(priv, 0);
 
         /* Save Rx buffer enable state */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_RX) {
-                        pch_can_get_rx_enable(priv, i + 1,
-                                                &(priv->rx_enable[i]));
-                        pch_can_get_rx_buffer_link(priv, i + 1,
-                                                &(priv->rx_link[i]));
-                }
+        for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
+                priv->rx_enable[i - 1] = pch_can_get_rxtx_ir(priv, i,
+                                                             PCH_RX_IFREG);
+                priv->rx_link[i - 1] = pch_can_get_rx_buffer_link(priv, i);
         }
 
         /* Disable all Receive buffers */
-        pch_can_rx_disable_all(priv);
+        pch_can_set_rx_all(priv, 0);
         retval = pci_save_state(pdev);
         if (retval) {
                 dev_err(&pdev->dev, "pci_save_state failed.\n");
@@ -1279,8 +1107,8 @@ static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
 
 static int pch_can_resume(struct pci_dev *pdev)
 {
-        int i;                  /* Counter variable. */
-        int retval;             /* Return variable. */
+        int i;
+        int retval;
         struct net_device *dev = pci_get_drvdata(pdev);
         struct pch_can_priv *priv = netdev_priv(dev);
 
@@ -1312,23 +1140,16 @@ static int pch_can_resume(struct pci_dev *pdev)
         pch_can_set_optmode(priv);
 
         /* Enabling the transmit buffer. */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_TX) {
-                        pch_can_set_tx_enable(priv, i + 1,
-                                              priv->tx_enable[i]);
-                }
-        }
+        for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
+                pch_can_set_rxtx(priv, i, priv->tx_enable[i - 1], PCH_TX_IFREG);
 
         /* Configuring the receive buffer and enabling them. */
-        for (i = 0; i < PCH_OBJ_NUM; i++) {
-                if (priv->msg_obj[i] == MSG_OBJ_RX) {
-                        /* Restore buffer link */
-                        pch_can_set_rx_buffer_link(priv, i + 1,
-                                                   priv->rx_link[i]);
-
-                        /* Restore buffer enables */
-                        pch_can_set_rx_enable(priv, i + 1, priv->rx_enable[i]);
-                }
+        for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
+                /* Restore buffer link */
+                pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i - 1]);
+
+                /* Restore buffer enables */
+                pch_can_set_rxtx(priv, i, priv->rx_enable[i - 1], PCH_RX_IFREG);
         }
 
         /* Enable CAN Interrupts */
@@ -1348,9 +1169,10 @@ static int pch_can_get_berr_counter(const struct net_device *dev,
                                     struct can_berr_counter *bec)
 {
         struct pch_can_priv *priv = netdev_priv(dev);
+        u32 errc = ioread32(&priv->regs->errc);
 
-        bec->txerr = ioread32(&priv->regs->errc) & CAN_TEC;
-        bec->rxerr = (ioread32(&priv->regs->errc) & CAN_REC) >> 8;
+        bec->txerr = errc & PCH_TEC;
+        bec->rxerr = (errc & PCH_REC) >> 8;
 
         return 0;
 }
@@ -1361,7 +1183,6 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
         struct net_device *ndev;
         struct pch_can_priv *priv;
         int rc;
-        int index;
         void __iomem *addr;
 
         rc = pci_enable_device(pdev);
@@ -1383,7 +1204,7 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
                 goto probe_exit_ipmap;
         }
 
-        ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
+        ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
         if (!ndev) {
                 rc = -ENOMEM;
                 dev_err(&pdev->dev, "Failed alloc_candev\n");
@@ -1399,7 +1220,7 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
         priv->can.do_get_berr_counter = pch_can_get_berr_counter;
         priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
                                        CAN_CTRLMODE_LOOPBACK;
-        priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
+        priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
 
         ndev->irq = pdev->irq;
         ndev->flags |= IFF_ECHO;
@@ -1407,15 +1228,18 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
         pci_set_drvdata(pdev, ndev);
         SET_NETDEV_DEV(ndev, &pdev->dev);
         ndev->netdev_ops = &pch_can_netdev_ops;
-
         priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
-        for (index = 0; index < PCH_RX_OBJ_NUM;)
-                priv->msg_obj[index++] = MSG_OBJ_RX;
 
-        for (index = index;  index < PCH_OBJ_NUM;)
-                priv->msg_obj[index++] = MSG_OBJ_TX;
+        netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
 
-        netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
+        rc = pci_enable_msi(priv->dev);
+        if (rc) {
+                netdev_err(ndev, "PCH CAN opened without MSI\n");
+                priv->use_msi = 0;
+        } else {
+                netdev_err(ndev, "PCH CAN opened with MSI\n");
+                priv->use_msi = 1;
+        }
 
         rc = register_candev(ndev);
         if (rc) {
@@ -1426,6 +1250,8 @@ static int __devinit pch_can_probe(struct pci_dev *pdev,
         return 0;
 
 probe_exit_reg_candev:
+        if (priv->use_msi)
+                pci_disable_msi(priv->dev);
         free_candev(ndev);
 probe_exit_alloc_candev:
         pci_iounmap(pdev, addr);
@@ -1458,6 +1284,6 @@ static void __exit pch_can_pci_exit(void)
 }
 module_exit(pch_can_pci_exit);
 
-MODULE_DESCRIPTION("Controller Area Network Driver");
+MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
 MODULE_LICENSE("GPL v2");
 MODULE_VERSION("0.94");
diff --git a/drivers/net/can/sja1000/plx_pci.c b/drivers/net/can/sja1000/plx_pci.c
index 437b5c716a24..231385b8e08f 100644
--- a/drivers/net/can/sja1000/plx_pci.c
+++ b/drivers/net/can/sja1000/plx_pci.c
@@ -383,7 +383,7 @@ static void plx_pci_reset_marathon(struct pci_dev *pdev)
 {
         void __iomem *reset_addr;
         int i;
-        int reset_bar[2] = {3, 5};
+        static const int reset_bar[2] = {3, 5};
 
         plx_pci_reset_common(pdev);
 
diff --git a/drivers/net/can/sja1000/sja1000_of_platform.c b/drivers/net/can/sja1000/sja1000_of_platform.c
index 5bfccfdf3bbb..09c3e9db9316 100644
--- a/drivers/net/can/sja1000/sja1000_of_platform.c
+++ b/drivers/net/can/sja1000/sja1000_of_platform.c
@@ -107,17 +107,13 @@ static int __devinit sja1000_ofp_probe(struct platform_device *ofdev,
         res_size = resource_size(&res);
 
         if (!request_mem_region(res.start, res_size, DRV_NAME)) {
-                dev_err(&ofdev->dev, "couldn't request %#llx..%#llx\n",
-                        (unsigned long long)res.start,
-                        (unsigned long long)res.end);
+                dev_err(&ofdev->dev, "couldn't request %pR\n", &res);
                 return -EBUSY;
         }
 
         base = ioremap_nocache(res.start, res_size);
         if (!base) {
-                dev_err(&ofdev->dev, "couldn't ioremap %#llx..%#llx\n",
-                        (unsigned long long)res.start,
-                        (unsigned long long)res.end);
+                dev_err(&ofdev->dev, "couldn't ioremap %pR\n", &res);
                 err = -ENOMEM;
                 goto exit_release_mem;
         }
diff --git a/drivers/net/can/slcan.c b/drivers/net/can/slcan.c
new file mode 100644
index 000000000000..b423965a78d1
--- /dev/null
+++ b/drivers/net/can/slcan.c
@@ -0,0 +1,756 @@
+/*
+ * slcan.c - serial line CAN interface driver (using tty line discipline)
+ *
+ * This file is derived from linux/drivers/net/slip.c
+ *
+ * slip.c Authors  : Laurence Culhane <loz@holmes.demon.co.uk>
+ *                   Fred N. van Kempen <waltje@uwalt.nl.mugnet.org>
+ * slcan.c Author  : Oliver Hartkopp <socketcan@hartkopp.net>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307. You can also get it
+ * at http://www.gnu.org/licenses/gpl.html
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * Send feedback to <socketcan-users@lists.berlios.de>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#include <asm/system.h>
+#include <linux/uaccess.h>
+#include <linux/bitops.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/errno.h>
+#include <linux/netdevice.h>
+#include <linux/skbuff.h>
+#include <linux/rtnetlink.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/can.h>
+
+static __initdata const char banner[] =
+        KERN_INFO "slcan: serial line CAN interface driver\n";
+
+MODULE_ALIAS_LDISC(N_SLCAN);
+MODULE_DESCRIPTION("serial line CAN interface");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Oliver Hartkopp <socketcan@hartkopp.net>");
+
+#define SLCAN_MAGIC 0x53CA
+
+static int maxdev = 10;         /* MAX number of SLCAN channels;
+                                   This can be overridden with
+                                   insmod slcan.ko maxdev=nnn   */
+module_param(maxdev, int, 0);
+MODULE_PARM_DESC(maxdev, "Maximum number of slcan interfaces");
+
+/* maximum rx buffer len: extended CAN frame with timestamp */
+#define SLC_MTU (sizeof("T1111222281122334455667788EA5F\r")+1)
+
+struct slcan {
+        int                     magic;
+
+        /* Various fields. */
+        struct tty_struct       *tty;           /* ptr to TTY structure      */
+        struct net_device       *dev;           /* easy for intr handling    */
+        spinlock_t              lock;
+
+        /* These are pointers to the malloc()ed frame buffers. */
+        unsigned char           rbuff[SLC_MTU]; /* receiver buffer           */
+        int                     rcount;         /* received chars counter    */
+        unsigned char           xbuff[SLC_MTU]; /* transmitter buffer        */
+        unsigned char           *xhead;         /* pointer to next XMIT byte */
+        int                     xleft;          /* bytes left in XMIT queue  */
+
+        unsigned long           flags;          /* Flag values/ mode etc     */
+#define SLF_INUSE               0               /* Channel in use            */
+#define SLF_ERROR               1               /* Parity, etc. error        */
+
+        unsigned char           leased;
+        dev_t                   line;
+        pid_t                   pid;
+};
+
+static struct net_device **slcan_devs;
+
+ /************************************************************************
+  *                     SLCAN ENCAPSULATION FORMAT                       *
+  ************************************************************************/
+
+/*
+ * A CAN frame has a can_id (11 bit standard frame format OR 29 bit extended
+ * frame format) a data length code (can_dlc) which can be from 0 to 8
+ * and up to <can_dlc> data bytes as payload.
+ * Additionally a CAN frame may become a remote transmission frame if the
+ * RTR-bit is set. This causes another ECU to send a CAN frame with the
+ * given can_id.
+ *
+ * The SLCAN ASCII representation of these different frame types is:
+ * <type> <id> <dlc> <data>*
+ *
+ * Extended frames (29 bit) are defined by capital characters in the type.
+ * RTR frames are defined as 'r' types - normal frames have 't' type:
+ * t => 11 bit data frame
+ * r => 11 bit RTR frame
+ * T => 29 bit data frame
+ * R => 29 bit RTR frame
+ *
+ * The <id> is 3 (standard) or 8 (extended) bytes in ASCII Hex (base64).
+ * The <dlc> is a one byte ASCII number ('0' - '8')
+ * The <data> section has at much ASCII Hex bytes as defined by the <dlc>
+ *
+ * Examples:
+ *
+ * t1230 : can_id 0x123, can_dlc 0, no data
+ * t4563112233 : can_id 0x456, can_dlc 3, data 0x11 0x22 0x33
+ * T12ABCDEF2AA55 : extended can_id 0x12ABCDEF, can_dlc 2, data 0xAA 0x55
+ * r1230 : can_id 0x123, can_dlc 0, no data, remote transmission request
+ *
+ */
+
+ /************************************************************************
+  *                     STANDARD SLCAN DECAPSULATION                     *
+  ************************************************************************/
+
+static int asc2nibble(char c)
+{
+
+        if ((c >= '0') && (c <= '9'))
+                return c - '0';
+
+        if ((c >= 'A') && (c <= 'F'))
+                return c - 'A' + 10;
+
+        if ((c >= 'a') && (c <= 'f'))
+                return c - 'a' + 10;
+
+        return 16; /* error */
+}
+
+/* Send one completely decapsulated can_frame to the network layer */
+static void slc_bump(struct slcan *sl)
+{
+        struct sk_buff *skb;
+        struct can_frame cf;
+        int i, dlc_pos, tmp;
+        unsigned long ultmp;
+        char cmd = sl->rbuff[0];
+
+        if ((cmd != 't') && (cmd != 'T') && (cmd != 'r') && (cmd != 'R'))
+                return;
+
+        if (cmd & 0x20) /* tiny chars 'r' 't' => standard frame format */
+                dlc_pos = 4; /* dlc position tiiid */
+        else
+                dlc_pos = 9; /* dlc position Tiiiiiiiid */
+
+        if (!((sl->rbuff[dlc_pos] >= '0') && (sl->rbuff[dlc_pos] < '9')))
+                return;
+
+        cf.can_dlc = sl->rbuff[dlc_pos] - '0'; /* get can_dlc from ASCII val */
+
+        sl->rbuff[dlc_pos] = 0; /* terminate can_id string */
+
+        if (strict_strtoul(sl->rbuff+1, 16, &ultmp))
+                return;
+
+        cf.can_id = ultmp;
+
+        if (!(cmd & 0x20)) /* NO tiny chars => extended frame format */
+                cf.can_id |= CAN_EFF_FLAG;
+
+        if ((cmd | 0x20) == 'r') /* RTR frame */
+                cf.can_id |= CAN_RTR_FLAG;
+
+        *(u64 *) (&cf.data) = 0; /* clear payload */
+
+        for (i = 0, dlc_pos++; i < cf.can_dlc; i++) {
+
+                tmp = asc2nibble(sl->rbuff[dlc_pos++]);
+                if (tmp > 0x0F)
+                        return;
+                cf.data[i] = (tmp << 4);
+                tmp = asc2nibble(sl->rbuff[dlc_pos++]);
+                if (tmp > 0x0F)
+                        return;
+                cf.data[i] |= tmp;
+        }
+
+
+        skb = dev_alloc_skb(sizeof(struct can_frame));
+        if (!skb)
+                return;
+
+        skb->dev = sl->dev;
+        skb->protocol = htons(ETH_P_CAN);
+        skb->pkt_type = PACKET_BROADCAST;
+        skb->ip_summed = CHECKSUM_UNNECESSARY;
+        memcpy(skb_put(skb, sizeof(struct can_frame)),
+               &cf, sizeof(struct can_frame));
+        netif_rx(skb);
+
+        sl->dev->stats.rx_packets++;
+        sl->dev->stats.rx_bytes += cf.can_dlc;
+}
+
+/* parse tty input stream */
+static void slcan_unesc(struct slcan *sl, unsigned char s)
+{
+
+        if ((s == '\r') || (s == '\a')) { /* CR or BEL ends the pdu */
+                if (!test_and_clear_bit(SLF_ERROR, &sl->flags) &&
+                    (sl->rcount > 4))  {
+                        slc_bump(sl);
+                }
+                sl->rcount = 0;
+        } else {
+                if (!test_bit(SLF_ERROR, &sl->flags))  {
+                        if (sl->rcount < SLC_MTU)  {
+                                sl->rbuff[sl->rcount++] = s;
+                                return;
+                        } else {
+                                sl->dev->stats.rx_over_errors++;
+                                set_bit(SLF_ERROR, &sl->flags);
+                        }
+                }
+        }
+}
+
+ /************************************************************************
+  *                     STANDARD SLCAN ENCAPSULATION                     *
+  ************************************************************************/
+
+/* Encapsulate one can_frame and stuff into a TTY queue. */
+static void slc_encaps(struct slcan *sl, struct can_frame *cf)
+{
+        int actual, idx, i;
+        char cmd;
+
+        if (cf->can_id & CAN_RTR_FLAG)
+                cmd = 'R'; /* becomes 'r' in standard frame format */
+        else
+                cmd = 'T'; /* becomes 't' in standard frame format */
+
+        if (cf->can_id & CAN_EFF_FLAG)
+                sprintf(sl->xbuff, "%c%08X%d", cmd,
+                        cf->can_id & CAN_EFF_MASK, cf->can_dlc);
+        else
+                sprintf(sl->xbuff, "%c%03X%d", cmd | 0x20,
+                        cf->can_id & CAN_SFF_MASK, cf->can_dlc);
+
+        idx = strlen(sl->xbuff);
+
+        for (i = 0; i < cf->can_dlc; i++)
+                sprintf(&sl->xbuff[idx + 2*i], "%02X", cf->data[i]);
+
+        strcat(sl->xbuff, "\r"); /* add terminating character */
+
+        /* Order of next two lines is *very* important.
+         * When we are sending a little amount of data,
+         * the transfer may be completed inside the ops->write()
+         * routine, because it's running with interrupts enabled.
+         * In this case we *never* got WRITE_WAKEUP event,
+         * if we did not request it before write operation.
+         *       14 Oct 1994  Dmitry Gorodchanin.
+         */
+        set_bit(TTY_DO_WRITE_WAKEUP, &sl->tty->flags);
+        actual = sl->tty->ops->write(sl->tty, sl->xbuff, strlen(sl->xbuff));
+        sl->xleft = strlen(sl->xbuff) - actual;
+        sl->xhead = sl->xbuff + actual;
+        sl->dev->stats.tx_bytes += cf->can_dlc;
+}
+
+/*
+ * Called by the driver when there's room for more data.  If we have
+ * more packets to send, we send them here.
+ */
+static void slcan_write_wakeup(struct tty_struct *tty)
+{
+        int actual;
+        struct slcan *sl = (struct slcan *) tty->disc_data;
+
+        /* First make sure we're connected. */
+        if (!sl || sl->magic != SLCAN_MAGIC || !netif_running(sl->dev))
+                return;
+
+        if (sl->xleft <= 0)  {
+                /* Now serial buffer is almost free & we can start
+                 * transmission of another packet */
+                sl->dev->stats.tx_packets++;
+                clear_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+                netif_wake_queue(sl->dev);
+                return;
+        }
+
+        actual = tty->ops->write(tty, sl->xhead, sl->xleft);
+        sl->xleft -= actual;
+        sl->xhead += actual;
+}
+
+/* Send a can_frame to a TTY queue. */
+static netdev_tx_t slc_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+        struct slcan *sl = netdev_priv(dev);
+
+        if (skb->len != sizeof(struct can_frame))
+                goto out;
+
+        spin_lock(&sl->lock);
+        if (!netif_running(dev))  {
+                spin_unlock(&sl->lock);
+                printk(KERN_WARNING "%s: xmit: iface is down\n", dev->name);
+                goto out;
+        }
+        if (sl->tty == NULL) {
+                spin_unlock(&sl->lock);
+                goto out;
+        }
+
+        netif_stop_queue(sl->dev);
+        slc_encaps(sl, (struct can_frame *) skb->data); /* encaps & send */
+        spin_unlock(&sl->lock);
+
+out:
+        kfree_skb(skb);
+        return NETDEV_TX_OK;
+}
+
+
+/******************************************
+ *   Routines looking at netdevice side.
+ ******************************************/
+
+/* Netdevice UP -> DOWN routine */
+static int slc_close(struct net_device *dev)
+{
+        struct slcan *sl = netdev_priv(dev);
+
+        spin_lock_bh(&sl->lock);
+        if (sl->tty) {
+                /* TTY discipline is running. */
+                clear_bit(TTY_DO_WRITE_WAKEUP, &sl->tty->flags);
+        }
+        netif_stop_queue(dev);
+        sl->rcount   = 0;
+        sl->xleft    = 0;
+        spin_unlock_bh(&sl->lock);
+
+        return 0;
+}
+
+/* Netdevice DOWN -> UP routine */
+static int slc_open(struct net_device *dev)
+{
+        struct slcan *sl = netdev_priv(dev);
+
+        if (sl->tty == NULL)
+                return -ENODEV;
+
+        sl->flags &= (1 << SLF_INUSE);
+        netif_start_queue(dev);
+        return 0;
+}
+
+/* Hook the destructor so we can free slcan devs at the right point in time */
+static void slc_free_netdev(struct net_device *dev)
+{
+        int i = dev->base_addr;
+        free_netdev(dev);
+        slcan_devs[i] = NULL;
+}
+
+static const struct net_device_ops slc_netdev_ops = {
+        .ndo_open               = slc_open,
+        .ndo_stop               = slc_close,
+        .ndo_start_xmit         = slc_xmit,
+};
+
+static void slc_setup(struct net_device *dev)
+{
+        dev->netdev_ops         = &slc_netdev_ops;
+        dev->destructor         = slc_free_netdev;
+
+        dev->hard_header_len    = 0;
+        dev->addr_len           = 0;
+        dev->tx_queue_len       = 10;
+
+        dev->mtu                = sizeof(struct can_frame);
+        dev->type               = ARPHRD_CAN;
+
+        /* New-style flags. */
+        dev->flags              = IFF_NOARP;
+        dev->features           = NETIF_F_NO_CSUM;
+}
+
+/******************************************
+  Routines looking at TTY side.
+ ******************************************/
+
+/*
+ * Handle the 'receiver data ready' interrupt.
+ * This function is called by the 'tty_io' module in the kernel when
+ * a block of SLCAN data has been received, which can now be decapsulated
+ * and sent on to some IP layer for further processing. This will not
+ * be re-entered while running but other ldisc functions may be called
+ * in parallel
+ */
+
+static void slcan_receive_buf(struct tty_struct *tty,
+                              const unsigned char *cp, char *fp, int count)
+{
+        struct slcan *sl = (struct slcan *) tty->disc_data;
+
+        if (!sl || sl->magic != SLCAN_MAGIC || !netif_running(sl->dev))
+                return;
+
+        /* Read the characters out of the buffer */
+        while (count--) {
+                if (fp && *fp++) {
+                        if (!test_and_set_bit(SLF_ERROR, &sl->flags))
+                                sl->dev->stats.rx_errors++;
+                        cp++;
+                        continue;
+                }
+                slcan_unesc(sl, *cp++);
+        }
+}
+
+/************************************
+ *  slcan_open helper routines.
+ ************************************/
+
+/* Collect hanged up channels */
+static void slc_sync(void)
+{
+        int i;
+        struct net_device *dev;
+        struct slcan      *sl;
+
+        for (i = 0; i < maxdev; i++) {
+                dev = slcan_devs[i];
+                if (dev == NULL)
+                        break;
+
+                sl = netdev_priv(dev);
+                if (sl->tty || sl->leased)
+                        continue;
+                if (dev->flags & IFF_UP)
+                        dev_close(dev);
+        }
+}
+
+/* Find a free SLCAN channel, and link in this `tty' line. */
+static struct slcan *slc_alloc(dev_t line)
+{
+        int i;
+        struct net_device *dev = NULL;
+        struct slcan       *sl;
+
+        if (slcan_devs == NULL)
+                return NULL;    /* Master array missing ! */
+
+        for (i = 0; i < maxdev; i++) {
+                dev = slcan_devs[i];
+                if (dev == NULL)
+                        break;
+
+        }
+
+        /* Sorry, too many, all slots in use */
+        if (i >= maxdev)
+                return NULL;
+
+        if (dev) {
+                sl = netdev_priv(dev);
+                if (test_bit(SLF_INUSE, &sl->flags)) {
+                        unregister_netdevice(dev);
+                        dev = NULL;
+                        slcan_devs[i] = NULL;
+                }
+        }
+
+        if (!dev) {
+                char name[IFNAMSIZ];
+                sprintf(name, "slcan%d", i);
+
+                dev = alloc_netdev(sizeof(*sl), name, slc_setup);
+                if (!dev)
+                        return NULL;
+                dev->base_addr  = i;
+        }
+
+        sl = netdev_priv(dev);
+
+        /* Initialize channel control data */
+        sl->magic = SLCAN_MAGIC;
+        sl->dev = dev;
+        spin_lock_init(&sl->lock);
+        slcan_devs[i] = dev;
+
+        return sl;
+}
+
+/*
+ * Open the high-level part of the SLCAN channel.
+ * This function is called by the TTY module when the
+ * SLCAN line discipline is called for.  Because we are
+ * sure the tty line exists, we only have to link it to
+ * a free SLCAN channel...
+ *
+ * Called in process context serialized from other ldisc calls.
+ */
+
+static int slcan_open(struct tty_struct *tty)
+{
+        struct slcan *sl;
+        int err;
+
+        if (!capable(CAP_NET_ADMIN))
+                return -EPERM;
+
+        if (tty->ops->write == NULL)
+                return -EOPNOTSUPP;
+
+        /* RTnetlink lock is misused here to serialize concurrent
+           opens of slcan channels. There are better ways, but it is
+           the simplest one.
+         */
+        rtnl_lock();
+
+        /* Collect hanged up channels. */
+        slc_sync();
+
+        sl = tty->disc_data;
+
+        err = -EEXIST;
+        /* First make sure we're not already connected. */
+        if (sl && sl->magic == SLCAN_MAGIC)
+                goto err_exit;
+
+        /* OK.  Find a free SLCAN channel to use. */
+        err = -ENFILE;
+        sl = slc_alloc(tty_devnum(tty));
+        if (sl == NULL)
+                goto err_exit;
+
+        sl->tty = tty;
+        tty->disc_data = sl;
+        sl->line = tty_devnum(tty);
+        sl->pid = current->pid;
+
+        if (!test_bit(SLF_INUSE, &sl->flags)) {
+                /* Perform the low-level SLCAN initialization. */
+                sl->rcount   = 0;
+                sl->xleft    = 0;
+
+                set_bit(SLF_INUSE, &sl->flags);
+
+                err = register_netdevice(sl->dev);
+                if (err)
+                        goto err_free_chan;
+        }
+
+        /* Done.  We have linked the TTY line to a channel. */
+        rtnl_unlock();
+        tty->receive_room = 65536;      /* We don't flow control */
+        return sl->dev->base_addr;
+
+err_free_chan:
+        sl->tty = NULL;
+        tty->disc_data = NULL;
+        clear_bit(SLF_INUSE, &sl->flags);
+
+err_exit:
+        rtnl_unlock();
+
+        /* Count references from TTY module */
+        return err;
+}
+
+/*
+ * Close down a SLCAN channel.
+ * This means flushing out any pending queues, and then returning. This
+ * call is serialized against other ldisc functions.
+ *
+ * We also use this method for a hangup event.
+ */
+
+static void slcan_close(struct tty_struct *tty)
+{
+        struct slcan *sl = (struct slcan *) tty->disc_data;
+
+        /* First make sure we're connected. */
+        if (!sl || sl->magic != SLCAN_MAGIC || sl->tty != tty)
+                return;
+
+        tty->disc_data = NULL;
+        sl->tty = NULL;
+        if (!sl->leased)
+                sl->line = 0;
+
+        /* Flush network side */
+        unregister_netdev(sl->dev);
+        /* This will complete via sl_free_netdev */
+}
+
+static int slcan_hangup(struct tty_struct *tty)
+{
+        slcan_close(tty);
+        return 0;
+}
+
+/* Perform I/O control on an active SLCAN channel. */
+static int slcan_ioctl(struct tty_struct *tty, struct file *file,
+                       unsigned int cmd, unsigned long arg)
+{
+        struct slcan *sl = (struct slcan *) tty->disc_data;
+        unsigned int tmp;
+
+        /* First make sure we're connected. */
+        if (!sl || sl->magic != SLCAN_MAGIC)
+                return -EINVAL;
+
+        switch (cmd) {
+        case SIOCGIFNAME:
+                tmp = strlen(sl->dev->name) + 1;
+                if (copy_to_user((void __user *)arg, sl->dev->name, tmp))
+                        return -EFAULT;
+                return 0;
+
+        case SIOCSIFHWADDR:
+                return -EINVAL;
+
+        default:
+                return tty_mode_ioctl(tty, file, cmd, arg);
+        }
+}
+
+static struct tty_ldisc_ops slc_ldisc = {
+        .owner          = THIS_MODULE,
+        .magic          = TTY_LDISC_MAGIC,
+        .name           = "slcan",
+        .open           = slcan_open,
+        .close          = slcan_close,
+        .hangup         = slcan_hangup,
+        .ioctl          = slcan_ioctl,
+        .receive_buf    = slcan_receive_buf,
+        .write_wakeup   = slcan_write_wakeup,
+};
+
+static int __init slcan_init(void)
+{
+        int status;
+
+        if (maxdev < 4)
+                maxdev = 4; /* Sanity */
+
+        printk(banner);
+        printk(KERN_INFO "slcan: %d dynamic interface channels.\n", maxdev);
+
+        slcan_devs = kzalloc(sizeof(struct net_device *)*maxdev, GFP_KERNEL);
+        if (!slcan_devs) {
+                printk(KERN_ERR "slcan: can't allocate slcan device array!\n");
+                return -ENOMEM;
+        }
+
+        /* Fill in our line protocol discipline, and register it */
+        status = tty_register_ldisc(N_SLCAN, &slc_ldisc);
+        if (status)  {
+                printk(KERN_ERR "slcan: can't register line discipline\n");
+                kfree(slcan_devs);
+        }
+        return status;
+}
+
+static void __exit slcan_exit(void)
+{
+        int i;
+        struct net_device *dev;
+        struct slcan *sl;
+        unsigned long timeout = jiffies + HZ;
+        int busy = 0;
+
+        if (slcan_devs == NULL)
+                return;
+
+        /* First of all: check for active disciplines and hangup them.
+         */
+        do {
+                if (busy)
+                        msleep_interruptible(100);
+
+                busy = 0;
+                for (i = 0; i < maxdev; i++) {
+                        dev = slcan_devs[i];
+                        if (!dev)
+                                continue;
+                        sl = netdev_priv(dev);
+                        spin_lock_bh(&sl->lock);
+                        if (sl->tty) {
+                                busy++;
+                                tty_hangup(sl->tty);
+                        }
+                        spin_unlock_bh(&sl->lock);
+                }
+        } while (busy && time_before(jiffies, timeout));
+
+        /* FIXME: hangup is async so we should wait when doing this second
+           phase */
+
+        for (i = 0; i < maxdev; i++) {
+                dev = slcan_devs[i];
+                if (!dev)
+                        continue;
+                slcan_devs[i] = NULL;
+
+                sl = netdev_priv(dev);
+                if (sl->tty) {
+                        printk(KERN_ERR "%s: tty discipline still running\n",
+                               dev->name);
+                        /* Intentionally leak the control block. */
+                        dev->destructor = NULL;
+                }
+
+                unregister_netdev(dev);
+        }
+
+        kfree(slcan_devs);
+        slcan_devs = NULL;
+
+        i = tty_unregister_ldisc(N_SLCAN);
+        if (i)
+                printk(KERN_ERR "slcan: can't unregister ldisc (err %d)\n", i);
+}
+
+module_init(slcan_init);
+module_exit(slcan_exit);
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c
index d6b6d6aa565a..7206ab2cbbf8 100644
--- a/drivers/net/cassini.c
+++ b/drivers/net/cassini.c
@@ -2788,7 +2788,7 @@ static inline int cas_xmit_tx_ringN(struct cas *cp, int ring,
 
         ctrl = 0;
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                const u64 csum_start_off = skb_transport_offset(skb);
+                const u64 csum_start_off = skb_checksum_start_offset(skb);
                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
 
                 ctrl =  TX_DESC_CSUM_EN |
@@ -3203,6 +3203,10 @@ static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr,
         int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */
         int mac_off  = 0;
 
+#if defined(CONFIG_OF)
+        const unsigned char *addr;
+#endif
+
         /* give us access to the PROM */
         writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,
                cp->regs + REG_BIM_LOCAL_DEV_EN);
@@ -3350,6 +3354,14 @@ use_random_mac_addr:
         if (found & VPD_FOUND_MAC)
                 goto done;
 
+#if defined(CONFIG_OF)
+        addr = of_get_property(cp->of_node, "local-mac-address", NULL);
+        if (addr != NULL) {
+                memcpy(dev_addr, addr, 6);
+                goto done;
+        }
+#endif
+
         /* Sun MAC prefix then 3 random bytes. */
         pr_info("MAC address not found in ROM VPD\n");
         dev_addr[0] = 0x08;
@@ -3880,7 +3892,7 @@ static int cas_change_mtu(struct net_device *dev, int new_mtu)
         schedule_work(&cp->reset_task);
 #endif
 
-        flush_scheduled_work();
+        flush_work_sync(&cp->reset_task);
         return 0;
 }
 
@@ -5019,6 +5031,10 @@ static int __devinit cas_init_one(struct pci_dev *pdev,
         cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE :
           cassini_debug;
 
+#if defined(CONFIG_OF)
+        cp->of_node = pci_device_to_OF_node(pdev);
+#endif
+
         cp->link_transition = LINK_TRANSITION_UNKNOWN;
         cp->link_transition_jiffies_valid = 0;
 
@@ -5177,7 +5193,7 @@ static void __devexit cas_remove_one(struct pci_dev *pdev)
                 vfree(cp->fw_data);
 
         mutex_lock(&cp->pm_mutex);
-        flush_scheduled_work();
+        cancel_work_sync(&cp->reset_task);
         if (cp->hw_running)
                 cas_shutdown(cp);
         mutex_unlock(&cp->pm_mutex);
diff --git a/drivers/net/cassini.h b/drivers/net/cassini.h
index dbc47878d83b..faf4746a0f3e 100644
--- a/drivers/net/cassini.h
+++ b/drivers/net/cassini.h
@@ -2868,6 +2868,9 @@ struct cas {
         dma_addr_t block_dvma, tx_tiny_dvma[N_TX_RINGS];
         struct pci_dev *pdev;
         struct net_device *dev;
+#if defined(CONFIG_OF)
+        struct device_node      *of_node;
+#endif
 
         /* Firmware Info */
         u16                     fw_load_addr;
diff --git a/drivers/net/chelsio/my3126.c b/drivers/net/chelsio/my3126.c
index 4c6028512d10..a683fd3bb624 100644
--- a/drivers/net/chelsio/my3126.c
+++ b/drivers/net/chelsio/my3126.c
@@ -22,7 +22,7 @@ static int my3126_interrupt_enable(struct cphy *cphy)
 
 static int my3126_interrupt_disable(struct cphy *cphy)
 {
-        cancel_rearming_delayed_work(&cphy->phy_update);
+        cancel_delayed_work_sync(&cphy->phy_update);
         return 0;
 }
 
diff --git a/drivers/net/chelsio/sge.c b/drivers/net/chelsio/sge.c
index 70221ca32683..f778b15ad3fd 100644
--- a/drivers/net/chelsio/sge.c
+++ b/drivers/net/chelsio/sge.c
@@ -273,6 +273,10 @@ struct sge {
         struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
 };
 
+static const u8 ch_mac_addr[ETH_ALEN] = {
+        0x0, 0x7, 0x43, 0x0, 0x0, 0x0
+};
+
 /*
  * stop tasklet and free all pending skb's
  */
@@ -2012,10 +2016,6 @@ static void espibug_workaround_t204(unsigned long data)
                                 continue;
 
                         if (!skb->cb[0]) {
-                                u8 ch_mac_addr[ETH_ALEN] = {
-                                        0x0, 0x7, 0x43, 0x0, 0x0, 0x0
-                                };
-
                                 skb_copy_to_linear_data_offset(skb,
                                                     sizeof(struct cpl_tx_pkt),
                                                                ch_mac_addr,
@@ -2048,8 +2048,6 @@ static void espibug_workaround(unsigned long data)
 
                 if ((seop & 0xfff0fff) == 0xfff && skb) {
                         if (!skb->cb[0]) {
-                                u8 ch_mac_addr[ETH_ALEN] =
-                                    {0x0, 0x7, 0x43, 0x0, 0x0, 0x0};
                                 skb_copy_to_linear_data_offset(skb,
                                                      sizeof(struct cpl_tx_pkt),
                                                                ch_mac_addr,
diff --git a/drivers/net/cnic.c b/drivers/net/cnic.c
index 92bac19ad60a..263a2944566f 100644
--- a/drivers/net/cnic.c
+++ b/drivers/net/cnic.c
@@ -59,6 +59,7 @@ MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(CNIC_MODULE_VERSION);
 
+/* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
 static LIST_HEAD(cnic_dev_list);
 static LIST_HEAD(cnic_udev_list);
 static DEFINE_RWLOCK(cnic_dev_lock);
@@ -278,6 +279,7 @@ static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
         u32 msg_type = ISCSI_KEVENT_IF_DOWN;
         struct cnic_ulp_ops *ulp_ops;
         struct cnic_uio_dev *udev = cp->udev;
+        int rc = 0, retry = 0;
 
         if (!udev || udev->uio_dev == -1)
                 return -ENODEV;
@@ -302,14 +304,26 @@ static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
                 path_req.pmtu = csk->mtu;
         }
 
-        rcu_read_lock();
-        ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
-        if (ulp_ops)
-                ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
-        rcu_read_unlock();
+        while (retry < 3) {
+                rc = 0;
+                rcu_read_lock();
+                ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
+                if (ulp_ops)
+                        rc = ulp_ops->iscsi_nl_send_msg(
+                                cp->ulp_handle[CNIC_ULP_ISCSI],
+                                msg_type, buf, len);
+                rcu_read_unlock();
+                if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
+                        break;
+
+                msleep(100);
+                retry++;
+        }
         return 0;
 }
 
+static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
+
 static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
                                   char *buf, u16 len)
 {
@@ -339,7 +353,9 @@ static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
                 }
                 csk = &cp->csk_tbl[l5_cid];
                 csk_hold(csk);
-                if (cnic_in_use(csk)) {
+                if (cnic_in_use(csk) &&
+                    test_bit(SK_F_CONNECT_START, &csk->flags)) {
+
                         memcpy(csk->ha, path_resp->mac_addr, 6);
                         if (test_bit(SK_F_IPV6, &csk->flags))
                                 memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
@@ -347,8 +363,16 @@ static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
                         else
                                 memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
                                        sizeof(struct in_addr));
-                        if (is_valid_ether_addr(csk->ha))
+
+                        if (is_valid_ether_addr(csk->ha)) {
                                 cnic_cm_set_pg(csk);
+                        } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
+                                !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
+
+                                cnic_cm_upcall(cp, csk,
+                                        L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
+                                clear_bit(SK_F_CONNECT_START, &csk->flags);
+                        }
                 }
                 csk_put(csk);
                 rcu_read_unlock();
@@ -402,19 +426,6 @@ static int cnic_abort_prep(struct cnic_sock *csk)
         return 0;
 }
 
-static void cnic_uio_stop(void)
-{
-        struct cnic_dev *dev;
-
-        read_lock(&cnic_dev_lock);
-        list_for_each_entry(dev, &cnic_dev_list, list) {
-                struct cnic_local *cp = dev->cnic_priv;
-
-                cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
-        }
-        read_unlock(&cnic_dev_lock);
-}
-
 int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
 {
         struct cnic_dev *dev;
@@ -445,14 +456,12 @@ int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
 
         /* Prevent race conditions with netdev_event */
         rtnl_lock();
-        read_lock(&cnic_dev_lock);
         list_for_each_entry(dev, &cnic_dev_list, list) {
                 struct cnic_local *cp = dev->cnic_priv;
 
                 if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
                         ulp_ops->cnic_init(dev);
         }
-        read_unlock(&cnic_dev_lock);
         rtnl_unlock();
 
         return 0;
@@ -488,9 +497,6 @@ int cnic_unregister_driver(int ulp_type)
         }
         read_unlock(&cnic_dev_lock);
 
-        if (ulp_type == CNIC_ULP_ISCSI)
-                cnic_uio_stop();
-
         rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
 
         mutex_unlock(&cnic_lock);
@@ -574,6 +580,9 @@ static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
         }
         mutex_unlock(&cnic_lock);
 
+        if (ulp_type == CNIC_ULP_ISCSI)
+                cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
+
         synchronize_rcu();
 
         while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
@@ -821,12 +830,14 @@ static void cnic_free_resc(struct cnic_dev *dev)
         cnic_free_dma(dev, &cp->conn_buf_info);
         cnic_free_dma(dev, &cp->kwq_info);
         cnic_free_dma(dev, &cp->kwq_16_data_info);
+        cnic_free_dma(dev, &cp->kcq2.dma);
         cnic_free_dma(dev, &cp->kcq1.dma);
         kfree(cp->iscsi_tbl);
         cp->iscsi_tbl = NULL;
         kfree(cp->ctx_tbl);
         cp->ctx_tbl = NULL;
 
+        cnic_free_id_tbl(&cp->fcoe_cid_tbl);
         cnic_free_id_tbl(&cp->cid_tbl);
 }
 
@@ -940,7 +951,7 @@ static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
                                            &udev->l2_ring_map,
                                            GFP_KERNEL | __GFP_COMP);
         if (!udev->l2_ring)
-                return -ENOMEM;
+                goto err_udev;
 
         udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
         udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
@@ -948,7 +959,7 @@ static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
                                           &udev->l2_buf_map,
                                           GFP_KERNEL | __GFP_COMP);
         if (!udev->l2_buf)
-                return -ENOMEM;
+                goto err_dma;
 
         write_lock(&cnic_dev_lock);
         list_add(&udev->list, &cnic_udev_list);
@@ -959,6 +970,12 @@ static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
         cp->udev = udev;
 
         return 0;
+ err_dma:
+        dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
+                          udev->l2_ring, udev->l2_ring_map);
+ err_udev:
+        kfree(udev);
+        return -ENOMEM;
 }
 
 static int cnic_init_uio(struct cnic_dev *dev)
@@ -1114,12 +1131,22 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
 
         cp->iro_arr = ethdev->iro_arr;
 
-        cp->max_cid_space = MAX_ISCSI_TBL_SZ;
+        cp->max_cid_space = MAX_ISCSI_TBL_SZ + BNX2X_FCOE_NUM_CONNECTIONS;
         cp->iscsi_start_cid = start_cid;
+        cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
+
+        if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                cp->max_cid_space += BNX2X_FCOE_NUM_CONNECTIONS;
+                cp->fcoe_init_cid = ethdev->fcoe_init_cid;
+                if (!cp->fcoe_init_cid)
+                        cp->fcoe_init_cid = 0x10;
+        }
+
         if (start_cid < BNX2X_ISCSI_START_CID) {
                 u32 delta = BNX2X_ISCSI_START_CID - start_cid;
 
                 cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
+                cp->fcoe_start_cid += delta;
                 cp->max_cid_space += delta;
         }
 
@@ -1138,6 +1165,9 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
                 cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
         }
 
+        for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
+                cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
+
         pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
                 PAGE_SIZE;
 
@@ -1161,6 +1191,12 @@ static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
         if (ret)
                 goto error;
 
+        if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                ret = cnic_alloc_kcq(dev, &cp->kcq2);
+                if (ret)
+                        goto error;
+        }
+
         pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
                            BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
         ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
@@ -1254,12 +1290,18 @@ static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
         struct cnic_local *cp = dev->cnic_priv;
         struct l5cm_spe kwqe;
         struct kwqe_16 *kwq[1];
+        u16 type_16;
         int ret;
 
         kwqe.hdr.conn_and_cmd_data =
                 cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
                              BNX2X_HW_CID(cp, cid)));
-        kwqe.hdr.type = cpu_to_le16(type);
+
+        type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
+        type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
+                   SPE_HDR_FUNCTION_ID;
+
+        kwqe.hdr.type = cpu_to_le16(type_16);
         kwqe.hdr.reserved1 = 0;
         kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
         kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
@@ -1425,8 +1467,11 @@ static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
                 cnic_free_dma(dev, &iscsi->hq_info);
                 cnic_free_dma(dev, &iscsi->r2tq_info);
                 cnic_free_dma(dev, &iscsi->task_array_info);
+                cnic_free_id(&cp->cid_tbl, ctx->cid);
+        } else {
+                cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
         }
-        cnic_free_id(&cp->cid_tbl, ctx->cid);
+
         ctx->cid = 0;
 }
 
@@ -1438,6 +1483,16 @@ static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
         struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
         struct cnic_iscsi *iscsi = ctx->proto.iscsi;
 
+        if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
+                cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
+                if (cid == -1) {
+                        ret = -ENOMEM;
+                        goto error;
+                }
+                ctx->cid = cid;
+                return 0;
+        }
+
         cid = cnic_alloc_new_id(&cp->cid_tbl);
         if (cid == -1) {
                 ret = -ENOMEM;
@@ -1695,7 +1750,7 @@ static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
                 *work = num;
                 return -EINVAL;
         }
-        *work = 2 + req2->num_additional_wqes;;
+        *work = 2 + req2->num_additional_wqes;
 
         l5_cid = req1->iscsi_conn_id;
         if (l5_cid >= MAX_ISCSI_TBL_SZ)
@@ -1770,19 +1825,15 @@ static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
         struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
         union l5cm_specific_data l5_data;
         int ret;
-        u32 hw_cid, type;
+        u32 hw_cid;
 
         init_waitqueue_head(&ctx->waitq);
         ctx->wait_cond = 0;
         memset(&l5_data, 0, sizeof(l5_data));
         hw_cid = BNX2X_HW_CID(cp, ctx->cid);
-        type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
-                & SPE_HDR_CONN_TYPE;
-        type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
-                 SPE_HDR_FUNCTION_ID);
 
         ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
-                                  hw_cid, type, &l5_data);
+                                  hw_cid, NONE_CONNECTION_TYPE, &l5_data);
 
         if (ret == 0)
                 wait_event(ctx->waitq, ctx->wait_cond);
@@ -2078,8 +2129,306 @@ static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
         return 0;
 }
 
-static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
-                                   u32 num_wqes)
+static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+        struct fcoe_kwqe_stat *req;
+        struct fcoe_stat_ramrod_params *fcoe_stat;
+        union l5cm_specific_data l5_data;
+        struct cnic_local *cp = dev->cnic_priv;
+        int ret;
+        u32 cid;
+
+        req = (struct fcoe_kwqe_stat *) kwqe;
+        cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
+
+        fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
+        if (!fcoe_stat)
+                return -ENOMEM;
+
+        memset(fcoe_stat, 0, sizeof(*fcoe_stat));
+        memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
+
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        return ret;
+}
+
+static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
+                                 u32 num, int *work)
+{
+        int ret;
+        struct cnic_local *cp = dev->cnic_priv;
+        u32 cid;
+        struct fcoe_init_ramrod_params *fcoe_init;
+        struct fcoe_kwqe_init1 *req1;
+        struct fcoe_kwqe_init2 *req2;
+        struct fcoe_kwqe_init3 *req3;
+        union l5cm_specific_data l5_data;
+
+        if (num < 3) {
+                *work = num;
+                return -EINVAL;
+        }
+        req1 = (struct fcoe_kwqe_init1 *) wqes[0];
+        req2 = (struct fcoe_kwqe_init2 *) wqes[1];
+        req3 = (struct fcoe_kwqe_init3 *) wqes[2];
+        if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
+                *work = 1;
+                return -EINVAL;
+        }
+        if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
+                *work = 2;
+                return -EINVAL;
+        }
+
+        if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
+                netdev_err(dev->netdev, "fcoe_init size too big\n");
+                return -ENOMEM;
+        }
+        fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
+        if (!fcoe_init)
+                return -ENOMEM;
+
+        memset(fcoe_init, 0, sizeof(*fcoe_init));
+        memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
+        memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
+        memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
+        fcoe_init->eq_addr.lo = cp->kcq2.dma.pg_map_arr[0] & 0xffffffff;
+        fcoe_init->eq_addr.hi = (u64) cp->kcq2.dma.pg_map_arr[0] >> 32;
+        fcoe_init->eq_next_page_addr.lo =
+                cp->kcq2.dma.pg_map_arr[1] & 0xffffffff;
+        fcoe_init->eq_next_page_addr.hi =
+                (u64) cp->kcq2.dma.pg_map_arr[1] >> 32;
+
+        fcoe_init->sb_num = cp->status_blk_num;
+        fcoe_init->eq_prod = MAX_KCQ_IDX;
+        fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
+        cp->kcq2.sw_prod_idx = 0;
+
+        cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        *work = 3;
+        return ret;
+}
+
+static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
+                                 u32 num, int *work)
+{
+        int ret = 0;
+        u32 cid = -1, l5_cid;
+        struct cnic_local *cp = dev->cnic_priv;
+        struct fcoe_kwqe_conn_offload1 *req1;
+        struct fcoe_kwqe_conn_offload2 *req2;
+        struct fcoe_kwqe_conn_offload3 *req3;
+        struct fcoe_kwqe_conn_offload4 *req4;
+        struct fcoe_conn_offload_ramrod_params *fcoe_offload;
+        struct cnic_context *ctx;
+        struct fcoe_context *fctx;
+        struct regpair ctx_addr;
+        union l5cm_specific_data l5_data;
+        struct fcoe_kcqe kcqe;
+        struct kcqe *cqes[1];
+
+        if (num < 4) {
+                *work = num;
+                return -EINVAL;
+        }
+        req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
+        req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
+        req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
+        req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
+
+        *work = 4;
+
+        l5_cid = req1->fcoe_conn_id;
+        if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
+                goto err_reply;
+
+        l5_cid += BNX2X_FCOE_L5_CID_BASE;
+
+        ctx = &cp->ctx_tbl[l5_cid];
+        if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
+                goto err_reply;
+
+        ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
+        if (ret) {
+                ret = 0;
+                goto err_reply;
+        }
+        cid = ctx->cid;
+
+        fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
+        if (fctx) {
+                u32 hw_cid = BNX2X_HW_CID(cp, cid);
+                u32 val;
+
+                val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
+                                             FCOE_CONNECTION_TYPE);
+                fctx->xstorm_ag_context.cdu_reserved = val;
+                val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
+                                             FCOE_CONNECTION_TYPE);
+                fctx->ustorm_ag_context.cdu_usage = val;
+        }
+        if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
+                netdev_err(dev->netdev, "fcoe_offload size too big\n");
+                goto err_reply;
+        }
+        fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
+        if (!fcoe_offload)
+                goto err_reply;
+
+        memset(fcoe_offload, 0, sizeof(*fcoe_offload));
+        memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
+        memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
+        memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
+        memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
+
+        cid = BNX2X_HW_CID(cp, cid);
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        if (!ret)
+                set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
+
+        return ret;
+
+err_reply:
+        if (cid != -1)
+                cnic_free_bnx2x_conn_resc(dev, l5_cid);
+
+        memset(&kcqe, 0, sizeof(kcqe));
+        kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
+        kcqe.fcoe_conn_id = req1->fcoe_conn_id;
+        kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
+
+        cqes[0] = (struct kcqe *) &kcqe;
+        cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
+        return ret;
+}
+
+static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+        struct fcoe_kwqe_conn_enable_disable *req;
+        struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
+        union l5cm_specific_data l5_data;
+        int ret;
+        u32 cid, l5_cid;
+        struct cnic_local *cp = dev->cnic_priv;
+
+        req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
+        cid = req->context_id;
+        l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
+
+        if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
+                netdev_err(dev->netdev, "fcoe_enable size too big\n");
+                return -ENOMEM;
+        }
+        fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
+        if (!fcoe_enable)
+                return -ENOMEM;
+
+        memset(fcoe_enable, 0, sizeof(*fcoe_enable));
+        memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        return ret;
+}
+
+static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+        struct fcoe_kwqe_conn_enable_disable *req;
+        struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
+        union l5cm_specific_data l5_data;
+        int ret;
+        u32 cid, l5_cid;
+        struct cnic_local *cp = dev->cnic_priv;
+
+        req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
+        cid = req->context_id;
+        l5_cid = req->conn_id;
+        if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
+                return -EINVAL;
+
+        l5_cid += BNX2X_FCOE_L5_CID_BASE;
+
+        if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
+                netdev_err(dev->netdev, "fcoe_disable size too big\n");
+                return -ENOMEM;
+        }
+        fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
+        if (!fcoe_disable)
+                return -ENOMEM;
+
+        memset(fcoe_disable, 0, sizeof(*fcoe_disable));
+        memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        return ret;
+}
+
+static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+        struct fcoe_kwqe_conn_destroy *req;
+        union l5cm_specific_data l5_data;
+        int ret;
+        u32 cid, l5_cid;
+        struct cnic_local *cp = dev->cnic_priv;
+        struct cnic_context *ctx;
+        struct fcoe_kcqe kcqe;
+        struct kcqe *cqes[1];
+
+        req = (struct fcoe_kwqe_conn_destroy *) kwqe;
+        cid = req->context_id;
+        l5_cid = req->conn_id;
+        if (l5_cid >= BNX2X_FCOE_NUM_CONNECTIONS)
+                return -EINVAL;
+
+        l5_cid += BNX2X_FCOE_L5_CID_BASE;
+
+        ctx = &cp->ctx_tbl[l5_cid];
+
+        init_waitqueue_head(&ctx->waitq);
+        ctx->wait_cond = 0;
+
+        memset(&l5_data, 0, sizeof(l5_data));
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        if (ret == 0) {
+                wait_event(ctx->waitq, ctx->wait_cond);
+                set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
+                queue_delayed_work(cnic_wq, &cp->delete_task,
+                                   msecs_to_jiffies(2000));
+        }
+
+        memset(&kcqe, 0, sizeof(kcqe));
+        kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
+        kcqe.fcoe_conn_id = req->conn_id;
+        kcqe.fcoe_conn_context_id = cid;
+
+        cqes[0] = (struct kcqe *) &kcqe;
+        cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
+        return ret;
+}
+
+static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
+{
+        struct fcoe_kwqe_destroy *req;
+        union l5cm_specific_data l5_data;
+        struct cnic_local *cp = dev->cnic_priv;
+        int ret;
+        u32 cid;
+
+        req = (struct fcoe_kwqe_destroy *) kwqe;
+        cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
+
+        memset(&l5_data, 0, sizeof(l5_data));
+        ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY, cid,
+                                  FCOE_CONNECTION_TYPE, &l5_data);
+        return ret;
+}
+
+static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
+                                         struct kwqe *wqes[], u32 num_wqes)
 {
         int i, work, ret;
         u32 opcode;
@@ -2143,6 +2492,98 @@ static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
         return 0;
 }
 
+static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
+                                        struct kwqe *wqes[], u32 num_wqes)
+{
+        struct cnic_local *cp = dev->cnic_priv;
+        int i, work, ret;
+        u32 opcode;
+        struct kwqe *kwqe;
+
+        if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
+                return -EAGAIN;         /* bnx2 is down */
+
+        if (BNX2X_CHIP_NUM(cp->chip_id) == BNX2X_CHIP_NUM_57710)
+                return -EINVAL;
+
+        for (i = 0; i < num_wqes; ) {
+                kwqe = wqes[i];
+                opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
+                work = 1;
+
+                switch (opcode) {
+                case FCOE_KWQE_OPCODE_INIT1:
+                        ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
+                                                    num_wqes - i, &work);
+                        break;
+                case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
+                        ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
+                                                    num_wqes - i, &work);
+                        break;
+                case FCOE_KWQE_OPCODE_ENABLE_CONN:
+                        ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
+                        break;
+                case FCOE_KWQE_OPCODE_DISABLE_CONN:
+                        ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
+                        break;
+                case FCOE_KWQE_OPCODE_DESTROY_CONN:
+                        ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
+                        break;
+                case FCOE_KWQE_OPCODE_DESTROY:
+                        ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
+                        break;
+                case FCOE_KWQE_OPCODE_STAT:
+                        ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
+                        break;
+                default:
+                        ret = 0;
+                        netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
+                                   opcode);
+                        break;
+                }
+                if (ret < 0)
+                        netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
+                                   opcode);
+                i += work;
+        }
+        return 0;
+}
+
+static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
+                                   u32 num_wqes)
+{
+        int ret = -EINVAL;
+        u32 layer_code;
+
+        if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
+                return -EAGAIN;         /* bnx2x is down */
+
+        if (!num_wqes)
+                return 0;
+
+        layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
+        switch (layer_code) {
+        case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
+        case KWQE_FLAGS_LAYER_MASK_L4:
+        case KWQE_FLAGS_LAYER_MASK_L2:
+                ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
+                break;
+
+        case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
+                ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
+                break;
+        }
+        return ret;
+}
+
+static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
+{
+        if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
+                return KCQE_FLAGS_LAYER_MASK_L4;
+
+        return opflag & KCQE_FLAGS_LAYER_MASK;
+}
+
 static void service_kcqes(struct cnic_dev *dev, int num_cqes)
 {
         struct cnic_local *cp = dev->cnic_priv;
@@ -2154,7 +2595,7 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
                 struct cnic_ulp_ops *ulp_ops;
                 int ulp_type;
                 u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
-                u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
+                u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
 
                 if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
                         comp++;
@@ -2162,7 +2603,7 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
                 while (j < num_cqes) {
                         u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
 
-                        if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
+                        if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
                                 break;
 
                         if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
@@ -2174,6 +2615,8 @@ static void service_kcqes(struct cnic_dev *dev, int num_cqes)
                         ulp_type = CNIC_ULP_RDMA;
                 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
                         ulp_type = CNIC_ULP_ISCSI;
+                else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
+                        ulp_type = CNIC_ULP_FCOE;
                 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
                         ulp_type = CNIC_ULP_L4;
                 else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
@@ -2342,11 +2785,12 @@ static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
 static int cnic_service_bnx2(void *data, void *status_blk)
 {
         struct cnic_dev *dev = data;
-        struct cnic_local *cp = dev->cnic_priv;
-        u32 status_idx = *cp->kcq1.status_idx_ptr;
 
-        if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
-                return status_idx;
+        if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
+                struct status_block *sblk = status_blk;
+
+                return sblk->status_idx;
+        }
 
         return cnic_service_bnx2_queues(dev);
 }
@@ -2365,9 +2809,10 @@ static void cnic_service_bnx2_msix(unsigned long data)
 static void cnic_doirq(struct cnic_dev *dev)
 {
         struct cnic_local *cp = dev->cnic_priv;
-        u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
 
         if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
+                u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
+
                 prefetch(cp->status_blk.gen);
                 prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
 
@@ -2469,12 +2914,19 @@ static void cnic_service_bnx2x_bh(unsigned long data)
         status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
 
         CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
-        if (BNX2X_CHIP_IS_E2(cp->chip_id))
+
+        if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
+
+                CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
+                          MAX_KCQ_IDX);
+
                 cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
                                 status_idx, IGU_INT_ENABLE, 1);
-        else
+        } else {
                 cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
                                    status_idx, IGU_INT_ENABLE, 1);
+        }
 }
 
 static int cnic_service_bnx2x(void *data, void *status_blk)
@@ -2883,7 +3335,7 @@ static void cnic_cm_cleanup(struct cnic_sock *csk)
                 struct cnic_dev *dev = csk->dev;
                 struct cnic_local *cp = dev->cnic_priv;
 
-                cnic_free_id(&cp->csk_port_tbl, csk->src_port);
+                cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
                 csk->src_port = 0;
         }
 }
@@ -3014,7 +3466,8 @@ static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
         int is_v6, rc = 0;
         struct dst_entry *dst = NULL;
         struct net_device *realdev;
-        u32 local_port;
+        __be16 local_port;
+        u32 port_id;
 
         if (saddr->local.v6.sin6_family == AF_INET6 &&
             saddr->remote.v6.sin6_family == AF_INET6)
@@ -3054,19 +3507,21 @@ static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
                 }
         }
 
-        if (local_port >= CNIC_LOCAL_PORT_MIN &&
-            local_port < CNIC_LOCAL_PORT_MAX) {
-                if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
-                        local_port = 0;
+        port_id = be16_to_cpu(local_port);
+        if (port_id >= CNIC_LOCAL_PORT_MIN &&
+            port_id < CNIC_LOCAL_PORT_MAX) {
+                if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
+                        port_id = 0;
         } else
-                local_port = 0;
+                port_id = 0;
 
-        if (!local_port) {
-                local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
-                if (local_port == -1) {
+        if (!port_id) {
+                port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
+                if (port_id == -1) {
                         rc = -ENOMEM;
                         goto err_out;
                 }
+                local_port = cpu_to_be16(port_id);
         }
         csk->src_port = local_port;
 
@@ -3208,6 +3663,18 @@ done:
         csk_put(csk);
 }
 
+static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
+{
+        struct cnic_local *cp = dev->cnic_priv;
+        struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
+        u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
+        struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
+
+        ctx->timestamp = jiffies;
+        ctx->wait_cond = 1;
+        wake_up(&ctx->waitq);
+}
+
 static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
 {
         struct cnic_local *cp = dev->cnic_priv;
@@ -3216,6 +3683,10 @@ static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
         u32 l5_cid;
         struct cnic_sock *csk;
 
+        if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
+                cnic_process_fcoe_term_conn(dev, kcqe);
+                return;
+        }
         if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
             opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
                 cnic_cm_process_offld_pg(dev, l4kcqe);
@@ -3852,7 +4323,7 @@ static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
 
         memset(&l2kwqe, 0, sizeof(l2kwqe));
         wqes[0] = &l2kwqe;
-        l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
+        l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
                               (L2_KWQE_OPCODE_VALUE_FLUSH <<
                                KWQE_OPCODE_SHIFT) | 2;
         dev->submit_kwqes(dev, wqes, 1);
@@ -4106,7 +4577,7 @@ static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
         struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
         int port = CNIC_PORT(cp);
         int i;
-        int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+        u32 cli = cp->ethdev->iscsi_l2_client_id;
         u32 val;
 
         memset(txbd, 0, BCM_PAGE_SIZE);
@@ -4167,7 +4638,7 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
         struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
         int i;
         int port = CNIC_PORT(cp);
-        int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+        u32 cli = cp->ethdev->iscsi_l2_client_id;
         int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
         u32 val;
         dma_addr_t ring_map = udev->l2_ring_map;
@@ -4231,12 +4702,39 @@ static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
 
         cp->rx_cons_ptr =
                 &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
+        cp->rx_cons = *cp->rx_cons_ptr;
+}
+
+static int cnic_read_bnx2x_iscsi_mac(struct cnic_dev *dev, u32 upper_addr,
+                                     u32 lower_addr)
+{
+        u32 val;
+        u8 mac[6];
+
+        val = CNIC_RD(dev, upper_addr);
+
+        mac[0] = (u8) (val >> 8);
+        mac[1] = (u8) val;
+
+        val = CNIC_RD(dev, lower_addr);
+
+        mac[2] = (u8) (val >> 24);
+        mac[3] = (u8) (val >> 16);
+        mac[4] = (u8) (val >> 8);
+        mac[5] = (u8) val;
+
+        if (is_valid_ether_addr(mac)) {
+                memcpy(dev->mac_addr, mac, 6);
+                return 0;
+        } else {
+                return -EINVAL;
+        }
 }
 
 static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
 {
         struct cnic_local *cp = dev->cnic_priv;
-        u32 base, base2, addr, val;
+        u32 base, base2, addr, addr1, val;
         int port = CNIC_PORT(cp);
 
         dev->max_iscsi_conn = 0;
@@ -4249,20 +4747,10 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
         addr = BNX2X_SHMEM_ADDR(base,
                 dev_info.port_hw_config[port].iscsi_mac_upper);
 
-        val = CNIC_RD(dev, addr);
-
-        dev->mac_addr[0] = (u8) (val >> 8);
-        dev->mac_addr[1] = (u8) val;
-
-        addr = BNX2X_SHMEM_ADDR(base,
+        addr1 = BNX2X_SHMEM_ADDR(base,
                 dev_info.port_hw_config[port].iscsi_mac_lower);
 
-        val = CNIC_RD(dev, addr);
-
-        dev->mac_addr[2] = (u8) (val >> 24);
-        dev->mac_addr[3] = (u8) (val >> 16);
-        dev->mac_addr[4] = (u8) (val >> 8);
-        dev->mac_addr[5] = (u8) val;
+        cnic_read_bnx2x_iscsi_mac(dev, addr, addr1);
 
         addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
         val = CNIC_RD(dev, addr);
@@ -4278,6 +4766,10 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
                         val16 ^= 0x1e1e;
                 dev->max_iscsi_conn = val16;
         }
+
+        if (BNX2X_CHIP_IS_E2(cp->chip_id))
+                dev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
+
         if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
                 int func = CNIC_FUNC(cp);
                 u32 mf_cfg_addr;
@@ -4288,21 +4780,90 @@ static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
                 else
                         mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
 
-                addr = mf_cfg_addr +
-                        offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
+                if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                        /* Must determine if the MF is SD vs SI mode */
+                        addr = BNX2X_SHMEM_ADDR(base,
+                                        dev_info.shared_feature_config.config);
+                        val = CNIC_RD(dev, addr);
+                        if ((val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) ==
+                            SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT) {
+                                int rc;
+
+                                /* MULTI_FUNCTION_SI mode */
+                                addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+                                        func_ext_config[func].func_cfg);
+                                val = CNIC_RD(dev, addr);
+                                if (!(val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD))
+                                        dev->max_iscsi_conn = 0;
+
+                                if (!(val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
+                                        dev->max_fcoe_conn = 0;
+
+                                addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+                                        func_ext_config[func].
+                                        iscsi_mac_addr_upper);
+                                addr1 = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+                                        func_ext_config[func].
+                                        iscsi_mac_addr_lower);
+                                rc = cnic_read_bnx2x_iscsi_mac(dev, addr,
+                                                                addr1);
+                                if (rc && func > 1)
+                                        dev->max_iscsi_conn = 0;
+
+                                return;
+                        }
+                }
+
+                addr = BNX2X_MF_CFG_ADDR(mf_cfg_addr,
+                        func_mf_config[func].e1hov_tag);
 
                 val = CNIC_RD(dev, addr);
                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
-                        addr = mf_cfg_addr +
-                                offsetof(struct mf_cfg,
-                                         func_mf_config[func].config);
-                        val = CNIC_RD(dev, addr);
-                        val &= FUNC_MF_CFG_PROTOCOL_MASK;
-                        if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
-                                dev->max_iscsi_conn = 0;
+                        dev->max_fcoe_conn = 0;
+                        dev->max_iscsi_conn = 0;
                 }
         }
+        if (!is_valid_ether_addr(dev->mac_addr))
+                dev->max_iscsi_conn = 0;
+}
+
+static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
+{
+        struct cnic_local *cp = dev->cnic_priv;
+        u32 pfid = cp->pfid;
+
+        cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
+                           CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
+        cp->kcq1.sw_prod_idx = 0;
+
+        if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
+
+                cp->kcq1.hw_prod_idx_ptr =
+                        &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
+                cp->kcq1.status_idx_ptr =
+                        &sb->sb.running_index[SM_RX_ID];
+        } else {
+                struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
+
+                cp->kcq1.hw_prod_idx_ptr =
+                        &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
+                cp->kcq1.status_idx_ptr =
+                        &sb->sb.running_index[SM_RX_ID];
+        }
+
+        if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
+                struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
+
+                cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
+                                        USTORM_FCOE_EQ_PROD_OFFSET(pfid);
+                cp->kcq2.sw_prod_idx = 0;
+                cp->kcq2.hw_prod_idx_ptr =
+                        &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
+                cp->kcq2.status_idx_ptr =
+                        &sb->sb.running_index[SM_RX_ID];
+        }
 }
 
 static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
@@ -4335,28 +4896,19 @@ static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
         if (ret)
                 return -ENOMEM;
 
-        cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
-
-        cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
-                          CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
-        cp->kcq1.sw_prod_idx = 0;
-
         if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
-                struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
-
-                cp->kcq1.hw_prod_idx_ptr =
-                        &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
-                cp->kcq1.status_idx_ptr =
-                        &sb->sb.running_index[SM_RX_ID];
-        } else {
-                struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
+                ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl,
+                                        BNX2X_FCOE_NUM_CONNECTIONS,
+                                        cp->fcoe_start_cid);
 
-                cp->kcq1.hw_prod_idx_ptr =
-                        &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
-                cp->kcq1.status_idx_ptr =
-                        &sb->sb.running_index[SM_RX_ID];
+                if (ret)
+                        return -ENOMEM;
         }
 
+        cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
+
+        cnic_init_bnx2x_kcq(dev);
+
         cnic_get_bnx2x_iscsi_info(dev);
 
         /* Only 1 EQ */
@@ -4424,8 +4976,9 @@ static void cnic_init_rings(struct cnic_dev *dev)
                 cnic_init_bnx2_rx_ring(dev);
                 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
         } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
-                u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
-                u32 cl_qzone_id, type;
+                u32 cli = cp->ethdev->iscsi_l2_client_id;
+                u32 cid = cp->ethdev->iscsi_l2_cid;
+                u32 cl_qzone_id;
                 struct client_init_ramrod_data *data;
                 union l5cm_specific_data l5_data;
                 struct ustorm_eth_rx_producers rx_prods = {0};
@@ -4457,15 +5010,10 @@ static void cnic_init_rings(struct cnic_dev *dev)
                 l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
                 l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
 
-                type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
-                        & SPE_HDR_CONN_TYPE;
-                type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
-                        SPE_HDR_FUNCTION_ID);
-
                 set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
 
                 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
-                        BNX2X_ISCSI_L2_CID, type, &l5_data);
+                        cid, ETH_CONNECTION_TYPE, &l5_data);
 
                 i = 0;
                 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
@@ -4476,7 +5024,7 @@ static void cnic_init_rings(struct cnic_dev *dev)
                         netdev_err(dev->netdev,
                                 "iSCSI CLIENT_SETUP did not complete\n");
                 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
-                cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
+                cnic_ring_ctl(dev, cid, cli, 1);
         }
 }
 
@@ -4491,19 +5039,19 @@ static void cnic_shutdown_rings(struct cnic_dev *dev)
                 cnic_shutdown_bnx2_rx_ring(dev);
         } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
                 struct cnic_local *cp = dev->cnic_priv;
-                u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
+                u32 cli = cp->ethdev->iscsi_l2_client_id;
+                u32 cid = cp->ethdev->iscsi_l2_cid;
                 union l5cm_specific_data l5_data;
                 int i;
-                u32 type;
 
-                cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
+                cnic_ring_ctl(dev, cid, cli, 0);
 
                 set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
 
                 l5_data.phy_address.lo = cli;
                 l5_data.phy_address.hi = 0;
                 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
-                        BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
+                        cid, ETH_CONNECTION_TYPE, &l5_data);
                 i = 0;
                 while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
                        ++i < 10)
@@ -4515,12 +5063,8 @@ static void cnic_shutdown_rings(struct cnic_dev *dev)
                 cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
 
                 memset(&l5_data, 0, sizeof(l5_data));
-                type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
-                        & SPE_HDR_CONN_TYPE;
-                type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
-                         SPE_HDR_FUNCTION_ID);
                 cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
-                        BNX2X_ISCSI_L2_CID, type, &l5_data);
+                        cid, NONE_CONNECTION_TYPE, &l5_data);
                 msleep(10);
         }
         clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
diff --git a/drivers/net/cnic.h b/drivers/net/cnic.h
index 6a4a0ae5cfe3..b328f6c924c3 100644
--- a/drivers/net/cnic.h
+++ b/drivers/net/cnic.h
@@ -82,7 +82,7 @@ struct cnic_redirect_entry {
 #define MAX_ISCSI_TBL_SZ        256
 
 #define CNIC_LOCAL_PORT_MIN     60000
-#define CNIC_LOCAL_PORT_MAX     61000
+#define CNIC_LOCAL_PORT_MAX     61024
 #define CNIC_LOCAL_PORT_RANGE   (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
 
 #define KWQE_CNT (BCM_PAGE_SIZE / sizeof(struct kwqe))
@@ -258,6 +258,7 @@ struct cnic_local {
         u16             kwq_con_idx;
 
         struct kcq_info kcq1;
+        struct kcq_info kcq2;
 
         union {
                 void                            *gen;
@@ -290,6 +291,10 @@ struct cnic_local {
         atomic_t                iscsi_conn;
         u32                     iscsi_start_cid;
 
+        u32                     fcoe_init_cid;
+        u32                     fcoe_start_cid;
+        struct cnic_id_tbl      fcoe_cid_tbl;
+
         u32                     max_cid_space;
 
         /* per connection parameters */
@@ -356,11 +361,6 @@ struct bnx2x_bd_chain_next {
 #define BNX2X_CONTEXT_MEM_SIZE          1024
 #define BNX2X_FCOE_CID                  16
 
-/* iSCSI client IDs are 17, 19, 21, 23 */
-#define BNX2X_ISCSI_BASE_CL_ID          17
-#define BNX2X_ISCSI_CL_ID(vn)           (BNX2X_ISCSI_BASE_CL_ID + ((vn) << 1))
-
-#define BNX2X_ISCSI_L2_CID              17
 #define BNX2X_ISCSI_START_CID           18
 #define BNX2X_ISCSI_NUM_CONNECTIONS     128
 #define BNX2X_ISCSI_TASK_CONTEXT_SIZE   128
@@ -372,6 +372,10 @@ struct bnx2x_bd_chain_next {
 #define BNX2X_ISCSI_PBL_NOT_CACHED      0xff
 #define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED       0xff
 
+#define BNX2X_FCOE_NUM_CONNECTIONS      128
+
+#define BNX2X_FCOE_L5_CID_BASE          MAX_ISCSI_TBL_SZ
+
 #define BNX2X_CHIP_NUM_57710            0x164e
 #define BNX2X_CHIP_NUM_57711            0x164f
 #define BNX2X_CHIP_NUM_57711E           0x1650
@@ -427,6 +431,13 @@ struct bnx2x_bd_chain_next {
                  (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
                   offsetof(struct shmem2_region, field)))
 
+#define BNX2X_MF_CFG_ADDR(base, field)                          \
+                        ((base) + offsetof(struct mf_cfg, field))
+
+#ifndef ETH_MAX_RX_CLIENTS_E2
+#define ETH_MAX_RX_CLIENTS_E2           ETH_MAX_RX_CLIENTS_E1H
+#endif
+
 #define CNIC_PORT(cp)                   ((cp)->pfid & 1)
 #define CNIC_FUNC(cp)                   ((cp)->func)
 #define CNIC_PATH(cp)                   (!BNX2X_CHIP_IS_E2(cp->chip_id) ? 0 :\
@@ -439,7 +450,9 @@ struct bnx2x_bd_chain_next {
 #define BNX2X_SW_CID(x)                 (x & 0x1ffff)
 
 #define BNX2X_CL_QZONE_ID(cp, cli)                                      \
-                (cli + (CNIC_PORT(cp) * ETH_MAX_RX_CLIENTS_E1H))
+                (cli + (CNIC_PORT(cp) * (BNX2X_CHIP_IS_E2(cp->chip_id) ?\
+                                        ETH_MAX_RX_CLIENTS_E2 :         \
+                                        ETH_MAX_RX_CLIENTS_E1H)))
 
 #define TCP_TSTORM_OOO_DROP_AND_PROC_ACK        (0<<4)
 #endif
diff --git a/drivers/net/cnic_defs.h b/drivers/net/cnic_defs.h
index 328e8b2765a3..fdbc00415603 100644
--- a/drivers/net/cnic_defs.h
+++ b/drivers/net/cnic_defs.h
@@ -35,6 +35,40 @@
 #define L5CM_RAMROD_CMD_ID_SEARCHER_DELETE      (L5CM_RAMROD_CMD_ID_BASE + 14)
 #define L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD    (L5CM_RAMROD_CMD_ID_BASE + 15)
 
+#define FCOE_KCQE_OPCODE_INIT_FUNC                      (0x10)
+#define FCOE_KCQE_OPCODE_DESTROY_FUNC                   (0x11)
+#define FCOE_KCQE_OPCODE_STAT_FUNC                      (0x12)
+#define FCOE_KCQE_OPCODE_OFFLOAD_CONN                   (0x15)
+#define FCOE_KCQE_OPCODE_ENABLE_CONN                    (0x16)
+#define FCOE_KCQE_OPCODE_DISABLE_CONN                   (0x17)
+#define FCOE_KCQE_OPCODE_DESTROY_CONN                   (0x18)
+#define FCOE_KCQE_OPCODE_CQ_EVENT_NOTIFICATION  (0x20)
+#define FCOE_KCQE_OPCODE_FCOE_ERROR                             (0x21)
+
+#define FCOE_RAMROD_CMD_ID_INIT                 (FCOE_KCQE_OPCODE_INIT_FUNC)
+#define FCOE_RAMROD_CMD_ID_DESTROY              (FCOE_KCQE_OPCODE_DESTROY_FUNC)
+#define FCOE_RAMROD_CMD_ID_OFFLOAD_CONN         (FCOE_KCQE_OPCODE_OFFLOAD_CONN)
+#define FCOE_RAMROD_CMD_ID_ENABLE_CONN          (FCOE_KCQE_OPCODE_ENABLE_CONN)
+#define FCOE_RAMROD_CMD_ID_DISABLE_CONN         (FCOE_KCQE_OPCODE_DISABLE_CONN)
+#define FCOE_RAMROD_CMD_ID_DESTROY_CONN         (FCOE_KCQE_OPCODE_DESTROY_CONN)
+#define FCOE_RAMROD_CMD_ID_STAT                 (FCOE_KCQE_OPCODE_STAT_FUNC)
+#define FCOE_RAMROD_CMD_ID_TERMINATE_CONN       (0x81)
+
+#define FCOE_KWQE_OPCODE_INIT1                  (0)
+#define FCOE_KWQE_OPCODE_INIT2                  (1)
+#define FCOE_KWQE_OPCODE_INIT3                  (2)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN1  (3)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN2  (4)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN3  (5)
+#define FCOE_KWQE_OPCODE_OFFLOAD_CONN4  (6)
+#define FCOE_KWQE_OPCODE_ENABLE_CONN    (7)
+#define FCOE_KWQE_OPCODE_DISABLE_CONN   (8)
+#define FCOE_KWQE_OPCODE_DESTROY_CONN   (9)
+#define FCOE_KWQE_OPCODE_DESTROY                (10)
+#define FCOE_KWQE_OPCODE_STAT                   (11)
+
+#define FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE   (0x3)
+
 /* KCQ (kernel completion queue) response op codes */
 #define L4_KCQE_OPCODE_VALUE_CLOSE_COMP             (53)
 #define L4_KCQE_OPCODE_VALUE_RESET_COMP             (54)
@@ -683,6 +717,1496 @@ struct cstorm_iscsi_ag_context {
 };
 
 /*
+ * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and used in FCoE context section
+ */
+struct ustorm_fcoe_params {
+#if defined(__BIG_ENDIAN)
+        u16 fcoe_conn_id;
+        u16 flags;
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
+#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
+#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
+#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
+#define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7)
+#define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7
+#define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8)
+#define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8
+#define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9)
+#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9
+#elif defined(__LITTLE_ENDIAN)
+        u16 flags;
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0)
+#define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1)
+#define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3)
+#define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
+#define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4)
+#define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5)
+#define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6)
+#define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
+#define USTORM_FCOE_PARAMS_B_C2_VALID (0x1<<7)
+#define USTORM_FCOE_PARAMS_B_C2_VALID_SHIFT 7
+#define USTORM_FCOE_PARAMS_B_ACK_0 (0x1<<8)
+#define USTORM_FCOE_PARAMS_B_ACK_0_SHIFT 8
+#define USTORM_FCOE_PARAMS_RSRV0 (0x7F<<9)
+#define USTORM_FCOE_PARAMS_RSRV0_SHIFT 9
+        u16 fcoe_conn_id;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 hc_csdm_byte_en;
+        u8 func_id;
+        u8 port_id;
+        u8 vnic_id;
+#elif defined(__LITTLE_ENDIAN)
+        u8 vnic_id;
+        u8 port_id;
+        u8 func_id;
+        u8 hc_csdm_byte_en;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 rx_total_conc_seqs;
+        u16 rx_max_fc_pay_len;
+#elif defined(__LITTLE_ENDIAN)
+        u16 rx_max_fc_pay_len;
+        u16 rx_total_conc_seqs;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 ox_id;
+        u16 rx_max_conc_seqs;
+#elif defined(__LITTLE_ENDIAN)
+        u16 rx_max_conc_seqs;
+        u16 ox_id;
+#endif
+};
+
+/*
+ * FCoE 16-bits index structure
+ */
+struct fcoe_idx16_fields {
+        u16 fields;
+#define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0)
+#define FCOE_IDX16_FIELDS_IDX_SHIFT 0
+#define FCOE_IDX16_FIELDS_MSB (0x1<<15)
+#define FCOE_IDX16_FIELDS_MSB_SHIFT 15
+};
+
+/*
+ * FCoE 16-bits index union
+ */
+union fcoe_idx16_field_union {
+        struct fcoe_idx16_fields fields;
+        u16 val;
+};
+
+/*
+ * 4 regs size
+ */
+struct fcoe_bd_ctx {
+        u32 buf_addr_hi;
+        u32 buf_addr_lo;
+#if defined(__BIG_ENDIAN)
+        u16 rsrv0;
+        u16 buf_len;
+#elif defined(__LITTLE_ENDIAN)
+        u16 buf_len;
+        u16 rsrv0;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 rsrv1;
+        u16 flags;
+#elif defined(__LITTLE_ENDIAN)
+        u16 flags;
+        u16 rsrv1;
+#endif
+};
+
+/*
+ * Parameters required for placement according to SGL
+ */
+struct ustorm_fcoe_data_place {
+#if defined(__BIG_ENDIAN)
+        u16 cached_sge_off;
+        u8 cached_num_sges;
+        u8 cached_sge_idx;
+#elif defined(__LITTLE_ENDIAN)
+        u8 cached_sge_idx;
+        u8 cached_num_sges;
+        u16 cached_sge_off;
+#endif
+        struct fcoe_bd_ctx cached_sge[3];
+};
+
+struct fcoe_task_ctx_entry_txwr_rxrd {
+#if defined(__BIG_ENDIAN)
+        u16 verify_tx_seq;
+        u8 init_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
+        u8 tx_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
+#elif defined(__LITTLE_ENDIAN)
+        u8 tx_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4 (0xF<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV4_SHIFT 4
+        u8 init_flags;
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE (0x7<<0)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_TASK_TYPE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE (0x1<<3)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_DEV_TYPE_SHIFT 3
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE (0x1<<4)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_CLASS_TYPE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE (0x1<<5)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_SINGLE_SGE_SHIFT 5
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5 (0x3<<6)
+#define FCOE_TASK_CTX_ENTRY_TXWR_RXRD_RSRV5_SHIFT 6
+        u16 verify_tx_seq;
+#endif
+};
+
+struct fcoe_fcp_cmd_payload {
+        u32 opaque[8];
+};
+
+struct fcoe_fc_hdr {
+#if defined(__BIG_ENDIAN)
+        u8 cs_ctl;
+        u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 s_id[3];
+        u8 cs_ctl;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 r_ctl;
+        u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 d_id[3];
+        u8 r_ctl;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 seq_id;
+        u8 df_ctl;
+        u16 seq_cnt;
+#elif defined(__LITTLE_ENDIAN)
+        u16 seq_cnt;
+        u8 df_ctl;
+        u8 seq_id;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 type;
+        u8 f_ctl[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 f_ctl[3];
+        u8 type;
+#endif
+        u32 parameters;
+#if defined(__BIG_ENDIAN)
+        u16 ox_id;
+        u16 rx_id;
+#elif defined(__LITTLE_ENDIAN)
+        u16 rx_id;
+        u16 ox_id;
+#endif
+};
+
+struct fcoe_fc_frame {
+        struct fcoe_fc_hdr fc_hdr;
+        u32 reserved0[2];
+};
+
+union fcoe_cmd_flow_info {
+        struct fcoe_fcp_cmd_payload fcp_cmd_payload;
+        struct fcoe_fc_frame mp_fc_frame;
+};
+
+struct fcoe_read_flow_info {
+        struct fcoe_fc_hdr fc_data_in_hdr;
+        u32 reserved[2];
+};
+
+struct fcoe_fcp_xfr_rdy_payload {
+        u32 burst_len;
+        u32 data_ro;
+};
+
+struct fcoe_write_flow_info {
+        struct fcoe_fc_hdr fc_data_out_hdr;
+        struct fcoe_fcp_xfr_rdy_payload fcp_xfr_payload;
+};
+
+struct fcoe_fcp_rsp_flags {
+        u8 flags;
+#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0)
+#define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
+#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1)
+#define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2)
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3)
+#define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
+#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4)
+#define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
+#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5)
+#define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
+};
+
+struct fcoe_fcp_rsp_payload {
+        struct regpair reserved0;
+        u32 fcp_resid;
+#if defined(__BIG_ENDIAN)
+        u16 retry_delay_timer;
+        struct fcoe_fcp_rsp_flags fcp_flags;
+        u8 scsi_status_code;
+#elif defined(__LITTLE_ENDIAN)
+        u8 scsi_status_code;
+        struct fcoe_fcp_rsp_flags fcp_flags;
+        u16 retry_delay_timer;
+#endif
+        u32 fcp_rsp_len;
+        u32 fcp_sns_len;
+};
+
+/*
+ * Fixed size structure in order to plant it in Union structure
+ */
+struct fcoe_fcp_rsp_union {
+        struct fcoe_fcp_rsp_payload payload;
+        struct regpair reserved0;
+};
+
+/*
+ * Fixed size structure in order to plant it in Union structure
+ */
+struct fcoe_abts_rsp_union {
+        u32 r_ctl;
+        u32 abts_rsp_payload[7];
+};
+
+union fcoe_rsp_flow_info {
+        struct fcoe_fcp_rsp_union fcp_rsp;
+        struct fcoe_abts_rsp_union abts_rsp;
+};
+
+struct fcoe_cleanup_flow_info {
+#if defined(__BIG_ENDIAN)
+        u16 reserved1;
+        u16 task_id;
+#elif defined(__LITTLE_ENDIAN)
+        u16 task_id;
+        u16 reserved1;
+#endif
+        u32 reserved2[7];
+};
+
+/*
+ * 32 bytes used for general purposes
+ */
+union fcoe_general_task_ctx {
+        union fcoe_cmd_flow_info cmd_info;
+        struct fcoe_read_flow_info read_info;
+        struct fcoe_write_flow_info write_info;
+        union fcoe_rsp_flow_info rsp_info;
+        struct fcoe_cleanup_flow_info cleanup_info;
+        u32 comp_info[8];
+};
+
+struct fcoe_s_stat_ctx {
+        u8 flags;
+#define FCOE_S_STAT_CTX_ACTIVE (0x1<<0)
+#define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
+#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1)
+#define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
+#define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2)
+#define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
+#define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3)
+#define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
+#define FCOE_S_STAT_CTX_P_RJT (0x1<<4)
+#define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
+#define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5)
+#define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
+#define FCOE_S_STAT_CTX_RSRV1 (0x3<<6)
+#define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
+};
+
+/*
+ * Common section. Both TX and RX processing might write and read from it in different flows
+ */
+struct fcoe_task_ctx_entry_tx_rx_cmn {
+        u32 data_2_trns;
+        union fcoe_general_task_ctx general;
+#if defined(__BIG_ENDIAN)
+        u16 tx_low_seq_cnt;
+        struct fcoe_s_stat_ctx tx_s_stat;
+        u8 tx_seq_id;
+#elif defined(__LITTLE_ENDIAN)
+        u8 tx_seq_id;
+        struct fcoe_s_stat_ctx tx_s_stat;
+        u16 tx_low_seq_cnt;
+#endif
+        u32 common_flags;
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID (0xFFFFFF<<0)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_CID_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID (0x1<<24)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_VALID_SHIFT 24
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT (0x1<<25)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_SEQ_INIT_SHIFT 25
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER (0x1<<26)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_XFER_SHIFT 26
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF (0x1<<27)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_PEND_CONF_SHIFT 27
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME (0x1<<28)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_EXP_FIRST_FRAME_SHIFT 28
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV (0x7<<29)
+#define FCOE_TASK_CTX_ENTRY_TX_RX_CMN_RSRV_SHIFT 29
+};
+
+struct fcoe_task_ctx_entry_rxwr_txrd {
+#if defined(__BIG_ENDIAN)
+        u16 rx_id;
+        u16 rx_flags;
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
+#elif defined(__LITTLE_ENDIAN)
+        u16 rx_flags;
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE (0xF<<0)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RX_STATE_SHIFT 0
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE (0x7<<4)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_NUM_RQ_WQE_SHIFT 4
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ (0x1<<7)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_CONF_REQ_SHIFT 7
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME (0x1<<8)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_MISS_FRAME_SHIFT 8
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0 (0x7F<<9)
+#define FCOE_TASK_CTX_ENTRY_RXWR_TXRD_RESERVED0_SHIFT 9
+        u16 rx_id;
+#endif
+};
+
+struct fcoe_seq_ctx {
+#if defined(__BIG_ENDIAN)
+        u16 low_seq_cnt;
+        struct fcoe_s_stat_ctx s_stat;
+        u8 seq_id;
+#elif defined(__LITTLE_ENDIAN)
+        u8 seq_id;
+        struct fcoe_s_stat_ctx s_stat;
+        u16 low_seq_cnt;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 err_seq_cnt;
+        u16 high_seq_cnt;
+#elif defined(__LITTLE_ENDIAN)
+        u16 high_seq_cnt;
+        u16 err_seq_cnt;
+#endif
+        u32 low_exp_ro;
+        u32 high_exp_ro;
+};
+
+struct fcoe_single_sge_ctx {
+        struct regpair cur_buf_addr;
+#if defined(__BIG_ENDIAN)
+        u16 reserved0;
+        u16 cur_buf_rem;
+#elif defined(__LITTLE_ENDIAN)
+        u16 cur_buf_rem;
+        u16 reserved0;
+#endif
+};
+
+struct fcoe_mul_sges_ctx {
+        struct regpair cur_sge_addr;
+#if defined(__BIG_ENDIAN)
+        u8 sgl_size;
+        u8 cur_sge_idx;
+        u16 cur_sge_off;
+#elif defined(__LITTLE_ENDIAN)
+        u16 cur_sge_off;
+        u8 cur_sge_idx;
+        u8 sgl_size;
+#endif
+};
+
+union fcoe_sgl_ctx {
+        struct fcoe_single_sge_ctx single_sge;
+        struct fcoe_mul_sges_ctx mul_sges;
+};
+
+struct fcoe_task_ctx_entry_rx_only {
+        struct fcoe_seq_ctx seq_ctx;
+        struct fcoe_seq_ctx ooo_seq_ctx;
+        u32 rsrv3;
+        union fcoe_sgl_ctx sgl_ctx;
+};
+
+struct ustorm_fcoe_task_ctx_entry_rd {
+        struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
+        struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
+        struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
+        struct fcoe_task_ctx_entry_rx_only rx_wr;
+        u32 reserved;
+};
+
+/*
+ * Ustorm FCoE Storm Context
+ */
+struct ustorm_fcoe_st_context {
+        struct ustorm_fcoe_params fcoe_params;
+        struct regpair task_addr;
+        struct regpair cq_base_addr;
+        struct regpair rq_pbl_base;
+        struct regpair rq_cur_page_addr;
+        struct regpair confq_pbl_base_addr;
+        struct regpair conn_db_base;
+        struct regpair xfrq_base_addr;
+        struct regpair lcq_base_addr;
+#if defined(__BIG_ENDIAN)
+        union fcoe_idx16_field_union rq_cons;
+        union fcoe_idx16_field_union rq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        union fcoe_idx16_field_union rq_prod;
+        union fcoe_idx16_field_union rq_cons;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 xfrq_prod;
+        u16 cq_cons;
+#elif defined(__LITTLE_ENDIAN)
+        u16 cq_cons;
+        u16 xfrq_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 lcq_cons;
+        u16 hc_cram_address;
+#elif defined(__LITTLE_ENDIAN)
+        u16 hc_cram_address;
+        u16 lcq_cons;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 sq_xfrq_lcq_confq_size;
+        u16 confq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 confq_prod;
+        u16 sq_xfrq_lcq_confq_size;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 hc_csdm_agg_int;
+        u8 flags;
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0)
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2
+#define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3)
+#define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3
+        u8 available_rqes;
+        u8 sp_q_flush_cnt;
+#elif defined(__LITTLE_ENDIAN)
+        u8 sp_q_flush_cnt;
+        u8 available_rqes;
+        u8 flags;
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG (0x1<<0)
+#define USTORM_FCOE_ST_CONTEXT_MID_SEQ_PROC_FLAG_SHIFT 0
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG (0x1<<1)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_CONN_FLAG_SHIFT 1
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG (0x1<<2)
+#define USTORM_FCOE_ST_CONTEXT_CACHED_TCE_FLAG_SHIFT 2
+#define USTORM_FCOE_ST_CONTEXT_RSRV1 (0x1F<<3)
+#define USTORM_FCOE_ST_CONTEXT_RSRV1_SHIFT 3
+        u8 hc_csdm_agg_int;
+#endif
+        struct ustorm_fcoe_data_place data_place;
+        struct ustorm_fcoe_task_ctx_entry_rd tce;
+};
+
+/*
+ * The FCoE non-aggregative context of Tstorm
+ */
+struct tstorm_fcoe_st_context {
+        struct regpair reserved0;
+        struct regpair reserved1;
+};
+
+/*
+ * The fcoe aggregative context section of Xstorm
+ */
+struct xstorm_fcoe_extra_ag_context_section {
+#if defined(__BIG_ENDIAN)
+        u8 tcp_agg_vars1;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
+        u8 __reserved_da_cnt;
+        u16 __mtu;
+#elif defined(__LITTLE_ENDIAN)
+        u16 __mtu;
+        u8 __reserved_da_cnt;
+        u8 tcp_agg_vars1;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF (0x3<<4)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
+#endif
+        u32 __task_addr_lo;
+        u32 __task_addr_hi;
+        u32 __reserved55;
+        u32 __tx_prods;
+#if defined(__BIG_ENDIAN)
+        u8 __agg_val8_th;
+        u8 __agg_val8;
+        u16 tcp_agg_vars2;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14
+#elif defined(__LITTLE_ENDIAN)
+        u16 tcp_agg_vars2;
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN (0x1<<7)
+#define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_PBF_TX_SEQ_ACK_CF_EN_SHIFT 7
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF (0x3<<14)
+#define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX8_CF_SHIFT 14
+        u8 __agg_val8;
+        u8 __agg_val8_th;
+#endif
+        u32 __sq_base_addr_lo;
+        u32 __sq_base_addr_hi;
+        u32 __xfrq_base_addr_lo;
+        u32 __xfrq_base_addr_hi;
+#if defined(__BIG_ENDIAN)
+        u16 __xfrq_cons;
+        u16 __xfrq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 __xfrq_prod;
+        u16 __xfrq_cons;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 __tcp_agg_vars5;
+        u8 __tcp_agg_vars4;
+        u8 __tcp_agg_vars3;
+        u8 __reserved_force_pure_ack_cnt;
+#elif defined(__LITTLE_ENDIAN)
+        u8 __reserved_force_pure_ack_cnt;
+        u8 __tcp_agg_vars3;
+        u8 __tcp_agg_vars4;
+        u8 __tcp_agg_vars5;
+#endif
+        u32 __tcp_agg_vars6;
+#if defined(__BIG_ENDIAN)
+        u16 __agg_misc6;
+        u16 __tcp_agg_vars7;
+#elif defined(__LITTLE_ENDIAN)
+        u16 __tcp_agg_vars7;
+        u16 __agg_misc6;
+#endif
+        u32 __agg_val10;
+        u32 __agg_val10_th;
+#if defined(__BIG_ENDIAN)
+        u16 __reserved3;
+        u8 __reserved2;
+        u8 __da_only_cnt;
+#elif defined(__LITTLE_ENDIAN)
+        u8 __da_only_cnt;
+        u8 __reserved2;
+        u16 __reserved3;
+#endif
+};
+
+/*
+ * The fcoe aggregative context of Xstorm
+ */
+struct xstorm_fcoe_ag_context {
+#if defined(__BIG_ENDIAN)
+        u16 agg_val1;
+        u8 agg_vars1;
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
+        u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+        u8 __state;
+        u8 agg_vars1;
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5)
+#define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
+        u16 agg_val1;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 cdu_reserved;
+        u8 __agg_vars4;
+        u8 agg_vars3;
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
+        u8 agg_vars2;
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+#elif defined(__LITTLE_ENDIAN)
+        u8 agg_vars2;
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+        u8 agg_vars3;
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
+        u8 __agg_vars4;
+        u8 cdu_reserved;
+#endif
+        u32 more_to_send;
+#if defined(__BIG_ENDIAN)
+        u16 agg_vars5;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
+        u16 sq_cons;
+#elif defined(__LITTLE_ENDIAN)
+        u16 sq_cons;
+        u16 agg_vars5;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8)
+#define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
+#endif
+        struct xstorm_fcoe_extra_ag_context_section __extra_section;
+#if defined(__BIG_ENDIAN)
+        u16 agg_vars7;
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
+        u8 agg_val3_th;
+        u8 agg_vars6;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
+#elif defined(__LITTLE_ENDIAN)
+        u8 agg_vars6;
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6)
+#define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
+        u8 agg_val3_th;
+        u16 agg_vars7;
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4)
+#define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6)
+#define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8)
+#define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10)
+#define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15)
+#define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 __agg_val11_th;
+        u16 __agg_val11;
+#elif defined(__LITTLE_ENDIAN)
+        u16 __agg_val11;
+        u16 __agg_val11_th;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 __reserved1;
+        u8 __agg_val6_th;
+        u16 __confq_tx_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 __confq_tx_prod;
+        u8 __agg_val6_th;
+        u8 __reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 confq_cons;
+        u16 confq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 confq_prod;
+        u16 confq_cons;
+#endif
+        u32 agg_vars8;
+#define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX (0xFFFFFF<<0)
+#define __XSTORM_FCOE_AG_CONTEXT_CACHE_WQE_IDX_SHIFT 0
+#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24)
+#define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
+#if defined(__BIG_ENDIAN)
+        u16 ox_id;
+        u16 sq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 sq_prod;
+        u16 ox_id;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 agg_val3;
+        u8 agg_val6;
+        u8 agg_val5_th;
+        u8 agg_val5;
+#elif defined(__LITTLE_ENDIAN)
+        u8 agg_val5;
+        u8 agg_val5_th;
+        u8 agg_val6;
+        u8 agg_val3;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 __pbf_tx_seq_ack;
+        u16 agg_limit1;
+#elif defined(__LITTLE_ENDIAN)
+        u16 agg_limit1;
+        u16 __pbf_tx_seq_ack;
+#endif
+        u32 completion_seq;
+        u32 confq_pbl_base_lo;
+        u32 confq_pbl_base_hi;
+};
+
+/*
+ * The fcoe extra aggregative context section of Tstorm
+ */
+struct tstorm_fcoe_extra_ag_context_section {
+        u32 __agg_val1;
+#if defined(__BIG_ENDIAN)
+        u8 __tcp_agg_vars2;
+        u8 __agg_val3;
+        u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+        u16 __agg_val2;
+        u8 __agg_val3;
+        u8 __tcp_agg_vars2;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 __agg_val5;
+        u8 __agg_val6;
+        u8 __tcp_agg_vars3;
+#elif defined(__LITTLE_ENDIAN)
+        u8 __tcp_agg_vars3;
+        u8 __agg_val6;
+        u16 __agg_val5;
+#endif
+        u32 __lcq_prod;
+        u32 rtt_seq;
+        u32 rtt_time;
+        u32 __reserved66;
+        u32 wnd_right_edge;
+        u32 tcp_agg_vars1;
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22)
+#define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28)
+#define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
+        u32 snd_max;
+        u32 __lcq_cons;
+        u32 __reserved2;
+};
+
+/*
+ * The fcoe aggregative context of Tstorm
+ */
+struct tstorm_fcoe_ag_context {
+#if defined(__BIG_ENDIAN)
+        u16 ulp_credit;
+        u8 agg_vars1;
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+        u8 state;
+#elif defined(__LITTLE_ENDIAN)
+        u8 state;
+        u8 agg_vars1;
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+        u16 ulp_credit;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 __agg_val4;
+        u16 agg_vars2;
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
+#elif defined(__LITTLE_ENDIAN)
+        u16 agg_vars2;
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10)
+#define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11)
+#define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12)
+#define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13)
+#define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14)
+#define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15)
+#define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
+        u16 __agg_val4;
+#endif
+        struct tstorm_fcoe_extra_ag_context_section __extra_section;
+};
+
+/*
+ * The fcoe aggregative context of Ustorm
+ */
+struct ustorm_fcoe_ag_context {
+#if defined(__BIG_ENDIAN)
+        u8 __aux_counter_flags;
+        u8 agg_vars2;
+#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
+        u8 agg_vars1;
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
+#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
+        u8 state;
+#elif defined(__LITTLE_ENDIAN)
+        u8 state;
+        u8 agg_vars1;
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3)
+#define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4)
+#define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
+        u8 agg_vars2;
+#define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4)
+#define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
+        u8 __aux_counter_flags;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 cdu_usage;
+        u8 agg_misc2;
+        u16 pbf_tx_seq_ack;
+#elif defined(__LITTLE_ENDIAN)
+        u16 pbf_tx_seq_ack;
+        u8 agg_misc2;
+        u8 cdu_usage;
+#endif
+        u32 agg_misc4;
+#if defined(__BIG_ENDIAN)
+        u8 agg_val3_th;
+        u8 agg_val3;
+        u16 agg_misc3;
+#elif defined(__LITTLE_ENDIAN)
+        u16 agg_misc3;
+        u8 agg_val3;
+        u8 agg_val3_th;
+#endif
+        u32 expired_task_id;
+        u32 agg_misc4_th;
+#if defined(__BIG_ENDIAN)
+        u16 cq_prod;
+        u16 cq_cons;
+#elif defined(__LITTLE_ENDIAN)
+        u16 cq_cons;
+        u16 cq_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 __reserved2;
+        u8 decision_rules;
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
+        u8 decision_rule_enable_bits;
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+#elif defined(__LITTLE_ENDIAN)
+        u8 decision_rule_enable_bits;
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1)
+#define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2)
+#define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3)
+#define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4)
+#define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5)
+#define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6)
+#define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
+        u8 decision_rules;
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0)
+#define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3)
+#define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6)
+#define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7)
+#define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
+        u16 __reserved2;
+#endif
+};
+
+/*
+ * Ethernet context section
+ */
+struct xstorm_fcoe_eth_context_section {
+#if defined(__BIG_ENDIAN)
+        u8 remote_addr_4;
+        u8 remote_addr_5;
+        u8 local_addr_0;
+        u8 local_addr_1;
+#elif defined(__LITTLE_ENDIAN)
+        u8 local_addr_1;
+        u8 local_addr_0;
+        u8 remote_addr_5;
+        u8 remote_addr_4;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 remote_addr_0;
+        u8 remote_addr_1;
+        u8 remote_addr_2;
+        u8 remote_addr_3;
+#elif defined(__LITTLE_ENDIAN)
+        u8 remote_addr_3;
+        u8 remote_addr_2;
+        u8 remote_addr_1;
+        u8 remote_addr_0;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 reserved_vlan_type;
+        u16 params;
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
+#elif defined(__LITTLE_ENDIAN)
+        u16 params;
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13)
+#define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
+        u16 reserved_vlan_type;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 local_addr_2;
+        u8 local_addr_3;
+        u8 local_addr_4;
+        u8 local_addr_5;
+#elif defined(__LITTLE_ENDIAN)
+        u8 local_addr_5;
+        u8 local_addr_4;
+        u8 local_addr_3;
+        u8 local_addr_2;
+#endif
+};
+
+/*
+ * Flags used in FCoE context section - 1 byte
+ */
+struct xstorm_fcoe_context_flags {
+        u8 flags;
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED (0x1<<3)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_EXCHANGE_CLEANUP_DEFFERED_SHIFT 3
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED (0x1<<7)
+#define XSTORM_FCOE_CONTEXT_FLAGS_B_ABTS_DEFFERED_SHIFT 7
+};
+
+/*
+ * FCoE SQ element
+ */
+struct fcoe_sqe {
+        u16 wqe;
+#define FCOE_SQE_TASK_ID (0x7FFF<<0)
+#define FCOE_SQE_TASK_ID_SHIFT 0
+#define FCOE_SQE_TOGGLE_BIT (0x1<<15)
+#define FCOE_SQE_TOGGLE_BIT_SHIFT 15
+};
+
+/*
+ * FCoE XFRQ element
+ */
+struct fcoe_xfrqe {
+        u16 wqe;
+#define FCOE_XFRQE_TASK_ID (0x7FFF<<0)
+#define FCOE_XFRQE_TASK_ID_SHIFT 0
+#define FCOE_XFRQE_TOGGLE_BIT (0x1<<15)
+#define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
+};
+
+/*
+ * FCoE SQ\XFRQ element
+ */
+struct fcoe_cached_wqe {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_xfrqe xfrqe;
+        struct fcoe_sqe sqe;
+#elif defined(__LITTLE_ENDIAN)
+        struct fcoe_sqe sqe;
+        struct fcoe_xfrqe xfrqe;
+#endif
+};
+
+struct fcoe_task_ctx_entry_tx_only {
+        union fcoe_sgl_ctx sgl_ctx;
+};
+
+struct xstorm_fcoe_task_ctx_entry_rd {
+        struct fcoe_task_ctx_entry_tx_only tx_wr;
+        struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
+        struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
+        struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
+};
+
+/*
+ * Cached SGEs
+ */
+struct common_fcoe_sgl {
+        struct fcoe_bd_ctx sge[2];
+};
+
+/*
+ * FCP_DATA parameters required for transmission
+ */
+struct xstorm_fcoe_fcp_data {
+        u32 io_rem;
+#if defined(__BIG_ENDIAN)
+        u16 cached_sge_off;
+        u8 cached_num_sges;
+        u8 cached_sge_idx;
+#elif defined(__LITTLE_ENDIAN)
+        u8 cached_sge_idx;
+        u8 cached_num_sges;
+        u16 cached_sge_off;
+#endif
+        struct common_fcoe_sgl cached_sgl;
+};
+
+/*
+ * FCoE context section
+ */
+struct xstorm_fcoe_context_section {
+#if defined(__BIG_ENDIAN)
+        u8 vlan_flag;
+        u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 s_id[3];
+        u8 vlan_flag;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 func_id;
+        u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 d_id[3];
+        u8 func_id;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 sq_xfrq_lcq_confq_size;
+        u16 tx_max_fc_pay_len;
+#elif defined(__LITTLE_ENDIAN)
+        u16 tx_max_fc_pay_len;
+        u16 sq_xfrq_lcq_confq_size;
+#endif
+        u32 lcq_prod;
+#if defined(__BIG_ENDIAN)
+        u8 port_id;
+        u8 tx_max_conc_seqs_c3;
+        u8 seq_id;
+        struct xstorm_fcoe_context_flags tx_flags;
+#elif defined(__LITTLE_ENDIAN)
+        struct xstorm_fcoe_context_flags tx_flags;
+        u8 seq_id;
+        u8 tx_max_conc_seqs_c3;
+        u8 port_id;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 verify_tx_seq;
+        u8 func_mode;
+        u8 vnic_id;
+#elif defined(__LITTLE_ENDIAN)
+        u8 vnic_id;
+        u8 func_mode;
+        u16 verify_tx_seq;
+#endif
+        struct regpair confq_curr_page_addr;
+        struct fcoe_cached_wqe cached_wqe[8];
+        struct regpair lcq_base_addr;
+        struct xstorm_fcoe_task_ctx_entry_rd tce;
+        struct xstorm_fcoe_fcp_data fcp_data;
+#if defined(__BIG_ENDIAN)
+        u16 fcoe_tx_stat_params_ram_addr;
+        u16 cmng_port_ram_addr;
+#elif defined(__LITTLE_ENDIAN)
+        u16 cmng_port_ram_addr;
+        u16 fcoe_tx_stat_params_ram_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 fcp_cmd_pb_cmd_size;
+        u8 eth_hdr_size;
+        u16 pbf_addr;
+#elif defined(__LITTLE_ENDIAN)
+        u16 pbf_addr;
+        u8 eth_hdr_size;
+        u8 fcp_cmd_pb_cmd_size;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 reserved2[2];
+        u8 cos;
+        u8 dcb_version;
+#elif defined(__LITTLE_ENDIAN)
+        u8 dcb_version;
+        u8 cos;
+        u8 reserved2[2];
+#endif
+        u32 reserved3;
+        struct regpair reserved4[2];
+};
+
+/*
+ * Xstorm FCoE Storm Context
+ */
+struct xstorm_fcoe_st_context {
+        struct xstorm_fcoe_eth_context_section eth;
+        struct xstorm_fcoe_context_section fcoe;
+};
+
+/*
+ * Fcoe connection context
+ */
+struct fcoe_context {
+        struct ustorm_fcoe_st_context ustorm_st_context;
+        struct tstorm_fcoe_st_context tstorm_st_context;
+        struct xstorm_fcoe_ag_context xstorm_ag_context;
+        struct tstorm_fcoe_ag_context tstorm_ag_context;
+        struct ustorm_fcoe_ag_context ustorm_ag_context;
+        struct timers_block_context timers_context;
+        struct xstorm_fcoe_st_context xstorm_st_context;
+};
+
+/*
  * iSCSI context region, used only in iSCSI
  */
 struct ustorm_iscsi_rq_db {
@@ -2268,6 +3792,577 @@ struct iscsi_context {
 };
 
 /*
+ * FCoE KCQ CQE parameters
+ */
+union fcoe_kcqe_params {
+        u32 reserved0[4];
+};
+
+/*
+ * FCoE KCQ CQE
+ */
+struct fcoe_kcqe {
+        u32 fcoe_conn_id;
+        u32 completion_status;
+        u32 fcoe_conn_context_id;
+        union fcoe_kcqe_params params;
+#if defined(__BIG_ENDIAN)
+        u8 flags;
+#define FCOE_KCQE_RESERVED0 (0x7<<0)
+#define FCOE_KCQE_RESERVED0_SHIFT 0
+#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
+#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
+#define FCOE_KCQE_LAYER_CODE (0x7<<4)
+#define FCOE_KCQE_LAYER_CODE_SHIFT 4
+#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
+#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
+        u8 op_code;
+        u16 qe_self_seq;
+#elif defined(__LITTLE_ENDIAN)
+        u16 qe_self_seq;
+        u8 op_code;
+        u8 flags;
+#define FCOE_KCQE_RESERVED0 (0x7<<0)
+#define FCOE_KCQE_RESERVED0_SHIFT 0
+#define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3)
+#define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
+#define FCOE_KCQE_LAYER_CODE (0x7<<4)
+#define FCOE_KCQE_LAYER_CODE_SHIFT 4
+#define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7)
+#define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
+#endif
+};
+
+/*
+ * FCoE KWQE header
+ */
+struct fcoe_kwqe_header {
+#if defined(__BIG_ENDIAN)
+        u8 flags;
+#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
+#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
+#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
+#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
+#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
+        u8 op_code;
+#elif defined(__LITTLE_ENDIAN)
+        u8 op_code;
+        u8 flags;
+#define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0)
+#define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
+#define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4)
+#define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
+#define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
+#endif
+};
+
+/*
+ * FCoE firmware init request 1
+ */
+struct fcoe_kwqe_init1 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 num_tasks;
+#elif defined(__LITTLE_ENDIAN)
+        u16 num_tasks;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 task_list_pbl_addr_lo;
+        u32 task_list_pbl_addr_hi;
+        u32 dummy_buffer_addr_lo;
+        u32 dummy_buffer_addr_hi;
+#if defined(__BIG_ENDIAN)
+        u16 rq_num_wqes;
+        u16 sq_num_wqes;
+#elif defined(__LITTLE_ENDIAN)
+        u16 sq_num_wqes;
+        u16 rq_num_wqes;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 cq_num_wqes;
+        u16 rq_buffer_log_size;
+#elif defined(__LITTLE_ENDIAN)
+        u16 rq_buffer_log_size;
+        u16 cq_num_wqes;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 flags;
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
+#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
+        u8 num_sessions_log;
+        u16 mtu;
+#elif defined(__LITTLE_ENDIAN)
+        u16 mtu;
+        u8 num_sessions_log;
+        u8 flags;
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0)
+#define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4)
+#define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
+#define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7)
+#define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7
+#endif
+};
+
+/*
+ * FCoE firmware init request 2
+ */
+struct fcoe_kwqe_init2 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+        u16 reserved0;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 hash_tbl_pbl_addr_lo;
+        u32 hash_tbl_pbl_addr_hi;
+        u32 t2_hash_tbl_addr_lo;
+        u32 t2_hash_tbl_addr_hi;
+        u32 t2_ptr_hash_tbl_addr_lo;
+        u32 t2_ptr_hash_tbl_addr_hi;
+        u32 free_list_count;
+};
+
+/*
+ * FCoE firmware init request 3
+ */
+struct fcoe_kwqe_init3 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+        u16 reserved0;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 error_bit_map_lo;
+        u32 error_bit_map_hi;
+#if defined(__BIG_ENDIAN)
+        u8 reserved21[3];
+        u8 cached_session_enable;
+#elif defined(__LITTLE_ENDIAN)
+        u8 cached_session_enable;
+        u8 reserved21[3];
+#endif
+        u32 reserved2[4];
+};
+
+/*
+ * FCoE connection offload request 1
+ */
+struct fcoe_kwqe_conn_offload1 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 fcoe_conn_id;
+#elif defined(__LITTLE_ENDIAN)
+        u16 fcoe_conn_id;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 sq_addr_lo;
+        u32 sq_addr_hi;
+        u32 rq_pbl_addr_lo;
+        u32 rq_pbl_addr_hi;
+        u32 rq_first_pbe_addr_lo;
+        u32 rq_first_pbe_addr_hi;
+#if defined(__BIG_ENDIAN)
+        u16 reserved0;
+        u16 rq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 rq_prod;
+        u16 reserved0;
+#endif
+};
+
+/*
+ * FCoE connection offload request 2
+ */
+struct fcoe_kwqe_conn_offload2 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 tx_max_fc_pay_len;
+#elif defined(__LITTLE_ENDIAN)
+        u16 tx_max_fc_pay_len;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 cq_addr_lo;
+        u32 cq_addr_hi;
+        u32 xferq_addr_lo;
+        u32 xferq_addr_hi;
+        u32 conn_db_addr_lo;
+        u32 conn_db_addr_hi;
+        u32 reserved1;
+};
+
+/*
+ * FCoE connection offload request 3
+ */
+struct fcoe_kwqe_conn_offload3 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 vlan_tag;
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
+#elif defined(__LITTLE_ENDIAN)
+        u16 vlan_tag;
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
+        struct fcoe_kwqe_header hdr;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 tx_max_conc_seqs_c3;
+        u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 s_id[3];
+        u8 tx_max_conc_seqs_c3;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 flags;
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
+        u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 d_id[3];
+        u8 flags;
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7)
+#define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
+#endif
+        u32 reserved;
+        u32 confq_first_pbe_addr_lo;
+        u32 confq_first_pbe_addr_hi;
+#if defined(__BIG_ENDIAN)
+        u16 rx_max_fc_pay_len;
+        u16 tx_total_conc_seqs;
+#elif defined(__LITTLE_ENDIAN)
+        u16 tx_total_conc_seqs;
+        u16 rx_max_fc_pay_len;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 rx_open_seqs_exch_c3;
+        u8 rx_max_conc_seqs_c3;
+        u16 rx_total_conc_seqs;
+#elif defined(__LITTLE_ENDIAN)
+        u16 rx_total_conc_seqs;
+        u8 rx_max_conc_seqs_c3;
+        u8 rx_open_seqs_exch_c3;
+#endif
+};
+
+/*
+ * FCoE connection offload request 4
+ */
+struct fcoe_kwqe_conn_offload4 {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u8 reserved2;
+        u8 e_d_tov_timer_val;
+#elif defined(__LITTLE_ENDIAN)
+        u8 e_d_tov_timer_val;
+        u8 reserved2;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u8 src_mac_addr_lo32[4];
+#if defined(__BIG_ENDIAN)
+        u8 dst_mac_addr_hi16[2];
+        u8 src_mac_addr_hi16[2];
+#elif defined(__LITTLE_ENDIAN)
+        u8 src_mac_addr_hi16[2];
+        u8 dst_mac_addr_hi16[2];
+#endif
+        u8 dst_mac_addr_lo32[4];
+        u32 lcq_addr_lo;
+        u32 lcq_addr_hi;
+        u32 confq_pbl_base_addr_lo;
+        u32 confq_pbl_base_addr_hi;
+};
+
+/*
+ * FCoE connection enable request
+ */
+struct fcoe_kwqe_conn_enable_disable {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+        u16 reserved0;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u8 src_mac_addr_lo32[4];
+#if defined(__BIG_ENDIAN)
+        u16 vlan_tag;
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
+        u8 src_mac_addr_hi16[2];
+#elif defined(__LITTLE_ENDIAN)
+        u8 src_mac_addr_hi16[2];
+        u16 vlan_tag;
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13)
+#define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
+#endif
+        u8 dst_mac_addr_lo32[4];
+#if defined(__BIG_ENDIAN)
+        u16 reserved1;
+        u8 dst_mac_addr_hi16[2];
+#elif defined(__LITTLE_ENDIAN)
+        u8 dst_mac_addr_hi16[2];
+        u16 reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 vlan_flag;
+        u8 s_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 s_id[3];
+        u8 vlan_flag;
+#endif
+#if defined(__BIG_ENDIAN)
+        u8 reserved3;
+        u8 d_id[3];
+#elif defined(__LITTLE_ENDIAN)
+        u8 d_id[3];
+        u8 reserved3;
+#endif
+        u32 context_id;
+        u32 conn_id;
+        u32 reserved4;
+};
+
+/*
+ * FCoE connection destroy request
+ */
+struct fcoe_kwqe_conn_destroy {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+        u16 reserved0;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 context_id;
+        u32 conn_id;
+        u32 reserved1[5];
+};
+
+/*
+ * FCoe destroy request
+ */
+struct fcoe_kwqe_destroy {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+        u16 reserved0;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 reserved1[7];
+};
+
+/*
+ * FCoe statistics request
+ */
+struct fcoe_kwqe_stat {
+#if defined(__BIG_ENDIAN)
+        struct fcoe_kwqe_header hdr;
+        u16 reserved0;
+#elif defined(__LITTLE_ENDIAN)
+        u16 reserved0;
+        struct fcoe_kwqe_header hdr;
+#endif
+        u32 stat_params_addr_lo;
+        u32 stat_params_addr_hi;
+        u32 reserved1[5];
+};
+
+/*
+ * FCoE KWQ WQE
+ */
+union fcoe_kwqe {
+        struct fcoe_kwqe_init1 init1;
+        struct fcoe_kwqe_init2 init2;
+        struct fcoe_kwqe_init3 init3;
+        struct fcoe_kwqe_conn_offload1 conn_offload1;
+        struct fcoe_kwqe_conn_offload2 conn_offload2;
+        struct fcoe_kwqe_conn_offload3 conn_offload3;
+        struct fcoe_kwqe_conn_offload4 conn_offload4;
+        struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
+        struct fcoe_kwqe_conn_destroy conn_destroy;
+        struct fcoe_kwqe_destroy destroy;
+        struct fcoe_kwqe_stat statistics;
+};
+
+struct fcoe_task_ctx_entry {
+        struct fcoe_task_ctx_entry_tx_only tx_wr_only;
+        struct fcoe_task_ctx_entry_txwr_rxrd tx_wr_rx_rd;
+        struct fcoe_task_ctx_entry_tx_rx_cmn cmn;
+        struct fcoe_task_ctx_entry_rxwr_txrd rx_wr_tx_rd;
+        struct fcoe_task_ctx_entry_rx_only rx_wr_only;
+        u32 reserved[4];
+};
+
+/*
+ * FCoE connection enable\disable params passed by driver to FW in FCoE enable ramrod
+ */
+struct fcoe_conn_enable_disable_ramrod_params {
+        struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
+};
+
+
+/*
+ * FCoE connection offload params passed by driver to FW in FCoE offload ramrod
+ */
+struct fcoe_conn_offload_ramrod_params {
+        struct fcoe_kwqe_conn_offload1 offload_kwqe1;
+        struct fcoe_kwqe_conn_offload2 offload_kwqe2;
+        struct fcoe_kwqe_conn_offload3 offload_kwqe3;
+        struct fcoe_kwqe_conn_offload4 offload_kwqe4;
+};
+
+/*
+ * FCoE init params passed by driver to FW in FCoE init ramrod
+ */
+struct fcoe_init_ramrod_params {
+        struct fcoe_kwqe_init1 init_kwqe1;
+        struct fcoe_kwqe_init2 init_kwqe2;
+        struct fcoe_kwqe_init3 init_kwqe3;
+        struct regpair eq_addr;
+        struct regpair eq_next_page_addr;
+#if defined(__BIG_ENDIAN)
+        u16 sb_num;
+        u16 eq_prod;
+#elif defined(__LITTLE_ENDIAN)
+        u16 eq_prod;
+        u16 sb_num;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 reserved1;
+        u8 reserved0;
+        u8 sb_id;
+#elif defined(__LITTLE_ENDIAN)
+        u8 sb_id;
+        u8 reserved0;
+        u16 reserved1;
+#endif
+};
+
+
+/*
+ * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod
+ */
+struct fcoe_stat_ramrod_params {
+        struct fcoe_kwqe_stat stat_kwqe;
+};
+
+
+/*
+ * FCoE 16-bits vlan structure
+ */
+struct fcoe_vlan_fields {
+        u16 fields;
+#define FCOE_VLAN_FIELDS_VID (0xFFF<<0)
+#define FCOE_VLAN_FIELDS_VID_SHIFT 0
+#define FCOE_VLAN_FIELDS_CLI (0x1<<12)
+#define FCOE_VLAN_FIELDS_CLI_SHIFT 12
+#define FCOE_VLAN_FIELDS_PRI (0x7<<13)
+#define FCOE_VLAN_FIELDS_PRI_SHIFT 13
+};
+
+
+/*
+ * FCoE 16-bits vlan union
+ */
+union fcoe_vlan_field_union {
+        struct fcoe_vlan_fields fields;
+        u16 val;
+};
+
+/*
+ * Parameters used for Class 2 verifications
+ */
+struct ustorm_fcoe_c2_params {
+#if defined(__BIG_ENDIAN)
+        u16 e2e_credit;
+        u16 con_seq;
+#elif defined(__LITTLE_ENDIAN)
+        u16 con_seq;
+        u16 e2e_credit;
+#endif
+#if defined(__BIG_ENDIAN)
+        u16 ackq_prod;
+        u16 open_seq_per_exch;
+#elif defined(__LITTLE_ENDIAN)
+        u16 open_seq_per_exch;
+        u16 ackq_prod;
+#endif
+        struct regpair ackq_pbl_base;
+        struct regpair ackq_cur_seg;
+};
+
+/*
+ * Parameters used for Class 2 verifications
+ */
+struct xstorm_fcoe_c2_params {
+#if defined(__BIG_ENDIAN)
+        u16 reserved0;
+        u8 ackq_x_prod;
+        u8 max_conc_seqs_c2;
+#elif defined(__LITTLE_ENDIAN)
+        u8 max_conc_seqs_c2;
+        u8 ackq_x_prod;
+        u16 reserved0;
+#endif
+        struct regpair ackq_pbl_base;
+        struct regpair ackq_cur_seg;
+};
+
+/*
  * Buffer per connection, used in Tstorm
  */
 struct iscsi_conn_buf {
diff --git a/drivers/net/cnic_if.h b/drivers/net/cnic_if.h
index 0dbeaec4f03a..9f44e0ffe003 100644
--- a/drivers/net/cnic_if.h
+++ b/drivers/net/cnic_if.h
@@ -1,6 +1,6 @@
 /* cnic_if.h: Broadcom CNIC core network driver.
  *
- * Copyright (c) 2006-2010 Broadcom Corporation
+ * Copyright (c) 2006-2011 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -12,22 +12,31 @@
 #ifndef CNIC_IF_H
 #define CNIC_IF_H
 
-#define CNIC_MODULE_VERSION     "2.2.6"
-#define CNIC_MODULE_RELDATE     "Oct 12, 2010"
+#define CNIC_MODULE_VERSION     "2.2.12"
+#define CNIC_MODULE_RELDATE     "Jan 03, 2011"
 
 #define CNIC_ULP_RDMA           0
 #define CNIC_ULP_ISCSI          1
-#define CNIC_ULP_L4             2
-#define MAX_CNIC_ULP_TYPE_EXT   2
-#define MAX_CNIC_ULP_TYPE       3
+#define CNIC_ULP_FCOE           2
+#define CNIC_ULP_L4             3
+#define MAX_CNIC_ULP_TYPE_EXT   3
+#define MAX_CNIC_ULP_TYPE       4
 
 struct kwqe {
         u32 kwqe_op_flag;
 
+#define KWQE_QID_SHIFT          8
 #define KWQE_OPCODE_MASK        0x00ff0000
 #define KWQE_OPCODE_SHIFT       16
-#define KWQE_FLAGS_LAYER_SHIFT  28
 #define KWQE_OPCODE(x)          ((x & KWQE_OPCODE_MASK) >> KWQE_OPCODE_SHIFT)
+#define KWQE_LAYER_MASK                 0x70000000
+#define KWQE_LAYER_SHIFT                28
+#define KWQE_FLAGS_LAYER_MASK_L2        (2<<28)
+#define KWQE_FLAGS_LAYER_MASK_L3        (3<<28)
+#define KWQE_FLAGS_LAYER_MASK_L4        (4<<28)
+#define KWQE_FLAGS_LAYER_MASK_L5_RDMA   (5<<28)
+#define KWQE_FLAGS_LAYER_MASK_L5_ISCSI  (6<<28)
+#define KWQE_FLAGS_LAYER_MASK_L5_FCOE   (7<<28)
 
         u32 kwqe_info0;
         u32 kwqe_info1;
@@ -62,6 +71,7 @@ struct kcqe {
                 #define KCQE_FLAGS_LAYER_MASK_L4        (4<<28)
                 #define KCQE_FLAGS_LAYER_MASK_L5_RDMA   (5<<28)
                 #define KCQE_FLAGS_LAYER_MASK_L5_ISCSI  (6<<28)
+                #define KCQE_FLAGS_LAYER_MASK_L5_FCOE   (7<<28)
                 #define KCQE_FLAGS_NEXT                 (1<<31)
                 #define KCQE_FLAGS_OPCODE_MASK          (0xff<<16)
                 #define KCQE_FLAGS_OPCODE_SHIFT         (16)
@@ -301,7 +311,7 @@ struct cnic_ulp_ops {
         void (*cm_abort_complete)(struct cnic_sock *);
         void (*cm_remote_close)(struct cnic_sock *);
         void (*cm_remote_abort)(struct cnic_sock *);
-        void (*iscsi_nl_send_msg)(struct cnic_dev *dev, u32 msg_type,
+        int (*iscsi_nl_send_msg)(void *ulp_ctx, u32 msg_type,
                                   char *data, u16 data_size);
         struct module *owner;
         atomic_t ref_count;
diff --git a/drivers/net/cris/eth_v10.c b/drivers/net/cris/eth_v10.c
index 81475cc80e1c..80c2feeefec5 100644
--- a/drivers/net/cris/eth_v10.c
+++ b/drivers/net/cris/eth_v10.c
@@ -59,7 +59,6 @@ static struct sockaddr default_mac = {
 
 /* Information that need to be kept for each board. */
 struct net_local {
-        struct net_device_stats stats;
         struct mii_if_info mii_if;
 
         /* Tx control lock.  This protects the transmit buffer ring
@@ -1059,7 +1058,7 @@ e100_tx_timeout(struct net_device *dev)
 
         /* remember we got an error */
 
-        np->stats.tx_errors++;
+        dev->stats.tx_errors++;
 
         /* reset the TX DMA in case it has hung on something */
 
@@ -1157,7 +1156,7 @@ e100rxtx_interrupt(int irq, void *dev_id)
                          * allocate a new buffer to put a packet in.
                          */
                         e100_rx(dev);
-                        np->stats.rx_packets++;
+                        dev->stats.rx_packets++;
                         /* restart/continue on the channel, for safety */
                         *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, restart);
                         /* clear dma channel 1 eop/descr irq bits */
@@ -1173,8 +1172,8 @@ e100rxtx_interrupt(int irq, void *dev_id)
         /* Report any packets that have been sent */
         while (virt_to_phys(myFirstTxDesc) != *R_DMA_CH0_FIRST &&
                (netif_queue_stopped(dev) || myFirstTxDesc != myNextTxDesc)) {
-                np->stats.tx_bytes += myFirstTxDesc->skb->len;
-                np->stats.tx_packets++;
+                dev->stats.tx_bytes += myFirstTxDesc->skb->len;
+                dev->stats.tx_packets++;
 
                 /* dma is ready with the transmission of the data in tx_skb, so now
                    we can release the skb memory */
@@ -1197,7 +1196,6 @@ static irqreturn_t
 e100nw_interrupt(int irq, void *dev_id)
 {
         struct net_device *dev = (struct net_device *)dev_id;
-        struct net_local *np = netdev_priv(dev);
         unsigned long irqbits = *R_IRQ_MASK0_RD;
 
         /* check for underrun irq */
@@ -1205,13 +1203,13 @@ e100nw_interrupt(int irq, void *dev_id)
                 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr);
                 *R_NETWORK_TR_CTRL = network_tr_ctrl_shadow;
                 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, nop);
-                np->stats.tx_errors++;
+                dev->stats.tx_errors++;
                 D(printk("ethernet receiver underrun!\n"));
         }
 
         /* check for overrun irq */
         if (irqbits & IO_STATE(R_IRQ_MASK0_RD, overrun, active)) {
-                update_rx_stats(&np->stats); /* this will ack the irq */
+                update_rx_stats(&dev->stats); /* this will ack the irq */
                 D(printk("ethernet receiver overrun!\n"));
         }
         /* check for excessive collision irq */
@@ -1219,7 +1217,7 @@ e100nw_interrupt(int irq, void *dev_id)
                 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, clr);
                 *R_NETWORK_TR_CTRL = network_tr_ctrl_shadow;
                 SETS(network_tr_ctrl_shadow, R_NETWORK_TR_CTRL, clr_error, nop);
-                np->stats.tx_errors++;
+                dev->stats.tx_errors++;
                 D(printk("ethernet excessive collisions!\n"));
         }
         return IRQ_HANDLED;
@@ -1250,7 +1248,7 @@ e100_rx(struct net_device *dev)
         spin_unlock(&np->led_lock);
 
         length = myNextRxDesc->descr.hw_len - 4;
-        np->stats.rx_bytes += length;
+        dev->stats.rx_bytes += length;
 
 #ifdef ETHDEBUG
         printk("Got a packet of length %d:\n", length);
@@ -1268,7 +1266,7 @@ e100_rx(struct net_device *dev)
                 /* Small packet, copy data */
                 skb = dev_alloc_skb(length - ETHER_HEAD_LEN);
                 if (!skb) {
-                        np->stats.rx_errors++;
+                        dev->stats.rx_errors++;
                         printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
                         goto update_nextrxdesc;
                 }
@@ -1294,7 +1292,7 @@ e100_rx(struct net_device *dev)
                 int align;
                 struct sk_buff *new_skb = dev_alloc_skb(MAX_MEDIA_DATA_SIZE + 2 * L1_CACHE_BYTES);
                 if (!new_skb) {
-                        np->stats.rx_errors++;
+                        dev->stats.rx_errors++;
                         printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
                         goto update_nextrxdesc;
                 }
@@ -1333,8 +1331,6 @@ e100_rx(struct net_device *dev)
 static int
 e100_close(struct net_device *dev)
 {
-        struct net_local *np = netdev_priv(dev);
-
         printk(KERN_INFO "Closing %s.\n", dev->name);
 
         netif_stop_queue(dev);
@@ -1366,8 +1362,8 @@ e100_close(struct net_device *dev)
 
         /* Update the statistics here. */
 
-        update_rx_stats(&np->stats);
-        update_tx_stats(&np->stats);
+        update_rx_stats(&dev->stats);
+        update_tx_stats(&dev->stats);
 
         /* Stop speed/duplex timers */
         del_timer(&speed_timer);
@@ -1545,11 +1541,11 @@ e100_get_stats(struct net_device *dev)
 
         spin_lock_irqsave(&lp->lock, flags);
 
-        update_rx_stats(&lp->stats);
-        update_tx_stats(&lp->stats);
+        update_rx_stats(&dev->stats);
+        update_tx_stats(&dev->stats);
 
         spin_unlock_irqrestore(&lp->lock, flags);
-        return &lp->stats;
+        return &dev->stats;
 }
 
 /*
diff --git a/drivers/net/cxgb3/ael1002.c b/drivers/net/cxgb3/ael1002.c
index 35cd36729155..2028da95afa1 100644
--- a/drivers/net/cxgb3/ael1002.c
+++ b/drivers/net/cxgb3/ael1002.c
@@ -292,7 +292,7 @@ unknown:
  */
 static int ael2005_setup_sr_edc(struct cphy *phy)
 {
-        static struct reg_val regs[] = {
+        static const struct reg_val regs[] = {
                 { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x181 },
                 { MDIO_MMD_PMAPMD, 0xc010, 0xffff, 0x448a },
                 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5200 },
@@ -324,11 +324,11 @@ static int ael2005_setup_sr_edc(struct cphy *phy)
 
 static int ael2005_setup_twinax_edc(struct cphy *phy, int modtype)
 {
-        static struct reg_val regs[] = {
+        static const struct reg_val regs[] = {
                 { MDIO_MMD_PMAPMD, 0xc04a, 0xffff, 0x5a00 },
                 { 0, 0, 0, 0 }
         };
-        static struct reg_val preemphasis[] = {
+        static const struct reg_val preemphasis[] = {
                 { MDIO_MMD_PMAPMD, 0xc014, 0xffff, 0xfe16 },
                 { MDIO_MMD_PMAPMD, 0xc015, 0xffff, 0xa000 },
                 { 0, 0, 0, 0 }
@@ -393,7 +393,7 @@ static int ael2005_intr_clear(struct cphy *phy)
 
 static int ael2005_reset(struct cphy *phy, int wait)
 {
-        static struct reg_val regs0[] = {
+        static const struct reg_val regs0[] = {
                 { MDIO_MMD_PMAPMD, 0xc001, 0, 1 << 5 },
                 { MDIO_MMD_PMAPMD, 0xc017, 0, 1 << 5 },
                 { MDIO_MMD_PMAPMD, 0xc013, 0xffff, 0xf341 },
@@ -403,7 +403,7 @@ static int ael2005_reset(struct cphy *phy, int wait)
                 { MDIO_MMD_PMAPMD, 0xc210, 0xffff, 0 },
                 { 0, 0, 0, 0 }
         };
-        static struct reg_val regs1[] = {
+        static const struct reg_val regs1[] = {
                 { MDIO_MMD_PMAPMD, 0xca00, 0xffff, 0x0080 },
                 { MDIO_MMD_PMAPMD, 0xca12, 0xffff, 0 },
                 { 0, 0, 0, 0 }
@@ -522,7 +522,7 @@ int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
  */
 static int ael2020_setup_sr_edc(struct cphy *phy)
 {
-        static struct reg_val regs[] = {
+        static const struct reg_val regs[] = {
                 /* set CDR offset to 10 */
                 { MDIO_MMD_PMAPMD, 0xcc01, 0xffff, 0x488a },
 
@@ -551,20 +551,20 @@ static int ael2020_setup_sr_edc(struct cphy *phy)
 static int ael2020_setup_twinax_edc(struct cphy *phy, int modtype)
 {
         /* set uC to 40MHz */
-        static struct reg_val uCclock40MHz[] = {
+        static const struct reg_val uCclock40MHz[] = {
                 { MDIO_MMD_PMAPMD, 0xff28, 0xffff, 0x4001 },
                 { MDIO_MMD_PMAPMD, 0xff2a, 0xffff, 0x0002 },
                 { 0, 0, 0, 0 }
         };
 
         /* activate uC clock */
-        static struct reg_val uCclockActivate[] = {
+        static const struct reg_val uCclockActivate[] = {
                 { MDIO_MMD_PMAPMD, 0xd000, 0xffff, 0x5200 },
                 { 0, 0, 0, 0 }
         };
 
         /* set PC to start of SRAM and activate uC */
-        static struct reg_val uCactivate[] = {
+        static const struct reg_val uCactivate[] = {
                 { MDIO_MMD_PMAPMD, 0xd080, 0xffff, 0x0100 },
                 { MDIO_MMD_PMAPMD, 0xd092, 0xffff, 0x0000 },
                 { 0, 0, 0, 0 }
@@ -624,7 +624,7 @@ static int ael2020_get_module_type(struct cphy *phy, int delay_ms)
  */
 static int ael2020_intr_enable(struct cphy *phy)
 {
-        struct reg_val regs[] = {
+        static const struct reg_val regs[] = {
                 /* output Module's Loss Of Signal (LOS) to LED */
                 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CFG+AEL2020_GPIO_LSTAT,
                         0xffff, 0x4 },
@@ -664,7 +664,7 @@ static int ael2020_intr_enable(struct cphy *phy)
  */
 static int ael2020_intr_disable(struct cphy *phy)
 {
-        struct reg_val regs[] = {
+        static const struct reg_val regs[] = {
                 /* reset "link status" LED to "off" */
                 { MDIO_MMD_PMAPMD, AEL2020_GPIO_CTRL,
                         0xffff, 0xb << (AEL2020_GPIO_LSTAT*4) },
@@ -701,7 +701,7 @@ static int ael2020_intr_clear(struct cphy *phy)
         return err ? err : t3_phy_lasi_intr_clear(phy);
 }
 
-static struct reg_val ael2020_reset_regs[] = {
+static const struct reg_val ael2020_reset_regs[] = {
         /* Erratum #2: CDRLOL asserted, causing PMA link down status */
         { MDIO_MMD_PMAPMD, 0xc003, 0xffff, 0x3101 },
 
diff --git a/drivers/net/cxgb3/cxgb3_main.c b/drivers/net/cxgb3/cxgb3_main.c
index 046d846c652d..4d538a4e9d55 100644
--- a/drivers/net/cxgb3/cxgb3_main.c
+++ b/drivers/net/cxgb3/cxgb3_main.c
@@ -1359,6 +1359,7 @@ out:
 static int offload_close(struct t3cdev *tdev)
 {
         struct adapter *adapter = tdev2adap(tdev);
+        struct t3c_data *td = T3C_DATA(tdev);
 
         if (!test_bit(OFFLOAD_DEVMAP_BIT, &adapter->open_device_map))
                 return 0;
@@ -1369,7 +1370,7 @@ static int offload_close(struct t3cdev *tdev)
         sysfs_remove_group(&tdev->lldev->dev.kobj, &offload_attr_group);
 
         /* Flush work scheduled while releasing TIDs */
-        flush_scheduled_work();
+        flush_work_sync(&td->tid_release_task);
 
         tdev->lldev = NULL;
         cxgb3_set_dummy_ops(tdev);
@@ -3006,12 +3007,11 @@ static pci_ers_result_t t3_io_error_detected(struct pci_dev *pdev,
                                              pci_channel_state_t state)
 {
         struct adapter *adapter = pci_get_drvdata(pdev);
-        int ret;
 
         if (state == pci_channel_io_perm_failure)
                 return PCI_ERS_RESULT_DISCONNECT;
 
-        ret = t3_adapter_error(adapter, 0, 0);
+        t3_adapter_error(adapter, 0, 0);
 
         /* Request a slot reset. */
         return PCI_ERS_RESULT_NEED_RESET;
diff --git a/drivers/net/cxgb3/cxgb3_offload.c b/drivers/net/cxgb3/cxgb3_offload.c
index bcf07532953d..ef02aa68c926 100644
--- a/drivers/net/cxgb3/cxgb3_offload.c
+++ b/drivers/net/cxgb3/cxgb3_offload.c
@@ -1164,12 +1164,10 @@ static void cxgb_redirect(struct dst_entry *old, struct dst_entry *new)
  */
 void *cxgb_alloc_mem(unsigned long size)
 {
-        void *p = kmalloc(size, GFP_KERNEL);
+        void *p = kzalloc(size, GFP_KERNEL);
 
         if (!p)
-                p = vmalloc(size);
-        if (p)
-                memset(p, 0, size);
+                p = vzalloc(size);
         return p;
 }
 
diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index 0b197043bc34..d55db6b38e7b 100644
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -1562,7 +1562,7 @@ static void tp_intr_handler(struct adapter *adapter)
                 {0}
         };
 
-        static struct intr_info tp_intr_info_t3c[] = {
+        static const struct intr_info tp_intr_info_t3c[] = {
                 {0x1fffffff, "TP parity error", -1, 1},
                 {F_FLMRXFLSTEMPTY, "TP out of Rx pages", -1, 1},
                 {F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1},
diff --git a/drivers/net/cxgb4/cxgb4.h b/drivers/net/cxgb4/cxgb4.h
index 3d4253d311eb..01d49eaa44d2 100644
--- a/drivers/net/cxgb4/cxgb4.h
+++ b/drivers/net/cxgb4/cxgb4.h
@@ -482,11 +482,9 @@ struct adapter {
         void __iomem *regs;
         struct pci_dev *pdev;
         struct device *pdev_dev;
-        unsigned long registered_device_map;
         unsigned int fn;
         unsigned int flags;
 
-        const char *name;
         int msg_enable;
 
         struct adapter_params params;
@@ -497,7 +495,7 @@ struct adapter {
 
         struct {
                 unsigned short vec;
-                char desc[14];
+                char desc[IFNAMSIZ + 10];
         } msix_info[MAX_INGQ + 1];
 
         struct sge sge;
diff --git a/drivers/net/cxgb4/cxgb4_main.c b/drivers/net/cxgb4/cxgb4_main.c
index f50bc98310f8..059c1eec8c3f 100644
--- a/drivers/net/cxgb4/cxgb4_main.c
+++ b/drivers/net/cxgb4/cxgb4_main.c
@@ -522,39 +522,33 @@ static irqreturn_t t4_nondata_intr(int irq, void *cookie)
  */
 static void name_msix_vecs(struct adapter *adap)
 {
-        int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc) - 1;
+        int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 
         /* non-data interrupts */
-        snprintf(adap->msix_info[0].desc, n, "%s", adap->name);
-        adap->msix_info[0].desc[n] = 0;
+        snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 
         /* FW events */
-        snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", adap->name);
-        adap->msix_info[1].desc[n] = 0;
+        snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
+                 adap->port[0]->name);
 
         /* Ethernet queues */
         for_each_port(adap, j) {
                 struct net_device *d = adap->port[j];
                 const struct port_info *pi = netdev_priv(d);
 
-                for (i = 0; i < pi->nqsets; i++, msi_idx++) {
+                for (i = 0; i < pi->nqsets; i++, msi_idx++)
                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
                                  d->name, i);
-                        adap->msix_info[msi_idx].desc[n] = 0;
-                }
         }
 
         /* offload queues */
-        for_each_ofldrxq(&adap->sge, i) {
-                snprintf(adap->msix_info[msi_idx].desc, n, "%s-ofld%d",
-                         adap->name, i);
-                adap->msix_info[msi_idx++].desc[n] = 0;
-        }
-        for_each_rdmarxq(&adap->sge, i) {
-                snprintf(adap->msix_info[msi_idx].desc, n, "%s-rdma%d",
-                         adap->name, i);
-                adap->msix_info[msi_idx++].desc[n] = 0;
-        }
+        for_each_ofldrxq(&adap->sge, i)
+                snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
+                         adap->port[0]->name, i);
+
+        for_each_rdmarxq(&adap->sge, i)
+                snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
+                         adap->port[0]->name, i);
 }
 
 static int request_msix_queue_irqs(struct adapter *adap)
@@ -868,12 +862,10 @@ out:	release_firmware(fw);
  */
 void *t4_alloc_mem(size_t size)
 {
-        void *p = kmalloc(size, GFP_KERNEL);
+        void *p = kzalloc(size, GFP_KERNEL);
 
         if (!p)
-                p = vmalloc(size);
-        if (p)
-                memset(p, 0, size);
+                p = vzalloc(size);
         return p;
 }
 
@@ -1377,7 +1369,12 @@ static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
         } else if (type == FW_PORT_TYPE_KR)
                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
         else if (type == FW_PORT_TYPE_BP_AP)
-                v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC;
+                v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
+                     SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
+        else if (type == FW_PORT_TYPE_BP4_AP)
+                v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
+                     SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
+                     SUPPORTED_10000baseKX4_Full;
         else if (type == FW_PORT_TYPE_FIBER_XFI ||
                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
                 v |= SUPPORTED_FIBRE;
@@ -2668,7 +2665,7 @@ static int cxgb_up(struct adapter *adap)
         } else {
                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
-                                  adap->name, adap);
+                                  adap->port[0]->name, adap);
                 if (err)
                         goto irq_err;
         }
@@ -2719,10 +2716,6 @@ static int cxgb_open(struct net_device *dev)
                         return err;
         }
 
-        netif_set_real_num_tx_queues(dev, pi->nqsets);
-        err = netif_set_real_num_rx_queues(dev, pi->nqsets);
-        if (err)
-                return err;
         err = link_start(dev);
         if (!err)
                 netif_tx_start_all_queues(dev);
@@ -3491,49 +3484,53 @@ static int __devinit init_rss(struct adapter *adap)
         return 0;
 }
 
-static void __devinit print_port_info(struct adapter *adap)
+static void __devinit print_port_info(const struct net_device *dev)
 {
         static const char *base[] = {
                 "R XFI", "R XAUI", "T SGMII", "T XFI", "T XAUI", "KX4", "CX4",
-                "KX", "KR", "KR SFP+", "KR FEC"
+                "KX", "KR", "R SFP+", "KR/KX", "KR/KX/KX4"
         };
 
-        int i;
         char buf[80];
+        char *bufp = buf;
         const char *spd = "";
+        const struct port_info *pi = netdev_priv(dev);
+        const struct adapter *adap = pi->adapter;
 
         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
                 spd = " 2.5 GT/s";
         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
                 spd = " 5 GT/s";
 
-        for_each_port(adap, i) {
-                struct net_device *dev = adap->port[i];
-                const struct port_info *pi = netdev_priv(dev);
-                char *bufp = buf;
+        if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
+                bufp += sprintf(bufp, "100/");
+        if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
+                bufp += sprintf(bufp, "1000/");
+        if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
+                bufp += sprintf(bufp, "10G/");
+        if (bufp != buf)
+                --bufp;
+        sprintf(bufp, "BASE-%s", base[pi->port_type]);
 
-                if (!test_bit(i, &adap->registered_device_map))
-                        continue;
+        netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
+                    adap->params.vpd.id, adap->params.rev, buf,
+                    is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
+                    (adap->flags & USING_MSIX) ? " MSI-X" :
+                    (adap->flags & USING_MSI) ? " MSI" : "");
+        netdev_info(dev, "S/N: %s, E/C: %s\n",
+                    adap->params.vpd.sn, adap->params.vpd.ec);
+}
 
-                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
-                        bufp += sprintf(bufp, "100/");
-                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
-                        bufp += sprintf(bufp, "1000/");
-                if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
-                        bufp += sprintf(bufp, "10G/");
-                if (bufp != buf)
-                        --bufp;
-                sprintf(bufp, "BASE-%s", base[pi->port_type]);
+static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev)
+{
+        u16 v;
+        int pos;
 
-                netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
-                            adap->params.vpd.id, adap->params.rev,
-                            buf, is_offload(adap) ? "R" : "",
-                            adap->params.pci.width, spd,
-                            (adap->flags & USING_MSIX) ? " MSI-X" :
-                            (adap->flags & USING_MSI) ? " MSI" : "");
-                if (adap->name == dev->name)
-                        netdev_info(dev, "S/N: %s, E/C: %s\n",
-                                    adap->params.vpd.sn, adap->params.vpd.ec);
+        pos = pci_pcie_cap(dev);
+        if (pos > 0) {
+                pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v);
+                v |= PCI_EXP_DEVCTL_RELAX_EN;
+                pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v);
         }
 }
 
@@ -3611,6 +3608,7 @@ static int __devinit init_one(struct pci_dev *pdev,
         }
 
         pci_enable_pcie_error_reporting(pdev);
+        enable_pcie_relaxed_ordering(pdev);
         pci_set_master(pdev);
         pci_save_state(pdev);
 
@@ -3630,7 +3628,6 @@ static int __devinit init_one(struct pci_dev *pdev,
         adapter->pdev = pdev;
         adapter->pdev_dev = &pdev->dev;
         adapter->fn = func;
-        adapter->name = pci_name(pdev);
         adapter->msg_enable = dflt_msg_enable;
         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
 
@@ -3721,27 +3718,24 @@ static int __devinit init_one(struct pci_dev *pdev,
          * register at least one net device.
          */
         for_each_port(adapter, i) {
+                pi = adap2pinfo(adapter, i);
+                netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
+                netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
+
                 err = register_netdev(adapter->port[i]);
                 if (err)
-                        dev_warn(&pdev->dev,
-                                 "cannot register net device %s, skipping\n",
-                                 adapter->port[i]->name);
-                else {
-                        /*
-                         * Change the name we use for messages to the name of
-                         * the first successfully registered interface.
-                         */
-                        if (!adapter->registered_device_map)
-                                adapter->name = adapter->port[i]->name;
-
-                        __set_bit(i, &adapter->registered_device_map);
-                        adapter->chan_map[adap2pinfo(adapter, i)->tx_chan] = i;
-                }
+                        break;
+                adapter->chan_map[pi->tx_chan] = i;
+                print_port_info(adapter->port[i]);
         }
-        if (!adapter->registered_device_map) {
+        if (i == 0) {
                 dev_err(&pdev->dev, "could not register any net devices\n");
                 goto out_free_dev;
         }
+        if (err) {
+                dev_warn(&pdev->dev, "only %d net devices registered\n", i);
+                err = 0;
+        };
 
         if (cxgb4_debugfs_root) {
                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
@@ -3752,8 +3746,6 @@ static int __devinit init_one(struct pci_dev *pdev,
         if (is_offload(adapter))
                 attach_ulds(adapter);
 
-        print_port_info(adapter);
-
 sriov:
 #ifdef CONFIG_PCI_IOV
         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
@@ -3792,7 +3784,7 @@ static void __devexit remove_one(struct pci_dev *pdev)
                         detach_ulds(adapter);
 
                 for_each_port(adapter, i)
-                        if (test_bit(i, &adapter->registered_device_map))
+                        if (adapter->port[i]->reg_state == NETREG_REGISTERED)
                                 unregister_netdev(adapter->port[i]);
 
                 if (adapter->debugfs_root)
diff --git a/drivers/net/cxgb4/sge.c b/drivers/net/cxgb4/sge.c
index 17022258ed68..311471b439a8 100644
--- a/drivers/net/cxgb4/sge.c
+++ b/drivers/net/cxgb4/sge.c
@@ -579,6 +579,7 @@ static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
  *      @phys: the physical address of the allocated ring
  *      @metadata: address of the array holding the SW state for the ring
  *      @stat_size: extra space in HW ring for status information
+ *      @node: preferred node for memory allocations
  *
  *      Allocates resources for an SGE descriptor ring, such as Tx queues,
  *      free buffer lists, or response queues.  Each SGE ring requires
@@ -590,7 +591,7 @@ static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
  */
 static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
                         size_t sw_size, dma_addr_t *phys, void *metadata,
-                        size_t stat_size)
+                        size_t stat_size, int node)
 {
         size_t len = nelem * elem_size + stat_size;
         void *s = NULL;
@@ -599,7 +600,7 @@ static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
         if (!p)
                 return NULL;
         if (sw_size) {
-                s = kcalloc(nelem, sw_size, GFP_KERNEL);
+                s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node);
 
                 if (!s) {
                         dma_free_coherent(dev, len, p, *phys);
@@ -1982,7 +1983,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
         iq->size = roundup(iq->size, 16);
 
         iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0,
-                              &iq->phys_addr, NULL, 0);
+                              &iq->phys_addr, NULL, 0, NUMA_NO_NODE);
         if (!iq->desc)
                 return -ENOMEM;
 
@@ -2008,12 +2009,14 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
                 fl->size = roundup(fl->size, 8);
                 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
                                       sizeof(struct rx_sw_desc), &fl->addr,
-                                      &fl->sdesc, STAT_LEN);
+                                      &fl->sdesc, STAT_LEN, NUMA_NO_NODE);
                 if (!fl->desc)
                         goto fl_nomem;
 
                 flsz = fl->size / 8 + STAT_LEN / sizeof(struct tx_desc);
                 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN |
+                                            FW_IQ_CMD_FL0FETCHRO(1) |
+                                            FW_IQ_CMD_FL0DATARO(1) |
                                             FW_IQ_CMD_FL0PADEN);
                 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN(2) |
                                 FW_IQ_CMD_FL0FBMAX(3));
@@ -2093,7 +2096,8 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
 
         txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
                         sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
-                        &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
+                        &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN,
+                        netdev_queue_numa_node_read(netdevq));
         if (!txq->q.desc)
                 return -ENOMEM;
 
@@ -2106,6 +2110,7 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
         c.viid_pkd = htonl(FW_EQ_ETH_CMD_VIID(pi->viid));
         c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE(2) |
                                    FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |
+                                   FW_EQ_ETH_CMD_FETCHRO(1) |
                                    FW_EQ_ETH_CMD_IQID(iqid));
         c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN(2) |
                                   FW_EQ_ETH_CMD_FBMAX(3) |
@@ -2144,7 +2149,7 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
 
         txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
                                  sizeof(struct tx_desc), 0, &txq->q.phys_addr,
-                                 NULL, 0);
+                                 NULL, 0, NUMA_NO_NODE);
         if (!txq->q.desc)
                 return -ENOMEM;
 
@@ -2158,6 +2163,7 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
         c.physeqid_pkd = htonl(0);
         c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE(2) |
                                    FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) |
+                                   FW_EQ_CTRL_CMD_FETCHRO |
                                    FW_EQ_CTRL_CMD_IQID(iqid));
         c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN(2) |
                                   FW_EQ_CTRL_CMD_FBMAX(3) |
@@ -2194,7 +2200,8 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
 
         txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
                         sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
-                        &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN);
+                        &txq->q.phys_addr, &txq->q.sdesc, STAT_LEN,
+                        NUMA_NO_NODE);
         if (!txq->q.desc)
                 return -ENOMEM;
 
@@ -2207,6 +2214,7 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
                                  FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
         c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE(2) |
                                    FW_EQ_OFLD_CMD_PCIECHN(pi->tx_chan) |
+                                   FW_EQ_OFLD_CMD_FETCHRO(1) |
                                    FW_EQ_OFLD_CMD_IQID(iqid));
         c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN(2) |
                                   FW_EQ_OFLD_CMD_FBMAX(3) |
diff --git a/drivers/net/cxgb4/t4_hw.c b/drivers/net/cxgb4/t4_hw.c
index e97521c801ea..b9fd8a6f2cc4 100644
--- a/drivers/net/cxgb4/t4_hw.c
+++ b/drivers/net/cxgb4/t4_hw.c
@@ -183,7 +183,7 @@ static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
                     void *rpl, bool sleep_ok)
 {
-        static int delay[] = {
+        static const int delay[] = {
                 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
         };
 
@@ -330,18 +330,6 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
         return 0;
 }
 
-/*
- * Partial EEPROM Vital Product Data structure.  Includes only the ID and
- * VPD-R header.
- */
-struct t4_vpd_hdr {
-        u8  id_tag;
-        u8  id_len[2];
-        u8  id_data[ID_LEN];
-        u8  vpdr_tag;
-        u8  vpdr_len[2];
-};
-
 #define EEPROM_STAT_ADDR   0x7bfc
 #define VPD_BASE           0
 #define VPD_LEN            512
@@ -370,25 +358,38 @@ int t4_seeprom_wp(struct adapter *adapter, bool enable)
 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
 {
         int i, ret;
-        int ec, sn, v2;
+        int ec, sn;
         u8 vpd[VPD_LEN], csum;
-        unsigned int vpdr_len;
-        const struct t4_vpd_hdr *v;
+        unsigned int vpdr_len, kw_offset, id_len;
 
         ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(vpd), vpd);
         if (ret < 0)
                 return ret;
 
-        v = (const struct t4_vpd_hdr *)vpd;
-        vpdr_len = pci_vpd_lrdt_size(&v->vpdr_tag);
-        if (vpdr_len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
+        if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
+                dev_err(adapter->pdev_dev, "missing VPD ID string\n");
+                return -EINVAL;
+        }
+
+        id_len = pci_vpd_lrdt_size(vpd);
+        if (id_len > ID_LEN)
+                id_len = ID_LEN;
+
+        i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
+        if (i < 0) {
+                dev_err(adapter->pdev_dev, "missing VPD-R section\n");
+                return -EINVAL;
+        }
+
+        vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
+        kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
+        if (vpdr_len + kw_offset > VPD_LEN) {
                 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
                 return -EINVAL;
         }
 
 #define FIND_VPD_KW(var, name) do { \
-        var = pci_vpd_find_info_keyword(&v->id_tag, sizeof(struct t4_vpd_hdr), \
-                                        vpdr_len, name); \
+        var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
         if (var < 0) { \
                 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
                 return -EINVAL; \
@@ -408,11 +409,9 @@ static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
 
         FIND_VPD_KW(ec, "EC");
         FIND_VPD_KW(sn, "SN");
-        FIND_VPD_KW(v2, "V2");
 #undef FIND_VPD_KW
 
-        p->cclk = simple_strtoul(vpd + v2, NULL, 10);
-        memcpy(p->id, v->id_data, ID_LEN);
+        memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
         strim(p->id);
         memcpy(p->ec, vpd + ec, EC_LEN);
         strim(p->ec);
@@ -919,7 +918,7 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
  */
 static void pcie_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info sysbus_intr_info[] = {
+        static const struct intr_info sysbus_intr_info[] = {
                 { RNPP, "RXNP array parity error", -1, 1 },
                 { RPCP, "RXPC array parity error", -1, 1 },
                 { RCIP, "RXCIF array parity error", -1, 1 },
@@ -927,7 +926,7 @@ static void pcie_intr_handler(struct adapter *adapter)
                 { RFTP, "RXFT array parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info pcie_port_intr_info[] = {
+        static const struct intr_info pcie_port_intr_info[] = {
                 { TPCP, "TXPC array parity error", -1, 1 },
                 { TNPP, "TXNP array parity error", -1, 1 },
                 { TFTP, "TXFT array parity error", -1, 1 },
@@ -939,7 +938,7 @@ static void pcie_intr_handler(struct adapter *adapter)
                 { TDUE, "Tx uncorrectable data error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info pcie_intr_info[] = {
+        static const struct intr_info pcie_intr_info[] = {
                 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
                 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
                 { MSIDATAPERR, "MSI data parity error", -1, 1 },
@@ -991,7 +990,7 @@ static void pcie_intr_handler(struct adapter *adapter)
  */
 static void tp_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info tp_intr_info[] = {
+        static const struct intr_info tp_intr_info[] = {
                 { 0x3fffffff, "TP parity error", -1, 1 },
                 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
                 { 0 }
@@ -1008,7 +1007,7 @@ static void sge_intr_handler(struct adapter *adapter)
 {
         u64 v;
 
-        static struct intr_info sge_intr_info[] = {
+        static const struct intr_info sge_intr_info[] = {
                 { ERR_CPL_EXCEED_IQE_SIZE,
                   "SGE received CPL exceeding IQE size", -1, 1 },
                 { ERR_INVALID_CIDX_INC,
@@ -1053,7 +1052,7 @@ static void sge_intr_handler(struct adapter *adapter)
  */
 static void cim_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info cim_intr_info[] = {
+        static const struct intr_info cim_intr_info[] = {
                 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
                 { OBQPARERR, "CIM OBQ parity error", -1, 1 },
                 { IBQPARERR, "CIM IBQ parity error", -1, 1 },
@@ -1063,7 +1062,7 @@ static void cim_intr_handler(struct adapter *adapter)
                 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info cim_upintr_info[] = {
+        static const struct intr_info cim_upintr_info[] = {
                 { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
                 { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
                 { ILLWRINT, "CIM illegal write", -1, 1 },
@@ -1110,7 +1109,7 @@ static void cim_intr_handler(struct adapter *adapter)
  */
 static void ulprx_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info ulprx_intr_info[] = {
+        static const struct intr_info ulprx_intr_info[] = {
                 { 0x1800000, "ULPRX context error", -1, 1 },
                 { 0x7fffff, "ULPRX parity error", -1, 1 },
                 { 0 }
@@ -1125,7 +1124,7 @@ static void ulprx_intr_handler(struct adapter *adapter)
  */
 static void ulptx_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info ulptx_intr_info[] = {
+        static const struct intr_info ulptx_intr_info[] = {
                 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
                   0 },
                 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
@@ -1147,7 +1146,7 @@ static void ulptx_intr_handler(struct adapter *adapter)
  */
 static void pmtx_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info pmtx_intr_info[] = {
+        static const struct intr_info pmtx_intr_info[] = {
                 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
                 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
                 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
@@ -1169,7 +1168,7 @@ static void pmtx_intr_handler(struct adapter *adapter)
  */
 static void pmrx_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info pmrx_intr_info[] = {
+        static const struct intr_info pmrx_intr_info[] = {
                 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
                 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
                 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
@@ -1188,7 +1187,7 @@ static void pmrx_intr_handler(struct adapter *adapter)
  */
 static void cplsw_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info cplsw_intr_info[] = {
+        static const struct intr_info cplsw_intr_info[] = {
                 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
                 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
                 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
@@ -1207,7 +1206,7 @@ static void cplsw_intr_handler(struct adapter *adapter)
  */
 static void le_intr_handler(struct adapter *adap)
 {
-        static struct intr_info le_intr_info[] = {
+        static const struct intr_info le_intr_info[] = {
                 { LIPMISS, "LE LIP miss", -1, 0 },
                 { LIP0, "LE 0 LIP error", -1, 0 },
                 { PARITYERR, "LE parity error", -1, 1 },
@@ -1225,11 +1224,11 @@ static void le_intr_handler(struct adapter *adap)
  */
 static void mps_intr_handler(struct adapter *adapter)
 {
-        static struct intr_info mps_rx_intr_info[] = {
+        static const struct intr_info mps_rx_intr_info[] = {
                 { 0xffffff, "MPS Rx parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info mps_tx_intr_info[] = {
+        static const struct intr_info mps_tx_intr_info[] = {
                 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
                 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
                 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
@@ -1239,25 +1238,25 @@ static void mps_intr_handler(struct adapter *adapter)
                 { FRMERR, "MPS Tx framing error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info mps_trc_intr_info[] = {
+        static const struct intr_info mps_trc_intr_info[] = {
                 { FILTMEM, "MPS TRC filter parity error", -1, 1 },
                 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
                 { MISCPERR, "MPS TRC misc parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info mps_stat_sram_intr_info[] = {
+        static const struct intr_info mps_stat_sram_intr_info[] = {
                 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info mps_stat_tx_intr_info[] = {
+        static const struct intr_info mps_stat_tx_intr_info[] = {
                 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info mps_stat_rx_intr_info[] = {
+        static const struct intr_info mps_stat_rx_intr_info[] = {
                 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
                 { 0 }
         };
-        static struct intr_info mps_cls_intr_info[] = {
+        static const struct intr_info mps_cls_intr_info[] = {
                 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
                 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
                 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
@@ -1356,7 +1355,7 @@ static void ma_intr_handler(struct adapter *adap)
  */
 static void smb_intr_handler(struct adapter *adap)
 {
-        static struct intr_info smb_intr_info[] = {
+        static const struct intr_info smb_intr_info[] = {
                 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
                 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
                 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
@@ -1372,7 +1371,7 @@ static void smb_intr_handler(struct adapter *adap)
  */
 static void ncsi_intr_handler(struct adapter *adap)
 {
-        static struct intr_info ncsi_intr_info[] = {
+        static const struct intr_info ncsi_intr_info[] = {
                 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
                 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
                 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
@@ -1410,7 +1409,7 @@ static void xgmac_intr_handler(struct adapter *adap, int port)
  */
 static void pl_intr_handler(struct adapter *adap)
 {
-        static struct intr_info pl_intr_info[] = {
+        static const struct intr_info pl_intr_info[] = {
                 { FATALPERR, "T4 fatal parity error", -1, 1 },
                 { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
                 { 0 }
diff --git a/drivers/net/cxgb4/t4fw_api.h b/drivers/net/cxgb4/t4fw_api.h
index 940584a8a640..edcfd7ec7802 100644
--- a/drivers/net/cxgb4/t4fw_api.h
+++ b/drivers/net/cxgb4/t4fw_api.h
@@ -1239,6 +1239,7 @@ enum fw_port_type {
         FW_PORT_TYPE_KR,
         FW_PORT_TYPE_SFP,
         FW_PORT_TYPE_BP_AP,
+        FW_PORT_TYPE_BP4_AP,
 
         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
 };
diff --git a/drivers/net/cxgb4vf/adapter.h b/drivers/net/cxgb4vf/adapter.h
index 8ea01962e045..4766b4116b41 100644
--- a/drivers/net/cxgb4vf/adapter.h
+++ b/drivers/net/cxgb4vf/adapter.h
@@ -60,7 +60,7 @@ enum {
          * MSI-X interrupt index usage.
          */
         MSIX_FW         = 0,            /* MSI-X index for firmware Q */
-        MSIX_NIQFLINT   = 1,            /* MSI-X index base for Ingress Qs */
+        MSIX_IQFLINT    = 1,            /* MSI-X index base for Ingress Qs */
         MSIX_EXTRAS     = 1,
         MSIX_ENTRIES    = MAX_ETH_QSETS + MSIX_EXTRAS,
 
diff --git a/drivers/net/cxgb4vf/cxgb4vf_main.c b/drivers/net/cxgb4vf/cxgb4vf_main.c
index 6bf464afa90e..56166ae2059f 100644
--- a/drivers/net/cxgb4vf/cxgb4vf_main.c
+++ b/drivers/net/cxgb4vf/cxgb4vf_main.c
@@ -280,9 +280,7 @@ static void name_msix_vecs(struct adapter *adapter)
                 const struct port_info *pi = netdev_priv(dev);
                 int qs, msi;
 
-                for (qs = 0, msi = MSIX_NIQFLINT;
-                     qs < pi->nqsets;
-                     qs++, msi++) {
+                for (qs = 0, msi = MSIX_IQFLINT; qs < pi->nqsets; qs++, msi++) {
                         snprintf(adapter->msix_info[msi].desc, namelen,
                                  "%s-%d", dev->name, qs);
                         adapter->msix_info[msi].desc[namelen] = 0;
@@ -309,7 +307,7 @@ static int request_msix_queue_irqs(struct adapter *adapter)
         /*
          * Ethernet queues.
          */
-        msi = MSIX_NIQFLINT;
+        msi = MSIX_IQFLINT;
         for_each_ethrxq(s, rxq) {
                 err = request_irq(adapter->msix_info[msi].vec,
                                   t4vf_sge_intr_msix, 0,
@@ -337,7 +335,7 @@ static void free_msix_queue_irqs(struct adapter *adapter)
         int rxq, msi;
 
         free_irq(adapter->msix_info[MSIX_FW].vec, &s->fw_evtq);
-        msi = MSIX_NIQFLINT;
+        msi = MSIX_IQFLINT;
         for_each_ethrxq(s, rxq)
                 free_irq(adapter->msix_info[msi++].vec,
                          &s->ethrxq[rxq].rspq);
@@ -527,7 +525,7 @@ static int setup_sge_queues(struct adapter *adapter)
          * brought up at which point lots of things get nailed down
          * permanently ...
          */
-        msix = MSIX_NIQFLINT;
+        msix = MSIX_IQFLINT;
         for_each_port(adapter, pidx) {
                 struct net_device *dev = adapter->port[pidx];
                 struct port_info *pi = netdev_priv(dev);
@@ -751,13 +749,19 @@ static int cxgb4vf_open(struct net_device *dev)
         netif_set_real_num_tx_queues(dev, pi->nqsets);
         err = netif_set_real_num_rx_queues(dev, pi->nqsets);
         if (err)
-                return err;
-        set_bit(pi->port_id, &adapter->open_device_map);
+                goto err_unwind;
         err = link_start(dev);
         if (err)
-                return err;
+                goto err_unwind;
+
         netif_tx_start_all_queues(dev);
+        set_bit(pi->port_id, &adapter->open_device_map);
         return 0;
+
+err_unwind:
+        if (adapter->open_device_map == 0)
+                adapter_down(adapter);
+        return err;
 }
 
 /*
@@ -766,13 +770,12 @@ static int cxgb4vf_open(struct net_device *dev)
  */
 static int cxgb4vf_stop(struct net_device *dev)
 {
-        int ret;
         struct port_info *pi = netdev_priv(dev);
         struct adapter *adapter = pi->adapter;
 
         netif_tx_stop_all_queues(dev);
         netif_carrier_off(dev);
-        ret = t4vf_enable_vi(adapter, pi->viid, false, false);
+        t4vf_enable_vi(adapter, pi->viid, false, false);
         pi->link_cfg.link_ok = 0;
 
         clear_bit(pi->port_id, &adapter->open_device_map);
@@ -1365,6 +1368,8 @@ struct queue_port_stats {
         u64 rx_csum;
         u64 vlan_ex;
         u64 vlan_ins;
+        u64 lro_pkts;
+        u64 lro_merged;
 };
 
 /*
@@ -1402,6 +1407,8 @@ static const char stats_strings[][ETH_GSTRING_LEN] = {
         "RxCsumGood        ",
         "VLANextractions   ",
         "VLANinsertions    ",
+        "GROPackets        ",
+        "GROMerged         ",
 };
 
 /*
@@ -1451,6 +1458,8 @@ static void collect_sge_port_stats(const struct adapter *adapter,
                 stats->rx_csum += rxq->stats.rx_cso;
                 stats->vlan_ex += rxq->stats.vlan_ex;
                 stats->vlan_ins += txq->vlan_ins;
+                stats->lro_pkts += rxq->stats.lro_pkts;
+                stats->lro_merged += rxq->stats.lro_merged;
         }
 }
 
@@ -1547,14 +1556,19 @@ static void cxgb4vf_get_wol(struct net_device *dev,
 }
 
 /*
+ * TCP Segmentation Offload flags which we support.
+ */
+#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
+
+/*
  * Set TCP Segmentation Offloading feature capabilities.
  */
 static int cxgb4vf_set_tso(struct net_device *dev, u32 tso)
 {
         if (tso)
-                dev->features |= NETIF_F_TSO | NETIF_F_TSO6;
+                dev->features |= TSO_FLAGS;
         else
-                dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
+                dev->features &= ~TSO_FLAGS;
         return 0;
 }
 
@@ -2045,7 +2059,7 @@ static int __devinit setup_debugfs(struct adapter *adapter)
  * Tear down the /sys/kernel/debug/cxgb4vf sub-nodes created above.  We leave
  * it to our caller to tear down the directory (debugfs_root).
  */
-static void __devexit cleanup_debugfs(struct adapter *adapter)
+static void cleanup_debugfs(struct adapter *adapter)
 {
         BUG_ON(adapter->debugfs_root == NULL);
 
@@ -2063,7 +2077,7 @@ static void __devexit cleanup_debugfs(struct adapter *adapter)
  * adapter parameters we're going to be using and initialize basic adapter
  * hardware support.
  */
-static int adap_init0(struct adapter *adapter)
+static int __devinit adap_init0(struct adapter *adapter)
 {
         struct vf_resources *vfres = &adapter->params.vfres;
         struct sge_params *sge_params = &adapter->params.sge;
@@ -2494,7 +2508,6 @@ static int __devinit cxgb4vf_pci_probe(struct pci_dev *pdev,
                 version_printed = 1;
         }
 
-
         /*
          * Initialize generic PCI device state.
          */
@@ -2631,7 +2644,7 @@ static int __devinit cxgb4vf_pci_probe(struct pci_dev *pdev,
                 netif_carrier_off(netdev);
                 netdev->irq = pdev->irq;
 
-                netdev->features = (NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
+                netdev->features = (NETIF_F_SG | TSO_FLAGS |
                                     NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
                                     NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
                                     NETIF_F_GRO);
diff --git a/drivers/net/cxgb4vf/sge.c b/drivers/net/cxgb4vf/sge.c
index ecf0770bf0ff..e0b3d1bc2fdf 100644
--- a/drivers/net/cxgb4vf/sge.c
+++ b/drivers/net/cxgb4vf/sge.c
@@ -1568,6 +1568,9 @@ int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp,
         } else
                 skb_checksum_none_assert(skb);
 
+        /*
+         * Deliver the packet to the stack.
+         */
         if (unlikely(pkt->vlan_ex)) {
                 struct vlan_group *grp = pi->vlan_grp;
 
@@ -2143,7 +2146,7 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
 
                 /*
                  * Calculate the size of the hardware free list ring plus
-                 * status page (which the SGE will place at the end of the
+                 * Status Page (which the SGE will place after the end of the
                  * free list ring) in Egress Queue Units.
                  */
                 flsz = (fl->size / FL_PER_EQ_UNIT +
@@ -2240,8 +2243,8 @@ int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
         struct port_info *pi = netdev_priv(dev);
 
         /*
-         * Calculate the size of the hardware TX Queue (including the
-         * status age on the end) in units of TX Descriptors.
+         * Calculate the size of the hardware TX Queue (including the Status
+         * Page on the end of the TX Queue) in units of TX Descriptors.
          */
         nentries = txq->q.size + STAT_LEN / sizeof(struct tx_desc);
 
diff --git a/drivers/net/cxgb4vf/t4vf_hw.c b/drivers/net/cxgb4vf/t4vf_hw.c
index 19520afe1a12..0f51c80475ce 100644
--- a/drivers/net/cxgb4vf/t4vf_hw.c
+++ b/drivers/net/cxgb4vf/t4vf_hw.c
@@ -116,7 +116,7 @@ static void dump_mbox(struct adapter *adapter, const char *tag, u32 mbox_data)
 int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
                       void *rpl, bool sleep_ok)
 {
-        static int delay[] = {
+        static const int delay[] = {
                 1, 1, 3, 5, 10, 10, 20, 50, 100
         };
 
@@ -147,9 +147,20 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
         /*
          * Write the command array into the Mailbox Data register array and
          * transfer ownership of the mailbox to the firmware.
+         *
+         * For the VFs, the Mailbox Data "registers" are actually backed by
+         * T4's "MA" interface rather than PL Registers (as is the case for
+         * the PFs).  Because these are in different coherency domains, the
+         * write to the VF's PL-register-backed Mailbox Control can race in
+         * front of the writes to the MA-backed VF Mailbox Data "registers".
+         * So we need to do a read-back on at least one byte of the VF Mailbox
+         * Data registers before doing the write to the VF Mailbox Control
+         * register.
          */
         for (i = 0, p = cmd; i < size; i += 8)
                 t4_write_reg64(adapter, mbox_data + i, be64_to_cpu(*p++));
+        t4_read_reg(adapter, mbox_data);         /* flush write */
+
         t4_write_reg(adapter, mbox_ctl,
                      MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
         t4_read_reg(adapter, mbox_ctl);          /* flush write */
@@ -1300,7 +1311,7 @@ int t4vf_eth_eq_free(struct adapter *adapter, unsigned int eqid)
  */
 int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
 {
-        struct fw_cmd_hdr *cmd_hdr = (struct fw_cmd_hdr *)rpl;
+        const struct fw_cmd_hdr *cmd_hdr = (const struct fw_cmd_hdr *)rpl;
         u8 opcode = FW_CMD_OP_GET(be32_to_cpu(cmd_hdr->hi));
 
         switch (opcode) {
@@ -1308,7 +1319,8 @@ int t4vf_handle_fw_rpl(struct adapter *adapter, const __be64 *rpl)
                 /*
                  * Link/module state change message.
                  */
-                const struct fw_port_cmd *port_cmd = (void *)rpl;
+                const struct fw_port_cmd *port_cmd =
+                        (const struct fw_port_cmd *)rpl;
                 u32 word;
                 int action, port_id, link_ok, speed, fc, pidx;
 
diff --git a/drivers/net/depca.c b/drivers/net/depca.c
index 91b3846ffc8a..1b48b68ad4fd 100644
--- a/drivers/net/depca.c
+++ b/drivers/net/depca.c
@@ -1513,7 +1513,7 @@ static enum depca_type __init depca_shmem_probe (ulong *mem_start)
         return adapter;
 }
 
-static int __init depca_isa_probe (struct platform_device *device)
+static int __devinit depca_isa_probe (struct platform_device *device)
 {
         struct net_device *dev;
         struct depca_private *lp;
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 9f6aeefa06bf..2d4c4fc1d900 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c
@@ -1675,7 +1675,7 @@ dm9000_drv_remove(struct platform_device *pdev)
         platform_set_drvdata(pdev, NULL);
 
         unregister_netdev(ndev);
-        dm9000_release_board(pdev, (board_info_t *) netdev_priv(ndev));
+        dm9000_release_board(pdev, netdev_priv(ndev));
         free_netdev(ndev);              /* free device structure */
 
         dev_dbg(&pdev->dev, "released and freed device\n");
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c
index c7e242b69a18..aed223b1b897 100644
--- a/drivers/net/e1000/e1000_hw.c
+++ b/drivers/net/e1000/e1000_hw.c
@@ -130,10 +130,15 @@ static s32 e1000_set_phy_type(struct e1000_hw *hw)
                 if (hw->mac_type == e1000_82541 ||
                     hw->mac_type == e1000_82541_rev_2 ||
                     hw->mac_type == e1000_82547 ||
-                    hw->mac_type == e1000_82547_rev_2) {
+                    hw->mac_type == e1000_82547_rev_2)
                         hw->phy_type = e1000_phy_igp;
-                        break;
-                }
+                break;
+        case RTL8211B_PHY_ID:
+                hw->phy_type = e1000_phy_8211;
+                break;
+        case RTL8201N_PHY_ID:
+                hw->phy_type = e1000_phy_8201;
+                break;
         default:
                 /* Should never have loaded on this device */
                 hw->phy_type = e1000_phy_undefined;
@@ -318,6 +323,9 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
         case E1000_DEV_ID_82547GI:
                 hw->mac_type = e1000_82547_rev_2;
                 break;
+        case E1000_DEV_ID_INTEL_CE4100_GBE:
+                hw->mac_type = e1000_ce4100;
+                break;
         default:
                 /* Should never have loaded on this device */
                 return -E1000_ERR_MAC_TYPE;
@@ -372,6 +380,9 @@ void e1000_set_media_type(struct e1000_hw *hw)
                 case e1000_82542_rev2_1:
                         hw->media_type = e1000_media_type_fiber;
                         break;
+                case e1000_ce4100:
+                        hw->media_type = e1000_media_type_copper;
+                        break;
                 default:
                         status = er32(STATUS);
                         if (status & E1000_STATUS_TBIMODE) {
@@ -460,6 +471,7 @@ s32 e1000_reset_hw(struct e1000_hw *hw)
                 /* Reset is performed on a shadow of the control register */
                 ew32(CTRL_DUP, (ctrl | E1000_CTRL_RST));
                 break;
+        case e1000_ce4100:
         default:
                 ew32(CTRL, (ctrl | E1000_CTRL_RST));
                 break;
@@ -952,6 +964,67 @@ static s32 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
 }
 
 /**
+ * e1000_copper_link_rtl_setup - Copper link setup for e1000_phy_rtl series.
+ * @hw: Struct containing variables accessed by shared code
+ *
+ * Commits changes to PHY configuration by calling e1000_phy_reset().
+ */
+static s32 e1000_copper_link_rtl_setup(struct e1000_hw *hw)
+{
+        s32 ret_val;
+
+        /* SW reset the PHY so all changes take effect */
+        ret_val = e1000_phy_reset(hw);
+        if (ret_val) {
+                e_dbg("Error Resetting the PHY\n");
+                return ret_val;
+        }
+
+        return E1000_SUCCESS;
+}
+
+static s32 gbe_dhg_phy_setup(struct e1000_hw *hw)
+{
+        s32 ret_val;
+        u32 ctrl_aux;
+
+        switch (hw->phy_type) {
+        case e1000_phy_8211:
+                ret_val = e1000_copper_link_rtl_setup(hw);
+                if (ret_val) {
+                        e_dbg("e1000_copper_link_rtl_setup failed!\n");
+                        return ret_val;
+                }
+                break;
+        case e1000_phy_8201:
+                /* Set RMII mode */
+                ctrl_aux = er32(CTL_AUX);
+                ctrl_aux |= E1000_CTL_AUX_RMII;
+                ew32(CTL_AUX, ctrl_aux);
+                E1000_WRITE_FLUSH();
+
+                /* Disable the J/K bits required for receive */
+                ctrl_aux = er32(CTL_AUX);
+                ctrl_aux |= 0x4;
+                ctrl_aux &= ~0x2;
+                ew32(CTL_AUX, ctrl_aux);
+                E1000_WRITE_FLUSH();
+                ret_val = e1000_copper_link_rtl_setup(hw);
+
+                if (ret_val) {
+                        e_dbg("e1000_copper_link_rtl_setup failed!\n");
+                        return ret_val;
+                }
+                break;
+        default:
+                e_dbg("Error Resetting the PHY\n");
+                return E1000_ERR_PHY_TYPE;
+        }
+
+        return E1000_SUCCESS;
+}
+
+/**
  * e1000_copper_link_preconfig - early configuration for copper
  * @hw: Struct containing variables accessed by shared code
  *
@@ -1286,6 +1359,10 @@ static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
         if (hw->autoneg_advertised == 0)
                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 
+        /* IFE/RTL8201N PHY only supports 10/100 */
+        if (hw->phy_type == e1000_phy_8201)
+                hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
+
         e_dbg("Reconfiguring auto-neg advertisement params\n");
         ret_val = e1000_phy_setup_autoneg(hw);
         if (ret_val) {
@@ -1341,7 +1418,7 @@ static s32 e1000_copper_link_postconfig(struct e1000_hw *hw)
         s32 ret_val;
         e_dbg("e1000_copper_link_postconfig");
 
-        if (hw->mac_type >= e1000_82544) {
+        if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100)) {
                 e1000_config_collision_dist(hw);
         } else {
                 ret_val = e1000_config_mac_to_phy(hw);
@@ -1395,6 +1472,12 @@ static s32 e1000_setup_copper_link(struct e1000_hw *hw)
                 ret_val = e1000_copper_link_mgp_setup(hw);
                 if (ret_val)
                         return ret_val;
+        } else {
+                ret_val = gbe_dhg_phy_setup(hw);
+                if (ret_val) {
+                        e_dbg("gbe_dhg_phy_setup failed!\n");
+                        return ret_val;
+                }
         }
 
         if (hw->autoneg) {
@@ -1461,10 +1544,11 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
                 return ret_val;
 
         /* Read the MII 1000Base-T Control Register (Address 9). */
-        ret_val =
-            e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
+        ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
         if (ret_val)
                 return ret_val;
+        else if (hw->phy_type == e1000_phy_8201)
+                mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
 
         /* Need to parse both autoneg_advertised and fc and set up
          * the appropriate PHY registers.  First we will parse for
@@ -1577,9 +1661,14 @@ s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 
         e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
-        ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
-        if (ret_val)
-                return ret_val;
+        if (hw->phy_type == e1000_phy_8201) {
+                mii_1000t_ctrl_reg = 0;
+        } else {
+                ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
+                                              mii_1000t_ctrl_reg);
+                if (ret_val)
+                        return ret_val;
+        }
 
         return E1000_SUCCESS;
 }
@@ -1860,7 +1949,7 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
 
         /* 82544 or newer MAC, Auto Speed Detection takes care of
          * MAC speed/duplex configuration.*/
-        if (hw->mac_type >= e1000_82544)
+        if ((hw->mac_type >= e1000_82544) && (hw->mac_type != e1000_ce4100))
                 return E1000_SUCCESS;
 
         /* Read the Device Control Register and set the bits to Force Speed
@@ -1870,27 +1959,49 @@ static s32 e1000_config_mac_to_phy(struct e1000_hw *hw)
         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
 
-        /* Set up duplex in the Device Control and Transmit Control
-         * registers depending on negotiated values.
-         */
-        ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
-        if (ret_val)
-                return ret_val;
+        switch (hw->phy_type) {
+        case e1000_phy_8201:
+                ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
+                if (ret_val)
+                        return ret_val;
 
-        if (phy_data & M88E1000_PSSR_DPLX)
-                ctrl |= E1000_CTRL_FD;
-        else
-                ctrl &= ~E1000_CTRL_FD;
+                if (phy_data & RTL_PHY_CTRL_FD)
+                        ctrl |= E1000_CTRL_FD;
+                else
+                        ctrl &= ~E1000_CTRL_FD;
 
-        e1000_config_collision_dist(hw);
+                if (phy_data & RTL_PHY_CTRL_SPD_100)
+                        ctrl |= E1000_CTRL_SPD_100;
+                else
+                        ctrl |= E1000_CTRL_SPD_10;
 
-        /* Set up speed in the Device Control register depending on
-         * negotiated values.
-         */
-        if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
-                ctrl |= E1000_CTRL_SPD_1000;
-        else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
-                ctrl |= E1000_CTRL_SPD_100;
+                e1000_config_collision_dist(hw);
+                break;
+        default:
+                /* Set up duplex in the Device Control and Transmit Control
+                 * registers depending on negotiated values.
+                 */
+                ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
+                                             &phy_data);
+                if (ret_val)
+                        return ret_val;
+
+                if (phy_data & M88E1000_PSSR_DPLX)
+                        ctrl |= E1000_CTRL_FD;
+                else
+                        ctrl &= ~E1000_CTRL_FD;
+
+                e1000_config_collision_dist(hw);
+
+                /* Set up speed in the Device Control register depending on
+                 * negotiated values.
+                 */
+                if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
+                        ctrl |= E1000_CTRL_SPD_1000;
+                else if ((phy_data & M88E1000_PSSR_SPEED) ==
+                         M88E1000_PSSR_100MBS)
+                        ctrl |= E1000_CTRL_SPD_100;
+        }
 
         /* Write the configured values back to the Device Control Reg. */
         ew32(CTRL, ctrl);
@@ -2401,7 +2512,8 @@ s32 e1000_check_for_link(struct e1000_hw *hw)
                  * speed/duplex on the MAC to the current PHY speed/duplex
                  * settings.
                  */
-                if (hw->mac_type >= e1000_82544)
+                if ((hw->mac_type >= e1000_82544) &&
+                    (hw->mac_type != e1000_ce4100))
                         e1000_config_collision_dist(hw);
                 else {
                         ret_val = e1000_config_mac_to_phy(hw);
@@ -2738,7 +2850,7 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
 {
         u32 i;
         u32 mdic = 0;
-        const u32 phy_addr = 1;
+        const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
 
         e_dbg("e1000_read_phy_reg_ex");
 
@@ -2752,28 +2864,61 @@ static s32 e1000_read_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
                  * Control register.  The MAC will take care of interfacing with the
                  * PHY to retrieve the desired data.
                  */
-                mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                        (E1000_MDIC_OP_READ));
+                if (hw->mac_type == e1000_ce4100) {
+                        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (INTEL_CE_GBE_MDIC_OP_READ) |
+                                (INTEL_CE_GBE_MDIC_GO));
 
-                ew32(MDIC, mdic);
+                        writel(mdic, E1000_MDIO_CMD);
 
-                /* Poll the ready bit to see if the MDI read completed */
-                for (i = 0; i < 64; i++) {
-                        udelay(50);
-                        mdic = er32(MDIC);
-                        if (mdic & E1000_MDIC_READY)
-                                break;
-                }
-                if (!(mdic & E1000_MDIC_READY)) {
-                        e_dbg("MDI Read did not complete\n");
-                        return -E1000_ERR_PHY;
-                }
-                if (mdic & E1000_MDIC_ERROR) {
-                        e_dbg("MDI Error\n");
-                        return -E1000_ERR_PHY;
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 64; i++) {
+                                udelay(50);
+                                mdic = readl(E1000_MDIO_CMD);
+                                if (!(mdic & INTEL_CE_GBE_MDIC_GO))
+                                        break;
+                        }
+
+                        if (mdic & INTEL_CE_GBE_MDIC_GO) {
+                                e_dbg("MDI Read did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
+
+                        mdic = readl(E1000_MDIO_STS);
+                        if (mdic & INTEL_CE_GBE_MDIC_READ_ERROR) {
+                                e_dbg("MDI Read Error\n");
+                                return -E1000_ERR_PHY;
+                        }
+                        *phy_data = (u16) mdic;
+                } else {
+                        mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (E1000_MDIC_OP_READ));
+
+                        ew32(MDIC, mdic);
+
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 64; i++) {
+                                udelay(50);
+                                mdic = er32(MDIC);
+                                if (mdic & E1000_MDIC_READY)
+                                        break;
+                        }
+                        if (!(mdic & E1000_MDIC_READY)) {
+                                e_dbg("MDI Read did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
+                        if (mdic & E1000_MDIC_ERROR) {
+                                e_dbg("MDI Error\n");
+                                return -E1000_ERR_PHY;
+                        }
+                        *phy_data = (u16) mdic;
                 }
-                *phy_data = (u16) mdic;
         } else {
                 /* We must first send a preamble through the MDIO pin to signal the
                  * beginning of an MII instruction.  This is done by sending 32
@@ -2840,7 +2985,7 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
 {
         u32 i;
         u32 mdic = 0;
-        const u32 phy_addr = 1;
+        const u32 phy_addr = (hw->mac_type == e1000_ce4100) ? hw->phy_addr : 1;
 
         e_dbg("e1000_write_phy_reg_ex");
 
@@ -2850,27 +2995,54 @@ static s32 e1000_write_phy_reg_ex(struct e1000_hw *hw, u32 reg_addr,
         }
 
         if (hw->mac_type > e1000_82543) {
-                /* Set up Op-code, Phy Address, register address, and data intended
-                 * for the PHY register in the MDI Control register.  The MAC will take
-                 * care of interfacing with the PHY to send the desired data.
+                /* Set up Op-code, Phy Address, register address, and data
+                 * intended for the PHY register in the MDI Control register.
+                 * The MAC will take care of interfacing with the PHY to send
+                 * the desired data.
                  */
-                mdic = (((u32) phy_data) |
-                        (reg_addr << E1000_MDIC_REG_SHIFT) |
-                        (phy_addr << E1000_MDIC_PHY_SHIFT) |
-                        (E1000_MDIC_OP_WRITE));
+                if (hw->mac_type == e1000_ce4100) {
+                        mdic = (((u32) phy_data) |
+                                (reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (INTEL_CE_GBE_MDIC_OP_WRITE) |
+                                (INTEL_CE_GBE_MDIC_GO));
 
-                ew32(MDIC, mdic);
+                        writel(mdic, E1000_MDIO_CMD);
 
-                /* Poll the ready bit to see if the MDI read completed */
-                for (i = 0; i < 641; i++) {
-                        udelay(5);
-                        mdic = er32(MDIC);
-                        if (mdic & E1000_MDIC_READY)
-                                break;
-                }
-                if (!(mdic & E1000_MDIC_READY)) {
-                        e_dbg("MDI Write did not complete\n");
-                        return -E1000_ERR_PHY;
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 640; i++) {
+                                udelay(5);
+                                mdic = readl(E1000_MDIO_CMD);
+                                if (!(mdic & INTEL_CE_GBE_MDIC_GO))
+                                        break;
+                        }
+                        if (mdic & INTEL_CE_GBE_MDIC_GO) {
+                                e_dbg("MDI Write did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
+                } else {
+                        mdic = (((u32) phy_data) |
+                                (reg_addr << E1000_MDIC_REG_SHIFT) |
+                                (phy_addr << E1000_MDIC_PHY_SHIFT) |
+                                (E1000_MDIC_OP_WRITE));
+
+                        ew32(MDIC, mdic);
+
+                        /* Poll the ready bit to see if the MDI read
+                         * completed
+                         */
+                        for (i = 0; i < 641; i++) {
+                                udelay(5);
+                                mdic = er32(MDIC);
+                                if (mdic & E1000_MDIC_READY)
+                                        break;
+                        }
+                        if (!(mdic & E1000_MDIC_READY)) {
+                                e_dbg("MDI Write did not complete\n");
+                                return -E1000_ERR_PHY;
+                        }
                 }
         } else {
                 /* We'll need to use the SW defined pins to shift the write command
@@ -3048,6 +3220,11 @@ static s32 e1000_detect_gig_phy(struct e1000_hw *hw)
                 if (hw->phy_id == M88E1011_I_PHY_ID)
                         match = true;
                 break;
+        case e1000_ce4100:
+                if ((hw->phy_id == RTL8211B_PHY_ID) ||
+                    (hw->phy_id == RTL8201N_PHY_ID))
+                        match = true;
+                break;
         case e1000_82541:
         case e1000_82541_rev_2:
         case e1000_82547:
@@ -3291,6 +3468,9 @@ s32 e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info)
 
         if (hw->phy_type == e1000_phy_igp)
                 return e1000_phy_igp_get_info(hw, phy_info);
+        else if ((hw->phy_type == e1000_phy_8211) ||
+                 (hw->phy_type == e1000_phy_8201))
+                return E1000_SUCCESS;
         else
                 return e1000_phy_m88_get_info(hw, phy_info);
 }
@@ -3742,6 +3922,12 @@ static s32 e1000_do_read_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
 
         e_dbg("e1000_read_eeprom");
 
+        if (hw->mac_type == e1000_ce4100) {
+                GBE_CONFIG_FLASH_READ(GBE_CONFIG_BASE_VIRT, offset, words,
+                                      data);
+                return E1000_SUCCESS;
+        }
+
         /* If eeprom is not yet detected, do so now */
         if (eeprom->word_size == 0)
                 e1000_init_eeprom_params(hw);
@@ -3904,6 +4090,12 @@ static s32 e1000_do_write_eeprom(struct e1000_hw *hw, u16 offset, u16 words,
 
         e_dbg("e1000_write_eeprom");
 
+        if (hw->mac_type == e1000_ce4100) {
+                GBE_CONFIG_FLASH_WRITE(GBE_CONFIG_BASE_VIRT, offset, words,
+                                       data);
+                return E1000_SUCCESS;
+        }
+
         /* If eeprom is not yet detected, do so now */
         if (eeprom->word_size == 0)
                 e1000_init_eeprom_params(hw);
@@ -4892,11 +5084,11 @@ static s32 e1000_get_cable_length(struct e1000_hw *hw, u16 *min_length,
         } else if (hw->phy_type == e1000_phy_igp) {     /* For IGP PHY */
                 u16 cur_agc_value;
                 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
-                u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
-                    { IGP01E1000_PHY_AGC_A,
-                        IGP01E1000_PHY_AGC_B,
-                        IGP01E1000_PHY_AGC_C,
-                        IGP01E1000_PHY_AGC_D
+                static const u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
+                       IGP01E1000_PHY_AGC_A,
+                       IGP01E1000_PHY_AGC_B,
+                       IGP01E1000_PHY_AGC_C,
+                       IGP01E1000_PHY_AGC_D
                 };
                 /* Read the AGC registers for all channels */
                 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
@@ -5071,11 +5263,11 @@ static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw, bool link_up)
 {
         s32 ret_val;
         u16 phy_data, phy_saved_data, speed, duplex, i;
-        u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
-            { IGP01E1000_PHY_AGC_PARAM_A,
-                IGP01E1000_PHY_AGC_PARAM_B,
-                IGP01E1000_PHY_AGC_PARAM_C,
-                IGP01E1000_PHY_AGC_PARAM_D
+        static const u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = {
+               IGP01E1000_PHY_AGC_PARAM_A,
+               IGP01E1000_PHY_AGC_PARAM_B,
+               IGP01E1000_PHY_AGC_PARAM_C,
+               IGP01E1000_PHY_AGC_PARAM_D
         };
         u16 min_length, max_length;
 
diff --git a/drivers/net/e1000/e1000_hw.h b/drivers/net/e1000/e1000_hw.h
index 5e820f4e68b9..196eeda2dd6c 100644
--- a/drivers/net/e1000/e1000_hw.h
+++ b/drivers/net/e1000/e1000_hw.h
@@ -52,6 +52,7 @@ typedef enum {
         e1000_82545,
         e1000_82545_rev_3,
         e1000_82546,
+        e1000_ce4100,
         e1000_82546_rev_3,
         e1000_82541,
         e1000_82541_rev_2,
@@ -209,9 +210,11 @@ typedef enum {
 } e1000_1000t_rx_status;
 
 typedef enum {
-    e1000_phy_m88 = 0,
-    e1000_phy_igp,
-    e1000_phy_undefined = 0xFF
+        e1000_phy_m88 = 0,
+        e1000_phy_igp,
+        e1000_phy_8211,
+        e1000_phy_8201,
+        e1000_phy_undefined = 0xFF
 } e1000_phy_type;
 
 typedef enum {
@@ -442,6 +445,7 @@ void e1000_io_write(struct e1000_hw *hw, unsigned long port, u32 value);
 #define E1000_DEV_ID_82547EI             0x1019
 #define E1000_DEV_ID_82547EI_MOBILE      0x101A
 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
+#define E1000_DEV_ID_INTEL_CE4100_GBE    0x2E6E
 
 #define NODE_ADDRESS_SIZE 6
 #define ETH_LENGTH_OF_ADDRESS 6
@@ -808,6 +812,16 @@ struct e1000_ffvt_entry {
 #define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
 #define E1000_FLA      0x0001C  /* Flash Access - RW */
 #define E1000_MDIC     0x00020  /* MDI Control - RW */
+
+extern void __iomem *ce4100_gbe_mdio_base_virt;
+#define INTEL_CE_GBE_MDIO_RCOMP_BASE    (ce4100_gbe_mdio_base_virt)
+#define E1000_MDIO_STS  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0)
+#define E1000_MDIO_CMD  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 4)
+#define E1000_MDIO_DRV  (INTEL_CE_GBE_MDIO_RCOMP_BASE + 8)
+#define E1000_MDC_CMD   (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0xC)
+#define E1000_RCOMP_CTL (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x20)
+#define E1000_RCOMP_STS (INTEL_CE_GBE_MDIO_RCOMP_BASE + 0x24)
+
 #define E1000_SCTL     0x00024  /* SerDes Control - RW */
 #define E1000_FEXTNVM  0x00028  /* Future Extended NVM register */
 #define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
@@ -820,6 +834,34 @@ struct e1000_ffvt_entry {
 #define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
 #define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
 #define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
+
+/* Auxiliary Control Register. This register is CE4100 specific,
+ * RMII/RGMII function is switched by this register - RW
+ * Following are bits definitions of the Auxiliary Control Register
+ */
+#define E1000_CTL_AUX  0x000E0
+#define E1000_CTL_AUX_END_SEL_SHIFT     10
+#define E1000_CTL_AUX_ENDIANESS_SHIFT   8
+#define E1000_CTL_AUX_RGMII_RMII_SHIFT  0
+
+/* descriptor and packet transfer use CTL_AUX.ENDIANESS */
+#define E1000_CTL_AUX_DES_PKT   (0x0 << E1000_CTL_AUX_END_SEL_SHIFT)
+/* descriptor use CTL_AUX.ENDIANESS, packet use default */
+#define E1000_CTL_AUX_DES       (0x1 << E1000_CTL_AUX_END_SEL_SHIFT)
+/* descriptor use default, packet use CTL_AUX.ENDIANESS */
+#define E1000_CTL_AUX_PKT       (0x2 << E1000_CTL_AUX_END_SEL_SHIFT)
+/* all use CTL_AUX.ENDIANESS */
+#define E1000_CTL_AUX_ALL       (0x3 << E1000_CTL_AUX_END_SEL_SHIFT)
+
+#define E1000_CTL_AUX_RGMII     (0x0 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
+#define E1000_CTL_AUX_RMII      (0x1 << E1000_CTL_AUX_RGMII_RMII_SHIFT)
+
+/* LW little endian, Byte big endian */
+#define E1000_CTL_AUX_LWLE_BBE  (0x0 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+#define E1000_CTL_AUX_LWLE_BLE  (0x1 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+#define E1000_CTL_AUX_LWBE_BBE  (0x2 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+#define E1000_CTL_AUX_LWBE_BLE  (0x3 << E1000_CTL_AUX_ENDIANESS_SHIFT)
+
 #define E1000_RCTL     0x00100  /* RX Control - RW */
 #define E1000_RDTR1    0x02820  /* RX Delay Timer (1) - RW */
 #define E1000_RDBAL1   0x02900  /* RX Descriptor Base Address Low (1) - RW */
@@ -1011,6 +1053,7 @@ struct e1000_ffvt_entry {
  * in more current versions of the 8254x. Despite the difference in location,
  * the registers function in the same manner.
  */
+#define E1000_82542_CTL_AUX  E1000_CTL_AUX
 #define E1000_82542_CTRL     E1000_CTRL
 #define E1000_82542_CTRL_DUP E1000_CTRL_DUP
 #define E1000_82542_STATUS   E1000_STATUS
@@ -1571,6 +1614,11 @@ struct e1000_hw {
 #define E1000_MDIC_INT_EN    0x20000000
 #define E1000_MDIC_ERROR     0x40000000
 
+#define INTEL_CE_GBE_MDIC_OP_WRITE      0x04000000
+#define INTEL_CE_GBE_MDIC_OP_READ       0x00000000
+#define INTEL_CE_GBE_MDIC_GO            0x80000000
+#define INTEL_CE_GBE_MDIC_READ_ERROR    0x80000000
+
 #define E1000_KUMCTRLSTA_MASK           0x0000FFFF
 #define E1000_KUMCTRLSTA_OFFSET         0x001F0000
 #define E1000_KUMCTRLSTA_OFFSET_SHIFT   16
@@ -2871,6 +2919,11 @@ struct e1000_host_command_info {
 #define M88E1111_I_PHY_ID  0x01410CC0
 #define L1LXT971A_PHY_ID   0x001378E0
 
+#define RTL8211B_PHY_ID    0x001CC910
+#define RTL8201N_PHY_ID    0x8200
+#define RTL_PHY_CTRL_FD    0x0100 /* Full duplex.0=half; 1=full */
+#define RTL_PHY_CTRL_SPD_100    0x200000 /* Force 100Mb */
+
 /* Bits...
  * 15-5: page
  * 4-0: register offset
diff --git a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
index e02c5d17af07..de69c54301c1 100644
--- a/drivers/net/e1000/e1000_main.c
+++ b/drivers/net/e1000/e1000_main.c
@@ -28,6 +28,12 @@
 
 #include "e1000.h"
 #include <net/ip6_checksum.h>
+#include <linux/io.h>
+
+/* Intel Media SOC GbE MDIO physical base address */
+static unsigned long ce4100_gbe_mdio_base_phy;
+/* Intel Media SOC GbE MDIO virtual base address */
+void __iomem *ce4100_gbe_mdio_base_virt;
 
 char e1000_driver_name[] = "e1000";
 static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver";
@@ -79,6 +85,7 @@ static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
         INTEL_E1000_ETHERNET_DEVICE(0x108A),
         INTEL_E1000_ETHERNET_DEVICE(0x1099),
         INTEL_E1000_ETHERNET_DEVICE(0x10B5),
+        INTEL_E1000_ETHERNET_DEVICE(0x2E6E),
         /* required last entry */
         {0,}
 };
@@ -459,6 +466,7 @@ static void e1000_power_down_phy(struct e1000_adapter *adapter)
                 case e1000_82545:
                 case e1000_82545_rev_3:
                 case e1000_82546:
+                case e1000_ce4100:
                 case e1000_82546_rev_3:
                 case e1000_82541:
                 case e1000_82541_rev_2:
@@ -573,6 +581,7 @@ void e1000_reset(struct e1000_adapter *adapter)
         case e1000_82545:
         case e1000_82545_rev_3:
         case e1000_82546:
+        case e1000_ce4100:
         case e1000_82546_rev_3:
                 pba = E1000_PBA_48K;
                 break;
@@ -894,6 +903,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
         static int global_quad_port_a = 0; /* global ksp3 port a indication */
         int i, err, pci_using_dac;
         u16 eeprom_data = 0;
+        u16 tmp = 0;
         u16 eeprom_apme_mask = E1000_EEPROM_APME;
         int bars, need_ioport;
 
@@ -971,11 +981,13 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                  */
                 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
                 pci_using_dac = 1;
-        } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
-                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
         } else {
-                pr_err("No usable DMA config, aborting\n");
-                goto err_dma;
+                err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (err) {
+                        pr_err("No usable DMA config, aborting\n");
+                        goto err_dma;
+                }
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
         }
 
         netdev->netdev_ops = &e1000_netdev_ops;
@@ -994,6 +1006,14 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
                 goto err_sw_init;
 
         err = -EIO;
+        if (hw->mac_type == e1000_ce4100) {
+                ce4100_gbe_mdio_base_phy = pci_resource_start(pdev, BAR_1);
+                ce4100_gbe_mdio_base_virt = ioremap(ce4100_gbe_mdio_base_phy,
+                                                pci_resource_len(pdev, BAR_1));
+
+                if (!ce4100_gbe_mdio_base_virt)
+                        goto err_mdio_ioremap;
+        }
 
         if (hw->mac_type >= e1000_82543) {
                 netdev->features = NETIF_F_SG |
@@ -1133,6 +1153,20 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
         adapter->wol = adapter->eeprom_wol;
         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
 
+        /* Auto detect PHY address */
+        if (hw->mac_type == e1000_ce4100) {
+                for (i = 0; i < 32; i++) {
+                        hw->phy_addr = i;
+                        e1000_read_phy_reg(hw, PHY_ID2, &tmp);
+                        if (tmp == 0 || tmp == 0xFF) {
+                                if (i == 31)
+                                        goto err_eeprom;
+                                continue;
+                        } else
+                                break;
+                }
+        }
+
         /* reset the hardware with the new settings */
         e1000_reset(adapter);
 
@@ -1169,6 +1203,8 @@ err_eeprom:
         kfree(adapter->rx_ring);
 err_dma:
 err_sw_init:
+err_mdio_ioremap:
+        iounmap(ce4100_gbe_mdio_base_virt);
         iounmap(hw->hw_addr);
 err_ioremap:
         free_netdev(netdev);
@@ -1407,6 +1443,7 @@ static bool e1000_check_64k_bound(struct e1000_adapter *adapter, void *start,
         /* First rev 82545 and 82546 need to not allow any memory
          * write location to cross 64k boundary due to errata 23 */
         if (hw->mac_type == e1000_82545 ||
+            hw->mac_type == e1000_ce4100 ||
             hw->mac_type == e1000_82546) {
                 return ((begin ^ (end - 1)) >> 16) != 0 ? false : true;
         }
@@ -1429,13 +1466,12 @@ static int e1000_setup_tx_resources(struct e1000_adapter *adapter,
         int size;
 
         size = sizeof(struct e1000_buffer) * txdr->count;
-        txdr->buffer_info = vmalloc(size);
+        txdr->buffer_info = vzalloc(size);
         if (!txdr->buffer_info) {
                 e_err(probe, "Unable to allocate memory for the Tx descriptor "
                       "ring\n");
                 return -ENOMEM;
         }
-        memset(txdr->buffer_info, 0, size);
 
         /* round up to nearest 4K */
 
@@ -1625,13 +1661,12 @@ static int e1000_setup_rx_resources(struct e1000_adapter *adapter,
         int size, desc_len;
 
         size = sizeof(struct e1000_buffer) * rxdr->count;
-        rxdr->buffer_info = vmalloc(size);
+        rxdr->buffer_info = vzalloc(size);
         if (!rxdr->buffer_info) {
                 e_err(probe, "Unable to allocate memory for the Rx descriptor "
                       "ring\n");
                 return -ENOMEM;
         }
-        memset(rxdr->buffer_info, 0, size);
 
         desc_len = sizeof(struct e1000_rx_desc);
 
@@ -2726,7 +2761,7 @@ static bool e1000_tx_csum(struct e1000_adapter *adapter,
                 break;
         }
 
-        css = skb_transport_offset(skb);
+        css = skb_checksum_start_offset(skb);
 
         i = tx_ring->next_to_use;
         buffer_info = &tx_ring->buffer_info[i];
diff --git a/drivers/net/e1000/e1000_osdep.h b/drivers/net/e1000/e1000_osdep.h
index edd1c75aa895..55c1711f1688 100644
--- a/drivers/net/e1000/e1000_osdep.h
+++ b/drivers/net/e1000/e1000_osdep.h
@@ -34,12 +34,21 @@
 #ifndef _E1000_OSDEP_H_
 #define _E1000_OSDEP_H_
 
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/delay.h>
 #include <asm/io.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
+
+#define CONFIG_RAM_BASE         0x60000
+#define GBE_CONFIG_OFFSET       0x0
+
+#define GBE_CONFIG_RAM_BASE \
+        ((unsigned int)(CONFIG_RAM_BASE + GBE_CONFIG_OFFSET))
+
+#define GBE_CONFIG_BASE_VIRT    phys_to_virt(GBE_CONFIG_RAM_BASE)
+
+#define GBE_CONFIG_FLASH_WRITE(base, offset, count, data) \
+        (iowrite16_rep(base + offset, data, count))
+
+#define GBE_CONFIG_FLASH_READ(base, offset, count, data) \
+        (ioread16_rep(base + (offset << 1), data, count))
 
 #define er32(reg)                                                       \
         (readl(hw->hw_addr + ((hw->mac_type >= e1000_82543)             \
diff --git a/drivers/net/e1000/e1000_param.c b/drivers/net/e1000/e1000_param.c
index 10d8d98bb797..1301eba8b57a 100644
--- a/drivers/net/e1000/e1000_param.c
+++ b/drivers/net/e1000/e1000_param.c
@@ -352,12 +352,13 @@ void __devinit e1000_check_options(struct e1000_adapter *adapter)
         }
         { /* Flow Control */
 
-                struct e1000_opt_list fc_list[] =
-                        {{ E1000_FC_NONE,    "Flow Control Disabled" },
-                         { E1000_FC_RX_PAUSE,"Flow Control Receive Only" },
-                         { E1000_FC_TX_PAUSE,"Flow Control Transmit Only" },
-                         { E1000_FC_FULL,    "Flow Control Enabled" },
-                         { E1000_FC_DEFAULT, "Flow Control Hardware Default" }};
+                static const struct e1000_opt_list fc_list[] = {
+                       { E1000_FC_NONE, "Flow Control Disabled" },
+                       { E1000_FC_RX_PAUSE, "Flow Control Receive Only" },
+                       { E1000_FC_TX_PAUSE, "Flow Control Transmit Only" },
+                       { E1000_FC_FULL, "Flow Control Enabled" },
+                       { E1000_FC_DEFAULT, "Flow Control Hardware Default" }
+                };
 
                 opt = (struct e1000_option) {
                         .type = list_option,
diff --git a/drivers/net/e1000e/82571.c b/drivers/net/e1000e/82571.c
index a655beb69320..1397da118f0d 100644
--- a/drivers/net/e1000e/82571.c
+++ b/drivers/net/e1000e/82571.c
@@ -52,6 +52,7 @@
                               (ID_LED_DEF1_DEF2))
 
 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
+#define AN_RETRY_COUNT          5 /* Autoneg Retry Count value */
 #define E1000_BASE1000T_STATUS          10
 #define E1000_IDLE_ERROR_COUNT_MASK     0xFF
 #define E1000_RECEIVE_ERROR_COUNTER     21
@@ -74,6 +75,11 @@ static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
 static s32 e1000_led_on_82574(struct e1000_hw *hw);
 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
+static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
+static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
+static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
+static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
+static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
 
 /**
  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
@@ -107,6 +113,10 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
         case e1000_82574:
         case e1000_82583:
                 phy->type                = e1000_phy_bm;
+                phy->ops.acquire = e1000_get_hw_semaphore_82574;
+                phy->ops.release = e1000_put_hw_semaphore_82574;
+                phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
+                phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
                 break;
         default:
                 return -E1000_ERR_PHY;
@@ -115,29 +125,36 @@ static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
 
         /* This can only be done after all function pointers are setup. */
         ret_val = e1000_get_phy_id_82571(hw);
+        if (ret_val) {
+                e_dbg("Error getting PHY ID\n");
+                return ret_val;
+        }
 
         /* Verify phy id */
         switch (hw->mac.type) {
         case e1000_82571:
         case e1000_82572:
                 if (phy->id != IGP01E1000_I_PHY_ID)
-                        return -E1000_ERR_PHY;
+                        ret_val = -E1000_ERR_PHY;
                 break;
         case e1000_82573:
                 if (phy->id != M88E1111_I_PHY_ID)
-                        return -E1000_ERR_PHY;
+                        ret_val = -E1000_ERR_PHY;
                 break;
         case e1000_82574:
         case e1000_82583:
                 if (phy->id != BME1000_E_PHY_ID_R2)
-                        return -E1000_ERR_PHY;
+                        ret_val = -E1000_ERR_PHY;
                 break;
         default:
-                return -E1000_ERR_PHY;
+                ret_val = -E1000_ERR_PHY;
                 break;
         }
 
-        return 0;
+        if (ret_val)
+                e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
+
+        return ret_val;
 }
 
 /**
@@ -200,6 +217,17 @@ static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
                 break;
         }
 
+        /* Function Pointers */
+        switch (hw->mac.type) {
+        case e1000_82574:
+        case e1000_82583:
+                nvm->ops.acquire = e1000_get_hw_semaphore_82574;
+                nvm->ops.release = e1000_put_hw_semaphore_82574;
+                break;
+        default:
+                break;
+        }
+
         return 0;
 }
 
@@ -542,6 +570,146 @@ static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
         swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
         ew32(SWSM, swsm);
 }
+/**
+ *  e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the HW semaphore during reset.
+ *
+ **/
+static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
+{
+        u32 extcnf_ctrl;
+        s32 ret_val = 0;
+        s32 i = 0;
+
+        extcnf_ctrl = er32(EXTCNF_CTRL);
+        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+        do {
+                ew32(EXTCNF_CTRL, extcnf_ctrl);
+                extcnf_ctrl = er32(EXTCNF_CTRL);
+
+                if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
+                        break;
+
+                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+
+                msleep(2);
+                i++;
+        } while (i < MDIO_OWNERSHIP_TIMEOUT);
+
+        if (i == MDIO_OWNERSHIP_TIMEOUT) {
+                /* Release semaphores */
+                e1000_put_hw_semaphore_82573(hw);
+                e_dbg("Driver can't access the PHY\n");
+                ret_val = -E1000_ERR_PHY;
+                goto out;
+        }
+
+out:
+        return ret_val;
+}
+
+/**
+ *  e1000_put_hw_semaphore_82573 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used during reset.
+ *
+ **/
+static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
+{
+        u32 extcnf_ctrl;
+
+        extcnf_ctrl = er32(EXTCNF_CTRL);
+        extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
+        ew32(EXTCNF_CTRL, extcnf_ctrl);
+}
+
+static DEFINE_MUTEX(swflag_mutex);
+
+/**
+ *  e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Acquire the HW semaphore to access the PHY or NVM.
+ *
+ **/
+static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
+{
+        s32 ret_val;
+
+        mutex_lock(&swflag_mutex);
+        ret_val = e1000_get_hw_semaphore_82573(hw);
+        if (ret_val)
+                mutex_unlock(&swflag_mutex);
+        return ret_val;
+}
+
+/**
+ *  e1000_put_hw_semaphore_82574 - Release hardware semaphore
+ *  @hw: pointer to the HW structure
+ *
+ *  Release hardware semaphore used to access the PHY or NVM
+ *
+ **/
+static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
+{
+        e1000_put_hw_semaphore_82573(hw);
+        mutex_unlock(&swflag_mutex);
+}
+
+/**
+ *  e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
+ *  @hw: pointer to the HW structure
+ *  @active: true to enable LPLU, false to disable
+ *
+ *  Sets the LPLU D0 state according to the active flag.
+ *  LPLU will not be activated unless the
+ *  device autonegotiation advertisement meets standards of
+ *  either 10 or 10/100 or 10/100/1000 at all duplexes.
+ *  This is a function pointer entry point only called by
+ *  PHY setup routines.
+ **/
+static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
+{
+        u16 data = er32(POEMB);
+
+        if (active)
+                data |= E1000_PHY_CTRL_D0A_LPLU;
+        else
+                data &= ~E1000_PHY_CTRL_D0A_LPLU;
+
+        ew32(POEMB, data);
+        return 0;
+}
+
+/**
+ *  e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
+ *  @hw: pointer to the HW structure
+ *  @active: boolean used to enable/disable lplu
+ *
+ *  The low power link up (lplu) state is set to the power management level D3
+ *  when active is true, else clear lplu for D3. LPLU
+ *  is used during Dx states where the power conservation is most important.
+ *  During driver activity, SmartSpeed should be enabled so performance is
+ *  maintained.
+ **/
+static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
+{
+        u16 data = er32(POEMB);
+
+        if (!active) {
+                data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
+        } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
+                   (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
+                   (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
+                data |= E1000_PHY_CTRL_NOND0A_LPLU;
+        }
+
+        ew32(POEMB, data);
+        return 0;
+}
 
 /**
  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
@@ -562,8 +730,6 @@ static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 
         switch (hw->mac.type) {
         case e1000_82573:
-        case e1000_82574:
-        case e1000_82583:
                 break;
         default:
                 ret_val = e1000e_acquire_nvm(hw);
@@ -853,9 +1019,8 @@ static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
  **/
 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 {
-        u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
+        u32 ctrl, ctrl_ext;
         s32 ret_val;
-        u16 i = 0;
 
         /*
          * Prevent the PCI-E bus from sticking if there is no TLP connection
@@ -880,33 +1045,33 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
          */
         switch (hw->mac.type) {
         case e1000_82573:
+                ret_val = e1000_get_hw_semaphore_82573(hw);
+                break;
         case e1000_82574:
         case e1000_82583:
-                extcnf_ctrl = er32(EXTCNF_CTRL);
-                extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
-                do {
-                        ew32(EXTCNF_CTRL, extcnf_ctrl);
-                        extcnf_ctrl = er32(EXTCNF_CTRL);
-
-                        if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
-                                break;
-
-                        extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
-
-                        msleep(2);
-                        i++;
-                } while (i < MDIO_OWNERSHIP_TIMEOUT);
+                ret_val = e1000_get_hw_semaphore_82574(hw);
                 break;
         default:
                 break;
         }
+        if (ret_val)
+                e_dbg("Cannot acquire MDIO ownership\n");
 
         ctrl = er32(CTRL);
 
         e_dbg("Issuing a global reset to MAC\n");
         ew32(CTRL, ctrl | E1000_CTRL_RST);
 
+        /* Must release MDIO ownership and mutex after MAC reset. */
+        switch (hw->mac.type) {
+        case e1000_82574:
+        case e1000_82583:
+                e1000_put_hw_semaphore_82574(hw);
+                break;
+        default:
+                break;
+        }
+
         if (hw->nvm.type == e1000_nvm_flash_hw) {
                 udelay(10);
                 ctrl_ext = er32(CTRL_EXT);
@@ -938,7 +1103,7 @@ static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 
         /* Clear any pending interrupt events. */
         ew32(IMC, 0xffffffff);
-        icr = er32(ICR);
+        er32(ICR);
 
         if (hw->mac.type == e1000_82571) {
                 /* Install any alternate MAC address into RAR0 */
@@ -1402,6 +1567,8 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
         u32 rxcw;
         u32 ctrl;
         u32 status;
+        u32 txcw;
+        u32 i;
         s32 ret_val = 0;
 
         ctrl = er32(CTRL);
@@ -1422,8 +1589,10 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                                     e1000_serdes_link_autoneg_progress;
                                 mac->serdes_has_link = false;
                                 e_dbg("AN_UP     -> AN_PROG\n");
+                        } else {
+                                mac->serdes_has_link = true;
                         }
-                break;
+                        break;
 
                 case e1000_serdes_link_forced_up:
                         /*
@@ -1431,8 +1600,10 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                          * auto-negotiation in the TXCW register and disable
                          * forced link in the Device Control register in an
                          * attempt to auto-negotiate with our link partner.
+                         * If the partner code word is null, stop forcing
+                         * and restart auto negotiation.
                          */
-                        if (rxcw & E1000_RXCW_C) {
+                        if ((rxcw & E1000_RXCW_C) || !(rxcw & E1000_RXCW_CW))  {
                                 /* Enable autoneg, and unforce link up */
                                 ew32(TXCW, mac->txcw);
                                 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
@@ -1440,6 +1611,8 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                                     e1000_serdes_link_autoneg_progress;
                                 mac->serdes_has_link = false;
                                 e_dbg("FORCED_UP -> AN_PROG\n");
+                        } else {
+                                mac->serdes_has_link = true;
                         }
                         break;
 
@@ -1495,6 +1668,7 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                         ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
                         mac->serdes_link_state =
                             e1000_serdes_link_autoneg_progress;
+                        mac->serdes_has_link = false;
                         e_dbg("DOWN      -> AN_PROG\n");
                         break;
                 }
@@ -1505,16 +1679,32 @@ static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
                         e_dbg("ANYSTATE  -> DOWN\n");
                 } else {
                         /*
-                         * We have sync, and can tolerate one invalid (IV)
-                         * codeword before declaring link down, so reread
-                         * to look again.
+                         * Check several times, if Sync and Config
+                         * both are consistently 1 then simply ignore
+                         * the Invalid bit and restart Autoneg
                          */
-                        udelay(10);
-                        rxcw = er32(RXCW);
-                        if (rxcw & E1000_RXCW_IV) {
-                                mac->serdes_link_state = e1000_serdes_link_down;
+                        for (i = 0; i < AN_RETRY_COUNT; i++) {
+                                udelay(10);
+                                rxcw = er32(RXCW);
+                                if ((rxcw & E1000_RXCW_IV) &&
+                                    !((rxcw & E1000_RXCW_SYNCH) &&
+                                      (rxcw & E1000_RXCW_C))) {
+                                        mac->serdes_has_link = false;
+                                        mac->serdes_link_state =
+                                            e1000_serdes_link_down;
+                                        e_dbg("ANYSTATE  -> DOWN\n");
+                                        break;
+                                }
+                        }
+
+                        if (i == AN_RETRY_COUNT) {
+                                txcw = er32(TXCW);
+                                txcw |= E1000_TXCW_ANE;
+                                ew32(TXCW, txcw);
+                                mac->serdes_link_state =
+                                    e1000_serdes_link_autoneg_progress;
                                 mac->serdes_has_link = false;
-                                e_dbg("ANYSTATE  -> DOWN\n");
+                                e_dbg("ANYSTATE  -> AN_PROG\n");
                         }
                 }
         }
@@ -1897,7 +2087,7 @@ struct e1000_info e1000_82574_info = {
                                   | FLAG_HAS_AMT
                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
         .flags2                   = FLAG2_CHECK_PHY_HANG,
-        .pba                    = 36,
+        .pba                    = 32,
         .max_hw_frame_size      = DEFAULT_JUMBO,
         .get_variants           = e1000_get_variants_82571,
         .mac_ops                = &e82571_mac_ops,
@@ -1914,7 +2104,7 @@ struct e1000_info e1000_82583_info = {
                                   | FLAG_HAS_SMART_POWER_DOWN
                                   | FLAG_HAS_AMT
                                   | FLAG_HAS_CTRLEXT_ON_LOAD,
-        .pba                    = 36,
+        .pba                    = 32,
         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
         .get_variants           = e1000_get_variants_82571,
         .mac_ops                = &e82571_mac_ops,
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h
index d3f7a9c3f973..7245dc2e0b7c 100644
--- a/drivers/net/e1000e/defines.h
+++ b/drivers/net/e1000e/defines.h
@@ -488,6 +488,9 @@
 #define E1000_BLK_PHY_RESET   12
 #define E1000_ERR_SWFW_SYNC 13
 #define E1000_NOT_IMPLEMENTED 14
+#define E1000_ERR_INVALID_ARGUMENT  16
+#define E1000_ERR_NO_SPACE          17
+#define E1000_ERR_NVM_PBA_SECTION   18
 
 /* Loop limit on how long we wait for auto-negotiation to complete */
 #define FIBER_LINK_UP_LIMIT               50
@@ -516,6 +519,7 @@
 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 
 /* Receive Configuration Word */
+#define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
 #define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
 #define E1000_RXCW_C          0x20000000        /* Receive config */
 #define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
@@ -649,13 +653,16 @@
 /* Mask bits for fields in Word 0x03 of the EEPROM */
 #define NVM_COMPAT_LOM    0x0800
 
+/* length of string needed to store PBA number */
+#define E1000_PBANUM_LENGTH             11
+
 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 #define NVM_SUM                    0xBABA
 
 /* PBA (printed board assembly) number words */
 #define NVM_PBA_OFFSET_0           8
 #define NVM_PBA_OFFSET_1           9
-
+#define NVM_PBA_PTR_GUARD          0xFAFA
 #define NVM_WORD_SIZE_BASE_SHIFT   6
 
 /* NVM Commands - SPI */
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h
index fdc67fead4ea..5255be753746 100644
--- a/drivers/net/e1000e/e1000.h
+++ b/drivers/net/e1000e/e1000.h
@@ -38,6 +38,7 @@
 #include <linux/netdevice.h>
 #include <linux/pci.h>
 #include <linux/pci-aspm.h>
+#include <linux/crc32.h>
 
 #include "hw.h"
 
@@ -482,6 +483,7 @@ extern const char e1000e_driver_version[];
 
 extern void e1000e_check_options(struct e1000_adapter *adapter);
 extern void e1000e_set_ethtool_ops(struct net_device *netdev);
+extern void e1000e_led_blink_task(struct work_struct *work);
 
 extern int e1000e_up(struct e1000_adapter *adapter);
 extern void e1000e_down(struct e1000_adapter *adapter);
@@ -495,6 +497,8 @@ extern void e1000e_free_tx_resources(struct e1000_adapter *adapter);
 extern void e1000e_update_stats(struct e1000_adapter *adapter);
 extern void e1000e_set_interrupt_capability(struct e1000_adapter *adapter);
 extern void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter);
+extern void e1000e_get_hw_control(struct e1000_adapter *adapter);
+extern void e1000e_release_hw_control(struct e1000_adapter *adapter);
 extern void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
 
 extern unsigned int copybreak;
@@ -513,7 +517,8 @@ extern struct e1000_info e1000_pch_info;
 extern struct e1000_info e1000_pch2_info;
 extern struct e1000_info e1000_es2_info;
 
-extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
+extern s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
+                                         u32 pba_num_size);
 
 extern s32  e1000e_commit_phy(struct e1000_hw *hw);
 
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c
index 24f8ac9cf703..e45a61c8930a 100644
--- a/drivers/net/e1000e/es2lan.c
+++ b/drivers/net/e1000e/es2lan.c
@@ -100,8 +100,8 @@
  * with a lower bound at "index" and the upper bound at
  * "index + 5".
  */
-static const u16 e1000_gg82563_cable_length_table[] =
-         { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
+static const u16 e1000_gg82563_cable_length_table[] = {
+         0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
 
@@ -426,8 +426,8 @@ static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 {
         u32 swfw_sync;
 
-        while (e1000e_get_hw_semaphore(hw) != 0);
-        /* Empty */
+        while (e1000e_get_hw_semaphore(hw) != 0)
+                ; /* Empty */
 
         swfw_sync = er32(SW_FW_SYNC);
         swfw_sync &= ~mask;
@@ -784,7 +784,7 @@ static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
  **/
 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 {
-        u32 ctrl, icr;
+        u32 ctrl;
         s32 ret_val;
 
         /*
@@ -818,7 +818,7 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 
         /* Clear any pending interrupt events. */
         ew32(IMC, 0xffffffff);
-        icr = er32(ICR);
+        er32(ICR);
 
         ret_val = e1000_check_alt_mac_addr_generic(hw);
 
diff --git a/drivers/net/e1000e/ethtool.c b/drivers/net/e1000e/ethtool.c
index 8984d165a39b..f8ed03dab9b1 100644
--- a/drivers/net/e1000e/ethtool.c
+++ b/drivers/net/e1000e/ethtool.c
@@ -45,63 +45,67 @@ struct e1000_stats {
         int stat_offset;
 };
 
-#define E1000_STAT(m)           E1000_STATS, \
-                                sizeof(((struct e1000_adapter *)0)->m), \
-                                offsetof(struct e1000_adapter, m)
-#define E1000_NETDEV_STAT(m)    NETDEV_STATS, \
-                                sizeof(((struct net_device *)0)->m), \
-                                offsetof(struct net_device, m)
+#define E1000_STAT(str, m) { \
+                        .stat_string = str, \
+                        .type = E1000_STATS, \
+                        .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
+                        .stat_offset = offsetof(struct e1000_adapter, m) }
+#define E1000_NETDEV_STAT(str, m) { \
+                        .stat_string = str, \
+                        .type = NETDEV_STATS, \
+                        .sizeof_stat = sizeof(((struct net_device *)0)->m), \
+                        .stat_offset = offsetof(struct net_device, m) }
 
 static const struct e1000_stats e1000_gstrings_stats[] = {
-        { "rx_packets", E1000_STAT(stats.gprc) },
-        { "tx_packets", E1000_STAT(stats.gptc) },
-        { "rx_bytes", E1000_STAT(stats.gorc) },
-        { "tx_bytes", E1000_STAT(stats.gotc) },
-        { "rx_broadcast", E1000_STAT(stats.bprc) },
-        { "tx_broadcast", E1000_STAT(stats.bptc) },
-        { "rx_multicast", E1000_STAT(stats.mprc) },
-        { "tx_multicast", E1000_STAT(stats.mptc) },
-        { "rx_errors", E1000_NETDEV_STAT(stats.rx_errors) },
-        { "tx_errors", E1000_NETDEV_STAT(stats.tx_errors) },
-        { "tx_dropped", E1000_NETDEV_STAT(stats.tx_dropped) },
-        { "multicast", E1000_STAT(stats.mprc) },
-        { "collisions", E1000_STAT(stats.colc) },
-        { "rx_length_errors", E1000_NETDEV_STAT(stats.rx_length_errors) },
-        { "rx_over_errors", E1000_NETDEV_STAT(stats.rx_over_errors) },
-        { "rx_crc_errors", E1000_STAT(stats.crcerrs) },
-        { "rx_frame_errors", E1000_NETDEV_STAT(stats.rx_frame_errors) },
-        { "rx_no_buffer_count", E1000_STAT(stats.rnbc) },
-        { "rx_missed_errors", E1000_STAT(stats.mpc) },
-        { "tx_aborted_errors", E1000_STAT(stats.ecol) },
-        { "tx_carrier_errors", E1000_STAT(stats.tncrs) },
-        { "tx_fifo_errors", E1000_NETDEV_STAT(stats.tx_fifo_errors) },
-        { "tx_heartbeat_errors", E1000_NETDEV_STAT(stats.tx_heartbeat_errors) },
-        { "tx_window_errors", E1000_STAT(stats.latecol) },
-        { "tx_abort_late_coll", E1000_STAT(stats.latecol) },
-        { "tx_deferred_ok", E1000_STAT(stats.dc) },
-        { "tx_single_coll_ok", E1000_STAT(stats.scc) },
-        { "tx_multi_coll_ok", E1000_STAT(stats.mcc) },
-        { "tx_timeout_count", E1000_STAT(tx_timeout_count) },
-        { "tx_restart_queue", E1000_STAT(restart_queue) },
-        { "rx_long_length_errors", E1000_STAT(stats.roc) },
-        { "rx_short_length_errors", E1000_STAT(stats.ruc) },
-        { "rx_align_errors", E1000_STAT(stats.algnerrc) },
-        { "tx_tcp_seg_good", E1000_STAT(stats.tsctc) },
-        { "tx_tcp_seg_failed", E1000_STAT(stats.tsctfc) },
-        { "rx_flow_control_xon", E1000_STAT(stats.xonrxc) },
-        { "rx_flow_control_xoff", E1000_STAT(stats.xoffrxc) },
-        { "tx_flow_control_xon", E1000_STAT(stats.xontxc) },
-        { "tx_flow_control_xoff", E1000_STAT(stats.xofftxc) },
-        { "rx_long_byte_count", E1000_STAT(stats.gorc) },
-        { "rx_csum_offload_good", E1000_STAT(hw_csum_good) },
-        { "rx_csum_offload_errors", E1000_STAT(hw_csum_err) },
-        { "rx_header_split", E1000_STAT(rx_hdr_split) },
-        { "alloc_rx_buff_failed", E1000_STAT(alloc_rx_buff_failed) },
-        { "tx_smbus", E1000_STAT(stats.mgptc) },
-        { "rx_smbus", E1000_STAT(stats.mgprc) },
-        { "dropped_smbus", E1000_STAT(stats.mgpdc) },
-        { "rx_dma_failed", E1000_STAT(rx_dma_failed) },
-        { "tx_dma_failed", E1000_STAT(tx_dma_failed) },
+        E1000_STAT("rx_packets", stats.gprc),
+        E1000_STAT("tx_packets", stats.gptc),
+        E1000_STAT("rx_bytes", stats.gorc),
+        E1000_STAT("tx_bytes", stats.gotc),
+        E1000_STAT("rx_broadcast", stats.bprc),
+        E1000_STAT("tx_broadcast", stats.bptc),
+        E1000_STAT("rx_multicast", stats.mprc),
+        E1000_STAT("tx_multicast", stats.mptc),
+        E1000_NETDEV_STAT("rx_errors", stats.rx_errors),
+        E1000_NETDEV_STAT("tx_errors", stats.tx_errors),
+        E1000_NETDEV_STAT("tx_dropped", stats.tx_dropped),
+        E1000_STAT("multicast", stats.mprc),
+        E1000_STAT("collisions", stats.colc),
+        E1000_NETDEV_STAT("rx_length_errors", stats.rx_length_errors),
+        E1000_NETDEV_STAT("rx_over_errors", stats.rx_over_errors),
+        E1000_STAT("rx_crc_errors", stats.crcerrs),
+        E1000_NETDEV_STAT("rx_frame_errors", stats.rx_frame_errors),
+        E1000_STAT("rx_no_buffer_count", stats.rnbc),
+        E1000_STAT("rx_missed_errors", stats.mpc),
+        E1000_STAT("tx_aborted_errors", stats.ecol),
+        E1000_STAT("tx_carrier_errors", stats.tncrs),
+        E1000_NETDEV_STAT("tx_fifo_errors", stats.tx_fifo_errors),
+        E1000_NETDEV_STAT("tx_heartbeat_errors", stats.tx_heartbeat_errors),
+        E1000_STAT("tx_window_errors", stats.latecol),
+        E1000_STAT("tx_abort_late_coll", stats.latecol),
+        E1000_STAT("tx_deferred_ok", stats.dc),
+        E1000_STAT("tx_single_coll_ok", stats.scc),
+        E1000_STAT("tx_multi_coll_ok", stats.mcc),
+        E1000_STAT("tx_timeout_count", tx_timeout_count),
+        E1000_STAT("tx_restart_queue", restart_queue),
+        E1000_STAT("rx_long_length_errors", stats.roc),
+        E1000_STAT("rx_short_length_errors", stats.ruc),
+        E1000_STAT("rx_align_errors", stats.algnerrc),
+        E1000_STAT("tx_tcp_seg_good", stats.tsctc),
+        E1000_STAT("tx_tcp_seg_failed", stats.tsctfc),
+        E1000_STAT("rx_flow_control_xon", stats.xonrxc),
+        E1000_STAT("rx_flow_control_xoff", stats.xoffrxc),
+        E1000_STAT("tx_flow_control_xon", stats.xontxc),
+        E1000_STAT("tx_flow_control_xoff", stats.xofftxc),
+        E1000_STAT("rx_long_byte_count", stats.gorc),
+        E1000_STAT("rx_csum_offload_good", hw_csum_good),
+        E1000_STAT("rx_csum_offload_errors", hw_csum_err),
+        E1000_STAT("rx_header_split", rx_hdr_split),
+        E1000_STAT("alloc_rx_buff_failed", alloc_rx_buff_failed),
+        E1000_STAT("tx_smbus", stats.mgptc),
+        E1000_STAT("rx_smbus", stats.mgprc),
+        E1000_STAT("dropped_smbus", stats.mgpdc),
+        E1000_STAT("rx_dma_failed", rx_dma_failed),
+        E1000_STAT("tx_dma_failed", tx_dma_failed),
 };
 
 #define E1000_GLOBAL_STATS_LEN  ARRAY_SIZE(e1000_gstrings_stats)
@@ -194,20 +198,6 @@ static int e1000_get_settings(struct net_device *netdev,
         return 0;
 }
 
-static u32 e1000_get_link(struct net_device *netdev)
-{
-        struct e1000_adapter *adapter = netdev_priv(netdev);
-        struct e1000_hw *hw = &adapter->hw;
-
-        /*
-         * Avoid touching hardware registers when possible, otherwise
-         * link negotiation can get messed up when user-level scripts
-         * are rapidly polling the driver to see if link is up.
-         */
-        return netif_running(netdev) ? netif_carrier_ok(netdev) :
-            !!(er32(STATUS) & E1000_STATUS_LU);
-}
-
 static int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx)
 {
         struct e1000_mac_info *mac = &adapter->hw.mac;
@@ -634,20 +624,24 @@ static void e1000_get_drvinfo(struct net_device *netdev,
         struct e1000_adapter *adapter = netdev_priv(netdev);
         char firmware_version[32];
 
-        strncpy(drvinfo->driver,  e1000e_driver_name, 32);
-        strncpy(drvinfo->version, e1000e_driver_version, 32);
+        strncpy(drvinfo->driver,  e1000e_driver_name,
+                sizeof(drvinfo->driver) - 1);
+        strncpy(drvinfo->version, e1000e_driver_version,
+                sizeof(drvinfo->version) - 1);
 
         /*
          * EEPROM image version # is reported as firmware version # for
          * PCI-E controllers
          */
-        sprintf(firmware_version, "%d.%d-%d",
+        snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
                 (adapter->eeprom_vers & 0xF000) >> 12,
                 (adapter->eeprom_vers & 0x0FF0) >> 4,
                 (adapter->eeprom_vers & 0x000F));
 
-        strncpy(drvinfo->fw_version, firmware_version, 32);
-        strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
+        strncpy(drvinfo->fw_version, firmware_version,
+                sizeof(drvinfo->fw_version) - 1);
+        strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
+                sizeof(drvinfo->bus_info) - 1);
         drvinfo->regdump_len = e1000_get_regs_len(netdev);
         drvinfo->eedump_len = e1000_get_eeprom_len(netdev);
 }
@@ -763,8 +757,8 @@ static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data,
                              int reg, int offset, u32 mask, u32 write)
 {
         u32 pat, val;
-        static const u32 test[] =
-                {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
+        static const u32 test[] = {
+                0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
         for (pat = 0; pat < ARRAY_SIZE(test); pat++) {
                 E1000_WRITE_REG_ARRAY(&adapter->hw, reg, offset,
                                       (test[pat] & write));
@@ -1263,6 +1257,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
         u32 ctrl_reg = 0;
         u32 stat_reg = 0;
         u16 phy_reg = 0;
+        s32 ret_val = 0;
 
         hw->mac.autoneg = 0;
 
@@ -1322,7 +1317,13 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
         case e1000_phy_82577:
         case e1000_phy_82578:
                 /* Workaround: K1 must be disabled for stable 1Gbps operation */
+                ret_val = hw->phy.ops.acquire(hw);
+                if (ret_val) {
+                        e_err("Cannot setup 1Gbps loopback.\n");
+                        return ret_val;
+                }
                 e1000_configure_k1_ich8lan(hw, false);
+                hw->phy.ops.release(hw);
                 break;
         case e1000_phy_82579:
                 /* Disable PHY energy detect power down */
@@ -1707,6 +1708,19 @@ static void e1000_diag_test(struct net_device *netdev,
         bool if_running = netif_running(netdev);
 
         set_bit(__E1000_TESTING, &adapter->state);
+
+        if (!if_running) {
+                /* Get control of and reset hardware */
+                if (adapter->flags & FLAG_HAS_AMT)
+                        e1000e_get_hw_control(adapter);
+
+                e1000e_power_up_phy(adapter);
+
+                adapter->hw.phy.autoneg_wait_to_complete = 1;
+                e1000e_reset(adapter);
+                adapter->hw.phy.autoneg_wait_to_complete = 0;
+        }
+
         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
                 /* Offline tests */
 
@@ -1720,8 +1734,6 @@ static void e1000_diag_test(struct net_device *netdev,
                 if (if_running)
                         /* indicate we're in test mode */
                         dev_close(netdev);
-                else
-                        e1000e_reset(adapter);
 
                 if (e1000_reg_test(adapter, &data[0]))
                         eth_test->flags |= ETH_TEST_FL_FAILED;
@@ -1735,8 +1747,6 @@ static void e1000_diag_test(struct net_device *netdev,
                         eth_test->flags |= ETH_TEST_FL_FAILED;
 
                 e1000e_reset(adapter);
-                /* make sure the phy is powered up */
-                e1000e_power_up_phy(adapter);
                 if (e1000_loopback_test(adapter, &data[3]))
                         eth_test->flags |= ETH_TEST_FL_FAILED;
 
@@ -1758,28 +1768,29 @@ static void e1000_diag_test(struct net_device *netdev,
                 if (if_running)
                         dev_open(netdev);
         } else {
-                if (!if_running && (adapter->flags & FLAG_HAS_AMT)) {
-                        clear_bit(__E1000_TESTING, &adapter->state);
-                        dev_open(netdev);
-                        set_bit(__E1000_TESTING, &adapter->state);
-                }
+                /* Online tests */
 
                 e_info("online testing starting\n");
-                /* Online tests */
-                if (e1000_link_test(adapter, &data[4]))
-                        eth_test->flags |= ETH_TEST_FL_FAILED;
 
-                /* Online tests aren't run; pass by default */
+                /* register, eeprom, intr and loopback tests not run online */
                 data[0] = 0;
                 data[1] = 0;
                 data[2] = 0;
                 data[3] = 0;
 
-                if (!if_running && (adapter->flags & FLAG_HAS_AMT))
-                        dev_close(netdev);
+                if (e1000_link_test(adapter, &data[4]))
+                        eth_test->flags |= ETH_TEST_FL_FAILED;
 
                 clear_bit(__E1000_TESTING, &adapter->state);
         }
+
+        if (!if_running) {
+                e1000e_reset(adapter);
+
+                if (adapter->flags & FLAG_HAS_AMT)
+                        e1000e_release_hw_control(adapter);
+        }
+
         msleep_interruptible(4 * 1000);
 }
 
@@ -1860,7 +1871,7 @@ static int e1000_set_wol(struct net_device *netdev,
 /* bit defines for adapter->led_status */
 #define E1000_LED_ON            0
 
-static void e1000e_led_blink_task(struct work_struct *work)
+void e1000e_led_blink_task(struct work_struct *work)
 {
         struct e1000_adapter *adapter = container_of(work,
                                         struct e1000_adapter, led_blink_task);
@@ -1892,7 +1903,6 @@ static int e1000_phys_id(struct net_device *netdev, u32 data)
             (hw->mac.type == e1000_pch2lan) ||
             (hw->mac.type == e1000_82583) ||
             (hw->mac.type == e1000_82574)) {
-                INIT_WORK(&adapter->led_blink_task, e1000e_led_blink_task);
                 if (!adapter->blink_timer.function) {
                         init_timer(&adapter->blink_timer);
                         adapter->blink_timer.function =
@@ -1986,6 +1996,9 @@ static void e1000_get_ethtool_stats(struct net_device *netdev,
                         p = (char *) adapter +
                                         e1000_gstrings_stats[i].stat_offset;
                         break;
+                default:
+                        data[i] = 0;
+                        continue;
                 }
 
                 data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
@@ -2024,7 +2037,7 @@ static const struct ethtool_ops e1000_ethtool_ops = {
         .get_msglevel           = e1000_get_msglevel,
         .set_msglevel           = e1000_set_msglevel,
         .nway_reset             = e1000_nway_reset,
-        .get_link               = e1000_get_link,
+        .get_link               = ethtool_op_get_link,
         .get_eeprom_len         = e1000_get_eeprom_len,
         .get_eeprom             = e1000_get_eeprom,
         .set_eeprom             = e1000_set_eeprom,
diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index ba302a5c2c30..e774380c7cec 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -83,6 +83,7 @@ enum e1e_registers {
         E1000_EXTCNF_CTRL  = 0x00F00, /* Extended Configuration Control */
         E1000_EXTCNF_SIZE  = 0x00F08, /* Extended Configuration Size */
         E1000_PHY_CTRL     = 0x00F10, /* PHY Control Register in CSR */
+#define E1000_POEMB     E1000_PHY_CTRL  /* PHY OEM Bits */
         E1000_PBA      = 0x01000, /* Packet Buffer Allocation - RW */
         E1000_PBS      = 0x01008, /* Packet Buffer Size */
         E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
diff --git a/drivers/net/e1000e/ich8lan.c b/drivers/net/e1000e/ich8lan.c
index 38c84ba3e3c1..5bb65b7382db 100644
--- a/drivers/net/e1000e/ich8lan.c
+++ b/drivers/net/e1000e/ich8lan.c
@@ -338,12 +338,17 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
         }
 
         phy->id = e1000_phy_unknown;
-        ret_val = e1000e_get_phy_id(hw);
-        if (ret_val)
-                goto out;
-        if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
+        switch (hw->mac.type) {
+        default:
+                ret_val = e1000e_get_phy_id(hw);
+                if (ret_val)
+                        goto out;
+                if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
+                        break;
+                /* fall-through */
+        case e1000_pch2lan:
                 /*
-                 * In case the PHY needs to be in mdio slow mode (eg. 82577),
+                 * In case the PHY needs to be in mdio slow mode,
                  * set slow mode and try to get the PHY id again.
                  */
                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
@@ -352,6 +357,7 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
                 ret_val = e1000e_get_phy_id(hw);
                 if (ret_val)
                         goto out;
+                break;
         }
         phy->type = e1000e_get_phy_type_from_id(phy->id);
 
@@ -1389,22 +1395,6 @@ void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
         }
 }
 
-static u32 e1000_calc_rx_da_crc(u8 mac[])
-{
-        u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
-        u32 i, j, mask, crc;
-
-        crc = 0xffffffff;
-        for (i = 0; i < 6; i++) {
-                crc = crc ^ mac[i];
-                for (j = 8; j > 0; j--) {
-                        mask = (crc & 1) * (-1);
-                        crc = (crc >> 1) ^ (poly & mask);
-                }
-        }
-        return ~crc;
-}
-
 /**
  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
  *  with 82579 PHY
@@ -1447,8 +1437,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
                         mac_addr[4] = (addr_high & 0xFF);
                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
 
-                        ew32(PCH_RAICC(i),
-                                        e1000_calc_rx_da_crc(mac_addr));
+                        ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
                 }
 
                 /* Write Rx addresses to the PHY */
@@ -2303,11 +2292,10 @@ static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
                  */
                 if (ret_val == 0) {
                         flash_data = er32flash(ICH_FLASH_FDATA0);
-                        if (size == 1) {
+                        if (size == 1)
                                 *data = (u8)(flash_data & 0x000000FF);
-                        } else if (size == 2) {
+                        else if (size == 2)
                                 *data = (u16)(flash_data & 0x0000FFFF);
-                        }
                         break;
                 } else {
                         /*
@@ -2972,7 +2960,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
 {
         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
         u16 reg;
-        u32 ctrl, icr, kab;
+        u32 ctrl, kab;
         s32 ret_val;
 
         /*
@@ -3062,7 +3050,7 @@ static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
                 ew32(CRC_OFFSET, 0x65656565);
 
         ew32(IMC, 0xffffffff);
-        icr = er32(ICR);
+        er32(ICR);
 
         kab = er32(KABGTXD);
         kab |= E1000_KABGTXD_BGSQLBIAS;
@@ -3113,7 +3101,7 @@ static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
          * Reset the phy after disabling host wakeup to reset the Rx buffer.
          */
         if (hw->phy.type == e1000_phy_82578) {
-                hw->phy.ops.read_reg(hw, BM_WUC, &i);
+                e1e_rphy(hw, BM_WUC, &i);
                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
                 if (ret_val)
                         return ret_val;
@@ -3271,9 +3259,8 @@ static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
             (hw->phy.type == e1000_phy_82577)) {
                 ew32(FCRTV_PCH, hw->fc.refresh_time);
 
-                ret_val = hw->phy.ops.write_reg(hw,
-                                             PHY_REG(BM_PORT_CTRL_PAGE, 27),
-                                             hw->fc.pause_time);
+                ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
+                                   hw->fc.pause_time);
                 if (ret_val)
                         return ret_val;
         }
@@ -3337,8 +3324,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
                         return ret_val;
                 break;
         case e1000_phy_ife:
-                ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
-                                               &reg_data);
+                ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
                 if (ret_val)
                         return ret_val;
 
@@ -3356,8 +3342,7 @@ static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
                         reg_data |= IFE_PMC_AUTO_MDIX;
                         break;
                 }
-                ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
-                                                reg_data);
+                ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
                 if (ret_val)
                         return ret_val;
                 break;
@@ -3591,7 +3576,7 @@ void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
         ew32(PHY_CTRL, phy_ctrl);
 
         if (hw->mac.type >= e1000_pchlan) {
-                e1000_oem_bits_config_ich8lan(hw, true);
+                e1000_oem_bits_config_ich8lan(hw, false);
                 ret_val = hw->phy.ops.acquire(hw);
                 if (ret_val)
                         return;
@@ -3641,7 +3626,8 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
 {
         if (hw->phy.type == e1000_phy_ife)
                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
-                               (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
+                                (IFE_PSCL_PROBE_MODE |
+                                 IFE_PSCL_PROBE_LEDS_OFF));
 
         ew32(LEDCTL, hw->mac.ledctl_mode1);
         return 0;
@@ -3655,8 +3641,7 @@ static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
  **/
 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
 {
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-                                        (u16)hw->mac.ledctl_mode1);
+        return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
 }
 
 /**
@@ -3667,8 +3652,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
  **/
 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
 {
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
-                                        (u16)hw->mac.ledctl_default);
+        return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
 }
 
 /**
@@ -3699,7 +3683,7 @@ static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
                 }
         }
 
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
+        return e1e_wphy(hw, HV_LED_CONFIG, data);
 }
 
 /**
@@ -3730,7 +3714,7 @@ static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
                 }
         }
 
-        return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
+        return e1e_wphy(hw, HV_LED_CONFIG, data);
 }
 
 /**
@@ -3839,20 +3823,20 @@ static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
         if ((hw->phy.type == e1000_phy_82578) ||
             (hw->phy.type == e1000_phy_82579) ||
             (hw->phy.type == e1000_phy_82577)) {
-                hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
-                hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
+                e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_ECOL_UPPER, &phy_data);
+                e1e_rphy(hw, HV_ECOL_LOWER, &phy_data);
+                e1e_rphy(hw, HV_MCC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_MCC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_LATECOL_UPPER, &phy_data);
+                e1e_rphy(hw, HV_LATECOL_LOWER, &phy_data);
+                e1e_rphy(hw, HV_COLC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_COLC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_DC_UPPER, &phy_data);
+                e1e_rphy(hw, HV_DC_LOWER, &phy_data);
+                e1e_rphy(hw, HV_TNCRS_UPPER, &phy_data);
+                e1e_rphy(hw, HV_TNCRS_LOWER, &phy_data);
         }
 }
 
diff --git a/drivers/net/e1000e/lib.c b/drivers/net/e1000e/lib.c
index 0fd4eb5ac5fb..ff2872153b21 100644
--- a/drivers/net/e1000e/lib.c
+++ b/drivers/net/e1000e/lib.c
@@ -493,9 +493,8 @@ s32 e1000e_check_for_copper_link(struct e1000_hw *hw)
          * different link partner.
          */
         ret_val = e1000e_config_fc_after_link_up(hw);
-        if (ret_val) {
+        if (ret_val)
                 e_dbg("Error configuring flow control\n");
-        }
 
         return ret_val;
 }
@@ -1136,7 +1135,8 @@ s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw)
                 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg);
                 if (ret_val)
                         return ret_val;
-                ret_val = e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
+                ret_val =
+                    e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg);
                 if (ret_val)
                         return ret_val;
 
@@ -1496,9 +1496,8 @@ s32 e1000e_setup_led_generic(struct e1000_hw *hw)
 {
         u32 ledctl;
 
-        if (hw->mac.ops.setup_led != e1000e_setup_led_generic) {
+        if (hw->mac.ops.setup_led != e1000e_setup_led_generic)
                 return -E1000_ERR_CONFIG;
-        }
 
         if (hw->phy.media_type == e1000_media_type_fiber) {
                 ledctl = er32(LEDCTL);
@@ -2139,6 +2138,119 @@ s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
 }
 
 /**
+ *  e1000_read_pba_string_generic - Read device part number
+ *  @hw: pointer to the HW structure
+ *  @pba_num: pointer to device part number
+ *  @pba_num_size: size of part number buffer
+ *
+ *  Reads the product board assembly (PBA) number from the EEPROM and stores
+ *  the value in pba_num.
+ **/
+s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
+                                  u32 pba_num_size)
+{
+        s32 ret_val;
+        u16 nvm_data;
+        u16 pba_ptr;
+        u16 offset;
+        u16 length;
+
+        if (pba_num == NULL) {
+                e_dbg("PBA string buffer was null\n");
+                ret_val = E1000_ERR_INVALID_ARGUMENT;
+                goto out;
+        }
+
+        ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
+        if (ret_val) {
+                e_dbg("NVM Read Error\n");
+                goto out;
+        }
+
+        ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
+        if (ret_val) {
+                e_dbg("NVM Read Error\n");
+                goto out;
+        }
+
+        /*
+         * if nvm_data is not ptr guard the PBA must be in legacy format which
+         * means pba_ptr is actually our second data word for the PBA number
+         * and we can decode it into an ascii string
+         */
+        if (nvm_data != NVM_PBA_PTR_GUARD) {
+                e_dbg("NVM PBA number is not stored as string\n");
+
+                /* we will need 11 characters to store the PBA */
+                if (pba_num_size < 11) {
+                        e_dbg("PBA string buffer too small\n");
+                        return E1000_ERR_NO_SPACE;
+                }
+
+                /* extract hex string from data and pba_ptr */
+                pba_num[0] = (nvm_data >> 12) & 0xF;
+                pba_num[1] = (nvm_data >> 8) & 0xF;
+                pba_num[2] = (nvm_data >> 4) & 0xF;
+                pba_num[3] = nvm_data & 0xF;
+                pba_num[4] = (pba_ptr >> 12) & 0xF;
+                pba_num[5] = (pba_ptr >> 8) & 0xF;
+                pba_num[6] = '-';
+                pba_num[7] = 0;
+                pba_num[8] = (pba_ptr >> 4) & 0xF;
+                pba_num[9] = pba_ptr & 0xF;
+
+                /* put a null character on the end of our string */
+                pba_num[10] = '\0';
+
+                /* switch all the data but the '-' to hex char */
+                for (offset = 0; offset < 10; offset++) {
+                        if (pba_num[offset] < 0xA)
+                                pba_num[offset] += '0';
+                        else if (pba_num[offset] < 0x10)
+                                pba_num[offset] += 'A' - 0xA;
+                }
+
+                goto out;
+        }
+
+        ret_val = e1000_read_nvm(hw, pba_ptr, 1, &length);
+        if (ret_val) {
+                e_dbg("NVM Read Error\n");
+                goto out;
+        }
+
+        if (length == 0xFFFF || length == 0) {
+                e_dbg("NVM PBA number section invalid length\n");
+                ret_val = E1000_ERR_NVM_PBA_SECTION;
+                goto out;
+        }
+        /* check if pba_num buffer is big enough */
+        if (pba_num_size < (((u32)length * 2) - 1)) {
+                e_dbg("PBA string buffer too small\n");
+                ret_val = E1000_ERR_NO_SPACE;
+                goto out;
+        }
+
+        /* trim pba length from start of string */
+        pba_ptr++;
+        length--;
+
+        for (offset = 0; offset < length; offset++) {
+                ret_val = e1000_read_nvm(hw, pba_ptr + offset, 1, &nvm_data);
+                if (ret_val) {
+                        e_dbg("NVM Read Error\n");
+                        goto out;
+                }
+                pba_num[offset * 2] = (u8)(nvm_data >> 8);
+                pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
+        }
+        pba_num[offset * 2] = '\0';
+
+out:
+        return ret_val;
+}
+
+/**
  *  e1000_read_mac_addr_generic - Read device MAC address
  *  @hw: pointer to the HW structure
  *
@@ -2579,25 +2691,3 @@ bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
 out:
         return ret_val;
 }
-
-s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
-{
-        s32 ret_val;
-        u16 nvm_data;
-
-        ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
-        if (ret_val) {
-                e_dbg("NVM Read Error\n");
-                return ret_val;
-        }
-        *pba_num = (u32)(nvm_data << 16);
-
-        ret_val = e1000_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
-        if (ret_val) {
-                e_dbg("NVM Read Error\n");
-                return ret_val;
-        }
-        *pba_num |= nvm_data;
-
-        return 0;
-}
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index c4ca1629f532..fa5b60452547 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -54,7 +54,7 @@
 
 #define DRV_EXTRAVERSION "-k2"
 
-#define DRV_VERSION "1.2.7" DRV_EXTRAVERSION
+#define DRV_VERSION "1.2.20" DRV_EXTRAVERSION
 char e1000e_driver_name[] = "e1000e";
 const char e1000e_driver_version[] = DRV_VERSION;
 
@@ -1325,7 +1325,7 @@ static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
                                 goto next_desc;
                 }
 
-#define rxtop rx_ring->rx_skb_top
+#define rxtop (rx_ring->rx_skb_top)
                 if (!(status & E1000_RXD_STAT_EOP)) {
                         /* this descriptor is only the beginning (or middle) */
                         if (!rxtop) {
@@ -1806,9 +1806,8 @@ void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
                                 err = pci_enable_msix(adapter->pdev,
                                                       adapter->msix_entries,
                                                       adapter->num_vectors);
-                                if (err == 0) {
+                                if (err == 0)
                                         return;
-                                }
                         }
                         /* MSI-X failed, so fall through and try MSI */
                         e_err("Failed to initialize MSI-X interrupts.  "
@@ -1981,15 +1980,15 @@ static void e1000_irq_enable(struct e1000_adapter *adapter)
 }
 
 /**
- * e1000_get_hw_control - get control of the h/w from f/w
+ * e1000e_get_hw_control - get control of the h/w from f/w
  * @adapter: address of board private structure
  *
- * e1000_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
+ * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
  * For ASF and Pass Through versions of f/w this means that
  * the driver is loaded. For AMT version (only with 82573)
  * of the f/w this means that the network i/f is open.
  **/
-static void e1000_get_hw_control(struct e1000_adapter *adapter)
+void e1000e_get_hw_control(struct e1000_adapter *adapter)
 {
         struct e1000_hw *hw = &adapter->hw;
         u32 ctrl_ext;
@@ -2006,16 +2005,16 @@ static void e1000_get_hw_control(struct e1000_adapter *adapter)
 }
 
 /**
- * e1000_release_hw_control - release control of the h/w to f/w
+ * e1000e_release_hw_control - release control of the h/w to f/w
  * @adapter: address of board private structure
  *
- * e1000_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
+ * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
  * For ASF and Pass Through versions of f/w this means that the
  * driver is no longer loaded. For AMT version (only with 82573) i
  * of the f/w this means that the network i/f is closed.
  *
  **/
-static void e1000_release_hw_control(struct e1000_adapter *adapter)
+void e1000e_release_hw_control(struct e1000_adapter *adapter)
 {
         struct e1000_hw *hw = &adapter->hw;
         u32 ctrl_ext;
@@ -2059,10 +2058,9 @@ int e1000e_setup_tx_resources(struct e1000_adapter *adapter)
         int err = -ENOMEM, size;
 
         size = sizeof(struct e1000_buffer) * tx_ring->count;
-        tx_ring->buffer_info = vmalloc(size);
+        tx_ring->buffer_info = vzalloc(size);
         if (!tx_ring->buffer_info)
                 goto err;
-        memset(tx_ring->buffer_info, 0, size);
 
         /* round up to nearest 4K */
         tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
@@ -2095,10 +2093,9 @@ int e1000e_setup_rx_resources(struct e1000_adapter *adapter)
         int i, size, desc_len, err = -ENOMEM;
 
         size = sizeof(struct e1000_buffer) * rx_ring->count;
-        rx_ring->buffer_info = vmalloc(size);
+        rx_ring->buffer_info = vzalloc(size);
         if (!rx_ring->buffer_info)
                 goto err;
-        memset(rx_ring->buffer_info, 0, size);
 
         for (i = 0; i < rx_ring->count; i++) {
                 buffer_info = &rx_ring->buffer_info[i];
@@ -2132,7 +2129,7 @@ err_pages:
         }
 err:
         vfree(rx_ring->buffer_info);
-        e_err("Unable to allocate memory for the transmit descriptor ring\n");
+        e_err("Unable to allocate memory for the receive descriptor ring\n");
         return err;
 }
 
@@ -2200,9 +2197,8 @@ void e1000e_free_rx_resources(struct e1000_adapter *adapter)
 
         e1000_clean_rx_ring(adapter);
 
-        for (i = 0; i < rx_ring->count; i++) {
+        for (i = 0; i < rx_ring->count; i++)
                 kfree(rx_ring->buffer_info[i].ps_pages);
-        }
 
         vfree(rx_ring->buffer_info);
         rx_ring->buffer_info = NULL;
@@ -2242,20 +2238,18 @@ static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
                 /* handle TSO and jumbo frames */
                 if (bytes/packets > 8000)
                         retval = bulk_latency;
-                else if ((packets < 5) && (bytes > 512)) {
+                else if ((packets < 5) && (bytes > 512))
                         retval = low_latency;
-                }
                 break;
         case low_latency:  /* 50 usec aka 20000 ints/s */
                 if (bytes > 10000) {
                         /* this if handles the TSO accounting */
-                        if (bytes/packets > 8000) {
+                        if (bytes/packets > 8000)
                                 retval = bulk_latency;
-                        } else if ((packets < 10) || ((bytes/packets) > 1200)) {
+                        else if ((packets < 10) || ((bytes/packets) > 1200))
                                 retval = bulk_latency;
-                        } else if ((packets > 35)) {
+                        else if ((packets > 35))
                                 retval = lowest_latency;
-                        }
                 } else if (bytes/packets > 2000) {
                         retval = bulk_latency;
                 } else if (packets <= 2 && bytes < 512) {
@@ -2264,9 +2258,8 @@ static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
                 break;
         case bulk_latency: /* 250 usec aka 4000 ints/s */
                 if (bytes > 25000) {
-                        if (packets > 35) {
+                        if (packets > 35)
                                 retval = low_latency;
-                        }
                 } else if (bytes < 6000) {
                         retval = low_latency;
                 }
@@ -2452,7 +2445,7 @@ static void e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
              E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
             (vid == adapter->mng_vlan_id)) {
                 /* release control to f/w */
-                e1000_release_hw_control(adapter);
+                e1000e_release_hw_control(adapter);
                 return;
         }
 
@@ -2741,6 +2734,9 @@ static void e1000_setup_rctl(struct e1000_adapter *adapter)
                         ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
                 else
                         ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
+
+                if (ret_val)
+                        e_dbg("failed to enable jumbo frame workaround mode\n");
         }
 
         /* Program MC offset vector base */
@@ -3191,7 +3187,6 @@ void e1000e_reset(struct e1000_adapter *adapter)
                 ew32(PBA, pba);
         }
 
-
         /*
          * flow control settings
          *
@@ -3279,7 +3274,7 @@ void e1000e_reset(struct e1000_adapter *adapter)
          * that the network interface is in control
          */
         if (adapter->flags & FLAG_HAS_AMT)
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
         ew32(WUC, 0);
 
@@ -3292,6 +3287,13 @@ void e1000e_reset(struct e1000_adapter *adapter)
         ew32(VET, ETH_P_8021Q);
 
         e1000e_reset_adaptive(hw);
+
+        if (!netif_running(adapter->netdev) &&
+            !test_bit(__E1000_TESTING, &adapter->state)) {
+                e1000_power_down_phy(adapter);
+                return;
+        }
+
         e1000_get_phy_info(hw);
 
         if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
@@ -3577,7 +3579,7 @@ static int e1000_open(struct net_device *netdev)
          * interface is now open and reset the part to a known state.
          */
         if (adapter->flags & FLAG_HAS_AMT) {
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
                 e1000e_reset(adapter);
         }
 
@@ -3641,7 +3643,7 @@ static int e1000_open(struct net_device *netdev)
         return 0;
 
 err_req_irq:
-        e1000_release_hw_control(adapter);
+        e1000e_release_hw_control(adapter);
         e1000_power_down_phy(adapter);
         e1000e_free_rx_resources(adapter);
 err_setup_rx:
@@ -3696,8 +3698,9 @@ static int e1000_close(struct net_device *netdev)
          * If AMT is enabled, let the firmware know that the network
          * interface is now closed
          */
-        if (adapter->flags & FLAG_HAS_AMT)
-                e1000_release_hw_control(adapter);
+        if ((adapter->flags & FLAG_HAS_AMT) &&
+            !test_bit(__E1000_TESTING, &adapter->state))
+                e1000e_release_hw_control(adapter);
 
         if ((adapter->flags & FLAG_HAS_ERT) ||
             (adapter->hw.mac.type == e1000_pch2lan))
@@ -4475,7 +4478,7 @@ static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
                 break;
         }
 
-        css = skb_transport_offset(skb);
+        css = skb_checksum_start_offset(skb);
 
         i = tx_ring->next_to_use;
         buffer_info = &tx_ring->buffer_info[i];
@@ -4595,7 +4598,7 @@ dma_error:
                         i += tx_ring->count;
                 i--;
                 buffer_info = &tx_ring->buffer_info[i];
-                e1000_put_txbuf(adapter, buffer_info);;
+                e1000_put_txbuf(adapter, buffer_info);
         }
 
         return 0;
@@ -4631,7 +4634,7 @@ static void e1000_tx_queue(struct e1000_adapter *adapter,
 
         i = tx_ring->next_to_use;
 
-        while (count--) {
+        do {
                 buffer_info = &tx_ring->buffer_info[i];
                 tx_desc = E1000_TX_DESC(*tx_ring, i);
                 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
@@ -4642,7 +4645,7 @@ static void e1000_tx_queue(struct e1000_adapter *adapter,
                 i++;
                 if (i == tx_ring->count)
                         i = 0;
-        }
+        } while (--count > 0);
 
         tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
 
@@ -5216,7 +5219,7 @@ static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
          * Release control of h/w to f/w.  If f/w is AMT enabled, this
          * would have already happened in close and is redundant.
          */
-        e1000_release_hw_control(adapter);
+        e1000e_release_hw_control(adapter);
 
         pci_disable_device(pdev);
 
@@ -5373,7 +5376,7 @@ static int __e1000_resume(struct pci_dev *pdev)
          * under the control of the driver.
          */
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
         return 0;
 }
@@ -5465,6 +5468,36 @@ static void e1000_shutdown(struct pci_dev *pdev)
 }
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
+
+static irqreturn_t e1000_intr_msix(int irq, void *data)
+{
+        struct net_device *netdev = data;
+        struct e1000_adapter *adapter = netdev_priv(netdev);
+        int vector, msix_irq;
+
+        if (adapter->msix_entries) {
+                vector = 0;
+                msix_irq = adapter->msix_entries[vector].vector;
+                disable_irq(msix_irq);
+                e1000_intr_msix_rx(msix_irq, netdev);
+                enable_irq(msix_irq);
+
+                vector++;
+                msix_irq = adapter->msix_entries[vector].vector;
+                disable_irq(msix_irq);
+                e1000_intr_msix_tx(msix_irq, netdev);
+                enable_irq(msix_irq);
+
+                vector++;
+                msix_irq = adapter->msix_entries[vector].vector;
+                disable_irq(msix_irq);
+                e1000_msix_other(msix_irq, netdev);
+                enable_irq(msix_irq);
+        }
+
+        return IRQ_HANDLED;
+}
+
 /*
  * Polling 'interrupt' - used by things like netconsole to send skbs
  * without having to re-enable interrupts. It's not called while
@@ -5474,10 +5507,21 @@ static void e1000_netpoll(struct net_device *netdev)
 {
         struct e1000_adapter *adapter = netdev_priv(netdev);
 
-        disable_irq(adapter->pdev->irq);
-        e1000_intr(adapter->pdev->irq, netdev);
-
-        enable_irq(adapter->pdev->irq);
+        switch (adapter->int_mode) {
+        case E1000E_INT_MODE_MSIX:
+                e1000_intr_msix(adapter->pdev->irq, netdev);
+                break;
+        case E1000E_INT_MODE_MSI:
+                disable_irq(adapter->pdev->irq);
+                e1000_intr_msi(adapter->pdev->irq, netdev);
+                enable_irq(adapter->pdev->irq);
+                break;
+        default: /* E1000E_INT_MODE_LEGACY */
+                disable_irq(adapter->pdev->irq);
+                e1000_intr(adapter->pdev->irq, netdev);
+                enable_irq(adapter->pdev->irq);
+                break;
+        }
 }
 #endif
 
@@ -5579,7 +5623,7 @@ static void e1000_io_resume(struct pci_dev *pdev)
          * under the control of the driver.
          */
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
 }
 
@@ -5587,7 +5631,8 @@ static void e1000_print_device_info(struct e1000_adapter *adapter)
 {
         struct e1000_hw *hw = &adapter->hw;
         struct net_device *netdev = adapter->netdev;
-        u32 pba_num;
+        u32 ret_val;
+        u8 pba_str[E1000_PBANUM_LENGTH];
 
         /* print bus type/speed/width info */
         e_info("(PCI Express:2.5GB/s:%s) %pM\n",
@@ -5598,9 +5643,12 @@ static void e1000_print_device_info(struct e1000_adapter *adapter)
                netdev->dev_addr);
         e_info("Intel(R) PRO/%s Network Connection\n",
                (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
-        e1000e_read_pba_num(hw, &pba_num);
-        e_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
-               hw->mac.type, hw->phy.type, (pba_num >> 8), (pba_num & 0xff));
+        ret_val = e1000_read_pba_string_generic(hw, pba_str,
+                                                E1000_PBANUM_LENGTH);
+        if (ret_val)
+                strncpy((char *)pba_str, "Unknown", sizeof(pba_str) - 1);
+        e_info("MAC: %d, PHY: %d, PBA No: %s\n",
+               hw->mac.type, hw->phy.type, pba_str);
 }
 
 static void e1000_eeprom_checks(struct e1000_adapter *adapter)
@@ -5864,6 +5912,7 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
         INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
         INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
         INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
+        INIT_WORK(&adapter->led_blink_task, e1000e_led_blink_task);
 
         /* Initialize link parameters. User can change them with ethtool */
         adapter->hw.mac.autoneg = 1;
@@ -5924,9 +5973,9 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
          * under the control of the driver.
          */
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_get_hw_control(adapter);
+                e1000e_get_hw_control(adapter);
 
-        strcpy(netdev->name, "eth%d");
+        strncpy(netdev->name, "eth%d", sizeof(netdev->name) - 1);
         err = register_netdev(netdev);
         if (err)
                 goto err_register;
@@ -5943,12 +5992,11 @@ static int __devinit e1000_probe(struct pci_dev *pdev,
 
 err_register:
         if (!(adapter->flags & FLAG_HAS_AMT))
-                e1000_release_hw_control(adapter);
+                e1000e_release_hw_control(adapter);
 err_eeprom:
         if (!e1000_check_reset_block(&adapter->hw))
                 e1000_phy_hw_reset(&adapter->hw);
 err_hw_init:
-
         kfree(adapter->tx_ring);
         kfree(adapter->rx_ring);
 err_sw_init:
@@ -5984,8 +6032,8 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
         bool down = test_bit(__E1000_DOWN, &adapter->state);
 
         /*
-         * flush_scheduled work may reschedule our watchdog task, so
-         * explicitly disable watchdog tasks from being rescheduled
+         * The timers may be rescheduled, so explicitly disable them
+         * from being rescheduled.
          */
         if (!down)
                 set_bit(__E1000_DOWN, &adapter->state);
@@ -5996,8 +6044,8 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
         cancel_work_sync(&adapter->watchdog_task);
         cancel_work_sync(&adapter->downshift_task);
         cancel_work_sync(&adapter->update_phy_task);
+        cancel_work_sync(&adapter->led_blink_task);
         cancel_work_sync(&adapter->print_hang_task);
-        flush_scheduled_work();
 
         if (!(netdev->flags & IFF_UP))
                 e1000_power_down_phy(adapter);
@@ -6014,7 +6062,7 @@ static void __devexit e1000_remove(struct pci_dev *pdev)
          * Release control of h/w to f/w.  If f/w is AMT enabled, this
          * would have already happened in close and is redundant.
          */
-        e1000_release_hw_control(adapter);
+        e1000e_release_hw_control(adapter);
 
         e1000e_reset_interrupt_capability(adapter);
         kfree(adapter->tx_ring);
diff --git a/drivers/net/e1000e/param.c b/drivers/net/e1000e/param.c
index 3d36911f77f3..a9612b0e4bca 100644
--- a/drivers/net/e1000e/param.c
+++ b/drivers/net/e1000e/param.c
@@ -421,7 +421,7 @@ void __devinit e1000e_check_options(struct e1000_adapter *adapter)
                 static const struct e1000_option opt = {
                         .type = enable_option,
                         .name = "CRC Stripping",
-                        .err  = "defaulting to enabled",
+                        .err  = "defaulting to Enabled",
                         .def  = OPTION_ENABLED
                 };
 
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c
index b9bff5ba009f..00f89e8a9fa0 100644
--- a/drivers/net/e1000e/phy.c
+++ b/drivers/net/e1000e/phy.c
@@ -42,20 +42,20 @@ static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
                                           u16 *data, bool read);
 
 /* Cable length tables */
-static const u16 e1000_m88_cable_length_table[] =
-        { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
+static const u16 e1000_m88_cable_length_table[] = {
+        0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
                 ARRAY_SIZE(e1000_m88_cable_length_table)
 
-static const u16 e1000_igp_2_cable_length_table[] =
-        { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
-          6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
-          26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
-          44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
-          66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
-          87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
-          100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
-          124};
+static const u16 e1000_igp_2_cable_length_table[] = {
+        0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
+        6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
+        26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
+        44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
+        66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
+        87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
+        100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
+        124};
 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
                 ARRAY_SIZE(e1000_igp_2_cable_length_table)
 
@@ -226,6 +226,13 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
         }
         *data = (u16) mdic;
 
+        /*
+         * Allow some time after each MDIC transaction to avoid
+         * reading duplicate data in the next MDIC transaction.
+         */
+        if (hw->mac.type == e1000_pch2lan)
+                udelay(100);
+
         return 0;
 }
 
@@ -279,6 +286,13 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
                 return -E1000_ERR_PHY;
         }
 
+        /*
+         * Allow some time after each MDIC transaction to avoid
+         * reading duplicate data in the next MDIC transaction.
+         */
+        if (hw->mac.type == e1000_pch2lan)
+                udelay(100);
+
         return 0;
 }
 
@@ -623,12 +637,11 @@ s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
  **/
 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
 {
-        struct e1000_phy_info *phy = &hw->phy;
         s32 ret_val;
         u16 phy_data;
 
         /* Enable CRS on TX. This must be set for half-duplex operation. */
-        ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
+        ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
         if (ret_val)
                 goto out;
 
@@ -637,7 +650,7 @@ s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
         /* Enable downshift */
         phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
 
-        ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
+        ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
 
 out:
         return ret_val;
@@ -760,16 +773,14 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
         }
 
         if (phy->type == e1000_phy_82578) {
-                ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-                                            &phy_data);
+                ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
                 if (ret_val)
                         return ret_val;
 
                 /* 82578 PHY - set the downshift count to 1x. */
                 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
                 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
-                ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
-                                             phy_data);
+                ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
                 if (ret_val)
                         return ret_val;
         }
@@ -1043,9 +1054,8 @@ static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
 
         e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
 
-        if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
+        if (phy->autoneg_mask & ADVERTISE_1000_FULL)
                 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
-        }
 
         return ret_val;
 }
@@ -1306,9 +1316,8 @@ s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
                                  * We didn't get link.
                                  * Reset the DSP and cross our fingers.
                                  */
-                                ret_val = e1e_wphy(hw,
-                                                M88E1000_PHY_PAGE_SELECT,
-                                                0x001d);
+                                ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
+                                                   0x001d);
                                 if (ret_val)
                                         return ret_val;
                                 ret_val = e1000e_phy_reset_dsp(hw);
@@ -1840,11 +1849,12 @@ s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
         u16 phy_data, i, agc_value = 0;
         u16 cur_agc_index, max_agc_index = 0;
         u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
-        u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
-                                                         {IGP02E1000_PHY_AGC_A,
-                                                          IGP02E1000_PHY_AGC_B,
-                                                          IGP02E1000_PHY_AGC_C,
-                                                          IGP02E1000_PHY_AGC_D};
+        static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
+               IGP02E1000_PHY_AGC_A,
+               IGP02E1000_PHY_AGC_B,
+               IGP02E1000_PHY_AGC_C,
+               IGP02E1000_PHY_AGC_D
+        };
 
         /* Read the AGC registers for all channels */
         for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
@@ -3057,12 +3067,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
                 goto out;
 
         /* Do not apply workaround if in PHY loopback bit 14 set */
-        hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
+        e1e_rphy(hw, PHY_CONTROL, &data);
         if (data & PHY_CONTROL_LB)
                 goto out;
 
         /* check if link is up and at 1Gbps */
-        ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
+        ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
         if (ret_val)
                 goto out;
 
@@ -3078,14 +3088,12 @@ s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
         mdelay(200);
 
         /* flush the packets in the fifo buffer */
-        ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-                                        HV_MUX_DATA_CTRL_GEN_TO_MAC |
-                                        HV_MUX_DATA_CTRL_FORCE_SPEED);
+        ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
+                           HV_MUX_DATA_CTRL_FORCE_SPEED);
         if (ret_val)
                 goto out;
 
-        ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
-                                        HV_MUX_DATA_CTRL_GEN_TO_MAC);
+        ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
 
 out:
         return ret_val;
@@ -3105,7 +3113,7 @@ s32 e1000_check_polarity_82577(struct e1000_hw *hw)
         s32 ret_val;
         u16 data;
 
-        ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
+        ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
 
         if (!ret_val)
                 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
@@ -3128,13 +3136,13 @@ s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
         u16 phy_data;
         bool link;
 
-        ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
+        ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
         if (ret_val)
                 goto out;
 
         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 
-        ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
+        ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
         if (ret_val)
                 goto out;
 
@@ -3198,7 +3206,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
         if (ret_val)
                 goto out;
 
-        ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
+        ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
         if (ret_val)
                 goto out;
 
@@ -3210,7 +3218,7 @@ s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
                 if (ret_val)
                         goto out;
 
-                ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
+                ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
                 if (ret_val)
                         goto out;
 
@@ -3244,7 +3252,7 @@ s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
         s32 ret_val;
         u16 phy_data, length;
 
-        ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
+        ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
         if (ret_val)
                 goto out;
 
diff --git a/drivers/net/e2100.c b/drivers/net/e2100.c
index 06e72fbef862..94ec973b2bdc 100644
--- a/drivers/net/e2100.c
+++ b/drivers/net/e2100.c
@@ -216,7 +216,7 @@ static int __init e21_probe1(struct net_device *dev, int ioaddr)
                 printk(" %02X", station_addr[i]);
 
         if (dev->irq < 2) {
-                int irqlist[] = {15, 11, 10, 12, 5, 9, 3, 4};
+                static const int irqlist[] = {15, 11, 10, 12, 5, 9, 3, 4};
                 for (i = 0; i < ARRAY_SIZE(irqlist); i++)
                         if (request_irq (irqlist[i], NULL, 0, "bogus", NULL) != -EBUSY) {
                                 dev->irq = irqlist[i];
diff --git a/drivers/net/eepro.c b/drivers/net/eepro.c
index dbaec546c428..eb35951a2442 100644
--- a/drivers/net/eepro.c
+++ b/drivers/net/eepro.c
@@ -302,7 +302,7 @@ struct eepro_local {
 #define ee_id_eepro10p0 0x10   /* ID for eepro/10+ */
 #define ee_id_eepro10p1 0x31
 
-#define TX_TIMEOUT 40
+#define TX_TIMEOUT ((4*HZ)/10)
 
 /* Index to functions, as function prototypes. */
 
@@ -891,12 +891,13 @@ err:
    there is non-reboot way to recover if something goes wrong.
    */
 
-static char irqrmap[] = {-1,-1,0,1,-1,2,-1,-1,-1,0,3,4,-1,-1,-1,-1};
-static char irqrmap2[] = {-1,-1,4,0,1,2,-1,3,-1,4,5,6,7,-1,-1,-1};
+static const char irqrmap[] = {-1,-1,0,1,-1,2,-1,-1,-1,0,3,4,-1,-1,-1,-1};
+static const char irqrmap2[] = {-1,-1,4,0,1,2,-1,3,-1,4,5,6,7,-1,-1,-1};
 static int      eepro_grab_irq(struct net_device *dev)
 {
-        int irqlist[] = { 3, 4, 5, 7, 9, 10, 11, 12, 0 };
-        int *irqp = irqlist, temp_reg, ioaddr = dev->base_addr;
+        static const int irqlist[] = { 3, 4, 5, 7, 9, 10, 11, 12, 0 };
+        const int *irqp = irqlist;
+        int temp_reg, ioaddr = dev->base_addr;
 
         eepro_sw2bank1(ioaddr); /* be CAREFUL, BANK 1 now */
 
diff --git a/drivers/net/eexpress.c b/drivers/net/eexpress.c
index 12c37d264108..48ee51bb9e50 100644
--- a/drivers/net/eexpress.c
+++ b/drivers/net/eexpress.c
@@ -1103,7 +1103,7 @@ static int __init eexp_hw_probe(struct net_device *dev, unsigned short ioaddr)
                 dev->dev_addr[i] = ((unsigned char *)hw_addr)[5-i];
 
         {
-                static char irqmap[]={0, 9, 3, 4, 5, 10, 11, 0};
+                static const char irqmap[] = { 0, 9, 3, 4, 5, 10, 11, 0 };
                 unsigned short setupval = eexp_hw_readeeprom(ioaddr,0);
 
                 /* Use the IRQ from EEPROM if none was given */
diff --git a/drivers/net/ehea/ehea.h b/drivers/net/ehea/ehea.h
index 8e745e74828d..6c7257bd73fc 100644
--- a/drivers/net/ehea/ehea.h
+++ b/drivers/net/ehea/ehea.h
@@ -40,7 +40,7 @@
 #include <asm/io.h>
 
 #define DRV_NAME        "ehea"
-#define DRV_VERSION     "EHEA_0106"
+#define DRV_VERSION     "EHEA_0107"
 
 /* eHEA capability flags */
 #define DLPAR_PORT_ADD_REM 1
@@ -130,19 +130,6 @@
 
 /* utility functions */
 
-#define ehea_info(fmt, args...) \
-        printk(KERN_INFO DRV_NAME ": " fmt "\n", ## args)
-
-#define ehea_error(fmt, args...) \
-        printk(KERN_ERR DRV_NAME ": Error in %s: " fmt "\n", __func__, ## args)
-
-#ifdef DEBUG
-#define ehea_debug(fmt, args...) \
-        printk(KERN_DEBUG DRV_NAME ": " fmt, ## args)
-#else
-#define ehea_debug(fmt, args...) do {} while (0)
-#endif
-
 void ehea_dump(void *adr, int len, char *msg);
 
 #define EHEA_BMASK(pos, length) (((pos) << 16) + (length))
@@ -515,6 +502,4 @@ void ehea_set_ethtool_ops(struct net_device *netdev);
 int ehea_sense_port_attr(struct ehea_port *port);
 int ehea_set_portspeed(struct ehea_port *port, u32 port_speed);
 
-extern struct work_struct ehea_rereg_mr_task;
-
 #endif  /* __EHEA_H__ */
diff --git a/drivers/net/ehea/ehea_ethtool.c b/drivers/net/ehea/ehea_ethtool.c
index 1f37ee6b2a26..3e2e734fecb7 100644
--- a/drivers/net/ehea/ehea_ethtool.c
+++ b/drivers/net/ehea/ehea_ethtool.c
@@ -26,6 +26,8 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include "ehea.h"
 #include "ehea_phyp.h"
 
@@ -118,10 +120,10 @@ doit:
         ret = ehea_set_portspeed(port, sp);
 
         if (!ret)
-                ehea_info("%s: Port speed successfully set: %dMbps "
-                          "%s Duplex",
-                          port->netdev->name, port->port_speed,
-                          port->full_duplex == 1 ? "Full" : "Half");
+                netdev_info(dev,
+                            "Port speed successfully set: %dMbps %s Duplex\n",
+                            port->port_speed,
+                            port->full_duplex == 1 ? "Full" : "Half");
 out:
         return ret;
 }
@@ -134,10 +136,10 @@ static int ehea_nway_reset(struct net_device *dev)
         ret = ehea_set_portspeed(port, EHEA_SPEED_AUTONEG);
 
         if (!ret)
-                ehea_info("%s: Port speed successfully set: %dMbps "
-                          "%s Duplex",
-                          port->netdev->name, port->port_speed,
-                          port->full_duplex == 1 ? "Full" : "Half");
+                netdev_info(port->netdev,
+                            "Port speed successfully set: %dMbps %s Duplex\n",
+                            port->port_speed,
+                            port->full_duplex == 1 ? "Full" : "Half");
         return ret;
 }
 
@@ -263,6 +265,13 @@ static void ehea_get_ethtool_stats(struct net_device *dev,
 
 static int ehea_set_flags(struct net_device *dev, u32 data)
 {
+        /* Avoid changing the VLAN flags */
+        if ((data & (ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN)) !=
+            (ethtool_op_get_flags(dev) & (ETH_FLAG_RXVLAN |
+                                          ETH_FLAG_TXVLAN))){
+                return -EINVAL;
+        }
+
         return ethtool_op_set_flags(dev, data, ETH_FLAG_LRO
                                         | ETH_FLAG_TXVLAN
                                         | ETH_FLAG_RXVLAN);
diff --git a/drivers/net/ehea/ehea_main.c b/drivers/net/ehea/ehea_main.c
index b95f087cd5a9..f75d3144b8a5 100644
--- a/drivers/net/ehea/ehea_main.c
+++ b/drivers/net/ehea/ehea_main.c
@@ -26,6 +26,8 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/in.h>
 #include <linux/ip.h>
 #include <linux/tcp.h>
@@ -101,7 +103,6 @@ MODULE_PARM_DESC(use_lro, " Large Receive Offload, 1: enable, 0: disable, "
 static int port_name_cnt;
 static LIST_HEAD(adapter_list);
 static unsigned long ehea_driver_flags;
-struct work_struct ehea_rereg_mr_task;
 static DEFINE_MUTEX(dlpar_mem_lock);
 struct ehea_fw_handle_array ehea_fw_handles;
 struct ehea_bcmc_reg_array ehea_bcmc_regs;
@@ -136,8 +137,8 @@ void ehea_dump(void *adr, int len, char *msg)
         int x;
         unsigned char *deb = adr;
         for (x = 0; x < len; x += 16) {
-                printk(DRV_NAME " %s adr=%p ofs=%04x %016llx %016llx\n", msg,
-                          deb, x, *((u64 *)&deb[0]), *((u64 *)&deb[8]));
+                pr_info("%s adr=%p ofs=%04x %016llx %016llx\n",
+                        msg, deb, x, *((u64 *)&deb[0]), *((u64 *)&deb[8]));
                 deb += 16;
         }
 }
@@ -337,7 +338,7 @@ static struct net_device_stats *ehea_get_stats(struct net_device *dev)
 
         cb2 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb2) {
-                ehea_error("no mem for cb2");
+                netdev_err(dev, "no mem for cb2\n");
                 goto out;
         }
 
@@ -345,7 +346,7 @@ static struct net_device_stats *ehea_get_stats(struct net_device *dev)
                                       port->logical_port_id,
                                       H_PORT_CB2, H_PORT_CB2_ALL, cb2);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_port failed");
+                netdev_err(dev, "query_ehea_port failed\n");
                 goto out_herr;
         }
 
@@ -400,7 +401,7 @@ static void ehea_refill_rq1(struct ehea_port_res *pr, int index, int nr_of_wqes)
                         skb_arr_rq1[index] = netdev_alloc_skb(dev,
                                                               EHEA_L_PKT_SIZE);
                         if (!skb_arr_rq1[index]) {
-                                ehea_info("Unable to allocate enough skb in the array\n");
+                                netdev_info(dev, "Unable to allocate enough skb in the array\n");
                                 pr->rq1_skba.os_skbs = fill_wqes - i;
                                 break;
                         }
@@ -424,19 +425,19 @@ static void ehea_init_fill_rq1(struct ehea_port_res *pr, int nr_rq1a)
         int i;
 
         if (nr_rq1a > pr->rq1_skba.len) {
-                ehea_error("NR_RQ1A bigger than skb array len\n");
+                netdev_err(dev, "NR_RQ1A bigger than skb array len\n");
                 return;
         }
 
         for (i = 0; i < nr_rq1a; i++) {
                 skb_arr_rq1[i] = netdev_alloc_skb(dev, EHEA_L_PKT_SIZE);
                 if (!skb_arr_rq1[i]) {
-                        ehea_info("No enough memory to allocate skb array\n");
+                        netdev_info(dev, "Not enough memory to allocate skb array\n");
                         break;
                 }
         }
         /* Ring doorbell */
-        ehea_update_rq1a(pr->qp, i);
+        ehea_update_rq1a(pr->qp, i - 1);
 }
 
 static int ehea_refill_rq_def(struct ehea_port_res *pr,
@@ -469,8 +470,9 @@ static int ehea_refill_rq_def(struct ehea_port_res *pr,
                 if (!skb) {
                         q_skba->os_skbs = fill_wqes - i;
                         if (q_skba->os_skbs == q_skba->len - 2) {
-                                ehea_info("%s: rq%i ran dry - no mem for skb",
-                                          pr->port->netdev->name, rq_nr);
+                                netdev_info(pr->port->netdev,
+                                            "rq%i ran dry - no mem for skb\n",
+                                            rq_nr);
                                 ret = -ENOMEM;
                         }
                         break;
@@ -635,8 +637,8 @@ static int ehea_treat_poll_error(struct ehea_port_res *pr, int rq,
 
         if (cqe->status & EHEA_CQE_STAT_FAT_ERR_MASK) {
                 if (netif_msg_rx_err(pr->port)) {
-                        ehea_error("Critical receive error for QP %d. "
-                                   "Resetting port.", pr->qp->init_attr.qp_nr);
+                        pr_err("Critical receive error for QP %d. Resetting port.\n",
+                               pr->qp->init_attr.qp_nr);
                         ehea_dump(cqe, sizeof(*cqe), "CQE");
                 }
                 ehea_schedule_port_reset(pr->port);
@@ -738,13 +740,13 @@ static int ehea_proc_rwqes(struct net_device *dev,
                                                           skb_arr_rq1_len,
                                                           wqe_index);
                                 if (unlikely(!skb)) {
-                                        if (netif_msg_rx_err(port))
-                                                ehea_error("LL rq1: skb=NULL");
+                                        netif_info(port, rx_err, dev,
+                                                  "LL rq1: skb=NULL\n");
 
                                         skb = netdev_alloc_skb(dev,
                                                                EHEA_L_PKT_SIZE);
                                         if (!skb) {
-                                                ehea_info("Not enough memory to allocate skb\n");
+                                                netdev_err(dev, "Not enough memory to allocate skb\n");
                                                 break;
                                         }
                                 }
@@ -756,8 +758,8 @@ static int ehea_proc_rwqes(struct net_device *dev,
                                 skb = get_skb_by_index(skb_arr_rq2,
                                                        skb_arr_rq2_len, cqe);
                                 if (unlikely(!skb)) {
-                                        if (netif_msg_rx_err(port))
-                                                ehea_error("rq2: skb=NULL");
+                                        netif_err(port, rx_err, dev,
+                                                  "rq2: skb=NULL\n");
                                         break;
                                 }
                                 ehea_fill_skb(dev, skb, cqe);
@@ -767,8 +769,8 @@ static int ehea_proc_rwqes(struct net_device *dev,
                                 skb = get_skb_by_index(skb_arr_rq3,
                                                        skb_arr_rq3_len, cqe);
                                 if (unlikely(!skb)) {
-                                        if (netif_msg_rx_err(port))
-                                                ehea_error("rq3: skb=NULL");
+                                        netif_err(port, rx_err, dev,
+                                                  "rq3: skb=NULL\n");
                                         break;
                                 }
                                 ehea_fill_skb(dev, skb, cqe);
@@ -840,7 +842,7 @@ static void check_sqs(struct ehea_port *port)
                                          msecs_to_jiffies(100));
 
                 if (!ret) {
-                        ehea_error("HW/SW queues out of sync");
+                        pr_err("HW/SW queues out of sync\n");
                         ehea_schedule_port_reset(pr->port);
                         return;
                 }
@@ -873,14 +875,14 @@ static struct ehea_cqe *ehea_proc_cqes(struct ehea_port_res *pr, int my_quota)
                 }
 
                 if (cqe->status & EHEA_CQE_STAT_ERR_MASK) {
-                        ehea_error("Bad send completion status=0x%04X",
-                                   cqe->status);
+                        pr_err("Bad send completion status=0x%04X\n",
+                               cqe->status);
 
                         if (netif_msg_tx_err(pr->port))
                                 ehea_dump(cqe, sizeof(*cqe), "Send CQE");
 
                         if (cqe->status & EHEA_CQE_STAT_RESET_MASK) {
-                                ehea_error("Resetting port");
+                                pr_err("Resetting port\n");
                                 ehea_schedule_port_reset(pr->port);
                                 break;
                         }
@@ -998,8 +1000,8 @@ static irqreturn_t ehea_qp_aff_irq_handler(int irq, void *param)
 
         while (eqe) {
                 qp_token = EHEA_BMASK_GET(EHEA_EQE_QP_TOKEN, eqe->entry);
-                ehea_error("QP aff_err: entry=0x%llx, token=0x%x",
-                           eqe->entry, qp_token);
+                pr_err("QP aff_err: entry=0x%llx, token=0x%x\n",
+                       eqe->entry, qp_token);
 
                 qp = port->port_res[qp_token].qp;
 
@@ -1017,7 +1019,7 @@ static irqreturn_t ehea_qp_aff_irq_handler(int irq, void *param)
         }
 
         if (reset_port) {
-                ehea_error("Resetting port");
+                pr_err("Resetting port\n");
                 ehea_schedule_port_reset(port);
         }
 
@@ -1045,7 +1047,7 @@ int ehea_sense_port_attr(struct ehea_port *port)
         /* may be called via ehea_neq_tasklet() */
         cb0 = (void *)get_zeroed_page(GFP_ATOMIC);
         if (!cb0) {
-                ehea_error("no mem for cb0");
+                pr_err("no mem for cb0\n");
                 ret = -ENOMEM;
                 goto out;
         }
@@ -1137,7 +1139,7 @@ int ehea_set_portspeed(struct ehea_port *port, u32 port_speed)
 
         cb4 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb4) {
-                ehea_error("no mem for cb4");
+                pr_err("no mem for cb4\n");
                 ret = -ENOMEM;
                 goto out;
         }
@@ -1188,16 +1190,16 @@ int ehea_set_portspeed(struct ehea_port *port, u32 port_speed)
                                 break;
                         }
                 } else {
-                        ehea_error("Failed sensing port speed");
+                        pr_err("Failed sensing port speed\n");
                         ret = -EIO;
                 }
         } else {
                 if (hret == H_AUTHORITY) {
-                        ehea_info("Hypervisor denied setting port speed");
+                        pr_info("Hypervisor denied setting port speed\n");
                         ret = -EPERM;
                 } else {
                         ret = -EIO;
-                        ehea_error("Failed setting port speed");
+                        pr_err("Failed setting port speed\n");
                 }
         }
         if (!prop_carrier_state || (port->phy_link == EHEA_PHY_LINK_UP))
@@ -1214,80 +1216,78 @@ static void ehea_parse_eqe(struct ehea_adapter *adapter, u64 eqe)
         u8 ec;
         u8 portnum;
         struct ehea_port *port;
+        struct net_device *dev;
 
         ec = EHEA_BMASK_GET(NEQE_EVENT_CODE, eqe);
         portnum = EHEA_BMASK_GET(NEQE_PORTNUM, eqe);
         port = ehea_get_port(adapter, portnum);
+        dev = port->netdev;
 
         switch (ec) {
         case EHEA_EC_PORTSTATE_CHG:     /* port state change */
 
                 if (!port) {
-                        ehea_error("unknown portnum %x", portnum);
+                        netdev_err(dev, "unknown portnum %x\n", portnum);
                         break;
                 }
 
                 if (EHEA_BMASK_GET(NEQE_PORT_UP, eqe)) {
-                        if (!netif_carrier_ok(port->netdev)) {
+                        if (!netif_carrier_ok(dev)) {
                                 ret = ehea_sense_port_attr(port);
                                 if (ret) {
-                                        ehea_error("failed resensing port "
-                                                   "attributes");
+                                        netdev_err(dev, "failed resensing port attributes\n");
                                         break;
                                 }
 
-                                if (netif_msg_link(port))
-                                        ehea_info("%s: Logical port up: %dMbps "
-                                                  "%s Duplex",
-                                                  port->netdev->name,
-                                                  port->port_speed,
-                                                  port->full_duplex ==
-                                                  1 ? "Full" : "Half");
+                                netif_info(port, link, dev,
+                                           "Logical port up: %dMbps %s Duplex\n",
+                                           port->port_speed,
+                                           port->full_duplex == 1 ?
+                                           "Full" : "Half");
 
-                                netif_carrier_on(port->netdev);
-                                netif_wake_queue(port->netdev);
+                                netif_carrier_on(dev);
+                                netif_wake_queue(dev);
                         }
                 } else
-                        if (netif_carrier_ok(port->netdev)) {
-                                if (netif_msg_link(port))
-                                        ehea_info("%s: Logical port down",
-                                                  port->netdev->name);
-                                netif_carrier_off(port->netdev);
-                                netif_stop_queue(port->netdev);
+                        if (netif_carrier_ok(dev)) {
+                                netif_info(port, link, dev,
+                                           "Logical port down\n");
+                                netif_carrier_off(dev);
+                                netif_stop_queue(dev);
                         }
 
                 if (EHEA_BMASK_GET(NEQE_EXTSWITCH_PORT_UP, eqe)) {
                         port->phy_link = EHEA_PHY_LINK_UP;
-                        if (netif_msg_link(port))
-                                ehea_info("%s: Physical port up",
-                                          port->netdev->name);
+                        netif_info(port, link, dev,
+                                   "Physical port up\n");
                         if (prop_carrier_state)
-                                netif_carrier_on(port->netdev);
+                                netif_carrier_on(dev);
                 } else {
                         port->phy_link = EHEA_PHY_LINK_DOWN;
-                        if (netif_msg_link(port))
-                                ehea_info("%s: Physical port down",
-                                          port->netdev->name);
+                        netif_info(port, link, dev,
+                                   "Physical port down\n");
                         if (prop_carrier_state)
-                                netif_carrier_off(port->netdev);
+                                netif_carrier_off(dev);
                 }
 
                 if (EHEA_BMASK_GET(NEQE_EXTSWITCH_PRIMARY, eqe))
-                        ehea_info("External switch port is primary port");
+                        netdev_info(dev,
+                                    "External switch port is primary port\n");
                 else
-                        ehea_info("External switch port is backup port");
+                        netdev_info(dev,
+                                    "External switch port is backup port\n");
 
                 break;
         case EHEA_EC_ADAPTER_MALFUNC:
-                ehea_error("Adapter malfunction");
+                netdev_err(dev, "Adapter malfunction\n");
                 break;
         case EHEA_EC_PORT_MALFUNC:
-                ehea_info("Port malfunction: Device: %s", port->netdev->name);
-                netif_carrier_off(port->netdev);
-                netif_stop_queue(port->netdev);
+                netdev_info(dev, "Port malfunction\n");
+                netif_carrier_off(dev);
+                netif_stop_queue(dev);
                 break;
         default:
-                ehea_error("unknown event code %x, eqe=0x%llX", ec, eqe);
+                netdev_err(dev, "unknown event code %x, eqe=0x%llX\n", ec, eqe);
                 break;
         }
 }
@@ -1299,13 +1299,13 @@ static void ehea_neq_tasklet(unsigned long data)
         u64 event_mask;
 
         eqe = ehea_poll_eq(adapter->neq);
-        ehea_debug("eqe=%p", eqe);
+        pr_debug("eqe=%p\n", eqe);
 
         while (eqe) {
-                ehea_debug("*eqe=%lx", eqe->entry);
+                pr_debug("*eqe=%lx\n", (unsigned long) eqe->entry);
                 ehea_parse_eqe(adapter, eqe->entry);
                 eqe = ehea_poll_eq(adapter->neq);
-                ehea_debug("next eqe=%p", eqe);
+                pr_debug("next eqe=%p\n", eqe);
         }
 
         event_mask = EHEA_BMASK_SET(NELR_PORTSTATE_CHG, 1)
@@ -1329,9 +1329,7 @@ static int ehea_fill_port_res(struct ehea_port_res *pr)
         int ret;
         struct ehea_qp_init_attr *init_attr = &pr->qp->init_attr;
 
-        ehea_init_fill_rq1(pr, init_attr->act_nr_rwqes_rq1
-                               - init_attr->act_nr_rwqes_rq2
-                               - init_attr->act_nr_rwqes_rq3 - 1);
+        ehea_init_fill_rq1(pr, pr->rq1_skba.len);
 
         ret = ehea_refill_rq2(pr, init_attr->act_nr_rwqes_rq2 - 1);
 
@@ -1354,14 +1352,14 @@ static int ehea_reg_interrupts(struct net_device *dev)
                                   ehea_qp_aff_irq_handler,
                                   IRQF_DISABLED, port->int_aff_name, port);
         if (ret) {
-                ehea_error("failed registering irq for qp_aff_irq_handler:"
-                           "ist=%X", port->qp_eq->attr.ist1);
+                netdev_err(dev, "failed registering irq for qp_aff_irq_handler:ist=%X\n",
+                           port->qp_eq->attr.ist1);
                 goto out_free_qpeq;
         }
 
-        if (netif_msg_ifup(port))
-                ehea_info("irq_handle 0x%X for function qp_aff_irq_handler "
-                          "registered", port->qp_eq->attr.ist1);
+        netif_info(port, ifup, dev,
+                   "irq_handle 0x%X for function qp_aff_irq_handler registered\n",
+                   port->qp_eq->attr.ist1);
 
 
         for (i = 0; i < port->num_def_qps + port->num_add_tx_qps; i++) {
@@ -1373,14 +1371,13 @@ static int ehea_reg_interrupts(struct net_device *dev)
                                           IRQF_DISABLED, pr->int_send_name,
                                           pr);
                 if (ret) {
-                        ehea_error("failed registering irq for ehea_queue "
-                                   "port_res_nr:%d, ist=%X", i,
-                                   pr->eq->attr.ist1);
+                        netdev_err(dev, "failed registering irq for ehea_queue port_res_nr:%d, ist=%X\n",
+                                   i, pr->eq->attr.ist1);
                         goto out_free_req;
                 }
-                if (netif_msg_ifup(port))
-                        ehea_info("irq_handle 0x%X for function ehea_queue_int "
-                                  "%d registered", pr->eq->attr.ist1, i);
+                netif_info(port, ifup, dev,
+                           "irq_handle 0x%X for function ehea_queue_int %d registered\n",
+                           pr->eq->attr.ist1, i);
         }
 out:
         return ret;
@@ -1411,16 +1408,16 @@ static void ehea_free_interrupts(struct net_device *dev)
         for (i = 0; i < port->num_def_qps + port->num_add_tx_qps; i++) {
                 pr = &port->port_res[i];
                 ibmebus_free_irq(pr->eq->attr.ist1, pr);
-                if (netif_msg_intr(port))
-                        ehea_info("free send irq for res %d with handle 0x%X",
-                                  i, pr->eq->attr.ist1);
+                netif_info(port, intr, dev,
+                           "free send irq for res %d with handle 0x%X\n",
+                           i, pr->eq->attr.ist1);
         }
 
         /* associated events */
         ibmebus_free_irq(port->qp_eq->attr.ist1, port);
-        if (netif_msg_intr(port))
-                ehea_info("associated event interrupt for handle 0x%X freed",
-                          port->qp_eq->attr.ist1);
+        netif_info(port, intr, dev,
+                   "associated event interrupt for handle 0x%X freed\n",
+                   port->qp_eq->attr.ist1);
 }
 
 static int ehea_configure_port(struct ehea_port *port)
@@ -1489,7 +1486,7 @@ int ehea_gen_smrs(struct ehea_port_res *pr)
 out_free:
         ehea_rem_mr(&pr->send_mr);
 out:
-        ehea_error("Generating SMRS failed\n");
+        pr_err("Generating SMRS failed\n");
         return -EIO;
 }
 
@@ -1506,12 +1503,10 @@ static int ehea_init_q_skba(struct ehea_q_skb_arr *q_skba, int max_q_entries)
 {
         int arr_size = sizeof(void *) * max_q_entries;
 
-        q_skba->arr = vmalloc(arr_size);
+        q_skba->arr = vzalloc(arr_size);
         if (!q_skba->arr)
                 return -ENOMEM;
 
-        memset(q_skba->arr, 0, arr_size);
-
         q_skba->len = max_q_entries;
         q_skba->index = 0;
         q_skba->os_skbs = 0;
@@ -1546,7 +1541,7 @@ static int ehea_init_port_res(struct ehea_port *port, struct ehea_port_res *pr,
 
         pr->eq = ehea_create_eq(adapter, eq_type, EHEA_MAX_ENTRIES_EQ, 0);
         if (!pr->eq) {
-                ehea_error("create_eq failed (eq)");
+                pr_err("create_eq failed (eq)\n");
                 goto out_free;
         }
 
@@ -1554,7 +1549,7 @@ static int ehea_init_port_res(struct ehea_port *port, struct ehea_port_res *pr,
                                      pr->eq->fw_handle,
                                      port->logical_port_id);
         if (!pr->recv_cq) {
-                ehea_error("create_cq failed (cq_recv)");
+                pr_err("create_cq failed (cq_recv)\n");
                 goto out_free;
         }
 
@@ -1562,19 +1557,19 @@ static int ehea_init_port_res(struct ehea_port *port, struct ehea_port_res *pr,
                                      pr->eq->fw_handle,
                                      port->logical_port_id);
         if (!pr->send_cq) {
-                ehea_error("create_cq failed (cq_send)");
+                pr_err("create_cq failed (cq_send)\n");
                 goto out_free;
         }
 
         if (netif_msg_ifup(port))
-                ehea_info("Send CQ: act_nr_cqes=%d, Recv CQ: act_nr_cqes=%d",
-                          pr->send_cq->attr.act_nr_of_cqes,
-                          pr->recv_cq->attr.act_nr_of_cqes);
+                pr_info("Send CQ: act_nr_cqes=%d, Recv CQ: act_nr_cqes=%d\n",
+                        pr->send_cq->attr.act_nr_of_cqes,
+                        pr->recv_cq->attr.act_nr_of_cqes);
 
         init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
         if (!init_attr) {
                 ret = -ENOMEM;
-                ehea_error("no mem for ehea_qp_init_attr");
+                pr_err("no mem for ehea_qp_init_attr\n");
                 goto out_free;
         }
 
@@ -1599,18 +1594,18 @@ static int ehea_init_port_res(struct ehea_port *port, struct ehea_port_res *pr,
 
         pr->qp = ehea_create_qp(adapter, adapter->pd, init_attr);
         if (!pr->qp) {
-                ehea_error("create_qp failed");
+                pr_err("create_qp failed\n");
                 ret = -EIO;
                 goto out_free;
         }
 
         if (netif_msg_ifup(port))
-                ehea_info("QP: qp_nr=%d\n act_nr_snd_wqe=%d\n nr_rwqe_rq1=%d\n "
-                          "nr_rwqe_rq2=%d\n nr_rwqe_rq3=%d", init_attr->qp_nr,
-                          init_attr->act_nr_send_wqes,
-                          init_attr->act_nr_rwqes_rq1,
-                          init_attr->act_nr_rwqes_rq2,
-                          init_attr->act_nr_rwqes_rq3);
+                pr_info("QP: qp_nr=%d\n act_nr_snd_wqe=%d\n nr_rwqe_rq1=%d\n nr_rwqe_rq2=%d\n nr_rwqe_rq3=%d\n",
+                        init_attr->qp_nr,
+                        init_attr->act_nr_send_wqes,
+                        init_attr->act_nr_rwqes_rq1,
+                        init_attr->act_nr_rwqes_rq2,
+                        init_attr->act_nr_rwqes_rq3);
 
         pr->sq_skba_size = init_attr->act_nr_send_wqes + 1;
 
@@ -1761,7 +1756,7 @@ static void write_swqe2_TSO(struct sk_buff *skb,
                         swqe->descriptors++;
                 }
         } else
-                ehea_error("cannot handle fragmented headers");
+                pr_err("cannot handle fragmented headers\n");
 }
 
 static void write_swqe2_nonTSO(struct sk_buff *skb,
@@ -1857,8 +1852,8 @@ static int ehea_broadcast_reg_helper(struct ehea_port *port, u32 hcallid)
                                      port->logical_port_id,
                                      reg_type, port->mac_addr, 0, hcallid);
         if (hret != H_SUCCESS) {
-                ehea_error("%sregistering bc address failed (tagged)",
-                           hcallid == H_REG_BCMC ? "" : "de");
+                pr_err("%sregistering bc address failed (tagged)\n",
+                       hcallid == H_REG_BCMC ? "" : "de");
                 ret = -EIO;
                 goto out_herr;
         }
@@ -1869,8 +1864,8 @@ static int ehea_broadcast_reg_helper(struct ehea_port *port, u32 hcallid)
                                      port->logical_port_id,
                                      reg_type, port->mac_addr, 0, hcallid);
         if (hret != H_SUCCESS) {
-                ehea_error("%sregistering bc address failed (vlan)",
-                           hcallid == H_REG_BCMC ? "" : "de");
+                pr_err("%sregistering bc address failed (vlan)\n",
+                       hcallid == H_REG_BCMC ? "" : "de");
                 ret = -EIO;
         }
 out_herr:
@@ -1892,7 +1887,7 @@ static int ehea_set_mac_addr(struct net_device *dev, void *sa)
 
         cb0 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb0) {
-                ehea_error("no mem for cb0");
+                pr_err("no mem for cb0\n");
                 ret = -ENOMEM;
                 goto out;
         }
@@ -1940,11 +1935,11 @@ out:
 static void ehea_promiscuous_error(u64 hret, int enable)
 {
         if (hret == H_AUTHORITY)
-                ehea_info("Hypervisor denied %sabling promiscuous mode",
-                          enable == 1 ? "en" : "dis");
+                pr_info("Hypervisor denied %sabling promiscuous mode\n",
+                        enable == 1 ? "en" : "dis");
         else
-                ehea_error("failed %sabling promiscuous mode",
-                           enable == 1 ? "en" : "dis");
+                pr_err("failed %sabling promiscuous mode\n",
+                       enable == 1 ? "en" : "dis");
 }
 
 static void ehea_promiscuous(struct net_device *dev, int enable)
@@ -1958,7 +1953,7 @@ static void ehea_promiscuous(struct net_device *dev, int enable)
 
         cb7 = (void *)get_zeroed_page(GFP_ATOMIC);
         if (!cb7) {
-                ehea_error("no mem for cb7");
+                pr_err("no mem for cb7\n");
                 goto out;
         }
 
@@ -2018,7 +2013,7 @@ static int ehea_drop_multicast_list(struct net_device *dev)
                 hret = ehea_multicast_reg_helper(port, mc_entry->macaddr,
                                                  H_DEREG_BCMC);
                 if (hret) {
-                        ehea_error("failed deregistering mcast MAC");
+                        pr_err("failed deregistering mcast MAC\n");
                         ret = -EIO;
                 }
 
@@ -2041,7 +2036,8 @@ static void ehea_allmulti(struct net_device *dev, int enable)
                         if (!hret)
                                 port->allmulti = 1;
                         else
-                                ehea_error("failed enabling IFF_ALLMULTI");
+                                netdev_err(dev,
+                                           "failed enabling IFF_ALLMULTI\n");
                 }
         } else
                 if (!enable) {
@@ -2050,7 +2046,8 @@ static void ehea_allmulti(struct net_device *dev, int enable)
                         if (!hret)
                                 port->allmulti = 0;
                         else
-                                ehea_error("failed disabling IFF_ALLMULTI");
+                                netdev_err(dev,
+                                           "failed disabling IFF_ALLMULTI\n");
                 }
 }
 
@@ -2061,7 +2058,7 @@ static void ehea_add_multicast_entry(struct ehea_port *port, u8 *mc_mac_addr)
 
         ehea_mcl_entry = kzalloc(sizeof(*ehea_mcl_entry), GFP_ATOMIC);
         if (!ehea_mcl_entry) {
-                ehea_error("no mem for mcl_entry");
+                pr_err("no mem for mcl_entry\n");
                 return;
         }
 
@@ -2074,7 +2071,7 @@ static void ehea_add_multicast_entry(struct ehea_port *port, u8 *mc_mac_addr)
         if (!hret)
                 list_add(&ehea_mcl_entry->list, &port->mc_list->list);
         else {
-                ehea_error("failed registering mcast MAC");
+                pr_err("failed registering mcast MAC\n");
                 kfree(ehea_mcl_entry);
         }
 }
@@ -2107,9 +2104,8 @@ static void ehea_set_multicast_list(struct net_device *dev)
                 }
 
                 if (netdev_mc_count(dev) > port->adapter->max_mc_mac) {
-                        ehea_info("Mcast registration limit reached (0x%llx). "
-                                  "Use ALLMULTI!",
-                                  port->adapter->max_mc_mac);
+                        pr_info("Mcast registration limit reached (0x%llx). Use ALLMULTI!\n",
+                                port->adapter->max_mc_mac);
                         goto out;
                 }
 
@@ -2315,10 +2311,10 @@ static int ehea_start_xmit(struct sk_buff *skb, struct net_device *dev)
         }
         pr->swqe_id_counter += 1;
 
-        if (netif_msg_tx_queued(port)) {
-                ehea_info("post swqe on QP %d", pr->qp->init_attr.qp_nr);
+        netif_info(port, tx_queued, dev,
+                   "post swqe on QP %d\n", pr->qp->init_attr.qp_nr);
+        if (netif_msg_tx_queued(port))
                 ehea_dump(swqe, 512, "swqe");
-        }
 
         if (unlikely(test_bit(__EHEA_STOP_XFER, &ehea_driver_flags))) {
                 netif_stop_queue(dev);
@@ -2354,14 +2350,14 @@ static void ehea_vlan_rx_register(struct net_device *dev,
 
         cb1 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb1) {
-                ehea_error("no mem for cb1");
+                pr_err("no mem for cb1\n");
                 goto out;
         }
 
         hret = ehea_h_modify_ehea_port(adapter->handle, port->logical_port_id,
                                        H_PORT_CB1, H_PORT_CB1_ALL, cb1);
         if (hret != H_SUCCESS)
-                ehea_error("modify_ehea_port failed");
+                pr_err("modify_ehea_port failed\n");
 
         free_page((unsigned long)cb1);
 out:
@@ -2378,14 +2374,14 @@ static void ehea_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
 
         cb1 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb1) {
-                ehea_error("no mem for cb1");
+                pr_err("no mem for cb1\n");
                 goto out;
         }
 
         hret = ehea_h_query_ehea_port(adapter->handle, port->logical_port_id,
                                       H_PORT_CB1, H_PORT_CB1_ALL, cb1);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_port failed");
+                pr_err("query_ehea_port failed\n");
                 goto out;
         }
 
@@ -2395,7 +2391,7 @@ static void ehea_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
         hret = ehea_h_modify_ehea_port(adapter->handle, port->logical_port_id,
                                        H_PORT_CB1, H_PORT_CB1_ALL, cb1);
         if (hret != H_SUCCESS)
-                ehea_error("modify_ehea_port failed");
+                pr_err("modify_ehea_port failed\n");
 out:
         free_page((unsigned long)cb1);
         return;
@@ -2413,14 +2409,14 @@ static void ehea_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 
         cb1 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb1) {
-                ehea_error("no mem for cb1");
+                pr_err("no mem for cb1\n");
                 goto out;
         }
 
         hret = ehea_h_query_ehea_port(adapter->handle, port->logical_port_id,
                                       H_PORT_CB1, H_PORT_CB1_ALL, cb1);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_port failed");
+                pr_err("query_ehea_port failed\n");
                 goto out;
         }
 
@@ -2430,7 +2426,7 @@ static void ehea_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
         hret = ehea_h_modify_ehea_port(adapter->handle, port->logical_port_id,
                                        H_PORT_CB1, H_PORT_CB1_ALL, cb1);
         if (hret != H_SUCCESS)
-                ehea_error("modify_ehea_port failed");
+                pr_err("modify_ehea_port failed\n");
 out:
         free_page((unsigned long)cb1);
 }
@@ -2452,7 +2448,7 @@ int ehea_activate_qp(struct ehea_adapter *adapter, struct ehea_qp *qp)
         hret = ehea_h_query_ehea_qp(adapter->handle, 0, qp->fw_handle,
                                     EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_qp failed (1)");
+                pr_err("query_ehea_qp failed (1)\n");
                 goto out;
         }
 
@@ -2461,14 +2457,14 @@ int ehea_activate_qp(struct ehea_adapter *adapter, struct ehea_qp *qp)
                                      EHEA_BMASK_SET(H_QPCB0_QP_CTL_REG, 1), cb0,
                                      &dummy64, &dummy64, &dummy16, &dummy16);
         if (hret != H_SUCCESS) {
-                ehea_error("modify_ehea_qp failed (1)");
+                pr_err("modify_ehea_qp failed (1)\n");
                 goto out;
         }
 
         hret = ehea_h_query_ehea_qp(adapter->handle, 0, qp->fw_handle,
                                     EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_qp failed (2)");
+                pr_err("query_ehea_qp failed (2)\n");
                 goto out;
         }
 
@@ -2477,14 +2473,14 @@ int ehea_activate_qp(struct ehea_adapter *adapter, struct ehea_qp *qp)
                                      EHEA_BMASK_SET(H_QPCB0_QP_CTL_REG, 1), cb0,
                                      &dummy64, &dummy64, &dummy16, &dummy16);
         if (hret != H_SUCCESS) {
-                ehea_error("modify_ehea_qp failed (2)");
+                pr_err("modify_ehea_qp failed (2)\n");
                 goto out;
         }
 
         hret = ehea_h_query_ehea_qp(adapter->handle, 0, qp->fw_handle,
                                     EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_qp failed (3)");
+                pr_err("query_ehea_qp failed (3)\n");
                 goto out;
         }
 
@@ -2493,14 +2489,14 @@ int ehea_activate_qp(struct ehea_adapter *adapter, struct ehea_qp *qp)
                                      EHEA_BMASK_SET(H_QPCB0_QP_CTL_REG, 1), cb0,
                                      &dummy64, &dummy64, &dummy16, &dummy16);
         if (hret != H_SUCCESS) {
-                ehea_error("modify_ehea_qp failed (3)");
+                pr_err("modify_ehea_qp failed (3)\n");
                 goto out;
         }
 
         hret = ehea_h_query_ehea_qp(adapter->handle, 0, qp->fw_handle,
                                     EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF), cb0);
         if (hret != H_SUCCESS) {
-                ehea_error("query_ehea_qp failed (4)");
+                pr_err("query_ehea_qp failed (4)\n");
                 goto out;
         }
 
@@ -2521,7 +2517,7 @@ static int ehea_port_res_setup(struct ehea_port *port, int def_qps,
                                    EHEA_MAX_ENTRIES_EQ, 1);
         if (!port->qp_eq) {
                 ret = -EINVAL;
-                ehea_error("ehea_create_eq failed (qp_eq)");
+                pr_err("ehea_create_eq failed (qp_eq)\n");
                 goto out_kill_eq;
         }
 
@@ -2602,27 +2598,27 @@ static int ehea_up(struct net_device *dev)
         ret = ehea_port_res_setup(port, port->num_def_qps,
                                   port->num_add_tx_qps);
         if (ret) {
-                ehea_error("port_res_failed");
+                netdev_err(dev, "port_res_failed\n");
                 goto out;
         }
 
         /* Set default QP for this port */
         ret = ehea_configure_port(port);
         if (ret) {
-                ehea_error("ehea_configure_port failed. ret:%d", ret);
+                netdev_err(dev, "ehea_configure_port failed. ret:%d\n", ret);
                 goto out_clean_pr;
         }
 
         ret = ehea_reg_interrupts(dev);
         if (ret) {
-                ehea_error("reg_interrupts failed. ret:%d", ret);
+                netdev_err(dev, "reg_interrupts failed. ret:%d\n", ret);
                 goto out_clean_pr;
         }
 
         for (i = 0; i < port->num_def_qps + port->num_add_tx_qps; i++) {
                 ret = ehea_activate_qp(port->adapter, port->port_res[i].qp);
                 if (ret) {
-                        ehea_error("activate_qp failed");
+                        netdev_err(dev, "activate_qp failed\n");
                         goto out_free_irqs;
                 }
         }
@@ -2630,7 +2626,7 @@ static int ehea_up(struct net_device *dev)
         for (i = 0; i < port->num_def_qps; i++) {
                 ret = ehea_fill_port_res(&port->port_res[i]);
                 if (ret) {
-                        ehea_error("out_free_irqs");
+                        netdev_err(dev, "out_free_irqs\n");
                         goto out_free_irqs;
                 }
         }
@@ -2653,7 +2649,7 @@ out_clean_pr:
         ehea_clean_all_portres(port);
 out:
         if (ret)
-                ehea_info("Failed starting %s. ret=%i", dev->name, ret);
+                netdev_info(dev, "Failed starting. ret=%i\n", ret);
 
         ehea_update_bcmc_registrations();
         ehea_update_firmware_handles();
@@ -2684,8 +2680,7 @@ static int ehea_open(struct net_device *dev)
 
         mutex_lock(&port->port_lock);
 
-        if (netif_msg_ifup(port))
-                ehea_info("enabling port %s", dev->name);
+        netif_info(port, ifup, dev, "enabling port\n");
 
         ret = ehea_up(dev);
         if (!ret) {
@@ -2720,8 +2715,7 @@ static int ehea_down(struct net_device *dev)
 
         ret = ehea_clean_all_portres(port);
         if (ret)
-                ehea_info("Failed freeing resources for %s. ret=%i",
-                          dev->name, ret);
+                netdev_info(dev, "Failed freeing resources. ret=%i\n", ret);
 
         ehea_update_firmware_handles();
 
@@ -2733,8 +2727,7 @@ static int ehea_stop(struct net_device *dev)
         int ret;
         struct ehea_port *port = netdev_priv(dev);
 
-        if (netif_msg_ifdown(port))
-                ehea_info("disabling port %s", dev->name);
+        netif_info(port, ifdown, dev, "disabling port\n");
 
         set_bit(__EHEA_DISABLE_PORT_RESET, &port->flags);
         cancel_work_sync(&port->reset_task);
@@ -2775,7 +2768,7 @@ static void ehea_flush_sq(struct ehea_port *port)
                          msecs_to_jiffies(100));
 
                 if (!ret) {
-                        ehea_error("WARNING: sq not flushed completely");
+                        pr_err("WARNING: sq not flushed completely\n");
                         break;
                 }
         }
@@ -2811,7 +2804,7 @@ int ehea_stop_qps(struct net_device *dev)
                                             EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF),
                                             cb0);
                 if (hret != H_SUCCESS) {
-                        ehea_error("query_ehea_qp failed (1)");
+                        pr_err("query_ehea_qp failed (1)\n");
                         goto out;
                 }
 
@@ -2823,7 +2816,7 @@ int ehea_stop_qps(struct net_device *dev)
                                                             1), cb0, &dummy64,
                                              &dummy64, &dummy16, &dummy16);
                 if (hret != H_SUCCESS) {
-                        ehea_error("modify_ehea_qp failed (1)");
+                        pr_err("modify_ehea_qp failed (1)\n");
                         goto out;
                 }
 
@@ -2831,14 +2824,14 @@ int ehea_stop_qps(struct net_device *dev)
                                             EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF),
                                             cb0);
                 if (hret != H_SUCCESS) {
-                        ehea_error("query_ehea_qp failed (2)");
+                        pr_err("query_ehea_qp failed (2)\n");
                         goto out;
                 }
 
                 /* deregister shared memory regions */
                 dret = ehea_rem_smrs(pr);
                 if (dret) {
-                        ehea_error("unreg shared memory region failed");
+                        pr_err("unreg shared memory region failed\n");
                         goto out;
                 }
         }
@@ -2907,7 +2900,7 @@ int ehea_restart_qps(struct net_device *dev)
 
                 ret = ehea_gen_smrs(pr);
                 if (ret) {
-                        ehea_error("creation of shared memory regions failed");
+                        netdev_err(dev, "creation of shared memory regions failed\n");
                         goto out;
                 }
 
@@ -2918,7 +2911,7 @@ int ehea_restart_qps(struct net_device *dev)
                                             EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF),
                                             cb0);
                 if (hret != H_SUCCESS) {
-                        ehea_error("query_ehea_qp failed (1)");
+                        netdev_err(dev, "query_ehea_qp failed (1)\n");
                         goto out;
                 }
 
@@ -2930,7 +2923,7 @@ int ehea_restart_qps(struct net_device *dev)
                                                             1), cb0, &dummy64,
                                              &dummy64, &dummy16, &dummy16);
                 if (hret != H_SUCCESS) {
-                        ehea_error("modify_ehea_qp failed (1)");
+                        netdev_err(dev, "modify_ehea_qp failed (1)\n");
                         goto out;
                 }
 
@@ -2938,7 +2931,7 @@ int ehea_restart_qps(struct net_device *dev)
                                             EHEA_BMASK_SET(H_QPCB0_ALL, 0xFFFF),
                                             cb0);
                 if (hret != H_SUCCESS) {
-                        ehea_error("query_ehea_qp failed (2)");
+                        netdev_err(dev, "query_ehea_qp failed (2)\n");
                         goto out;
                 }
 
@@ -2975,8 +2968,7 @@ static void ehea_reset_port(struct work_struct *work)
 
         ehea_set_multicast_list(dev);
 
-        if (netif_msg_timer(port))
-                ehea_info("Device %s resetted successfully", dev->name);
+        netif_info(port, timer, dev, "reset successful\n");
 
         port_napi_enable(port);
 
@@ -2986,12 +2978,12 @@ out:
         mutex_unlock(&dlpar_mem_lock);
 }
 
-static void ehea_rereg_mrs(struct work_struct *work)
+static void ehea_rereg_mrs(void)
 {
         int ret, i;
         struct ehea_adapter *adapter;
 
-        ehea_info("LPAR memory changed - re-initializing driver");
+        pr_info("LPAR memory changed - re-initializing driver\n");
 
         list_for_each_entry(adapter, &adapter_list, list)
                 if (adapter->active_ports) {
@@ -3023,8 +3015,7 @@ static void ehea_rereg_mrs(struct work_struct *work)
                         /* Unregister old memory region */
                         ret = ehea_rem_mr(&adapter->mr);
                         if (ret) {
-                                ehea_error("unregister MR failed - driver"
-                                           " inoperable!");
+                                pr_err("unregister MR failed - driver inoperable!\n");
                                 goto out;
                         }
                 }
@@ -3036,8 +3027,7 @@ static void ehea_rereg_mrs(struct work_struct *work)
                         /* Register new memory region */
                         ret = ehea_reg_kernel_mr(adapter, &adapter->mr);
                         if (ret) {
-                                ehea_error("register MR failed - driver"
-                                           " inoperable!");
+                                pr_err("register MR failed - driver inoperable!\n");
                                 goto out;
                         }
 
@@ -3060,7 +3050,7 @@ static void ehea_rereg_mrs(struct work_struct *work)
                                 }
                         }
                 }
-        ehea_info("re-initializing driver complete");
+        pr_info("re-initializing driver complete\n");
 out:
         return;
 }
@@ -3113,7 +3103,7 @@ int ehea_get_jumboframe_status(struct ehea_port *port, int *jumbo)
         /* (Try to) enable *jumbo frames */
         cb4 = (void *)get_zeroed_page(GFP_KERNEL);
         if (!cb4) {
-                ehea_error("no mem for cb4");
+                pr_err("no mem for cb4\n");
                 ret = -ENOMEM;
                 goto out;
         } else {
@@ -3175,13 +3165,13 @@ static struct device *ehea_register_port(struct ehea_port *port,
 
         ret = of_device_register(&port->ofdev);
         if (ret) {
-                ehea_error("failed to register device. ret=%d", ret);
+                pr_err("failed to register device. ret=%d\n", ret);
                 goto out;
         }
 
         ret = device_create_file(&port->ofdev.dev, &dev_attr_log_port_id);
         if (ret) {
-                ehea_error("failed to register attributes, ret=%d", ret);
+                pr_err("failed to register attributes, ret=%d\n", ret);
                 goto out_unreg_of_dev;
         }
 
@@ -3231,7 +3221,7 @@ struct ehea_port *ehea_setup_single_port(struct ehea_adapter *adapter,
         dev = alloc_etherdev(sizeof(struct ehea_port));
 
         if (!dev) {
-                ehea_error("no mem for net_device");
+                pr_err("no mem for net_device\n");
                 ret = -ENOMEM;
                 goto out_err;
         }
@@ -3285,7 +3275,7 @@ struct ehea_port *ehea_setup_single_port(struct ehea_adapter *adapter,
 
         ret = register_netdev(dev);
         if (ret) {
-                ehea_error("register_netdev failed. ret=%d", ret);
+                pr_err("register_netdev failed. ret=%d\n", ret);
                 goto out_unreg_port;
         }
 
@@ -3293,11 +3283,10 @@ struct ehea_port *ehea_setup_single_port(struct ehea_adapter *adapter,
 
         ret = ehea_get_jumboframe_status(port, &jumbo);
         if (ret)
-                ehea_error("failed determining jumbo frame status for %s",
-                           port->netdev->name);
+                netdev_err(dev, "failed determining jumbo frame status\n");
 
-        ehea_info("%s: Jumbo frames are %sabled", dev->name,
-                  jumbo == 1 ? "en" : "dis");
+        netdev_info(dev, "Jumbo frames are %sabled\n",
+                    jumbo == 1 ? "en" : "dis");
 
         adapter->active_ports++;
 
@@ -3313,14 +3302,16 @@ out_free_ethdev:
         free_netdev(dev);
 
 out_err:
-        ehea_error("setting up logical port with id=%d failed, ret=%d",
-                   logical_port_id, ret);
+        pr_err("setting up logical port with id=%d failed, ret=%d\n",
+               logical_port_id, ret);
         return NULL;
 }
 
 static void ehea_shutdown_single_port(struct ehea_port *port)
 {
         struct ehea_adapter *adapter = port->adapter;
+
+        cancel_work_sync(&port->reset_task);
         unregister_netdev(port->netdev);
         ehea_unregister_port(port);
         kfree(port->mc_list);
@@ -3342,13 +3333,13 @@ static int ehea_setup_ports(struct ehea_adapter *adapter)
                 dn_log_port_id = of_get_property(eth_dn, "ibm,hea-port-no",
                                                  NULL);
                 if (!dn_log_port_id) {
-                        ehea_error("bad device node: eth_dn name=%s",
-                                   eth_dn->full_name);
+                        pr_err("bad device node: eth_dn name=%s\n",
+                               eth_dn->full_name);
                         continue;
                 }
 
                 if (ehea_add_adapter_mr(adapter)) {
-                        ehea_error("creating MR failed");
+                        pr_err("creating MR failed\n");
                         of_node_put(eth_dn);
                         return -EIO;
                 }
@@ -3357,9 +3348,8 @@ static int ehea_setup_ports(struct ehea_adapter *adapter)
                                                           *dn_log_port_id,
                                                           eth_dn);
                 if (adapter->port[i])
-                        ehea_info("%s -> logical port id #%d",
-                                  adapter->port[i]->netdev->name,
-                                  *dn_log_port_id);
+                        netdev_info(adapter->port[i]->netdev,
+                                    "logical port id #%d\n", *dn_log_port_id);
                 else
                         ehea_remove_adapter_mr(adapter);
 
@@ -3404,21 +3394,20 @@ static ssize_t ehea_probe_port(struct device *dev,
         port = ehea_get_port(adapter, logical_port_id);
 
         if (port) {
-                ehea_info("adding port with logical port id=%d failed. port "
-                          "already configured as %s.", logical_port_id,
-                          port->netdev->name);
+                netdev_info(port->netdev, "adding port with logical port id=%d failed: port already configured\n",
+                            logical_port_id);
                 return -EINVAL;
         }
 
         eth_dn = ehea_get_eth_dn(adapter, logical_port_id);
 
         if (!eth_dn) {
-                ehea_info("no logical port with id %d found", logical_port_id);
+                pr_info("no logical port with id %d found\n", logical_port_id);
                 return -EINVAL;
         }
 
         if (ehea_add_adapter_mr(adapter)) {
-                ehea_error("creating MR failed");
+                pr_err("creating MR failed\n");
                 return -EIO;
         }
 
@@ -3433,8 +3422,8 @@ static ssize_t ehea_probe_port(struct device *dev,
                                 break;
                         }
 
-                ehea_info("added %s (logical port id=%d)", port->netdev->name,
-                          logical_port_id);
+                netdev_info(port->netdev, "added: (logical port id=%d)\n",
+                            logical_port_id);
         } else {
                 ehea_remove_adapter_mr(adapter);
                 return -EIO;
@@ -3457,8 +3446,8 @@ static ssize_t ehea_remove_port(struct device *dev,
         port = ehea_get_port(adapter, logical_port_id);
 
         if (port) {
-                ehea_info("removed %s (logical port id=%d)", port->netdev->name,
-                          logical_port_id);
+                netdev_info(port->netdev, "removed: (logical port id=%d)\n",
+                            logical_port_id);
 
                 ehea_shutdown_single_port(port);
 
@@ -3468,8 +3457,8 @@ static ssize_t ehea_remove_port(struct device *dev,
                                 break;
                         }
         } else {
-                ehea_error("removing port with logical port id=%d failed. port "
-                           "not configured.", logical_port_id);
+                pr_err("removing port with logical port id=%d failed. port not configured.\n",
+                       logical_port_id);
                 return -EINVAL;
         }
 
@@ -3506,7 +3495,7 @@ static int __devinit ehea_probe_adapter(struct platform_device *dev,
         int ret;
 
         if (!dev || !dev->dev.of_node) {
-                ehea_error("Invalid ibmebus device probed");
+                pr_err("Invalid ibmebus device probed\n");
                 return -EINVAL;
         }
 
@@ -3610,8 +3599,6 @@ static int __devexit ehea_remove(struct platform_device *dev)
 
         ehea_remove_device_sysfs(dev);
 
-        flush_scheduled_work();
-
         ibmebus_free_irq(adapter->neq->attr.ist1, adapter);
         tasklet_kill(&adapter->neq_tasklet);
 
@@ -3654,21 +3641,21 @@ static int ehea_mem_notifier(struct notifier_block *nb,
 
         switch (action) {
         case MEM_CANCEL_OFFLINE:
-                ehea_info("memory offlining canceled");
+                pr_info("memory offlining canceled");
                 /* Readd canceled memory block */
         case MEM_ONLINE:
-                ehea_info("memory is going online");
+                pr_info("memory is going online");
                 set_bit(__EHEA_STOP_XFER, &ehea_driver_flags);
                 if (ehea_add_sect_bmap(arg->start_pfn, arg->nr_pages))
                         goto out_unlock;
-                ehea_rereg_mrs(NULL);
+                ehea_rereg_mrs();
                 break;
         case MEM_GOING_OFFLINE:
-                ehea_info("memory is going offline");
+                pr_info("memory is going offline");
                 set_bit(__EHEA_STOP_XFER, &ehea_driver_flags);
                 if (ehea_rem_sect_bmap(arg->start_pfn, arg->nr_pages))
                         goto out_unlock;
-                ehea_rereg_mrs(NULL);
+                ehea_rereg_mrs();
                 break;
         default:
                 break;
@@ -3690,7 +3677,7 @@ static int ehea_reboot_notifier(struct notifier_block *nb,
                                 unsigned long action, void *unused)
 {
         if (action == SYS_RESTART) {
-                ehea_info("Reboot: freeing all eHEA resources");
+                pr_info("Reboot: freeing all eHEA resources\n");
                 ibmebus_unregister_driver(&ehea_driver);
         }
         return NOTIFY_DONE;
@@ -3706,22 +3693,22 @@ static int check_module_parm(void)
 
         if ((rq1_entries < EHEA_MIN_ENTRIES_QP) ||
             (rq1_entries > EHEA_MAX_ENTRIES_RQ1)) {
-                ehea_info("Bad parameter: rq1_entries");
+                pr_info("Bad parameter: rq1_entries\n");
                 ret = -EINVAL;
         }
         if ((rq2_entries < EHEA_MIN_ENTRIES_QP) ||
             (rq2_entries > EHEA_MAX_ENTRIES_RQ2)) {
-                ehea_info("Bad parameter: rq2_entries");
+                pr_info("Bad parameter: rq2_entries\n");
                 ret = -EINVAL;
         }
         if ((rq3_entries < EHEA_MIN_ENTRIES_QP) ||
             (rq3_entries > EHEA_MAX_ENTRIES_RQ3)) {
-                ehea_info("Bad parameter: rq3_entries");
+                pr_info("Bad parameter: rq3_entries\n");
                 ret = -EINVAL;
         }
         if ((sq_entries < EHEA_MIN_ENTRIES_QP) ||
             (sq_entries > EHEA_MAX_ENTRIES_SQ)) {
-                ehea_info("Bad parameter: sq_entries");
+                pr_info("Bad parameter: sq_entries\n");
                 ret = -EINVAL;
         }
 
@@ -3741,11 +3728,8 @@ int __init ehea_module_init(void)
 {
         int ret;
 
-        printk(KERN_INFO "IBM eHEA ethernet device driver (Release %s)\n",
-               DRV_VERSION);
-
+        pr_info("IBM eHEA ethernet device driver (Release %s)\n", DRV_VERSION);
 
-        INIT_WORK(&ehea_rereg_mr_task, ehea_rereg_mrs);
         memset(&ehea_fw_handles, 0, sizeof(ehea_fw_handles));
         memset(&ehea_bcmc_regs, 0, sizeof(ehea_bcmc_regs));
 
@@ -3762,27 +3746,27 @@ int __init ehea_module_init(void)
 
         ret = register_reboot_notifier(&ehea_reboot_nb);
         if (ret)
-                ehea_info("failed registering reboot notifier");
+                pr_info("failed registering reboot notifier\n");
 
         ret = register_memory_notifier(&ehea_mem_nb);
         if (ret)
-                ehea_info("failed registering memory remove notifier");
+                pr_info("failed registering memory remove notifier\n");
 
         ret = crash_shutdown_register(ehea_crash_handler);
         if (ret)
-                ehea_info("failed registering crash handler");
+                pr_info("failed registering crash handler\n");
 
         ret = ibmebus_register_driver(&ehea_driver);
         if (ret) {
-                ehea_error("failed registering eHEA device driver on ebus");
+                pr_err("failed registering eHEA device driver on ebus\n");
                 goto out2;
         }
 
         ret = driver_create_file(&ehea_driver.driver,
                                  &driver_attr_capabilities);
         if (ret) {
-                ehea_error("failed to register capabilities attribute, ret=%d",
-                           ret);
+                pr_err("failed to register capabilities attribute, ret=%d\n",
+                       ret);
                 goto out3;
         }
 
@@ -3802,13 +3786,12 @@ static void __exit ehea_module_exit(void)
 {
         int ret;
 
-        flush_scheduled_work();
         driver_remove_file(&ehea_driver.driver, &driver_attr_capabilities);
         ibmebus_unregister_driver(&ehea_driver);
         unregister_reboot_notifier(&ehea_reboot_nb);
         ret = crash_shutdown_unregister(ehea_crash_handler);
         if (ret)
-                ehea_info("failed unregistering crash handler");
+                pr_info("failed unregistering crash handler\n");
         unregister_memory_notifier(&ehea_mem_nb);
         kfree(ehea_fw_handles.arr);
         kfree(ehea_bcmc_regs.arr);
diff --git a/drivers/net/ehea/ehea_phyp.c b/drivers/net/ehea/ehea_phyp.c
index 8fe9dcaa7538..0506967b9044 100644
--- a/drivers/net/ehea/ehea_phyp.c
+++ b/drivers/net/ehea/ehea_phyp.c
@@ -26,6 +26,8 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include "ehea_phyp.h"
 
 
@@ -67,12 +69,11 @@ static long ehea_plpar_hcall_norets(unsigned long opcode,
                 }
 
                 if (ret < H_SUCCESS)
-                        ehea_error("opcode=%lx ret=%lx"
-                                   " arg1=%lx arg2=%lx arg3=%lx arg4=%lx"
-                                   " arg5=%lx arg6=%lx arg7=%lx ",
-                                   opcode, ret,
-                                   arg1, arg2, arg3, arg4, arg5,
-                                   arg6, arg7);
+                        pr_err("opcode=%lx ret=%lx"
+                               " arg1=%lx arg2=%lx arg3=%lx arg4=%lx"
+                               " arg5=%lx arg6=%lx arg7=%lx\n",
+                               opcode, ret,
+                               arg1, arg2, arg3, arg4, arg5, arg6, arg7);
 
                 return ret;
         }
@@ -114,19 +115,18 @@ static long ehea_plpar_hcall9(unsigned long opcode,
                     && (((cb_cat == H_PORT_CB4) && ((arg3 == H_PORT_CB4_JUMBO)
                     || (arg3 == H_PORT_CB4_SPEED))) || ((cb_cat == H_PORT_CB7)
                     && (arg3 == H_PORT_CB7_DUCQPN)))))
-                        ehea_error("opcode=%lx ret=%lx"
-                                   " arg1=%lx arg2=%lx arg3=%lx arg4=%lx"
-                                   " arg5=%lx arg6=%lx arg7=%lx arg8=%lx"
-                                   " arg9=%lx"
-                                   " out1=%lx out2=%lx out3=%lx out4=%lx"
-                                   " out5=%lx out6=%lx out7=%lx out8=%lx"
-                                   " out9=%lx",
-                                   opcode, ret,
-                                   arg1, arg2, arg3, arg4, arg5,
-                                   arg6, arg7, arg8, arg9,
-                                   outs[0], outs[1], outs[2], outs[3],
-                                   outs[4], outs[5], outs[6], outs[7],
-                                   outs[8]);
+                        pr_err("opcode=%lx ret=%lx"
+                               " arg1=%lx arg2=%lx arg3=%lx arg4=%lx"
+                               " arg5=%lx arg6=%lx arg7=%lx arg8=%lx"
+                               " arg9=%lx"
+                               " out1=%lx out2=%lx out3=%lx out4=%lx"
+                               " out5=%lx out6=%lx out7=%lx out8=%lx"
+                               " out9=%lx\n",
+                               opcode, ret,
+                               arg1, arg2, arg3, arg4, arg5,
+                               arg6, arg7, arg8, arg9,
+                               outs[0], outs[1], outs[2], outs[3], outs[4],
+                               outs[5], outs[6], outs[7], outs[8]);
                 return ret;
         }
 
@@ -515,7 +515,7 @@ u64 ehea_h_register_rpage_mr(const u64 adapter_handle, const u64 mr_handle,
                              const u64 log_pageaddr, const u64 count)
 {
         if ((count > 1) && (log_pageaddr & ~PAGE_MASK)) {
-                ehea_error("not on pageboundary");
+                pr_err("not on pageboundary\n");
                 return H_PARAMETER;
         }
 
diff --git a/drivers/net/ehea/ehea_qmr.c b/drivers/net/ehea/ehea_qmr.c
index 89128b6373e3..cd44bb8017d9 100644
--- a/drivers/net/ehea/ehea_qmr.c
+++ b/drivers/net/ehea/ehea_qmr.c
@@ -26,6 +26,8 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/mm.h>
 #include <linux/slab.h>
 #include "ehea.h"
@@ -45,7 +47,7 @@ static void *hw_qpageit_get_inc(struct hw_queue *queue)
                 queue->current_q_offset -= queue->pagesize;
                 retvalue = NULL;
         } else if (((u64) retvalue) & (EHEA_PAGESIZE-1)) {
-                ehea_error("not on pageboundary");
+                pr_err("not on pageboundary\n");
                 retvalue = NULL;
         }
         return retvalue;
@@ -58,15 +60,15 @@ static int hw_queue_ctor(struct hw_queue *queue, const u32 nr_of_pages,
         int i, k;
 
         if ((pagesize > PAGE_SIZE) || (!pages_per_kpage)) {
-                ehea_error("pagesize conflict! kernel pagesize=%d, "
-                           "ehea pagesize=%d", (int)PAGE_SIZE, (int)pagesize);
+                pr_err("pagesize conflict! kernel pagesize=%d, ehea pagesize=%d\n",
+                       (int)PAGE_SIZE, (int)pagesize);
                 return -EINVAL;
         }
 
         queue->queue_length = nr_of_pages * pagesize;
         queue->queue_pages = kmalloc(nr_of_pages * sizeof(void *), GFP_KERNEL);
         if (!queue->queue_pages) {
-                ehea_error("no mem for queue_pages");
+                pr_err("no mem for queue_pages\n");
                 return -ENOMEM;
         }
 
@@ -130,7 +132,7 @@ struct ehea_cq *ehea_create_cq(struct ehea_adapter *adapter,
 
         cq = kzalloc(sizeof(*cq), GFP_KERNEL);
         if (!cq) {
-                ehea_error("no mem for cq");
+                pr_err("no mem for cq\n");
                 goto out_nomem;
         }
 
@@ -147,7 +149,7 @@ struct ehea_cq *ehea_create_cq(struct ehea_adapter *adapter,
         hret = ehea_h_alloc_resource_cq(adapter->handle, &cq->attr,
                                         &cq->fw_handle, &cq->epas);
         if (hret != H_SUCCESS) {
-                ehea_error("alloc_resource_cq failed");
+                pr_err("alloc_resource_cq failed\n");
                 goto out_freemem;
         }
 
@@ -159,7 +161,7 @@ struct ehea_cq *ehea_create_cq(struct ehea_adapter *adapter,
         for (counter = 0; counter < cq->attr.nr_pages; counter++) {
                 vpage = hw_qpageit_get_inc(&cq->hw_queue);
                 if (!vpage) {
-                        ehea_error("hw_qpageit_get_inc failed");
+                        pr_err("hw_qpageit_get_inc failed\n");
                         goto out_kill_hwq;
                 }
 
@@ -168,9 +170,8 @@ struct ehea_cq *ehea_create_cq(struct ehea_adapter *adapter,
                                              0, EHEA_CQ_REGISTER_ORIG,
                                              cq->fw_handle, rpage, 1);
                 if (hret < H_SUCCESS) {
-                        ehea_error("register_rpage_cq failed ehea_cq=%p "
-                                   "hret=%llx counter=%i act_pages=%i",
-                                   cq, hret, counter, cq->attr.nr_pages);
+                        pr_err("register_rpage_cq failed ehea_cq=%p hret=%llx counter=%i act_pages=%i\n",
+                               cq, hret, counter, cq->attr.nr_pages);
                         goto out_kill_hwq;
                 }
 
@@ -178,14 +179,14 @@ struct ehea_cq *ehea_create_cq(struct ehea_adapter *adapter,
                         vpage = hw_qpageit_get_inc(&cq->hw_queue);
 
                         if ((hret != H_SUCCESS) || (vpage)) {
-                                ehea_error("registration of pages not "
-                                           "complete hret=%llx\n", hret);
+                                pr_err("registration of pages not complete hret=%llx\n",
+                                       hret);
                                 goto out_kill_hwq;
                         }
                 } else {
                         if (hret != H_PAGE_REGISTERED) {
-                                ehea_error("CQ: registration of page failed "
-                                           "hret=%llx\n", hret);
+                                pr_err("CQ: registration of page failed hret=%llx\n",
+                                       hret);
                                 goto out_kill_hwq;
                         }
                 }
@@ -241,7 +242,7 @@ int ehea_destroy_cq(struct ehea_cq *cq)
         }
 
         if (hret != H_SUCCESS) {
-                ehea_error("destroy CQ failed");
+                pr_err("destroy CQ failed\n");
                 return -EIO;
         }
 
@@ -259,7 +260,7 @@ struct ehea_eq *ehea_create_eq(struct ehea_adapter *adapter,
 
         eq = kzalloc(sizeof(*eq), GFP_KERNEL);
         if (!eq) {
-                ehea_error("no mem for eq");
+                pr_err("no mem for eq\n");
                 return NULL;
         }
 
@@ -272,21 +273,21 @@ struct ehea_eq *ehea_create_eq(struct ehea_adapter *adapter,
         hret = ehea_h_alloc_resource_eq(adapter->handle,
                                         &eq->attr, &eq->fw_handle);
         if (hret != H_SUCCESS) {
-                ehea_error("alloc_resource_eq failed");
+                pr_err("alloc_resource_eq failed\n");
                 goto out_freemem;
         }
 
         ret = hw_queue_ctor(&eq->hw_queue, eq->attr.nr_pages,
                             EHEA_PAGESIZE, sizeof(struct ehea_eqe));
         if (ret) {
-                ehea_error("can't allocate eq pages");
+                pr_err("can't allocate eq pages\n");
                 goto out_freeres;
         }
 
         for (i = 0; i < eq->attr.nr_pages; i++) {
                 vpage = hw_qpageit_get_inc(&eq->hw_queue);
                 if (!vpage) {
-                        ehea_error("hw_qpageit_get_inc failed");
+                        pr_err("hw_qpageit_get_inc failed\n");
                         hret = H_RESOURCE;
                         goto out_kill_hwq;
                 }
@@ -370,7 +371,7 @@ int ehea_destroy_eq(struct ehea_eq *eq)
         }
 
         if (hret != H_SUCCESS) {
-                ehea_error("destroy EQ failed");
+                pr_err("destroy EQ failed\n");
                 return -EIO;
         }
 
@@ -395,7 +396,7 @@ int ehea_qp_alloc_register(struct ehea_qp *qp, struct hw_queue *hw_queue,
         for (cnt = 0; cnt < nr_pages; cnt++) {
                 vpage = hw_qpageit_get_inc(hw_queue);
                 if (!vpage) {
-                        ehea_error("hw_qpageit_get_inc failed");
+                        pr_err("hw_qpageit_get_inc failed\n");
                         goto out_kill_hwq;
                 }
                 rpage = virt_to_abs(vpage);
@@ -403,7 +404,7 @@ int ehea_qp_alloc_register(struct ehea_qp *qp, struct hw_queue *hw_queue,
                                              0, h_call_q_selector,
                                              qp->fw_handle, rpage, 1);
                 if (hret < H_SUCCESS) {
-                        ehea_error("register_rpage_qp failed");
+                        pr_err("register_rpage_qp failed\n");
                         goto out_kill_hwq;
                 }
         }
@@ -432,7 +433,7 @@ struct ehea_qp *ehea_create_qp(struct ehea_adapter *adapter,
 
         qp = kzalloc(sizeof(*qp), GFP_KERNEL);
         if (!qp) {
-                ehea_error("no mem for qp");
+                pr_err("no mem for qp\n");
                 return NULL;
         }
 
@@ -441,7 +442,7 @@ struct ehea_qp *ehea_create_qp(struct ehea_adapter *adapter,
         hret = ehea_h_alloc_resource_qp(adapter->handle, init_attr, pd,
                                         &qp->fw_handle, &qp->epas);
         if (hret != H_SUCCESS) {
-                ehea_error("ehea_h_alloc_resource_qp failed");
+                pr_err("ehea_h_alloc_resource_qp failed\n");
                 goto out_freemem;
         }
 
@@ -455,7 +456,7 @@ struct ehea_qp *ehea_create_qp(struct ehea_adapter *adapter,
                                      init_attr->act_wqe_size_enc_sq, adapter,
                                      0);
         if (ret) {
-                ehea_error("can't register for sq ret=%x", ret);
+                pr_err("can't register for sq ret=%x\n", ret);
                 goto out_freeres;
         }
 
@@ -465,7 +466,7 @@ struct ehea_qp *ehea_create_qp(struct ehea_adapter *adapter,
                                      init_attr->act_wqe_size_enc_rq1,
                                      adapter, 1);
         if (ret) {
-                ehea_error("can't register for rq1 ret=%x", ret);
+                pr_err("can't register for rq1 ret=%x\n", ret);
                 goto out_kill_hwsq;
         }
 
@@ -476,7 +477,7 @@ struct ehea_qp *ehea_create_qp(struct ehea_adapter *adapter,
                                              init_attr->act_wqe_size_enc_rq2,
                                              adapter, 2);
                 if (ret) {
-                        ehea_error("can't register for rq2 ret=%x", ret);
+                        pr_err("can't register for rq2 ret=%x\n", ret);
                         goto out_kill_hwr1q;
                 }
         }
@@ -488,7 +489,7 @@ struct ehea_qp *ehea_create_qp(struct ehea_adapter *adapter,
                                              init_attr->act_wqe_size_enc_rq3,
                                              adapter, 3);
                 if (ret) {
-                        ehea_error("can't register for rq3 ret=%x", ret);
+                        pr_err("can't register for rq3 ret=%x\n", ret);
                         goto out_kill_hwr2q;
                 }
         }
@@ -553,7 +554,7 @@ int ehea_destroy_qp(struct ehea_qp *qp)
         }
 
         if (hret != H_SUCCESS) {
-                ehea_error("destroy QP failed");
+                pr_err("destroy QP failed\n");
                 return -EIO;
         }
 
@@ -842,7 +843,7 @@ static u64 ehea_reg_mr_section(int top, int dir, int idx, u64 *pt,
                     (hret != H_PAGE_REGISTERED)) {
                         ehea_h_free_resource(adapter->handle, mr->handle,
                                              FORCE_FREE);
-                        ehea_error("register_rpage_mr failed");
+                        pr_err("register_rpage_mr failed\n");
                         return hret;
                 }
         }
@@ -896,7 +897,7 @@ int ehea_reg_kernel_mr(struct ehea_adapter *adapter, struct ehea_mr *mr)
 
         pt = (void *)get_zeroed_page(GFP_KERNEL);
         if (!pt) {
-                ehea_error("no mem");
+                pr_err("no mem\n");
                 ret = -ENOMEM;
                 goto out;
         }
@@ -906,14 +907,14 @@ int ehea_reg_kernel_mr(struct ehea_adapter *adapter, struct ehea_mr *mr)
                                         &mr->handle, &mr->lkey);
 
         if (hret != H_SUCCESS) {
-                ehea_error("alloc_resource_mr failed");
+                pr_err("alloc_resource_mr failed\n");
                 ret = -EIO;
                 goto out;
         }
 
         if (!ehea_bmap) {
                 ehea_h_free_resource(adapter->handle, mr->handle, FORCE_FREE);
-                ehea_error("no busmap available");
+                pr_err("no busmap available\n");
                 ret = -EIO;
                 goto out;
         }
@@ -929,7 +930,7 @@ int ehea_reg_kernel_mr(struct ehea_adapter *adapter, struct ehea_mr *mr)
 
         if (hret != H_SUCCESS) {
                 ehea_h_free_resource(adapter->handle, mr->handle, FORCE_FREE);
-                ehea_error("registering mr failed");
+                pr_err("registering mr failed\n");
                 ret = -EIO;
                 goto out;
         }
@@ -952,7 +953,7 @@ int ehea_rem_mr(struct ehea_mr *mr)
         hret = ehea_h_free_resource(mr->adapter->handle, mr->handle,
                                     FORCE_FREE);
         if (hret != H_SUCCESS) {
-                ehea_error("destroy MR failed");
+                pr_err("destroy MR failed\n");
                 return -EIO;
         }
 
@@ -987,14 +988,14 @@ void print_error_data(u64 *data)
                 length = EHEA_PAGESIZE;
 
         if (type == EHEA_AER_RESTYPE_QP)
-                ehea_error("QP (resource=%llX) state: AER=0x%llX, AERR=0x%llX, "
-                           "port=%llX", resource, data[6], data[12], data[22]);
+                pr_err("QP (resource=%llX) state: AER=0x%llX, AERR=0x%llX, port=%llX\n",
+                       resource, data[6], data[12], data[22]);
         else if (type == EHEA_AER_RESTYPE_CQ)
-                ehea_error("CQ (resource=%llX) state: AER=0x%llX", resource,
-                           data[6]);
+                pr_err("CQ (resource=%llX) state: AER=0x%llX\n",
+                       resource, data[6]);
         else if (type == EHEA_AER_RESTYPE_EQ)
-                ehea_error("EQ (resource=%llX) state: AER=0x%llX", resource,
-                           data[6]);
+                pr_err("EQ (resource=%llX) state: AER=0x%llX\n",
+                       resource, data[6]);
 
         ehea_dump(data, length, "error data");
 }
@@ -1008,7 +1009,7 @@ u64 ehea_error_data(struct ehea_adapter *adapter, u64 res_handle,
 
         rblock = (void *)get_zeroed_page(GFP_KERNEL);
         if (!rblock) {
-                ehea_error("Cannot allocate rblock memory.");
+                pr_err("Cannot allocate rblock memory\n");
                 goto out;
         }
 
@@ -1020,9 +1021,9 @@ u64 ehea_error_data(struct ehea_adapter *adapter, u64 res_handle,
                 *aerr = rblock[12];
                 print_error_data(rblock);
         } else if (ret == H_R_STATE) {
-                ehea_error("No error data available: %llX.", res_handle);
+                pr_err("No error data available: %llX\n", res_handle);
         } else
-                ehea_error("Error data could not be fetched: %llX", res_handle);
+                pr_err("Error data could not be fetched: %llX\n", res_handle);
 
         free_page((unsigned long)rblock);
 out:
diff --git a/drivers/net/enic/enic.h b/drivers/net/enic/enic.h
index c91d364c5527..a937f49d9db7 100644
--- a/drivers/net/enic/enic.h
+++ b/drivers/net/enic/enic.h
@@ -32,7 +32,7 @@
 
 #define DRV_NAME                "enic"
 #define DRV_DESCRIPTION         "Cisco VIC Ethernet NIC Driver"
-#define DRV_VERSION             "1.4.1.6"
+#define DRV_VERSION             "1.4.1.10"
 #define DRV_COPYRIGHT           "Copyright 2008-2010 Cisco Systems, Inc"
 
 #define ENIC_BARS_MAX           6
@@ -61,6 +61,8 @@ struct enic_port_profile {
         char name[PORT_PROFILE_MAX];
         u8 instance_uuid[PORT_UUID_MAX];
         u8 host_uuid[PORT_UUID_MAX];
+        u8 vf_mac[ETH_ALEN];
+        u8 mac_addr[ETH_ALEN];
 };
 
 /* Per-instance private data structure */
@@ -78,8 +80,10 @@ struct enic {
         spinlock_t devcmd_lock;
         u8 mac_addr[ETH_ALEN];
         u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
+        u8 uc_addr[ENIC_UNICAST_PERFECT_FILTERS][ETH_ALEN];
         unsigned int flags;
         unsigned int mc_count;
+        unsigned int uc_count;
         int csum_rx_enabled;
         u32 port_mtu;
         u32 rx_coalesce_usecs;
diff --git a/drivers/net/enic/enic_main.c b/drivers/net/enic/enic_main.c
index aa28b270c045..a0af48c51fb3 100644
--- a/drivers/net/enic/enic_main.c
+++ b/drivers/net/enic/enic_main.c
@@ -702,7 +702,7 @@ static inline void enic_queue_wq_skb_csum_l4(struct enic *enic,
 {
         unsigned int head_len = skb_headlen(skb);
         unsigned int len_left = skb->len - head_len;
-        unsigned int hdr_len = skb_transport_offset(skb);
+        unsigned int hdr_len = skb_checksum_start_offset(skb);
         unsigned int csum_offset = hdr_len + skb->csum_offset;
         int eop = (len_left == 0);
 
@@ -1002,7 +1002,7 @@ static int enic_dev_packet_filter(struct enic *enic, int directed,
         return err;
 }
 
-static int enic_dev_add_multicast_addr(struct enic *enic, u8 *addr)
+static int enic_dev_add_addr(struct enic *enic, u8 *addr)
 {
         int err;
 
@@ -1013,7 +1013,7 @@ static int enic_dev_add_multicast_addr(struct enic *enic, u8 *addr)
         return err;
 }
 
-static int enic_dev_del_multicast_addr(struct enic *enic, u8 *addr)
+static int enic_dev_del_addr(struct enic *enic, u8 *addr)
 {
         int err;
 
@@ -1024,29 +1024,19 @@ static int enic_dev_del_multicast_addr(struct enic *enic, u8 *addr)
         return err;
 }
 
-/* netif_tx_lock held, BHs disabled */
-static void enic_set_multicast_list(struct net_device *netdev)
+static void enic_add_multicast_addr_list(struct enic *enic)
 {
-        struct enic *enic = netdev_priv(netdev);
+        struct net_device *netdev = enic->netdev;
         struct netdev_hw_addr *ha;
-        int directed = 1;
-        int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
-        int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
-        int promisc = (netdev->flags & IFF_PROMISC) ? 1 : 0;
         unsigned int mc_count = netdev_mc_count(netdev);
-        int allmulti = (netdev->flags & IFF_ALLMULTI) ||
-                mc_count > ENIC_MULTICAST_PERFECT_FILTERS;
-        unsigned int flags = netdev->flags | (allmulti ? IFF_ALLMULTI : 0);
         u8 mc_addr[ENIC_MULTICAST_PERFECT_FILTERS][ETH_ALEN];
         unsigned int i, j;
 
-        if (mc_count > ENIC_MULTICAST_PERFECT_FILTERS)
+        if (mc_count > ENIC_MULTICAST_PERFECT_FILTERS) {
+                netdev_warn(netdev, "Registering only %d out of %d "
+                        "multicast addresses\n",
+                        ENIC_MULTICAST_PERFECT_FILTERS, mc_count);
                 mc_count = ENIC_MULTICAST_PERFECT_FILTERS;
-
-        if (enic->flags != flags) {
-                enic->flags = flags;
-                enic_dev_packet_filter(enic, directed,
-                        multicast, broadcast, promisc, allmulti);
         }
 
         /* Is there an easier way?  Trying to minimize to
@@ -1068,7 +1058,7 @@ static void enic_set_multicast_list(struct net_device *netdev)
                                 mc_addr[j]) == 0)
                                 break;
                 if (j == mc_count)
-                        enic_dev_del_multicast_addr(enic, enic->mc_addr[i]);
+                        enic_dev_del_addr(enic, enic->mc_addr[i]);
         }
 
         for (i = 0; i < mc_count; i++) {
@@ -1077,7 +1067,7 @@ static void enic_set_multicast_list(struct net_device *netdev)
                                 enic->mc_addr[j]) == 0)
                                 break;
                 if (j == enic->mc_count)
-                        enic_dev_add_multicast_addr(enic, mc_addr[i]);
+                        enic_dev_add_addr(enic, mc_addr[i]);
         }
 
         /* Save the list to compare against next time
@@ -1089,6 +1079,89 @@ static void enic_set_multicast_list(struct net_device *netdev)
         enic->mc_count = mc_count;
 }
 
+static void enic_add_unicast_addr_list(struct enic *enic)
+{
+        struct net_device *netdev = enic->netdev;
+        struct netdev_hw_addr *ha;
+        unsigned int uc_count = netdev_uc_count(netdev);
+        u8 uc_addr[ENIC_UNICAST_PERFECT_FILTERS][ETH_ALEN];
+        unsigned int i, j;
+
+        if (uc_count > ENIC_UNICAST_PERFECT_FILTERS) {
+                netdev_warn(netdev, "Registering only %d out of %d "
+                        "unicast addresses\n",
+                        ENIC_UNICAST_PERFECT_FILTERS, uc_count);
+                uc_count = ENIC_UNICAST_PERFECT_FILTERS;
+        }
+
+        /* Is there an easier way?  Trying to minimize to
+         * calls to add/del unicast addrs.  We keep the
+         * addrs from the last call in enic->uc_addr and
+         * look for changes to add/del.
+         */
+
+        i = 0;
+        netdev_for_each_uc_addr(ha, netdev) {
+                if (i == uc_count)
+                        break;
+                memcpy(uc_addr[i++], ha->addr, ETH_ALEN);
+        }
+
+        for (i = 0; i < enic->uc_count; i++) {
+                for (j = 0; j < uc_count; j++)
+                        if (compare_ether_addr(enic->uc_addr[i],
+                                uc_addr[j]) == 0)
+                                break;
+                if (j == uc_count)
+                        enic_dev_del_addr(enic, enic->uc_addr[i]);
+        }
+
+        for (i = 0; i < uc_count; i++) {
+                for (j = 0; j < enic->uc_count; j++)
+                        if (compare_ether_addr(uc_addr[i],
+                                enic->uc_addr[j]) == 0)
+                                break;
+                if (j == enic->uc_count)
+                        enic_dev_add_addr(enic, uc_addr[i]);
+        }
+
+        /* Save the list to compare against next time
+         */
+
+        for (i = 0; i < uc_count; i++)
+                memcpy(enic->uc_addr[i], uc_addr[i], ETH_ALEN);
+
+        enic->uc_count = uc_count;
+}
+
+/* netif_tx_lock held, BHs disabled */
+static void enic_set_rx_mode(struct net_device *netdev)
+{
+        struct enic *enic = netdev_priv(netdev);
+        int directed = 1;
+        int multicast = (netdev->flags & IFF_MULTICAST) ? 1 : 0;
+        int broadcast = (netdev->flags & IFF_BROADCAST) ? 1 : 0;
+        int promisc = (netdev->flags & IFF_PROMISC) ||
+                netdev_uc_count(netdev) > ENIC_UNICAST_PERFECT_FILTERS;
+        int allmulti = (netdev->flags & IFF_ALLMULTI) ||
+                netdev_mc_count(netdev) > ENIC_MULTICAST_PERFECT_FILTERS;
+        unsigned int flags = netdev->flags |
+                (allmulti ? IFF_ALLMULTI : 0) |
+                (promisc ? IFF_PROMISC : 0);
+
+        if (enic->flags != flags) {
+                enic->flags = flags;
+                enic_dev_packet_filter(enic, directed,
+                        multicast, broadcast, promisc, allmulti);
+        }
+
+        if (!promisc) {
+                enic_add_unicast_addr_list(enic);
+                if (!allmulti)
+                        enic_add_multicast_addr_list(enic);
+        }
+}
+
 /* rtnl lock is held */
 static void enic_vlan_rx_register(struct net_device *netdev,
         struct vlan_group *vlan_group)
@@ -1158,11 +1231,31 @@ static int enic_dev_init_done(struct enic *enic, int *done, int *error)
         return err;
 }
 
+static int enic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
+{
+        struct enic *enic = netdev_priv(netdev);
+
+        if (vf != PORT_SELF_VF)
+                return -EOPNOTSUPP;
+
+        /* Ignore the vf argument for now. We can assume the request
+         * is coming on a vf.
+         */
+        if (is_valid_ether_addr(mac)) {
+                memcpy(enic->pp.vf_mac, mac, ETH_ALEN);
+                return 0;
+        } else
+                return -EINVAL;
+}
+
 static int enic_set_port_profile(struct enic *enic, u8 *mac)
 {
         struct vic_provinfo *vp;
         u8 oui[3] = VIC_PROVINFO_CISCO_OUI;
+        u16 os_type = VIC_GENERIC_PROV_OS_TYPE_LINUX;
         char uuid_str[38];
+        char client_mac_str[18];
+        u8 *client_mac;
         int err;
 
         err = enic_vnic_dev_deinit(enic);
@@ -1180,46 +1273,63 @@ static int enic_set_port_profile(struct enic *enic, u8 *mac)
                         return -EADDRNOTAVAIL;
 
                 vp = vic_provinfo_alloc(GFP_KERNEL, oui,
-                        VIC_PROVINFO_LINUX_TYPE);
+                        VIC_PROVINFO_GENERIC_TYPE);
                 if (!vp)
                         return -ENOMEM;
 
                 vic_provinfo_add_tlv(vp,
-                        VIC_LINUX_PROV_TLV_PORT_PROFILE_NAME_STR,
+                        VIC_GENERIC_PROV_TLV_PORT_PROFILE_NAME_STR,
                         strlen(enic->pp.name) + 1, enic->pp.name);
 
+                if (!is_zero_ether_addr(enic->pp.mac_addr))
+                        client_mac = enic->pp.mac_addr;
+                else
+                        client_mac = mac;
+
+                vic_provinfo_add_tlv(vp,
+                        VIC_GENERIC_PROV_TLV_CLIENT_MAC_ADDR,
+                        ETH_ALEN, client_mac);
+
+                sprintf(client_mac_str, "%pM", client_mac);
                 vic_provinfo_add_tlv(vp,
-                        VIC_LINUX_PROV_TLV_CLIENT_MAC_ADDR,
-                        ETH_ALEN, mac);
+                        VIC_GENERIC_PROV_TLV_CLUSTER_PORT_UUID_STR,
+                        sizeof(client_mac_str), client_mac_str);
 
                 if (enic->pp.set & ENIC_SET_INSTANCE) {
                         sprintf(uuid_str, "%pUB", enic->pp.instance_uuid);
                         vic_provinfo_add_tlv(vp,
-                                VIC_LINUX_PROV_TLV_CLIENT_UUID_STR,
+                                VIC_GENERIC_PROV_TLV_CLIENT_UUID_STR,
                                 sizeof(uuid_str), uuid_str);
                 }
 
                 if (enic->pp.set & ENIC_SET_HOST) {
                         sprintf(uuid_str, "%pUB", enic->pp.host_uuid);
                         vic_provinfo_add_tlv(vp,
-                                VIC_LINUX_PROV_TLV_HOST_UUID_STR,
+                                VIC_GENERIC_PROV_TLV_HOST_UUID_STR,
                                 sizeof(uuid_str), uuid_str);
                 }
 
+                os_type = htons(os_type);
+                vic_provinfo_add_tlv(vp,
+                        VIC_GENERIC_PROV_TLV_OS_TYPE,
+                        sizeof(os_type), &os_type);
+
                 err = enic_dev_init_prov(enic, vp);
                 vic_provinfo_free(vp);
                 if (err)
                         return err;
+
+                enic->pp.set |= ENIC_SET_APPLIED;
                 break;
 
         case PORT_REQUEST_DISASSOCIATE:
+                enic->pp.set &= ~ENIC_SET_APPLIED;
                 break;
 
         default:
                 return -EINVAL;
         }
 
-        enic->pp.set |= ENIC_SET_APPLIED;
         return 0;
 }
 
@@ -1227,29 +1337,31 @@ static int enic_set_vf_port(struct net_device *netdev, int vf,
         struct nlattr *port[])
 {
         struct enic *enic = netdev_priv(netdev);
+        struct enic_port_profile new_pp;
+        int err = 0;
 
-        memset(&enic->pp, 0, sizeof(enic->pp));
+        memset(&new_pp, 0, sizeof(new_pp));
 
         if (port[IFLA_PORT_REQUEST]) {
-                enic->pp.set |= ENIC_SET_REQUEST;
-                enic->pp.request = nla_get_u8(port[IFLA_PORT_REQUEST]);
+                new_pp.set |= ENIC_SET_REQUEST;
+                new_pp.request = nla_get_u8(port[IFLA_PORT_REQUEST]);
         }
 
         if (port[IFLA_PORT_PROFILE]) {
-                enic->pp.set |= ENIC_SET_NAME;
-                memcpy(enic->pp.name, nla_data(port[IFLA_PORT_PROFILE]),
+                new_pp.set |= ENIC_SET_NAME;
+                memcpy(new_pp.name, nla_data(port[IFLA_PORT_PROFILE]),
                         PORT_PROFILE_MAX);
         }
 
         if (port[IFLA_PORT_INSTANCE_UUID]) {
-                enic->pp.set |= ENIC_SET_INSTANCE;
-                memcpy(enic->pp.instance_uuid,
+                new_pp.set |= ENIC_SET_INSTANCE;
+                memcpy(new_pp.instance_uuid,
                         nla_data(port[IFLA_PORT_INSTANCE_UUID]), PORT_UUID_MAX);
         }
 
         if (port[IFLA_PORT_HOST_UUID]) {
-                enic->pp.set |= ENIC_SET_HOST;
-                memcpy(enic->pp.host_uuid,
+                new_pp.set |= ENIC_SET_HOST;
+                memcpy(new_pp.host_uuid,
                         nla_data(port[IFLA_PORT_HOST_UUID]), PORT_UUID_MAX);
         }
 
@@ -1257,21 +1369,39 @@ static int enic_set_vf_port(struct net_device *netdev, int vf,
         if (vf != PORT_SELF_VF)
                 return -EOPNOTSUPP;
 
-        if (!(enic->pp.set & ENIC_SET_REQUEST))
+        if (!(new_pp.set & ENIC_SET_REQUEST))
                 return -EOPNOTSUPP;
 
-        if (enic->pp.request == PORT_REQUEST_ASSOCIATE) {
-
-                /* If the interface mac addr hasn't been assigned,
-                 * assign a random mac addr before setting port-
-                 * profile.
-                 */
+        if (new_pp.request == PORT_REQUEST_ASSOCIATE) {
+                /* Special case handling */
+                if (!is_zero_ether_addr(enic->pp.vf_mac))
+                        memcpy(new_pp.mac_addr, enic->pp.vf_mac, ETH_ALEN);
 
                 if (is_zero_ether_addr(netdev->dev_addr))
                         random_ether_addr(netdev->dev_addr);
+        } else if (new_pp.request == PORT_REQUEST_DISASSOCIATE) {
+                if (!is_zero_ether_addr(enic->pp.mac_addr))
+                        enic_dev_del_addr(enic, enic->pp.mac_addr);
         }
 
-        return enic_set_port_profile(enic, netdev->dev_addr);
+        memcpy(&enic->pp, &new_pp, sizeof(struct enic_port_profile));
+
+        err = enic_set_port_profile(enic, netdev->dev_addr);
+        if (err)
+                goto set_port_profile_cleanup;
+
+        if (!is_zero_ether_addr(enic->pp.mac_addr))
+                enic_dev_add_addr(enic, enic->pp.mac_addr);
+
+set_port_profile_cleanup:
+        memset(enic->pp.vf_mac, 0, ETH_ALEN);
+
+        if (err || enic->pp.request == PORT_REQUEST_DISASSOCIATE) {
+                memset(netdev->dev_addr, 0, ETH_ALEN);
+                memset(enic->pp.mac_addr, 0, ETH_ALEN);
+        }
+
+        return err;
 }
 
 static int enic_get_vf_port(struct net_device *netdev, int vf,
@@ -1851,8 +1981,11 @@ static int enic_open(struct net_device *netdev)
         for (i = 0; i < enic->rq_count; i++)
                 vnic_rq_enable(&enic->rq[i]);
 
-        enic_dev_add_station_addr(enic);
-        enic_set_multicast_list(netdev);
+        if (enic_is_dynamic(enic) && !is_zero_ether_addr(enic->pp.mac_addr))
+                enic_dev_add_addr(enic, enic->pp.mac_addr);
+        else
+                enic_dev_add_station_addr(enic);
+        enic_set_rx_mode(netdev);
 
         netif_wake_queue(netdev);
 
@@ -1899,7 +2032,10 @@ static int enic_stop(struct net_device *netdev)
 
         netif_carrier_off(netdev);
         netif_tx_disable(netdev);
-        enic_dev_del_station_addr(enic);
+        if (enic_is_dynamic(enic) && !is_zero_ether_addr(enic->pp.mac_addr))
+                enic_dev_del_addr(enic, enic->pp.mac_addr);
+        else
+                enic_dev_del_station_addr(enic);
 
         for (i = 0; i < enic->wq_count; i++) {
                 err = vnic_wq_disable(&enic->wq[i]);
@@ -2043,7 +2179,7 @@ static int enic_dev_hang_reset(struct enic *enic)
 
 static int enic_set_rsskey(struct enic *enic)
 {
-        u64 rss_key_buf_pa;
+        dma_addr_t rss_key_buf_pa;
         union vnic_rss_key *rss_key_buf_va = NULL;
         union vnic_rss_key rss_key = {
                 .key[0].b = {85, 67, 83, 97, 119, 101, 115, 111, 109, 101},
@@ -2074,7 +2210,7 @@ static int enic_set_rsskey(struct enic *enic)
 
 static int enic_set_rsscpu(struct enic *enic, u8 rss_hash_bits)
 {
-        u64 rss_cpu_buf_pa;
+        dma_addr_t rss_cpu_buf_pa;
         union vnic_rss_cpu *rss_cpu_buf_va = NULL;
         unsigned int i;
         int err;
@@ -2329,7 +2465,8 @@ static const struct net_device_ops enic_netdev_dynamic_ops = {
         .ndo_start_xmit         = enic_hard_start_xmit,
         .ndo_get_stats          = enic_get_stats,
         .ndo_validate_addr      = eth_validate_addr,
-        .ndo_set_multicast_list = enic_set_multicast_list,
+        .ndo_set_rx_mode        = enic_set_rx_mode,
+        .ndo_set_multicast_list = enic_set_rx_mode,
         .ndo_set_mac_address    = enic_set_mac_address_dynamic,
         .ndo_change_mtu         = enic_change_mtu,
         .ndo_vlan_rx_register   = enic_vlan_rx_register,
@@ -2338,6 +2475,9 @@ static const struct net_device_ops enic_netdev_dynamic_ops = {
         .ndo_tx_timeout         = enic_tx_timeout,
         .ndo_set_vf_port        = enic_set_vf_port,
         .ndo_get_vf_port        = enic_get_vf_port,
+#ifdef IFLA_VF_MAX
+        .ndo_set_vf_mac         = enic_set_vf_mac,
+#endif
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller    = enic_poll_controller,
 #endif
@@ -2350,7 +2490,8 @@ static const struct net_device_ops enic_netdev_ops = {
         .ndo_get_stats          = enic_get_stats,
         .ndo_validate_addr      = eth_validate_addr,
         .ndo_set_mac_address    = enic_set_mac_address,
-        .ndo_set_multicast_list = enic_set_multicast_list,
+        .ndo_set_rx_mode        = enic_set_rx_mode,
+        .ndo_set_multicast_list = enic_set_rx_mode,
         .ndo_change_mtu         = enic_change_mtu,
         .ndo_vlan_rx_register   = enic_vlan_rx_register,
         .ndo_vlan_rx_add_vid    = enic_vlan_rx_add_vid,
@@ -2694,7 +2835,7 @@ static void __devexit enic_remove(struct pci_dev *pdev)
         if (netdev) {
                 struct enic *enic = netdev_priv(netdev);
 
-                flush_scheduled_work();
+                cancel_work_sync(&enic->reset);
                 unregister_netdev(netdev);
                 enic_dev_deinit(enic);
                 vnic_dev_close(enic->vdev);
diff --git a/drivers/net/enic/enic_res.h b/drivers/net/enic/enic_res.h
index 9a103d9ef9e2..25be2734c3fe 100644
--- a/drivers/net/enic/enic_res.h
+++ b/drivers/net/enic/enic_res.h
@@ -34,6 +34,7 @@
 #define ENIC_MAX_MTU                    9000
 
 #define ENIC_MULTICAST_PERFECT_FILTERS  32
+#define ENIC_UNICAST_PERFECT_FILTERS    32
 
 #define ENIC_NON_TSO_MAX_DESC           16
 
diff --git a/drivers/net/enic/vnic_vic.h b/drivers/net/enic/vnic_vic.h
index 7e46e5e8600f..f700f5d9e81d 100644
--- a/drivers/net/enic/vnic_vic.h
+++ b/drivers/net/enic/vnic_vic.h
@@ -24,14 +24,29 @@
 /* Note: String field lengths include null char */
 
 #define VIC_PROVINFO_CISCO_OUI          { 0x00, 0x00, 0x0c }
-#define VIC_PROVINFO_LINUX_TYPE         0x2
-
-enum vic_linux_prov_tlv_type {
-        VIC_LINUX_PROV_TLV_PORT_PROFILE_NAME_STR = 0,
-        VIC_LINUX_PROV_TLV_CLIENT_MAC_ADDR = 1,                 /* u8[6] */
-        VIC_LINUX_PROV_TLV_CLIENT_NAME_STR = 2,
-        VIC_LINUX_PROV_TLV_HOST_UUID_STR = 8,
-        VIC_LINUX_PROV_TLV_CLIENT_UUID_STR = 9,
+#define VIC_PROVINFO_GENERIC_TYPE               0x4
+
+enum vic_generic_prov_tlv_type {
+        VIC_GENERIC_PROV_TLV_PORT_PROFILE_NAME_STR = 0,
+        VIC_GENERIC_PROV_TLV_CLIENT_MAC_ADDR = 1,
+        VIC_GENERIC_PROV_TLV_CLIENT_NAME_STR = 2,
+        VIC_GENERIC_PROV_TLV_CLUSTER_PORT_NAME_STR = 3,
+        VIC_GENERIC_PROV_TLV_CLUSTER_PORT_UUID_STR = 4,
+        VIC_GENERIC_PROV_TLV_CLUSTER_UUID_STR = 5,
+        VIC_GENERIC_PROV_TLV_CLUSTER_NAME_STR = 7,
+        VIC_GENERIC_PROV_TLV_HOST_UUID_STR = 8,
+        VIC_GENERIC_PROV_TLV_CLIENT_UUID_STR = 9,
+        VIC_GENERIC_PROV_TLV_INCARNATION_NUMBER = 10,
+        VIC_GENERIC_PROV_TLV_OS_TYPE = 11,
+        VIC_GENERIC_PROV_TLV_OS_VENDOR = 12,
+        VIC_GENERIC_PROV_TLV_CLIENT_TYPE = 15,
+};
+
+enum vic_generic_prov_os_type {
+        VIC_GENERIC_PROV_OS_TYPE_UNKNOWN = 0,
+        VIC_GENERIC_PROV_OS_TYPE_ESX = 1,
+        VIC_GENERIC_PROV_OS_TYPE_LINUX = 2,
+        VIC_GENERIC_PROV_OS_TYPE_WINDOWS = 3,
 };
 
 struct vic_provinfo {
diff --git a/drivers/net/epic100.c b/drivers/net/epic100.c
index aa56963ad558..c353bf3113cc 100644
--- a/drivers/net/epic100.c
+++ b/drivers/net/epic100.c
@@ -935,7 +935,7 @@ static void epic_init_ring(struct net_device *dev)
 
         /* Fill in the Rx buffers.  Handle allocation failure gracefully. */
         for (i = 0; i < RX_RING_SIZE; i++) {
-                struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz);
+                struct sk_buff *skb = dev_alloc_skb(ep->rx_buf_sz + 2);
                 ep->rx_skbuff[i] = skb;
                 if (skb == NULL)
                         break;
@@ -1233,7 +1233,7 @@ static int epic_rx(struct net_device *dev, int budget)
                 entry = ep->dirty_rx % RX_RING_SIZE;
                 if (ep->rx_skbuff[entry] == NULL) {
                         struct sk_buff *skb;
-                        skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz);
+                        skb = ep->rx_skbuff[entry] = dev_alloc_skb(ep->rx_buf_sz + 2);
                         if (skb == NULL)
                                 break;
                         skb_reserve(skb, 2);    /* Align IP on 16 byte boundaries */
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index c5a2fe099a8d..b79d7e1555d5 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -19,6 +19,7 @@
 #include <linux/platform_device.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
+#include <linux/of.h>
 #include <net/ethoc.h>
 
 static int buffer_size = 0x8000; /* 32 KBytes */
@@ -184,7 +185,6 @@ MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
  * @netdev:     pointer to network device structure
  * @napi:       NAPI structure
  * @msg_enable: device state flags
- * @rx_lock:    receive lock
  * @lock:       device lock
  * @phy:        attached PHY
  * @mdio:       MDIO bus for PHY access
@@ -209,7 +209,6 @@ struct ethoc {
         struct napi_struct napi;
         u32 msg_enable;
 
-        spinlock_t rx_lock;
         spinlock_t lock;
 
         struct phy_device *phy;
@@ -413,10 +412,21 @@ static int ethoc_rx(struct net_device *dev, int limit)
                 unsigned int entry;
                 struct ethoc_bd bd;
 
-                entry = priv->num_tx + (priv->cur_rx % priv->num_rx);
+                entry = priv->num_tx + priv->cur_rx;
                 ethoc_read_bd(priv, entry, &bd);
-                if (bd.stat & RX_BD_EMPTY)
-                        break;
+                if (bd.stat & RX_BD_EMPTY) {
+                        ethoc_ack_irq(priv, INT_MASK_RX);
+                        /* If packet (interrupt) came in between checking
+                         * BD_EMTPY and clearing the interrupt source, then we
+                         * risk missing the packet as the RX interrupt won't
+                         * trigger right away when we reenable it; hence, check
+                         * BD_EMTPY here again to make sure there isn't such a
+                         * packet waiting for us...
+                         */
+                        ethoc_read_bd(priv, entry, &bd);
+                        if (bd.stat & RX_BD_EMPTY)
+                                break;
+                }
 
                 if (ethoc_update_rx_stats(priv, &bd) == 0) {
                         int size = bd.stat >> 16;
@@ -446,13 +456,14 @@ static int ethoc_rx(struct net_device *dev, int limit)
                 bd.stat &= ~RX_BD_STATS;
                 bd.stat |=  RX_BD_EMPTY;
                 ethoc_write_bd(priv, entry, &bd);
-                priv->cur_rx++;
+                if (++priv->cur_rx == priv->num_rx)
+                        priv->cur_rx = 0;
         }
 
         return count;
 }
 
-static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
+static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
 {
         struct net_device *netdev = dev->netdev;
 
@@ -482,32 +493,44 @@ static int ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
         netdev->stats.collisions += (bd->stat >> 4) & 0xf;
         netdev->stats.tx_bytes += bd->stat >> 16;
         netdev->stats.tx_packets++;
-        return 0;
 }
 
-static void ethoc_tx(struct net_device *dev)
+static int ethoc_tx(struct net_device *dev, int limit)
 {
         struct ethoc *priv = netdev_priv(dev);
+        int count;
+        struct ethoc_bd bd;
 
-        spin_lock(&priv->lock);
+        for (count = 0; count < limit; ++count) {
+                unsigned int entry;
 
-        while (priv->dty_tx != priv->cur_tx) {
-                unsigned int entry = priv->dty_tx % priv->num_tx;
-                struct ethoc_bd bd;
+                entry = priv->dty_tx & (priv->num_tx-1);
 
                 ethoc_read_bd(priv, entry, &bd);
-                if (bd.stat & TX_BD_READY)
-                        break;
 
-                entry = (++priv->dty_tx) % priv->num_tx;
-                (void)ethoc_update_tx_stats(priv, &bd);
+                if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
+                        ethoc_ack_irq(priv, INT_MASK_TX);
+                        /* If interrupt came in between reading in the BD
+                         * and clearing the interrupt source, then we risk
+                         * missing the event as the TX interrupt won't trigger
+                         * right away when we reenable it; hence, check
+                         * BD_EMPTY here again to make sure there isn't such an
+                         * event pending...
+                         */
+                        ethoc_read_bd(priv, entry, &bd);
+                        if (bd.stat & TX_BD_READY ||
+                            (priv->dty_tx == priv->cur_tx))
+                                break;
+                }
+
+                ethoc_update_tx_stats(priv, &bd);
+                priv->dty_tx++;
         }
 
         if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
                 netif_wake_queue(dev);
 
-        ethoc_ack_irq(priv, INT_MASK_TX);
-        spin_unlock(&priv->lock);
+        return count;
 }
 
 static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
@@ -515,32 +538,38 @@ static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
         struct net_device *dev = dev_id;
         struct ethoc *priv = netdev_priv(dev);
         u32 pending;
-
-        ethoc_disable_irq(priv, INT_MASK_ALL);
+        u32 mask;
+
+        /* Figure out what triggered the interrupt...
+         * The tricky bit here is that the interrupt source bits get
+         * set in INT_SOURCE for an event irregardless of whether that
+         * event is masked or not.  Thus, in order to figure out what
+         * triggered the interrupt, we need to remove the sources
+         * for all events that are currently masked.  This behaviour
+         * is not particularly well documented but reasonable...
+         */
+        mask = ethoc_read(priv, INT_MASK);
         pending = ethoc_read(priv, INT_SOURCE);
+        pending &= mask;
+
         if (unlikely(pending == 0)) {
-                ethoc_enable_irq(priv, INT_MASK_ALL);
                 return IRQ_NONE;
         }
 
         ethoc_ack_irq(priv, pending);
 
+        /* We always handle the dropped packet interrupt */
         if (pending & INT_MASK_BUSY) {
                 dev_err(&dev->dev, "packet dropped\n");
                 dev->stats.rx_dropped++;
         }
 
-        if (pending & INT_MASK_RX) {
-                if (napi_schedule_prep(&priv->napi))
-                        __napi_schedule(&priv->napi);
-        } else {
-                ethoc_enable_irq(priv, INT_MASK_RX);
+        /* Handle receive/transmit event by switching to polling */
+        if (pending & (INT_MASK_TX | INT_MASK_RX)) {
+                ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
+                napi_schedule(&priv->napi);
         }
 
-        if (pending & INT_MASK_TX)
-                ethoc_tx(dev);
-
-        ethoc_enable_irq(priv, INT_MASK_ALL & ~INT_MASK_RX);
         return IRQ_HANDLED;
 }
 
@@ -566,26 +595,29 @@ static int ethoc_get_mac_address(struct net_device *dev, void *addr)
 static int ethoc_poll(struct napi_struct *napi, int budget)
 {
         struct ethoc *priv = container_of(napi, struct ethoc, napi);
-        int work_done = 0;
+        int rx_work_done = 0;
+        int tx_work_done = 0;
+
+        rx_work_done = ethoc_rx(priv->netdev, budget);
+        tx_work_done = ethoc_tx(priv->netdev, budget);
 
-        work_done = ethoc_rx(priv->netdev, budget);
-        if (work_done < budget) {
-                ethoc_enable_irq(priv, INT_MASK_RX);
+        if (rx_work_done < budget && tx_work_done < budget) {
                 napi_complete(napi);
+                ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
         }
 
-        return work_done;
+        return rx_work_done;
 }
 
 static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
 {
-        unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
         struct ethoc *priv = bus->priv;
+        int i;
 
         ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
         ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
 
-        while (time_before(jiffies, timeout)) {
+        for (i=0; i < 5; i++) {
                 u32 status = ethoc_read(priv, MIISTATUS);
                 if (!(status & MIISTATUS_BUSY)) {
                         u32 data = ethoc_read(priv, MIIRX_DATA);
@@ -593,8 +625,7 @@ static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
                         ethoc_write(priv, MIICOMMAND, 0);
                         return data;
                 }
-
-                schedule();
+                usleep_range(100,200);
         }
 
         return -EBUSY;
@@ -602,22 +633,21 @@ static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
 
 static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
 {
-        unsigned long timeout = jiffies + ETHOC_MII_TIMEOUT;
         struct ethoc *priv = bus->priv;
+        int i;
 
         ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
         ethoc_write(priv, MIITX_DATA, val);
         ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
 
-        while (time_before(jiffies, timeout)) {
+        for (i=0; i < 5; i++) {
                 u32 stat = ethoc_read(priv, MIISTATUS);
                 if (!(stat & MIISTATUS_BUSY)) {
                         /* reset MII command register */
                         ethoc_write(priv, MIICOMMAND, 0);
                         return 0;
                 }
-
-                schedule();
+                usleep_range(100,200);
         }
 
         return -EBUSY;
@@ -971,9 +1001,17 @@ static int __devinit ethoc_probe(struct platform_device *pdev)
         /* calculate the number of TX/RX buffers, maximum 128 supported */
         num_bd = min_t(unsigned int,
                 128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
-        priv->num_tx = max(2, num_bd / 4);
+        if (num_bd < 4) {
+                ret = -ENODEV;
+                goto error;
+        }
+        /* num_tx must be a power of two */
+        priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
         priv->num_rx = num_bd - priv->num_tx;
 
+        dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
+                priv->num_tx, priv->num_rx);
+
         priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void*), GFP_KERNEL);
         if (!priv->vma) {
                 ret = -ENOMEM;
@@ -982,10 +1020,23 @@ static int __devinit ethoc_probe(struct platform_device *pdev)
 
         /* Allow the platform setup code to pass in a MAC address. */
         if (pdev->dev.platform_data) {
-                struct ethoc_platform_data *pdata =
-                        (struct ethoc_platform_data *)pdev->dev.platform_data;
+                struct ethoc_platform_data *pdata = pdev->dev.platform_data;
                 memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
                 priv->phy_id = pdata->phy_id;
+        } else {
+                priv->phy_id = -1;
+
+#ifdef CONFIG_OF
+                {
+                const uint8_t* mac;
+
+                mac = of_get_property(pdev->dev.of_node,
+                                      "local-mac-address",
+                                      NULL);
+                if (mac)
+                        memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
+                }
+#endif
         }
 
         /* Check that the given MAC address is valid. If it isn't, read the
@@ -1046,7 +1097,6 @@ static int __devinit ethoc_probe(struct platform_device *pdev)
         /* setup NAPI */
         netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
 
-        spin_lock_init(&priv->rx_lock);
         spin_lock_init(&priv->lock);
 
         ret = register_netdev(netdev);
@@ -1113,6 +1163,16 @@ static int ethoc_resume(struct platform_device *pdev)
 # define ethoc_resume  NULL
 #endif
 
+#ifdef CONFIG_OF
+static struct of_device_id ethoc_match[] = {
+        {
+                .compatible = "opencores,ethoc",
+        },
+        {},
+};
+MODULE_DEVICE_TABLE(of, ethoc_match);
+#endif
+
 static struct platform_driver ethoc_driver = {
         .probe   = ethoc_probe,
         .remove  = __devexit_p(ethoc_remove),
@@ -1120,6 +1180,10 @@ static struct platform_driver ethoc_driver = {
         .resume  = ethoc_resume,
         .driver  = {
                 .name = "ethoc",
+                .owner = THIS_MODULE,
+#ifdef CONFIG_OF
+                .of_match_table = ethoc_match,
+#endif
         },
 };
 
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index cce32d43175f..2a71373719ae 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -17,6 +17,8 @@
  *
  * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
  * Copyright (c) 2004-2006 Macq Electronique SA.
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
  */
 
 #include <linux/module.h>
@@ -45,29 +47,41 @@
 
 #include <asm/cacheflush.h>
 
-#ifndef CONFIG_ARCH_MXC
+#ifndef CONFIG_ARM
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #endif
 
 #include "fec.h"
 
-#ifdef CONFIG_ARCH_MXC
-#include <mach/hardware.h>
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 #define FEC_ALIGNMENT   0xf
 #else
 #define FEC_ALIGNMENT   0x3
 #endif
 
-/*
- * Define the fixed address of the FEC hardware.
- */
-#if defined(CONFIG_M5272)
+#define DRIVER_NAME     "fec"
+
+/* Controller is ENET-MAC */
+#define FEC_QUIRK_ENET_MAC              (1 << 0)
+/* Controller needs driver to swap frame */
+#define FEC_QUIRK_SWAP_FRAME            (1 << 1)
 
-static unsigned char    fec_mac_default[] = {
-        0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+static struct platform_device_id fec_devtype[] = {
+        {
+                .name = DRIVER_NAME,
+                .driver_data = 0,
+        }, {
+                .name = "imx28-fec",
+                .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
+        }
 };
 
+static unsigned char macaddr[ETH_ALEN];
+module_param_array(macaddr, byte, NULL, 0);
+MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
+
+#if defined(CONFIG_M5272)
 /*
  * Some hardware gets it MAC address out of local flash memory.
  * if this is non-zero then assume it is the address to get MAC from.
@@ -133,7 +147,8 @@ static unsigned char	fec_mac_default[] = {
  * account when setting it.
  */
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 #define OPT_FRAME_SIZE  (PKT_MAXBUF_SIZE << 16)
 #else
 #define OPT_FRAME_SIZE  0
@@ -186,7 +201,6 @@ struct fec_enet_private {
         int     mii_timeout;
         uint    phy_speed;
         phy_interface_t phy_interface;
-        int     index;
         int     link;
         int     full_duplex;
         struct  completion mdio_done;
@@ -213,10 +227,23 @@ static void fec_stop(struct net_device *dev);
 /* Transmitter timeout */
 #define TX_TIMEOUT (2 * HZ)
 
+static void *swap_buffer(void *bufaddr, int len)
+{
+        int i;
+        unsigned int *buf = bufaddr;
+
+        for (i = 0; i < (len + 3) / 4; i++, buf++)
+                *buf = cpu_to_be32(*buf);
+
+        return bufaddr;
+}
+
 static netdev_tx_t
 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         struct bufdesc *bdp;
         void *bufaddr;
         unsigned short  status;
@@ -261,6 +288,14 @@ fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
                 bufaddr = fep->tx_bounce[index];
         }
 
+        /*
+         * Some design made an incorrect assumption on endian mode of
+         * the system that it's running on. As the result, driver has to
+         * swap every frame going to and coming from the controller.
+         */
+        if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
+                swap_buffer(bufaddr, skb->len);
+
         /* Save skb pointer */
         fep->tx_skbuff[fep->skb_cur] = skb;
 
@@ -429,6 +464,8 @@ static void
 fec_enet_rx(struct net_device *dev)
 {
         struct  fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         struct bufdesc *bdp;
         unsigned short status;
         struct  sk_buff *skb;
@@ -492,6 +529,9 @@ fec_enet_rx(struct net_device *dev)
                 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen,
                                 DMA_FROM_DEVICE);
 
+                if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
+                        swap_buffer(data, pkt_len);
+
                 /* This does 16 byte alignment, exactly what we need.
                  * The packet length includes FCS, but we don't want to
                  * include that when passing upstream as it messes up
@@ -538,37 +578,50 @@ rx_processing_done:
 }
 
 /* ------------------------------------------------------------------------- */
-#ifdef CONFIG_M5272
 static void __inline__ fec_get_mac(struct net_device *dev)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
+        struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
         unsigned char *iap, tmpaddr[ETH_ALEN];
 
-        if (FEC_FLASHMAC) {
-                /*
-                 * Get MAC address from FLASH.
-                 * If it is all 1's or 0's, use the default.
-                 */
-                iap = (unsigned char *)FEC_FLASHMAC;
-                if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) &&
-                    (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0))
-                        iap = fec_mac_default;
-                if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) &&
-                    (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff))
-                        iap = fec_mac_default;
-        } else {
-                *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW);
-                *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
+        /*
+         * try to get mac address in following order:
+         *
+         * 1) module parameter via kernel command line in form
+         *    fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
+         */
+        iap = macaddr;
+
+        /*
+         * 2) from flash or fuse (via platform data)
+         */
+        if (!is_valid_ether_addr(iap)) {
+#ifdef CONFIG_M5272
+                if (FEC_FLASHMAC)
+                        iap = (unsigned char *)FEC_FLASHMAC;
+#else
+                if (pdata)
+                        memcpy(iap, pdata->mac, ETH_ALEN);
+#endif
+        }
+
+        /*
+         * 3) FEC mac registers set by bootloader
+         */
+        if (!is_valid_ether_addr(iap)) {
+                *((unsigned long *) &tmpaddr[0]) =
+                        be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
+                *((unsigned short *) &tmpaddr[4]) =
+                        be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
                 iap = &tmpaddr[0];
         }
 
         memcpy(dev->dev_addr, iap, ETH_ALEN);
 
-        /* Adjust MAC if using default MAC address */
-        if (iap == fec_mac_default)
-                 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index;
+        /* Adjust MAC if using macaddr */
+        if (iap == macaddr)
+                 dev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->pdev->id;
 }
-#endif
 
 /* ------------------------------------------------------------------------- */
 
@@ -651,8 +704,8 @@ static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
         fep->mii_timeout = 0;
         init_completion(&fep->mdio_done);
 
-        /* start a read op */
-        writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
+        /* start a write op */
+        writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
                 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
                 FEC_MMFR_TA | FEC_MMFR_DATA(value),
                 fep->hwp + FEC_MII_DATA);
@@ -681,6 +734,7 @@ static int fec_enet_mii_probe(struct net_device *dev)
         char mdio_bus_id[MII_BUS_ID_SIZE];
         char phy_name[MII_BUS_ID_SIZE + 3];
         int phy_id;
+        int dev_id = fep->pdev->id;
 
         fep->phy_dev = NULL;
 
@@ -692,6 +746,8 @@ static int fec_enet_mii_probe(struct net_device *dev)
                         continue;
                 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
                         continue;
+                if (dev_id--)
+                        continue;
                 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
                 break;
         }
@@ -729,10 +785,35 @@ static int fec_enet_mii_probe(struct net_device *dev)
 
 static int fec_enet_mii_init(struct platform_device *pdev)
 {
+        static struct mii_bus *fec0_mii_bus;
         struct net_device *dev = platform_get_drvdata(pdev);
         struct fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         int err = -ENXIO, i;
 
+        /*
+         * The dual fec interfaces are not equivalent with enet-mac.
+         * Here are the differences:
+         *
+         *  - fec0 supports MII & RMII modes while fec1 only supports RMII
+         *  - fec0 acts as the 1588 time master while fec1 is slave
+         *  - external phys can only be configured by fec0
+         *
+         * That is to say fec1 can not work independently. It only works
+         * when fec0 is working. The reason behind this design is that the
+         * second interface is added primarily for Switch mode.
+         *
+         * Because of the last point above, both phys are attached on fec0
+         * mdio interface in board design, and need to be configured by
+         * fec0 mii_bus.
+         */
+        if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && pdev->id) {
+                /* fec1 uses fec0 mii_bus */
+                fep->mii_bus = fec0_mii_bus;
+                return 0;
+        }
+
         fep->mii_timeout = 0;
 
         /*
@@ -769,6 +850,10 @@ static int fec_enet_mii_init(struct platform_device *pdev)
         if (mdiobus_register(fep->mii_bus))
                 goto err_out_free_mdio_irq;
 
+        /* save fec0 mii_bus */
+        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
+                fec0_mii_bus = fep->mii_bus;
+
         return 0;
 
 err_out_free_mdio_irq:
@@ -1067,9 +1152,8 @@ static const struct net_device_ops fec_netdev_ops = {
  /*
   * XXX:  We need to clean up on failure exits here.
   *
-  * index is only used in legacy code
   */
-static int fec_enet_init(struct net_device *dev, int index)
+static int fec_enet_init(struct net_device *dev)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
         struct bufdesc *cbd_base;
@@ -1086,26 +1170,11 @@ static int fec_enet_init(struct net_device *dev, int index)
 
         spin_lock_init(&fep->hw_lock);
 
-        fep->index = index;
         fep->hwp = (void __iomem *)dev->base_addr;
         fep->netdev = dev;
 
-        /* Set the Ethernet address */
-#ifdef CONFIG_M5272
+        /* Get the Ethernet address */
         fec_get_mac(dev);
-#else
-        {
-                unsigned long l;
-                l = readl(fep->hwp + FEC_ADDR_LOW);
-                dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24);
-                dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16);
-                dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8);
-                dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0);
-                l = readl(fep->hwp + FEC_ADDR_HIGH);
-                dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24);
-                dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16);
-        }
-#endif
 
         /* Set receive and transmit descriptor base. */
         fep->rx_bd_base = cbd_base;
@@ -1156,12 +1225,25 @@ static void
 fec_restart(struct net_device *dev, int duplex)
 {
         struct fec_enet_private *fep = netdev_priv(dev);
+        const struct platform_device_id *id_entry =
+                                platform_get_device_id(fep->pdev);
         int i;
+        u32 val, temp_mac[2];
 
         /* Whack a reset.  We should wait for this. */
         writel(1, fep->hwp + FEC_ECNTRL);
         udelay(10);
 
+        /*
+         * enet-mac reset will reset mac address registers too,
+         * so need to reconfigure it.
+         */
+        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+                memcpy(&temp_mac, dev->dev_addr, ETH_ALEN);
+                writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
+                writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
+        }
+
         /* Clear any outstanding interrupt. */
         writel(0xffc00000, fep->hwp + FEC_IEVENT);
 
@@ -1208,20 +1290,45 @@ fec_restart(struct net_device *dev, int duplex)
         /* Set MII speed */
         writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
 
-#ifdef FEC_MIIGSK_ENR
-        if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
-                /* disable the gasket and wait */
-                writel(0, fep->hwp + FEC_MIIGSK_ENR);
-                while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
-                        udelay(1);
+        /*
+         * The phy interface and speed need to get configured
+         * differently on enet-mac.
+         */
+        if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
+                val = readl(fep->hwp + FEC_R_CNTRL);
 
-                /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
-                writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+                /* MII or RMII */
+                if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
+                        val |= (1 << 8);
+                else
+                        val &= ~(1 << 8);
 
-                /* re-enable the gasket */
-                writel(2, fep->hwp + FEC_MIIGSK_ENR);
-        }
+                /* 10M or 100M */
+                if (fep->phy_dev && fep->phy_dev->speed == SPEED_100)
+                        val &= ~(1 << 9);
+                else
+                        val |= (1 << 9);
+
+                writel(val, fep->hwp + FEC_R_CNTRL);
+        } else {
+#ifdef FEC_MIIGSK_ENR
+                if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) {
+                        /* disable the gasket and wait */
+                        writel(0, fep->hwp + FEC_MIIGSK_ENR);
+                        while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
+                                udelay(1);
+
+                        /*
+                         * configure the gasket:
+                         *   RMII, 50 MHz, no loopback, no echo
+                         */
+                        writel(1, fep->hwp + FEC_MIIGSK_CFGR);
+
+                        /* re-enable the gasket */
+                        writel(2, fep->hwp + FEC_MIIGSK_ENR);
+                }
 #endif
+        }
 
         /* And last, enable the transmit and receive processing */
         writel(2, fep->hwp + FEC_ECNTRL);
@@ -1316,7 +1423,7 @@ fec_probe(struct platform_device *pdev)
         }
         clk_enable(fep->clk);
 
-        ret = fec_enet_init(ndev, 0);
+        ret = fec_enet_init(ndev);
         if (ret)
                 goto failed_init;
 
@@ -1380,8 +1487,10 @@ fec_suspend(struct device *dev)
 
         if (ndev) {
                 fep = netdev_priv(ndev);
-                if (netif_running(ndev))
-                        fec_enet_close(ndev);
+                if (netif_running(ndev)) {
+                        fec_stop(ndev);
+                        netif_device_detach(ndev);
+                }
                 clk_disable(fep->clk);
         }
         return 0;
@@ -1396,8 +1505,10 @@ fec_resume(struct device *dev)
         if (ndev) {
                 fep = netdev_priv(ndev);
                 clk_enable(fep->clk);
-                if (netif_running(ndev))
-                        fec_enet_open(ndev);
+                if (netif_running(ndev)) {
+                        fec_restart(ndev, fep->full_duplex);
+                        netif_device_attach(ndev);
+                }
         }
         return 0;
 }
@@ -1414,12 +1525,13 @@ static const struct dev_pm_ops fec_pm_ops = {
 
 static struct platform_driver fec_driver = {
         .driver = {
-                .name   = "fec",
+                .name   = DRIVER_NAME,
                 .owner  = THIS_MODULE,
 #ifdef CONFIG_PM
                 .pm     = &fec_pm_ops,
 #endif
         },
+        .id_table = fec_devtype,
         .probe  = fec_probe,
         .remove = __devexit_p(fec_drv_remove),
 };
diff --git a/drivers/net/fec.h b/drivers/net/fec.h
index 2c48b25668d5..ace318df4c8d 100644
--- a/drivers/net/fec.h
+++ b/drivers/net/fec.h
@@ -14,7 +14,8 @@
 /****************************************************************************/
 
 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
+    defined(CONFIG_M520x) || defined(CONFIG_M532x) || \
+    defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 /*
  *      Just figures, Motorola would have to change the offsets for
  *      registers in the same peripheral device on different models
@@ -78,7 +79,7 @@
 /*
  *      Define the buffer descriptor structure.
  */
-#ifdef CONFIG_ARCH_MXC
+#if defined(CONFIG_ARCH_MXC) || defined(CONFIG_SOC_IMX28)
 struct bufdesc {
         unsigned short cbd_datlen;      /* Data length */
         unsigned short cbd_sc;  /* Control and status info */
diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c
index e9f5d030bc26..50c1213f61fe 100644
--- a/drivers/net/fec_mpc52xx.c
+++ b/drivers/net/fec_mpc52xx.c
@@ -366,9 +366,8 @@ static irqreturn_t mpc52xx_fec_tx_interrupt(int irq, void *dev_id)
 {
         struct net_device *dev = dev_id;
         struct mpc52xx_fec_priv *priv = netdev_priv(dev);
-        unsigned long flags;
 
-        spin_lock_irqsave(&priv->lock, flags);
+        spin_lock(&priv->lock);
         while (bcom_buffer_done(priv->tx_dmatsk)) {
                 struct sk_buff *skb;
                 struct bcom_fec_bd *bd;
@@ -379,7 +378,7 @@ static irqreturn_t mpc52xx_fec_tx_interrupt(int irq, void *dev_id)
 
                 dev_kfree_skb_irq(skb);
         }
-        spin_unlock_irqrestore(&priv->lock, flags);
+        spin_unlock(&priv->lock);
 
         netif_wake_queue(dev);
 
@@ -395,9 +394,8 @@ static irqreturn_t mpc52xx_fec_rx_interrupt(int irq, void *dev_id)
         struct bcom_fec_bd *bd;
         u32 status, physaddr;
         int length;
-        unsigned long flags;
 
-        spin_lock_irqsave(&priv->lock, flags);
+        spin_lock(&priv->lock);
 
         while (bcom_buffer_done(priv->rx_dmatsk)) {
 
@@ -429,7 +427,7 @@ static irqreturn_t mpc52xx_fec_rx_interrupt(int irq, void *dev_id)
 
                 /* Process the received skb - Drop the spin lock while
                  * calling into the network stack */
-                spin_unlock_irqrestore(&priv->lock, flags);
+                spin_unlock(&priv->lock);
 
                 dma_unmap_single(dev->dev.parent, physaddr, rskb->len,
                                  DMA_FROM_DEVICE);
@@ -438,10 +436,10 @@ static irqreturn_t mpc52xx_fec_rx_interrupt(int irq, void *dev_id)
                 rskb->protocol = eth_type_trans(rskb, dev);
                 netif_rx(rskb);
 
-                spin_lock_irqsave(&priv->lock, flags);
+                spin_lock(&priv->lock);
         }
 
-        spin_unlock_irqrestore(&priv->lock, flags);
+        spin_unlock(&priv->lock);
 
         return IRQ_HANDLED;
 }
@@ -452,7 +450,6 @@ static irqreturn_t mpc52xx_fec_interrupt(int irq, void *dev_id)
         struct mpc52xx_fec_priv *priv = netdev_priv(dev);
         struct mpc52xx_fec __iomem *fec = priv->fec;
         u32 ievent;
-        unsigned long flags;
 
         ievent = in_be32(&fec->ievent);
 
@@ -470,9 +467,9 @@ static irqreturn_t mpc52xx_fec_interrupt(int irq, void *dev_id)
                 if (net_ratelimit() && (ievent & FEC_IEVENT_XFIFO_ERROR))
                         dev_warn(&dev->dev, "FEC_IEVENT_XFIFO_ERROR\n");
 
-                spin_lock_irqsave(&priv->lock, flags);
+                spin_lock(&priv->lock);
                 mpc52xx_fec_reset(dev);
-                spin_unlock_irqrestore(&priv->lock, flags);
+                spin_unlock(&priv->lock);
 
                 return IRQ_HANDLED;
         }
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index 0fa1776563a3..af09296ef0dd 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -39,6 +39,9 @@
  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  * superfluous timer interrupts from the nic.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #define FORCEDETH_VERSION               "0.64"
 #define DRV_NAME                        "forcedeth"
 
@@ -60,18 +63,12 @@
 #include <linux/if_vlan.h>
 #include <linux/dma-mapping.h>
 #include <linux/slab.h>
+#include <linux/uaccess.h>
+#include  <linux/io.h>
 
 #include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/uaccess.h>
 #include <asm/system.h>
 
-#if 0
-#define dprintk                 printk
-#else
-#define dprintk(x...)           do { } while (0)
-#endif
-
 #define TX_WORK_PER_LOOP  64
 #define RX_WORK_PER_LOOP  64
 
@@ -186,9 +183,9 @@ enum {
         NvRegSlotTime = 0x9c,
 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
-#define NVREG_SLOTTIME_1000_FULL        0x0003ff00
+#define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 #define NVREG_SLOTTIME_HALF             0x0000ff00
-#define NVREG_SLOTTIME_DEFAULT          0x00007f00
+#define NVREG_SLOTTIME_DEFAULT          0x00007f00
 #define NVREG_SLOTTIME_MASK             0x000000ff
 
         NvRegTxDeferral = 0xA0,
@@ -297,7 +294,7 @@ enum {
 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 
         NvRegMgmtUnitGetVersion = 0x204,
-#define NVREG_MGMTUNITGETVERSION        0x01
+#define NVREG_MGMTUNITGETVERSION        0x01
         NvRegMgmtUnitVersion = 0x208,
 #define NVREG_MGMTUNITVERSION           0x08
         NvRegPowerCap = 0x268,
@@ -368,8 +365,8 @@ struct ring_desc_ex {
 };
 
 union ring_type {
-        struct ring_desc* orig;
-        struct ring_desc_ex* ex;
+        struct ring_desc *orig;
+        struct ring_desc_ex *ex;
 };
 
 #define FLAG_MASK_V1 0xffff0000
@@ -444,10 +441,10 @@ union ring_type {
 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 
 /* Miscelaneous hardware related defines: */
-#define NV_PCI_REGSZ_VER1       0x270
-#define NV_PCI_REGSZ_VER2       0x2d4
-#define NV_PCI_REGSZ_VER3       0x604
-#define NV_PCI_REGSZ_MAX        0x604
+#define NV_PCI_REGSZ_VER1       0x270
+#define NV_PCI_REGSZ_VER2       0x2d4
+#define NV_PCI_REGSZ_VER3       0x604
+#define NV_PCI_REGSZ_MAX        0x604
 
 /* various timeout delays: all in usec */
 #define NV_TXRX_RESET_DELAY     4
@@ -717,7 +714,7 @@ static const struct register_test nv_registers_test[] = {
         { NvRegMulticastAddrA, 0xffffffff },
         { NvRegTxWatermark, 0x0ff },
         { NvRegWakeUpFlags, 0x07777 },
-        { 0,0 }
+        { 0, 0 }
 };
 
 struct nv_skb_map {
@@ -911,7 +908,7 @@ static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
  * Power down phy when interface is down (persists through reboot;
  * older Linux and other OSes may not power it up again)
  */
-static int phy_power_down = 0;
+static int phy_power_down;
 
 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 {
@@ -948,7 +945,7 @@ static bool nv_optimized(struct fe_priv *np)
 }
 
 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
-                                int delay, int delaymax, const char *msg)
+                     int delay, int delaymax)
 {
         u8 __iomem *base = get_hwbase(dev);
 
@@ -956,11 +953,8 @@ static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
         do {
                 udelay(delay);
                 delaymax -= delay;
-                if (delaymax < 0) {
-                        if (msg)
-                                printk("%s", msg);
+                if (delaymax < 0)
                         return 1;
-                }
         } while ((readl(base + offset) & mask) != target);
         return 0;
 }
@@ -984,12 +978,10 @@ static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
         u8 __iomem *base = get_hwbase(dev);
 
         if (!nv_optimized(np)) {
-                if (rxtx_flags & NV_SETUP_RX_RING) {
+                if (rxtx_flags & NV_SETUP_RX_RING)
                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
-                }
-                if (rxtx_flags & NV_SETUP_TX_RING) {
+                if (rxtx_flags & NV_SETUP_TX_RING)
                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
-                }
         } else {
                 if (rxtx_flags & NV_SETUP_RX_RING) {
                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
@@ -1015,10 +1007,8 @@ static void free_rings(struct net_device *dev)
                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
                                             np->rx_ring.ex, np->ring_addr);
         }
-        if (np->rx_skb)
-                kfree(np->rx_skb);
-        if (np->tx_skb)
-                kfree(np->tx_skb);
+        kfree(np->rx_skb);
+        kfree(np->tx_skb);
 }
 
 static int using_multi_irqs(struct net_device *dev)
@@ -1145,23 +1135,15 @@ static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
         writel(reg, base + NvRegMIIControl);
 
         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
-                        NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
-                dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
-                                dev->name, miireg, addr);
+                        NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
                 retval = -1;
         } else if (value != MII_READ) {
                 /* it was a write operation - fewer failures are detectable */
-                dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
-                                dev->name, value, miireg, addr);
                 retval = 0;
         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
-                dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
-                                dev->name, miireg, addr);
                 retval = -1;
         } else {
                 retval = readl(base + NvRegMIIData);
-                dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
-                                dev->name, miireg, addr, retval);
         }
 
         return retval;
@@ -1174,16 +1156,15 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup)
         unsigned int tries = 0;
 
         miicontrol = BMCR_RESET | bmcr_setup;
-        if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
+        if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
                 return -1;
-        }
 
         /* wait for 500ms */
         msleep(500);
 
         /* must wait till reset is deasserted */
         while (miicontrol & BMCR_RESET) {
-                msleep(10);
+                usleep_range(10000, 20000);
                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
                 /* FIXME: 100 tries seem excessive */
                 if (tries++ > 100)
@@ -1192,106 +1173,239 @@ static int phy_reset(struct net_device *dev, u32 bmcr_setup)
         return 0;
 }
 
+static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
+{
+        static const struct {
+                int reg;
+                int init;
+        } ri[] = {
+                { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
+                { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
+                { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
+                { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
+                { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
+                { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
+                { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
+        };
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ri); i++) {
+                if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
+                        return PHY_ERROR;
+        }
+
+        return 0;
+}
+
+static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
+{
+        u32 reg;
+        u8 __iomem *base = get_hwbase(dev);
+        u32 powerstate = readl(base + NvRegPowerState2);
+
+        /* need to perform hw phy reset */
+        powerstate |= NVREG_POWERSTATE2_PHY_RESET;
+        writel(powerstate, base + NvRegPowerState2);
+        msleep(25);
+
+        powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
+        writel(powerstate, base + NvRegPowerState2);
+        msleep(25);
+
+        reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
+        reg |= PHY_REALTEK_INIT9;
+        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
+                return PHY_ERROR;
+        reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
+        if (!(reg & PHY_REALTEK_INIT11)) {
+                reg |= PHY_REALTEK_INIT11;
+                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
+                        return PHY_ERROR;
+        }
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
+                return PHY_ERROR;
+
+        return 0;
+}
+
+static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
+{
+        u32 phy_reserved;
+
+        if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
+                phy_reserved = mii_rw(dev, np->phyaddr,
+                                      PHY_REALTEK_INIT_REG6, MII_READ);
+                phy_reserved |= PHY_REALTEK_INIT7;
+                if (mii_rw(dev, np->phyaddr,
+                           PHY_REALTEK_INIT_REG6, phy_reserved))
+                        return PHY_ERROR;
+        }
+
+        return 0;
+}
+
+static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
+{
+        u32 phy_reserved;
+
+        if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
+                if (mii_rw(dev, np->phyaddr,
+                           PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
+                        return PHY_ERROR;
+                phy_reserved = mii_rw(dev, np->phyaddr,
+                                      PHY_REALTEK_INIT_REG2, MII_READ);
+                phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
+                phy_reserved |= PHY_REALTEK_INIT3;
+                if (mii_rw(dev, np->phyaddr,
+                           PHY_REALTEK_INIT_REG2, phy_reserved))
+                        return PHY_ERROR;
+                if (mii_rw(dev, np->phyaddr,
+                           PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
+                        return PHY_ERROR;
+        }
+
+        return 0;
+}
+
+static int init_cicada(struct net_device *dev, struct fe_priv *np,
+                       u32 phyinterface)
+{
+        u32 phy_reserved;
+
+        if (phyinterface & PHY_RGMII) {
+                phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
+                phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
+                phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
+                if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
+                        return PHY_ERROR;
+                phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
+                phy_reserved |= PHY_CICADA_INIT5;
+                if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
+                        return PHY_ERROR;
+        }
+        phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
+        phy_reserved |= PHY_CICADA_INIT6;
+        if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
+                return PHY_ERROR;
+
+        return 0;
+}
+
+static int init_vitesse(struct net_device *dev, struct fe_priv *np)
+{
+        u32 phy_reserved;
+
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
+                return PHY_ERROR;
+        phy_reserved = mii_rw(dev, np->phyaddr,
+                              PHY_VITESSE_INIT_REG4, MII_READ);
+        if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
+                return PHY_ERROR;
+        phy_reserved = mii_rw(dev, np->phyaddr,
+                              PHY_VITESSE_INIT_REG3, MII_READ);
+        phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
+        phy_reserved |= PHY_VITESSE_INIT3;
+        if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
+                return PHY_ERROR;
+        phy_reserved = mii_rw(dev, np->phyaddr,
+                              PHY_VITESSE_INIT_REG4, MII_READ);
+        phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
+        phy_reserved |= PHY_VITESSE_INIT3;
+        if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
+                return PHY_ERROR;
+        phy_reserved = mii_rw(dev, np->phyaddr,
+                              PHY_VITESSE_INIT_REG3, MII_READ);
+        if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
+                return PHY_ERROR;
+        phy_reserved = mii_rw(dev, np->phyaddr,
+                              PHY_VITESSE_INIT_REG4, MII_READ);
+        if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
+                return PHY_ERROR;
+        phy_reserved = mii_rw(dev, np->phyaddr,
+                              PHY_VITESSE_INIT_REG3, MII_READ);
+        phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
+        phy_reserved |= PHY_VITESSE_INIT8;
+        if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
+                return PHY_ERROR;
+        if (mii_rw(dev, np->phyaddr,
+                   PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
+                return PHY_ERROR;
+
+        return 0;
+}
+
 static int phy_init(struct net_device *dev)
 {
         struct fe_priv *np = get_nvpriv(dev);
         u8 __iomem *base = get_hwbase(dev);
-        u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
+        u32 phyinterface;
+        u32 mii_status, mii_control, mii_control_1000, reg;
 
         /* phy errata for E3016 phy */
         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
                 reg &= ~PHY_MARVELL_E3016_INITMASK;
                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
-                        printk(KERN_INFO "%s: phy write to errata reg failed.\n", pci_name(np->pci_dev));
+                        netdev_info(dev, "%s: phy write to errata reg failed\n",
+                                    pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
         }
         if (np->phy_oui == PHY_OUI_REALTEK) {
                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
                     np->phy_rev == PHY_REV_REALTEK_8211B) {
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        if (init_realtek_8211b(dev, np)) {
+                                netdev_info(dev, "%s: phy init failed\n",
+                                            pci_name(np->pci_dev));
                                 return PHY_ERROR;
                         }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
+                           np->phy_rev == PHY_REV_REALTEK_8211C) {
+                        if (init_realtek_8211c(dev, np)) {
+                                netdev_info(dev, "%s: phy init failed\n",
+                                            pci_name(np->pci_dev));
                                 return PHY_ERROR;
                         }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                }
-                if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
-                    np->phy_rev == PHY_REV_REALTEK_8211C) {
-                        u32 powerstate = readl(base + NvRegPowerState2);
-
-                        /* need to perform hw phy reset */
-                        powerstate |= NVREG_POWERSTATE2_PHY_RESET;
-                        writel(powerstate, base + NvRegPowerState2);
-                        msleep(25);
-
-                        powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
-                        writel(powerstate, base + NvRegPowerState2);
-                        msleep(25);
-
-                        reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
-                        reg |= PHY_REALTEK_INIT9;
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
-                        if (!(reg & PHY_REALTEK_INIT11)) {
-                                reg |= PHY_REALTEK_INIT11;
-                                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) {
-                                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                        return PHY_ERROR;
-                                }
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
+                        if (init_realtek_8201(dev, np)) {
+                                netdev_info(dev, "%s: phy init failed\n",
+                                            pci_name(np->pci_dev));
                                 return PHY_ERROR;
                         }
                 }
-                if (np->phy_model == PHY_MODEL_REALTEK_8201) {
-                        if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
-                                phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
-                                phy_reserved |= PHY_REALTEK_INIT7;
-                                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
-                                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                        return PHY_ERROR;
-                                }
-                        }
-                }
         }
 
         /* set advertise register */
         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
-        reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|ADVERTISE_PAUSE_ASYM|ADVERTISE_PAUSE_CAP);
+        reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
+                ADVERTISE_100HALF | ADVERTISE_100FULL |
+                ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
-                printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
+                netdev_info(dev, "%s: phy write to advertise failed\n",
+                            pci_name(np->pci_dev));
                 return PHY_ERROR;
         }
 
@@ -1302,7 +1416,8 @@ static int phy_init(struct net_device *dev)
         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
         if (mii_status & PHY_GIGABIT) {
                 np->gigabit = PHY_GIGABIT;
-                mii_control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
+                mii_control_1000 = mii_rw(dev, np->phyaddr,
+                                          MII_CTRL1000, MII_READ);
                 mii_control_1000 &= ~ADVERTISE_1000HALF;
                 if (phyinterface & PHY_RGMII)
                         mii_control_1000 |= ADVERTISE_1000FULL;
@@ -1310,11 +1425,11 @@ static int phy_init(struct net_device *dev)
                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 
                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        netdev_info(dev, "%s: phy init failed\n",
+                                    pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
-        }
-        else
+        } else
                 np->gigabit = 0;
 
         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
@@ -1326,7 +1441,8 @@ static int phy_init(struct net_device *dev)
                 /* start autoneg since we already performed hw reset above */
                 mii_control |= BMCR_ANRESTART;
                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
-                        printk(KERN_INFO "%s: phy init failed\n", pci_name(np->pci_dev));
+                        netdev_info(dev, "%s: phy init failed\n",
+                                    pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
         } else {
@@ -1334,164 +1450,41 @@ static int phy_init(struct net_device *dev)
                  * (certain phys need bmcr to be setup with reset)
                  */
                 if (phy_reset(dev, mii_control)) {
-                        printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
+                        netdev_info(dev, "%s: phy reset failed\n",
+                                    pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
         }
 
         /* phy vendor specific configuration */
-        if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
-                phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
-                phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
-                phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
-                if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+        if ((np->phy_oui == PHY_OUI_CICADA)) {
+                if (init_cicada(dev, np, phyinterface)) {
+                        netdev_info(dev, "%s: phy init failed\n",
+                                    pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
-                phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
-                phy_reserved |= PHY_CICADA_INIT5;
-                if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+        } else if (np->phy_oui == PHY_OUI_VITESSE) {
+                if (init_vitesse(dev, np)) {
+                        netdev_info(dev, "%s: phy init failed\n",
+                                    pci_name(np->pci_dev));
                         return PHY_ERROR;
                 }
-        }
-        if (np->phy_oui == PHY_OUI_CICADA) {
-                phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
-                phy_reserved |= PHY_CICADA_INIT6;
-                if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-        }
-        if (np->phy_oui == PHY_OUI_VITESSE) {
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
-                phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
-                phy_reserved |= PHY_VITESSE_INIT3;
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
-                phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
-                phy_reserved |= PHY_VITESSE_INIT3;
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, MII_READ);
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                phy_reserved = mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, MII_READ);
-                phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
-                phy_reserved |= PHY_VITESSE_INIT8;
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-                if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10)) {
-                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                        return PHY_ERROR;
-                }
-        }
-        if (np->phy_oui == PHY_OUI_REALTEK) {
+        } else if (np->phy_oui == PHY_OUI_REALTEK) {
                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
                     np->phy_rev == PHY_REV_REALTEK_8211B) {
                         /* reset could have cleared these out, set them back */
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                        if (init_realtek_8211b(dev, np)) {
+                                netdev_info(dev, "%s: phy init failed\n",
+                                            pci_name(np->pci_dev));
                                 return PHY_ERROR;
                         }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
+                } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
+                        if (init_realtek_8201(dev, np) ||
+                            init_realtek_8201_cross(dev, np)) {
+                                netdev_info(dev, "%s: phy init failed\n",
+                                            pci_name(np->pci_dev));
                                 return PHY_ERROR;
                         }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                        if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
-                                printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                return PHY_ERROR;
-                        }
-                }
-                if (np->phy_model == PHY_MODEL_REALTEK_8201) {
-                        if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
-                                phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
-                                phy_reserved |= PHY_REALTEK_INIT7;
-                                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, phy_reserved)) {
-                                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                        return PHY_ERROR;
-                                }
-                        }
-                        if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
-                                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
-                                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                        return PHY_ERROR;
-                                }
-                                phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
-                                phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
-                                phy_reserved |= PHY_REALTEK_INIT3;
-                                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved)) {
-                                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                        return PHY_ERROR;
-                                }
-                                if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
-                                        printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
-                                        return PHY_ERROR;
-                                }
-                        }
                 }
         }
 
@@ -1501,12 +1494,10 @@ static int phy_init(struct net_device *dev)
         /* restart auto negotiation, power down phy */
         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
-        if (phy_power_down) {
+        if (phy_power_down)
                 mii_control |= BMCR_PDOWN;
-        }
-        if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
+        if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
                 return PHY_ERROR;
-        }
 
         return 0;
 }
@@ -1517,7 +1508,6 @@ static void nv_start_rx(struct net_device *dev)
         u8 __iomem *base = get_hwbase(dev);
         u32 rx_ctrl = readl(base + NvRegReceiverControl);
 
-        dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
         /* Already running? Stop it. */
         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
                 rx_ctrl &= ~NVREG_RCVCTL_START;
@@ -1526,12 +1516,10 @@ static void nv_start_rx(struct net_device *dev)
         }
         writel(np->linkspeed, base + NvRegLinkSpeed);
         pci_push(base);
-        rx_ctrl |= NVREG_RCVCTL_START;
-        if (np->mac_in_use)
+        rx_ctrl |= NVREG_RCVCTL_START;
+        if (np->mac_in_use)
                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
         writel(rx_ctrl, base + NvRegReceiverControl);
-        dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
-                                dev->name, np->duplex, np->linkspeed);
         pci_push(base);
 }
 
@@ -1541,15 +1529,15 @@ static void nv_stop_rx(struct net_device *dev)
         u8 __iomem *base = get_hwbase(dev);
         u32 rx_ctrl = readl(base + NvRegReceiverControl);
 
-        dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
         if (!np->mac_in_use)
                 rx_ctrl &= ~NVREG_RCVCTL_START;
         else
                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
         writel(rx_ctrl, base + NvRegReceiverControl);
-        reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
-                        NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
-                        KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
+        if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
+                      NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
+                netdev_info(dev, "%s: ReceiverStatus remained busy\n",
+                            __func__);
 
         udelay(NV_RXSTOP_DELAY2);
         if (!np->mac_in_use)
@@ -1562,7 +1550,6 @@ static void nv_start_tx(struct net_device *dev)
         u8 __iomem *base = get_hwbase(dev);
         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
 
-        dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
         tx_ctrl |= NVREG_XMITCTL_START;
         if (np->mac_in_use)
                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
@@ -1576,15 +1563,15 @@ static void nv_stop_tx(struct net_device *dev)
         u8 __iomem *base = get_hwbase(dev);
         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
 
-        dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
         if (!np->mac_in_use)
                 tx_ctrl &= ~NVREG_XMITCTL_START;
         else
                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
         writel(tx_ctrl, base + NvRegTransmitterControl);
-        reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
-                        NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
-                        KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
+        if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
+                      NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
+                netdev_info(dev, "%s: TransmitterStatus remained busy\n",
+                            __func__);
 
         udelay(NV_TXSTOP_DELAY2);
         if (!np->mac_in_use)
@@ -1609,7 +1596,6 @@ static void nv_txrx_reset(struct net_device *dev)
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
 
-        dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
         pci_push(base);
         udelay(NV_TXRX_RESET_DELAY);
@@ -1623,8 +1609,6 @@ static void nv_mac_reset(struct net_device *dev)
         u8 __iomem *base = get_hwbase(dev);
         u32 temp1, temp2, temp3;
 
-        dprintk(KERN_DEBUG "%s: nv_mac_reset\n", dev->name);
-
         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
         pci_push(base);
 
@@ -1745,7 +1729,7 @@ static struct net_device_stats *nv_get_stats(struct net_device *dev)
 static int nv_alloc_rx(struct net_device *dev)
 {
         struct fe_priv *np = netdev_priv(dev);
-        struct ring_desc* less_rx;
+        struct ring_desc *less_rx;
 
         less_rx = np->get_rx.orig;
         if (less_rx-- == np->first_rx.orig)
@@ -1767,9 +1751,8 @@ static int nv_alloc_rx(struct net_device *dev)
                                 np->put_rx.orig = np->first_rx.orig;
                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
                                 np->put_rx_ctx = np->first_rx_ctx;
-                } else {
+                } else
                         return 1;
-                }
         }
         return 0;
 }
@@ -1777,7 +1760,7 @@ static int nv_alloc_rx(struct net_device *dev)
 static int nv_alloc_rx_optimized(struct net_device *dev)
 {
         struct fe_priv *np = netdev_priv(dev);
-        struct ring_desc_ex* less_rx;
+        struct ring_desc_ex *less_rx;
 
         less_rx = np->get_rx.ex;
         if (less_rx-- == np->first_rx.ex)
@@ -1800,9 +1783,8 @@ static int nv_alloc_rx_optimized(struct net_device *dev)
                                 np->put_rx.ex = np->first_rx.ex;
                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
                                 np->put_rx_ctx = np->first_rx_ctx;
-                } else {
+                } else
                         return 1;
-                }
         }
         return 0;
 }
@@ -2018,24 +2000,24 @@ static void nv_legacybackoff_reseed(struct net_device *dev)
 
 /* Known Good seed sets */
 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
-    {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
-    {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
-    {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
-    {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
-    {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
-    {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
-    {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
-    {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184}};
+        {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
+        {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
+        {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
+        {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
+        {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
+        {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
+        {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
+        {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
 
 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
-    {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
-    {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
-    {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
-    {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
-    {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
-    {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
-    {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
-    {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395}};
+        {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
+        {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
+        {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
+        {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
+        {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
+        {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
+        {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
+        {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
 
 static void nv_gear_backoff_reseed(struct net_device *dev)
 {
@@ -2083,13 +2065,12 @@ static void nv_gear_backoff_reseed(struct net_device *dev)
         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
-        writel(temp,base + NvRegBackOffControl);
+        writel(temp, base + NvRegBackOffControl);
 
-        /* Setup seeds for all gear LFSRs. */
+        /* Setup seeds for all gear LFSRs. */
         get_random_bytes(&seedset, sizeof(seedset));
         seedset = seedset % BACKOFF_SEEDSET_ROWS;
-        for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++)
-        {
+        for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
                 temp |= main_seedset[seedset][i-1] & 0x3ff;
                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
@@ -2113,10 +2094,10 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
         u32 size = skb_headlen(skb);
         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
         u32 empty_slots;
-        struct ring_desc* put_tx;
-        struct ring_desc* start_tx;
-        struct ring_desc* prev_tx;
-        struct nv_skb_map* prev_tx_ctx;
+        struct ring_desc *put_tx;
+        struct ring_desc *start_tx;
+        struct ring_desc *prev_tx;
+        struct nv_skb_map *prev_tx_ctx;
         unsigned long flags;
 
         /* add fragments to entries count */
@@ -2204,18 +2185,6 @@ static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         spin_unlock_irqrestore(&np->lock, flags);
 
-        dprintk(KERN_DEBUG "%s: nv_start_xmit: entries %d queued for transmission. tx_flags_extra: %x\n",
-                dev->name, entries, tx_flags_extra);
-        {
-                int j;
-                for (j=0; j<64; j++) {
-                        if ((j%16) == 0)
-                                dprintk("\n%03x:", j);
-                        dprintk(" %02x", ((unsigned char*)skb->data)[j]);
-                }
-                dprintk("\n");
-        }
-
         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
         return NETDEV_TX_OK;
 }
@@ -2233,11 +2202,11 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
         u32 size = skb_headlen(skb);
         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
         u32 empty_slots;
-        struct ring_desc_ex* put_tx;
-        struct ring_desc_ex* start_tx;
-        struct ring_desc_ex* prev_tx;
-        struct nv_skb_map* prev_tx_ctx;
-        struct nv_skb_map* start_tx_ctx;
+        struct ring_desc_ex *put_tx;
+        struct ring_desc_ex *start_tx;
+        struct ring_desc_ex *prev_tx;
+        struct nv_skb_map *prev_tx_ctx;
+        struct nv_skb_map *start_tx_ctx;
         unsigned long flags;
 
         /* add fragments to entries count */
@@ -2355,18 +2324,6 @@ static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
 
         spin_unlock_irqrestore(&np->lock, flags);
 
-        dprintk(KERN_DEBUG "%s: nv_start_xmit_optimized: entries %d queued for transmission. tx_flags_extra: %x\n",
-                dev->name, entries, tx_flags_extra);
-        {
-                int j;
-                for (j=0; j<64; j++) {
-                        if ((j%16) == 0)
-                                dprintk("\n%03x:", j);
-                        dprintk(" %02x", ((unsigned char*)skb->data)[j]);
-                }
-                dprintk("\n");
-        }
-
         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
         return NETDEV_TX_OK;
 }
@@ -2399,15 +2356,12 @@ static int nv_tx_done(struct net_device *dev, int limit)
         struct fe_priv *np = netdev_priv(dev);
         u32 flags;
         int tx_work = 0;
-        struct ring_desc* orig_get_tx = np->get_tx.orig;
+        struct ring_desc *orig_get_tx = np->get_tx.orig;
 
         while ((np->get_tx.orig != np->put_tx.orig) &&
                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
                (tx_work < limit)) {
 
-                dprintk(KERN_DEBUG "%s: nv_tx_done: flags 0x%x.\n",
-                                        dev->name, flags);
-
                 nv_unmap_txskb(np, np->get_tx_ctx);
 
                 if (np->desc_ver == DESC_VER_1) {
@@ -2464,15 +2418,12 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit)
         struct fe_priv *np = netdev_priv(dev);
         u32 flags;
         int tx_work = 0;
-        struct ring_desc_ex* orig_get_tx = np->get_tx.ex;
+        struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
 
         while ((np->get_tx.ex != np->put_tx.ex) &&
                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
                (tx_work < limit)) {
 
-                dprintk(KERN_DEBUG "%s: nv_tx_done_optimized: flags 0x%x.\n",
-                                        dev->name, flags);
-
                 nv_unmap_txskb(np, np->get_tx_ctx);
 
                 if (flags & NV_TX2_LASTPACKET) {
@@ -2491,9 +2442,8 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit)
                         np->get_tx_ctx->skb = NULL;
                         tx_work++;
 
-                        if (np->tx_limit) {
+                        if (np->tx_limit)
                                 nv_tx_flip_ownership(dev);
-                        }
                 }
                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
                         np->get_tx.ex = np->first_tx.ex;
@@ -2518,57 +2468,56 @@ static void nv_tx_timeout(struct net_device *dev)
         u32 status;
         union ring_type put_tx;
         int saved_tx_limit;
+        int i;
 
         if (np->msi_flags & NV_MSI_X_ENABLED)
                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
         else
                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
 
-        printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name, status);
-
-        {
-                int i;
-
-                printk(KERN_INFO "%s: Ring at %lx\n",
-                       dev->name, (unsigned long)np->ring_addr);
-                printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
-                for (i=0;i<=np->register_size;i+= 32) {
-                        printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
-                                        i,
-                                        readl(base + i + 0), readl(base + i + 4),
-                                        readl(base + i + 8), readl(base + i + 12),
-                                        readl(base + i + 16), readl(base + i + 20),
-                                        readl(base + i + 24), readl(base + i + 28));
-                }
-                printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
-                for (i=0;i<np->tx_ring_size;i+= 4) {
-                        if (!nv_optimized(np)) {
-                                printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
-                                       i,
-                                       le32_to_cpu(np->tx_ring.orig[i].buf),
-                                       le32_to_cpu(np->tx_ring.orig[i].flaglen),
-                                       le32_to_cpu(np->tx_ring.orig[i+1].buf),
-                                       le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
-                                       le32_to_cpu(np->tx_ring.orig[i+2].buf),
-                                       le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
-                                       le32_to_cpu(np->tx_ring.orig[i+3].buf),
-                                       le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
-                        } else {
-                                printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
-                                       i,
-                                       le32_to_cpu(np->tx_ring.ex[i].bufhigh),
-                                       le32_to_cpu(np->tx_ring.ex[i].buflow),
-                                       le32_to_cpu(np->tx_ring.ex[i].flaglen),
-                                       le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
-                                       le32_to_cpu(np->tx_ring.ex[i+1].buflow),
-                                       le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
-                                       le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
-                                       le32_to_cpu(np->tx_ring.ex[i+2].buflow),
-                                       le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
-                                       le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
-                                       le32_to_cpu(np->tx_ring.ex[i+3].buflow),
-                                       le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
-                        }
+        netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
+
+        netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
+        netdev_info(dev, "Dumping tx registers\n");
+        for (i = 0; i <= np->register_size; i += 32) {
+                netdev_info(dev,
+                            "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+                            i,
+                            readl(base + i + 0), readl(base + i + 4),
+                            readl(base + i + 8), readl(base + i + 12),
+                            readl(base + i + 16), readl(base + i + 20),
+                            readl(base + i + 24), readl(base + i + 28));
+        }
+        netdev_info(dev, "Dumping tx ring\n");
+        for (i = 0; i < np->tx_ring_size; i += 4) {
+                if (!nv_optimized(np)) {
+                        netdev_info(dev,
+                                    "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
+                                    i,
+                                    le32_to_cpu(np->tx_ring.orig[i].buf),
+                                    le32_to_cpu(np->tx_ring.orig[i].flaglen),
+                                    le32_to_cpu(np->tx_ring.orig[i+1].buf),
+                                    le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
+                                    le32_to_cpu(np->tx_ring.orig[i+2].buf),
+                                    le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
+                                    le32_to_cpu(np->tx_ring.orig[i+3].buf),
+                                    le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
+                } else {
+                        netdev_info(dev,
+                                    "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
+                                    i,
+                                    le32_to_cpu(np->tx_ring.ex[i].bufhigh),
+                                    le32_to_cpu(np->tx_ring.ex[i].buflow),
+                                    le32_to_cpu(np->tx_ring.ex[i].flaglen),
+                                    le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
+                                    le32_to_cpu(np->tx_ring.ex[i+1].buflow),
+                                    le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
+                                    le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
+                                    le32_to_cpu(np->tx_ring.ex[i+2].buflow),
+                                    le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
+                                    le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
+                                    le32_to_cpu(np->tx_ring.ex[i+3].buflow),
+                                    le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
                 }
         }
 
@@ -2616,15 +2565,13 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen)
         int protolen;   /* length as stored in the proto field */
 
         /* 1) calculate len according to header */
-        if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
-                protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
+        if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
+                protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
                 hdrlen = VLAN_HLEN;
         } else {
-                protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
+                protolen = ntohs(((struct ethhdr *)packet)->h_proto);
                 hdrlen = ETH_HLEN;
         }
-        dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
-                                dev->name, datalen, protolen, hdrlen);
         if (protolen > ETH_DATA_LEN)
                 return datalen; /* Value in proto field not a len, no checks possible */
 
@@ -2635,26 +2582,18 @@ static int nv_getlen(struct net_device *dev, void *packet, int datalen)
                         /* more data on wire than in 802 header, trim of
                          * additional data.
                          */
-                        dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
-                                        dev->name, protolen);
                         return protolen;
                 } else {
                         /* less data on wire than mentioned in header.
                          * Discard the packet.
                          */
-                        dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
-                                        dev->name);
                         return -1;
                 }
         } else {
                 /* short packet. Accept only if 802 values are also short */
                 if (protolen > ETH_ZLEN) {
-                        dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
-                                        dev->name);
                         return -1;
                 }
-                dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
-                                dev->name, datalen);
                 return datalen;
         }
 }
@@ -2667,13 +2606,10 @@ static int nv_rx_process(struct net_device *dev, int limit)
         struct sk_buff *skb;
         int len;
 
-        while((np->get_rx.orig != np->put_rx.orig) &&
+        while ((np->get_rx.orig != np->put_rx.orig) &&
               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
                 (rx_work < limit)) {
 
-                dprintk(KERN_DEBUG "%s: nv_rx_process: flags 0x%x.\n",
-                                        dev->name, flags);
-
                 /*
                  * the packet is for us - immediately tear down the pci mapping.
                  * TODO: check if a prefetch of the first cacheline improves
@@ -2685,16 +2621,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
                 skb = np->get_rx_ctx->skb;
                 np->get_rx_ctx->skb = NULL;
 
-                {
-                        int j;
-                        dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
-                        for (j=0; j<64; j++) {
-                                if ((j%16) == 0)
-                                        dprintk("\n%03x:", j);
-                                dprintk(" %02x", ((unsigned char*)skb->data)[j]);
-                        }
-                        dprintk("\n");
-                }
                 /* look at what we actually got: */
                 if (np->desc_ver == DESC_VER_1) {
                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
@@ -2710,9 +2636,8 @@ static int nv_rx_process(struct net_device *dev, int limit)
                                         }
                                         /* framing errors are soft errors */
                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
-                                                if (flags & NV_RX_SUBSTRACT1) {
+                                                if (flags & NV_RX_SUBSTRACT1)
                                                         len--;
-                                                }
                                         }
                                         /* the rest are hard errors */
                                         else {
@@ -2745,9 +2670,8 @@ static int nv_rx_process(struct net_device *dev, int limit)
                                         }
                                         /* framing errors are soft errors */
                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
-                                                if (flags & NV_RX2_SUBSTRACT1) {
+                                                if (flags & NV_RX2_SUBSTRACT1)
                                                         len--;
-                                                }
                                         }
                                         /* the rest are hard errors */
                                         else {
@@ -2771,8 +2695,6 @@ static int nv_rx_process(struct net_device *dev, int limit)
                 /* got a valid packet - forward it to the network core */
                 skb_put(skb, len);
                 skb->protocol = eth_type_trans(skb, dev);
-                dprintk(KERN_DEBUG "%s: nv_rx_process: %d bytes, proto %d accepted.\n",
-                                        dev->name, len, skb->protocol);
                 napi_gro_receive(&np->napi, skb);
                 dev->stats.rx_packets++;
                 dev->stats.rx_bytes += len;
@@ -2797,13 +2719,10 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
         struct sk_buff *skb;
         int len;
 
-        while((np->get_rx.ex != np->put_rx.ex) &&
+        while ((np->get_rx.ex != np->put_rx.ex) &&
               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
               (rx_work < limit)) {
 
-                dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: flags 0x%x.\n",
-                                        dev->name, flags);
-
                 /*
                  * the packet is for us - immediately tear down the pci mapping.
                  * TODO: check if a prefetch of the first cacheline improves
@@ -2815,16 +2734,6 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
                 skb = np->get_rx_ctx->skb;
                 np->get_rx_ctx->skb = NULL;
 
-                {
-                        int j;
-                        dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",flags);
-                        for (j=0; j<64; j++) {
-                                if ((j%16) == 0)
-                                        dprintk("\n%03x:", j);
-                                dprintk(" %02x", ((unsigned char*)skb->data)[j]);
-                        }
-                        dprintk("\n");
-                }
                 /* look at what we actually got: */
                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
                         len = flags & LEN_MASK_V2;
@@ -2838,9 +2747,8 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
                                 }
                                 /* framing errors are soft errors */
                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
-                                        if (flags & NV_RX2_SUBSTRACT1) {
+                                        if (flags & NV_RX2_SUBSTRACT1)
                                                 len--;
-                                        }
                                 }
                                 /* the rest are hard errors */
                                 else {
@@ -2858,9 +2766,6 @@ static int nv_rx_process_optimized(struct net_device *dev, int limit)
                         skb->protocol = eth_type_trans(skb, dev);
                         prefetch(skb->data);
 
-                        dprintk(KERN_DEBUG "%s: nv_rx_process_optimized: %d bytes, proto %d accepted.\n",
-                                dev->name, len, skb->protocol);
-
                         if (likely(!np->vlangrp)) {
                                 napi_gro_receive(&np->napi, skb);
                         } else {
@@ -2949,7 +2854,7 @@ static int nv_change_mtu(struct net_device *dev, int new_mtu)
                 /* reinit nic view of the rx queue */
                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
-                writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
+                writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
                         base + NvRegRingSizes);
                 pci_push(base);
                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -2986,7 +2891,7 @@ static void nv_copy_mac_to_hw(struct net_device *dev)
 static int nv_set_mac_address(struct net_device *dev, void *addr)
 {
         struct fe_priv *np = netdev_priv(dev);
-        struct sockaddr *macaddr = (struct sockaddr*)addr;
+        struct sockaddr *macaddr = (struct sockaddr *)addr;
 
         if (!is_valid_ether_addr(macaddr->sa_data))
                 return -EADDRNOTAVAIL;
@@ -3076,8 +2981,6 @@ static void nv_set_multicast(struct net_device *dev)
         writel(mask[0], base + NvRegMulticastMaskA);
         writel(mask[1], base + NvRegMulticastMaskB);
         writel(pff, base + NvRegPacketFilterFlags);
-        dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
-                dev->name);
         nv_start_rx(dev);
         spin_unlock_irq(&np->lock);
 }
@@ -3152,8 +3055,6 @@ static int nv_update_linkspeed(struct net_device *dev)
         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 
         if (!(mii_status & BMSR_LSTATUS)) {
-                dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
-                                dev->name);
                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
                 newdup = 0;
                 retval = 0;
@@ -3161,8 +3062,6 @@ static int nv_update_linkspeed(struct net_device *dev)
         }
 
         if (np->autoneg == 0) {
-                dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
-                                dev->name, np->fixed_mode);
                 if (np->fixed_mode & LPA_100FULL) {
                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
                         newdup = 1;
@@ -3185,14 +3084,11 @@ static int nv_update_linkspeed(struct net_device *dev)
                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
                 newdup = 0;
                 retval = 0;
-                dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
                 goto set_speed;
         }
 
         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
-        dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
-                                dev->name, adv, lpa);
 
         retval = 1;
         if (np->gigabit == PHY_GIGABIT) {
@@ -3201,8 +3097,6 @@ static int nv_update_linkspeed(struct net_device *dev)
 
                 if ((control_1000 & ADVERTISE_1000FULL) &&
                         (status_1000 & LPA_1000FULL)) {
-                        dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
-                                dev->name);
                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
                         newdup = 1;
                         goto set_speed;
@@ -3224,7 +3118,6 @@ static int nv_update_linkspeed(struct net_device *dev)
                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
                 newdup = 0;
         } else {
-                dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, adv_lpa);
                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
                 newdup = 0;
         }
@@ -3233,9 +3126,6 @@ set_speed:
         if (np->duplex == newdup && np->linkspeed == newls)
                 return retval;
 
-        dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
-                        dev->name, np->linkspeed, np->duplex, newls, newdup);
-
         np->duplex = newdup;
         np->linkspeed = newls;
 
@@ -3302,7 +3192,7 @@ set_speed:
         }
         writel(txreg, base + NvRegTxWatermark);
 
-        writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
+        writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
                 base + NvRegMisc1);
         pci_push(base);
         writel(np->linkspeed, base + NvRegLinkSpeed);
@@ -3312,8 +3202,8 @@ set_speed:
         /* setup pause frame */
         if (np->duplex != 0) {
                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
-                        adv_pause = adv & (ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM);
-                        lpa_pause = lpa & (LPA_PAUSE_CAP| LPA_PAUSE_ASYM);
+                        adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
+                        lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
 
                         switch (adv_pause) {
                         case ADVERTISE_PAUSE_CAP:
@@ -3324,22 +3214,17 @@ set_speed:
                                 }
                                 break;
                         case ADVERTISE_PAUSE_ASYM:
-                                if (lpa_pause == (LPA_PAUSE_CAP| LPA_PAUSE_ASYM))
-                                {
+                                if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
-                                }
                                 break;
-                        case ADVERTISE_PAUSE_CAP| ADVERTISE_PAUSE_ASYM:
-                                if (lpa_pause & LPA_PAUSE_CAP)
-                                {
+                        case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
+                                if (lpa_pause & LPA_PAUSE_CAP) {
                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
                                 }
                                 if (lpa_pause == LPA_PAUSE_ASYM)
-                                {
                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
-                                }
                                 break;
                         }
                 } else {
@@ -3361,14 +3246,14 @@ static void nv_linkchange(struct net_device *dev)
         if (nv_update_linkspeed(dev)) {
                 if (!netif_carrier_ok(dev)) {
                         netif_carrier_on(dev);
-                        printk(KERN_INFO "%s: link up.\n", dev->name);
+                        netdev_info(dev, "link up\n");
                         nv_txrx_gate(dev, false);
                         nv_start_rx(dev);
                 }
         } else {
                 if (netif_carrier_ok(dev)) {
                         netif_carrier_off(dev);
-                        printk(KERN_INFO "%s: link down.\n", dev->name);
+                        netdev_info(dev, "link down\n");
                         nv_txrx_gate(dev, true);
                         nv_stop_rx(dev);
                 }
@@ -3382,11 +3267,9 @@ static void nv_link_irq(struct net_device *dev)
 
         miistat = readl(base + NvRegMIIStatus);
         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
-        dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
 
         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
                 nv_linkchange(dev);
-        dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
 }
 
 static void nv_msi_workaround(struct fe_priv *np)
@@ -3437,8 +3320,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
-
         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
                 np->events = readl(base + NvRegIrqStatus);
                 writel(np->events, base + NvRegIrqStatus);
@@ -3446,7 +3327,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
                 np->events = readl(base + NvRegMSIXIrqStatus);
                 writel(np->events, base + NvRegMSIXIrqStatus);
         }
-        dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
         if (!(np->events & np->irqmask))
                 return IRQ_NONE;
 
@@ -3460,8 +3340,6 @@ static irqreturn_t nv_nic_irq(int foo, void *data)
                 __napi_schedule(&np->napi);
         }
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
-
         return IRQ_HANDLED;
 }
 
@@ -3476,8 +3354,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized\n", dev->name);
-
         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
                 np->events = readl(base + NvRegIrqStatus);
                 writel(np->events, base + NvRegIrqStatus);
@@ -3485,7 +3361,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
                 np->events = readl(base + NvRegMSIXIrqStatus);
                 writel(np->events, base + NvRegMSIXIrqStatus);
         }
-        dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, np->events);
         if (!(np->events & np->irqmask))
                 return IRQ_NONE;
 
@@ -3498,7 +3373,6 @@ static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
                 writel(0, base + NvRegIrqMask);
                 __napi_schedule(&np->napi);
         }
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_optimized completed\n", dev->name);
 
         return IRQ_HANDLED;
 }
@@ -3512,12 +3386,9 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data)
         int i;
         unsigned long flags;
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_tx\n", dev->name);
-
-        for (i=0; ; i++) {
+        for (i = 0;; i++) {
                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
                 writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus);
-                dprintk(KERN_DEBUG "%s: tx irq: %08x\n", dev->name, events);
                 if (!(events & np->irqmask))
                         break;
 
@@ -3536,12 +3407,12 @@ static irqreturn_t nv_nic_irq_tx(int foo, void *data)
                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
                         }
                         spin_unlock_irqrestore(&np->lock, flags);
-                        printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_tx.\n", dev->name, i);
+                        netdev_dbg(dev, "%s: too many iterations (%d)\n",
+                                   __func__, i);
                         break;
                 }
 
         }
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_tx completed\n", dev->name);
 
         return IRQ_RETVAL(i);
 }
@@ -3553,7 +3424,7 @@ static int nv_napi_poll(struct napi_struct *napi, int budget)
         u8 __iomem *base = get_hwbase(dev);
         unsigned long flags;
         int retcode;
-        int rx_count, tx_work=0, rx_work=0;
+        int rx_count, tx_work = 0, rx_work = 0;
 
         do {
                 if (!nv_optimized(np)) {
@@ -3626,12 +3497,9 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data)
         int i;
         unsigned long flags;
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_rx\n", dev->name);
-
-        for (i=0; ; i++) {
+        for (i = 0;; i++) {
                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
                 writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus);
-                dprintk(KERN_DEBUG "%s: rx irq: %08x\n", dev->name, events);
                 if (!(events & np->irqmask))
                         break;
 
@@ -3655,11 +3523,11 @@ static irqreturn_t nv_nic_irq_rx(int foo, void *data)
                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
                         }
                         spin_unlock_irqrestore(&np->lock, flags);
-                        printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_rx.\n", dev->name, i);
+                        netdev_dbg(dev, "%s: too many iterations (%d)\n",
+                                   __func__, i);
                         break;
                 }
         }
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_rx completed\n", dev->name);
 
         return IRQ_RETVAL(i);
 }
@@ -3673,12 +3541,9 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
         int i;
         unsigned long flags;
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_other\n", dev->name);
-
-        for (i=0; ; i++) {
+        for (i = 0;; i++) {
                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
                 writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus);
-                dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
                 if (!(events & np->irqmask))
                         break;
 
@@ -3723,12 +3588,12 @@ static irqreturn_t nv_nic_irq_other(int foo, void *data)
                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
                         }
                         spin_unlock_irqrestore(&np->lock, flags);
-                        printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq_other.\n", dev->name, i);
+                        netdev_dbg(dev, "%s: too many iterations (%d)\n",
+                                   __func__, i);
                         break;
                 }
 
         }
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_other completed\n", dev->name);
 
         return IRQ_RETVAL(i);
 }
@@ -3740,8 +3605,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
         u8 __iomem *base = get_hwbase(dev);
         u32 events;
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_test\n", dev->name);
-
         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
                 writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus);
@@ -3750,7 +3613,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
                 writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
         }
         pci_push(base);
-        dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
         if (!(events & NVREG_IRQ_TIMER))
                 return IRQ_RETVAL(0);
 
@@ -3760,8 +3622,6 @@ static irqreturn_t nv_nic_irq_test(int foo, void *data)
         np->intr_test = 1;
         spin_unlock(&np->lock);
 
-        dprintk(KERN_DEBUG "%s: nv_nic_irq_test completed\n", dev->name);
-
         return IRQ_RETVAL(1);
 }
 
@@ -3776,17 +3636,15 @@ static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
          * the remaining 8 interrupts.
          */
         for (i = 0; i < 8; i++) {
-                if ((irqmask >> i) & 0x1) {
+                if ((irqmask >> i) & 0x1)
                         msixmap |= vector << (i << 2);
-                }
         }
         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
 
         msixmap = 0;
         for (i = 0; i < 8; i++) {
-                if ((irqmask >> (i + 8)) & 0x1) {
+                if ((irqmask >> (i + 8)) & 0x1)
                         msixmap |= vector << (i << 2);
-                }
         }
         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
 }
@@ -3809,17 +3667,19 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
         }
 
         if (np->msi_flags & NV_MSI_X_CAPABLE) {
-                for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
+                for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
                         np->msi_x_entry[i].entry = i;
-                }
-                if ((ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK))) == 0) {
+                ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
+                if (ret == 0) {
                         np->msi_flags |= NV_MSI_X_ENABLED;
                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
                                 /* Request irq for rx handling */
                                 sprintf(np->name_rx, "%s-rx", dev->name);
                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
-                                        printk(KERN_INFO "forcedeth: request_irq failed for rx %d\n", ret);
+                                        netdev_info(dev,
+                                                    "request_irq failed for rx %d\n",
+                                                    ret);
                                         pci_disable_msix(np->pci_dev);
                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
                                         goto out_err;
@@ -3828,7 +3688,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
                                 sprintf(np->name_tx, "%s-tx", dev->name);
                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
-                                        printk(KERN_INFO "forcedeth: request_irq failed for tx %d\n", ret);
+                                        netdev_info(dev,
+                                                    "request_irq failed for tx %d\n",
+                                                    ret);
                                         pci_disable_msix(np->pci_dev);
                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
                                         goto out_free_rx;
@@ -3837,7 +3699,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
                                 sprintf(np->name_other, "%s-other", dev->name);
                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
-                                        printk(KERN_INFO "forcedeth: request_irq failed for link %d\n", ret);
+                                        netdev_info(dev,
+                                                    "request_irq failed for link %d\n",
+                                                    ret);
                                         pci_disable_msix(np->pci_dev);
                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
                                         goto out_free_tx;
@@ -3851,7 +3715,9 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
                         } else {
                                 /* Request irq for all interrupts */
                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
-                                        printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
+                                        netdev_info(dev,
+                                                    "request_irq failed %d\n",
+                                                    ret);
                                         pci_disable_msix(np->pci_dev);
                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
                                         goto out_err;
@@ -3864,11 +3730,13 @@ static int nv_request_irq(struct net_device *dev, int intr_test)
                 }
         }
         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
-                if ((ret = pci_enable_msi(np->pci_dev)) == 0) {
+                ret = pci_enable_msi(np->pci_dev);
+                if (ret == 0) {
                         np->msi_flags |= NV_MSI_ENABLED;
                         dev->irq = np->pci_dev->irq;
                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
-                                printk(KERN_INFO "forcedeth: request_irq failed %d\n", ret);
+                                netdev_info(dev, "request_irq failed %d\n",
+                                            ret);
                                 pci_disable_msi(np->pci_dev);
                                 np->msi_flags &= ~NV_MSI_ENABLED;
                                 dev->irq = np->pci_dev->irq;
@@ -3903,9 +3771,8 @@ static void nv_free_irq(struct net_device *dev)
         int i;
 
         if (np->msi_flags & NV_MSI_X_ENABLED) {
-                for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++) {
+                for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
                         free_irq(np->msi_x_entry[i].vector, dev);
-                }
                 pci_disable_msix(np->pci_dev);
                 np->msi_flags &= ~NV_MSI_X_ENABLED;
         } else {
@@ -3954,7 +3821,7 @@ static void nv_do_nic_poll(unsigned long data)
 
         if (np->recover_error) {
                 np->recover_error = 0;
-                printk(KERN_INFO "%s: MAC in recoverable error state\n", dev->name);
+                netdev_info(dev, "MAC in recoverable error state\n");
                 if (netif_running(dev)) {
                         netif_tx_lock_bh(dev);
                         netif_addr_lock(dev);
@@ -3975,7 +3842,7 @@ static void nv_do_nic_poll(unsigned long data)
                         /* reinit nic view of the rx queue */
                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
-                        writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
+                        writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
                                 base + NvRegRingSizes);
                         pci_push(base);
                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -4082,6 +3949,7 @@ static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
                 writel(flags, base + NvRegWakeUpFlags);
                 spin_unlock_irq(&np->lock);
         }
+        device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
         return 0;
 }
 
@@ -4105,7 +3973,7 @@ static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         }
 
         if (netif_carrier_ok(dev)) {
-                switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
+                switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
                 case NVREG_LINKSPEED_10:
                         ecmd->speed = SPEED_10;
                         break;
@@ -4250,14 +4118,14 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                 }
 
                 if (netif_running(dev))
-                        printk(KERN_INFO "%s: link down.\n", dev->name);
+                        netdev_info(dev, "link down\n");
                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
                         bmcr |= BMCR_ANENABLE;
                         /* reset the phy in order for settings to stick,
                          * and cause autoneg to start */
                         if (phy_reset(dev, bmcr)) {
-                                printk(KERN_INFO "%s: phy reset failed\n", dev->name);
+                                netdev_info(dev, "phy reset failed\n");
                                 return -EINVAL;
                         }
                 } else {
@@ -4306,7 +4174,7 @@ static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                 if (np->phy_oui == PHY_OUI_MARVELL) {
                         /* reset the phy in order for forced mode settings to stick */
                         if (phy_reset(dev, bmcr)) {
-                                printk(KERN_INFO "%s: phy reset failed\n", dev->name);
+                                netdev_info(dev, "phy reset failed\n");
                                 return -EINVAL;
                         }
                 } else {
@@ -4344,7 +4212,7 @@ static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void
 
         regs->version = FORCEDETH_REGS_VER;
         spin_lock_irq(&np->lock);
-        for (i = 0;i <= np->register_size/sizeof(u32); i++)
+        for (i = 0; i <= np->register_size/sizeof(u32); i++)
                 rbuf[i] = readl(base + i*sizeof(u32));
         spin_unlock_irq(&np->lock);
 }
@@ -4368,7 +4236,7 @@ static int nv_nway_reset(struct net_device *dev)
                         spin_unlock(&np->lock);
                         netif_addr_unlock(dev);
                         netif_tx_unlock_bh(dev);
-                        printk(KERN_INFO "%s: link down.\n", dev->name);
+                        netdev_info(dev, "link down\n");
                 }
 
                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
@@ -4376,7 +4244,7 @@ static int nv_nway_reset(struct net_device *dev)
                         bmcr |= BMCR_ANENABLE;
                         /* reset the phy in order for settings to stick*/
                         if (phy_reset(dev, bmcr)) {
-                                printk(KERN_INFO "%s: phy reset failed\n", dev->name);
+                                netdev_info(dev, "phy reset failed\n");
                                 return -EINVAL;
                         }
                 } else {
@@ -4464,10 +4332,9 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
                                                     rxtx_ring, ring_addr);
                 }
-                if (rx_skbuff)
-                        kfree(rx_skbuff);
-                if (tx_skbuff)
-                        kfree(tx_skbuff);
+
+                kfree(rx_skbuff);
+                kfree(tx_skbuff);
                 goto exit;
         }
 
@@ -4491,14 +4358,14 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
         np->tx_ring_size = ring->tx_pending;
 
         if (!nv_optimized(np)) {
-                np->rx_ring.orig = (struct ring_desc*)rxtx_ring;
+                np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
         } else {
-                np->rx_ring.ex = (struct ring_desc_ex*)rxtx_ring;
+                np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
         }
-        np->rx_skb = (struct nv_skb_map*)rx_skbuff;
-        np->tx_skb = (struct nv_skb_map*)tx_skbuff;
+        np->rx_skb = (struct nv_skb_map *)rx_skbuff;
+        np->tx_skb = (struct nv_skb_map *)tx_skbuff;
         np->ring_addr = ring_addr;
 
         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
@@ -4515,7 +4382,7 @@ static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ri
                 /* reinit nic view of the queues */
                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
-                writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
+                writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
                         base + NvRegRingSizes);
                 pci_push(base);
                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -4550,12 +4417,11 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
 
         if ((!np->autoneg && np->duplex == 0) ||
             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
-                printk(KERN_INFO "%s: can not set pause settings when forced link is in half duplex.\n",
-                       dev->name);
+                netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
                 return -EINVAL;
         }
         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
-                printk(KERN_INFO "%s: hardware does not support tx pause frames.\n", dev->name);
+                netdev_info(dev, "hardware does not support tx pause frames\n");
                 return -EINVAL;
         }
 
@@ -4590,7 +4456,7 @@ static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam*
                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
 
                 if (netif_running(dev))
-                        printk(KERN_INFO "%s: link down.\n", dev->name);
+                        netdev_info(dev, "link down\n");
                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
@@ -4841,7 +4707,7 @@ static int nv_loopback_test(struct net_device *dev)
         /* reinit nic view of the rx queue */
         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
-        writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
+        writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
                 base + NvRegRingSizes);
         pci_push(base);
 
@@ -4852,8 +4718,7 @@ static int nv_loopback_test(struct net_device *dev)
         pkt_len = ETH_DATA_LEN;
         tx_skb = dev_alloc_skb(pkt_len);
         if (!tx_skb) {
-                printk(KERN_ERR "dev_alloc_skb() failed during loopback test"
-                         " of %s\n", dev->name);
+                netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
                 ret = 0;
                 goto out;
         }
@@ -4893,29 +4758,22 @@ static int nv_loopback_test(struct net_device *dev)
                 if (flags & NV_RX_ERROR)
                         ret = 0;
         } else {
-                if (flags & NV_RX2_ERROR) {
+                if (flags & NV_RX2_ERROR)
                         ret = 0;
-                }
         }
 
         if (ret) {
                 if (len != pkt_len) {
                         ret = 0;
-                        dprintk(KERN_DEBUG "%s: loopback len mismatch %d vs %d\n",
-                                dev->name, len, pkt_len);
                 } else {
                         rx_skb = np->rx_skb[0].skb;
                         for (i = 0; i < pkt_len; i++) {
                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
                                         ret = 0;
-                                        dprintk(KERN_DEBUG "%s: loopback pattern check failed on byte %d\n",
-                                                dev->name, i);
                                         break;
                                 }
                         }
                 }
-        } else {
-                dprintk(KERN_DEBUG "%s: loopback - did not receive test packet\n", dev->name);
         }
 
         pci_unmap_single(np->pci_dev, test_dma_addr,
@@ -4958,11 +4816,10 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
                         netif_addr_lock(dev);
                         spin_lock_irq(&np->lock);
                         nv_disable_hw_interrupts(dev, np->irqmask);
-                        if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
+                        if (!(np->msi_flags & NV_MSI_X_ENABLED))
                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
-                        } else {
+                        else
                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
-                        }
                         /* stop engines */
                         nv_stop_rxtx(dev);
                         nv_txrx_reset(dev);
@@ -5003,7 +4860,7 @@ static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64
                         /* reinit nic view of the rx queue */
                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
-                        writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
+                        writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
                                 base + NvRegRingSizes);
                         pci_push(base);
                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
@@ -5106,8 +4963,7 @@ static int nv_mgmt_acquire_sema(struct net_device *dev)
                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
                         np->mgmt_sema = 1;
                         return 1;
-                }
-                else
+                } else
                         udelay(50);
         }
 
@@ -5167,8 +5023,6 @@ static int nv_open(struct net_device *dev)
         int oom, i;
         u32 low;
 
-        dprintk(KERN_DEBUG "nv_open: begin\n");
-
         /* power up phy */
         mii_rw(dev, np->phyaddr, MII_BMCR,
                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
@@ -5204,7 +5058,7 @@ static int nv_open(struct net_device *dev)
 
         /* give hw rings */
         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
-        writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
+        writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
                 base + NvRegRingSizes);
 
         writel(np->linkspeed, base + NvRegLinkSpeed);
@@ -5216,9 +5070,11 @@ static int nv_open(struct net_device *dev)
         writel(np->vlanctl_bits, base + NvRegVlanControl);
         pci_push(base);
         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
-        reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
-                        NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
-                        KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
+        if (reg_delay(dev, NvRegUnknownSetupReg5,
+                      NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
+                      NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
+                netdev_info(dev,
+                            "%s: SetupReg5, Bit 31 remained off\n", __func__);
 
         writel(0, base + NvRegMIIMask);
         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
@@ -5251,8 +5107,7 @@ static int nv_open(struct net_device *dev)
                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
                 else
                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
-        }
-        else
+        } else
                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
@@ -5263,7 +5118,7 @@ static int nv_open(struct net_device *dev)
                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
 
         i = readl(base + NvRegPowerState);
-        if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
+        if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
 
         pci_push(base);
@@ -5276,9 +5131,8 @@ static int nv_open(struct net_device *dev)
         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
         pci_push(base);
 
-        if (nv_request_irq(dev, 0)) {
+        if (nv_request_irq(dev, 0))
                 goto out_drain;
-        }
 
         /* ask for interrupts */
         nv_enable_hw_interrupts(dev, np->irqmask);
@@ -5296,7 +5150,6 @@ static int nv_open(struct net_device *dev)
                 u32 miistat;
                 miistat = readl(base + NvRegMIIStatus);
                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
-                dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
         }
         /* set linkspeed to invalid value, thus force nv_update_linkspeed
          * to init hw */
@@ -5309,7 +5162,7 @@ static int nv_open(struct net_device *dev)
         if (ret) {
                 netif_carrier_on(dev);
         } else {
-                printk(KERN_INFO "%s: no link during initialization.\n", dev->name);
+                netdev_info(dev, "no link during initialization\n");
                 netif_carrier_off(dev);
         }
         if (oom)
@@ -5352,7 +5205,6 @@ static int nv_close(struct net_device *dev)
         base = get_hwbase(dev);
         nv_disable_hw_interrupts(dev, np->irqmask);
         pci_push(base);
-        dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
 
         spin_unlock_irq(&np->lock);
 
@@ -5421,8 +5273,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
         static int printed_version;
 
         if (!printed_version++)
-                printk(KERN_INFO "%s: Reverse Engineered nForce ethernet"
-                       " driver. Version %s.\n", DRV_NAME, FORCEDETH_VERSION);
+                pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
+                        FORCEDETH_VERSION);
 
         dev = alloc_etherdev(sizeof(struct fe_priv));
         err = -ENOMEM;
@@ -5465,10 +5317,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
         err = -EINVAL;
         addr = 0;
         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
-                dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
-                                pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
-                                pci_resource_len(pci_dev, i),
-                                pci_resource_flags(pci_dev, i));
                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
                                 pci_resource_len(pci_dev, i) >= np->register_size) {
                         addr = pci_resource_start(pci_dev, i);
@@ -5476,8 +5324,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                 }
         }
         if (i == DEVICE_COUNT_RESOURCE) {
-                dev_printk(KERN_INFO, &pci_dev->dev,
-                           "Couldn't find register window\n");
+                dev_info(&pci_dev->dev, "Couldn't find register window\n");
                 goto out_relreg;
         }
 
@@ -5493,13 +5340,13 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
                 if (dma_64bit) {
                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
-                                dev_printk(KERN_INFO, &pci_dev->dev,
-                                        "64-bit DMA failed, using 32-bit addressing\n");
+                                dev_info(&pci_dev->dev,
+                                         "64-bit DMA failed, using 32-bit addressing\n");
                         else
                                 dev->features |= NETIF_F_HIGHDMA;
                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
-                                dev_printk(KERN_INFO, &pci_dev->dev,
-                                        "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
+                                dev_info(&pci_dev->dev,
+                                         "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
                         }
                 }
         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
@@ -5620,7 +5467,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
-                printk(KERN_DEBUG "nv_probe: set workaround bit for reversed mac addr\n");
+                dev_dbg(&pci_dev->dev,
+                        "%s: set workaround bit for reversed mac addr\n",
+                        __func__);
         }
         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
 
@@ -5629,28 +5478,21 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                  * Bad mac address. At least one bios sets the mac address
                  * to 01:23:45:67:89:ab
                  */
-                dev_printk(KERN_ERR, &pci_dev->dev,
-                        "Invalid Mac address detected: %pM\n",
-                        dev->dev_addr);
-                dev_printk(KERN_ERR, &pci_dev->dev,
-                        "Please complain to your hardware vendor. Switching to a random MAC.\n");
+                dev_err(&pci_dev->dev,
+                        "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
+                        dev->dev_addr);
                 random_ether_addr(dev->dev_addr);
+                dev_err(&pci_dev->dev,
+                        "Using random MAC address: %pM\n", dev->dev_addr);
         }
 
-        dprintk(KERN_DEBUG "%s: MAC Address %pM\n",
-                pci_name(pci_dev), dev->dev_addr);
-
         /* set mac address */
         nv_copy_mac_to_hw(dev);
 
-        /* Workaround current PCI init glitch:  wakeup bits aren't
-         * being set from PCI PM capability.
-         */
-        device_init_wakeup(&pci_dev->dev, 1);
-
         /* disable WOL */
         writel(0, base + NvRegWakeUpFlags);
         np->wolenabled = 0;
+        device_set_wakeup_enable(&pci_dev->dev, false);
 
         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
 
@@ -5663,16 +5505,15 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                 writel(powerstate, base + NvRegPowerState2);
         }
 
-        if (np->desc_ver == DESC_VER_1) {
+        if (np->desc_ver == DESC_VER_1)
                 np->tx_flags = NV_TX_VALID;
-        } else {
+        else
                 np->tx_flags = NV_TX2_VALID;
-        }
 
         np->msi_flags = 0;
-        if ((id->driver_data & DEV_HAS_MSI) && msi) {
+        if ((id->driver_data & DEV_HAS_MSI) && msi)
                 np->msi_flags |= NV_MSI_CAPABLE;
-        }
+
         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
                 /* msix has had reported issues when modifying irqmask
                    as in the case of napi, therefore, disable for now
@@ -5702,11 +5543,9 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
         if (id->driver_data & DEV_NEED_TIMERIRQ)
                 np->irqmask |= NVREG_IRQ_TIMER;
         if (id->driver_data & DEV_NEED_LINKTIMER) {
-                dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
                 np->need_linktimer = 1;
                 np->link_timeout = jiffies + LINK_TIMEOUT;
         } else {
-                dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
                 np->need_linktimer = 0;
         }
 
@@ -5735,19 +5574,14 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                     nv_mgmt_acquire_sema(dev) &&
                     nv_mgmt_get_version(dev)) {
                         np->mac_in_use = 1;
-                        if (np->mgmt_version > 0) {
+                        if (np->mgmt_version > 0)
                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
-                        }
-                        dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n",
-                                pci_name(pci_dev), np->mac_in_use);
                         /* management unit setup the phy already? */
                         if (np->mac_in_use &&
                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
                                 /* phy is inited by mgmt unit */
                                 phyinitialized = 1;
-                                dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n",
-                                        pci_name(pci_dev));
                         } else {
                                 /* we need to init the phy */
                         }
@@ -5773,8 +5607,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                 np->phy_model = id2 & PHYID2_MODEL_MASK;
                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
-                dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
-                        pci_name(pci_dev), id1, id2, phyaddr);
                 np->phyaddr = phyaddr;
                 np->phy_oui = id1 | id2;
 
@@ -5788,8 +5620,7 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
                 break;
         }
         if (i == 33) {
-                dev_printk(KERN_INFO, &pci_dev->dev,
-                        "open: Could not find a valid PHY.\n");
+                dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
                 goto out_error;
         }
 
@@ -5799,9 +5630,8 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
         } else {
                 /* see if it is a gigabit phy */
                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
-                if (mii_status & PHY_GIGABIT) {
+                if (mii_status & PHY_GIGABIT)
                         np->gigabit = PHY_GIGABIT;
-                }
         }
 
         /* set default link speed settings */
@@ -5811,37 +5641,27 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
 
         err = register_netdev(dev);
         if (err) {
-                dev_printk(KERN_INFO, &pci_dev->dev,
-                           "unable to register netdev: %d\n", err);
+                dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
                 goto out_error;
         }
 
-        dev_printk(KERN_INFO, &pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, "
-                   "addr %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
-                   dev->name,
-                   np->phy_oui,
-                   np->phyaddr,
-                   dev->dev_addr[0],
-                   dev->dev_addr[1],
-                   dev->dev_addr[2],
-                   dev->dev_addr[3],
-                   dev->dev_addr[4],
-                   dev->dev_addr[5]);
-
-        dev_printk(KERN_INFO, &pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
-                   dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
-                   dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
-                        "csum " : "",
-                   dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
-                        "vlan " : "",
-                   id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
-                   id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
-                   id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
-                   np->gigabit == PHY_GIGABIT ? "gbit " : "",
-                   np->need_linktimer ? "lnktim " : "",
-                   np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
-                   np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
-                   np->desc_ver);
+        dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
+                 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
+
+        dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
+                 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
+                 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
+                        "csum " : "",
+                 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
+                        "vlan " : "",
+                 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
+                 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
+                 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
+                 np->gigabit == PHY_GIGABIT ? "gbit " : "",
+                 np->need_linktimer ? "lnktim " : "",
+                 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
+                 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
+                 np->desc_ver);
 
         return 0;
 
@@ -5923,44 +5743,37 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
 }
 
 #ifdef CONFIG_PM
-static int nv_suspend(struct pci_dev *pdev, pm_message_t state)
+static int nv_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct net_device *dev = pci_get_drvdata(pdev);
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
         int i;
 
         if (netif_running(dev)) {
-                // Gross.
+                /* Gross. */
                 nv_close(dev);
         }
         netif_device_detach(dev);
 
         /* save non-pci configuration space */
-        for (i = 0;i <= np->register_size/sizeof(u32); i++)
+        for (i = 0; i <= np->register_size/sizeof(u32); i++)
                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
 
-        pci_save_state(pdev);
-        pci_enable_wake(pdev, pci_choose_state(pdev, state), np->wolenabled);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, pci_choose_state(pdev, state));
         return 0;
 }
 
-static int nv_resume(struct pci_dev *pdev)
+static int nv_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct net_device *dev = pci_get_drvdata(pdev);
         struct fe_priv *np = netdev_priv(dev);
         u8 __iomem *base = get_hwbase(dev);
         int i, rc = 0;
 
-        pci_set_power_state(pdev, PCI_D0);
-        pci_restore_state(pdev);
-        /* ack any pending wake events, disable PME */
-        pci_enable_wake(pdev, PCI_D0, 0);
-
         /* restore non-pci configuration space */
-        for (i = 0;i <= np->register_size/sizeof(u32); i++)
+        for (i = 0; i <= np->register_size/sizeof(u32); i++)
                 writel(np->saved_config_space[i], base+i*sizeof(u32));
 
         if (np->driver_data & DEV_NEED_MSI_FIX)
@@ -5977,6 +5790,9 @@ static int nv_resume(struct pci_dev *pdev)
         return rc;
 }
 
+static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
+#define NV_PM_OPS (&nv_pm_ops)
+
 static void nv_shutdown(struct pci_dev *pdev)
 {
         struct net_device *dev = pci_get_drvdata(pdev);
@@ -5990,9 +5806,8 @@ static void nv_shutdown(struct pci_dev *pdev)
          * If we really go for poweroff, we must not restore the MAC,
          * otherwise the MAC for WOL will be reversed at least on some boards.
          */
-        if (system_state != SYSTEM_POWER_OFF) {
+        if (system_state != SYSTEM_POWER_OFF)
                 nv_restore_mac_addr(pdev);
-        }
 
         pci_disable_device(pdev);
         /*
@@ -6000,15 +5815,13 @@ static void nv_shutdown(struct pci_dev *pdev)
          * only put the device into D3 if we really go for poweroff.
          */
         if (system_state == SYSTEM_POWER_OFF) {
-                if (pci_enable_wake(pdev, PCI_D3cold, np->wolenabled))
-                        pci_enable_wake(pdev, PCI_D3hot, np->wolenabled);
+                pci_wake_from_d3(pdev, np->wolenabled);
                 pci_set_power_state(pdev, PCI_D3hot);
         }
 }
 #else
-#define nv_suspend NULL
+#define NV_PM_OPS NULL
 #define nv_shutdown NULL
-#define nv_resume NULL
 #endif /* CONFIG_PM */
 
 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
@@ -6180,9 +5993,8 @@ static struct pci_driver driver = {
         .id_table       = pci_tbl,
         .probe          = nv_probe,
         .remove         = __devexit_p(nv_remove),
-        .suspend        = nv_suspend,
-        .resume         = nv_resume,
         .shutdown       = nv_shutdown,
+        .driver.pm      = NV_PM_OPS,
 };
 
 static int __init init_nic(void)
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index d684f187de57..7a1f3d0ffa78 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -40,6 +40,7 @@
 #include <linux/of_mdio.h>
 #include <linux/of_platform.h>
 #include <linux/of_gpio.h>
+#include <linux/of_net.h>
 
 #include <linux/vmalloc.h>
 #include <asm/pgtable.h>
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index d1bec6269173..6de4675016b5 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -95,6 +95,7 @@
 #include <linux/phy.h>
 #include <linux/phy_fixed.h>
 #include <linux/of.h>
+#include <linux/of_net.h>
 
 #include "gianfar.h"
 #include "fsl_pq_mdio.h"
@@ -143,7 +144,8 @@ void gfar_halt(struct net_device *dev);
 static void gfar_halt_nodisable(struct net_device *dev);
 void gfar_start(struct net_device *dev);
 static void gfar_clear_exact_match(struct net_device *dev);
-static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
+static void gfar_set_mac_for_addr(struct net_device *dev, int num,
+                                  const u8 *addr);
 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 
 MODULE_AUTHOR("Freescale Semiconductor, Inc");
@@ -3094,10 +3096,10 @@ static void gfar_set_multi(struct net_device *dev)
 static void gfar_clear_exact_match(struct net_device *dev)
 {
         int idx;
-        u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
+        static const u8 zero_arr[MAC_ADDR_LEN] = {0, 0, 0, 0, 0, 0};
 
         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
-                gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
+                gfar_set_mac_for_addr(dev, idx, zero_arr);
 }
 
 /* Set the appropriate hash bit for the given addr */
@@ -3132,7 +3134,8 @@ static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
 /* There are multiple MAC Address register pairs on some controllers
  * This function sets the numth pair to a given address
  */
-static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
+static void gfar_set_mac_for_addr(struct net_device *dev, int num,
+                                  const u8 *addr)
 {
         struct gfar_private *priv = netdev_priv(dev);
         struct gfar __iomem *regs = priv->gfargrp[0].regs;
diff --git a/drivers/net/hamachi.c b/drivers/net/hamachi.c
index 9a6485892b3d..80d25ed53344 100644
--- a/drivers/net/hamachi.c
+++ b/drivers/net/hamachi.c
@@ -1202,7 +1202,7 @@ static void hamachi_init_ring(struct net_device *dev)
         }
         /* Fill in the Rx buffers.  Handle allocation failure gracefully. */
         for (i = 0; i < RX_RING_SIZE; i++) {
-                struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
+                struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz + 2);
                 hmp->rx_skbuff[i] = skb;
                 if (skb == NULL)
                         break;
@@ -1669,7 +1669,7 @@ static int hamachi_rx(struct net_device *dev)
                 entry = hmp->dirty_rx % RX_RING_SIZE;
                 desc = &(hmp->rx_ring[entry]);
                 if (hmp->rx_skbuff[entry] == NULL) {
-                        struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz);
+                        struct sk_buff *skb = dev_alloc_skb(hmp->rx_buf_sz + 2);
 
                         hmp->rx_skbuff[entry] = skb;
                         if (skb == NULL)
diff --git a/drivers/net/hamradio/yam.c b/drivers/net/hamradio/yam.c
index 4e7d1d0a2340..7d9ced0738c5 100644
--- a/drivers/net/hamradio/yam.c
+++ b/drivers/net/hamradio/yam.c
@@ -396,7 +396,7 @@ static unsigned char *add_mcs(unsigned char *bits, int bitrate,
         while (p) {
                 if (p->bitrate == bitrate) {
                         memcpy(p->bits, bits, YAM_FPGA_SIZE);
-                        return p->bits;
+                        goto out;
                 }
                 p = p->next;
         }
@@ -411,7 +411,7 @@ static unsigned char *add_mcs(unsigned char *bits, int bitrate,
         p->bitrate = bitrate;
         p->next = yam_data;
         yam_data = p;
-
+ out:
         release_firmware(fw);
         return p->bits;
 }
diff --git a/drivers/net/hp.c b/drivers/net/hp.c
index d15d2f2ba78e..ef2014375e62 100644
--- a/drivers/net/hp.c
+++ b/drivers/net/hp.c
@@ -162,9 +162,9 @@ static int __init hp_probe1(struct net_device *dev, int ioaddr)
 
         /* Snarf the interrupt now.  Someday this could be moved to open(). */
         if (dev->irq < 2) {
-                int irq_16list[] = { 11, 10, 5, 3, 4, 7, 9, 0};
-                int irq_8list[] = { 7, 5, 3, 4, 9, 0};
-                int *irqp = wordmode ? irq_16list : irq_8list;
+                static const int irq_16list[] = { 11, 10, 5, 3, 4, 7, 9, 0};
+                static const int irq_8list[] = { 7, 5, 3, 4, 9, 0};
+                const int *irqp = wordmode ? irq_16list : irq_8list;
                 do {
                         int irq = *irqp;
                         if (request_irq (irq, NULL, 0, "bogus", NULL) != -EBUSY) {
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c
index 06bb9b799458..6d9275c52e05 100644
--- a/drivers/net/ibm_newemac/core.c
+++ b/drivers/net/ibm_newemac/core.c
@@ -1279,7 +1279,7 @@ static void emac_force_link_update(struct emac_instance *dev)
         netif_carrier_off(dev->ndev);
         smp_rmb();
         if (dev->link_polling) {
-                cancel_rearming_delayed_work(&dev->link_work);
+                cancel_delayed_work_sync(&dev->link_work);
                 if (dev->link_polling)
                         schedule_delayed_work(&dev->link_work,  PHY_POLL_LINK_OFF);
         }
@@ -1294,7 +1294,7 @@ static int emac_close(struct net_device *ndev)
 
         if (dev->phy.address >= 0) {
                 dev->link_polling = 0;
-                cancel_rearming_delayed_work(&dev->link_work);
+                cancel_delayed_work_sync(&dev->link_work);
         }
         mutex_lock(&dev->link_lock);
         emac_netif_stop(dev);
@@ -2950,7 +2950,7 @@ static int __devexit emac_remove(struct platform_device *ofdev)
 
         unregister_netdev(dev->ndev);
 
-        flush_scheduled_work();
+        cancel_work_sync(&dev->reset_work);
 
         if (emac_has_feature(dev, EMAC_FTR_HAS_TAH))
                 tah_detach(dev->tah_dev, dev->tah_port);
diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c
index c454b45ca7ec..5522d459654c 100644
--- a/drivers/net/ibmveth.c
+++ b/drivers/net/ibmveth.c
@@ -729,11 +729,6 @@ static void netdev_get_drvinfo(struct net_device *dev,
                 sizeof(info->version) - 1);
 }
 
-static u32 netdev_get_link(struct net_device *dev)
-{
-        return 1;
-}
-
 static void ibmveth_set_rx_csum_flags(struct net_device *dev, u32 data)
 {
         struct ibmveth_adapter *adapter = netdev_priv(dev);
@@ -918,7 +913,7 @@ static void ibmveth_get_ethtool_stats(struct net_device *dev,
 static const struct ethtool_ops netdev_ethtool_ops = {
         .get_drvinfo            = netdev_get_drvinfo,
         .get_settings           = netdev_get_settings,
-        .get_link               = netdev_get_link,
+        .get_link               = ethtool_op_get_link,
         .set_tx_csum            = ibmveth_set_tx_csum,
         .get_rx_csum            = ibmveth_get_rx_csum,
         .set_rx_csum            = ibmveth_set_rx_csum,
diff --git a/drivers/net/ifb.c b/drivers/net/ifb.c
index fe337bd121aa..e07d487f015a 100644
--- a/drivers/net/ifb.c
+++ b/drivers/net/ifb.c
@@ -36,22 +36,10 @@
 #include <net/pkt_sched.h>
 #include <net/net_namespace.h>
 
-#define TX_TIMEOUT  (2*HZ)
-
 #define TX_Q_LIMIT    32
 struct ifb_private {
         struct tasklet_struct   ifb_tasklet;
         int     tasklet_pending;
-        /* mostly debug stats leave in for now */
-        unsigned long   st_task_enter; /* tasklet entered */
-        unsigned long   st_txq_refl_try; /* transmit queue refill attempt */
-        unsigned long   st_rxq_enter; /* receive queue entered */
-        unsigned long   st_rx2tx_tran; /* receive to trasmit transfers */
-        unsigned long   st_rxq_notenter; /*receiveQ not entered, resched */
-        unsigned long   st_rx_frm_egr; /* received from egress path */
-        unsigned long   st_rx_frm_ing; /* received from ingress path */
-        unsigned long   st_rxq_check;
-        unsigned long   st_rxq_rsch;
         struct sk_buff_head     rq;
         struct sk_buff_head     tq;
 };
@@ -73,24 +61,17 @@ static void ri_tasklet(unsigned long dev)
         struct sk_buff *skb;
 
         txq = netdev_get_tx_queue(_dev, 0);
-        dp->st_task_enter++;
         if ((skb = skb_peek(&dp->tq)) == NULL) {
-                dp->st_txq_refl_try++;
                 if (__netif_tx_trylock(txq)) {
-                        dp->st_rxq_enter++;
-                        while ((skb = skb_dequeue(&dp->rq)) != NULL) {
-                                skb_queue_tail(&dp->tq, skb);
-                                dp->st_rx2tx_tran++;
-                        }
+                        skb_queue_splice_tail_init(&dp->rq, &dp->tq);
                         __netif_tx_unlock(txq);
                 } else {
                         /* reschedule */
-                        dp->st_rxq_notenter++;
                         goto resched;
                 }
         }
 
-        while ((skb = skb_dequeue(&dp->tq)) != NULL) {
+        while ((skb = __skb_dequeue(&dp->tq)) != NULL) {
                 u32 from = G_TC_FROM(skb->tc_verd);
 
                 skb->tc_verd = 0;
@@ -112,24 +93,20 @@ static void ri_tasklet(unsigned long dev)
                 skb->skb_iif = _dev->ifindex;
 
                 if (from & AT_EGRESS) {
-                        dp->st_rx_frm_egr++;
                         dev_queue_xmit(skb);
                 } else if (from & AT_INGRESS) {
-                        dp->st_rx_frm_ing++;
                         skb_pull(skb, skb->dev->hard_header_len);
-                        netif_rx(skb);
+                        netif_receive_skb(skb);
                 } else
                         BUG();
         }
 
         if (__netif_tx_trylock(txq)) {
-                dp->st_rxq_check++;
                 if ((skb = skb_peek(&dp->rq)) == NULL) {
                         dp->tasklet_pending = 0;
                         if (netif_queue_stopped(_dev))
                                 netif_wake_queue(_dev);
                 } else {
-                        dp->st_rxq_rsch++;
                         __netif_tx_unlock(txq);
                         goto resched;
                 }
@@ -149,6 +126,10 @@ static const struct net_device_ops ifb_netdev_ops = {
         .ndo_validate_addr = eth_validate_addr,
 };
 
+#define IFB_FEATURES (NETIF_F_NO_CSUM | NETIF_F_SG  | NETIF_F_FRAGLIST  | \
+                      NETIF_F_TSO_ECN | NETIF_F_TSO | NETIF_F_TSO6      | \
+                      NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_TX)
+
 static void ifb_setup(struct net_device *dev)
 {
         /* Initialize the device structure. */
@@ -159,6 +140,9 @@ static void ifb_setup(struct net_device *dev)
         ether_setup(dev);
         dev->tx_queue_len = TX_Q_LIMIT;
 
+        dev->features |= IFB_FEATURES;
+        dev->vlan_features |= IFB_FEATURES;
+
         dev->flags |= IFF_NOARP;
         dev->flags &= ~IFF_MULTICAST;
         dev->priv_flags &= ~IFF_XMIT_DST_RELEASE;
@@ -184,7 +168,7 @@ static netdev_tx_t ifb_xmit(struct sk_buff *skb, struct net_device *dev)
                 netif_stop_queue(dev);
         }
 
-        skb_queue_tail(&dp->rq, skb);
+        __skb_queue_tail(&dp->rq, skb);
         if (!dp->tasklet_pending) {
                 dp->tasklet_pending = 1;
                 tasklet_schedule(&dp->ifb_tasklet);
@@ -199,8 +183,8 @@ static int ifb_close(struct net_device *dev)
 
         tasklet_kill(&dp->ifb_tasklet);
         netif_stop_queue(dev);
-        skb_queue_purge(&dp->rq);
-        skb_queue_purge(&dp->tq);
+        __skb_queue_purge(&dp->rq);
+        __skb_queue_purge(&dp->tq);
         return 0;
 }
 
@@ -209,8 +193,8 @@ static int ifb_open(struct net_device *dev)
         struct ifb_private *dp = netdev_priv(dev);
 
         tasklet_init(&dp->ifb_tasklet, ri_tasklet, (unsigned long)dev);
-        skb_queue_head_init(&dp->rq);
-        skb_queue_head_init(&dp->tq);
+        __skb_queue_head_init(&dp->rq);
+        __skb_queue_head_init(&dp->tq);
         netif_start_queue(dev);
 
         return 0;
diff --git a/drivers/net/igb/e1000_82575.c b/drivers/net/igb/e1000_82575.c
index bc183f5487cb..0a2368fa6bc6 100644
--- a/drivers/net/igb/e1000_82575.c
+++ b/drivers/net/igb/e1000_82575.c
@@ -134,6 +134,8 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw)
         case E1000_DEV_ID_82580_COPPER_DUAL:
         case E1000_DEV_ID_DH89XXCC_SGMII:
         case E1000_DEV_ID_DH89XXCC_SERDES:
+        case E1000_DEV_ID_DH89XXCC_BACKPLANE:
+        case E1000_DEV_ID_DH89XXCC_SFP:
                 mac->type = e1000_82580;
                 break;
         case E1000_DEV_ID_I350_COPPER:
@@ -1478,6 +1480,39 @@ out:
 }
 
 /**
+ *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
+ *  @hw: pointer to the hardware struct
+ *  @enable: state to enter, either enabled or disabled
+ *  @pf: Physical Function pool - do not set anti-spoofing for the PF
+ *
+ *  enables/disables L2 switch anti-spoofing functionality.
+ **/
+void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
+{
+        u32 dtxswc;
+
+        switch (hw->mac.type) {
+        case e1000_82576:
+        case e1000_i350:
+                dtxswc = rd32(E1000_DTXSWC);
+                if (enable) {
+                        dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
+                                   E1000_DTXSWC_VLAN_SPOOF_MASK);
+                        /* The PF can spoof - it has to in order to
+                         * support emulation mode NICs */
+                        dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
+                } else {
+                        dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
+                                    E1000_DTXSWC_VLAN_SPOOF_MASK);
+                }
+                wr32(E1000_DTXSWC, dtxswc);
+                break;
+        default:
+                break;
+        }
+}
+
+/**
  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
  *  @hw: pointer to the hardware struct
  *  @enable: state to enter, either enabled or disabled
@@ -1578,7 +1613,7 @@ static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
 {
         s32 ret_val = 0;
         u32 mdicnfg;
-        u16 nvm_data;
+        u16 nvm_data = 0;
 
         if (hw->mac.type != e1000_82580)
                 goto out;
diff --git a/drivers/net/igb/e1000_82575.h b/drivers/net/igb/e1000_82575.h
index cbd1e1259e4d..1d01af2472e7 100644
--- a/drivers/net/igb/e1000_82575.h
+++ b/drivers/net/igb/e1000_82575.h
@@ -194,6 +194,10 @@ struct e1000_adv_tx_context_desc {
 #define E1000_NVM_APME_82575          0x0400
 #define MAX_NUM_VFS                   8
 
+#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
+#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
+#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
+#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
 #define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
 
 /* Easy defines for setting default pool, would normally be left a zero */
@@ -243,6 +247,7 @@ struct e1000_adv_tx_context_desc {
 
 /* RX packet buffer size defines */
 #define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
+void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
 void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
 u16 igb_rxpbs_adjust_82580(u32 data);
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 62222796a8b3..6319ed902bc0 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -419,6 +419,9 @@
 #define E1000_ERR_SWFW_SYNC 13
 #define E1000_NOT_IMPLEMENTED 14
 #define E1000_ERR_MBX      15
+#define E1000_ERR_INVALID_ARGUMENT  16
+#define E1000_ERR_NO_SPACE          17
+#define E1000_ERR_NVM_PBA_SECTION   18
 
 /* Loop limit on how long we wait for auto-negotiation to complete */
 #define COPPER_LINK_UP_LIMIT              10
@@ -580,11 +583,15 @@
 
 /* Mask bits for fields in Word 0x1a of the NVM */
 
+/* length of string needed to store part num */
+#define E1000_PBANUM_LENGTH         11
+
 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 #define NVM_SUM                    0xBABA
 
 #define NVM_PBA_OFFSET_0           8
 #define NVM_PBA_OFFSET_1           9
+#define NVM_PBA_PTR_GUARD          0xFAFA
 #define NVM_WORD_SIZE_BASE_SHIFT   6
 
 /* NVM Commands - Microwire */
diff --git a/drivers/net/igb/e1000_hw.h b/drivers/net/igb/e1000_hw.h
index c0b017f8d782..e2638afb8cdc 100644
--- a/drivers/net/igb/e1000_hw.h
+++ b/drivers/net/igb/e1000_hw.h
@@ -54,8 +54,10 @@ struct e1000_hw;
 #define E1000_DEV_ID_82580_SERDES             0x1510
 #define E1000_DEV_ID_82580_SGMII              0x1511
 #define E1000_DEV_ID_82580_COPPER_DUAL        0x1516
-#define E1000_DEV_ID_DH89XXCC_SGMII           0x0436
-#define E1000_DEV_ID_DH89XXCC_SERDES          0x0438
+#define E1000_DEV_ID_DH89XXCC_SGMII           0x0438
+#define E1000_DEV_ID_DH89XXCC_SERDES          0x043A
+#define E1000_DEV_ID_DH89XXCC_BACKPLANE       0x043C
+#define E1000_DEV_ID_DH89XXCC_SFP             0x0440
 #define E1000_DEV_ID_I350_COPPER              0x1521
 #define E1000_DEV_ID_I350_FIBER               0x1522
 #define E1000_DEV_ID_I350_SERDES              0x1523
diff --git a/drivers/net/igb/e1000_nvm.c b/drivers/net/igb/e1000_nvm.c
index d83b77fa4038..6b5cc2cc453d 100644
--- a/drivers/net/igb/e1000_nvm.c
+++ b/drivers/net/igb/e1000_nvm.c
@@ -445,31 +445,112 @@ out:
 }
 
 /**
- *  igb_read_part_num - Read device part number
+ *  igb_read_part_string - Read device part number
  *  @hw: pointer to the HW structure
  *  @part_num: pointer to device part number
+ *  @part_num_size: size of part number buffer
  *
  *  Reads the product board assembly (PBA) number from the EEPROM and stores
  *  the value in part_num.
  **/
-s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num)
+s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
 {
-        s32  ret_val;
+        s32 ret_val;
         u16 nvm_data;
+        u16 pointer;
+        u16 offset;
+        u16 length;
+
+        if (part_num == NULL) {
+                hw_dbg("PBA string buffer was null\n");
+                ret_val = E1000_ERR_INVALID_ARGUMENT;
+                goto out;
+        }
 
         ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
         if (ret_val) {
                 hw_dbg("NVM Read Error\n");
                 goto out;
         }
-        *part_num = (u32)(nvm_data << 16);
 
-        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
+        ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
+        if (ret_val) {
+                hw_dbg("NVM Read Error\n");
+                goto out;
+        }
+
+        /*
+         * if nvm_data is not ptr guard the PBA must be in legacy format which
+         * means pointer is actually our second data word for the PBA number
+         * and we can decode it into an ascii string
+         */
+        if (nvm_data != NVM_PBA_PTR_GUARD) {
+                hw_dbg("NVM PBA number is not stored as string\n");
+
+                /* we will need 11 characters to store the PBA */
+                if (part_num_size < 11) {
+                        hw_dbg("PBA string buffer too small\n");
+                        return E1000_ERR_NO_SPACE;
+                }
+
+                /* extract hex string from data and pointer */
+                part_num[0] = (nvm_data >> 12) & 0xF;
+                part_num[1] = (nvm_data >> 8) & 0xF;
+                part_num[2] = (nvm_data >> 4) & 0xF;
+                part_num[3] = nvm_data & 0xF;
+                part_num[4] = (pointer >> 12) & 0xF;
+                part_num[5] = (pointer >> 8) & 0xF;
+                part_num[6] = '-';
+                part_num[7] = 0;
+                part_num[8] = (pointer >> 4) & 0xF;
+                part_num[9] = pointer & 0xF;
+
+                /* put a null character on the end of our string */
+                part_num[10] = '\0';
+
+                /* switch all the data but the '-' to hex char */
+                for (offset = 0; offset < 10; offset++) {
+                        if (part_num[offset] < 0xA)
+                                part_num[offset] += '0';
+                        else if (part_num[offset] < 0x10)
+                                part_num[offset] += 'A' - 0xA;
+                }
+
+                goto out;
+        }
+
+        ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
         if (ret_val) {
                 hw_dbg("NVM Read Error\n");
                 goto out;
         }
-        *part_num |= nvm_data;
+
+        if (length == 0xFFFF || length == 0) {
+                hw_dbg("NVM PBA number section invalid length\n");
+                ret_val = E1000_ERR_NVM_PBA_SECTION;
+                goto out;
+        }
+        /* check if part_num buffer is big enough */
+        if (part_num_size < (((u32)length * 2) - 1)) {
+                hw_dbg("PBA string buffer too small\n");
+                ret_val = E1000_ERR_NO_SPACE;
+                goto out;
+        }
+
+        /* trim pba length from start of string */
+        pointer++;
+        length--;
+
+        for (offset = 0; offset < length; offset++) {
+                ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
+                if (ret_val) {
+                        hw_dbg("NVM Read Error\n");
+                        goto out;
+                }
+                part_num[offset * 2] = (u8)(nvm_data >> 8);
+                part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
+        }
+        part_num[offset * 2] = '\0';
 
 out:
         return ret_val;
diff --git a/drivers/net/igb/e1000_nvm.h b/drivers/net/igb/e1000_nvm.h
index 1041c34dcbe1..29c956a84bd0 100644
--- a/drivers/net/igb/e1000_nvm.h
+++ b/drivers/net/igb/e1000_nvm.h
@@ -32,6 +32,8 @@ s32  igb_acquire_nvm(struct e1000_hw *hw);
 void igb_release_nvm(struct e1000_hw *hw);
 s32  igb_read_mac_addr(struct e1000_hw *hw);
 s32  igb_read_part_num(struct e1000_hw *hw, u32 *part_num);
+s32  igb_read_part_string(struct e1000_hw *hw, u8 *part_num,
+                          u32 part_num_size);
 s32  igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 s32  igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
 s32  igb_validate_nvm_checksum(struct e1000_hw *hw);
diff --git a/drivers/net/igb/e1000_phy.c b/drivers/net/igb/e1000_phy.c
index ddd036a78999..6694bf3e5ad9 100644
--- a/drivers/net/igb/e1000_phy.c
+++ b/drivers/net/igb/e1000_phy.c
@@ -1757,11 +1757,12 @@ s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
         u16 phy_data, i, agc_value = 0;
         u16 cur_agc_index, max_agc_index = 0;
         u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
-        u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
-                                                         {IGP02E1000_PHY_AGC_A,
-                                                          IGP02E1000_PHY_AGC_B,
-                                                          IGP02E1000_PHY_AGC_C,
-                                                          IGP02E1000_PHY_AGC_D};
+        static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
+               IGP02E1000_PHY_AGC_A,
+               IGP02E1000_PHY_AGC_B,
+               IGP02E1000_PHY_AGC_C,
+               IGP02E1000_PHY_AGC_D
+        };
 
         /* Read the AGC registers for all channels */
         for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
diff --git a/drivers/net/igb/e1000_regs.h b/drivers/net/igb/e1000_regs.h
index abb7333a1fbf..8ac83c5190d5 100644
--- a/drivers/net/igb/e1000_regs.h
+++ b/drivers/net/igb/e1000_regs.h
@@ -301,6 +301,7 @@
 #define E1000_VFTE      0x00C90 /* VF Transmit Enables */
 #define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
 #define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
+#define E1000_WVBR      0x03554 /* VM Wrong Behavior - RWS */
 #define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
 #define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
 #define E1000_IOVTCL    0x05BBC /* IOV Control Register */
diff --git a/drivers/net/igb/igb.h b/drivers/net/igb/igb.h
index edab9c442399..92a4ef09e55c 100644
--- a/drivers/net/igb/igb.h
+++ b/drivers/net/igb/igb.h
@@ -324,6 +324,7 @@ struct igb_adapter {
         unsigned int vfs_allocated_count;
         struct vf_data_storage *vf_data;
         u32 rss_queues;
+        u32 wvbr;
 };
 
 #define IGB_FLAG_HAS_MSI           (1 << 0)
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index 892d196f17ac..58c665b7513d 100644
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -73,6 +73,8 @@ static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
+        { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
+        { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
@@ -1654,7 +1656,7 @@ void igb_reset(struct igb_adapter *adapter)
         if (adapter->vfs_allocated_count) {
                 int i;
                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
-                        adapter->vf_data[i].flags = 0;
+                        adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
 
                 /* ping all the active vfs to let them know we are going down */
                 igb_ping_all_vfs(adapter);
@@ -1729,12 +1731,13 @@ static int __devinit igb_probe(struct pci_dev *pdev,
         struct igb_adapter *adapter;
         struct e1000_hw *hw;
         u16 eeprom_data = 0;
+        s32 ret_val;
         static int global_quad_port_a; /* global quad port a indication */
         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
         unsigned long mmio_start, mmio_len;
         int err, pci_using_dac;
         u16 eeprom_apme_mask = IGB_EEPROM_APME;
-        u32 part_num;
+        u8 part_str[E1000_PBANUM_LENGTH];
 
         /* Catch broken hardware that put the wrong VF device ID in
          * the PCIe SR-IOV capability.
@@ -2000,10 +2003,10 @@ static int __devinit igb_probe(struct pci_dev *pdev,
                    "unknown"),
                  netdev->dev_addr);
 
-        igb_read_part_num(hw, &part_num);
-        dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
-                (part_num >> 8), (part_num & 0xff));
-
+        ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
+        if (ret_val)
+                strcpy(part_str, "Unknown");
+        dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
         dev_info(&pdev->dev,
                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
                 adapter->msix_entries ? "MSI-X" :
@@ -2049,13 +2052,16 @@ static void __devexit igb_remove(struct pci_dev *pdev)
         struct igb_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
 
-        /* flush_scheduled work may reschedule our watchdog task, so
-         * explicitly disable watchdog tasks from being rescheduled  */
+        /*
+         * The watchdog timer may be rescheduled, so explicitly
+         * disable watchdog from being rescheduled.
+         */
         set_bit(__IGB_DOWN, &adapter->state);
         del_timer_sync(&adapter->watchdog_timer);
         del_timer_sync(&adapter->phy_info_timer);
 
-        flush_scheduled_work();
+        cancel_work_sync(&adapter->reset_task);
+        cancel_work_sync(&adapter->watchdog_task);
 
 #ifdef CONFIG_IGB_DCA
         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
@@ -2436,10 +2442,9 @@ int igb_setup_tx_resources(struct igb_ring *tx_ring)
         int size;
 
         size = sizeof(struct igb_buffer) * tx_ring->count;
-        tx_ring->buffer_info = vmalloc(size);
+        tx_ring->buffer_info = vzalloc(size);
         if (!tx_ring->buffer_info)
                 goto err;
-        memset(tx_ring->buffer_info, 0, size);
 
         /* round up to nearest 4K */
         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
@@ -2587,10 +2592,9 @@ int igb_setup_rx_resources(struct igb_ring *rx_ring)
         int size, desc_len;
 
         size = sizeof(struct igb_buffer) * rx_ring->count;
-        rx_ring->buffer_info = vmalloc(size);
+        rx_ring->buffer_info = vzalloc(size);
         if (!rx_ring->buffer_info)
                 goto err;
-        memset(rx_ring->buffer_info, 0, size);
 
         desc_len = sizeof(union e1000_adv_rx_desc);
 
@@ -3362,6 +3366,45 @@ static void igb_set_rx_mode(struct net_device *netdev)
         igb_restore_vf_multicasts(adapter);
 }
 
+static void igb_check_wvbr(struct igb_adapter *adapter)
+{
+        struct e1000_hw *hw = &adapter->hw;
+        u32 wvbr = 0;
+
+        switch (hw->mac.type) {
+        case e1000_82576:
+        case e1000_i350:
+                if (!(wvbr = rd32(E1000_WVBR)))
+                        return;
+                break;
+        default:
+                break;
+        }
+
+        adapter->wvbr |= wvbr;
+}
+
+#define IGB_STAGGERED_QUEUE_OFFSET 8
+
+static void igb_spoof_check(struct igb_adapter *adapter)
+{
+        int j;
+
+        if (!adapter->wvbr)
+                return;
+
+        for(j = 0; j < adapter->vfs_allocated_count; j++) {
+                if (adapter->wvbr & (1 << j) ||
+                    adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
+                        dev_warn(&adapter->pdev->dev,
+                                "Spoof event(s) detected on VF %d\n", j);
+                        adapter->wvbr &=
+                                ~((1 << j) |
+                                  (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
+                }
+        }
+}
+
 /* Need to wait a few seconds after link up to get diagnostic information from
  * the phy */
 static void igb_update_phy_info(unsigned long data)
@@ -3521,6 +3564,8 @@ static void igb_watchdog_task(struct work_struct *work)
                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
         }
 
+        igb_spoof_check(adapter);
+
         /* Reset the timer */
         if (!test_bit(__IGB_DOWN, &adapter->state))
                 mod_timer(&adapter->watchdog_timer,
@@ -4517,6 +4562,10 @@ static irqreturn_t igb_msix_other(int irq, void *data)
         if (icr & E1000_ICR_DOUTSYNC) {
                 /* HW is reporting DMA is out of sync */
                 adapter->stats.doosync++;
+                /* The DMA Out of Sync is also indication of a spoof event
+                 * in IOV mode. Check the Wrong VM Behavior register to
+                 * see if it is really a spoof event. */
+                igb_check_wvbr(adapter);
         }
 
         /* Check for a mailbox event */
@@ -4969,8 +5018,8 @@ static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
 
 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
 {
-        /* clear flags */
-        adapter->vf_data[vf].flags &= ~(IGB_VF_FLAG_PF_SET_MAC);
+        /* clear flags - except flag that indicates PF has set the MAC */
+        adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
         adapter->vf_data[vf].last_nack = jiffies;
 
         /* reset offloads to defaults */
@@ -5024,7 +5073,7 @@ static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
         reg = rd32(E1000_VFRE);
         wr32(E1000_VFRE, reg | (1 << vf));
 
-        adapter->vf_data[vf].flags = IGB_VF_FLAG_CTS;
+        adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
 
         /* reply to reset with ack and vf mac address */
         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
@@ -5103,7 +5152,14 @@ static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
 
         switch ((msgbuf[0] & 0xFFFF)) {
         case E1000_VF_SET_MAC_ADDR:
-                retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
+                retval = -EINVAL;
+                if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
+                        retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
+                else
+                        dev_warn(&pdev->dev,
+                                 "VF %d attempted to override administratively "
+                                 "set MAC address\nReload the VF driver to "
+                                 "resume operations\n", vf);
                 break;
         case E1000_VF_SET_PROMISC:
                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
@@ -5115,8 +5171,12 @@ static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
                 break;
         case E1000_VF_SET_VLAN:
-                if (adapter->vf_data[vf].pf_vlan)
-                        retval = -1;
+                retval = -1;
+                if (vf_data->pf_vlan)
+                        dev_warn(&pdev->dev,
+                                 "VF %d attempted to override administratively "
+                                 "set VLAN tag\nReload the VF driver to "
+                                 "resume operations\n", vf);
                 else
                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
                 break;
@@ -6580,6 +6640,8 @@ static void igb_vmm_control(struct igb_adapter *adapter)
         if (adapter->vfs_allocated_count) {
                 igb_vmdq_set_loopback_pf(hw, true);
                 igb_vmdq_set_replication_pf(hw, true);
+                igb_vmdq_set_anti_spoofing_pf(hw, true,
+                                                adapter->vfs_allocated_count);
         } else {
                 igb_vmdq_set_loopback_pf(hw, false);
                 igb_vmdq_set_replication_pf(hw, false);
diff --git a/drivers/net/igbvf/Makefile b/drivers/net/igbvf/Makefile
index c2f150d8f2d9..0fa3db3dd8b6 100644
--- a/drivers/net/igbvf/Makefile
+++ b/drivers/net/igbvf/Makefile
@@ -1,7 +1,7 @@
 ################################################################################
 #
 # Intel(R) 82576 Virtual Function Linux driver
-# Copyright(c) 2009 Intel Corporation.
+# Copyright(c) 2009 - 2010 Intel Corporation.
 #
 # This program is free software; you can redistribute it and/or modify it
 # under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/igbvf/defines.h b/drivers/net/igbvf/defines.h
index 88a47537518a..79f2604673fe 100644
--- a/drivers/net/igbvf/defines.h
+++ b/drivers/net/igbvf/defines.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/igbvf/ethtool.c b/drivers/net/igbvf/ethtool.c
index 33add708bcbe..ed6e3d910247 100644
--- a/drivers/net/igbvf/ethtool.c
+++ b/drivers/net/igbvf/ethtool.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -110,11 +110,6 @@ static int igbvf_get_settings(struct net_device *netdev,
         return 0;
 }
 
-static u32 igbvf_get_link(struct net_device *netdev)
-{
-        return netif_carrier_ok(netdev);
-}
-
 static int igbvf_set_settings(struct net_device *netdev,
                               struct ethtool_cmd *ecmd)
 {
@@ -515,7 +510,7 @@ static const struct ethtool_ops igbvf_ethtool_ops = {
         .get_msglevel           = igbvf_get_msglevel,
         .set_msglevel           = igbvf_set_msglevel,
         .nway_reset             = igbvf_nway_reset,
-        .get_link               = igbvf_get_link,
+        .get_link               = ethtool_op_get_link,
         .get_eeprom_len         = igbvf_get_eeprom_len,
         .get_eeprom             = igbvf_get_eeprom,
         .set_eeprom             = igbvf_set_eeprom,
diff --git a/drivers/net/igbvf/igbvf.h b/drivers/net/igbvf/igbvf.h
index debeee2dc717..990c329e6c3b 100644
--- a/drivers/net/igbvf/igbvf.h
+++ b/drivers/net/igbvf/igbvf.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -97,6 +97,7 @@ struct igbvf_adapter;
 
 enum igbvf_boards {
         board_vf,
+        board_i350_vf,
 };
 
 struct igbvf_queue_stats {
@@ -126,7 +127,6 @@ struct igbvf_buffer {
                         unsigned int page_offset;
                 };
         };
-        struct page *page;
 };
 
 union igbvf_desc {
diff --git a/drivers/net/igbvf/mbx.c b/drivers/net/igbvf/mbx.c
index 819a8ec901dc..3d6f4cc3998a 100644
--- a/drivers/net/igbvf/mbx.c
+++ b/drivers/net/igbvf/mbx.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/igbvf/mbx.h b/drivers/net/igbvf/mbx.h
index 4938609dbfb5..c2883c45d477 100644
--- a/drivers/net/igbvf/mbx.h
+++ b/drivers/net/igbvf/mbx.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/igbvf/netdev.c b/drivers/net/igbvf/netdev.c
index 28af019c97bb..6352c8158e6d 100644
--- a/drivers/net/igbvf/netdev.c
+++ b/drivers/net/igbvf/netdev.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -44,12 +44,13 @@
 
 #include "igbvf.h"
 
-#define DRV_VERSION "1.0.0-k0"
+#define DRV_VERSION "1.0.8-k0"
 char igbvf_driver_name[] = "igbvf";
 const char igbvf_driver_version[] = DRV_VERSION;
 static const char igbvf_driver_string[] =
                                 "Intel(R) Virtual Function Network Driver";
-static const char igbvf_copyright[] = "Copyright (c) 2009 Intel Corporation.";
+static const char igbvf_copyright[] =
+                                "Copyright (c) 2009 - 2010 Intel Corporation.";
 
 static int igbvf_poll(struct napi_struct *napi, int budget);
 static void igbvf_reset(struct igbvf_adapter *);
@@ -63,8 +64,16 @@ static struct igbvf_info igbvf_vf_info = {
         .init_ops               = e1000_init_function_pointers_vf,
 };
 
+static struct igbvf_info igbvf_i350_vf_info = {
+        .mac                    = e1000_vfadapt_i350,
+        .flags                  = 0,
+        .pba                    = 10,
+        .init_ops               = e1000_init_function_pointers_vf,
+};
+
 static const struct igbvf_info *igbvf_info_tbl[] = {
         [board_vf]              = &igbvf_vf_info,
+        [board_i350_vf]         = &igbvf_i350_vf_info,
 };
 
 /**
@@ -429,10 +438,9 @@ int igbvf_setup_tx_resources(struct igbvf_adapter *adapter,
         int size;
 
         size = sizeof(struct igbvf_buffer) * tx_ring->count;
-        tx_ring->buffer_info = vmalloc(size);
+        tx_ring->buffer_info = vzalloc(size);
         if (!tx_ring->buffer_info)
                 goto err;
-        memset(tx_ring->buffer_info, 0, size);
 
         /* round up to nearest 4K */
         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
@@ -469,10 +477,9 @@ int igbvf_setup_rx_resources(struct igbvf_adapter *adapter,
         int size, desc_len;
 
         size = sizeof(struct igbvf_buffer) * rx_ring->count;
-        rx_ring->buffer_info = vmalloc(size);
+        rx_ring->buffer_info = vzalloc(size);
         if (!rx_ring->buffer_info)
                 goto err;
-        memset(rx_ring->buffer_info, 0, size);
 
         desc_len = sizeof(union e1000_adv_rx_desc);
 
@@ -1851,8 +1858,6 @@ static void igbvf_watchdog_task(struct work_struct *work)
 
         if (link) {
                 if (!netif_carrier_ok(netdev)) {
-                        bool txb2b = 1;
-
                         mac->ops.get_link_up_info(&adapter->hw,
                                                   &adapter->link_speed,
                                                   &adapter->link_duplex);
@@ -1862,11 +1867,9 @@ static void igbvf_watchdog_task(struct work_struct *work)
                         adapter->tx_timeout_factor = 1;
                         switch (adapter->link_speed) {
                         case SPEED_10:
-                                txb2b = 0;
                                 adapter->tx_timeout_factor = 16;
                                 break;
                         case SPEED_100:
-                                txb2b = 0;
                                 /* maybe add some timeout factor ? */
                                 break;
                         }
@@ -2830,13 +2833,14 @@ static void __devexit igbvf_remove(struct pci_dev *pdev)
         struct e1000_hw *hw = &adapter->hw;
 
         /*
-         * flush_scheduled work may reschedule our watchdog task, so
-         * explicitly disable watchdog tasks from being rescheduled
+         * The watchdog timer may be rescheduled, so explicitly
+         * disable it from being rescheduled.
          */
         set_bit(__IGBVF_DOWN, &adapter->state);
         del_timer_sync(&adapter->watchdog_timer);
 
-        flush_scheduled_work();
+        cancel_work_sync(&adapter->reset_task);
+        cancel_work_sync(&adapter->watchdog_task);
 
         unregister_netdev(netdev);
 
@@ -2869,6 +2873,7 @@ static struct pci_error_handlers igbvf_err_handler = {
 
 static DEFINE_PCI_DEVICE_TABLE(igbvf_pci_tbl) = {
         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_VF), board_vf },
+        { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_VF), board_i350_vf },
         { } /* terminate list */
 };
 MODULE_DEVICE_TABLE(pci, igbvf_pci_tbl);
diff --git a/drivers/net/igbvf/regs.h b/drivers/net/igbvf/regs.h
index b9e24ed70d0a..77e18d3d6b15 100644
--- a/drivers/net/igbvf/regs.h
+++ b/drivers/net/igbvf/regs.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/igbvf/vf.c b/drivers/net/igbvf/vf.c
index a9a61efa964c..74486a8b009a 100644
--- a/drivers/net/igbvf/vf.c
+++ b/drivers/net/igbvf/vf.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -362,8 +362,8 @@ static s32 e1000_check_for_link_vf(struct e1000_hw *hw)
          * or a virtual function reset
          */
 
-        /* If we were hit with a reset drop the link */
-        if (!mbx->ops.check_for_rst(hw))
+        /* If we were hit with a reset or timeout drop the link */
+        if (!mbx->ops.check_for_rst(hw) || !mbx->timeout)
                 mac->get_link_status = true;
 
         if (!mac->get_link_status)
diff --git a/drivers/net/igbvf/vf.h b/drivers/net/igbvf/vf.h
index 1e8ce3741a67..d7ed58fcd9bb 100644
--- a/drivers/net/igbvf/vf.h
+++ b/drivers/net/igbvf/vf.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel(R) 82576 Virtual Function Linux driver
-  Copyright(c) 2009 Intel Corporation.
+  Copyright(c) 2009 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -39,6 +39,7 @@
 struct e1000_hw;
 
 #define E1000_DEV_ID_82576_VF                 0x10CA
+#define E1000_DEV_ID_I350_VF                  0x1520
 #define E1000_REVISION_0 0
 #define E1000_REVISION_1 1
 #define E1000_REVISION_2 2
@@ -133,6 +134,7 @@ struct e1000_adv_tx_context_desc {
 enum e1000_mac_type {
         e1000_undefined = 0,
         e1000_vfadapt,
+        e1000_vfadapt_i350,
         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 };
 
diff --git a/drivers/net/irda/act200l-sir.c b/drivers/net/irda/act200l-sir.c
index 37ab8c855719..8ff084f1d236 100644
--- a/drivers/net/irda/act200l-sir.c
+++ b/drivers/net/irda/act200l-sir.c
@@ -199,7 +199,7 @@ static int act200l_reset(struct sir_dev *dev)
 {
         unsigned state = dev->fsm.substate;
         unsigned delay = 0;
-        u8 control[9] = {
+        static const u8 control[9] = {
                 ACT200L_REG15,
                 ACT200L_REG13 | ACT200L_SHDW,
                 ACT200L_REG21 | ACT200L_EXCK | ACT200L_OSCL,
diff --git a/drivers/net/irda/bfin_sir.h b/drivers/net/irda/bfin_sir.h
index b54a6f08db45..e3b285a67734 100644
--- a/drivers/net/irda/bfin_sir.h
+++ b/drivers/net/irda/bfin_sir.h
@@ -26,6 +26,8 @@
 #include <asm/cacheflush.h>
 #include <asm/dma.h>
 #include <asm/portmux.h>
+#include <mach/bfin_serial_5xx.h>
+#undef DRIVER_NAME
 
 #ifdef CONFIG_SIR_BFIN_DMA
 struct dma_rx_buf {
diff --git a/drivers/net/irda/donauboe.c b/drivers/net/irda/donauboe.c
index b626cccbccd1..f81d944fc360 100644
--- a/drivers/net/irda/donauboe.c
+++ b/drivers/net/irda/donauboe.c
@@ -818,9 +818,9 @@ toshoboe_probe (struct toshoboe_cb *self)
 {
   int i, j, n;
 #ifdef USE_MIR
-  int bauds[] = { 9600, 115200, 4000000, 1152000 };
+  static const int bauds[] = { 9600, 115200, 4000000, 1152000 };
 #else
-  int bauds[] = { 9600, 115200, 4000000 };
+  static const int bauds[] = { 9600, 115200, 4000000 };
 #endif
   unsigned long flags;
 
diff --git a/drivers/net/irda/mcs7780.c b/drivers/net/irda/mcs7780.c
index 74b20f179cea..cc821de2c966 100644
--- a/drivers/net/irda/mcs7780.c
+++ b/drivers/net/irda/mcs7780.c
@@ -959,7 +959,7 @@ static void mcs_disconnect(struct usb_interface *intf)
         if (!mcs)
                 return;
 
-        flush_scheduled_work();
+        cancel_work_sync(&mcs->work);
 
         unregister_netdev(mcs->netdev);
         free_netdev(mcs->netdev);
diff --git a/drivers/net/irda/smsc-ircc2.c b/drivers/net/irda/smsc-ircc2.c
index 8c57bfb5f098..1c1677cfea29 100644
--- a/drivers/net/irda/smsc-ircc2.c
+++ b/drivers/net/irda/smsc-ircc2.c
@@ -376,7 +376,7 @@ MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
 static int pnp_driver_registered;
 
 #ifdef CONFIG_PNP
-static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
+static int __devinit smsc_ircc_pnp_probe(struct pnp_dev *dev,
                                       const struct pnp_device_id *dev_id)
 {
         unsigned int firbase, sirbase;
diff --git a/drivers/net/iseries_veth.c b/drivers/net/iseries_veth.c
index 8df645e78f2e..9ece1fd9889d 100644
--- a/drivers/net/iseries_veth.c
+++ b/drivers/net/iseries_veth.c
@@ -885,17 +885,8 @@ static void veth_stop_connection(struct veth_lpar_connection *cnx)
         veth_kick_statemachine(cnx);
         spin_unlock_irq(&cnx->lock);
 
-        /* There's a slim chance the reset code has just queued the
-         * statemachine to run in five seconds. If so we need to cancel
-         * that and requeue the work to run now. */
-        if (cancel_delayed_work(&cnx->statemachine_wq)) {
-                spin_lock_irq(&cnx->lock);
-                veth_kick_statemachine(cnx);
-                spin_unlock_irq(&cnx->lock);
-        }
-
-        /* Wait for the state machine to run. */
-        flush_scheduled_work();
+        /* ensure the statemachine runs now and waits for its completion */
+        flush_delayed_work_sync(&cnx->statemachine_wq);
 }
 
 static void veth_destroy_connection(struct veth_lpar_connection *cnx)
@@ -1009,15 +1000,10 @@ static int veth_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         return 0;
 }
 
-static u32 veth_get_link(struct net_device *dev)
-{
-        return 1;
-}
-
 static const struct ethtool_ops ops = {
         .get_drvinfo = veth_get_drvinfo,
         .get_settings = veth_get_settings,
-        .get_link = veth_get_link,
+        .get_link = ethtool_op_get_link,
 };
 
 static const struct net_device_ops veth_netdev_ops = {
@@ -1605,7 +1591,7 @@ static int veth_probe(struct vio_dev *vdev, const struct vio_device_id *id)
         }
         veth_dev[i] = dev;
 
-        port = (struct veth_port*)netdev_priv(dev);
+        port = netdev_priv(dev);
 
         /* Start the state machine on each connection on this vlan. If we're
          * the first dev to do so this will commence link negotiation */
@@ -1658,15 +1644,14 @@ static void __exit veth_module_cleanup(void)
         /* Disconnect our "irq" to stop events coming from the Hypervisor. */
         HvLpEvent_unregisterHandler(HvLpEvent_Type_VirtualLan);
 
-        /* Make sure any work queued from Hypervisor callbacks is finished. */
-        flush_scheduled_work();
-
         for (i = 0; i < HVMAXARCHITECTEDLPS; ++i) {
                 cnx = veth_cnx[i];
 
                 if (!cnx)
                         continue;
 
+                /* Cancel work queued from Hypervisor callbacks */
+                cancel_delayed_work_sync(&cnx->statemachine_wq);
                 /* Remove the connection from sysfs */
                 kobject_del(&cnx->kobject);
                 /* Drop the driver's reference to the connection */
diff --git a/drivers/net/ixgb/ixgb_main.c b/drivers/net/ixgb/ixgb_main.c
index caa8192fff2a..5639cccb4935 100644
--- a/drivers/net/ixgb/ixgb_main.c
+++ b/drivers/net/ixgb/ixgb_main.c
@@ -98,6 +98,8 @@ static void ixgb_alloc_rx_buffers(struct ixgb_adapter *, int);
 static void ixgb_tx_timeout(struct net_device *dev);
 static void ixgb_tx_timeout_task(struct work_struct *work);
 
+static void ixgb_vlan_strip_enable(struct ixgb_adapter *adapter);
+static void ixgb_vlan_strip_disable(struct ixgb_adapter *adapter);
 static void ixgb_vlan_rx_register(struct net_device *netdev,
                                   struct vlan_group *grp);
 static void ixgb_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
@@ -525,7 +527,7 @@ ixgb_remove(struct pci_dev *pdev)
         struct net_device *netdev = pci_get_drvdata(pdev);
         struct ixgb_adapter *adapter = netdev_priv(netdev);
 
-        flush_scheduled_work();
+        cancel_work_sync(&adapter->tx_timeout_task);
 
         unregister_netdev(netdev);
 
@@ -669,13 +671,12 @@ ixgb_setup_tx_resources(struct ixgb_adapter *adapter)
         int size;
 
         size = sizeof(struct ixgb_buffer) * txdr->count;
-        txdr->buffer_info = vmalloc(size);
+        txdr->buffer_info = vzalloc(size);
         if (!txdr->buffer_info) {
                 netif_err(adapter, probe, adapter->netdev,
                           "Unable to allocate transmit descriptor ring memory\n");
                 return -ENOMEM;
         }
-        memset(txdr->buffer_info, 0, size);
 
         /* round up to nearest 4K */
 
@@ -759,13 +760,12 @@ ixgb_setup_rx_resources(struct ixgb_adapter *adapter)
         int size;
 
         size = sizeof(struct ixgb_buffer) * rxdr->count;
-        rxdr->buffer_info = vmalloc(size);
+        rxdr->buffer_info = vzalloc(size);
         if (!rxdr->buffer_info) {
                 netif_err(adapter, probe, adapter->netdev,
                           "Unable to allocate receive descriptor ring\n");
                 return -ENOMEM;
         }
-        memset(rxdr->buffer_info, 0, size);
 
         /* Round up to nearest 4K */
 
@@ -1078,6 +1078,8 @@ ixgb_set_multi(struct net_device *netdev)
 
         if (netdev->flags & IFF_PROMISC) {
                 rctl |= (IXGB_RCTL_UPE | IXGB_RCTL_MPE);
+                /* disable VLAN filtering */
+                rctl &= ~IXGB_RCTL_CFIEN;
                 rctl &= ~IXGB_RCTL_VFE;
         } else {
                 if (netdev->flags & IFF_ALLMULTI) {
@@ -1086,7 +1088,9 @@ ixgb_set_multi(struct net_device *netdev)
                 } else {
                         rctl &= ~(IXGB_RCTL_UPE | IXGB_RCTL_MPE);
                 }
+                /* enable VLAN filtering */
                 rctl |= IXGB_RCTL_VFE;
+                rctl &= ~IXGB_RCTL_CFIEN;
         }
 
         if (netdev_mc_count(netdev) > IXGB_MAX_NUM_MULTICAST_ADDRESSES) {
@@ -1105,6 +1109,12 @@ ixgb_set_multi(struct net_device *netdev)
 
                 ixgb_mc_addr_list_update(hw, mta, netdev_mc_count(netdev), 0);
         }
+
+        if (netdev->features & NETIF_F_HW_VLAN_RX)
+                ixgb_vlan_strip_enable(adapter);
+        else
+                ixgb_vlan_strip_disable(adapter);
+
 }
 
 /**
@@ -1252,7 +1262,7 @@ ixgb_tx_csum(struct ixgb_adapter *adapter, struct sk_buff *skb)
 
         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
                 struct ixgb_buffer *buffer_info;
-                css = skb_transport_offset(skb);
+                css = skb_checksum_start_offset(skb);
                 cso = css + skb->csum_offset;
 
                 i = adapter->tx_ring.next_to_use;
@@ -2152,33 +2162,30 @@ static void
 ixgb_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
 {
         struct ixgb_adapter *adapter = netdev_priv(netdev);
-        u32 ctrl, rctl;
 
-        ixgb_irq_disable(adapter);
         adapter->vlgrp = grp;
+}
 
-        if (grp) {
-                /* enable VLAN tag insert/strip */
-                ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
-                ctrl |= IXGB_CTRL0_VME;
-                IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
-
-                /* enable VLAN receive filtering */
+static void
+ixgb_vlan_strip_enable(struct ixgb_adapter *adapter)
+{
+        u32 ctrl;
 
-                rctl = IXGB_READ_REG(&adapter->hw, RCTL);
-                rctl &= ~IXGB_RCTL_CFIEN;
-                IXGB_WRITE_REG(&adapter->hw, RCTL, rctl);
-        } else {
-                /* disable VLAN tag insert/strip */
+        /* enable VLAN tag insert/strip */
+        ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
+        ctrl |= IXGB_CTRL0_VME;
+        IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
+}
 
-                ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
-                ctrl &= ~IXGB_CTRL0_VME;
-                IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
-        }
+static void
+ixgb_vlan_strip_disable(struct ixgb_adapter *adapter)
+{
+        u32 ctrl;
 
-        /* don't enable interrupts unless we are UP */
-        if (adapter->netdev->flags & IFF_UP)
-                ixgb_irq_enable(adapter);
+        /* disable VLAN tag insert/strip */
+        ctrl = IXGB_READ_REG(&adapter->hw, CTRL0);
+        ctrl &= ~IXGB_CTRL0_VME;
+        IXGB_WRITE_REG(&adapter->hw, CTRL0, ctrl);
 }
 
 static void
diff --git a/drivers/net/ixgb/ixgb_param.c b/drivers/net/ixgb/ixgb_param.c
index 88a08f056241..dd7fbeb1f7d1 100644
--- a/drivers/net/ixgb/ixgb_param.c
+++ b/drivers/net/ixgb/ixgb_param.c
@@ -191,9 +191,9 @@ struct ixgb_option {
                 } r;
                 struct {        /* list_option info */
                         int nr;
-                        struct ixgb_opt_list {
+                        const struct ixgb_opt_list {
                                 int i;
-                                char *str;
+                                const char *str;
                         } *p;
                 } l;
         } arg;
@@ -226,7 +226,7 @@ ixgb_validate_option(unsigned int *value, const struct ixgb_option *opt)
                 break;
         case list_option: {
                 int i;
-                struct ixgb_opt_list *ent;
+                const struct ixgb_opt_list *ent;
 
                 for (i = 0; i < opt->arg.l.nr; i++) {
                         ent = &opt->arg.l.p[i];
@@ -322,14 +322,15 @@ ixgb_check_options(struct ixgb_adapter *adapter)
         }
         { /* Flow Control */
 
-                struct ixgb_opt_list fc_list[] =
-                        {{ ixgb_fc_none,        "Flow Control Disabled" },
-                         { ixgb_fc_rx_pause,"Flow Control Receive Only" },
-                         { ixgb_fc_tx_pause,"Flow Control Transmit Only" },
-                         { ixgb_fc_full,        "Flow Control Enabled" },
-                         { ixgb_fc_default, "Flow Control Hardware Default" }};
+                static const struct ixgb_opt_list fc_list[] = {
+                       { ixgb_fc_none, "Flow Control Disabled" },
+                       { ixgb_fc_rx_pause, "Flow Control Receive Only" },
+                       { ixgb_fc_tx_pause, "Flow Control Transmit Only" },
+                       { ixgb_fc_full, "Flow Control Enabled" },
+                       { ixgb_fc_default, "Flow Control Hardware Default" }
+                };
 
-                const struct ixgb_option opt = {
+                static const struct ixgb_option opt = {
                         .type = list_option,
                         .name = "Flow Control",
                         .err  = "reading default settings from EEPROM",
diff --git a/drivers/net/ixgbe/Makefile b/drivers/net/ixgbe/Makefile
index 8f81efb49169..7d7387fbdecd 100644
--- a/drivers/net/ixgbe/Makefile
+++ b/drivers/net/ixgbe/Makefile
@@ -34,7 +34,7 @@ obj-$(CONFIG_IXGBE) += ixgbe.o
 
 ixgbe-objs := ixgbe_main.o ixgbe_common.o ixgbe_ethtool.o \
               ixgbe_82599.o ixgbe_82598.o ixgbe_phy.o ixgbe_sriov.o \
-              ixgbe_mbx.o
+              ixgbe_mbx.o ixgbe_x540.o
 
 ixgbe-$(CONFIG_IXGBE_DCB) +=  ixgbe_dcb.o ixgbe_dcb_82598.o \
                               ixgbe_dcb_82599.o ixgbe_dcb_nl.o
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index ed8703cfffb7..3b8c92463617 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -61,10 +61,8 @@
 #define IXGBE_MIN_RXD                        64
 
 /* flow control */
-#define IXGBE_DEFAULT_FCRTL             0x10000
 #define IXGBE_MIN_FCRTL                    0x40
 #define IXGBE_MAX_FCRTL                 0x7FF80
-#define IXGBE_DEFAULT_FCRTH             0x20000
 #define IXGBE_MIN_FCRTH                   0x600
 #define IXGBE_MAX_FCRTH                 0x7FFF0
 #define IXGBE_DEFAULT_FCPAUSE            0xFFFF
@@ -130,7 +128,9 @@ struct ixgbe_tx_buffer {
         unsigned long time_stamp;
         u16 length;
         u16 next_to_watch;
-        u16 mapped_as_page;
+        unsigned int bytecount;
+        u16 gso_segs;
+        u8 mapped_as_page;
 };
 
 struct ixgbe_rx_buffer {
@@ -146,12 +146,56 @@ struct ixgbe_queue_stats {
         u64 bytes;
 };
 
+struct ixgbe_tx_queue_stats {
+        u64 restart_queue;
+        u64 tx_busy;
+        u64 completed;
+        u64 tx_done_old;
+};
+
+struct ixgbe_rx_queue_stats {
+        u64 rsc_count;
+        u64 rsc_flush;
+        u64 non_eop_descs;
+        u64 alloc_rx_page_failed;
+        u64 alloc_rx_buff_failed;
+};
+
+enum ixbge_ring_state_t {
+        __IXGBE_TX_FDIR_INIT_DONE,
+        __IXGBE_TX_DETECT_HANG,
+        __IXGBE_HANG_CHECK_ARMED,
+        __IXGBE_RX_PS_ENABLED,
+        __IXGBE_RX_RSC_ENABLED,
+};
+
+#define ring_is_ps_enabled(ring) \
+        test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define set_ring_ps_enabled(ring) \
+        set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define clear_ring_ps_enabled(ring) \
+        clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
+#define check_for_tx_hang(ring) \
+        test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define set_check_for_tx_hang(ring) \
+        set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define clear_check_for_tx_hang(ring) \
+        clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
+#define ring_is_rsc_enabled(ring) \
+        test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
+#define set_ring_rsc_enabled(ring) \
+        set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
+#define clear_ring_rsc_enabled(ring) \
+        clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
 struct ixgbe_ring {
         void *desc;                     /* descriptor ring memory */
+        struct device *dev;             /* device for DMA mapping */
+        struct net_device *netdev;      /* netdev ring belongs to */
         union {
                 struct ixgbe_tx_buffer *tx_buffer_info;
                 struct ixgbe_rx_buffer *rx_buffer_info;
         };
+        unsigned long state;
         u8 atr_sample_rate;
         u8 atr_count;
         u16 count;                      /* amount of descriptors */
@@ -160,38 +204,30 @@ struct ixgbe_ring {
         u16 next_to_clean;
 
         u8 queue_index; /* needed for multiqueue queue management */
-
-#define IXGBE_RING_RX_PS_ENABLED                (u8)(1)
-        u8 flags;                       /* per ring feature flags */
-        u16 head;
-        u16 tail;
-
-        unsigned int total_bytes;
-        unsigned int total_packets;
-
-#ifdef CONFIG_IXGBE_DCA
-        /* cpu for tx queue */
-        int cpu;
-#endif
-
-        u16 work_limit;                 /* max work per interrupt */
-        u16 reg_idx;                    /* holds the special value that gets
+        u8 reg_idx;                     /* holds the special value that gets
                                          * the hardware register offset
                                          * associated with this ring, which is
                                          * different for DCB and RSS modes
                                          */
 
+        u16 work_limit;                 /* max work per interrupt */
+
+        u8 __iomem *tail;
+
+        unsigned int total_bytes;
+        unsigned int total_packets;
+
         struct ixgbe_queue_stats stats;
         struct u64_stats_sync syncp;
+        union {
+                struct ixgbe_tx_queue_stats tx_stats;
+                struct ixgbe_rx_queue_stats rx_stats;
+        };
         int numa_node;
-        unsigned long reinit_state;
-        u64 rsc_count;                  /* stat for coalesced packets */
-        u64 rsc_flush;                  /* stats for flushed packets */
-        u32 restart_queue;              /* track tx queue restarts */
-        u32 non_eop_descs;              /* track hardware descriptor chaining */
-
         unsigned int size;              /* length in bytes */
         dma_addr_t dma;                 /* phys. address of descriptor ring */
+        struct rcu_head rcu;
+        struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
 } ____cacheline_internodealigned_in_smp;
 
 enum ixgbe_ring_f_enum {
@@ -237,6 +273,9 @@ struct ixgbe_q_vector {
         unsigned int v_idx; /* index of q_vector within array, also used for
                              * finding the bit in EICR and friends that
                              * represents the vector for this ring */
+#ifdef CONFIG_IXGBE_DCA
+        int cpu;            /* CPU for DCA */
+#endif
         struct napi_struct napi;
         DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
         DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
@@ -246,6 +285,7 @@ struct ixgbe_q_vector {
         u8 rx_itr;
         u32 eitr;
         cpumask_var_t affinity_mask;
+        char name[IFNAMSIZ + 9];
 };
 
 /* Helper macros to switch between ints/sec and what the register uses.
@@ -294,7 +334,6 @@ struct ixgbe_adapter {
         u16 bd_number;
         struct work_struct reset_task;
         struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
-        char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
         struct ixgbe_dcb_config dcb_cfg;
         struct ixgbe_dcb_config temp_dcb_cfg;
         u8 dcb_set_bitmap;
@@ -417,6 +456,7 @@ struct ixgbe_adapter {
         int node;
         struct work_struct check_overtemp_task;
         u32 interrupt_event;
+        char lsc_int_name[IFNAMSIZ + 9];
 
         /* SR-IOV */
         DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
@@ -428,17 +468,25 @@ enum ixbge_state_t {
         __IXGBE_TESTING,
         __IXGBE_RESETTING,
         __IXGBE_DOWN,
-        __IXGBE_FDIR_INIT_DONE,
         __IXGBE_SFP_MODULE_NOT_FOUND
 };
 
+struct ixgbe_rsc_cb {
+        dma_addr_t dma;
+        u16 skb_cnt;
+        bool delay_unmap;
+};
+#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
+
 enum ixgbe_boards {
         board_82598,
         board_82599,
+        board_X540,
 };
 
 extern struct ixgbe_info ixgbe_82598_info;
 extern struct ixgbe_info ixgbe_82599_info;
+extern struct ixgbe_info ixgbe_X540_info;
 #ifdef CONFIG_IXGBE_DCB
 extern const struct dcbnl_rtnl_ops dcbnl_ops;
 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
@@ -454,50 +502,41 @@ extern void ixgbe_down(struct ixgbe_adapter *adapter);
 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
-extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
-extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
-extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
-extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
+extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
+extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
+extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
+extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
+extern void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
+                                   struct ixgbe_ring *);
 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
-                                         struct net_device *,
                                          struct ixgbe_adapter *,
                                          struct ixgbe_ring *);
-extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
+extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
                                              struct ixgbe_tx_buffer *);
-extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
-                                   struct ixgbe_ring *rx_ring,
-                                   int cleaned_count);
+extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
 extern int ethtool_ioctl(struct ifreq *ifr);
+extern u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 index);
 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-                                                 struct ixgbe_atr_input *input,
+                                                 union ixgbe_atr_hash_dword input,
+                                                 union ixgbe_atr_hash_dword common,
                                                  u8 queue);
 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-                                      struct ixgbe_atr_input *input,
+                                      union ixgbe_atr_input *input,
                                       struct ixgbe_atr_input_masks *input_masks,
                                       u16 soft_id, u8 queue);
-extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
-                                       u16 vlan_id);
-extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 src_addr);
-extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 dst_addr);
-extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
-                                        u16 src_port);
-extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
-                                        u16 dst_port);
-extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
-                                         u16 flex_byte);
-extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
-                                      u8 l4type);
+extern void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
+                                   struct ixgbe_ring *ring);
+extern void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
+                               struct ixgbe_ring *ring);
 extern void ixgbe_set_rx_mode(struct net_device *netdev);
 #ifdef IXGBE_FCOE
 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index 9c02d6014cc4..d0f1d9d2c416 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -38,9 +38,6 @@
 #define IXGBE_82598_MC_TBL_SIZE  128
 #define IXGBE_82598_VFT_TBL_SIZE 128
 
-static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
-                                             ixgbe_link_speed *speed,
-                                             bool *autoneg);
 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
                                          ixgbe_link_speed speed,
                                          bool autoneg,
@@ -156,7 +153,7 @@ static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
                 mac->ops.get_link_capabilities =
-                                  &ixgbe_get_copper_link_capabilities_82598;
+                        &ixgbe_get_copper_link_capabilities_generic;
         }
 
         switch (hw->phy.type) {
@@ -274,37 +271,6 @@ static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 }
 
 /**
- *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
- *  @hw: pointer to hardware structure
- *  @speed: pointer to link speed
- *  @autoneg: boolean auto-negotiation value
- *
- *  Determines the link capabilities by reading the AUTOC register.
- **/
-static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
-                                                    ixgbe_link_speed *speed,
-                                                    bool *autoneg)
-{
-        s32 status = IXGBE_ERR_LINK_SETUP;
-        u16 speed_ability;
-
-        *speed = 0;
-        *autoneg = true;
-
-        status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
-                                      &speed_ability);
-
-        if (status == 0) {
-                if (speed_ability & MDIO_SPEED_10G)
-                    *speed |= IXGBE_LINK_SPEED_10GB_FULL;
-                if (speed_ability & MDIO_PMA_SPEED_1000)
-                    *speed |= IXGBE_LINK_SPEED_1GB_FULL;
-        }
-
-        return status;
-}
-
-/**
  *  ixgbe_get_media_type_82598 - Determines media type
  *  @hw: pointer to hardware structure
  *
@@ -357,6 +323,7 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
         u32 fctrl_reg;
         u32 rmcs_reg;
         u32 reg;
+        u32 rx_pba_size;
         u32 link_speed = 0;
         bool link_up;
 
@@ -459,16 +426,18 @@ static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 
         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-                if (hw->fc.send_xon) {
-                        IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
-                                        (hw->fc.low_water | IXGBE_FCRTL_XONE));
-                } else {
-                        IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
-                                        hw->fc.low_water);
-                }
+                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
+
+                reg = (rx_pba_size - hw->fc.low_water) << 6;
+                if (hw->fc.send_xon)
+                        reg |= IXGBE_FCRTL_XONE;
+                IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
+
+                reg = (rx_pba_size - hw->fc.high_water) << 10;
+                reg |= IXGBE_FCRTH_FCEN;
 
-                IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
-                                (hw->fc.high_water | IXGBE_FCRTH_FCEN));
+                IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
         }
 
         /* Configure pause time (2 TCs per register) */
@@ -1222,6 +1191,7 @@ static struct ixgbe_mac_operations mac_ops_82598 = {
 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
         .init_params            = &ixgbe_init_eeprom_params_generic,
         .read                   = &ixgbe_read_eerd_generic,
+        .calc_checksum          = &ixgbe_calc_eeprom_checksum_generic,
         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
 };
diff --git a/drivers/net/ixgbe/ixgbe_82599.c b/drivers/net/ixgbe/ixgbe_82599.c
index 05e6b8cafb39..a21f5817685b 100644
--- a/drivers/net/ixgbe/ixgbe_82599.c
+++ b/drivers/net/ixgbe/ixgbe_82599.c
@@ -56,9 +56,6 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
                                ixgbe_link_speed speed,
                                bool autoneg,
                                bool autoneg_wait_to_complete);
-static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
-                                             ixgbe_link_speed *speed,
-                                             bool *autoneg);
 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
                                          ixgbe_link_speed speed,
                                          bool autoneg,
@@ -68,9 +65,9 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
 {
         struct ixgbe_mac_info *mac = &hw->mac;
-        if (hw->phy.multispeed_fiber) {
-                /* Set up dual speed SFP+ support */
-                mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
+
+        /* enable the laser control functions for SFP+ fiber */
+        if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
                 mac->ops.disable_tx_laser =
                                        &ixgbe_disable_tx_laser_multispeed_fiber;
                 mac->ops.enable_tx_laser =
@@ -80,6 +77,12 @@ static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
                 mac->ops.disable_tx_laser = NULL;
                 mac->ops.enable_tx_laser = NULL;
                 mac->ops.flap_tx_laser = NULL;
+        }
+
+        if (hw->phy.multispeed_fiber) {
+                /* Set up dual speed SFP+ support */
+                mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
+        } else {
                 if ((mac->ops.get_media_type(hw) ==
                      ixgbe_media_type_backplane) &&
                     (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
@@ -93,6 +96,8 @@ static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
 {
         s32 ret_val = 0;
+        u32 reg_anlp1 = 0;
+        u32 i = 0;
         u16 list_offset, data_offset, data_value;
 
         if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
@@ -119,14 +124,34 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
                         IXGBE_WRITE_FLUSH(hw);
                         hw->eeprom.ops.read(hw, ++data_offset, &data_value);
                 }
-                /* Now restart DSP by setting Restart_AN */
-                IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
-                    (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
 
                 /* Release the semaphore */
                 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
                 /* Delay obtaining semaphore again to allow FW access */
                 msleep(hw->eeprom.semaphore_delay);
+
+                /* Now restart DSP by setting Restart_AN and clearing LMS */
+                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
+                                IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
+                                IXGBE_AUTOC_AN_RESTART));
+
+                /* Wait for AN to leave state 0 */
+                for (i = 0; i < 10; i++) {
+                        msleep(4);
+                        reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
+                        if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
+                                break;
+                }
+                if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
+                        hw_dbg(hw, "sfp module setup not complete\n");
+                        ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
+                        goto setup_sfp_out;
+                }
+
+                /* Restart DSP by setting Restart_AN and return to SFI mode */
+                IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
+                                IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
+                                IXGBE_AUTOC_AN_RESTART));
         }
 
 setup_sfp_out:
@@ -174,7 +199,7 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
                 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
                 mac->ops.get_link_capabilities =
-                                  &ixgbe_get_copper_link_capabilities_82599;
+                        &ixgbe_get_copper_link_capabilities_generic;
         }
 
         /* Set necessary function pointers based on phy type */
@@ -184,6 +209,10 @@ static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
                 phy->ops.get_firmware_version =
                              &ixgbe_get_phy_firmware_version_tnx;
                 break;
+        case ixgbe_phy_aq:
+                phy->ops.get_firmware_version =
+                        &ixgbe_get_phy_firmware_version_generic;
+                break;
         default:
                 break;
         }
@@ -290,37 +319,6 @@ out:
 }
 
 /**
- *  ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
- *  @hw: pointer to hardware structure
- *  @speed: pointer to link speed
- *  @autoneg: boolean auto-negotiation value
- *
- *  Determines the link capabilities by reading the AUTOC register.
- **/
-static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
-                                                    ixgbe_link_speed *speed,
-                                                    bool *autoneg)
-{
-        s32 status = IXGBE_ERR_LINK_SETUP;
-        u16 speed_ability;
-
-        *speed = 0;
-        *autoneg = true;
-
-        status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
-                                      &speed_ability);
-
-        if (status == 0) {
-                if (speed_ability & MDIO_SPEED_10G)
-                    *speed |= IXGBE_LINK_SPEED_10GB_FULL;
-                if (speed_ability & MDIO_PMA_SPEED_1000)
-                    *speed |= IXGBE_LINK_SPEED_1GB_FULL;
-        }
-
-        return status;
-}
-
-/**
  *  ixgbe_get_media_type_82599 - Get media type
  *  @hw: pointer to hardware structure
  *
@@ -332,7 +330,8 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 
         /* Detect if there is a copper PHY attached. */
         if (hw->phy.type == ixgbe_phy_cu_unknown ||
-            hw->phy.type == ixgbe_phy_tn) {
+            hw->phy.type == ixgbe_phy_tn ||
+            hw->phy.type == ixgbe_phy_aq) {
                 media_type = ixgbe_media_type_copper;
                 goto out;
         }
@@ -342,11 +341,13 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
         case IXGBE_DEV_ID_82599_KX4_MEZZ:
         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
         case IXGBE_DEV_ID_82599_KR:
+        case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
         case IXGBE_DEV_ID_82599_XAUI_LOM:
                 /* Default device ID is mezzanine card KX/KX4 */
                 media_type = ixgbe_media_type_backplane;
                 break;
         case IXGBE_DEV_ID_82599_SFP:
+        case IXGBE_DEV_ID_82599_SFP_FCOE:
         case IXGBE_DEV_ID_82599_SFP_EM:
                 media_type = ixgbe_media_type_fiber;
                 break;
@@ -1002,7 +1003,7 @@ s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
                 udelay(10);
         }
         if (i >= IXGBE_FDIRCMD_CMD_POLL) {
-                hw_dbg(hw ,"Flow Director previous command isn't complete, "
+                hw_dbg(hw, "Flow Director previous command isn't complete, "
                        "aborting table re-initialization.\n");
                 return IXGBE_ERR_FDIR_REINIT_FAILED;
         }
@@ -1112,13 +1113,10 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
         /* Move the flexible bytes to use the ethertype - shift 6 words */
         fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 
-        fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 
         /* Prime the keys for hashing */
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
-                        htonl(IXGBE_ATR_BUCKET_HASH_KEY));
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-                        htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 
         /*
          * Poll init-done after we write the register.  Estimated times:
@@ -1208,10 +1206,8 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
         fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
 
         /* Prime the keys for hashing */
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
-                        htonl(IXGBE_ATR_BUCKET_HASH_KEY));
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
-                        htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 
         /*
          * Poll init-done after we write the register.  Estimated times:
@@ -1250,8 +1246,8 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
  *  @stream: input bitstream to compute the hash on
  *  @key: 32-bit hash key
  **/
-static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
-                                        u32 key)
+static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
+                                        u32 key)
 {
         /*
          * The algorithm is as follows:
@@ -1271,410 +1267,250 @@ static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
          *    To simplify for programming, the algorithm is implemented
          *    in software this way:
          *
-         *    Key[31:0], Stream[335:0]
+         *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
          *
-         *    tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
-         *    int_key[350:0] = tmp_key[351:1]
-         *    int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
+         *    for (i = 0; i < 352; i+=32)
+         *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
          *
-         *    hash[15:0] = 0;
-         *    for (i = 0; i < 351; i++) {
-         *        if (int_key[i])
-         *            hash ^= int_stream[(i + 15):i];
+         *    lo_hash_dword[15:0]  ^= Stream[15:0];
+         *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
+         *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
+         *
+         *    hi_hash_dword[31:0]  ^= Stream[351:320];
+         *
+         *    if(key[0])
+         *        hash[15:0] ^= Stream[15:0];
+         *
+         *    for (i = 0; i < 16; i++) {
+         *        if (key[i])
+         *            hash[15:0] ^= lo_hash_dword[(i+15):i];
+         *        if (key[i + 16])
+         *            hash[15:0] ^= hi_hash_dword[(i+15):i];
          *    }
+         *
          */
+        __be32 common_hash_dword = 0;
+        u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+        u32 hash_result = 0;
+        u8 i;
 
-        union {
-                u64    fill[6];
-                u32    key[11];
-                u8     key_stream[44];
-        } tmp_key;
+        /* record the flow_vm_vlan bits as they are a key part to the hash */
+        flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
 
-        u8   *stream = (u8 *)atr_input;
-        u8   int_key[44];      /* upper-most bit unused */
-        u8   hash_str[46];     /* upper-most 2 bits unused */
-        u16  hash_result = 0;
-        int  i, j, k, h;
+        /* generate common hash dword */
+        for (i = 10; i; i -= 2)
+                common_hash_dword ^= atr_input->dword_stream[i] ^
+                                     atr_input->dword_stream[i - 1];
 
-        /*
-         * Initialize the fill member to prevent warnings
-         * on some compilers
-         */
-         tmp_key.fill[0] = 0;
+        hi_hash_dword = ntohl(common_hash_dword);
 
-        /* First load the temporary key stream */
-        for (i = 0; i < 6; i++) {
-                u64 fillkey = ((u64)key << 32) | key;
-                tmp_key.fill[i] = fillkey;
-        }
+        /* low dword is word swapped version of common */
+        lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 
-        /*
-         * Set the interim key for the hashing.  Bit 352 is unused, so we must
-         * shift and compensate when building the key.
-         */
+        /* apply flow ID/VM pool/VLAN ID bits to hash words */
+        hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 
-        int_key[0] = tmp_key.key_stream[0] >> 1;
-        for (i = 1, j = 0; i < 44; i++) {
-                unsigned int this_key = tmp_key.key_stream[j] << 7;
-                j++;
-                int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
-        }
+        /* Process bits 0 and 16 */
+        if (key & 0x0001) hash_result ^= lo_hash_dword;
+        if (key & 0x00010000) hash_result ^= hi_hash_dword;
 
         /*
-         * Set the interim bit string for the hashing.  Bits 368 and 367 are
-         * unused, so shift and compensate when building the string.
+         * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+         * delay this because bit 0 of the stream should not be processed
+         * so we do not add the vlan until after bit 0 was processed
          */
-        hash_str[0] = (stream[40] & 0x7f) >> 1;
-        for (i = 1, j = 40; i < 46; i++) {
-                unsigned int this_str = stream[j] << 7;
-                j++;
-                if (j > 41)
-                        j = 0;
-                hash_str[i] = (u8)(this_str | (stream[j] >> 1));
-        }
-
-        /*
-         * Now compute the hash.  i is the index into hash_str, j is into our
-         * key stream, k is counting the number of bits, and h interates within
-         * each byte.
-         */
-        for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
-                for (h = 0; h < 8 && k < 351; h++, k++) {
-                        if (int_key[j] & (1 << h)) {
-                                /*
-                                 * Key bit is set, XOR in the current 16-bit
-                                 * string.  Example of processing:
-                                 *    h = 0,
-                                 *      tmp = (hash_str[i - 2] & 0 << 16) |
-                                 *            (hash_str[i - 1] & 0xff << 8) |
-                                 *            (hash_str[i] & 0xff >> 0)
-                                 *      So tmp = hash_str[15 + k:k], since the
-                                 *      i + 2 clause rolls off the 16-bit value
-                                 *    h = 7,
-                                 *      tmp = (hash_str[i - 2] & 0x7f << 9) |
-                                 *            (hash_str[i - 1] & 0xff << 1) |
-                                 *            (hash_str[i] & 0x80 >> 7)
-                                 */
-                                int tmp = (hash_str[i] >> h);
-                                tmp |= (hash_str[i - 1] << (8 - h));
-                                tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
-                                             << (16 - h);
-                                hash_result ^= (u16)tmp;
-                        }
-                }
-        }
-
-        return hash_result;
-}
-
-/**
- *  ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
- *  @input: input stream to modify
- *  @vlan: the VLAN id to load
- **/
-s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
-{
-        input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
-        input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
- *  @input: input stream to modify
- *  @src_addr: the IP address to load
- **/
-s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
-{
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
-                                                       (src_addr >> 16) & 0xff;
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
-                                                        (src_addr >> 8) & 0xff;
-        input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
- *  @input: input stream to modify
- *  @dst_addr: the IP address to load
- **/
-s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
-{
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
-                                                       (dst_addr >> 16) & 0xff;
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
-                                                        (dst_addr >> 8) & 0xff;
-        input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_src_port_82599 - Sets the source port
- *  @input: input stream to modify
- *  @src_port: the source port to load
- **/
-s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
-{
-        input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
-        input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_dst_port_82599 - Sets the destination port
- *  @input: input stream to modify
- *  @dst_port: the destination port to load
- **/
-s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
-{
-        input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
-        input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
- *  @input: input stream to modify
- *  @flex_bytes: the flexible bytes to load
- **/
-s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
-{
-        input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
-        input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
- *  @input: input stream to modify
- *  @l4type: the layer 4 type value to load
- **/
-s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
-{
-        input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
- *  @input: input stream to search
- *  @vlan: the VLAN id to load
- **/
-static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input, u16 *vlan)
-{
-        *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
-        *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
+        lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 
-        return 0;
-}
 
-/**
- *  ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
- *  @input: input stream to search
- *  @src_addr: the IP address to load
- **/
-static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 *src_addr)
-{
-        *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
-        *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
-        *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
-        *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
+        /* process the remaining 30 bits in the key 2 bits at a time */
+        for (i = 15; i; i-- ) {
+                if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
+                if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
+        }
 
-        return 0;
+        return hash_result & IXGBE_ATR_HASH_MASK;
 }
 
-/**
- *  ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
- *  @input: input stream to search
- *  @dst_addr: the IP address to load
- **/
-static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
-                                        u32 *dst_addr)
-{
-        *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
-        *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
-        *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
-        *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
-
-        return 0;
-}
+/*
+ * These defines allow us to quickly generate all of the necessary instructions
+ * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
+ * for values 0 through 15
+ */
+#define IXGBE_ATR_COMMON_HASH_KEY \
+                (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
+#define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
+do { \
+        u32 n = (_n); \
+        if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
+                common_hash ^= lo_hash_dword >> n; \
+        else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
+                bucket_hash ^= lo_hash_dword >> n; \
+        else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
+                sig_hash ^= lo_hash_dword << (16 - n); \
+        if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
+                common_hash ^= hi_hash_dword >> n; \
+        else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
+                bucket_hash ^= hi_hash_dword >> n; \
+        else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
+                sig_hash ^= hi_hash_dword << (16 - n); \
+} while (0);
 
 /**
- *  ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
- *  @input: input stream to search
- *  @src_addr_1: the first 4 bytes of the IP address to load
- *  @src_addr_2: the second 4 bytes of the IP address to load
- *  @src_addr_3: the third 4 bytes of the IP address to load
- *  @src_addr_4: the fourth 4 bytes of the IP address to load
- **/
-static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
-                                        u32 *src_addr_1, u32 *src_addr_2,
-                                        u32 *src_addr_3, u32 *src_addr_4)
-{
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
-        *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
-
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
-        *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
-
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
-        *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
-
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
-        *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
-
-        return 0;
-}
-
-/**
- *  ixgbe_atr_get_src_port_82599 - Gets the source port
- *  @input: input stream to modify
- *  @src_port: the source port to load
+ *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
+ *  @stream: input bitstream to compute the hash on
  *
- *  Even though the input is given in big-endian, the FDIRPORT registers
- *  expect the ports to be programmed in little-endian.  Hence the need to swap
- *  endianness when retrieving the data.  This can be confusing since the
- *  internal hash engine expects it to be big-endian.
+ *  This function is almost identical to the function above but contains
+ *  several optomizations such as unwinding all of the loops, letting the
+ *  compiler work out all of the conditional ifs since the keys are static
+ *  defines, and computing two keys at once since the hashed dword stream
+ *  will be the same for both keys.
  **/
-static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
-                                        u16 *src_port)
+static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
+                                            union ixgbe_atr_hash_dword common)
 {
-        *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
-        *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
+        u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
+        u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
 
-        return 0;
-}
+        /* record the flow_vm_vlan bits as they are a key part to the hash */
+        flow_vm_vlan = ntohl(input.dword);
 
-/**
- *  ixgbe_atr_get_dst_port_82599 - Gets the destination port
- *  @input: input stream to modify
- *  @dst_port: the destination port to load
- *
- *  Even though the input is given in big-endian, the FDIRPORT registers
- *  expect the ports to be programmed in little-endian.  Hence the need to swap
- *  endianness when retrieving the data.  This can be confusing since the
- *  internal hash engine expects it to be big-endian.
- **/
-static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
-                                        u16 *dst_port)
-{
-        *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
-        *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
+        /* generate common hash dword */
+        hi_hash_dword = ntohl(common.dword);
 
-        return 0;
-}
+        /* low dword is word swapped version of common */
+        lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 
-/**
- *  ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
- *  @input: input stream to modify
- *  @flex_bytes: the flexible bytes to load
- **/
-static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
-                                         u16 *flex_byte)
-{
-        *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
-        *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
+        /* apply flow ID/VM pool/VLAN ID bits to hash words */
+        hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 
-        return 0;
-}
+        /* Process bits 0 and 16 */
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
 
-/**
- *  ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
- *  @input: input stream to modify
- *  @l4type: the layer 4 type value to load
- **/
-static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
-                                      u8 *l4type)
-{
-        *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
+        /*
+         * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
+         * delay this because bit 0 of the stream should not be processed
+         * so we do not add the vlan until after bit 0 was processed
+         */
+        lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
+
+        /* Process remaining 30 bit of the key */
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
+        IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
+
+        /* combine common_hash result with signature and bucket hashes */
+        bucket_hash ^= common_hash;
+        bucket_hash &= IXGBE_ATR_HASH_MASK;
 
-        return 0;
+        sig_hash ^= common_hash << 16;
+        sig_hash &= IXGBE_ATR_HASH_MASK << 16;
+
+        /* return completed signature hash */
+        return sig_hash ^ bucket_hash;
 }
 
 /**
  *  ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
  *  @hw: pointer to hardware structure
- *  @stream: input bitstream
+ *  @input: unique input dword
+ *  @common: compressed common input dword
  *  @queue: queue index to direct traffic to
  **/
 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
-                                          struct ixgbe_atr_input *input,
+                                          union ixgbe_atr_hash_dword input,
+                                          union ixgbe_atr_hash_dword common,
                                           u8 queue)
 {
         u64  fdirhashcmd;
-        u64  fdircmd;
-        u32  fdirhash;
-        u16  bucket_hash, sig_hash;
-        u8   l4type;
-
-        bucket_hash = ixgbe_atr_compute_hash_82599(input,
-                                                   IXGBE_ATR_BUCKET_HASH_KEY);
-
-        /* bucket_hash is only 15 bits */
-        bucket_hash &= IXGBE_ATR_HASH_MASK;
-
-        sig_hash = ixgbe_atr_compute_hash_82599(input,
-                                                IXGBE_ATR_SIGNATURE_HASH_KEY);
-
-        /* Get the l4type in order to program FDIRCMD properly */
-        /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
-        ixgbe_atr_get_l4type_82599(input, &l4type);
+        u32  fdircmd;
 
         /*
-         * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
-         * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
+         * Get the flow_type in order to program FDIRCMD properly
+         * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
          */
-        fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
-
-        fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
-                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
-
-        switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-        case IXGBE_ATR_L4TYPE_TCP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
-                break;
-        case IXGBE_ATR_L4TYPE_UDP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
-                break;
-        case IXGBE_ATR_L4TYPE_SCTP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
+        switch (input.formatted.flow_type) {
+        case IXGBE_ATR_FLOW_TYPE_TCPV4:
+        case IXGBE_ATR_FLOW_TYPE_UDPV4:
+        case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+        case IXGBE_ATR_FLOW_TYPE_TCPV6:
+        case IXGBE_ATR_FLOW_TYPE_UDPV6:
+        case IXGBE_ATR_FLOW_TYPE_SCTPV6:
                 break;
         default:
-                hw_dbg(hw, "Error on l4type input\n");
+                hw_dbg(hw, " Error on flow type input\n");
                 return IXGBE_ERR_CONFIG;
         }
 
-        if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
-                fdircmd |= IXGBE_FDIRCMD_IPV6;
+        /* configure FDIRCMD register */
+        fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+                  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+        fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+        fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 
-        fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
-        fdirhashcmd = ((fdircmd << 32) | fdirhash);
+        /*
+         * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
+         * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
+         */
+        fdirhashcmd = (u64)fdircmd << 32;
+        fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
 
         IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
 
+        hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
+
         return 0;
 }
 
 /**
+ *  ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
+ *  @input_mask: mask to be bit swapped
+ *
+ *  The source and destination port masks for flow director are bit swapped
+ *  in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc.  In order to
+ *  generate a correctly swapped value we need to bit swap the mask and that
+ *  is what is accomplished by this function.
+ **/
+static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
+{
+        u32 mask = ntohs(input_masks->dst_port_mask);
+        mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
+        mask |= ntohs(input_masks->src_port_mask);
+        mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
+        mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
+        mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
+        return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
+}
+
+/*
+ * These two macros are meant to address the fact that we have registers
+ * that are either all or in part big-endian.  As a result on big-endian
+ * systems we will end up byte swapping the value to little-endian before
+ * it is byte swapped again and written to the hardware in the original
+ * big-endian format.
+ */
+#define IXGBE_STORE_AS_BE32(_value) \
+        (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
+         (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
+
+#define IXGBE_WRITE_REG_BE32(a, reg, value) \
+        IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
+
+#define IXGBE_STORE_AS_BE16(_value) \
+        (((u16)(_value) >> 8) | ((u16)(_value) << 8))
+
+/**
  *  ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
  *  @hw: pointer to hardware structure
  *  @input: input bitstream
@@ -1686,135 +1522,139 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
  *  hardware writes must be protected from one another.
  **/
 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
-                                      struct ixgbe_atr_input *input,
+                                      union ixgbe_atr_input *input,
                                       struct ixgbe_atr_input_masks *input_masks,
                                       u16 soft_id, u8 queue)
 {
-        u32 fdircmd = 0;
         u32 fdirhash;
-        u32 src_ipv4 = 0, dst_ipv4 = 0;
-        u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
-        u16 src_port, dst_port, vlan_id, flex_bytes;
-        u16 bucket_hash;
-        u8  l4type;
-        u8  fdirm = 0;
-
-        /* Get our input values */
-        ixgbe_atr_get_l4type_82599(input, &l4type);
+        u32 fdircmd;
+        u32 fdirport, fdirtcpm;
+        u32 fdirvlan;
+        /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
+        u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
+                    IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
 
         /*
-         * Check l4type formatting, and bail out before we touch the hardware
+         * Check flow_type formatting, and bail out before we touch the hardware
          * if there's a configuration issue
          */
-        switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-        case IXGBE_ATR_L4TYPE_TCP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
-                break;
-        case IXGBE_ATR_L4TYPE_UDP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
-                break;
-        case IXGBE_ATR_L4TYPE_SCTP:
-                fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
+        switch (input->formatted.flow_type) {
+        case IXGBE_ATR_FLOW_TYPE_IPV4:
+                /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
+                fdirm |= IXGBE_FDIRM_L4P;
+        case IXGBE_ATR_FLOW_TYPE_SCTPV4:
+                if (input_masks->dst_port_mask || input_masks->src_port_mask) {
+                        hw_dbg(hw, " Error on src/dst port mask\n");
+                        return IXGBE_ERR_CONFIG;
+                }
+        case IXGBE_ATR_FLOW_TYPE_TCPV4:
+        case IXGBE_ATR_FLOW_TYPE_UDPV4:
                 break;
         default:
-                hw_dbg(hw, "Error on l4type input\n");
+                hw_dbg(hw, " Error on flow type input\n");
                 return IXGBE_ERR_CONFIG;
         }
 
-        bucket_hash = ixgbe_atr_compute_hash_82599(input,
-                                                   IXGBE_ATR_BUCKET_HASH_KEY);
-
-        /* bucket_hash is only 15 bits */
-        bucket_hash &= IXGBE_ATR_HASH_MASK;
-
-        ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
-        ixgbe_atr_get_src_port_82599(input, &src_port);
-        ixgbe_atr_get_dst_port_82599(input, &dst_port);
-        ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
-
-        fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
-
-        /* Now figure out if we're IPv4 or IPv6 */
-        if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
-                /* IPv6 */
-                ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
-                                             &src_ipv6_3, &src_ipv6_4);
-
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
-                /* The last 4 bytes is the same register as IPv4 */
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
-
-                fdircmd |= IXGBE_FDIRCMD_IPV6;
-                fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
-        } else {
-                /* IPv4 */
-                ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
-        }
-
-        ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
-
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
-                                    (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
-                      (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
-
         /*
-         * Program the relevant mask registers.  L4type cannot be
-         * masked out in this implementation.
+         * Program the relevant mask registers.  If src/dst_port or src/dst_addr
+         * are zero, then assume a full mask for that field.  Also assume that
+         * a VLAN of 0 is unspecified, so mask that out as well.  L4type
+         * cannot be masked out in this implementation.
          *
          * This also assumes IPv4 only.  IPv6 masking isn't supported at this
          * point in time.
          */
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, input_masks->src_ip_mask);
-        IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, input_masks->dst_ip_mask);
-
-        switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
-        case IXGBE_ATR_L4TYPE_TCP:
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, input_masks->src_port_mask);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM,
-                                (IXGBE_READ_REG(hw, IXGBE_FDIRTCPM) |
-                                 (input_masks->dst_port_mask << 16)));
+
+        /* Program FDIRM */
+        switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
+        case 0xEFFF:
+                /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
+                fdirm &= ~IXGBE_FDIRM_VLANID;
+        case 0xE000:
+                /* Unmask VLAN prio - bit 1 */
+                fdirm &= ~IXGBE_FDIRM_VLANP;
                 break;
-        case IXGBE_ATR_L4TYPE_UDP:
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, input_masks->src_port_mask);
-                IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM,
-                                (IXGBE_READ_REG(hw, IXGBE_FDIRUDPM) |
-                                 (input_masks->src_port_mask << 16)));
+        case 0x0FFF:
+                /* Unmask VLAN ID - bit 0 */
+                fdirm &= ~IXGBE_FDIRM_VLANID;
                 break;
-        default:
-                /* this already would have failed above */
+        case 0x0000:
+                /* do nothing, vlans already masked */
                 break;
+        default:
+                hw_dbg(hw, " Error on VLAN mask\n");
+                return IXGBE_ERR_CONFIG;
         }
 
-        /* Program the last mask register, FDIRM */
-        if (input_masks->vlan_id_mask)
-                /* Mask both VLAN and VLANP - bits 0 and 1 */
-                fdirm |= 0x3;
-
-        if (input_masks->data_mask)
-                /* Flex bytes need masking, so mask the whole thing - bit 4 */
-                fdirm |= 0x10;
+        if (input_masks->flex_mask & 0xFFFF) {
+                if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
+                        hw_dbg(hw, " Error on flexible byte mask\n");
+                        return IXGBE_ERR_CONFIG;
+                }
+                /* Unmask Flex Bytes - bit 4 */
+                fdirm &= ~IXGBE_FDIRM_FLEX;
+        }
 
         /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
-        fdirm |= 0x24;
-
         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 
-        fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
-        fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
-        fdircmd |= IXGBE_FDIRCMD_LAST;
-        fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
-        fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+        /* store the TCP/UDP port masks, bit reversed from port layout */
+        fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
+
+        /* write both the same so that UDP and TCP use the same mask */
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
+
+        /* store source and destination IP masks (big-enian) */
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
+                             ~input_masks->src_ip_mask[0]);
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
+                             ~input_masks->dst_ip_mask[0]);
+
+        /* Apply masks to input data */
+        input->formatted.vlan_id &= input_masks->vlan_id_mask;
+        input->formatted.flex_bytes &= input_masks->flex_mask;
+        input->formatted.src_port &= input_masks->src_port_mask;
+        input->formatted.dst_port &= input_masks->dst_port_mask;
+        input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
+        input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
+
+        /* record vlan (little-endian) and flex_bytes(big-endian) */
+        fdirvlan =
+                IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
+        fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
+        fdirvlan |= ntohs(input->formatted.vlan_id);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
+
+        /* record source and destination port (little-endian)*/
+        fdirport = ntohs(input->formatted.dst_port);
+        fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
+        fdirport |= ntohs(input->formatted.src_port);
+        IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
+
+        /* record the first 32 bits of the destination address (big-endian) */
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
+
+        /* record the source address (big-endian) */
+        IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
+
+        /* configure FDIRCMD register */
+        fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
+                  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
+        fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
+        fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
+
+        /* we only want the bucket hash so drop the upper 16 bits */
+        fdirhash = ixgbe_atr_compute_hash_82599(input,
+                                                IXGBE_ATR_BUCKET_HASH_KEY);
+        fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
 
         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
 
         return 0;
 }
+
 /**
  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
  *  @hw: pointer to hardware structure
@@ -1924,6 +1764,7 @@ static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
         hw->phy.ops.identify(hw);
 
         if (hw->phy.type == ixgbe_phy_tn ||
+            hw->phy.type == ixgbe_phy_aq ||
             hw->phy.type == ixgbe_phy_cu_unknown) {
                 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
                                      &ext_ability);
@@ -2125,51 +1966,6 @@ fw_version_out:
         return status;
 }
 
-/**
- *  ixgbe_get_wwn_prefix_82599 - Get alternative WWNN/WWPN prefix from
- *  the EEPROM
- *  @hw: pointer to hardware structure
- *  @wwnn_prefix: the alternative WWNN prefix
- *  @wwpn_prefix: the alternative WWPN prefix
- *
- *  This function will read the EEPROM from the alternative SAN MAC address
- *  block to check the support for the alternative WWNN/WWPN prefix support.
- **/
-static s32 ixgbe_get_wwn_prefix_82599(struct ixgbe_hw *hw, u16 *wwnn_prefix,
-                                      u16 *wwpn_prefix)
-{
-        u16 offset, caps;
-        u16 alt_san_mac_blk_offset;
-
-        /* clear output first */
-        *wwnn_prefix = 0xFFFF;
-        *wwpn_prefix = 0xFFFF;
-
-        /* check if alternative SAN MAC is supported */
-        hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
-                            &alt_san_mac_blk_offset);
-
-        if ((alt_san_mac_blk_offset == 0) ||
-            (alt_san_mac_blk_offset == 0xFFFF))
-                goto wwn_prefix_out;
-
-        /* check capability in alternative san mac address block */
-        offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
-        hw->eeprom.ops.read(hw, offset, &caps);
-        if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
-                goto wwn_prefix_out;
-
-        /* get the corresponding prefix for WWNN/WWPN */
-        offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
-        hw->eeprom.ops.read(hw, offset, wwnn_prefix);
-
-        offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
-        hw->eeprom.ops.read(hw, offset, wwpn_prefix);
-
-wwn_prefix_out:
-        return 0;
-}
-
 static struct ixgbe_mac_operations mac_ops_82599 = {
         .init_hw                = &ixgbe_init_hw_generic,
         .reset_hw               = &ixgbe_reset_hw_82599,
@@ -2181,7 +1977,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
         .get_device_caps        = &ixgbe_get_device_caps_82599,
-        .get_wwn_prefix         = &ixgbe_get_wwn_prefix_82599,
+        .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
         .stop_adapter           = &ixgbe_stop_adapter_generic,
         .get_bus_info           = &ixgbe_get_bus_info_generic,
         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
@@ -2208,12 +2004,15 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
         .fc_enable              = &ixgbe_fc_enable_generic,
         .init_uta_tables        = &ixgbe_init_uta_tables_generic,
         .setup_sfp              = &ixgbe_setup_sfp_modules_82599,
+        .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
+        .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
 };
 
 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
         .init_params            = &ixgbe_init_eeprom_params_generic,
         .read                   = &ixgbe_read_eerd_generic,
         .write                  = &ixgbe_write_eeprom_generic,
+        .calc_checksum          = &ixgbe_calc_eeprom_checksum_generic,
         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
 };
@@ -2240,5 +2039,5 @@ struct ixgbe_info ixgbe_82599_info = {
         .mac_ops                = &mac_ops_82599,
         .eeprom_ops             = &eeprom_ops_82599,
         .phy_ops                = &phy_ops_82599,
-        .mbx_ops                = &mbx_ops_82599,
+        .mbx_ops                = &mbx_ops_generic,
 };
diff --git a/drivers/net/ixgbe/ixgbe_common.c b/drivers/net/ixgbe/ixgbe_common.c
index e3eca1316389..d5ede2df3e42 100644
--- a/drivers/net/ixgbe/ixgbe_common.c
+++ b/drivers/net/ixgbe/ixgbe_common.c
@@ -45,14 +45,12 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
-static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
 
 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num);
-static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
 
 /**
  *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
@@ -198,30 +196,110 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
 }
 
 /**
- *  ixgbe_read_pba_num_generic - Reads part number from EEPROM
+ *  ixgbe_read_pba_string_generic - Reads part number string from EEPROM
  *  @hw: pointer to hardware structure
- *  @pba_num: stores the part number from the EEPROM
+ *  @pba_num: stores the part number string from the EEPROM
+ *  @pba_num_size: part number string buffer length
  *
- *  Reads the part number from the EEPROM.
+ *  Reads the part number string from the EEPROM.
  **/
-s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
+s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
+                                  u32 pba_num_size)
 {
         s32 ret_val;
         u16 data;
+        u16 pba_ptr;
+        u16 offset;
+        u16 length;
+
+        if (pba_num == NULL) {
+                hw_dbg(hw, "PBA string buffer was null\n");
+                return IXGBE_ERR_INVALID_ARGUMENT;
+        }
 
         ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
         if (ret_val) {
                 hw_dbg(hw, "NVM Read Error\n");
                 return ret_val;
         }
-        *pba_num = (u32)(data << 16);
 
-        ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
+        ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
         if (ret_val) {
                 hw_dbg(hw, "NVM Read Error\n");
                 return ret_val;
         }
-        *pba_num |= data;
+
+        /*
+         * if data is not ptr guard the PBA must be in legacy format which
+         * means pba_ptr is actually our second data word for the PBA number
+         * and we can decode it into an ascii string
+         */
+        if (data != IXGBE_PBANUM_PTR_GUARD) {
+                hw_dbg(hw, "NVM PBA number is not stored as string\n");
+
+                /* we will need 11 characters to store the PBA */
+                if (pba_num_size < 11) {
+                        hw_dbg(hw, "PBA string buffer too small\n");
+                        return IXGBE_ERR_NO_SPACE;
+                }
+
+                /* extract hex string from data and pba_ptr */
+                pba_num[0] = (data >> 12) & 0xF;
+                pba_num[1] = (data >> 8) & 0xF;
+                pba_num[2] = (data >> 4) & 0xF;
+                pba_num[3] = data & 0xF;
+                pba_num[4] = (pba_ptr >> 12) & 0xF;
+                pba_num[5] = (pba_ptr >> 8) & 0xF;
+                pba_num[6] = '-';
+                pba_num[7] = 0;
+                pba_num[8] = (pba_ptr >> 4) & 0xF;
+                pba_num[9] = pba_ptr & 0xF;
+
+                /* put a null character on the end of our string */
+                pba_num[10] = '\0';
+
+                /* switch all the data but the '-' to hex char */
+                for (offset = 0; offset < 10; offset++) {
+                        if (pba_num[offset] < 0xA)
+                                pba_num[offset] += '0';
+                        else if (pba_num[offset] < 0x10)
+                                pba_num[offset] += 'A' - 0xA;
+                }
+
+                return 0;
+        }
+
+        ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
+        if (ret_val) {
+                hw_dbg(hw, "NVM Read Error\n");
+                return ret_val;
+        }
+
+        if (length == 0xFFFF || length == 0) {
+                hw_dbg(hw, "NVM PBA number section invalid length\n");
+                return IXGBE_ERR_PBA_SECTION;
+        }
+
+        /* check if pba_num buffer is big enough */
+        if (pba_num_size  < (((u32)length * 2) - 1)) {
+                hw_dbg(hw, "PBA string buffer too small\n");
+                return IXGBE_ERR_NO_SPACE;
+        }
+
+        /* trim pba length from start of string */
+        pba_ptr++;
+        length--;
+
+        for (offset = 0; offset < length; offset++) {
+                ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
+                if (ret_val) {
+                        hw_dbg(hw, "NVM Read Error\n");
+                        return ret_val;
+                }
+                pba_num[offset * 2] = (u8)(data >> 8);
+                pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
+        }
+        pba_num[offset * 2] = '\0';
 
         return 0;
 }
@@ -638,7 +716,7 @@ out:
  *  Polls the status bit (bit 1) of the EERD or EEWR to determine when the
  *  read or write is done respectively.
  **/
-static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
+s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
 {
         u32 i;
         u32 reg;
@@ -1009,7 +1087,7 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
  *  ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
  *  @hw: pointer to hardware structure
  **/
-static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
+u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
 {
         u16 i;
         u16 j;
@@ -1072,7 +1150,7 @@ s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
         status = hw->eeprom.ops.read(hw, 0, &checksum);
 
         if (status == 0) {
-                checksum = ixgbe_calc_eeprom_checksum(hw);
+                checksum = hw->eeprom.ops.calc_checksum(hw);
 
                 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
 
@@ -1110,7 +1188,7 @@ s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
         status = hw->eeprom.ops.read(hw, 0, &checksum);
 
         if (status == 0) {
-                checksum = ixgbe_calc_eeprom_checksum(hw);
+                checksum = hw->eeprom.ops.calc_checksum(hw);
                 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
                                             checksum);
         } else {
@@ -1595,6 +1673,7 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
         u32 mflcn_reg, fccfg_reg;
         u32 reg;
         u32 rx_pba_size;
+        u32 fcrtl, fcrth;
 
 #ifdef CONFIG_DCB
         if (hw->fc.requested_mode == ixgbe_fc_pfc)
@@ -1671,41 +1750,21 @@ s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
 
-        reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
-        /* Thresholds are different for link flow control when in DCB mode */
-        if (reg & IXGBE_MTQC_RT_ENA) {
-                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+        rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
+        rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
 
-                /* Always disable XON for LFC when in DCB mode */
-                reg = (rx_pba_size >> 5) & 0xFFE0;
-                IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
+        fcrth = (rx_pba_size - hw->fc.high_water) << 10;
+        fcrtl = (rx_pba_size - hw->fc.low_water) << 10;
 
-                reg = (rx_pba_size >> 2) & 0xFFE0;
-                if (hw->fc.current_mode & ixgbe_fc_tx_pause)
-                        reg |= IXGBE_FCRTH_FCEN;
-                IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
-        } else {
-                /*
-                 * Set up and enable Rx high/low water mark thresholds,
-                 * enable XON.
-                 */
-                if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
-                        if (hw->fc.send_xon) {
-                                IXGBE_WRITE_REG(hw,
-                                              IXGBE_FCRTL_82599(packetbuf_num),
-                                              (hw->fc.low_water |
-                                              IXGBE_FCRTL_XONE));
-                        } else {
-                                IXGBE_WRITE_REG(hw,
-                                              IXGBE_FCRTL_82599(packetbuf_num),
-                                              hw->fc.low_water);
-                        }
-
-                        IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
-                                       (hw->fc.high_water | IXGBE_FCRTH_FCEN));
-                }
+        if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
+                fcrth |= IXGBE_FCRTH_FCEN;
+                if (hw->fc.send_xon)
+                        fcrtl |= IXGBE_FCRTL_XONE;
         }
 
+        IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), fcrth);
+        IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), fcrtl);
+
         /* Configure pause time (2 TCs per register) */
         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
         if ((packetbuf_num & 1) == 0)
@@ -2705,3 +2764,112 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 
         return 0;
 }
+
+/**
+ *  ixgbe_get_wwn_prefix_generic Get alternative WWNN/WWPN prefix from
+ *  the EEPROM
+ *  @hw: pointer to hardware structure
+ *  @wwnn_prefix: the alternative WWNN prefix
+ *  @wwpn_prefix: the alternative WWPN prefix
+ *
+ *  This function will read the EEPROM from the alternative SAN MAC address
+ *  block to check the support for the alternative WWNN/WWPN prefix support.
+ **/
+s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
+                                        u16 *wwpn_prefix)
+{
+        u16 offset, caps;
+        u16 alt_san_mac_blk_offset;
+
+        /* clear output first */
+        *wwnn_prefix = 0xFFFF;
+        *wwpn_prefix = 0xFFFF;
+
+        /* check if alternative SAN MAC is supported */
+        hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
+                            &alt_san_mac_blk_offset);
+
+        if ((alt_san_mac_blk_offset == 0) ||
+            (alt_san_mac_blk_offset == 0xFFFF))
+                goto wwn_prefix_out;
+
+        /* check capability in alternative san mac address block */
+        offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
+        hw->eeprom.ops.read(hw, offset, &caps);
+        if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
+                goto wwn_prefix_out;
+
+        /* get the corresponding prefix for WWNN/WWPN */
+        offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
+        hw->eeprom.ops.read(hw, offset, wwnn_prefix);
+
+        offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
+        hw->eeprom.ops.read(hw, offset, wwpn_prefix);
+
+wwn_prefix_out:
+        return 0;
+}
+
+/**
+ *  ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
+ *  @hw: pointer to hardware structure
+ *  @enable: enable or disable switch for anti-spoofing
+ *  @pf: Physical Function pool - do not enable anti-spoofing for the PF
+ *
+ **/
+void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
+{
+        int j;
+        int pf_target_reg = pf >> 3;
+        int pf_target_shift = pf % 8;
+        u32 pfvfspoof = 0;
+
+        if (hw->mac.type == ixgbe_mac_82598EB)
+                return;
+
+        if (enable)
+                pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
+
+        /*
+         * PFVFSPOOF register array is size 8 with 8 bits assigned to
+         * MAC anti-spoof enables in each register array element.
+         */
+        for (j = 0; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
+                IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
+
+        /* If not enabling anti-spoofing then done */
+        if (!enable)
+                return;
+
+        /*
+         * The PF should be allowed to spoof so that it can support
+         * emulation mode NICs.  Reset the bit assigned to the PF
+         */
+        pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg));
+        pfvfspoof ^= (1 << pf_target_shift);
+        IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(pf_target_reg), pfvfspoof);
+}
+
+/**
+ *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
+ *  @hw: pointer to hardware structure
+ *  @enable: enable or disable switch for VLAN anti-spoofing
+ *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
+ *
+ **/
+void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
+{
+        int vf_target_reg = vf >> 3;
+        int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
+        u32 pfvfspoof;
+
+        if (hw->mac.type == ixgbe_mac_82598EB)
+                return;
+
+        pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
+        if (enable)
+                pfvfspoof |= (1 << vf_target_shift);
+        else
+                pfvfspoof &= ~(1 << vf_target_shift);
+        IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
+}
diff --git a/drivers/net/ixgbe/ixgbe_common.h b/drivers/net/ixgbe/ixgbe_common.h
index 424c223437dc..66ed045a8cf0 100644
--- a/drivers/net/ixgbe/ixgbe_common.h
+++ b/drivers/net/ixgbe/ixgbe_common.h
@@ -35,7 +35,8 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw);
 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw);
 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw);
 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw);
-s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
+s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
+                                  u32 pba_num_size);
 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
@@ -49,9 +50,11 @@ s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);
 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data);
 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
                                        u16 *data);
+u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw);
 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
                                            u16 *checksum_val);
 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw);
+s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
 
 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
                           u32 enable_addr);
@@ -81,9 +84,12 @@ s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw);
 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw,
                                  ixgbe_link_speed *speed,
                                  bool *link_up, bool link_up_wait_to_complete);
-
+s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
+                                 u16 *wwpn_prefix);
 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index);
 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index);
+void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf);
+void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf);
 
 #define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
 
diff --git a/drivers/net/ixgbe/ixgbe_dcb.c b/drivers/net/ixgbe/ixgbe_dcb.c
index 0d44c6470ca3..d16c260c1f50 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.c
+++ b/drivers/net/ixgbe/ixgbe_dcb.c
@@ -42,7 +42,8 @@
  * It should be called only after the rules are checked by
  * ixgbe_dcb_check_config().
  */
-s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
+s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *hw,
+                                   struct ixgbe_dcb_config *dcb_config,
                                    int max_frame, u8 direction)
 {
         struct tc_bw_alloc *p;
@@ -124,7 +125,8 @@ s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *dcb_config,
                          * credit may not be enough to send out a TSO
                          * packet in descriptor plane arbitration.
                          */
-                        if (credit_max &&
+                        if ((hw->mac.type == ixgbe_mac_82598EB) &&
+                            credit_max &&
                             (credit_max < MINIMUM_CREDIT_FOR_TSO))
                                 credit_max = MINIMUM_CREDIT_FOR_TSO;
 
@@ -150,10 +152,17 @@ s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw,
                         struct ixgbe_dcb_config *dcb_config)
 {
         s32 ret = 0;
-        if (hw->mac.type == ixgbe_mac_82598EB)
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
                 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config);
-        else if (hw->mac.type == ixgbe_mac_82599EB)
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config);
+                break;
+        default:
+                break;
+        }
         return ret;
 }
 
diff --git a/drivers/net/ixgbe/ixgbe_dcb.h b/drivers/net/ixgbe/ixgbe_dcb.h
index 0208a87b129e..1cfe38ee1644 100644
--- a/drivers/net/ixgbe/ixgbe_dcb.h
+++ b/drivers/net/ixgbe/ixgbe_dcb.h
@@ -150,7 +150,8 @@ struct ixgbe_dcb_config {
 /* DCB driver APIs */
 
 /* DCB credits calculation */
-s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_dcb_config *, int, u8);
+s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
+                                   struct ixgbe_dcb_config *, int, u8);
 
 /* DCB hw initialization */
 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82598.c b/drivers/net/ixgbe/ixgbe_dcb_82598.c
index 50288bcadc59..9a5e89c12e05 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82598.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82598.c
@@ -256,21 +256,17 @@ s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw,
          * for each traffic class.
          */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                if (dcb_config->rx_pba_cfg == pba_equal) {
-                        rx_pba_size = IXGBE_RXPBSIZE_64KB;
-                } else {
-                        rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
-                                              : IXGBE_RXPBSIZE_48KB;
-                }
+                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
+                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
+                reg = (rx_pba_size - hw->fc.low_water) << 10;
 
-                reg = ((rx_pba_size >> 5) &  0xFFF0);
                 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
                     dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
                         reg |= IXGBE_FCRTL_XONE;
 
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), reg);
 
-                reg = ((rx_pba_size >> 2) & 0xFFF0);
+                reg = (rx_pba_size - hw->fc.high_water) << 10;
                 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx ||
                     dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full)
                         reg |= IXGBE_FCRTH_FCEN;
diff --git a/drivers/net/ixgbe/ixgbe_dcb_82599.c b/drivers/net/ixgbe/ixgbe_dcb_82599.c
index 05f224715073..374e1f74d0f5 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_82599.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_82599.c
@@ -251,19 +251,17 @@ s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw,
 
         /* Configure PFC Tx thresholds per TC */
         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
-                if (dcb_config->rx_pba_cfg == pba_equal)
-                        rx_pba_size = IXGBE_RXPBSIZE_64KB;
-                else
-                        rx_pba_size = (i < 4) ? IXGBE_RXPBSIZE_80KB
-                                              : IXGBE_RXPBSIZE_48KB;
+                rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
+                rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
+
+                reg = (rx_pba_size - hw->fc.low_water) << 10;
 
-                reg = ((rx_pba_size >> 5) & 0xFFE0);
                 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
                     dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
                         reg |= IXGBE_FCRTL_XONE;
                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), reg);
 
-                reg = ((rx_pba_size >> 2) & 0xFFE0);
+                reg = (rx_pba_size - hw->fc.high_water) << 10;
                 if (dcb_config->tc_config[i].dcb_pfc == pfc_enabled_full ||
                     dcb_config->tc_config[i].dcb_pfc == pfc_enabled_tx)
                         reg |= IXGBE_FCRTH_FCEN;
diff --git a/drivers/net/ixgbe/ixgbe_dcb_nl.c b/drivers/net/ixgbe/ixgbe_dcb_nl.c
index b53b465e24af..bf566e8a455e 100644
--- a/drivers/net/ixgbe/ixgbe_dcb_nl.c
+++ b/drivers/net/ixgbe/ixgbe_dcb_nl.c
@@ -130,15 +130,21 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
                         netdev->netdev_ops->ndo_stop(netdev);
                 ixgbe_clear_interrupt_scheme(adapter);
 
-                if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+                adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
+                switch (adapter->hw.mac.type) {
+                case ixgbe_mac_82598EB:
                         adapter->last_lfc_mode = adapter->hw.fc.current_mode;
                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
-                }
-                adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
-                if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+                        break;
+                case ixgbe_mac_82599EB:
+                case ixgbe_mac_X540:
                         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
                         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
+                        break;
+                default:
+                        break;
                 }
+
                 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
                 ixgbe_init_interrupt_scheme(adapter);
                 if (netif_running(netdev))
@@ -155,8 +161,14 @@ static u8 ixgbe_dcbnl_set_state(struct net_device *netdev, u8 state)
                         adapter->dcb_cfg.pfc_mode_enable = false;
                         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
                         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
-                        if (adapter->hw.mac.type == ixgbe_mac_82599EB)
+                        switch (adapter->hw.mac.type) {
+                        case ixgbe_mac_82599EB:
+                        case ixgbe_mac_X540:
                                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
+                                break;
+                        default:
+                                break;
+                        }
 
                         ixgbe_init_interrupt_scheme(adapter);
                         if (netif_running(netdev))
@@ -178,9 +190,14 @@ static void ixgbe_dcbnl_get_perm_hw_addr(struct net_device *netdev,
         for (i = 0; i < netdev->addr_len; i++)
                 perm_addr[i] = adapter->hw.mac.perm_addr[i];
 
-        if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 for (j = 0; j < netdev->addr_len; j++, i++)
                         perm_addr[i] = adapter->hw.mac.san_addr[j];
+                break;
+        default:
+                break;
         }
 }
 
@@ -366,15 +383,29 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
         }
 
         if (adapter->dcb_cfg.pfc_mode_enable) {
-                if ((adapter->hw.mac.type != ixgbe_mac_82598EB) &&
-                        (adapter->hw.fc.current_mode != ixgbe_fc_pfc))
-                        adapter->last_lfc_mode = adapter->hw.fc.current_mode;
+                switch (adapter->hw.mac.type) {
+                case ixgbe_mac_82599EB:
+                case ixgbe_mac_X540:
+                        if (adapter->hw.fc.current_mode != ixgbe_fc_pfc)
+                                adapter->last_lfc_mode =
+                                                  adapter->hw.fc.current_mode;
+                        break;
+                default:
+                        break;
+                }
                 adapter->hw.fc.requested_mode = ixgbe_fc_pfc;
         } else {
-                if (adapter->hw.mac.type != ixgbe_mac_82598EB)
-                        adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
-                else
+                switch (adapter->hw.mac.type) {
+                case ixgbe_mac_82598EB:
                         adapter->hw.fc.requested_mode = ixgbe_fc_none;
+                        break;
+                case ixgbe_mac_82599EB:
+                case ixgbe_mac_X540:
+                        adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
+                        break;
+                default:
+                        break;
+                }
         }
 
         if (adapter->dcb_set_bitmap & BIT_RESETLINK) {
diff --git a/drivers/net/ixgbe/ixgbe_ethtool.c b/drivers/net/ixgbe/ixgbe_ethtool.c
index 3dc731c22ff2..2002ea88ca2a 100644
--- a/drivers/net/ixgbe/ixgbe_ethtool.c
+++ b/drivers/net/ixgbe/ixgbe_ethtool.c
@@ -185,6 +185,16 @@ static int ixgbe_get_settings(struct net_device *netdev,
                                              ADVERTISED_FIBRE);
                         ecmd->port = PORT_FIBRE;
                         ecmd->autoneg = AUTONEG_DISABLE;
+                } else if ((hw->device_id == IXGBE_DEV_ID_82599_COMBO_BACKPLANE) ||
+                           (hw->device_id == IXGBE_DEV_ID_82599_KX4_MEZZ)) {
+                        ecmd->supported |= (SUPPORTED_1000baseT_Full |
+                                            SUPPORTED_Autoneg |
+                                            SUPPORTED_FIBRE);
+                        ecmd->advertising = (ADVERTISED_10000baseT_Full |
+                                             ADVERTISED_1000baseT_Full |
+                                             ADVERTISED_Autoneg |
+                                             ADVERTISED_FIBRE);
+                        ecmd->port = PORT_FIBRE;
                 } else {
                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
                                             SUPPORTED_FIBRE);
@@ -204,6 +214,7 @@ static int ixgbe_get_settings(struct net_device *netdev,
         /* Get PHY type */
         switch (adapter->hw.phy.type) {
         case ixgbe_phy_tn:
+        case ixgbe_phy_aq:
         case ixgbe_phy_cu_unknown:
                 /* Copper 10G-BASET */
                 ecmd->port = PORT_TP;
@@ -332,13 +343,6 @@ static void ixgbe_get_pauseparam(struct net_device *netdev,
         else
                 pause->autoneg = 1;
 
-#ifdef CONFIG_DCB
-        if (hw->fc.current_mode == ixgbe_fc_pfc) {
-                pause->rx_pause = 0;
-                pause->tx_pause = 0;
-        }
-
-#endif
         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
                 pause->rx_pause = 1;
         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
@@ -346,6 +350,11 @@ static void ixgbe_get_pauseparam(struct net_device *netdev,
         } else if (hw->fc.current_mode == ixgbe_fc_full) {
                 pause->rx_pause = 1;
                 pause->tx_pause = 1;
+#ifdef CONFIG_DCB
+        } else if (hw->fc.current_mode == ixgbe_fc_pfc) {
+                pause->rx_pause = 0;
+                pause->tx_pause = 0;
+#endif
         }
 }
 
@@ -363,7 +372,6 @@ static int ixgbe_set_pauseparam(struct net_device *netdev,
                 return -EINVAL;
 
 #endif
-
         fc = hw->fc;
 
         if (pause->autoneg != AUTONEG_ENABLE)
@@ -412,11 +420,6 @@ static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
         else
                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
 
-        if (netif_running(netdev))
-                ixgbe_reinit_locked(adapter);
-        else
-                ixgbe_reset(adapter);
-
         return 0;
 }
 
@@ -428,16 +431,21 @@ static u32 ixgbe_get_tx_csum(struct net_device *netdev)
 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 {
         struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        u32 feature_list;
 
-        if (data) {
-                netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
-                if (adapter->hw.mac.type == ixgbe_mac_82599EB)
-                        netdev->features |= NETIF_F_SCTP_CSUM;
-        } else {
-                netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
-                if (adapter->hw.mac.type == ixgbe_mac_82599EB)
-                        netdev->features &= ~NETIF_F_SCTP_CSUM;
+        feature_list = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                feature_list |= NETIF_F_SCTP_CSUM;
+                break;
+        default:
+                break;
         }
+        if (data)
+                netdev->features |= feature_list;
+        else
+                netdev->features &= ~feature_list;
 
         return 0;
 }
@@ -530,10 +538,20 @@ static void ixgbe_get_regs(struct net_device *netdev,
         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
-        for (i = 0; i < 8; i++)
-                regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
-        for (i = 0; i < 8; i++)
-                regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
+        for (i = 0; i < 8; i++) {
+                switch (hw->mac.type) {
+                case ixgbe_mac_82598EB:
+                        regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
+                        regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
+                        break;
+                case ixgbe_mac_82599EB:
+                        regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
+                        regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
+                        break;
+                default:
+                        break;
+                }
+        }
         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 
@@ -615,6 +633,7 @@ static void ixgbe_get_regs(struct net_device *netdev,
         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 
+        /* DCB */
         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
@@ -820,9 +839,10 @@ static void ixgbe_get_drvinfo(struct net_device *netdev,
         struct ixgbe_adapter *adapter = netdev_priv(netdev);
         char firmware_version[32];
 
-        strncpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
+        strncpy(drvinfo->driver, ixgbe_driver_name,
+                sizeof(drvinfo->driver) - 1);
         strncpy(drvinfo->version, ixgbe_driver_version,
-                sizeof(drvinfo->version));
+                sizeof(drvinfo->version) - 1);
 
         snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
                  (adapter->eeprom_version & 0xF000) >> 12,
@@ -905,13 +925,11 @@ static int ixgbe_set_ringparam(struct net_device *netdev,
                         memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
                                sizeof(struct ixgbe_ring));
                         temp_tx_ring[i].count = new_tx_count;
-                        err = ixgbe_setup_tx_resources(adapter,
-                                                       &temp_tx_ring[i]);
+                        err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
                         if (err) {
                                 while (i) {
                                         i--;
-                                        ixgbe_free_tx_resources(adapter,
-                                                              &temp_tx_ring[i]);
+                                        ixgbe_free_tx_resources(&temp_tx_ring[i]);
                                 }
                                 goto clear_reset;
                         }
@@ -930,13 +948,11 @@ static int ixgbe_set_ringparam(struct net_device *netdev,
                         memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
                                sizeof(struct ixgbe_ring));
                         temp_rx_ring[i].count = new_rx_count;
-                        err = ixgbe_setup_rx_resources(adapter,
-                                                       &temp_rx_ring[i]);
+                        err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
                         if (err) {
                                 while (i) {
                                         i--;
-                                        ixgbe_free_rx_resources(adapter,
-                                                              &temp_rx_ring[i]);
+                                        ixgbe_free_rx_resources(&temp_rx_ring[i]);
                                 }
                                 goto err_setup;
                         }
@@ -951,8 +967,7 @@ static int ixgbe_set_ringparam(struct net_device *netdev,
                 /* tx */
                 if (new_tx_count != adapter->tx_ring_count) {
                         for (i = 0; i < adapter->num_tx_queues; i++) {
-                                ixgbe_free_tx_resources(adapter,
-                                                        adapter->tx_ring[i]);
+                                ixgbe_free_tx_resources(adapter->tx_ring[i]);
                                 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
                                        sizeof(struct ixgbe_ring));
                         }
@@ -962,8 +977,7 @@ static int ixgbe_set_ringparam(struct net_device *netdev,
                 /* rx */
                 if (new_rx_count != adapter->rx_ring_count) {
                         for (i = 0; i < adapter->num_rx_queues; i++) {
-                                ixgbe_free_rx_resources(adapter,
-                                                        adapter->rx_ring[i]);
+                                ixgbe_free_rx_resources(adapter->rx_ring[i]);
                                 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
                                        sizeof(struct ixgbe_ring));
                         }
@@ -1144,7 +1158,7 @@ struct ixgbe_reg_test {
 #define TABLE64_TEST_HI 6
 
 /* default 82599 register test */
-static struct ixgbe_reg_test reg_test_82599[] = {
+static const struct ixgbe_reg_test reg_test_82599[] = {
         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
@@ -1168,7 +1182,7 @@ static struct ixgbe_reg_test reg_test_82599[] = {
 };
 
 /* default 82598 register test */
-static struct ixgbe_reg_test reg_test_82598[] = {
+static const struct ixgbe_reg_test reg_test_82598[] = {
         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
@@ -1195,18 +1209,22 @@ static struct ixgbe_reg_test reg_test_82598[] = {
         { 0, 0, 0, 0 }
 };
 
+static const u32 register_test_patterns[] = {
+        0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
+};
+
 #define REG_PATTERN_TEST(R, M, W)                                             \
 {                                                                             \
         u32 pat, val, before;                                                 \
-        const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
-        for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
+        for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) {      \
                 before = readl(adapter->hw.hw_addr + R);                      \
-                writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
+                writel((register_test_patterns[pat] & W),                     \
+                       (adapter->hw.hw_addr + R));                            \
                 val = readl(adapter->hw.hw_addr + R);                         \
-                if (val != (_test[pat] & W & M)) {                            \
-                        e_err(drv, "pattern test reg %04X failed: got "   \
-                              "0x%08X expected 0x%08X\n",                     \
-                              R, val, (_test[pat] & W & M));                \
+                if (val != (register_test_patterns[pat] & W & M)) {           \
+                        e_err(drv, "pattern test reg %04X failed: got "       \
+                              "0x%08X expected 0x%08X\n",                     \
+                              R, val, (register_test_patterns[pat] & W & M)); \
                         *data = R;                                            \
                         writel(before, adapter->hw.hw_addr + R);              \
                         return 1;                                             \
@@ -1233,16 +1251,24 @@ static struct ixgbe_reg_test reg_test_82598[] = {
 
 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
 {
-        struct ixgbe_reg_test *test;
+        const struct ixgbe_reg_test *test;
         u32 value, before, after;
         u32 i, toggle;
 
-        if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
-                toggle = 0x7FFFF30F;
-                test = reg_test_82599;
-        } else {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
                 toggle = 0x7FFFF3FF;
                 test = reg_test_82598;
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                toggle = 0x7FFFF30F;
+                test = reg_test_82599;
+                break;
+        default:
+                *data = 1;
+                return 1;
+                break;
         }
 
         /*
@@ -1451,25 +1477,28 @@ static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
-        reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx));
-        reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
-        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl);
+        ixgbe_disable_rx_queue(adapter, rx_ring);
 
         /* now Tx */
         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
 
-        if (hw->mac.type == ixgbe_mac_82599EB) {
+        switch (hw->mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
+                break;
+        default:
+                break;
         }
 
         ixgbe_reset(adapter);
 
-        ixgbe_free_tx_resources(adapter, &adapter->test_tx_ring);
-        ixgbe_free_rx_resources(adapter, &adapter->test_rx_ring);
+        ixgbe_free_tx_resources(&adapter->test_tx_ring);
+        ixgbe_free_rx_resources(&adapter->test_rx_ring);
 }
 
 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
@@ -1483,17 +1512,24 @@ static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
         /* Setup Tx descriptor ring and Tx buffers */
         tx_ring->count = IXGBE_DEFAULT_TXD;
         tx_ring->queue_index = 0;
+        tx_ring->dev = &adapter->pdev->dev;
+        tx_ring->netdev = adapter->netdev;
         tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
         tx_ring->numa_node = adapter->node;
 
-        err = ixgbe_setup_tx_resources(adapter, tx_ring);
+        err = ixgbe_setup_tx_resources(tx_ring);
         if (err)
                 return 1;
 
-        if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
                 reg_data |= IXGBE_DMATXCTL_TE;
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
+                break;
+        default:
+                break;
         }
 
         ixgbe_configure_tx_ring(adapter, tx_ring);
@@ -1501,11 +1537,13 @@ static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
         /* Setup Rx Descriptor ring and Rx buffers */
         rx_ring->count = IXGBE_DEFAULT_RXD;
         rx_ring->queue_index = 0;
+        rx_ring->dev = &adapter->pdev->dev;
+        rx_ring->netdev = adapter->netdev;
         rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
         rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
         rx_ring->numa_node = adapter->node;
 
-        err = ixgbe_setup_rx_resources(adapter, rx_ring);
+        err = ixgbe_setup_rx_resources(rx_ring);
         if (err) {
                 ret_val = 4;
                 goto err_nomem;
@@ -1604,8 +1642,7 @@ static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
         return 13;
 }
 
-static u16 ixgbe_clean_test_rings(struct ixgbe_adapter *adapter,
-                                  struct ixgbe_ring *rx_ring,
+static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
                                   struct ixgbe_ring *tx_ring,
                                   unsigned int size)
 {
@@ -1627,7 +1664,7 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_adapter *adapter,
                 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
 
                 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
-                dma_unmap_single(&adapter->pdev->dev,
+                dma_unmap_single(rx_ring->dev,
                                  rx_buffer_info->dma,
                                  bufsz,
                                  DMA_FROM_DEVICE);
@@ -1639,7 +1676,7 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_adapter *adapter,
 
                 /* unmap buffer on Tx side */
                 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
-                ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
+                ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
 
                 /* increment Rx/Tx next to clean counters */
                 rx_ntc++;
@@ -1655,7 +1692,7 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_adapter *adapter,
         }
 
         /* re-map buffers to ring, store next to clean values */
-        ixgbe_alloc_rx_buffers(adapter, rx_ring, count);
+        ixgbe_alloc_rx_buffers(rx_ring, count);
         rx_ring->next_to_clean = rx_ntc;
         tx_ring->next_to_clean = tx_ntc;
 
@@ -1699,7 +1736,6 @@ static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
                 for (i = 0; i < 64; i++) {
                         skb_get(skb);
                         tx_ret_val = ixgbe_xmit_frame_ring(skb,
-                                                           adapter->netdev,
                                                            adapter,
                                                            tx_ring);
                         if (tx_ret_val == NETDEV_TX_OK)
@@ -1714,8 +1750,7 @@ static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
                 /* allow 200 milliseconds for packets to go from Tx to Rx */
                 msleep(200);
 
-                good_cnt = ixgbe_clean_test_rings(adapter, rx_ring,
-                                                  tx_ring, size);
+                good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
                 if (good_cnt != 64) {
                         ret_val = 13;
                         break;
@@ -1847,7 +1882,25 @@ static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
         struct ixgbe_hw *hw = &adapter->hw;
         int retval = 1;
 
+        /* WOL not supported except for the following */
         switch(hw->device_id) {
+        case IXGBE_DEV_ID_82599_SFP:
+                /* Only this subdevice supports WOL */
+                if (hw->subsystem_device_id != IXGBE_SUBDEV_ID_82599_SFP) {
+                        wol->supported = 0;
+                        break;
+                }
+                retval = 0;
+                break;
+        case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
+                /* All except this subdevice support WOL */
+                if (hw->subsystem_device_id ==
+                    IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
+                        wol->supported = 0;
+                        break;
+                }
+                retval = 0;
+                break;
         case IXGBE_DEV_ID_82599_KX4:
                 retval = 0;
                 break;
@@ -1985,6 +2038,41 @@ static int ixgbe_get_coalesce(struct net_device *netdev,
         return 0;
 }
 
+/*
+ * this function must be called before setting the new value of
+ * rx_itr_setting
+ */
+static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
+                             struct ethtool_coalesce *ec)
+{
+        struct net_device *netdev = adapter->netdev;
+
+        if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
+                return false;
+
+        /* if interrupt rate is too high then disable RSC */
+        if (ec->rx_coalesce_usecs != 1 &&
+            ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
+                if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
+                        e_info(probe, "rx-usecs set too low, "
+                                      "disabling RSC\n");
+                        adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
+                        return true;
+                }
+        } else {
+                /* check the feature flag value and enable RSC if necessary */
+                if ((netdev->features & NETIF_F_LRO) &&
+                    !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
+                        e_info(probe, "rx-usecs set to %d, "
+                                      "re-enabling RSC\n",
+                               ec->rx_coalesce_usecs);
+                        adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
+                        return true;
+                }
+        }
+        return false;
+}
+
 static int ixgbe_set_coalesce(struct net_device *netdev,
                               struct ethtool_coalesce *ec)
 {
@@ -2002,17 +2090,14 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
                 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
 
         if (ec->rx_coalesce_usecs > 1) {
-                u32 max_int;
-                if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
-                        max_int = IXGBE_MAX_RSC_INT_RATE;
-                else
-                        max_int = IXGBE_MAX_INT_RATE;
-
                 /* check the limits */
-                if ((1000000/ec->rx_coalesce_usecs > max_int) ||
+                if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
                         return -EINVAL;
 
+                /* check the old value and enable RSC if necessary */
+                need_reset = ixgbe_update_rsc(adapter, ec);
+
                 /* store the value in ints/second */
                 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
 
@@ -2021,32 +2106,21 @@ static int ixgbe_set_coalesce(struct net_device *netdev,
                 /* clear the lower bit as its used for dynamic state */
                 adapter->rx_itr_setting &= ~1;
         } else if (ec->rx_coalesce_usecs == 1) {
+                /* check the old value and enable RSC if necessary */
+                need_reset = ixgbe_update_rsc(adapter, ec);
+
                 /* 1 means dynamic mode */
                 adapter->rx_eitr_param = 20000;
                 adapter->rx_itr_setting = 1;
         } else {
+                /* check the old value and enable RSC if necessary */
+                need_reset = ixgbe_update_rsc(adapter, ec);
                 /*
                  * any other value means disable eitr, which is best
                  * served by setting the interrupt rate very high
                  */
                 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
                 adapter->rx_itr_setting = 0;
-
-                /*
-                 * if hardware RSC is enabled, disable it when
-                 * setting low latency mode, to avoid errata, assuming
-                 * that when the user set low latency mode they want
-                 * it at the cost of anything else
-                 */
-                if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
-                        adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
-                        if (netdev->features & NETIF_F_LRO) {
-                                netdev->features &= ~NETIF_F_LRO;
-                                e_info(probe, "rx-usecs set to 0, "
-                                       "disabling RSC\n");
-                        }
-                        need_reset = true;
-                }
         }
 
         if (ec->tx_coalesce_usecs > 1) {
@@ -2127,34 +2201,45 @@ static int ixgbe_set_flags(struct net_device *netdev, u32 data)
         need_reset = (data & ETH_FLAG_RXVLAN) !=
                      (netdev->features & NETIF_F_HW_VLAN_RX);
 
-        rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO |
+        rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO | ETH_FLAG_NTUPLE |
                                         ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN);
         if (rc)
                 return rc;
 
         /* if state changes we need to update adapter->flags and reset */
-        if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) {
-                /*
-                 * cast both to bool and verify if they are set the same
-                 * but only enable RSC if itr is non-zero, as
-                 * itr=0 and RSC are mutually exclusive
-                 */
-                if (((!!(data & ETH_FLAG_LRO)) !=
-                     (!!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) &&
-                    adapter->rx_itr_setting) {
+        if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
+            (!!(data & ETH_FLAG_LRO) !=
+             !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
+                if ((data & ETH_FLAG_LRO) &&
+                    (!adapter->rx_itr_setting ||
+                     (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) {
+                        e_info(probe, "rx-usecs set too low, "
+                                      "not enabling RSC.\n");
+                } else {
                         adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
                         switch (adapter->hw.mac.type) {
                         case ixgbe_mac_82599EB:
                                 need_reset = true;
                                 break;
+                        case ixgbe_mac_X540: {
+                                int i;
+                                for (i = 0; i < adapter->num_rx_queues; i++) {
+                                        struct ixgbe_ring *ring =
+                                                          adapter->rx_ring[i];
+                                        if (adapter->flags2 &
+                                            IXGBE_FLAG2_RSC_ENABLED) {
+                                                ixgbe_configure_rscctl(adapter,
+                                                                       ring);
+                                        } else {
+                                                ixgbe_clear_rscctl(adapter,
+                                                                   ring);
+                                        }
+                                }
+                        }
+                                break;
                         default:
                                 break;
                         }
-                } else if (!adapter->rx_itr_setting) {
-                        netdev->features &= ~NETIF_F_LRO;
-                        if (data & ETH_FLAG_LRO)
-                                e_info(probe, "rx-usecs set to 0, "
-                                       "LRO/RSC cannot be enabled.\n");
                 }
         }
 
@@ -2192,10 +2277,11 @@ static int ixgbe_set_rx_ntuple(struct net_device *dev,
                                struct ethtool_rx_ntuple *cmd)
 {
         struct ixgbe_adapter *adapter = netdev_priv(dev);
-        struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
-        struct ixgbe_atr_input input_struct;
+        struct ethtool_rx_ntuple_flow_spec *fs = &cmd->fs;
+        union ixgbe_atr_input input_struct;
         struct ixgbe_atr_input_masks input_masks;
         int target_queue;
+        int err;
 
         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
                 return -EOPNOTSUPP;
@@ -2204,67 +2290,122 @@ static int ixgbe_set_rx_ntuple(struct net_device *dev,
          * Don't allow programming if the action is a queue greater than
          * the number of online Tx queues.
          */
-        if ((fs.action >= adapter->num_tx_queues) ||
-            (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
+        if ((fs->action >= adapter->num_tx_queues) ||
+            (fs->action < ETHTOOL_RXNTUPLE_ACTION_DROP))
                 return -EINVAL;
 
-        memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
+        memset(&input_struct, 0, sizeof(union ixgbe_atr_input));
         memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
 
-        input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
-        input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
-        input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
-        input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
-        input_masks.vlan_id_mask = fs.vlan_tag_mask;
-        /* only use the lowest 2 bytes for flex bytes */
-        input_masks.data_mask = (fs.data_mask & 0xffff);
-
-        switch (fs.flow_type) {
+        /* record flow type */
+        switch (fs->flow_type) {
+        case IPV4_FLOW:
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
+                break;
         case TCP_V4_FLOW:
-                ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
                 break;
         case UDP_V4_FLOW:
-                ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
                 break;
         case SCTP_V4_FLOW:
-                ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
+                input_struct.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
                 break;
         default:
                 return -1;
         }
 
-        /* Mask bits from the inputs based on user-supplied mask */
-        ixgbe_atr_set_src_ipv4_82599(&input_struct,
-                    (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
-        ixgbe_atr_set_dst_ipv4_82599(&input_struct,
-                    (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
-        /* 82599 expects these to be byte-swapped for perfect filtering */
-        ixgbe_atr_set_src_port_82599(&input_struct,
-               ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
-        ixgbe_atr_set_dst_port_82599(&input_struct,
-               ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
-
-        /* VLAN and Flex bytes are either completely masked or not */
-        if (!fs.vlan_tag_mask)
-                ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
-
-        if (!input_masks.data_mask)
-                /* make sure we only use the first 2 bytes of user data */
-                ixgbe_atr_set_flex_byte_82599(&input_struct,
-                                              (fs.data & 0xffff));
+        /* copy vlan tag minus the CFI bit */
+        if ((fs->vlan_tag & 0xEFFF) || (~fs->vlan_tag_mask & 0xEFFF)) {
+                input_struct.formatted.vlan_id = htons(fs->vlan_tag & 0xEFFF);
+                if (!fs->vlan_tag_mask) {
+                        input_masks.vlan_id_mask = htons(0xEFFF);
+                } else {
+                        switch (~fs->vlan_tag_mask & 0xEFFF) {
+                        /* all of these are valid vlan-mask values */
+                        case 0xEFFF:
+                        case 0xE000:
+                        case 0x0FFF:
+                        case 0x0000:
+                                input_masks.vlan_id_mask =
+                                        htons(~fs->vlan_tag_mask);
+                                break;
+                        /* exit with error if vlan-mask is invalid */
+                        default:
+                                e_err(drv, "Partial VLAN ID or "
+                                      "priority mask in vlan-mask is not "
+                                      "supported by hardware\n");
+                                return -1;
+                        }
+                }
+        }
+
+        /* make sure we only use the first 2 bytes of user data */
+        if ((fs->data & 0xFFFF) || (~fs->data_mask & 0xFFFF)) {
+                input_struct.formatted.flex_bytes = htons(fs->data & 0xFFFF);
+                if (!(fs->data_mask & 0xFFFF)) {
+                        input_masks.flex_mask = 0xFFFF;
+                } else if (~fs->data_mask & 0xFFFF) {
+                        e_err(drv, "Partial user-def-mask is not "
+                              "supported by hardware\n");
+                        return -1;
+                }
+        }
+
+        /*
+         * Copy input into formatted structures
+         *
+         * These assignments are based on the following logic
+         * If neither input or mask are set assume value is masked out.
+         * If input is set, but mask is not mask should default to accept all.
+         * If input is not set, but mask is set then mask likely results in 0.
+         * If input is set and mask is set then assign both.
+         */
+        if (fs->h_u.tcp_ip4_spec.ip4src || ~fs->m_u.tcp_ip4_spec.ip4src) {
+                input_struct.formatted.src_ip[0] = fs->h_u.tcp_ip4_spec.ip4src;
+                if (!fs->m_u.tcp_ip4_spec.ip4src)
+                        input_masks.src_ip_mask[0] = 0xFFFFFFFF;
+                else
+                        input_masks.src_ip_mask[0] =
+                                ~fs->m_u.tcp_ip4_spec.ip4src;
+        }
+        if (fs->h_u.tcp_ip4_spec.ip4dst || ~fs->m_u.tcp_ip4_spec.ip4dst) {
+                input_struct.formatted.dst_ip[0] = fs->h_u.tcp_ip4_spec.ip4dst;
+                if (!fs->m_u.tcp_ip4_spec.ip4dst)
+                        input_masks.dst_ip_mask[0] = 0xFFFFFFFF;
+                else
+                        input_masks.dst_ip_mask[0] =
+                                ~fs->m_u.tcp_ip4_spec.ip4dst;
+        }
+        if (fs->h_u.tcp_ip4_spec.psrc || ~fs->m_u.tcp_ip4_spec.psrc) {
+                input_struct.formatted.src_port = fs->h_u.tcp_ip4_spec.psrc;
+                if (!fs->m_u.tcp_ip4_spec.psrc)
+                        input_masks.src_port_mask = 0xFFFF;
+                else
+                        input_masks.src_port_mask = ~fs->m_u.tcp_ip4_spec.psrc;
+        }
+        if (fs->h_u.tcp_ip4_spec.pdst || ~fs->m_u.tcp_ip4_spec.pdst) {
+                input_struct.formatted.dst_port = fs->h_u.tcp_ip4_spec.pdst;
+                if (!fs->m_u.tcp_ip4_spec.pdst)
+                        input_masks.dst_port_mask = 0xFFFF;
+                else
+                        input_masks.dst_port_mask = ~fs->m_u.tcp_ip4_spec.pdst;
+        }
 
         /* determine if we need to drop or route the packet */
-        if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
+        if (fs->action == ETHTOOL_RXNTUPLE_ACTION_DROP)
                 target_queue = MAX_RX_QUEUES - 1;
         else
-                target_queue = fs.action;
+                target_queue = fs->action;
 
         spin_lock(&adapter->fdir_perfect_lock);
-        ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
-                                            &input_masks, 0, target_queue);
+        err = ixgbe_fdir_add_perfect_filter_82599(&adapter->hw,
+                                                  &input_struct,
+                                                  &input_masks, 0,
+                                                  target_queue);
         spin_unlock(&adapter->fdir_perfect_lock);
 
-        return 0;
+        return err ? -1 : 0;
 }
 
 static const struct ethtool_ops ixgbe_ethtool_ops = {
diff --git a/drivers/net/ixgbe/ixgbe_fcoe.c b/drivers/net/ixgbe/ixgbe_fcoe.c
index 05efa6a8ce8e..6342d4859790 100644
--- a/drivers/net/ixgbe/ixgbe_fcoe.c
+++ b/drivers/net/ixgbe/ixgbe_fcoe.c
@@ -68,7 +68,7 @@ static inline bool ixgbe_rx_is_fcoe(union ixgbe_adv_rx_desc *rx_desc)
 static inline void ixgbe_fcoe_clear_ddp(struct ixgbe_fcoe_ddp *ddp)
 {
         ddp->len = 0;
-        ddp->err = 0;
+        ddp->err = 1;
         ddp->udl = NULL;
         ddp->udp = 0UL;
         ddp->sgl = NULL;
@@ -92,6 +92,7 @@ int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
         struct ixgbe_fcoe *fcoe;
         struct ixgbe_adapter *adapter;
         struct ixgbe_fcoe_ddp *ddp;
+        u32 fcbuff;
 
         if (!netdev)
                 goto out_ddp_put;
@@ -115,7 +116,14 @@ int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid)
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCBUFF, 0);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
                                 (xid | IXGBE_FCDMARW_WE));
+
+                /* guaranteed to be invalidated after 100us */
+                IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCDMARW,
+                                (xid | IXGBE_FCDMARW_RE));
+                fcbuff = IXGBE_READ_REG(&adapter->hw, IXGBE_FCBUFF);
                 spin_unlock_bh(&fcoe->lock);
+                if (fcbuff & IXGBE_FCBUFF_VALID)
+                        udelay(100);
         }
         if (ddp->sgl)
                 pci_unmap_sg(adapter->pdev, ddp->sgl, ddp->sgc,
@@ -168,6 +176,11 @@ int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
                 return 0;
         }
 
+        /* no DDP if we are already down or resetting */
+        if (test_bit(__IXGBE_DOWN, &adapter->state) ||
+            test_bit(__IXGBE_RESETTING, &adapter->state))
+                return 0;
+
         fcoe = &adapter->fcoe;
         if (!fcoe->pool) {
                 e_warn(drv, "xid=0x%x no ddp pool for fcoe\n", xid);
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index eee0b298bd36..a060610a42db 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -52,13 +52,14 @@ char ixgbe_driver_name[] = "ixgbe";
 static const char ixgbe_driver_string[] =
                               "Intel(R) 10 Gigabit PCI Express Network Driver";
 
-#define DRV_VERSION "2.0.84-k2"
+#define DRV_VERSION "3.0.12-k2"
 const char ixgbe_driver_version[] = DRV_VERSION;
 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
 
 static const struct ixgbe_info *ixgbe_info_tbl[] = {
         [board_82598] = &ixgbe_82598_info,
         [board_82599] = &ixgbe_82599_info,
+        [board_X540] = &ixgbe_X540_info,
 };
 
 /* ixgbe_pci_tbl - PCI Device ID Table
@@ -108,10 +109,16 @@ static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
          board_82599 },
         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
          board_82599 },
+        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
+         board_82599 },
+        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
+         board_82599 },
         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
          board_82599 },
         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
          board_82599 },
+        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
+         board_X540 },
 
         /* required last entry */
         {0, }
@@ -560,6 +567,7 @@ static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
                 break;
         case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 if (direction == -1) {
                         /* other causes */
                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
@@ -589,29 +597,34 @@ static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 {
         u32 mask;
 
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
-        } else {
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 mask = (qmask & 0xFFFFFFFF);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
                 mask = (qmask >> 32);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
+                break;
+        default:
+                break;
         }
 }
 
-void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
-                                      struct ixgbe_tx_buffer
-                                      *tx_buffer_info)
+void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
+                                      struct ixgbe_tx_buffer *tx_buffer_info)
 {
         if (tx_buffer_info->dma) {
                 if (tx_buffer_info->mapped_as_page)
-                        dma_unmap_page(&adapter->pdev->dev,
+                        dma_unmap_page(tx_ring->dev,
                                        tx_buffer_info->dma,
                                        tx_buffer_info->length,
                                        DMA_TO_DEVICE);
                 else
-                        dma_unmap_single(&adapter->pdev->dev,
+                        dma_unmap_single(tx_ring->dev,
                                          tx_buffer_info->dma,
                                          tx_buffer_info->length,
                                          DMA_TO_DEVICE);
@@ -626,92 +639,166 @@ void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 }
 
 /**
- * ixgbe_tx_xon_state - check the tx ring xon state
- * @adapter: the ixgbe adapter
- * @tx_ring: the corresponding tx_ring
+ * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
+ * @adapter: driver private struct
+ * @index: reg idx of queue to query (0-127)
  *
- * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
- * corresponding TC of this tx_ring when checking TFCS.
+ * Helper function to determine the traffic index for a paticular
+ * register index.
  *
- * Returns : true if in xon state (currently not paused)
+ * Returns : a tc index for use in range 0-7, or 0-3
  */
-static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
-                                      struct ixgbe_ring *tx_ring)
+u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 {
-        u32 txoff = IXGBE_TFCS_TXOFF;
+        int tc = -1;
+        int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 
-#ifdef CONFIG_IXGBE_DCB
-        if (adapter->dcb_cfg.pfc_mode_enable) {
-                int tc;
-                int reg_idx = tx_ring->reg_idx;
-                int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
+        /* if DCB is not enabled the queues have no TC */
+        if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
+                return tc;
+
+        /* check valid range */
+        if (reg_idx >= adapter->hw.mac.max_tx_queues)
+                return tc;
+
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
+                tc = reg_idx >> 2;
+                break;
+        default:
+                if (dcb_i != 4 && dcb_i != 8)
+                        break;
+
+                /* if VMDq is enabled the lowest order bits determine TC */
+                if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
+                                      IXGBE_FLAG_VMDQ_ENABLED)) {
+                        tc = reg_idx & (dcb_i - 1);
+                        break;
+                }
+
+                /*
+                 * Convert the reg_idx into the correct TC. This bitmask
+                 * targets the last full 32 ring traffic class and assigns
+                 * it a value of 1. From there the rest of the rings are
+                 * based on shifting the mask further up to include the
+                 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
+                 * will only ever be 8 or 4 and that reg_idx will never
+                 * be greater then 128. The code without the power of 2
+                 * optimizations would be:
+                 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
+                 */
+                tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
+                tc >>= 9 - (reg_idx >> 5);
+        }
 
-                switch (adapter->hw.mac.type) {
+        return tc;
+}
+
+static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
+{
+        struct ixgbe_hw *hw = &adapter->hw;
+        struct ixgbe_hw_stats *hwstats = &adapter->stats;
+        u32 data = 0;
+        u32 xoff[8] = {0};
+        int i;
+
+        if ((hw->fc.current_mode == ixgbe_fc_full) ||
+            (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
+                switch (hw->mac.type) {
                 case ixgbe_mac_82598EB:
-                        tc = reg_idx >> 2;
-                        txoff = IXGBE_TFCS_TXOFF0;
+                        data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
                         break;
-                case ixgbe_mac_82599EB:
-                        tc = 0;
-                        txoff = IXGBE_TFCS_TXOFF;
-                        if (dcb_i == 8) {
-                                /* TC0, TC1 */
-                                tc = reg_idx >> 5;
-                                if (tc == 2) /* TC2, TC3 */
-                                        tc += (reg_idx - 64) >> 4;
-                                else if (tc == 3) /* TC4, TC5, TC6, TC7 */
-                                        tc += 1 + ((reg_idx - 96) >> 3);
-                        } else if (dcb_i == 4) {
-                                /* TC0, TC1 */
-                                tc = reg_idx >> 6;
-                                if (tc == 1) {
-                                        tc += (reg_idx - 64) >> 5;
-                                        if (tc == 2) /* TC2, TC3 */
-                                                tc += (reg_idx - 96) >> 4;
-                                }
-                        }
+                default:
+                        data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
+                }
+                hwstats->lxoffrxc += data;
+
+                /* refill credits (no tx hang) if we received xoff */
+                if (!data)
+                        return;
+
+                for (i = 0; i < adapter->num_tx_queues; i++)
+                        clear_bit(__IXGBE_HANG_CHECK_ARMED,
+                                  &adapter->tx_ring[i]->state);
+                return;
+        } else if (!(adapter->dcb_cfg.pfc_mode_enable))
+                return;
+
+        /* update stats for each tc, only valid with PFC enabled */
+        for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
+                switch (hw->mac.type) {
+                case ixgbe_mac_82598EB:
+                        xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
                         break;
                 default:
-                        tc = 0;
+                        xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
                 }
-                txoff <<= tc;
+                hwstats->pxoffrxc[i] += xoff[i];
         }
-#endif
-        return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
+
+        /* disarm tx queues that have received xoff frames */
+        for (i = 0; i < adapter->num_tx_queues; i++) {
+                struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
+                u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
+
+                if (xoff[tc])
+                        clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
+        }
+}
+
+static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
+{
+        return ring->tx_stats.completed;
 }
 
-static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
-                                       struct ixgbe_ring *tx_ring,
-                                       unsigned int eop)
+static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 {
+        struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
         struct ixgbe_hw *hw = &adapter->hw;
 
-        /* Detect a transmit hang in hardware, this serializes the
-         * check with the clearing of time_stamp and movement of eop */
-        adapter->detect_tx_hung = false;
-        if (tx_ring->tx_buffer_info[eop].time_stamp &&
-            time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
-            ixgbe_tx_xon_state(adapter, tx_ring)) {
-                /* detected Tx unit hang */
-                union ixgbe_adv_tx_desc *tx_desc;
-                tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
-                e_err(drv, "Detected Tx Unit Hang\n"
-                      "  Tx Queue             <%d>\n"
-                      "  TDH, TDT             <%x>, <%x>\n"
-                      "  next_to_use          <%x>\n"
-                      "  next_to_clean        <%x>\n"
-                      "tx_buffer_info[next_to_clean]\n"
-                      "  time_stamp           <%lx>\n"
-                      "  jiffies              <%lx>\n",
-                      tx_ring->queue_index,
-                      IXGBE_READ_REG(hw, tx_ring->head),
-                      IXGBE_READ_REG(hw, tx_ring->tail),
-                      tx_ring->next_to_use, eop,
-                      tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
-                return true;
+        u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
+        u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
+
+        if (head != tail)
+                return (head < tail) ?
+                        tail - head : (tail + ring->count - head);
+
+        return 0;
+}
+
+static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
+{
+        u32 tx_done = ixgbe_get_tx_completed(tx_ring);
+        u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
+        u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
+        bool ret = false;
+
+        clear_check_for_tx_hang(tx_ring);
+
+        /*
+         * Check for a hung queue, but be thorough. This verifies
+         * that a transmit has been completed since the previous
+         * check AND there is at least one packet pending. The
+         * ARMED bit is set to indicate a potential hang. The
+         * bit is cleared if a pause frame is received to remove
+         * false hang detection due to PFC or 802.3x frames. By
+         * requiring this to fail twice we avoid races with
+         * pfc clearing the ARMED bit and conditions where we
+         * run the check_tx_hang logic with a transmit completion
+         * pending but without time to complete it yet.
+         */
+        if ((tx_done_old == tx_done) && tx_pending) {
+                /* make sure it is true for two checks in a row */
+                ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
+                                       &tx_ring->state);
+        } else {
+                /* update completed stats and continue */
+                tx_ring->tx_stats.tx_done_old = tx_done;
+                /* reset the countdown */
+                clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
         }
 
-        return false;
+        return ret;
 }
 
 #define IXGBE_MAX_TXD_PWR       14
@@ -734,11 +821,10 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
                                struct ixgbe_ring *tx_ring)
 {
         struct ixgbe_adapter *adapter = q_vector->adapter;
-        struct net_device *netdev = adapter->netdev;
         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
         struct ixgbe_tx_buffer *tx_buffer_info;
-        unsigned int i, eop, count = 0;
         unsigned int total_bytes = 0, total_packets = 0;
+        u16 i, eop, count = 0;
 
         i = tx_ring->next_to_clean;
         eop = tx_ring->tx_buffer_info[i].next_to_watch;
@@ -749,148 +835,182 @@ static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
                 bool cleaned = false;
                 rmb(); /* read buffer_info after eop_desc */
                 for ( ; !cleaned; count++) {
-                        struct sk_buff *skb;
                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
-                        cleaned = (i == eop);
-                        skb = tx_buffer_info->skb;
-
-                        if (cleaned && skb) {
-                                unsigned int segs, bytecount;
-                                unsigned int hlen = skb_headlen(skb);
-
-                                /* gso_segs is currently only valid for tcp */
-                                segs = skb_shinfo(skb)->gso_segs ?: 1;
-#ifdef IXGBE_FCOE
-                                /* adjust for FCoE Sequence Offload */
-                                if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
-                                    && skb_is_gso(skb)
-                                    && vlan_get_protocol(skb) ==
-                                    htons(ETH_P_FCOE)) {
-                                        hlen = skb_transport_offset(skb) +
-                                                sizeof(struct fc_frame_header) +
-                                                sizeof(struct fcoe_crc_eof);
-                                        segs = DIV_ROUND_UP(skb->len - hlen,
-                                                skb_shinfo(skb)->gso_size);
-                                }
-#endif /* IXGBE_FCOE */
-                                /* multiply data chunks by size of headers */
-                                bytecount = ((segs - 1) * hlen) + skb->len;
-                                total_packets += segs;
-                                total_bytes += bytecount;
-                        }
-
-                        ixgbe_unmap_and_free_tx_resource(adapter,
-                                                         tx_buffer_info);
 
                         tx_desc->wb.status = 0;
+                        cleaned = (i == eop);
 
                         i++;
                         if (i == tx_ring->count)
                                 i = 0;
+
+                        if (cleaned && tx_buffer_info->skb) {
+                                total_bytes += tx_buffer_info->bytecount;
+                                total_packets += tx_buffer_info->gso_segs;
+                        }
+
+                        ixgbe_unmap_and_free_tx_resource(tx_ring,
+                                                         tx_buffer_info);
                 }
 
+                tx_ring->tx_stats.completed++;
                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
         }
 
         tx_ring->next_to_clean = i;
+        tx_ring->total_bytes += total_bytes;
+        tx_ring->total_packets += total_packets;
+        u64_stats_update_begin(&tx_ring->syncp);
+        tx_ring->stats.packets += total_packets;
+        tx_ring->stats.bytes += total_bytes;
+        u64_stats_update_end(&tx_ring->syncp);
+
+        if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
+                /* schedule immediate reset if we believe we hung */
+                struct ixgbe_hw *hw = &adapter->hw;
+                tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
+                e_err(drv, "Detected Tx Unit Hang\n"
+                        "  Tx Queue             <%d>\n"
+                        "  TDH, TDT             <%x>, <%x>\n"
+                        "  next_to_use          <%x>\n"
+                        "  next_to_clean        <%x>\n"
+                        "tx_buffer_info[next_to_clean]\n"
+                        "  time_stamp           <%lx>\n"
+                        "  jiffies              <%lx>\n",
+                        tx_ring->queue_index,
+                        IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
+                        IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
+                        tx_ring->next_to_use, eop,
+                        tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
+
+                netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
+
+                e_info(probe,
+                       "tx hang %d detected on queue %d, resetting adapter\n",
+                        adapter->tx_timeout_count + 1, tx_ring->queue_index);
+
+                /* schedule immediate reset if we believe we hung */
+                ixgbe_tx_timeout(adapter->netdev);
+
+                /* the adapter is about to reset, no point in enabling stuff */
+                return true;
+        }
 
 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
-        if (unlikely(count && netif_carrier_ok(netdev) &&
+        if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
                 /* Make sure that anybody stopping the queue after this
                  * sees the new next_to_clean.
                  */
                 smp_mb();
-                if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
+                if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
-                        netif_wake_subqueue(netdev, tx_ring->queue_index);
-                        ++tx_ring->restart_queue;
-                }
-        }
-
-        if (adapter->detect_tx_hung) {
-                if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
-                        /* schedule immediate reset if we believe we hung */
-                        e_info(probe, "tx hang %d detected, resetting "
-                               "adapter\n", adapter->tx_timeout_count + 1);
-                        ixgbe_tx_timeout(adapter->netdev);
+                        netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
+                        ++tx_ring->tx_stats.restart_queue;
                 }
         }
 
-        /* re-arm the interrupt */
-        if (count >= tx_ring->work_limit)
-                ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
-
-        tx_ring->total_bytes += total_bytes;
-        tx_ring->total_packets += total_packets;
-        u64_stats_update_begin(&tx_ring->syncp);
-        tx_ring->stats.packets += total_packets;
-        tx_ring->stats.bytes += total_bytes;
-        u64_stats_update_end(&tx_ring->syncp);
         return count < tx_ring->work_limit;
 }
 
 #ifdef CONFIG_IXGBE_DCA
 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
-                                struct ixgbe_ring *rx_ring)
+                                struct ixgbe_ring *rx_ring,
+                                int cpu)
 {
+        struct ixgbe_hw *hw = &adapter->hw;
         u32 rxctrl;
-        int cpu = get_cpu();
-        int q = rx_ring->reg_idx;
-
-        if (rx_ring->cpu != cpu) {
-                rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
-                if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
-                        rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
-                        rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
-                } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
-                        rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
-                        rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
-                                   IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
-                }
-                rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
-                rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
-                rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
-                rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
-                            IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
-                rx_ring->cpu = cpu;
+        u8 reg_idx = rx_ring->reg_idx;
+
+        rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
+                rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
+                rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
+                rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
+                           IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
+                break;
+        default:
+                break;
         }
-        put_cpu();
+        rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
+        rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
+        rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
+        rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
+                    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
+        IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 }
 
 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
-                                struct ixgbe_ring *tx_ring)
+                                struct ixgbe_ring *tx_ring,
+                                int cpu)
 {
+        struct ixgbe_hw *hw = &adapter->hw;
         u32 txctrl;
+        u8 reg_idx = tx_ring->reg_idx;
+
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
+                txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
+                txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
+                txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
+                txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
+                txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
+                txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
+                txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
+                           IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
+                txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
+                txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
+                IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
+                break;
+        default:
+                break;
+        }
+}
+
+static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
+{
+        struct ixgbe_adapter *adapter = q_vector->adapter;
         int cpu = get_cpu();
-        int q = tx_ring->reg_idx;
-        struct ixgbe_hw *hw = &adapter->hw;
+        long r_idx;
+        int i;
 
-        if (tx_ring->cpu != cpu) {
-                if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
-                        txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
-                        txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
-                        txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
-                        txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
-                        IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
-                } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
-                        txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
-                        txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
-                        txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
-                                  IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
-                        txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
-                        IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
-                }
-                tx_ring->cpu = cpu;
+        if (q_vector->cpu == cpu)
+                goto out_no_update;
+
+        r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
+        for (i = 0; i < q_vector->txr_count; i++) {
+                ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
+                r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
+                                      r_idx + 1);
+        }
+
+        r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+        for (i = 0; i < q_vector->rxr_count; i++) {
+                ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
+                r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
+                                      r_idx + 1);
         }
+
+        q_vector->cpu = cpu;
+out_no_update:
         put_cpu();
 }
 
 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 {
+        int num_q_vectors;
         int i;
 
         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
@@ -899,22 +1019,25 @@ static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
         /* always use CB2 mode, difference is masked in the CB driver */
         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 
-        for (i = 0; i < adapter->num_tx_queues; i++) {
-                adapter->tx_ring[i]->cpu = -1;
-                ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
-        }
-        for (i = 0; i < adapter->num_rx_queues; i++) {
-                adapter->rx_ring[i]->cpu = -1;
-                ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
+        if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
+                num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
+        else
+                num_q_vectors = 1;
+
+        for (i = 0; i < num_q_vectors; i++) {
+                adapter->q_vector[i]->cpu = -1;
+                ixgbe_update_dca(adapter->q_vector[i]);
         }
 }
 
 static int __ixgbe_notify_dca(struct device *dev, void *data)
 {
-        struct net_device *netdev = dev_get_drvdata(dev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
         unsigned long event = *(unsigned long *)data;
 
+        if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
+                return 0;
+
         switch (event) {
         case DCA_PROVIDER_ADD:
                 /* if we're already enabled, don't do it again */
@@ -1013,8 +1136,7 @@ static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
         skb->ip_summed = CHECKSUM_UNNECESSARY;
 }
 
-static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
-                                         struct ixgbe_ring *rx_ring, u32 val)
+static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
 {
         /*
          * Force memory writes to complete before letting h/w
@@ -1023,72 +1145,81 @@ static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
          * such as IA-64).
          */
         wmb();
-        IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
+        writel(val, rx_ring->tail);
 }
 
 /**
  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
- * @adapter: address of board private structure
+ * @rx_ring: ring to place buffers on
+ * @cleaned_count: number of buffers to replace
  **/
-void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
-                            struct ixgbe_ring *rx_ring,
-                            int cleaned_count)
+void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
 {
-        struct net_device *netdev = adapter->netdev;
-        struct pci_dev *pdev = adapter->pdev;
         union ixgbe_adv_rx_desc *rx_desc;
         struct ixgbe_rx_buffer *bi;
-        unsigned int i;
-        unsigned int bufsz = rx_ring->rx_buf_len;
+        struct sk_buff *skb;
+        u16 i = rx_ring->next_to_use;
 
-        i = rx_ring->next_to_use;
-        bi = &rx_ring->rx_buffer_info[i];
+        /* do nothing if no valid netdev defined */
+        if (!rx_ring->netdev)
+                return;
 
         while (cleaned_count--) {
                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
+                bi = &rx_ring->rx_buffer_info[i];
+                skb = bi->skb;
 
-                if (!bi->page_dma &&
-                    (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
-                        if (!bi->page) {
-                                bi->page = netdev_alloc_page(netdev);
-                                if (!bi->page) {
-                                        adapter->alloc_rx_page_failed++;
-                                        goto no_buffers;
-                                }
-                                bi->page_offset = 0;
-                        } else {
-                                /* use a half page if we're re-using */
-                                bi->page_offset ^= (PAGE_SIZE / 2);
-                        }
-
-                        bi->page_dma = dma_map_page(&pdev->dev, bi->page,
-                                                    bi->page_offset,
-                                                    (PAGE_SIZE / 2),
-                                                    DMA_FROM_DEVICE);
-                }
-
-                if (!bi->skb) {
-                        struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
-                                                                        bufsz);
-                        bi->skb = skb;
-
+                if (!skb) {
+                        skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
+                                                        rx_ring->rx_buf_len);
                         if (!skb) {
-                                adapter->alloc_rx_buff_failed++;
+                                rx_ring->rx_stats.alloc_rx_buff_failed++;
                                 goto no_buffers;
                         }
                         /* initialize queue mapping */
                         skb_record_rx_queue(skb, rx_ring->queue_index);
+                        bi->skb = skb;
                 }
 
                 if (!bi->dma) {
-                        bi->dma = dma_map_single(&pdev->dev,
-                                                 bi->skb->data,
+                        bi->dma = dma_map_single(rx_ring->dev,
+                                                 skb->data,
                                                  rx_ring->rx_buf_len,
                                                  DMA_FROM_DEVICE);
+                        if (dma_mapping_error(rx_ring->dev, bi->dma)) {
+                                rx_ring->rx_stats.alloc_rx_buff_failed++;
+                                bi->dma = 0;
+                                goto no_buffers;
+                        }
                 }
-                /* Refresh the desc even if buffer_addrs didn't change because
-                 * each write-back erases this info. */
-                if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
+
+                if (ring_is_ps_enabled(rx_ring)) {
+                        if (!bi->page) {
+                                bi->page = netdev_alloc_page(rx_ring->netdev);
+                                if (!bi->page) {
+                                        rx_ring->rx_stats.alloc_rx_page_failed++;
+                                        goto no_buffers;
+                                }
+                        }
+
+                        if (!bi->page_dma) {
+                                /* use a half page if we're re-using */
+                                bi->page_offset ^= PAGE_SIZE / 2;
+                                bi->page_dma = dma_map_page(rx_ring->dev,
+                                                            bi->page,
+                                                            bi->page_offset,
+                                                            PAGE_SIZE / 2,
+                                                            DMA_FROM_DEVICE);
+                                if (dma_mapping_error(rx_ring->dev,
+                                                      bi->page_dma)) {
+                                        rx_ring->rx_stats.alloc_rx_page_failed++;
+                                        bi->page_dma = 0;
+                                        goto no_buffers;
+                                }
+                        }
+
+                        /* Refresh the desc even if buffer_addrs didn't change
+                         * because each write-back erases this info. */
                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
                 } else {
@@ -1099,56 +1230,48 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
                 i++;
                 if (i == rx_ring->count)
                         i = 0;
-                bi = &rx_ring->rx_buffer_info[i];
         }
 
 no_buffers:
         if (rx_ring->next_to_use != i) {
                 rx_ring->next_to_use = i;
-                if (i-- == 0)
-                        i = (rx_ring->count - 1);
-
-                ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
+                ixgbe_release_rx_desc(rx_ring, i);
         }
 }
 
-static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
+static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
 {
-        return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
-}
-
-static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
-{
-        return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
-}
-
-static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
-{
-        return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
-                IXGBE_RXDADV_RSCCNT_MASK) >>
-                IXGBE_RXDADV_RSCCNT_SHIFT;
+        /* HW will not DMA in data larger than the given buffer, even if it
+         * parses the (NFS, of course) header to be larger.  In that case, it
+         * fills the header buffer and spills the rest into the page.
+         */
+        u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
+        u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
+                    IXGBE_RXDADV_HDRBUFLEN_SHIFT;
+        if (hlen > IXGBE_RX_HDR_SIZE)
+                hlen = IXGBE_RX_HDR_SIZE;
+        return hlen;
 }
 
 /**
  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
  * @skb: pointer to the last skb in the rsc queue
- * @count: pointer to number of packets coalesced in this context
  *
  * This function changes a queue full of hw rsc buffers into a completed
  * packet.  It uses the ->prev pointers to find the first packet and then
  * turns it into the frag list owner.
  **/
-static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
-                                                        u64 *count)
+static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 {
         unsigned int frag_list_size = 0;
+        unsigned int skb_cnt = 1;
 
         while (skb->prev) {
                 struct sk_buff *prev = skb->prev;
                 frag_list_size += skb->len;
                 skb->prev = NULL;
                 skb = prev;
-                *count += 1;
+                skb_cnt++;
         }
 
         skb_shinfo(skb)->frag_list = skb->next;
@@ -1156,68 +1279,59 @@ static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
         skb->len += frag_list_size;
         skb->data_len += frag_list_size;
         skb->truesize += frag_list_size;
+        IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
+
         return skb;
 }
 
-struct ixgbe_rsc_cb {
-        dma_addr_t dma;
-        bool delay_unmap;
-};
-
-#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
+static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
+{
+        return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
+                IXGBE_RXDADV_RSCCNT_MASK);
+}
 
-static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
+static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                                struct ixgbe_ring *rx_ring,
                                int *work_done, int work_to_do)
 {
         struct ixgbe_adapter *adapter = q_vector->adapter;
-        struct pci_dev *pdev = adapter->pdev;
         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
         struct sk_buff *skb;
-        unsigned int i, rsc_count = 0;
-        u32 len, staterr;
-        u16 hdr_info;
-        bool cleaned = false;
-        int cleaned_count = 0;
         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
+        const int current_node = numa_node_id();
 #ifdef IXGBE_FCOE
         int ddp_bytes = 0;
 #endif /* IXGBE_FCOE */
+        u32 staterr;
+        u16 i;
+        u16 cleaned_count = 0;
+        bool pkt_is_rsc = false;
 
         i = rx_ring->next_to_clean;
         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
-        rx_buffer_info = &rx_ring->rx_buffer_info[i];
 
         while (staterr & IXGBE_RXD_STAT_DD) {
                 u32 upper_len = 0;
-                if (*work_done >= work_to_do)
-                        break;
-                (*work_done)++;
 
                 rmb(); /* read descriptor and rx_buffer_info after status DD */
-                if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
-                        hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
-                        len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
-                               IXGBE_RXDADV_HDRBUFLEN_SHIFT;
-                        upper_len = le16_to_cpu(rx_desc->wb.upper.length);
-                        if ((len > IXGBE_RX_HDR_SIZE) ||
-                            (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
-                                len = IXGBE_RX_HDR_SIZE;
-                } else {
-                        len = le16_to_cpu(rx_desc->wb.upper.length);
-                }
 
-                cleaned = true;
+                rx_buffer_info = &rx_ring->rx_buffer_info[i];
+
                 skb = rx_buffer_info->skb;
-                prefetch(skb->data);
                 rx_buffer_info->skb = NULL;
+                prefetch(skb->data);
+
+                if (ring_is_rsc_enabled(rx_ring))
+                        pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
 
+                /* if this is a skb from previous receive DMA will be 0 */
                 if (rx_buffer_info->dma) {
-                        if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
-                            (!(staterr & IXGBE_RXD_STAT_EOP)) &&
-                                 (!(skb->prev))) {
+                        u16 hlen;
+                        if (pkt_is_rsc &&
+                            !(staterr & IXGBE_RXD_STAT_EOP) &&
+                            !skb->prev) {
                                 /*
                                  * When HWRSC is enabled, delay unmapping
                                  * of the first packet. It carries the
@@ -1228,29 +1342,42 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
                         } else {
-                                dma_unmap_single(&pdev->dev,
+                                dma_unmap_single(rx_ring->dev,
                                                  rx_buffer_info->dma,
                                                  rx_ring->rx_buf_len,
                                                  DMA_FROM_DEVICE);
                         }
                         rx_buffer_info->dma = 0;
-                        skb_put(skb, len);
+
+                        if (ring_is_ps_enabled(rx_ring)) {
+                                hlen = ixgbe_get_hlen(rx_desc);
+                                upper_len = le16_to_cpu(rx_desc->wb.upper.length);
+                        } else {
+                                hlen = le16_to_cpu(rx_desc->wb.upper.length);
+                        }
+
+                        skb_put(skb, hlen);
+                } else {
+                        /* assume packet split since header is unmapped */
+                        upper_len = le16_to_cpu(rx_desc->wb.upper.length);
                 }
 
                 if (upper_len) {
-                        dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
-                                       PAGE_SIZE / 2, DMA_FROM_DEVICE);
+                        dma_unmap_page(rx_ring->dev,
+                                       rx_buffer_info->page_dma,
+                                       PAGE_SIZE / 2,
+                                       DMA_FROM_DEVICE);
                         rx_buffer_info->page_dma = 0;
                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
                                            rx_buffer_info->page,
                                            rx_buffer_info->page_offset,
                                            upper_len);
 
-                        if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
-                            (page_count(rx_buffer_info->page) != 1))
-                                rx_buffer_info->page = NULL;
-                        else
+                        if ((page_count(rx_buffer_info->page) == 1) &&
+                            (page_to_nid(rx_buffer_info->page) == current_node))
                                 get_page(rx_buffer_info->page);
+                        else
+                                rx_buffer_info->page = NULL;
 
                         skb->len += upper_len;
                         skb->data_len += upper_len;
@@ -1265,10 +1392,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                 prefetch(next_rxd);
                 cleaned_count++;
 
-                if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
-                        rsc_count = ixgbe_get_rsc_count(rx_desc);
-
-                if (rsc_count) {
+                if (pkt_is_rsc) {
                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
                                      IXGBE_RXDADV_NEXTP_SHIFT;
                         next_buffer = &rx_ring->rx_buffer_info[nextp];
@@ -1276,32 +1400,8 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                         next_buffer = &rx_ring->rx_buffer_info[i];
                 }
 
-                if (staterr & IXGBE_RXD_STAT_EOP) {
-                        if (skb->prev)
-                                skb = ixgbe_transform_rsc_queue(skb,
-                                                                &(rx_ring->rsc_count));
-                        if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
-                                if (IXGBE_RSC_CB(skb)->delay_unmap) {
-                                        dma_unmap_single(&pdev->dev,
-                                                         IXGBE_RSC_CB(skb)->dma,
-                                                         rx_ring->rx_buf_len,
-                                                         DMA_FROM_DEVICE);
-                                        IXGBE_RSC_CB(skb)->dma = 0;
-                                        IXGBE_RSC_CB(skb)->delay_unmap = false;
-                                }
-                                if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
-                                        rx_ring->rsc_count +=
-                                                skb_shinfo(skb)->nr_frags;
-                                else
-                                        rx_ring->rsc_count++;
-                                rx_ring->rsc_flush++;
-                        }
-                        u64_stats_update_begin(&rx_ring->syncp);
-                        rx_ring->stats.packets++;
-                        rx_ring->stats.bytes += skb->len;
-                        u64_stats_update_end(&rx_ring->syncp);
-                } else {
-                        if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
+                if (!(staterr & IXGBE_RXD_STAT_EOP)) {
+                        if (ring_is_ps_enabled(rx_ring)) {
                                 rx_buffer_info->skb = next_buffer->skb;
                                 rx_buffer_info->dma = next_buffer->dma;
                                 next_buffer->skb = skb;
@@ -1310,12 +1410,45 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                                 skb->next = next_buffer->skb;
                                 skb->next->prev = skb;
                         }
-                        rx_ring->non_eop_descs++;
+                        rx_ring->rx_stats.non_eop_descs++;
                         goto next_desc;
                 }
 
+                if (skb->prev) {
+                        skb = ixgbe_transform_rsc_queue(skb);
+                        /* if we got here without RSC the packet is invalid */
+                        if (!pkt_is_rsc) {
+                                __pskb_trim(skb, 0);
+                                rx_buffer_info->skb = skb;
+                                goto next_desc;
+                        }
+                }
+
+                if (ring_is_rsc_enabled(rx_ring)) {
+                        if (IXGBE_RSC_CB(skb)->delay_unmap) {
+                                dma_unmap_single(rx_ring->dev,
+                                                 IXGBE_RSC_CB(skb)->dma,
+                                                 rx_ring->rx_buf_len,
+                                                 DMA_FROM_DEVICE);
+                                IXGBE_RSC_CB(skb)->dma = 0;
+                                IXGBE_RSC_CB(skb)->delay_unmap = false;
+                        }
+                }
+                if (pkt_is_rsc) {
+                        if (ring_is_ps_enabled(rx_ring))
+                                rx_ring->rx_stats.rsc_count +=
+                                        skb_shinfo(skb)->nr_frags;
+                        else
+                                rx_ring->rx_stats.rsc_count +=
+                                        IXGBE_RSC_CB(skb)->skb_cnt;
+                        rx_ring->rx_stats.rsc_flush++;
+                }
+
+                /* ERR_MASK will only have valid bits if EOP set */
                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
-                        dev_kfree_skb_irq(skb);
+                        /* trim packet back to size 0 and recycle it */
+                        __pskb_trim(skb, 0);
+                        rx_buffer_info->skb = skb;
                         goto next_desc;
                 }
 
@@ -1325,7 +1458,7 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
                 total_rx_bytes += skb->len;
                 total_rx_packets++;
 
-                skb->protocol = eth_type_trans(skb, adapter->netdev);
+                skb->protocol = eth_type_trans(skb, rx_ring->netdev);
 #ifdef IXGBE_FCOE
                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
@@ -1339,16 +1472,18 @@ static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 next_desc:
                 rx_desc->wb.upper.status_error = 0;
 
+                (*work_done)++;
+                if (*work_done >= work_to_do)
+                        break;
+
                 /* return some buffers to hardware, one at a time is too slow */
                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
-                        ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
+                        ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
                         cleaned_count = 0;
                 }
 
                 /* use prefetched values */
                 rx_desc = next_rxd;
-                rx_buffer_info = &rx_ring->rx_buffer_info[i];
-
                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
         }
 
@@ -1356,14 +1491,14 @@ next_desc:
         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 
         if (cleaned_count)
-                ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
+                ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
 
 #ifdef IXGBE_FCOE
         /* include DDPed FCoE data */
         if (ddp_bytes > 0) {
                 unsigned int mss;
 
-                mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
+                mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
                         sizeof(struct fc_frame_header) -
                         sizeof(struct fcoe_crc_eof);
                 if (mss > 512)
@@ -1375,8 +1510,10 @@ next_desc:
 
         rx_ring->total_packets += total_rx_packets;
         rx_ring->total_bytes += total_rx_bytes;
-
-        return cleaned;
+        u64_stats_update_begin(&rx_ring->syncp);
+        rx_ring->stats.packets += total_rx_packets;
+        rx_ring->stats.bytes += total_rx_bytes;
+        u64_stats_update_end(&rx_ring->syncp);
 }
 
 static int ixgbe_clean_rxonly(struct napi_struct *, int);
@@ -1390,7 +1527,7 @@ static int ixgbe_clean_rxonly(struct napi_struct *, int);
 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 {
         struct ixgbe_q_vector *q_vector;
-        int i, j, q_vectors, v_idx, r_idx;
+        int i, q_vectors, v_idx, r_idx;
         u32 mask;
 
         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
@@ -1406,8 +1543,8 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
                                        adapter->num_rx_queues);
 
                 for (i = 0; i < q_vector->rxr_count; i++) {
-                        j = adapter->rx_ring[r_idx]->reg_idx;
-                        ixgbe_set_ivar(adapter, 0, j, v_idx);
+                        u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
+                        ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
                         r_idx = find_next_bit(q_vector->rxr_idx,
                                               adapter->num_rx_queues,
                                               r_idx + 1);
@@ -1416,8 +1553,8 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
                                        adapter->num_tx_queues);
 
                 for (i = 0; i < q_vector->txr_count; i++) {
-                        j = adapter->tx_ring[r_idx]->reg_idx;
-                        ixgbe_set_ivar(adapter, 1, j, v_idx);
+                        u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
+                        ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
                         r_idx = find_next_bit(q_vector->txr_idx,
                                               adapter->num_tx_queues,
                                               r_idx + 1);
@@ -1448,11 +1585,19 @@ static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
                 }
         }
 
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB)
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
                                v_idx);
-        else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
+                break;
+
+        default:
+                break;
+        }
         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 
         /* set up to autoclear timer, and the vectors */
@@ -1548,12 +1693,15 @@ void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
         int v_idx = q_vector->v_idx;
         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
 
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
                 /* must write high and low 16 bits to reset counter */
                 itr_reg |= (itr_reg << 16);
-        } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 /*
-                 * 82599 can support a value of zero, so allow it for
+                 * 82599 and X540 can support a value of zero, so allow it for
                  * max interrupt rate, but there is an errata where it can
                  * not be zero with RSC
                  */
@@ -1566,6 +1714,9 @@ void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
                  * immediate assertion of the interrupt
                  */
                 itr_reg |= IXGBE_EITR_CNT_WDIS;
+                break;
+        default:
+                break;
         }
         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
 }
@@ -1573,14 +1724,13 @@ void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 {
         struct ixgbe_adapter *adapter = q_vector->adapter;
+        int i, r_idx;
         u32 new_itr;
         u8 current_itr, ret_itr;
-        int i, r_idx;
-        struct ixgbe_ring *rx_ring, *tx_ring;
 
         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
         for (i = 0; i < q_vector->txr_count; i++) {
-                tx_ring = adapter->tx_ring[r_idx];
+                struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
                                            q_vector->tx_itr,
                                            tx_ring->total_packets,
@@ -1595,7 +1745,7 @@ static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 
         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
         for (i = 0; i < q_vector->rxr_count; i++) {
-                rx_ring = adapter->rx_ring[r_idx];
+                struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
                                            q_vector->rx_itr,
                                            rx_ring->total_packets,
@@ -1626,7 +1776,7 @@ static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
 
         if (new_itr != q_vector->eitr) {
                 /* do an exponential smoothing */
-                new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
+                new_itr = ((q_vector->eitr * 9) + new_itr)/10;
 
                 /* save the algorithm value here, not the smoothed one */
                 q_vector->eitr = new_itr;
@@ -1694,17 +1844,18 @@ static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
 {
         struct ixgbe_hw *hw = &adapter->hw;
 
+        if (eicr & IXGBE_EICR_GPI_SDP2) {
+                /* Clear the interrupt */
+                IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
+                if (!test_bit(__IXGBE_DOWN, &adapter->state))
+                        schedule_work(&adapter->sfp_config_module_task);
+        }
+
         if (eicr & IXGBE_EICR_GPI_SDP1) {
                 /* Clear the interrupt */
                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
-                schedule_work(&adapter->multispeed_fiber_task);
-        } else if (eicr & IXGBE_EICR_GPI_SDP2) {
-                /* Clear the interrupt */
-                IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
-                schedule_work(&adapter->sfp_config_module_task);
-        } else {
-                /* Interrupt isn't for us... */
-                return;
+                if (!test_bit(__IXGBE_DOWN, &adapter->state))
+                        schedule_work(&adapter->multispeed_fiber_task);
         }
 }
 
@@ -1744,16 +1895,16 @@ static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
         if (eicr & IXGBE_EICR_MAILBOX)
                 ixgbe_msg_task(adapter);
 
-        if (hw->mac.type == ixgbe_mac_82598EB)
-                ixgbe_check_fan_failure(adapter, eicr);
-
-        if (hw->mac.type == ixgbe_mac_82599EB) {
+        switch (hw->mac.type) {
+        case ixgbe_mac_82599EB:
                 ixgbe_check_sfp_event(adapter, eicr);
-                adapter->interrupt_event = eicr;
                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
-                    ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
+                    ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
+                        adapter->interrupt_event = eicr;
                         schedule_work(&adapter->check_overtemp_task);
-
+                }
+                /* now fallthrough to handle Flow Director */
+        case ixgbe_mac_X540:
                 /* Handle Flow Director Full threshold interrupt */
                 if (eicr & IXGBE_EICR_FLOW_DIR) {
                         int i;
@@ -1763,12 +1914,18 @@ static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
                         for (i = 0; i < adapter->num_tx_queues; i++) {
                                 struct ixgbe_ring *tx_ring =
                                                             adapter->tx_ring[i];
-                                if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
-                                                       &tx_ring->reinit_state))
+                                if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
+                                                       &tx_ring->state))
                                         schedule_work(&adapter->fdir_reinit_task);
                         }
                 }
+                break;
+        default:
+                break;
         }
+
+        ixgbe_check_fan_failure(adapter, eicr);
+
         if (!test_bit(__IXGBE_DOWN, &adapter->state))
                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
 
@@ -1779,15 +1936,24 @@ static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
                                            u64 qmask)
 {
         u32 mask;
+        struct ixgbe_hw *hw = &adapter->hw;
 
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
-        } else {
+                IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 mask = (qmask & 0xFFFFFFFF);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
+                if (mask)
+                        IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
                 mask = (qmask >> 32);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
+                if (mask)
+                        IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
+                break;
+        default:
+                break;
         }
         /* skip the flush */
 }
@@ -1796,15 +1962,24 @@ static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
                                             u64 qmask)
 {
         u32 mask;
+        struct ixgbe_hw *hw = &adapter->hw;
 
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
-        } else {
+                IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 mask = (qmask & 0xFFFFFFFF);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
+                if (mask)
+                        IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
                 mask = (qmask >> 32);
-                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
+                if (mask)
+                        IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
+                break;
+        default:
+                break;
         }
         /* skip the flush */
 }
@@ -1847,8 +2022,13 @@ static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
         int r_idx;
         int i;
 
+#ifdef CONFIG_IXGBE_DCA
+        if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                ixgbe_update_dca(q_vector);
+#endif
+
         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
-        for (i = 0;  i < q_vector->rxr_count; i++) {
+        for (i = 0; i < q_vector->rxr_count; i++) {
                 rx_ring = adapter->rx_ring[r_idx];
                 rx_ring->total_bytes = 0;
                 rx_ring->total_packets = 0;
@@ -1859,7 +2039,6 @@ static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
         if (!q_vector->rxr_count)
                 return IRQ_HANDLED;
 
-        /* disable interrupts on this vector only */
         /* EIAM disabled interrupts (on this vector) for us */
         napi_schedule(&q_vector->napi);
 
@@ -1918,13 +2097,14 @@ static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
         int work_done = 0;
         long r_idx;
 
-        r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
-        rx_ring = adapter->rx_ring[r_idx];
 #ifdef CONFIG_IXGBE_DCA
         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
-                ixgbe_update_rx_dca(adapter, rx_ring);
+                ixgbe_update_dca(q_vector);
 #endif
 
+        r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
+        rx_ring = adapter->rx_ring[r_idx];
+
         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
 
         /* If all Rx work done, exit the polling mode */
@@ -1958,13 +2138,14 @@ static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
         long r_idx;
         bool tx_clean_complete = true;
 
+#ifdef CONFIG_IXGBE_DCA
+        if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                ixgbe_update_dca(q_vector);
+#endif
+
         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
         for (i = 0; i < q_vector->txr_count; i++) {
                 ring = adapter->tx_ring[r_idx];
-#ifdef CONFIG_IXGBE_DCA
-                if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
-                        ixgbe_update_tx_dca(adapter, ring);
-#endif
                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
                                       r_idx + 1);
@@ -1977,10 +2158,6 @@ static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
         for (i = 0; i < q_vector->rxr_count; i++) {
                 ring = adapter->rx_ring[r_idx];
-#ifdef CONFIG_IXGBE_DCA
-                if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
-                        ixgbe_update_rx_dca(adapter, ring);
-#endif
                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
                                       r_idx + 1);
@@ -2019,13 +2196,14 @@ static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
         int work_done = 0;
         long r_idx;
 
-        r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
-        tx_ring = adapter->tx_ring[r_idx];
 #ifdef CONFIG_IXGBE_DCA
         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
-                ixgbe_update_tx_dca(adapter, tx_ring);
+                ixgbe_update_dca(q_vector);
 #endif
 
+        r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
+        tx_ring = adapter->tx_ring[r_idx];
+
         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
                 work_done = budget;
 
@@ -2046,24 +2224,27 @@ static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
                                      int r_idx)
 {
         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
+        struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
 
         set_bit(r_idx, q_vector->rxr_idx);
         q_vector->rxr_count++;
+        rx_ring->q_vector = q_vector;
 }
 
 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
                                      int t_idx)
 {
         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
+        struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
 
         set_bit(t_idx, q_vector->txr_idx);
         q_vector->txr_count++;
+        tx_ring->q_vector = q_vector;
 }
 
 /**
  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
  * @adapter: board private structure to initialize
- * @vectors: allotted vector count for descriptor rings
  *
  * This function maps descriptor rings to the queue-specific vectors
  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
@@ -2071,9 +2252,9 @@ static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
  * group the rings as "efficiently" as possible.  You would add new
  * mapping configurations in here.
  **/
-static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
-                                      int vectors)
+static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
 {
+        int q_vectors;
         int v_start = 0;
         int rxr_idx = 0, txr_idx = 0;
         int rxr_remaining = adapter->num_rx_queues;
@@ -2086,11 +2267,13 @@ static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
                 goto out;
 
+        q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
+
         /*
          * The ideal configuration...
          * We have enough vectors to map one per queue.
          */
-        if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
+        if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
                         map_vector_to_rxq(adapter, v_start, rxr_idx);
 
@@ -2106,23 +2289,20 @@ static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
          * multiple queues per vector.
          */
         /* Re-adjusting *qpv takes care of the remainder. */
-        for (i = v_start; i < vectors; i++) {
-                rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
+        for (i = v_start; i < q_vectors; i++) {
+                rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
                 for (j = 0; j < rqpv; j++) {
                         map_vector_to_rxq(adapter, i, rxr_idx);
                         rxr_idx++;
                         rxr_remaining--;
                 }
-        }
-        for (i = v_start; i < vectors; i++) {
-                tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
+                tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
                 for (j = 0; j < tqpv; j++) {
                         map_vector_to_txq(adapter, i, txr_idx);
                         txr_idx++;
                         txr_remaining--;
                 }
         }
-
 out:
         return err;
 }
@@ -2144,30 +2324,36 @@ static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
         /* Decrement for Other and TCP Timer vectors */
         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 
-        /* Map the Tx/Rx rings to the vectors we were allotted. */
-        err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
+        err = ixgbe_map_rings_to_vectors(adapter);
         if (err)
-                goto out;
+                return err;
 
-#define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
-                         (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
-                         &ixgbe_msix_clean_many)
+#define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
+                                          ? &ixgbe_msix_clean_many : \
+                          (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
+                          (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
+                          NULL)
         for (vector = 0; vector < q_vectors; vector++) {
-                handler = SET_HANDLER(adapter->q_vector[vector]);
+                struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
+                handler = SET_HANDLER(q_vector);
 
                 if (handler == &ixgbe_msix_clean_rx) {
-                        sprintf(adapter->name[vector], "%s-%s-%d",
-                                netdev->name, "rx", ri++);
+                        snprintf(q_vector->name, sizeof(q_vector->name) - 1,
+                                 "%s-%s-%d", netdev->name, "rx", ri++);
                 } else if (handler == &ixgbe_msix_clean_tx) {
-                        sprintf(adapter->name[vector], "%s-%s-%d",
-                                netdev->name, "tx", ti++);
-                } else
-                        sprintf(adapter->name[vector], "%s-%s-%d",
-                                netdev->name, "TxRx", vector);
-
+                        snprintf(q_vector->name, sizeof(q_vector->name) - 1,
+                                 "%s-%s-%d", netdev->name, "tx", ti++);
+                } else if (handler == &ixgbe_msix_clean_many) {
+                        snprintf(q_vector->name, sizeof(q_vector->name) - 1,
+                                 "%s-%s-%d", netdev->name, "TxRx", ri++);
+                        ti++;
+                } else {
+                        /* skip this unused q_vector */
+                        continue;
+                }
                 err = request_irq(adapter->msix_entries[vector].vector,
-                                  handler, 0, adapter->name[vector],
-                                  adapter->q_vector[vector]);
+                                  handler, 0, q_vector->name,
+                                  q_vector);
                 if (err) {
                         e_err(probe, "request_irq failed for MSIX interrupt "
                               "Error: %d\n", err);
@@ -2175,9 +2361,9 @@ static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
                 }
         }
 
-        sprintf(adapter->name[vector], "%s:lsc", netdev->name);
+        sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
         err = request_irq(adapter->msix_entries[vector].vector,
-                          ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
+                          ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
         if (err) {
                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
                 goto free_queue_irqs;
@@ -2193,17 +2379,16 @@ free_queue_irqs:
         pci_disable_msix(adapter->pdev);
         kfree(adapter->msix_entries);
         adapter->msix_entries = NULL;
-out:
         return err;
 }
 
 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
 {
         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
-        u8 current_itr;
-        u32 new_itr = q_vector->eitr;
         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
+        u32 new_itr = q_vector->eitr;
+        u8 current_itr;
 
         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
                                             q_vector->tx_itr,
@@ -2233,9 +2418,9 @@ static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
 
         if (new_itr != q_vector->eitr) {
                 /* do an exponential smoothing */
-                new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
+                new_itr = ((q_vector->eitr * 9) + new_itr)/10;
 
-                /* save the algorithm value here, not the smoothed one */
+                /* save the algorithm value here */
                 q_vector->eitr = new_itr;
 
                 ixgbe_write_eitr(q_vector);
@@ -2256,12 +2441,17 @@ static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
                 mask |= IXGBE_EIMS_GPI_SDP0;
         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
                 mask |= IXGBE_EIMS_GPI_SDP1;
-        if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 mask |= IXGBE_EIMS_ECC;
                 mask |= IXGBE_EIMS_GPI_SDP1;
                 mask |= IXGBE_EIMS_GPI_SDP2;
                 if (adapter->num_vfs)
                         mask |= IXGBE_EIMS_MAILBOX;
+                break;
+        default:
+                break;
         }
         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
@@ -2317,13 +2507,20 @@ static irqreturn_t ixgbe_intr(int irq, void *data)
         if (eicr & IXGBE_EICR_LSC)
                 ixgbe_check_lsc(adapter);
 
-        if (hw->mac.type == ixgbe_mac_82599EB)
+        switch (hw->mac.type) {
+        case ixgbe_mac_82599EB:
                 ixgbe_check_sfp_event(adapter, eicr);
+                if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
+                    ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
+                        adapter->interrupt_event = eicr;
+                        schedule_work(&adapter->check_overtemp_task);
+                }
+                break;
+        default:
+                break;
+        }
 
         ixgbe_check_fan_failure(adapter, eicr);
-        if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
-            ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
-                schedule_work(&adapter->check_overtemp_task);
 
         if (napi_schedule_prep(&(q_vector->napi))) {
                 adapter->tx_ring[0]->total_packets = 0;
@@ -2416,14 +2613,20 @@ static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
  **/
 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
 {
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
-        } else {
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
                 if (adapter->num_vfs > 32)
                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
+                break;
+        default:
+                break;
         }
         IXGBE_WRITE_FLUSH(&adapter->hw);
         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
@@ -2469,7 +2672,7 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
         u64 tdba = ring->dma;
         int wait_loop = 10;
         u32 txdctl;
-        u16 reg_idx = ring->reg_idx;
+        u8 reg_idx = ring->reg_idx;
 
         /* disable queue to avoid issues while updating state */
         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
@@ -2484,8 +2687,7 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
                         ring->count * sizeof(union ixgbe_adv_tx_desc));
         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
-        ring->head = IXGBE_TDH(reg_idx);
-        ring->tail = IXGBE_TDT(reg_idx);
+        ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
 
         /* configure fetching thresholds */
         if (adapter->rx_itr_setting == 0) {
@@ -2501,7 +2703,16 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
         }
 
         /* reinitialize flowdirector state */
-        set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
+        if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
+            adapter->atr_sample_rate) {
+                ring->atr_sample_rate = adapter->atr_sample_rate;
+                ring->atr_count = 0;
+                set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
+        } else {
+                ring->atr_sample_rate = 0;
+        }
+
+        clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
 
         /* enable queue */
         txdctl |= IXGBE_TXDCTL_ENABLE;
@@ -2592,16 +2803,22 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
                                    struct ixgbe_ring *rx_ring)
 {
         u32 srrctl;
-        int index;
-        struct ixgbe_ring_feature *feature = adapter->ring_feature;
+        u8 reg_idx = rx_ring->reg_idx;
 
-        index = rx_ring->reg_idx;
-        if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
-                unsigned long mask;
-                mask = (unsigned long) feature[RING_F_RSS].mask;
-                index = index & mask;
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB: {
+                struct ixgbe_ring_feature *feature = adapter->ring_feature;
+                const int mask = feature[RING_F_RSS].mask;
+                reg_idx = reg_idx & mask;
         }
-        srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+        default:
+                break;
+        }
+
+        srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
 
         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
@@ -2611,7 +2828,7 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
                   IXGBE_SRRCTL_BSIZEHDR_MASK;
 
-        if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
+        if (ring_is_ps_enabled(rx_ring)) {
 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
 #else
@@ -2624,7 +2841,7 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
         }
 
-        IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
+        IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
 }
 
 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
@@ -2694,19 +2911,36 @@ static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
 }
 
 /**
+ * ixgbe_clear_rscctl - disable RSC for the indicated ring
+ * @adapter: address of board private structure
+ * @ring: structure containing ring specific data
+ **/
+void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
+                        struct ixgbe_ring *ring)
+{
+        struct ixgbe_hw *hw = &adapter->hw;
+        u32 rscctrl;
+        u8 reg_idx = ring->reg_idx;
+
+        rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
+        rscctrl &= ~IXGBE_RSCCTL_RSCEN;
+        IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
+}
+
+/**
  * ixgbe_configure_rscctl - enable RSC for the indicated ring
  * @adapter:    address of board private structure
  * @index:      index of ring to set
  **/
-static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
+void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
                                    struct ixgbe_ring *ring)
 {
         struct ixgbe_hw *hw = &adapter->hw;
         u32 rscctrl;
         int rx_buf_len;
-        u16 reg_idx = ring->reg_idx;
+        u8 reg_idx = ring->reg_idx;
 
-        if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
+        if (!ring_is_rsc_enabled(ring))
                 return;
 
         rx_buf_len = ring->rx_buf_len;
@@ -2717,7 +2951,7 @@ static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
          * total size of max desc * buf_len is not greater
          * than 65535
          */
-        if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
+        if (ring_is_ps_enabled(ring)) {
 #if (MAX_SKB_FRAGS > 16)
                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
 #elif (MAX_SKB_FRAGS > 8)
@@ -2770,9 +3004,9 @@ static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
                                        struct ixgbe_ring *ring)
 {
         struct ixgbe_hw *hw = &adapter->hw;
-        int reg_idx = ring->reg_idx;
         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
         u32 rxdctl;
+        u8 reg_idx = ring->reg_idx;
 
         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
         if (hw->mac.type == ixgbe_mac_82598EB &&
@@ -2790,19 +3024,47 @@ static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
         }
 }
 
+void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
+                            struct ixgbe_ring *ring)
+{
+        struct ixgbe_hw *hw = &adapter->hw;
+        int wait_loop = IXGBE_MAX_RX_DESC_POLL;
+        u32 rxdctl;
+        u8 reg_idx = ring->reg_idx;
+
+        rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
+        rxdctl &= ~IXGBE_RXDCTL_ENABLE;
+
+        /* write value back with RXDCTL.ENABLE bit cleared */
+        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
+
+        if (hw->mac.type == ixgbe_mac_82598EB &&
+            !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
+                return;
+
+        /* the hardware may take up to 100us to really disable the rx queue */
+        do {
+                udelay(10);
+                rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
+        } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
+
+        if (!wait_loop) {
+                e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
+                      "the polling period\n", reg_idx);
+        }
+}
+
 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
                              struct ixgbe_ring *ring)
 {
         struct ixgbe_hw *hw = &adapter->hw;
         u64 rdba = ring->dma;
         u32 rxdctl;
-        u16 reg_idx = ring->reg_idx;
+        u8 reg_idx = ring->reg_idx;
 
         /* disable queue to avoid issues while updating state */
         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
-        IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
-                        rxdctl & ~IXGBE_RXDCTL_ENABLE);
-        IXGBE_WRITE_FLUSH(hw);
+        ixgbe_disable_rx_queue(adapter, ring);
 
         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
@@ -2810,8 +3072,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
                         ring->count * sizeof(union ixgbe_adv_rx_desc));
         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
-        ring->head = IXGBE_RDH(reg_idx);
-        ring->tail = IXGBE_RDT(reg_idx);
+        ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
 
         ixgbe_configure_srrctl(adapter, ring);
         ixgbe_configure_rscctl(adapter, ring);
@@ -2833,7 +3094,7 @@ void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
 
         ixgbe_rx_desc_queue_enable(adapter, ring);
-        ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
+        ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
 }
 
 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
@@ -2899,6 +3160,9 @@ static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
 
         /* enable Tx loopback for VF/PF communication */
         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
+        /* Enable MAC Anti-Spoofing */
+        hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
+                                          adapter->num_vfs);
 }
 
 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
@@ -2956,24 +3220,32 @@ static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
                 rx_ring->rx_buf_len = rx_buf_len;
 
                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
-                        rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
+                        set_ring_ps_enabled(rx_ring);
+                else
+                        clear_ring_ps_enabled(rx_ring);
+
+                if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
+                        set_ring_rsc_enabled(rx_ring);
                 else
-                        rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
+                        clear_ring_rsc_enabled(rx_ring);
 
 #ifdef IXGBE_FCOE
                 if (netdev->features & NETIF_F_FCOE_MTU) {
                         struct ixgbe_ring_feature *f;
                         f = &adapter->ring_feature[RING_F_FCOE];
                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
-                                rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
+                                clear_ring_ps_enabled(rx_ring);
                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
                                         rx_ring->rx_buf_len =
                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
+                        } else if (!ring_is_rsc_enabled(rx_ring) &&
+                                   !ring_is_ps_enabled(rx_ring)) {
+                                rx_ring->rx_buf_len =
+                                                IXGBE_FCOE_JUMBO_FRAME_SIZE;
                         }
                 }
 #endif /* IXGBE_FCOE */
         }
-
 }
 
 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
@@ -2996,6 +3268,7 @@ static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
                 break;
         case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 /* Disable RSC for ACK packets */
                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
@@ -3123,6 +3396,7 @@ static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
                 break;
         case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 for (i = 0; i < adapter->num_rx_queues; i++) {
                         j = adapter->rx_ring[i]->reg_idx;
                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
@@ -3152,6 +3426,7 @@ static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
                 break;
         case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 for (i = 0; i < adapter->num_rx_queues; i++) {
                         j = adapter->rx_ring[i]->reg_idx;
                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
@@ -3349,8 +3624,6 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
 {
         struct ixgbe_hw *hw = &adapter->hw;
         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
-        u32 txdctl;
-        int i, j;
 
         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
                 if (hw->mac.type == ixgbe_mac_82598EB)
@@ -3366,25 +3639,18 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
 #endif
 
-        ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
+        ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
                                         DCB_TX_CONFIG);
-        ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
+        ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
                                         DCB_RX_CONFIG);
 
-        /* reconfigure the hardware */
-        ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
-
-        for (i = 0; i < adapter->num_tx_queues; i++) {
-                j = adapter->tx_ring[i]->reg_idx;
-                txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
-                /* PThresh workaround for Tx hang with DFP enabled. */
-                txdctl |= 32;
-                IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
-        }
         /* Enable VLAN tag insert/strip */
         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
 
         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
+
+        /* reconfigure the hardware */
+        ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
 }
 
 #endif
@@ -3516,8 +3782,9 @@ static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
                 case ixgbe_mac_82598EB:
                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
                         break;
-                default:
                 case ixgbe_mac_82599EB:
+                case ixgbe_mac_X540:
+                default:
                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
                         break;
@@ -3561,13 +3828,24 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
         else
                 ixgbe_configure_msi_and_legacy(adapter);
 
-        /* enable the optics */
-        if (hw->phy.multispeed_fiber)
+        /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
+        if (hw->mac.ops.enable_tx_laser &&
+            ((hw->phy.multispeed_fiber) ||
+             ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
+              (hw->mac.type == ixgbe_mac_82599EB))))
                 hw->mac.ops.enable_tx_laser(hw);
 
         clear_bit(__IXGBE_DOWN, &adapter->state);
         ixgbe_napi_enable_all(adapter);
 
+        if (ixgbe_is_sfp(hw)) {
+                ixgbe_sfp_link_config(adapter);
+        } else {
+                err = ixgbe_non_sfp_link_config(hw);
+                if (err)
+                        e_err(probe, "link_config FAILED %d\n", err);
+        }
+
         /* clear any pending interrupts, may auto mask */
         IXGBE_READ_REG(hw, IXGBE_EICR);
         ixgbe_irq_enable(adapter, true, true);
@@ -3590,26 +3868,8 @@ static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
          * If we're not hot-pluggable SFP+, we just need to configure link
          * and bring it up.
          */
-        if (hw->phy.type == ixgbe_phy_unknown) {
-                err = hw->phy.ops.identify(hw);
-                if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
-                        /*
-                         * Take the device down and schedule the sfp tasklet
-                         * which will unregister_netdev and log it.
-                         */
-                        ixgbe_down(adapter);
-                        schedule_work(&adapter->sfp_config_module_task);
-                        return err;
-                }
-        }
-
-        if (ixgbe_is_sfp(hw)) {
-                ixgbe_sfp_link_config(adapter);
-        } else {
-                err = ixgbe_non_sfp_link_config(hw);
-                if (err)
-                        e_err(probe, "link_config FAILED %d\n", err);
-        }
+        if (hw->phy.type == ixgbe_phy_unknown)
+                schedule_work(&adapter->sfp_config_module_task);
 
         /* enable transmits */
         netif_tx_start_all_queues(adapter->netdev);
@@ -3687,15 +3947,13 @@ void ixgbe_reset(struct ixgbe_adapter *adapter)
 
 /**
  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
- * @adapter: board private structure
  * @rx_ring: ring to free buffers from
  **/
-static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
-                                struct ixgbe_ring *rx_ring)
+static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
 {
-        struct pci_dev *pdev = adapter->pdev;
+        struct device *dev = rx_ring->dev;
         unsigned long size;
-        unsigned int i;
+        u16 i;
 
         /* ring already cleared, nothing to do */
         if (!rx_ring->rx_buffer_info)
@@ -3707,7 +3965,7 @@ static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
 
                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
                 if (rx_buffer_info->dma) {
-                        dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
+                        dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
                                          rx_ring->rx_buf_len,
                                          DMA_FROM_DEVICE);
                         rx_buffer_info->dma = 0;
@@ -3718,7 +3976,7 @@ static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
                         do {
                                 struct sk_buff *this = skb;
                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
-                                        dma_unmap_single(&pdev->dev,
+                                        dma_unmap_single(dev,
                                                          IXGBE_RSC_CB(this)->dma,
                                                          rx_ring->rx_buf_len,
                                                          DMA_FROM_DEVICE);
@@ -3732,7 +3990,7 @@ static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
                 if (!rx_buffer_info->page)
                         continue;
                 if (rx_buffer_info->page_dma) {
-                        dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
+                        dma_unmap_page(dev, rx_buffer_info->page_dma,
                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
                         rx_buffer_info->page_dma = 0;
                 }
@@ -3749,24 +4007,17 @@ static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
 
         rx_ring->next_to_clean = 0;
         rx_ring->next_to_use = 0;
-
-        if (rx_ring->head)
-                writel(0, adapter->hw.hw_addr + rx_ring->head);
-        if (rx_ring->tail)
-                writel(0, adapter->hw.hw_addr + rx_ring->tail);
 }
 
 /**
  * ixgbe_clean_tx_ring - Free Tx Buffers
- * @adapter: board private structure
  * @tx_ring: ring to be cleaned
  **/
-static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
-                                struct ixgbe_ring *tx_ring)
+static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
 {
         struct ixgbe_tx_buffer *tx_buffer_info;
         unsigned long size;
-        unsigned int i;
+        u16 i;
 
         /* ring already cleared, nothing to do */
         if (!tx_ring->tx_buffer_info)
@@ -3775,7 +4026,7 @@ static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
         /* Free all the Tx ring sk_buffs */
         for (i = 0; i < tx_ring->count; i++) {
                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
-                ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
+                ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
         }
 
         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
@@ -3786,11 +4037,6 @@ static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
 
         tx_ring->next_to_use = 0;
         tx_ring->next_to_clean = 0;
-
-        if (tx_ring->head)
-                writel(0, adapter->hw.hw_addr + tx_ring->head);
-        if (tx_ring->tail)
-                writel(0, adapter->hw.hw_addr + tx_ring->tail);
 }
 
 /**
@@ -3802,7 +4048,7 @@ static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
         int i;
 
         for (i = 0; i < adapter->num_rx_queues; i++)
-                ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
+                ixgbe_clean_rx_ring(adapter->rx_ring[i]);
 }
 
 /**
@@ -3814,7 +4060,7 @@ static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
         int i;
 
         for (i = 0; i < adapter->num_tx_queues; i++)
-                ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
+                ixgbe_clean_tx_ring(adapter->tx_ring[i]);
 }
 
 void ixgbe_down(struct ixgbe_adapter *adapter)
@@ -3823,7 +4069,7 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
         struct ixgbe_hw *hw = &adapter->hw;
         u32 rxctrl;
         u32 txdctl;
-        int i, j;
+        int i;
         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 
         /* signal that we are down to the interrupt handler */
@@ -3846,7 +4092,11 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
 
-        IXGBE_WRITE_FLUSH(hw);
+        /* disable all enabled rx queues */
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                /* this call also flushes the previous write */
+                ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
+
         msleep(10);
 
         netif_tx_stop_all_queues(netdev);
@@ -3881,26 +4131,36 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
 
         /* disable transmits in the hardware now that interrupts are off */
         for (i = 0; i < adapter->num_tx_queues; i++) {
-                j = adapter->tx_ring[i]->reg_idx;
-                txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
-                IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
+                u8 reg_idx = adapter->tx_ring[i]->reg_idx;
+                txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
+                IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
         }
         /* Disable the Tx DMA engine on 82599 */
-        if (hw->mac.type == ixgbe_mac_82599EB)
+        switch (hw->mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
                                  ~IXGBE_DMATXCTL_TE));
-
-        /* power down the optics */
-        if (hw->phy.multispeed_fiber)
-                hw->mac.ops.disable_tx_laser(hw);
+                break;
+        default:
+                break;
+        }
 
         /* clear n-tuple filters that are cached */
         ethtool_ntuple_flush(netdev);
 
         if (!pci_channel_offline(adapter->pdev))
                 ixgbe_reset(adapter);
+
+        /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
+        if (hw->mac.ops.disable_tx_laser &&
+            ((hw->phy.multispeed_fiber) ||
+             ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
+              (hw->mac.type == ixgbe_mac_82599EB))))
+                hw->mac.ops.disable_tx_laser(hw);
+
         ixgbe_clean_all_tx_rings(adapter);
         ixgbe_clean_all_rx_rings(adapter);
 
@@ -3925,10 +4185,8 @@ static int ixgbe_poll(struct napi_struct *napi, int budget)
         int tx_clean_complete, work_done = 0;
 
 #ifdef CONFIG_IXGBE_DCA
-        if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
-                ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
-                ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
-        }
+        if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
+                ixgbe_update_dca(q_vector);
 #endif
 
         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
@@ -3956,6 +4214,8 @@ static void ixgbe_tx_timeout(struct net_device *netdev)
 {
         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 
+        adapter->tx_timeout_count++;
+
         /* Do the reset outside of interrupt context */
         schedule_work(&adapter->reset_task);
 }
@@ -3970,8 +4230,6 @@ static void ixgbe_reset_task(struct work_struct *work)
             test_bit(__IXGBE_RESETTING, &adapter->state))
                 return;
 
-        adapter->tx_timeout_count++;
-
         ixgbe_dump(adapter);
         netdev_err(adapter->netdev, "Reset adapter\n");
         ixgbe_reinit_locked(adapter);
@@ -4221,19 +4479,16 @@ static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
 {
         int i;
-        bool ret = false;
 
-        if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
-                for (i = 0; i < adapter->num_rx_queues; i++)
-                        adapter->rx_ring[i]->reg_idx = i;
-                for (i = 0; i < adapter->num_tx_queues; i++)
-                        adapter->tx_ring[i]->reg_idx = i;
-                ret = true;
-        } else {
-                ret = false;
-        }
+        if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
+                return false;
 
-        return ret;
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                adapter->rx_ring[i]->reg_idx = i;
+        for (i = 0; i < adapter->num_tx_queues; i++)
+                adapter->tx_ring[i]->reg_idx = i;
+
+        return true;
 }
 
 #ifdef CONFIG_IXGBE_DCB
@@ -4250,71 +4505,67 @@ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
         bool ret = false;
         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 
-        if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
-                if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
-                        /* the number of queues is assumed to be symmetric */
-                        for (i = 0; i < dcb_i; i++) {
-                                adapter->rx_ring[i]->reg_idx = i << 3;
-                                adapter->tx_ring[i]->reg_idx = i << 2;
-                        }
-                        ret = true;
-                } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
-                        if (dcb_i == 8) {
-                                /*
-                                 * Tx TC0 starts at: descriptor queue 0
-                                 * Tx TC1 starts at: descriptor queue 32
-                                 * Tx TC2 starts at: descriptor queue 64
-                                 * Tx TC3 starts at: descriptor queue 80
-                                 * Tx TC4 starts at: descriptor queue 96
-                                 * Tx TC5 starts at: descriptor queue 104
-                                 * Tx TC6 starts at: descriptor queue 112
-                                 * Tx TC7 starts at: descriptor queue 120
-                                 *
-                                 * Rx TC0-TC7 are offset by 16 queues each
-                                 */
-                                for (i = 0; i < 3; i++) {
-                                        adapter->tx_ring[i]->reg_idx = i << 5;
-                                        adapter->rx_ring[i]->reg_idx = i << 4;
-                                }
-                                for ( ; i < 5; i++) {
-                                        adapter->tx_ring[i]->reg_idx =
-                                                                 ((i + 2) << 4);
-                                        adapter->rx_ring[i]->reg_idx = i << 4;
-                                }
-                                for ( ; i < dcb_i; i++) {
-                                        adapter->tx_ring[i]->reg_idx =
-                                                                 ((i + 8) << 3);
-                                        adapter->rx_ring[i]->reg_idx = i << 4;
-                                }
+        if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
+                return false;
 
-                                ret = true;
-                        } else if (dcb_i == 4) {
-                                /*
-                                 * Tx TC0 starts at: descriptor queue 0
-                                 * Tx TC1 starts at: descriptor queue 64
-                                 * Tx TC2 starts at: descriptor queue 96
-                                 * Tx TC3 starts at: descriptor queue 112
-                                 *
-                                 * Rx TC0-TC3 are offset by 32 queues each
-                                 */
-                                adapter->tx_ring[0]->reg_idx = 0;
-                                adapter->tx_ring[1]->reg_idx = 64;
-                                adapter->tx_ring[2]->reg_idx = 96;
-                                adapter->tx_ring[3]->reg_idx = 112;
-                                for (i = 0 ; i < dcb_i; i++)
-                                        adapter->rx_ring[i]->reg_idx = i << 5;
-
-                                ret = true;
-                        } else {
-                                ret = false;
+        /* the number of queues is assumed to be symmetric */
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82598EB:
+                for (i = 0; i < dcb_i; i++) {
+                        adapter->rx_ring[i]->reg_idx = i << 3;
+                        adapter->tx_ring[i]->reg_idx = i << 2;
+                }
+                ret = true;
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                if (dcb_i == 8) {
+                        /*
+                         * Tx TC0 starts at: descriptor queue 0
+                         * Tx TC1 starts at: descriptor queue 32
+                         * Tx TC2 starts at: descriptor queue 64
+                         * Tx TC3 starts at: descriptor queue 80
+                         * Tx TC4 starts at: descriptor queue 96
+                         * Tx TC5 starts at: descriptor queue 104
+                         * Tx TC6 starts at: descriptor queue 112
+                         * Tx TC7 starts at: descriptor queue 120
+                         *
+                         * Rx TC0-TC7 are offset by 16 queues each
+                         */
+                        for (i = 0; i < 3; i++) {
+                                adapter->tx_ring[i]->reg_idx = i << 5;
+                                adapter->rx_ring[i]->reg_idx = i << 4;
                         }
-                } else {
-                        ret = false;
+                        for ( ; i < 5; i++) {
+                                adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
+                                adapter->rx_ring[i]->reg_idx = i << 4;
+                        }
+                        for ( ; i < dcb_i; i++) {
+                                adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
+                                adapter->rx_ring[i]->reg_idx = i << 4;
+                        }
+                        ret = true;
+                } else if (dcb_i == 4) {
+                        /*
+                         * Tx TC0 starts at: descriptor queue 0
+                         * Tx TC1 starts at: descriptor queue 64
+                         * Tx TC2 starts at: descriptor queue 96
+                         * Tx TC3 starts at: descriptor queue 112
+                         *
+                         * Rx TC0-TC3 are offset by 32 queues each
+                         */
+                        adapter->tx_ring[0]->reg_idx = 0;
+                        adapter->tx_ring[1]->reg_idx = 64;
+                        adapter->tx_ring[2]->reg_idx = 96;
+                        adapter->tx_ring[3]->reg_idx = 112;
+                        for (i = 0 ; i < dcb_i; i++)
+                                adapter->rx_ring[i]->reg_idx = i << 5;
+                        ret = true;
                 }
-        } else {
-                ret = false;
+                break;
+        default:
+                break;
         }
-
         return ret;
 }
 #endif
@@ -4354,55 +4605,55 @@ static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
  */
 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
 {
-        int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
-        bool ret = false;
         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
+        int i;
+        u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
+
+        if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
+                return false;
 
-        if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 #ifdef CONFIG_IXGBE_DCB
-                if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
-                        struct ixgbe_fcoe *fcoe = &adapter->fcoe;
+        if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
+                struct ixgbe_fcoe *fcoe = &adapter->fcoe;
 
-                        ixgbe_cache_ring_dcb(adapter);
-                        /* find out queues in TC for FCoE */
-                        fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
-                        fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
-                        /*
-                         * In 82599, the number of Tx queues for each traffic
-                         * class for both 8-TC and 4-TC modes are:
-                         * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
-                         * 8 TCs:  32  32  16  16   8   8   8   8
-                         * 4 TCs:  64  64  32  32
-                         * We have max 8 queues for FCoE, where 8 the is
-                         * FCoE redirection table size. If TC for FCoE is
-                         * less than or equal to TC3, we have enough queues
-                         * to add max of 8 queues for FCoE, so we start FCoE
-                         * tx descriptor from the next one, i.e., reg_idx + 1.
-                         * If TC for FCoE is above TC3, implying 8 TC mode,
-                         * and we need 8 for FCoE, we have to take all queues
-                         * in that traffic class for FCoE.
-                         */
-                        if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
-                                fcoe_tx_i--;
-                }
+                ixgbe_cache_ring_dcb(adapter);
+                /* find out queues in TC for FCoE */
+                fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
+                fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
+                /*
+                 * In 82599, the number of Tx queues for each traffic
+                 * class for both 8-TC and 4-TC modes are:
+                 * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
+                 * 8 TCs:  32  32  16  16   8   8   8   8
+                 * 4 TCs:  64  64  32  32
+                 * We have max 8 queues for FCoE, where 8 the is
+                 * FCoE redirection table size. If TC for FCoE is
+                 * less than or equal to TC3, we have enough queues
+                 * to add max of 8 queues for FCoE, so we start FCoE
+                 * Tx queue from the next one, i.e., reg_idx + 1.
+                 * If TC for FCoE is above TC3, implying 8 TC mode,
+                 * and we need 8 for FCoE, we have to take all queues
+                 * in that traffic class for FCoE.
+                 */
+                if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
+                        fcoe_tx_i--;
+        }
 #endif /* CONFIG_IXGBE_DCB */
-                if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
-                        if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
-                            (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
-                                ixgbe_cache_ring_fdir(adapter);
-                        else
-                                ixgbe_cache_ring_rss(adapter);
+        if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
+                if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
+                    (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
+                        ixgbe_cache_ring_fdir(adapter);
+                else
+                        ixgbe_cache_ring_rss(adapter);
 
-                        fcoe_rx_i = f->mask;
-                        fcoe_tx_i = f->mask;
-                }
-                for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
-                        adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
-                        adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
-                }
-                ret = true;
+                fcoe_rx_i = f->mask;
+                fcoe_tx_i = f->mask;
         }
-        return ret;
+        for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
+                adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
+                adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
+        }
+        return true;
 }
 
 #endif /* IXGBE_FCOE */
@@ -4471,65 +4722,55 @@ static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
  **/
 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
 {
-        int i;
-        int orig_node = adapter->node;
+        int rx = 0, tx = 0, nid = adapter->node;
 
-        for (i = 0; i < adapter->num_tx_queues; i++) {
-                struct ixgbe_ring *ring = adapter->tx_ring[i];
-                if (orig_node == -1) {
-                        int cur_node = next_online_node(adapter->node);
-                        if (cur_node == MAX_NUMNODES)
-                                cur_node = first_online_node;
-                        adapter->node = cur_node;
-                }
-                ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
-                                    adapter->node);
+        if (nid < 0 || !node_online(nid))
+                nid = first_online_node;
+
+        for (; tx < adapter->num_tx_queues; tx++) {
+                struct ixgbe_ring *ring;
+
+                ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
                 if (!ring)
-                        ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
+                        ring = kzalloc(sizeof(*ring), GFP_KERNEL);
                 if (!ring)
-                        goto err_tx_ring_allocation;
+                        goto err_allocation;
                 ring->count = adapter->tx_ring_count;
-                ring->queue_index = i;
-                ring->numa_node = adapter->node;
+                ring->queue_index = tx;
+                ring->numa_node = nid;
+                ring->dev = &adapter->pdev->dev;
+                ring->netdev = adapter->netdev;
 
-                adapter->tx_ring[i] = ring;
+                adapter->tx_ring[tx] = ring;
         }
 
-        /* Restore the adapter's original node */
-        adapter->node = orig_node;
+        for (; rx < adapter->num_rx_queues; rx++) {
+                struct ixgbe_ring *ring;
 
-        for (i = 0; i < adapter->num_rx_queues; i++) {
-                struct ixgbe_ring *ring = adapter->rx_ring[i];
-                if (orig_node == -1) {
-                        int cur_node = next_online_node(adapter->node);
-                        if (cur_node == MAX_NUMNODES)
-                                cur_node = first_online_node;
-                        adapter->node = cur_node;
-                }
-                ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
-                                    adapter->node);
+                ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
                 if (!ring)
-                        ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
+                        ring = kzalloc(sizeof(*ring), GFP_KERNEL);
                 if (!ring)
-                        goto err_rx_ring_allocation;
+                        goto err_allocation;
                 ring->count = adapter->rx_ring_count;
-                ring->queue_index = i;
-                ring->numa_node = adapter->node;
+                ring->queue_index = rx;
+                ring->numa_node = nid;
+                ring->dev = &adapter->pdev->dev;
+                ring->netdev = adapter->netdev;
 
-                adapter->rx_ring[i] = ring;
+                adapter->rx_ring[rx] = ring;
         }
 
-        /* Restore the adapter's original node */
-        adapter->node = orig_node;
-
         ixgbe_cache_ring_register(adapter);
 
         return 0;
 
-err_rx_ring_allocation:
-        for (i = 0; i < adapter->num_tx_queues; i++)
-                kfree(adapter->tx_ring[i]);
-err_tx_ring_allocation:
+err_allocation:
+        while (tx)
+                kfree(adapter->tx_ring[--tx]);
+
+        while (rx)
+                kfree(adapter->rx_ring[--rx]);
         return -ENOMEM;
 }
 
@@ -4580,6 +4821,12 @@ static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
 
         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
+        if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
+                              IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
+                e_err(probe,
+                      "Flow Director is not supported while multiple "
+                      "queues are disabled.  Disabling Flow Director\n");
+        }
         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
         adapter->atr_sample_rate = 0;
@@ -4751,6 +4998,11 @@ err_set_interrupt:
         return err;
 }
 
+static void ring_free_rcu(struct rcu_head *head)
+{
+        kfree(container_of(head, struct ixgbe_ring, rcu));
+}
+
 /**
  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
  * @adapter: board private structure to clear interrupt scheme on
@@ -4767,7 +5019,12 @@ void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
                 adapter->tx_ring[i] = NULL;
         }
         for (i = 0; i < adapter->num_rx_queues; i++) {
-                kfree(adapter->rx_ring[i]);
+                struct ixgbe_ring *ring = adapter->rx_ring[i];
+
+                /* ixgbe_get_stats64() might access this ring, we must wait
+                 * a grace period before freeing it.
+                 */
+                call_rcu(&ring->rcu, ring_free_rcu);
                 adapter->rx_ring[i] = NULL;
         }
 
@@ -4847,6 +5104,7 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
         int j;
         struct tc_configuration *tc;
 #endif
+        int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
 
         /* PCI config space info */
 
@@ -4861,26 +5119,24 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
         adapter->ring_feature[RING_F_RSS].indices = rss;
         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
-        if (hw->mac.type == ixgbe_mac_82598EB) {
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
-        } else if (hw->mac.type == ixgbe_mac_82599EB) {
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
-                if (dev->features & NETIF_F_NTUPLE) {
-                        /* Flow Director perfect filter enabled */
-                        adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
-                        adapter->atr_sample_rate = 0;
-                        spin_lock_init(&adapter->fdir_perfect_lock);
-                } else {
-                        /* Flow Director hash filters enabled */
-                        adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
-                        adapter->atr_sample_rate = 20;
-                }
+                /* n-tuple support exists, always init our spinlock */
+                spin_lock_init(&adapter->fdir_perfect_lock);
+                /* Flow Director hash filters enabled */
+                adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
+                adapter->atr_sample_rate = 20;
                 adapter->ring_feature[RING_F_FDIR].indices =
                                                          IXGBE_MAX_FDIR_INDICES;
                 adapter->fdir_pballoc = 0;
@@ -4894,6 +5150,9 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
 #endif
 #endif /* IXGBE_FCOE */
+                break;
+        default:
+                break;
         }
 
 #ifdef CONFIG_IXGBE_DCB
@@ -4923,8 +5182,8 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
 #ifdef CONFIG_DCB
         adapter->last_lfc_mode = hw->fc.current_mode;
 #endif
-        hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
-        hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
+        hw->fc.high_water = FC_HIGH_WATER(max_frame);
+        hw->fc.low_water = FC_LOW_WATER(max_frame);
         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
         hw->fc.send_xon = true;
         hw->fc.disable_fc_autoneg = false;
@@ -4962,30 +5221,27 @@ static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
 
 /**
  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
- * @adapter: board private structure
  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
  *
  * Return 0 on success, negative on failure
  **/
-int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
-                             struct ixgbe_ring *tx_ring)
+int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
 {
-        struct pci_dev *pdev = adapter->pdev;
+        struct device *dev = tx_ring->dev;
         int size;
 
         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
-        tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
+        tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
         if (!tx_ring->tx_buffer_info)
-                tx_ring->tx_buffer_info = vmalloc(size);
+                tx_ring->tx_buffer_info = vzalloc(size);
         if (!tx_ring->tx_buffer_info)
                 goto err;
-        memset(tx_ring->tx_buffer_info, 0, size);
 
         /* round up to nearest 4K */
         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
         tx_ring->size = ALIGN(tx_ring->size, 4096);
 
-        tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
+        tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
                                            &tx_ring->dma, GFP_KERNEL);
         if (!tx_ring->desc)
                 goto err;
@@ -4998,7 +5254,7 @@ int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
 err:
         vfree(tx_ring->tx_buffer_info);
         tx_ring->tx_buffer_info = NULL;
-        e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
+        dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
         return -ENOMEM;
 }
 
@@ -5017,7 +5273,7 @@ static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
         int i, err = 0;
 
         for (i = 0; i < adapter->num_tx_queues; i++) {
-                err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
+                err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
                 if (!err)
                         continue;
                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
@@ -5029,48 +5285,40 @@ static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
 
 /**
  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
- * @adapter: board private structure
  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
  *
  * Returns 0 on success, negative on failure
  **/
-int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
-                             struct ixgbe_ring *rx_ring)
+int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
 {
-        struct pci_dev *pdev = adapter->pdev;
+        struct device *dev = rx_ring->dev;
         int size;
 
         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
-        rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
+        rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
         if (!rx_ring->rx_buffer_info)
-                rx_ring->rx_buffer_info = vmalloc(size);
-        if (!rx_ring->rx_buffer_info) {
-                e_err(probe, "vmalloc allocation failed for the Rx "
-                      "descriptor ring\n");
-                goto alloc_failed;
-        }
-        memset(rx_ring->rx_buffer_info, 0, size);
+                rx_ring->rx_buffer_info = vzalloc(size);
+        if (!rx_ring->rx_buffer_info)
+                goto err;
 
         /* Round up to nearest 4K */
         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
         rx_ring->size = ALIGN(rx_ring->size, 4096);
 
-        rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
+        rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
                                            &rx_ring->dma, GFP_KERNEL);
 
-        if (!rx_ring->desc) {
-                e_err(probe, "Memory allocation failed for the Rx "
-                      "descriptor ring\n");
-                vfree(rx_ring->rx_buffer_info);
-                goto alloc_failed;
-        }
+        if (!rx_ring->desc)
+                goto err;
 
         rx_ring->next_to_clean = 0;
         rx_ring->next_to_use = 0;
 
         return 0;
-
-alloc_failed:
+err:
+        vfree(rx_ring->rx_buffer_info);
+        rx_ring->rx_buffer_info = NULL;
+        dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
         return -ENOMEM;
 }
 
@@ -5084,13 +5332,12 @@ alloc_failed:
  *
  * Return 0 on success, negative on failure
  **/
-
 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
 {
         int i, err = 0;
 
         for (i = 0; i < adapter->num_rx_queues; i++) {
-                err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
+                err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
                 if (!err)
                         continue;
                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
@@ -5102,23 +5349,23 @@ static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
 
 /**
  * ixgbe_free_tx_resources - Free Tx Resources per Queue
- * @adapter: board private structure
  * @tx_ring: Tx descriptor ring for a specific queue
  *
  * Free all transmit software resources
  **/
-void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
-                             struct ixgbe_ring *tx_ring)
+void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
 {
-        struct pci_dev *pdev = adapter->pdev;
-
-        ixgbe_clean_tx_ring(adapter, tx_ring);
+        ixgbe_clean_tx_ring(tx_ring);
 
         vfree(tx_ring->tx_buffer_info);
         tx_ring->tx_buffer_info = NULL;
 
-        dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
-                          tx_ring->dma);
+        /* if not set, then don't free */
+        if (!tx_ring->desc)
+                return;
+
+        dma_free_coherent(tx_ring->dev, tx_ring->size,
+                          tx_ring->desc, tx_ring->dma);
 
         tx_ring->desc = NULL;
 }
@@ -5135,28 +5382,28 @@ static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
 
         for (i = 0; i < adapter->num_tx_queues; i++)
                 if (adapter->tx_ring[i]->desc)
-                        ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
+                        ixgbe_free_tx_resources(adapter->tx_ring[i]);
 }
 
 /**
  * ixgbe_free_rx_resources - Free Rx Resources
- * @adapter: board private structure
  * @rx_ring: ring to clean the resources from
  *
  * Free all receive software resources
  **/
-void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
-                             struct ixgbe_ring *rx_ring)
+void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
 {
-        struct pci_dev *pdev = adapter->pdev;
-
-        ixgbe_clean_rx_ring(adapter, rx_ring);
+        ixgbe_clean_rx_ring(rx_ring);
 
         vfree(rx_ring->rx_buffer_info);
         rx_ring->rx_buffer_info = NULL;
 
-        dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
-                          rx_ring->dma);
+        /* if not set, then don't free */
+        if (!rx_ring->desc)
+                return;
+
+        dma_free_coherent(rx_ring->dev, rx_ring->size,
+                          rx_ring->desc, rx_ring->dma);
 
         rx_ring->desc = NULL;
 }
@@ -5173,7 +5420,7 @@ static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
 
         for (i = 0; i < adapter->num_rx_queues; i++)
                 if (adapter->rx_ring[i]->desc)
-                        ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
+                        ixgbe_free_rx_resources(adapter->rx_ring[i]);
 }
 
 /**
@@ -5186,6 +5433,7 @@ static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
 {
         struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_hw *hw = &adapter->hw;
         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
 
         /* MTU < 68 is an error and causes problems on some kernels */
@@ -5196,6 +5444,9 @@ static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
         /* must set new MTU before calling down or up */
         netdev->mtu = new_mtu;
 
+        hw->fc.high_water = FC_HIGH_WATER(max_frame);
+        hw->fc.low_water = FC_LOW_WATER(max_frame);
+
         if (netif_running(netdev))
                 ixgbe_reinit_locked(adapter);
 
@@ -5291,8 +5542,8 @@ static int ixgbe_close(struct net_device *netdev)
 #ifdef CONFIG_PM
 static int ixgbe_resume(struct pci_dev *pdev)
 {
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
         u32 err;
 
         pci_set_power_state(pdev, PCI_D0);
@@ -5323,7 +5574,7 @@ static int ixgbe_resume(struct pci_dev *pdev)
         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
 
         if (netif_running(netdev)) {
-                err = ixgbe_open(adapter->netdev);
+                err = ixgbe_open(netdev);
                 if (err)
                         return err;
         }
@@ -5336,8 +5587,8 @@ static int ixgbe_resume(struct pci_dev *pdev)
 
 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
 {
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
         struct ixgbe_hw *hw = &adapter->hw;
         u32 ctrl, fctrl;
         u32 wufc = adapter->wol;
@@ -5354,6 +5605,8 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
                 ixgbe_free_all_rx_resources(adapter);
         }
 
+        ixgbe_clear_interrupt_scheme(adapter);
+
 #ifdef CONFIG_PM
         retval = pci_save_state(pdev);
         if (retval)
@@ -5380,15 +5633,20 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
         }
 
-        if (wufc && hw->mac.type == ixgbe_mac_82599EB)
-                pci_wake_from_d3(pdev, true);
-        else
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
                 pci_wake_from_d3(pdev, false);
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                pci_wake_from_d3(pdev, !!wufc);
+                break;
+        default:
+                break;
+        }
 
         *enable_wake = !!wufc;
 
-        ixgbe_clear_interrupt_scheme(adapter);
-
         ixgbe_release_hw_control(adapter);
 
         pci_disable_device(pdev);
@@ -5437,10 +5695,12 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
 {
         struct net_device *netdev = adapter->netdev;
         struct ixgbe_hw *hw = &adapter->hw;
+        struct ixgbe_hw_stats *hwstats = &adapter->stats;
         u64 total_mpc = 0;
         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
-        u64 non_eop_descs = 0, restart_queue = 0;
-        struct ixgbe_hw_stats *hwstats = &adapter->stats;
+        u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
+        u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
+        u64 bytes = 0, packets = 0;
 
         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
             test_bit(__IXGBE_RESETTING, &adapter->state))
@@ -5453,21 +5713,41 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
                         adapter->hw_rx_no_dma_resources +=
                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
                 for (i = 0; i < adapter->num_rx_queues; i++) {
-                        rsc_count += adapter->rx_ring[i]->rsc_count;
-                        rsc_flush += adapter->rx_ring[i]->rsc_flush;
+                        rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
+                        rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
                 }
                 adapter->rsc_total_count = rsc_count;
                 adapter->rsc_total_flush = rsc_flush;
         }
 
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
+                non_eop_descs += rx_ring->rx_stats.non_eop_descs;
+                alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
+                alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
+                bytes += rx_ring->stats.bytes;
+                packets += rx_ring->stats.packets;
+        }
+        adapter->non_eop_descs = non_eop_descs;
+        adapter->alloc_rx_page_failed = alloc_rx_page_failed;
+        adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
+        netdev->stats.rx_bytes = bytes;
+        netdev->stats.rx_packets = packets;
+
+        bytes = 0;
+        packets = 0;
         /* gather some stats to the adapter struct that are per queue */
-        for (i = 0; i < adapter->num_tx_queues; i++)
-                restart_queue += adapter->tx_ring[i]->restart_queue;
+        for (i = 0; i < adapter->num_tx_queues; i++) {
+                struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
+                restart_queue += tx_ring->tx_stats.restart_queue;
+                tx_busy += tx_ring->tx_stats.tx_busy;
+                bytes += tx_ring->stats.bytes;
+                packets += tx_ring->stats.packets;
+        }
         adapter->restart_queue = restart_queue;
-
-        for (i = 0; i < adapter->num_rx_queues; i++)
-                non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
-        adapter->non_eop_descs = non_eop_descs;
+        adapter->tx_busy = tx_busy;
+        netdev->stats.tx_bytes = bytes;
+        netdev->stats.tx_packets = packets;
 
         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
         for (i = 0; i < 8; i++) {
@@ -5482,17 +5762,18 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
-                if (hw->mac.type == ixgbe_mac_82599EB) {
-                        hwstats->pxonrxc[i] +=
-                                IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
-                        hwstats->pxoffrxc[i] +=
-                                IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
-                        hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
-                } else {
+                switch (hw->mac.type) {
+                case ixgbe_mac_82598EB:
                         hwstats->pxonrxc[i] +=
                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
-                        hwstats->pxoffrxc[i] +=
-                                IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
+                        break;
+                case ixgbe_mac_82599EB:
+                case ixgbe_mac_X540:
+                        hwstats->pxonrxc[i] +=
+                                IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
+                        break;
+                default:
+                        break;
                 }
                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
@@ -5501,21 +5782,25 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
         /* work around hardware counting issue */
         hwstats->gprc -= missed_rx;
 
+        ixgbe_update_xoff_received(adapter);
+
         /* 82598 hardware only has a 32 bit counter in the high register */
-        if (hw->mac.type == ixgbe_mac_82599EB) {
-                u64 tmp;
+        switch (hw->mac.type) {
+        case ixgbe_mac_82598EB:
+                hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
+                hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
+                hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
+                hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
+                break;
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
-                tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
-                                                /* 4 high bits of GORC */
-                hwstats->gorc += (tmp << 32);
+                IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
-                tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
-                                                /* 4 high bits of GOTC */
-                hwstats->gotc += (tmp << 32);
+                IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
-                IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
+                IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
-                hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
 #ifdef IXGBE_FCOE
@@ -5526,12 +5811,9 @@ void ixgbe_update_stats(struct ixgbe_adapter *adapter)
                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
 #endif /* IXGBE_FCOE */
-        } else {
-                hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
-                hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
-                hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
-                hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
-                hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
+                break;
+        default:
+                break;
         }
         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
         hwstats->bprc += bprc;
@@ -5704,8 +5986,8 @@ static void ixgbe_fdir_reinit_task(struct work_struct *work)
 
         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
                 for (i = 0; i < adapter->num_tx_queues; i++)
-                        set_bit(__IXGBE_FDIR_INIT_DONE,
-                                &(adapter->tx_ring[i]->reinit_state));
+                        set_bit(__IXGBE_TX_FDIR_INIT_DONE,
+                                &(adapter->tx_ring[i]->state));
         } else {
                 e_err(probe, "failed to finish FDIR re-initialization, "
                       "ignored adding FDIR ATR filters\n");
@@ -5714,6 +5996,26 @@ static void ixgbe_fdir_reinit_task(struct work_struct *work)
         netif_tx_start_all_queues(adapter->netdev);
 }
 
+static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
+{
+        u32 ssvpc;
+
+        /* Do not perform spoof check for 82598 */
+        if (adapter->hw.mac.type == ixgbe_mac_82598EB)
+                return;
+
+        ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
+
+        /*
+         * ssvpc register is cleared on read, if zero then no
+         * spoofed packets in the last interval.
+         */
+        if (!ssvpc)
+                return;
+
+        e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
+}
+
 static DEFINE_MUTEX(ixgbe_watchdog_lock);
 
 /**
@@ -5767,17 +6069,27 @@ static void ixgbe_watchdog_task(struct work_struct *work)
                 if (!netif_carrier_ok(netdev)) {
                         bool flow_rx, flow_tx;
 
-                        if (hw->mac.type == ixgbe_mac_82599EB) {
-                                u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
-                                u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
-                                flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
-                                flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
-                        } else {
+                        switch (hw->mac.type) {
+                        case ixgbe_mac_82598EB: {
                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
                         }
+                                break;
+                        case ixgbe_mac_82599EB:
+                        case ixgbe_mac_X540: {
+                                u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
+                                u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
+                                flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
+                                flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
+                        }
+                                break;
+                        default:
+                                flow_tx = false;
+                                flow_rx = false;
+                                break;
+                        }
 
                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
@@ -5791,7 +6103,10 @@ static void ixgbe_watchdog_task(struct work_struct *work)
                         netif_carrier_on(netdev);
                 } else {
                         /* Force detection of hung controller */
-                        adapter->detect_tx_hung = true;
+                        for (i = 0; i < adapter->num_tx_queues; i++) {
+                                tx_ring = adapter->tx_ring[i];
+                                set_check_for_tx_hang(tx_ring);
+                        }
                 }
         } else {
                 adapter->link_up = false;
@@ -5821,6 +6136,7 @@ static void ixgbe_watchdog_task(struct work_struct *work)
                 }
         }
 
+        ixgbe_spoof_check(adapter);
         ixgbe_update_stats(adapter);
         mutex_unlock(&ixgbe_watchdog_lock);
 }
@@ -6003,15 +6319,17 @@ static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
                         struct ixgbe_ring *tx_ring,
                         struct sk_buff *skb, u32 tx_flags,
-                        unsigned int first)
+                        unsigned int first, const u8 hdr_len)
 {
-        struct pci_dev *pdev = adapter->pdev;
+        struct device *dev = tx_ring->dev;
         struct ixgbe_tx_buffer *tx_buffer_info;
         unsigned int len;
         unsigned int total = skb->len;
         unsigned int offset = 0, size, count = 0, i;
         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
         unsigned int f;
+        unsigned int bytecount = skb->len;
+        u16 gso_segs = 1;
 
         i = tx_ring->next_to_use;
 
@@ -6026,10 +6344,10 @@ static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
 
                 tx_buffer_info->length = size;
                 tx_buffer_info->mapped_as_page = false;
-                tx_buffer_info->dma = dma_map_single(&pdev->dev,
+                tx_buffer_info->dma = dma_map_single(dev,
                                                      skb->data + offset,
                                                      size, DMA_TO_DEVICE);
-                if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
+                if (dma_mapping_error(dev, tx_buffer_info->dma))
                         goto dma_error;
                 tx_buffer_info->time_stamp = jiffies;
                 tx_buffer_info->next_to_watch = i;
@@ -6062,12 +6380,12 @@ static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
 
                         tx_buffer_info->length = size;
-                        tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
+                        tx_buffer_info->dma = dma_map_page(dev,
                                                            frag->page,
                                                            offset, size,
                                                            DMA_TO_DEVICE);
                         tx_buffer_info->mapped_as_page = true;
-                        if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
+                        if (dma_mapping_error(dev, tx_buffer_info->dma))
                                 goto dma_error;
                         tx_buffer_info->time_stamp = jiffies;
                         tx_buffer_info->next_to_watch = i;
@@ -6081,6 +6399,19 @@ static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
                         break;
         }
 
+        if (tx_flags & IXGBE_TX_FLAGS_TSO)
+                gso_segs = skb_shinfo(skb)->gso_segs;
+#ifdef IXGBE_FCOE
+        /* adjust for FCoE Sequence Offload */
+        else if (tx_flags & IXGBE_TX_FLAGS_FSO)
+                gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
+                                        skb_shinfo(skb)->gso_size);
+#endif /* IXGBE_FCOE */
+        bytecount += (gso_segs - 1) * hdr_len;
+
+        /* multiply data chunks by size of headers */
+        tx_ring->tx_buffer_info[i].bytecount = bytecount;
+        tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
         tx_ring->tx_buffer_info[i].skb = skb;
         tx_ring->tx_buffer_info[first].next_to_watch = i;
 
@@ -6102,14 +6433,13 @@ dma_error:
                         i += tx_ring->count;
                 i--;
                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
-                ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
+                ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
         }
 
         return 0;
 }
 
-static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
-                           struct ixgbe_ring *tx_ring,
+static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
                            int tx_flags, int count, u32 paylen, u8 hdr_len)
 {
         union ixgbe_adv_tx_desc *tx_desc = NULL;
@@ -6174,60 +6504,100 @@ static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
         wmb();
 
         tx_ring->next_to_use = i;
-        writel(i, adapter->hw.hw_addr + tx_ring->tail);
+        writel(i, tx_ring->tail);
 }
 
-static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
-                      int queue, u32 tx_flags, __be16 protocol)
+static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
+                      u32 tx_flags, __be16 protocol)
 {
-        struct ixgbe_atr_input atr_input;
+        struct ixgbe_q_vector *q_vector = ring->q_vector;
+        union ixgbe_atr_hash_dword input = { .dword = 0 };
+        union ixgbe_atr_hash_dword common = { .dword = 0 };
+        union {
+                unsigned char *network;
+                struct iphdr *ipv4;
+                struct ipv6hdr *ipv6;
+        } hdr;
         struct tcphdr *th;
-        struct iphdr *iph = ip_hdr(skb);
-        struct ethhdr *eth = (struct ethhdr *)skb->data;
-        u16 vlan_id, src_port, dst_port, flex_bytes;
-        u32 src_ipv4_addr, dst_ipv4_addr;
-        u8 l4type = 0;
-
-        /* Right now, we support IPv4 only */
-        if (protocol != htons(ETH_P_IP))
+        __be16 vlan_id;
+
+        /* if ring doesn't have a interrupt vector, cannot perform ATR */
+        if (!q_vector)
                 return;
-        /* check if we're UDP or TCP */
-        if (iph->protocol == IPPROTO_TCP) {
-                th = tcp_hdr(skb);
-                src_port = th->source;
-                dst_port = th->dest;
-                l4type |= IXGBE_ATR_L4TYPE_TCP;
-                /* l4type IPv4 type is 0, no need to assign */
-        } else {
-                /* Unsupported L4 header, just bail here */
+
+        /* do nothing if sampling is disabled */
+        if (!ring->atr_sample_rate)
                 return;
-        }
 
-        memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
+        ring->atr_count++;
 
-        vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
-                   IXGBE_TX_FLAGS_VLAN_SHIFT;
-        src_ipv4_addr = iph->saddr;
-        dst_ipv4_addr = iph->daddr;
-        flex_bytes = eth->h_proto;
+        /* snag network header to get L4 type and address */
+        hdr.network = skb_network_header(skb);
 
-        ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
-        ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
-        ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
-        ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
-        ixgbe_atr_set_l4type_82599(&atr_input, l4type);
-        /* src and dst are inverted, think how the receiver sees them */
-        ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
-        ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
+        /* Currently only IPv4/IPv6 with TCP is supported */
+        if ((protocol != __constant_htons(ETH_P_IPV6) ||
+             hdr.ipv6->nexthdr != IPPROTO_TCP) &&
+            (protocol != __constant_htons(ETH_P_IP) ||
+             hdr.ipv4->protocol != IPPROTO_TCP))
+                return;
+
+        th = tcp_hdr(skb);
+
+        /* skip this packet since the socket is closing */
+        if (th->fin)
+                return;
+
+        /* sample on all syn packets or once every atr sample count */
+        if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
+                return;
+
+        /* reset sample count */
+        ring->atr_count = 0;
+
+        vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
+
+        /*
+         * src and dst are inverted, think how the receiver sees them
+         *
+         * The input is broken into two sections, a non-compressed section
+         * containing vm_pool, vlan_id, and flow_type.  The rest of the data
+         * is XORed together and stored in the compressed dword.
+         */
+        input.formatted.vlan_id = vlan_id;
+
+        /*
+         * since src port and flex bytes occupy the same word XOR them together
+         * and write the value to source port portion of compressed dword
+         */
+        if (vlan_id)
+                common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
+        else
+                common.port.src ^= th->dest ^ protocol;
+        common.port.dst ^= th->source;
+
+        if (protocol == __constant_htons(ETH_P_IP)) {
+                input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
+                common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
+        } else {
+                input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
+                common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
+                             hdr.ipv6->saddr.s6_addr32[1] ^
+                             hdr.ipv6->saddr.s6_addr32[2] ^
+                             hdr.ipv6->saddr.s6_addr32[3] ^
+                             hdr.ipv6->daddr.s6_addr32[0] ^
+                             hdr.ipv6->daddr.s6_addr32[1] ^
+                             hdr.ipv6->daddr.s6_addr32[2] ^
+                             hdr.ipv6->daddr.s6_addr32[3];
+        }
 
         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
-        ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
+        ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
+                                              input, common, ring->queue_index);
 }
 
-static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
-                                 struct ixgbe_ring *tx_ring, int size)
+static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
 {
-        netif_stop_subqueue(netdev, tx_ring->queue_index);
+        netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
         /* Herbert's original patch had:
          *  smp_mb__after_netif_stop_queue();
          * but since that doesn't exist yet, just open code it. */
@@ -6239,17 +6609,16 @@ static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
                 return -EBUSY;
 
         /* A reprieve! - use start_queue because it doesn't call schedule */
-        netif_start_subqueue(netdev, tx_ring->queue_index);
-        ++tx_ring->restart_queue;
+        netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
+        ++tx_ring->tx_stats.restart_queue;
         return 0;
 }
 
-static int ixgbe_maybe_stop_tx(struct net_device *netdev,
-                              struct ixgbe_ring *tx_ring, int size)
+static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
 {
         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
                 return 0;
-        return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
+        return __ixgbe_maybe_stop_tx(tx_ring, size);
 }
 
 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
@@ -6294,10 +6663,11 @@ static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
         return skb_tx_hash(dev, skb);
 }
 
-netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
+netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
                           struct ixgbe_adapter *adapter,
                           struct ixgbe_ring *tx_ring)
 {
+        struct net_device *netdev = tx_ring->netdev;
         struct netdev_queue *txq;
         unsigned int first;
         unsigned int tx_flags = 0;
@@ -6355,8 +6725,8 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev
         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
 
-        if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
-                adapter->tx_busy++;
+        if (ixgbe_maybe_stop_tx(tx_ring, count)) {
+                tx_ring->tx_stats.tx_busy++;
                 return NETDEV_TX_BUSY;
         }
 
@@ -6390,25 +6760,16 @@ netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev
                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
         }
 
-        count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
+        count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
         if (count) {
                 /* add the ATR filter if ATR is on */
-                if (tx_ring->atr_sample_rate) {
-                        ++tx_ring->atr_count;
-                        if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
-                             test_bit(__IXGBE_FDIR_INIT_DONE,
-                                      &tx_ring->reinit_state)) {
-                                ixgbe_atr(adapter, skb, tx_ring->queue_index,
-                                          tx_flags, protocol);
-                                tx_ring->atr_count = 0;
-                        }
-                }
+                if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
+                        ixgbe_atr(tx_ring, skb, tx_flags, protocol);
                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
                 txq->tx_bytes += skb->len;
                 txq->tx_packets++;
-                ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
-                               hdr_len);
-                ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
+                ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
+                ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
 
         } else {
                 dev_kfree_skb_any(skb);
@@ -6425,7 +6786,7 @@ static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netd
         struct ixgbe_ring *tx_ring;
 
         tx_ring = adapter->tx_ring[skb->queue_mapping];
-        return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
+        return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
 }
 
 /**
@@ -6566,20 +6927,23 @@ static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
 
         /* accurate rx/tx bytes/packets stats */
         dev_txq_stats_fold(netdev, stats);
+        rcu_read_lock();
         for (i = 0; i < adapter->num_rx_queues; i++) {
-                struct ixgbe_ring *ring = adapter->rx_ring[i];
+                struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
                 u64 bytes, packets;
                 unsigned int start;
 
-                do {
-                        start = u64_stats_fetch_begin_bh(&ring->syncp);
-                        packets = ring->stats.packets;
-                        bytes   = ring->stats.bytes;
-                } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
-                stats->rx_packets += packets;
-                stats->rx_bytes   += bytes;
+                if (ring) {
+                        do {
+                                start = u64_stats_fetch_begin_bh(&ring->syncp);
+                                packets = ring->stats.packets;
+                                bytes   = ring->stats.bytes;
+                        } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
+                        stats->rx_packets += packets;
+                        stats->rx_bytes   += bytes;
+                }
         }
-
+        rcu_read_unlock();
         /* following stats updated by ixgbe_watchdog_task() */
         stats->multicast        = netdev->stats.multicast;
         stats->rx_errors        = netdev->stats.rx_errors;
@@ -6628,7 +6992,7 @@ static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
         struct ixgbe_hw *hw = &adapter->hw;
         int err;
 
-        if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
+        if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
                 return;
 
         /* The 82599 supports up to 64 VFs per physical function
@@ -6694,11 +7058,12 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
         static int cards_found;
         int i, err, pci_using_dac;
+        u8 part_str[IXGBE_PBANUM_LENGTH];
         unsigned int indices = num_possible_cpus();
 #ifdef IXGBE_FCOE
         u16 device_caps;
 #endif
-        u32 part_num, eec;
+        u32 eec;
 
         /* Catch broken hardware that put the wrong VF device ID in
          * the PCIe SR-IOV capability.
@@ -6761,8 +7126,8 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
 
         SET_NETDEV_DEV(netdev, &pdev->dev);
 
-        pci_set_drvdata(pdev, netdev);
         adapter = netdev_priv(netdev);
+        pci_set_drvdata(pdev, adapter);
 
         adapter->netdev = netdev;
         adapter->pdev = pdev;
@@ -6785,7 +7150,7 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
         netdev->netdev_ops = &ixgbe_netdev_ops;
         ixgbe_set_ethtool_ops(netdev);
         netdev->watchdog_timeo = 5 * HZ;
-        strcpy(netdev->name, pci_name(pdev));
+        strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
 
         adapter->bd_number = cards_found;
 
@@ -6835,8 +7200,14 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
                 goto err_sw_init;
 
         /* Make it possible the adapter to be woken up via WOL */
-        if (adapter->hw.mac.type == ixgbe_mac_82599EB)
+        switch (adapter->hw.mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
+                break;
+        default:
+                break;
+        }
 
         /*
          * If there is a fan on this device and it has failed log the
@@ -6944,8 +7315,11 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
                 goto err_eeprom;
         }
 
-        /* power down the optics */
-        if (hw->phy.multispeed_fiber)
+        /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
+        if (hw->mac.ops.disable_tx_laser &&
+            ((hw->phy.multispeed_fiber) ||
+             ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
+              (hw->mac.type == ixgbe_mac_82599EB))))
                 hw->mac.ops.disable_tx_laser(hw);
 
         init_timer(&adapter->watchdog_timer);
@@ -6960,6 +7334,18 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
                 goto err_sw_init;
 
         switch (pdev->device) {
+        case IXGBE_DEV_ID_82599_SFP:
+                /* Only this subdevice supports WOL */
+                if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
+                        adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
+                                        IXGBE_WUFC_MC | IXGBE_WUFC_BC);
+                break;
+        case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
+                /* All except this subdevice support WOL */
+                if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
+                        adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
+                                        IXGBE_WUFC_MC | IXGBE_WUFC_BC);
+                break;
         case IXGBE_DEV_ID_82599_KX4:
                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
@@ -6983,16 +7369,17 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
                     "Unknown"),
                    netdev->dev_addr);
-        ixgbe_read_pba_num_generic(hw, &part_num);
+
+        err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
+        if (err)
+                strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
-                e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
-                           "PBA No: %06x-%03x\n",
+                e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
-                           (part_num >> 8), (part_num & 0xff));
+                           part_str);
         else
-                e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
-                           hw->mac.type, hw->phy.type,
-                           (part_num >> 8), (part_num & 0xff));
+                e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
+                           hw->mac.type, hw->phy.type, part_str);
 
         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
                 e_dev_warn("PCI-Express bandwidth available for this card is "
@@ -7085,17 +7472,19 @@ err_dma:
  **/
 static void __devexit ixgbe_remove(struct pci_dev *pdev)
 {
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
 
         set_bit(__IXGBE_DOWN, &adapter->state);
-        /* clear the module not found bit to make sure the worker won't
-         * reschedule
+
+        /*
+         * The timers may be rescheduled, so explicitly disable them
+         * from being rescheduled.
          */
         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
         del_timer_sync(&adapter->watchdog_timer);
-
         del_timer_sync(&adapter->sfp_timer);
+
         cancel_work_sync(&adapter->watchdog_task);
         cancel_work_sync(&adapter->sfp_task);
         cancel_work_sync(&adapter->multispeed_fiber_task);
@@ -7103,7 +7492,8 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev)
         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
                 cancel_work_sync(&adapter->fdir_reinit_task);
-        flush_scheduled_work();
+        if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
+                cancel_work_sync(&adapter->check_overtemp_task);
 
 #ifdef CONFIG_IXGBE_DCA
         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
@@ -7156,8 +7546,8 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev)
 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
                                                 pci_channel_state_t state)
 {
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
 
         netif_device_detach(netdev);
 
@@ -7180,8 +7570,7 @@ static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
  */
 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
 {
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
         pci_ers_result_t result;
         int err;
 
@@ -7219,8 +7608,8 @@ static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
  */
 static void ixgbe_io_resume(struct pci_dev *pdev)
 {
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
+        struct net_device *netdev = adapter->netdev;
 
         if (netif_running(netdev)) {
                 if (ixgbe_up(adapter)) {
@@ -7285,6 +7674,7 @@ static void __exit ixgbe_exit_module(void)
         dca_unregister_notify(&dca_notifier);
 #endif
         pci_unregister_driver(&ixgbe_driver);
+        rcu_barrier(); /* Wait for completion of call_rcu()'s */
 }
 
 #ifdef CONFIG_IXGBE_DCA
diff --git a/drivers/net/ixgbe/ixgbe_mbx.c b/drivers/net/ixgbe/ixgbe_mbx.c
index 471f0f2cdb98..ea82c5a1cd3e 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.c
+++ b/drivers/net/ixgbe/ixgbe_mbx.c
@@ -319,8 +319,16 @@ static s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)
         u32 vflre = 0;
         s32 ret_val = IXGBE_ERR_MBX;
 
-        if (hw->mac.type == ixgbe_mac_82599EB)
+        switch (hw->mac.type) {
+        case ixgbe_mac_82599EB:
                 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
+                break;
+        case ixgbe_mac_X540:
+                vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
+                break;
+        default:
+                break;
+        }
 
         if (vflre & (1 << vf_shift)) {
                 ret_val = 0;
@@ -439,22 +447,26 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)
 {
         struct ixgbe_mbx_info *mbx = &hw->mbx;
 
-        if (hw->mac.type != ixgbe_mac_82599EB)
-                return;
-
-        mbx->timeout = 0;
-        mbx->usec_delay = 0;
-
-        mbx->size = IXGBE_VFMAILBOX_SIZE;
-
-        mbx->stats.msgs_tx = 0;
-        mbx->stats.msgs_rx = 0;
-        mbx->stats.reqs = 0;
-        mbx->stats.acks = 0;
-        mbx->stats.rsts = 0;
+        switch (hw->mac.type) {
+        case ixgbe_mac_82599EB:
+        case ixgbe_mac_X540:
+                mbx->timeout = 0;
+                mbx->usec_delay = 0;
+
+                mbx->size = IXGBE_VFMAILBOX_SIZE;
+
+                mbx->stats.msgs_tx = 0;
+                mbx->stats.msgs_rx = 0;
+                mbx->stats.reqs = 0;
+                mbx->stats.acks = 0;
+                mbx->stats.rsts = 0;
+                break;
+        default:
+                break;
+        }
 }
 
-struct ixgbe_mbx_operations mbx_ops_82599 = {
+struct ixgbe_mbx_operations mbx_ops_generic = {
         .read                   = ixgbe_read_mbx_pf,
         .write                  = ixgbe_write_mbx_pf,
         .read_posted            = ixgbe_read_posted_mbx,
diff --git a/drivers/net/ixgbe/ixgbe_mbx.h b/drivers/net/ixgbe/ixgbe_mbx.h
index 7e0d08ff5b53..3df9b1590218 100644
--- a/drivers/net/ixgbe/ixgbe_mbx.h
+++ b/drivers/net/ixgbe/ixgbe_mbx.h
@@ -88,6 +88,6 @@ s32 ixgbe_check_for_ack(struct ixgbe_hw *, u16);
 s32 ixgbe_check_for_rst(struct ixgbe_hw *, u16);
 void ixgbe_init_mbx_params_pf(struct ixgbe_hw *);
 
-extern struct ixgbe_mbx_operations mbx_ops_82599;
+extern struct ixgbe_mbx_operations mbx_ops_generic;
 
 #endif /* _IXGBE_MBX_H_ */
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 6c0d42e33f21..8f7123e8fc0a 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -115,6 +115,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
         case TN1010_PHY_ID:
                 phy_type = ixgbe_phy_tn;
                 break;
+        case X540_PHY_ID:
+                phy_type = ixgbe_phy_aq;
+                break;
         case QT2022_PHY_ID:
                 phy_type = ixgbe_phy_qt;
                 break;
@@ -425,6 +428,39 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 }
 
 /**
+ * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
+ * @hw: pointer to hardware structure
+ * @speed: pointer to link speed
+ * @autoneg: boolean auto-negotiation value
+ *
+ * Determines the link capabilities by reading the AUTOC register.
+ */
+s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
+                                               ixgbe_link_speed *speed,
+                                               bool *autoneg)
+{
+        s32 status = IXGBE_ERR_LINK_SETUP;
+        u16 speed_ability;
+
+        *speed = 0;
+        *autoneg = true;
+
+        status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
+                                      &speed_ability);
+
+        if (status == 0) {
+                if (speed_ability & MDIO_SPEED_10G)
+                        *speed |= IXGBE_LINK_SPEED_10GB_FULL;
+                if (speed_ability & MDIO_PMA_SPEED_1000)
+                        *speed |= IXGBE_LINK_SPEED_1GB_FULL;
+                if (speed_ability & MDIO_PMA_SPEED_100)
+                        *speed |= IXGBE_LINK_SPEED_100_FULL;
+        }
+
+        return status;
+}
+
+/**
  *  ixgbe_reset_phy_nl - Performs a PHY reset
  *  @hw: pointer to hardware structure
  **/
@@ -1378,6 +1414,22 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 }
 
 /**
+ *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
+ *  @hw: pointer to hardware structure
+ *  @firmware_version: pointer to the PHY Firmware Version
+**/
+s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
+                                           u16 *firmware_version)
+{
+        s32 status = 0;
+
+        status = hw->phy.ops.read_reg(hw, AQ_FW_REV, MDIO_MMD_VEND1,
+                                      firmware_version);
+
+        return status;
+}
+
+/**
  *  ixgbe_tn_check_overtemp - Checks if an overtemp occured.
  *  @hw: pointer to hardware structure
  *
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h
index fb3898f12fc5..e2c6b7eac641 100644
--- a/drivers/net/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ixgbe/ixgbe_phy.h
@@ -96,6 +96,9 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                        ixgbe_link_speed speed,
                                        bool autoneg,
                                        bool autoneg_wait_to_complete);
+s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
+                                               ixgbe_link_speed *speed,
+                                               bool *autoneg);
 
 /* PHY specific */
 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
@@ -103,6 +106,8 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
                              bool *link_up);
 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
                                        u16 *firmware_version);
+s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
+                                           u16 *firmware_version);
 
 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
diff --git a/drivers/net/ixgbe/ixgbe_sriov.c b/drivers/net/ixgbe/ixgbe_sriov.c
index 5428153af8f3..47b15738b009 100644
--- a/drivers/net/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ixgbe/ixgbe_sriov.c
@@ -68,7 +68,7 @@ static int ixgbe_set_vf_multicasts(struct ixgbe_adapter *adapter,
          * addresses
          */
         for (i = 0; i < entries; i++) {
-                vfinfo->vf_mc_hashes[i] = hash_list[i];;
+                vfinfo->vf_mc_hashes[i] = hash_list[i];
         }
 
         for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
@@ -178,8 +178,7 @@ static int ixgbe_set_vf_mac(struct ixgbe_adapter *adapter,
 int ixgbe_vf_configuration(struct pci_dev *pdev, unsigned int event_mask)
 {
         unsigned char vf_mac_addr[6];
-        struct net_device *netdev = pci_get_drvdata(pdev);
-        struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
         unsigned int vfn = (event_mask & 0x3f);
 
         bool enable = ((event_mask & 0x10000000U) != 0);
@@ -216,6 +215,11 @@ static inline void ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
         reg |= (reg | (1 << vf_shift));
         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
 
+        /* Enable counting of spoofed packets in the SSVPC register */
+        reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
+        reg |= (1 << vf_shift);
+        IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
+
         ixgbe_vf_reset_event(adapter, vf);
 }
 
@@ -228,6 +232,7 @@ static int ixgbe_rcv_msg_from_vf(struct ixgbe_adapter *adapter, u32 vf)
         int entries;
         u16 *hash_list;
         int add, vid;
+        u8 *new_mac;
 
         retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
 
@@ -245,15 +250,22 @@ static int ixgbe_rcv_msg_from_vf(struct ixgbe_adapter *adapter, u32 vf)
 
         if (msgbuf[0] == IXGBE_VF_RESET) {
                 unsigned char *vf_mac = adapter->vfinfo[vf].vf_mac_addresses;
-                u8 *addr = (u8 *)(&msgbuf[1]);
+                new_mac = (u8 *)(&msgbuf[1]);
                 e_info(probe, "VF Reset msg received from vf %d\n", vf);
                 adapter->vfinfo[vf].clear_to_send = false;
                 ixgbe_vf_reset_msg(adapter, vf);
                 adapter->vfinfo[vf].clear_to_send = true;
 
+                if (is_valid_ether_addr(new_mac) &&
+                    !adapter->vfinfo[vf].pf_set_mac)
+                        ixgbe_set_vf_mac(adapter, vf, vf_mac);
+                else
+                        ixgbe_set_vf_mac(adapter,
+                                 vf, adapter->vfinfo[vf].vf_mac_addresses);
+
                 /* reply to reset with ack and vf mac address */
                 msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
-                memcpy(addr, vf_mac, IXGBE_ETH_LENGTH_OF_ADDRESS);
+                memcpy(new_mac, vf_mac, IXGBE_ETH_LENGTH_OF_ADDRESS);
                 /*
                  * Piggyback the multicast filter type so VF can compute the
                  * correct vectors
@@ -272,14 +284,16 @@ static int ixgbe_rcv_msg_from_vf(struct ixgbe_adapter *adapter, u32 vf)
 
         switch ((msgbuf[0] & 0xFFFF)) {
         case IXGBE_VF_SET_MAC_ADDR:
-                {
-                        u8 *new_mac = ((u8 *)(&msgbuf[1]));
-                        if (is_valid_ether_addr(new_mac) &&
-                            !adapter->vfinfo[vf].pf_set_mac)
-                                ixgbe_set_vf_mac(adapter, vf, new_mac);
-                        else
-                                ixgbe_set_vf_mac(adapter,
-                                  vf, adapter->vfinfo[vf].vf_mac_addresses);
+                new_mac = ((u8 *)(&msgbuf[1]));
+                if (is_valid_ether_addr(new_mac) &&
+                    !adapter->vfinfo[vf].pf_set_mac) {
+                        ixgbe_set_vf_mac(adapter, vf, new_mac);
+                } else if (memcmp(adapter->vfinfo[vf].vf_mac_addresses,
+                                  new_mac, ETH_ALEN)) {
+                        e_warn(drv, "VF %d attempted to override "
+                               "administratively set MAC address\nReload "
+                               "the VF driver to resume operations\n", vf);
+                        retval = -1;
                 }
                 break;
         case IXGBE_VF_SET_MULTICAST:
@@ -296,7 +310,15 @@ static int ixgbe_rcv_msg_from_vf(struct ixgbe_adapter *adapter, u32 vf)
                 add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
                       >> IXGBE_VT_MSGINFO_SHIFT;
                 vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
-                retval = ixgbe_set_vf_vlan(adapter, add, vid, vf);
+                if (adapter->vfinfo[vf].pf_vlan) {
+                        e_warn(drv, "VF %d attempted to override "
+                               "administratively set VLAN configuration\n"
+                               "Reload the VF driver to resume operations\n",
+                               vf);
+                        retval = -1;
+                } else {
+                        retval = ixgbe_set_vf_vlan(adapter, add, vid, vf);
+                }
                 break;
         default:
                 e_err(drv, "Unhandled Msg %8.8x\n", msgbuf[0]);
@@ -395,6 +417,7 @@ int ixgbe_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos)
 {
         int err = 0;
         struct ixgbe_adapter *adapter = netdev_priv(netdev);
+        struct ixgbe_hw *hw = &adapter->hw;
 
         if ((vf >= adapter->num_vfs) || (vlan > 4095) || (qos > 7))
                 return -EINVAL;
@@ -403,7 +426,8 @@ int ixgbe_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos)
                 if (err)
                         goto out;
                 ixgbe_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
-                ixgbe_set_vmolr(&adapter->hw, vf, false);
+                ixgbe_set_vmolr(hw, vf, false);
+                hw->mac.ops.set_vlan_anti_spoofing(hw, true, vf);
                 adapter->vfinfo[vf].pf_vlan = vlan;
                 adapter->vfinfo[vf].pf_qos = qos;
                 dev_info(&adapter->pdev->dev,
@@ -420,7 +444,8 @@ int ixgbe_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos)
                 err = ixgbe_set_vf_vlan(adapter, false,
                                         adapter->vfinfo[vf].pf_vlan, vf);
                 ixgbe_set_vmvir(adapter, vlan, vf);
-                ixgbe_set_vmolr(&adapter->hw, vf, true);
+                ixgbe_set_vmolr(hw, vf, true);
+                hw->mac.ops.set_vlan_anti_spoofing(hw, false, vf);
                 adapter->vfinfo[vf].pf_vlan = 0;
                 adapter->vfinfo[vf].pf_qos = 0;
        }
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index d3cc6ce7c973..fd3358f54139 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -54,9 +54,14 @@
 #define IXGBE_DEV_ID_82599_T3_LOM        0x151C
 #define IXGBE_DEV_ID_82599_CX4           0x10F9
 #define IXGBE_DEV_ID_82599_SFP           0x10FB
+#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152a
+#define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
+#define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
 #define IXGBE_DEV_ID_82599_SFP_EM        0x1507
 #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
+#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
+#define IXGBE_DEV_ID_X540T               0x1528
 
 /* General Registers */
 #define IXGBE_CTRL      0x00000
@@ -225,6 +230,7 @@
 #define IXGBE_VT_CTL    0x051B0
 #define IXGBE_VFRE(_i)  (0x051E0 + ((_i) * 4))
 #define IXGBE_VFTE(_i)  (0x08110 + ((_i) * 4))
+#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
 #define IXGBE_QDE       0x2F04
 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
 #define IXGBE_UTA(_i)   (0x0F400 + ((_i) * 4))
@@ -279,7 +285,8 @@
 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
 #define IXGBE_DTXCTL    0x07E00
 
-#define IXGBE_DMATXCTL  0x04A80
+#define IXGBE_DMATXCTL      0x04A80
+#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 #define IXGBE_PFDTXGSWC     0x08220
 #define IXGBE_DTXMXSZRQ     0x08100
 #define IXGBE_DTXTCPFLGL    0x04A88
@@ -293,6 +300,13 @@
 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 
 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
+
+/* Anti-spoofing defines */
+#define IXGBE_SPOOF_MACAS_MASK          0xFF
+#define IXGBE_SPOOF_VLANAS_MASK         0xFF00
+#define IXGBE_SPOOF_VLANAS_SHIFT        8
+#define IXGBE_PFVFSPOOF_REG_COUNT       8
+
 #define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
 /* Tx DCA Control register : 128 of these (0-127) */
 #define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
@@ -994,8 +1008,10 @@
 /* PHY IDs*/
 #define TN1010_PHY_ID    0x00A19410
 #define TNX_FW_REV       0xB
+#define X540_PHY_ID      0x01540200
 #define QT2022_PHY_ID    0x0043A400
 #define ATH_PHY_ID       0x03429050
+#define AQ_FW_REV        0x20
 
 /* PHY Types */
 #define IXGBE_M88E1145_E_PHY_ID  0x01410CD0
@@ -1463,6 +1479,8 @@
 #define IXGBE_ANLP1_PAUSE               0x0C00
 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
+#define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
+
 
 /* SW Semaphore Register bitmasks */
 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
@@ -1491,6 +1509,7 @@
 #define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
 #define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
 #define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
+#define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
 #define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
 /* EEPROM Addressing bits based on type (0-small, 1-large) */
 #define IXGBE_EEC_ADDR_SIZE 0x00000400
@@ -1500,12 +1519,18 @@
 #define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
 #define IXGBE_EEPROM_OPCODE_BITS      8
 
+/* Part Number String Length */
+#define IXGBE_PBANUM_LENGTH 11
+
 /* Checksum and EEPROM pointers */
+#define IXGBE_PBANUM_PTR_GUARD  0xFAFA
 #define IXGBE_EEPROM_CHECKSUM   0x3F
 #define IXGBE_EEPROM_SUM        0xBABA
 #define IXGBE_PCIE_ANALOG_PTR   0x03
 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
+#define IXGBE_PHY_PTR           0x04
 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
+#define IXGBE_OPTION_ROM_PTR    0x05
 #define IXGBE_PCIE_GENERAL_PTR  0x06
 #define IXGBE_PCIE_CONFIG0_PTR  0x07
 #define IXGBE_PCIE_CONFIG1_PTR  0x08
@@ -1922,10 +1947,9 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRM_VLANID                      0x00000001
 #define IXGBE_FDIRM_VLANP                       0x00000002
 #define IXGBE_FDIRM_POOL                        0x00000004
-#define IXGBE_FDIRM_L3P                         0x00000008
-#define IXGBE_FDIRM_L4P                         0x00000010
-#define IXGBE_FDIRM_FLEX                        0x00000020
-#define IXGBE_FDIRM_DIPv6                       0x00000040
+#define IXGBE_FDIRM_L4P                         0x00000008
+#define IXGBE_FDIRM_FLEX                        0x00000010
+#define IXGBE_FDIRM_DIPv6                       0x00000020
 
 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
 #define IXGBE_FDIRFREE_FREE_SHIFT               0
@@ -1965,6 +1989,7 @@ enum ixgbe_fdir_pballoc_type {
 #define IXGBE_FDIRCMD_LAST                      0x00000800
 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
+#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
 #define IXGBE_FDIR_INIT_DONE_POLL               10
@@ -2113,57 +2138,95 @@ typedef u32 ixgbe_physical_layer;
 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
 
+/* Flow Control Macros */
+#define PAUSE_RTT       8
+#define PAUSE_MTU(MTU)  ((MTU + 1024 - 1) / 1024)
+
+#define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
+                                PAUSE_MTU(MTU))
+#define FC_LOW_WATER(MTU)  (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
+
 /* Software ATR hash keys */
-#define IXGBE_ATR_BUCKET_HASH_KEY    0xE214AD3D
-#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
-
-/* Software ATR input stream offsets and masks */
-#define IXGBE_ATR_VLAN_OFFSET       0
-#define IXGBE_ATR_SRC_IPV6_OFFSET   2
-#define IXGBE_ATR_SRC_IPV4_OFFSET  14
-#define IXGBE_ATR_DST_IPV6_OFFSET  18
-#define IXGBE_ATR_DST_IPV4_OFFSET  30
-#define IXGBE_ATR_SRC_PORT_OFFSET  34
-#define IXGBE_ATR_DST_PORT_OFFSET  36
-#define IXGBE_ATR_FLEX_BYTE_OFFSET 38
-#define IXGBE_ATR_VM_POOL_OFFSET   40
-#define IXGBE_ATR_L4TYPE_OFFSET    41
+#define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
+#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
 
+/* Software ATR input stream values and masks */
+#define IXGBE_ATR_HASH_MASK     0x7fff
 #define IXGBE_ATR_L4TYPE_MASK      0x3
-#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
 #define IXGBE_ATR_L4TYPE_UDP       0x1
 #define IXGBE_ATR_L4TYPE_TCP       0x2
 #define IXGBE_ATR_L4TYPE_SCTP      0x3
-#define IXGBE_ATR_HASH_MASK     0x7fff
+#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
+enum ixgbe_atr_flow_type {
+        IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
+        IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
+        IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
+        IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
+        IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
+        IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
+        IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
+        IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
+};
 
 /* Flow Director ATR input struct. */
-struct ixgbe_atr_input {
-        /* Byte layout in order, all values with MSB first:
+union ixgbe_atr_input {
+        /*
+         * Byte layout in order, all values with MSB first:
          *
+         * vm_pool    - 1 byte
+         * flow_type  - 1 byte
          * vlan_id    - 2 bytes
          * src_ip     - 16 bytes
          * dst_ip     - 16 bytes
          * src_port   - 2 bytes
          * dst_port   - 2 bytes
          * flex_bytes - 2 bytes
-         * vm_pool    - 1 byte
-         * l4type     - 1 byte
+         * rsvd0      - 2 bytes - space reserved must be 0.
          */
-        u8 byte_stream[42];
+        struct {
+                u8     vm_pool;
+                u8     flow_type;
+                __be16 vlan_id;
+                __be32 dst_ip[4];
+                __be32 src_ip[4];
+                __be16 src_port;
+                __be16 dst_port;
+                __be16 flex_bytes;
+                __be16 rsvd0;
+        } formatted;
+        __be32 dword_stream[11];
+};
+
+/* Flow Director compressed ATR hash input struct */
+union ixgbe_atr_hash_dword {
+        struct {
+                u8 vm_pool;
+                u8 flow_type;
+                __be16 vlan_id;
+        } formatted;
+        __be32 ip;
+        struct {
+                __be16 src;
+                __be16 dst;
+        } port;
+        __be16 flex_bytes;
+        __be32 dword;
 };
 
 struct ixgbe_atr_input_masks {
-        u32 src_ip_mask;
-        u32 dst_ip_mask;
-        u16 src_port_mask;
-        u16 dst_port_mask;
-        u16 vlan_id_mask;
-        u16 data_mask;
+        __be16 rsvd0;
+        __be16 vlan_id_mask;
+        __be32 dst_ip_mask[4];
+        __be32 src_ip_mask[4];
+        __be16 src_port_mask;
+        __be16 dst_port_mask;
+        __be16 flex_mask;
 };
 
 enum ixgbe_eeprom_type {
         ixgbe_eeprom_uninitialized = 0,
         ixgbe_eeprom_spi,
+        ixgbe_flash,
         ixgbe_eeprom_none /* No NVM support */
 };
 
@@ -2171,12 +2234,14 @@ enum ixgbe_mac_type {
         ixgbe_mac_unknown = 0,
         ixgbe_mac_82598EB,
         ixgbe_mac_82599EB,
+        ixgbe_mac_X540,
         ixgbe_num_macs
 };
 
 enum ixgbe_phy_type {
         ixgbe_phy_unknown = 0,
         ixgbe_phy_tn,
+        ixgbe_phy_aq,
         ixgbe_phy_cu_unknown,
         ixgbe_phy_qt,
         ixgbe_phy_xaui,
@@ -2405,6 +2470,7 @@ struct ixgbe_eeprom_operations {
         s32 (*write)(struct ixgbe_hw *, u16, u16);
         s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
         s32 (*update_checksum)(struct ixgbe_hw *);
+        u16 (*calc_checksum)(struct ixgbe_hw *);
 };
 
 struct ixgbe_mac_operations {
@@ -2454,6 +2520,8 @@ struct ixgbe_mac_operations {
         s32 (*clear_vfta)(struct ixgbe_hw *);
         s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
         s32 (*init_uta_tables)(struct ixgbe_hw *);
+        void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
+        void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
 
         /* Flow Control */
         s32 (*fc_enable)(struct ixgbe_hw *, s32);
@@ -2574,6 +2642,7 @@ struct ixgbe_hw {
         u16                             subsystem_vendor_id;
         u8                              revision_id;
         bool                            adapter_stopped;
+        bool                            force_full_reset;
 };
 
 struct ixgbe_info {
@@ -2614,6 +2683,9 @@ struct ixgbe_info {
 #define IXGBE_ERR_NO_SPACE                      -25
 #define IXGBE_ERR_OVERTEMP                      -26
 #define IXGBE_ERR_RAR_INDEX                     -27
+#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
+#define IXGBE_ERR_PBA_SECTION                   -31
+#define IXGBE_ERR_INVALID_ARGUMENT              -32
 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
 
 #endif /* _IXGBE_TYPE_H_ */
diff --git a/drivers/net/ixgbe/ixgbe_x540.c b/drivers/net/ixgbe/ixgbe_x540.c
new file mode 100644
index 000000000000..3a8923993ce3
--- /dev/null
+++ b/drivers/net/ixgbe/ixgbe_x540.c
@@ -0,0 +1,724 @@
+/*******************************************************************************
+
+  Intel 10 Gigabit PCI Express Linux driver
+  Copyright(c) 1999 - 2010 Intel Corporation.
+
+  This program is free software; you can redistribute it and/or modify it
+  under the terms and conditions of the GNU General Public License,
+  version 2, as published by the Free Software Foundation.
+
+  This program is distributed in the hope it will be useful, but WITHOUT
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  more details.
+
+  You should have received a copy of the GNU General Public License along with
+  this program; if not, write to the Free Software Foundation, Inc.,
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+
+  The full GNU General Public License is included in this distribution in
+  the file called "COPYING".
+
+  Contact Information:
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+
+*******************************************************************************/
+
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include "ixgbe.h"
+#include "ixgbe_phy.h"
+//#include "ixgbe_mbx.h"
+
+#define IXGBE_X540_MAX_TX_QUEUES 128
+#define IXGBE_X540_MAX_RX_QUEUES 128
+#define IXGBE_X540_RAR_ENTRIES   128
+#define IXGBE_X540_MC_TBL_SIZE   128
+#define IXGBE_X540_VFT_TBL_SIZE  128
+
+static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
+static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
+static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
+static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
+static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
+static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
+
+static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
+{
+        return ixgbe_media_type_copper;
+}
+
+static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
+{
+        struct ixgbe_mac_info *mac = &hw->mac;
+
+        /* Call PHY identify routine to get the phy type */
+        ixgbe_identify_phy_generic(hw);
+
+        mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
+        mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
+        mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
+        mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
+        mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
+        mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
+
+        return 0;
+}
+
+/**
+ *  ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
+ *  @hw: pointer to hardware structure
+ *  @speed: new link speed
+ *  @autoneg: true if autonegotiation enabled
+ *  @autoneg_wait_to_complete: true when waiting for completion is needed
+ **/
+static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
+                                     ixgbe_link_speed speed, bool autoneg,
+                                     bool autoneg_wait_to_complete)
+{
+        return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
+                                            autoneg_wait_to_complete);
+}
+
+/**
+ *  ixgbe_reset_hw_X540 - Perform hardware reset
+ *  @hw: pointer to hardware structure
+ *
+ *  Resets the hardware by resetting the transmit and receive units, masks
+ *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
+ *  reset.
+ **/
+static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
+{
+        ixgbe_link_speed link_speed;
+        s32 status = 0;
+        u32 ctrl;
+        u32 ctrl_ext;
+        u32 reset_bit;
+        u32 i;
+        u32 autoc;
+        u32 autoc2;
+        bool link_up = false;
+
+        /* Call adapter stop to disable tx/rx and clear interrupts */
+        hw->mac.ops.stop_adapter(hw);
+
+        /*
+         * Prevent the PCI-E bus from from hanging by disabling PCI-E master
+         * access and verify no pending requests before reset
+         */
+        status = ixgbe_disable_pcie_master(hw);
+        if (status != 0) {
+                status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
+                hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
+        }
+
+        /*
+         * Issue global reset to the MAC.  Needs to be SW reset if link is up.
+         * If link reset is used when link is up, it might reset the PHY when
+         * mng is using it.  If link is down or the flag to force full link
+         * reset is set, then perform link reset.
+         */
+        if (hw->force_full_reset) {
+                reset_bit = IXGBE_CTRL_LNK_RST;
+        } else {
+                hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
+                if (!link_up)
+                        reset_bit = IXGBE_CTRL_LNK_RST;
+                else
+                        reset_bit = IXGBE_CTRL_RST;
+        }
+
+        ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
+        IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
+        IXGBE_WRITE_FLUSH(hw);
+
+        /* Poll for reset bit to self-clear indicating reset is complete */
+        for (i = 0; i < 10; i++) {
+                udelay(1);
+                ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
+                if (!(ctrl & IXGBE_CTRL_RST))
+                        break;
+        }
+        if (ctrl & IXGBE_CTRL_RST) {
+                status = IXGBE_ERR_RESET_FAILED;
+                hw_dbg(hw, "Reset polling failed to complete.\n");
+        }
+
+        /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
+        ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
+        ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
+        IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
+
+        msleep(50);
+
+        /* Set the Rx packet buffer size. */
+        IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
+
+        /* Store the permanent mac address */
+        hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+
+        /*
+         * Store the original AUTOC/AUTOC2 values if they have not been
+         * stored off yet.  Otherwise restore the stored original
+         * values since the reset operation sets back to defaults.
+         */
+        autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
+        autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
+        if (hw->mac.orig_link_settings_stored == false) {
+                hw->mac.orig_autoc = autoc;
+                hw->mac.orig_autoc2 = autoc2;
+                hw->mac.orig_link_settings_stored = true;
+        } else {
+                if (autoc != hw->mac.orig_autoc)
+                        IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
+                                        IXGBE_AUTOC_AN_RESTART));
+
+                if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
+                    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
+                        autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
+                        autoc2 |= (hw->mac.orig_autoc2 &
+                                   IXGBE_AUTOC2_UPPER_MASK);
+                        IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
+                }
+        }
+
+        /*
+         * Store MAC address from RAR0, clear receive address registers, and
+         * clear the multicast table.  Also reset num_rar_entries to 128,
+         * since we modify this value when programming the SAN MAC address.
+         */
+        hw->mac.num_rar_entries = 128;
+        hw->mac.ops.init_rx_addrs(hw);
+
+        /* Store the permanent mac address */
+        hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
+
+        /* Store the permanent SAN mac address */
+        hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
+
+        /* Add the SAN MAC address to the RAR only if it's a valid address */
+        if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
+                hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
+                                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
+
+                /* Reserve the last RAR for the SAN MAC address */
+                hw->mac.num_rar_entries--;
+        }
+
+        /* Store the alternative WWNN/WWPN prefix */
+        hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
+                                   &hw->mac.wwpn_prefix);
+
+        return status;
+}
+
+/**
+ *  ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
+ *  @hw: pointer to hardware structure
+ *
+ *  Determines physical layer capabilities of the current configuration.
+ **/
+static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
+{
+        u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
+        u16 ext_ability = 0;
+
+        hw->phy.ops.identify(hw);
+
+        hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
+                             &ext_ability);
+        if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
+                physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
+        if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
+                physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
+        if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
+                physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
+
+        return physical_layer;
+}
+
+/**
+ * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
+ * @hw: pointer to hardware structure
+ **/
+static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
+{
+        struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
+        u32 eec;
+        u16 eeprom_size;
+
+        if (eeprom->type == ixgbe_eeprom_uninitialized) {
+                eeprom->semaphore_delay = 10;
+                eeprom->type = ixgbe_flash;
+
+                eec = IXGBE_READ_REG(hw, IXGBE_EEC);
+                eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
+                                    IXGBE_EEC_SIZE_SHIFT);
+                eeprom->word_size = 1 << (eeprom_size +
+                                          IXGBE_EEPROM_WORD_SIZE_SHIFT);
+
+                hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
+                        eeprom->type, eeprom->word_size);
+        }
+
+        return 0;
+}
+
+/**
+ * ixgbe_read_eerd_X540 - Read EEPROM word using EERD
+ * @hw: pointer to hardware structure
+ * @offset: offset of word in the EEPROM to read
+ * @data: word read from the EERPOM
+ **/
+static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
+{
+        s32 status;
+
+        if (ixgbe_acquire_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM) == 0)
+                status = ixgbe_read_eerd_generic(hw, offset, data);
+        else
+                status = IXGBE_ERR_SWFW_SYNC;
+
+        ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM);
+        return status;
+}
+
+/**
+ * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
+ * @hw: pointer to hardware structure
+ * @offset: offset of  word in the EEPROM to write
+ * @data: word write to the EEPROM
+ *
+ * Write a 16 bit word to the EEPROM using the EEWR register.
+ **/
+static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
+{
+        u32 eewr;
+        s32 status;
+
+        hw->eeprom.ops.init_params(hw);
+
+        if (offset >= hw->eeprom.word_size) {
+                status = IXGBE_ERR_EEPROM;
+                goto out;
+        }
+
+        eewr = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) |
+               (data << IXGBE_EEPROM_RW_REG_DATA) |
+               IXGBE_EEPROM_RW_REG_START;
+
+        if (ixgbe_acquire_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM) == 0) {
+                status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
+                if (status != 0) {
+                        hw_dbg(hw, "Eeprom write EEWR timed out\n");
+                        goto out;
+                }
+
+                IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
+
+                status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
+                if (status != 0) {
+                        hw_dbg(hw, "Eeprom write EEWR timed out\n");
+                        goto out;
+                }
+        } else {
+                status = IXGBE_ERR_SWFW_SYNC;
+        }
+
+out:
+        ixgbe_release_swfw_sync_X540(hw, IXGBE_GSSR_EEP_SM);
+        return status;
+}
+
+/**
+ * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
+ * @hw: pointer to hardware structure
+ **/
+static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
+{
+        u16 i;
+        u16 j;
+        u16 checksum = 0;
+        u16 length = 0;
+        u16 pointer = 0;
+        u16 word = 0;
+
+        /* Include 0x0-0x3F in the checksum */
+        for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
+                if (hw->eeprom.ops.read(hw, i, &word) != 0) {
+                        hw_dbg(hw, "EEPROM read failed\n");
+                        break;
+                }
+                checksum += word;
+        }
+
+        /*
+         * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
+         * FW, PHY module, and PCIe Expansion/Option ROM pointers.
+         */
+        for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
+                if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
+                        continue;
+
+                if (hw->eeprom.ops.read(hw, i, &pointer) != 0) {
+                        hw_dbg(hw, "EEPROM read failed\n");
+                        break;
+                }
+
+                /* Skip pointer section if the pointer is invalid. */
+                if (pointer == 0xFFFF || pointer == 0 ||
+                    pointer >= hw->eeprom.word_size)
+                        continue;
+
+                if (hw->eeprom.ops.read(hw, pointer, &length) != 0) {
+                        hw_dbg(hw, "EEPROM read failed\n");
+                        break;
+                }
+
+                /* Skip pointer section if length is invalid. */
+                if (length == 0xFFFF || length == 0 ||
+                    (pointer + length) >= hw->eeprom.word_size)
+                        continue;
+
+                for (j = pointer+1; j <= pointer+length; j++) {
+                        if (hw->eeprom.ops.read(hw, j, &word) != 0) {
+                                hw_dbg(hw, "EEPROM read failed\n");
+                                break;
+                        }
+                        checksum += word;
+                }
+        }
+
+        checksum = (u16)IXGBE_EEPROM_SUM - checksum;
+
+        return checksum;
+}
+
+/**
+ * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
+ * @hw: pointer to hardware structure
+ *
+ * After writing EEPROM to shadow RAM using EEWR register, software calculates
+ * checksum and updates the EEPROM and instructs the hardware to update
+ * the flash.
+ **/
+static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
+{
+        s32 status;
+
+        status = ixgbe_update_eeprom_checksum_generic(hw);
+
+        if (status)
+                status = ixgbe_update_flash_X540(hw);
+
+        return status;
+}
+
+/**
+ * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
+ * @hw: pointer to hardware structure
+ *
+ * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
+ * EEPROM from shadow RAM to the flash device.
+ **/
+static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
+{
+        u32 flup;
+        s32 status = IXGBE_ERR_EEPROM;
+
+        status = ixgbe_poll_flash_update_done_X540(hw);
+        if (status == IXGBE_ERR_EEPROM) {
+                hw_dbg(hw, "Flash update time out\n");
+                goto out;
+        }
+
+        flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
+        IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+
+        status = ixgbe_poll_flash_update_done_X540(hw);
+        if (status)
+                hw_dbg(hw, "Flash update complete\n");
+        else
+                hw_dbg(hw, "Flash update time out\n");
+
+        if (hw->revision_id == 0) {
+                flup = IXGBE_READ_REG(hw, IXGBE_EEC);
+
+                if (flup & IXGBE_EEC_SEC1VAL) {
+                        flup |= IXGBE_EEC_FLUP;
+                        IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
+                }
+
+                status = ixgbe_poll_flash_update_done_X540(hw);
+                if (status)
+                        hw_dbg(hw, "Flash update complete\n");
+                else
+                        hw_dbg(hw, "Flash update time out\n");
+
+        }
+out:
+        return status;
+}
+
+/**
+ * ixgbe_poll_flash_update_done_X540 - Poll flash update status
+ * @hw: pointer to hardware structure
+ *
+ * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
+ * flash update is done.
+ **/
+static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
+{
+        u32 i;
+        u32 reg;
+        s32 status = IXGBE_ERR_EEPROM;
+
+        for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
+                reg = IXGBE_READ_REG(hw, IXGBE_EEC);
+                if (reg & IXGBE_EEC_FLUDONE) {
+                        status = 0;
+                        break;
+                }
+                udelay(5);
+        }
+        return status;
+}
+
+/**
+ * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to acquire
+ *
+ * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
+ * the specified function (CSR, PHY0, PHY1, NVM, Flash)
+ **/
+static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
+{
+        u32 swfw_sync;
+        u32 swmask = mask;
+        u32 fwmask = mask << 5;
+        u32 hwmask = 0;
+        u32 timeout = 200;
+        u32 i;
+
+        if (swmask == IXGBE_GSSR_EEP_SM)
+                hwmask = IXGBE_GSSR_FLASH_SM;
+
+        for (i = 0; i < timeout; i++) {
+                /*
+                 * SW NVM semaphore bit is used for access to all
+                 * SW_FW_SYNC bits (not just NVM)
+                 */
+                if (ixgbe_get_swfw_sync_semaphore(hw))
+                        return IXGBE_ERR_SWFW_SYNC;
+
+                swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+                if (!(swfw_sync & (fwmask | swmask | hwmask))) {
+                        swfw_sync |= swmask;
+                        IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+                        ixgbe_release_swfw_sync_semaphore(hw);
+                        break;
+                } else {
+                        /*
+                         * Firmware currently using resource (fwmask),
+                         * hardware currently using resource (hwmask),
+                         * or other software thread currently using
+                         * resource (swmask)
+                         */
+                        ixgbe_release_swfw_sync_semaphore(hw);
+                        msleep(5);
+                }
+        }
+
+        /*
+         * If the resource is not released by the FW/HW the SW can assume that
+         * the FW/HW malfunctions. In that case the SW should sets the
+         * SW bit(s) of the requested resource(s) while ignoring the
+         * corresponding FW/HW bits in the SW_FW_SYNC register.
+         */
+        if (i >= timeout) {
+                swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+                if (swfw_sync & (fwmask | hwmask)) {
+                        if (ixgbe_get_swfw_sync_semaphore(hw))
+                                return IXGBE_ERR_SWFW_SYNC;
+
+                        swfw_sync |= swmask;
+                        IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+                        ixgbe_release_swfw_sync_semaphore(hw);
+                }
+        }
+
+        msleep(5);
+        return 0;
+}
+
+/**
+ * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
+ * @hw: pointer to hardware structure
+ * @mask: Mask to specify which semaphore to release
+ *
+ * Releases the SWFW semaphore throught the SW_FW_SYNC register
+ * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
+ **/
+static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
+{
+        u32 swfw_sync;
+        u32 swmask = mask;
+
+        ixgbe_get_swfw_sync_semaphore(hw);
+
+        swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+        swfw_sync &= ~swmask;
+        IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
+
+        ixgbe_release_swfw_sync_semaphore(hw);
+        msleep(5);
+}
+
+/**
+ * ixgbe_get_nvm_semaphore - Get hardware semaphore
+ * @hw: pointer to hardware structure
+ *
+ * Sets the hardware semaphores so SW/FW can gain control of shared resources
+ **/
+static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
+{
+        s32 status = IXGBE_ERR_EEPROM;
+        u32 timeout = 2000;
+        u32 i;
+        u32 swsm;
+
+        /* Get SMBI software semaphore between device drivers first */
+        for (i = 0; i < timeout; i++) {
+                /*
+                 * If the SMBI bit is 0 when we read it, then the bit will be
+                 * set and we have the semaphore
+                 */
+                swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+                if (!(swsm & IXGBE_SWSM_SMBI)) {
+                        status = 0;
+                        break;
+                }
+                udelay(50);
+        }
+
+        /* Now get the semaphore between SW/FW through the REGSMP bit */
+        if (status) {
+                for (i = 0; i < timeout; i++) {
+                        swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+                        if (!(swsm & IXGBE_SWFW_REGSMP))
+                                break;
+
+                        udelay(50);
+                }
+        } else {
+                hw_dbg(hw, "Software semaphore SMBI between device drivers "
+                           "not granted.\n");
+        }
+
+        return status;
+}
+
+/**
+ * ixgbe_release_nvm_semaphore - Release hardware semaphore
+ * @hw: pointer to hardware structure
+ *
+ * This function clears hardware semaphore bits.
+ **/
+static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
+{
+         u32 swsm;
+
+        /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
+
+        swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
+        swsm &= ~IXGBE_SWSM_SMBI;
+        IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
+
+        swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
+        swsm &= ~IXGBE_SWFW_REGSMP;
+        IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
+
+        IXGBE_WRITE_FLUSH(hw);
+}
+
+static struct ixgbe_mac_operations mac_ops_X540 = {
+        .init_hw                = &ixgbe_init_hw_generic,
+        .reset_hw               = &ixgbe_reset_hw_X540,
+        .start_hw               = &ixgbe_start_hw_generic,
+        .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
+        .get_media_type         = &ixgbe_get_media_type_X540,
+        .get_supported_physical_layer =
+                                  &ixgbe_get_supported_physical_layer_X540,
+        .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
+        .get_mac_addr           = &ixgbe_get_mac_addr_generic,
+        .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
+        .get_device_caps        = NULL,
+        .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
+        .stop_adapter           = &ixgbe_stop_adapter_generic,
+        .get_bus_info           = &ixgbe_get_bus_info_generic,
+        .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
+        .read_analog_reg8       = NULL,
+        .write_analog_reg8      = NULL,
+        .setup_link             = &ixgbe_setup_mac_link_X540,
+        .check_link             = &ixgbe_check_mac_link_generic,
+        .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
+        .led_on                 = &ixgbe_led_on_generic,
+        .led_off                = &ixgbe_led_off_generic,
+        .blink_led_start        = &ixgbe_blink_led_start_generic,
+        .blink_led_stop         = &ixgbe_blink_led_stop_generic,
+        .set_rar                = &ixgbe_set_rar_generic,
+        .clear_rar              = &ixgbe_clear_rar_generic,
+        .set_vmdq               = &ixgbe_set_vmdq_generic,
+        .clear_vmdq             = &ixgbe_clear_vmdq_generic,
+        .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
+        .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
+        .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
+        .enable_mc              = &ixgbe_enable_mc_generic,
+        .disable_mc             = &ixgbe_disable_mc_generic,
+        .clear_vfta             = &ixgbe_clear_vfta_generic,
+        .set_vfta               = &ixgbe_set_vfta_generic,
+        .fc_enable              = &ixgbe_fc_enable_generic,
+        .init_uta_tables        = &ixgbe_init_uta_tables_generic,
+        .setup_sfp              = NULL,
+        .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
+        .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
+};
+
+static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
+        .init_params            = &ixgbe_init_eeprom_params_X540,
+        .read                   = &ixgbe_read_eerd_X540,
+        .write                  = &ixgbe_write_eewr_X540,
+        .calc_checksum          = &ixgbe_calc_eeprom_checksum_X540,
+        .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
+        .update_checksum        = &ixgbe_update_eeprom_checksum_X540,
+};
+
+static struct ixgbe_phy_operations phy_ops_X540 = {
+        .identify               = &ixgbe_identify_phy_generic,
+        .identify_sfp           = &ixgbe_identify_sfp_module_generic,
+        .init                   = NULL,
+        .reset                  = &ixgbe_reset_phy_generic,
+        .read_reg               = &ixgbe_read_phy_reg_generic,
+        .write_reg              = &ixgbe_write_phy_reg_generic,
+        .setup_link             = &ixgbe_setup_phy_link_generic,
+        .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
+        .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
+        .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
+        .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
+        .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
+        .check_overtemp         = &ixgbe_tn_check_overtemp,
+};
+
+struct ixgbe_info ixgbe_X540_info = {
+        .mac                    = ixgbe_mac_X540,
+        .get_invariants         = &ixgbe_get_invariants_X540,
+        .mac_ops                = &mac_ops_X540,
+        .eeprom_ops             = &eeprom_ops_X540,
+        .phy_ops                = &phy_ops_X540,
+        .mbx_ops                = &mbx_ops_generic,
+};
diff --git a/drivers/net/ixgbevf/Makefile b/drivers/net/ixgbevf/Makefile
index dd4e0d27e8cc..1f35d229e71a 100644
--- a/drivers/net/ixgbevf/Makefile
+++ b/drivers/net/ixgbevf/Makefile
@@ -1,7 +1,7 @@
 ################################################################################
 #
 # Intel 82599 Virtual Function driver
-# Copyright(c) 1999 - 2009 Intel Corporation.
+# Copyright(c) 1999 - 2010 Intel Corporation.
 #
 # This program is free software; you can redistribute it and/or modify it
 # under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbevf/defines.h b/drivers/net/ixgbevf/defines.h
index ca2c81f49a05..de643eb2ada6 100644
--- a/drivers/net/ixgbevf/defines.h
+++ b/drivers/net/ixgbevf/defines.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -30,6 +30,7 @@
 
 /* Device IDs */
 #define IXGBE_DEV_ID_82599_VF           0x10ED
+#define IXGBE_DEV_ID_X540_VF            0x1515
 
 #define IXGBE_VF_IRQ_CLEAR_MASK         7
 #define IXGBE_VF_MAX_TX_QUEUES          1
diff --git a/drivers/net/ixgbevf/ethtool.c b/drivers/net/ixgbevf/ethtool.c
index 4cc817acfb62..fa29b3c8c464 100644
--- a/drivers/net/ixgbevf/ethtool.c
+++ b/drivers/net/ixgbevf/ethtool.c
@@ -544,7 +544,7 @@ struct ixgbevf_reg_test {
 #define TABLE64_TEST_HI 6
 
 /* default VF register test */
-static struct ixgbevf_reg_test reg_test_vf[] = {
+static const struct ixgbevf_reg_test reg_test_vf[] = {
         { IXGBE_VFRDBAL(0), 2, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
         { IXGBE_VFRDBAH(0), 2, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
         { IXGBE_VFRDLEN(0), 2, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
@@ -557,19 +557,23 @@ static struct ixgbevf_reg_test reg_test_vf[] = {
         { 0, 0, 0, 0 }
 };
 
+static const u32 register_test_patterns[] = {
+        0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
+};
+
 #define REG_PATTERN_TEST(R, M, W)                                             \
 {                                                                             \
         u32 pat, val, before;                                                 \
-        const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
-        for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
+        for (pat = 0; pat < ARRAY_SIZE(register_test_patterns); pat++) {      \
                 before = readl(adapter->hw.hw_addr + R);                      \
-                writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
+                writel((register_test_patterns[pat] & W),                     \
+                       (adapter->hw.hw_addr + R));                            \
                 val = readl(adapter->hw.hw_addr + R);                         \
-                if (val != (_test[pat] & W & M)) {                            \
+                if (val != (register_test_patterns[pat] & W & M)) {           \
                         hw_dbg(&adapter->hw,                                  \
                         "pattern test reg %04X failed: got "                  \
                         "0x%08X expected 0x%08X\n",                           \
-                        R, val, (_test[pat] & W & M));                        \
+                        R, val, (register_test_patterns[pat] & W & M));       \
                         *data = R;                                            \
                         writel(before, adapter->hw.hw_addr + R);              \
                         return 1;                                             \
@@ -596,7 +600,7 @@ static struct ixgbevf_reg_test reg_test_vf[] = {
 
 static int ixgbevf_reg_test(struct ixgbevf_adapter *adapter, u64 *data)
 {
-        struct ixgbevf_reg_test *test;
+        const struct ixgbevf_reg_test *test;
         u32 i;
 
         test = reg_test_vf;
diff --git a/drivers/net/ixgbevf/ixgbevf.h b/drivers/net/ixgbevf/ixgbevf.h
index da4033c6efa2..a63efcb2cf1b 100644
--- a/drivers/net/ixgbevf/ixgbevf.h
+++ b/drivers/net/ixgbevf/ixgbevf.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -275,9 +275,11 @@ enum ixbgevf_state_t {
 
 enum ixgbevf_boards {
         board_82599_vf,
+        board_X540_vf,
 };
 
-extern struct ixgbevf_info ixgbevf_vf_info;
+extern struct ixgbevf_info ixgbevf_82599_vf_info;
+extern struct ixgbevf_info ixgbevf_X540_vf_info;
 extern struct ixgbe_mac_operations ixgbevf_mbx_ops;
 
 /* needed by ethtool.c */
diff --git a/drivers/net/ixgbevf/ixgbevf_main.c b/drivers/net/ixgbevf/ixgbevf_main.c
index dc03c9652389..464e6c9d3fc2 100644
--- a/drivers/net/ixgbevf/ixgbevf_main.c
+++ b/drivers/net/ixgbevf/ixgbevf_main.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -51,12 +51,14 @@ char ixgbevf_driver_name[] = "ixgbevf";
 static const char ixgbevf_driver_string[] =
         "Intel(R) 82599 Virtual Function";
 
-#define DRV_VERSION "1.0.0-k0"
+#define DRV_VERSION "1.0.19-k0"
 const char ixgbevf_driver_version[] = DRV_VERSION;
-static char ixgbevf_copyright[] = "Copyright (c) 2009 Intel Corporation.";
+static char ixgbevf_copyright[] =
+        "Copyright (c) 2009 - 2010 Intel Corporation.";
 
 static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
-        [board_82599_vf] = &ixgbevf_vf_info,
+        [board_82599_vf] = &ixgbevf_82599_vf_info,
+        [board_X540_vf]  = &ixgbevf_X540_vf_info,
 };
 
 /* ixgbevf_pci_tbl - PCI Device ID Table
@@ -70,6 +72,8 @@ static const struct ixgbevf_info *ixgbevf_info_tbl[] = {
 static struct pci_device_id ixgbevf_pci_tbl[] = {
         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_VF),
         board_82599_vf},
+        {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540_VF),
+        board_X540_vf},
 
         /* required last entry */
         {0, }
@@ -2488,10 +2492,9 @@ int ixgbevf_setup_tx_resources(struct ixgbevf_adapter *adapter,
         int size;
 
         size = sizeof(struct ixgbevf_tx_buffer) * tx_ring->count;
-        tx_ring->tx_buffer_info = vmalloc(size);
+        tx_ring->tx_buffer_info = vzalloc(size);
         if (!tx_ring->tx_buffer_info)
                 goto err;
-        memset(tx_ring->tx_buffer_info, 0, size);
 
         /* round up to nearest 4K */
         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
@@ -2555,14 +2558,13 @@ int ixgbevf_setup_rx_resources(struct ixgbevf_adapter *adapter,
         int size;
 
         size = sizeof(struct ixgbevf_rx_buffer) * rx_ring->count;
-        rx_ring->rx_buffer_info = vmalloc(size);
+        rx_ring->rx_buffer_info = vzalloc(size);
         if (!rx_ring->rx_buffer_info) {
                 hw_dbg(&adapter->hw,
                        "Unable to vmalloc buffer memory for "
                        "the receive descriptor ring\n");
                 goto alloc_failed;
         }
-        memset(rx_ring->rx_buffer_info, 0, size);
 
         /* Round up to nearest 4K */
         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
@@ -3424,10 +3426,6 @@ static int __devinit ixgbevf_probe(struct pci_dev *pdev,
         if (hw->mac.ops.get_bus_info)
                 hw->mac.ops.get_bus_info(hw);
 
-
-        netif_carrier_off(netdev);
-        netif_tx_stop_all_queues(netdev);
-
         strcpy(netdev->name, "eth%d");
 
         err = register_netdev(netdev);
@@ -3436,6 +3434,8 @@ static int __devinit ixgbevf_probe(struct pci_dev *pdev,
 
         adapter->netdev_registered = true;
 
+        netif_carrier_off(netdev);
+
         ixgbevf_init_last_counter_stats(adapter);
 
         /* print the MAC address */
@@ -3487,10 +3487,9 @@ static void __devexit ixgbevf_remove(struct pci_dev *pdev)
 
         del_timer_sync(&adapter->watchdog_timer);
 
+        cancel_work_sync(&adapter->reset_task);
         cancel_work_sync(&adapter->watchdog_task);
 
-        flush_scheduled_work();
-
         if (adapter->netdev_registered) {
                 unregister_netdev(netdev);
                 adapter->netdev_registered = false;
diff --git a/drivers/net/ixgbevf/mbx.c b/drivers/net/ixgbevf/mbx.c
index 84ac486f4a65..7a8833125770 100644
--- a/drivers/net/ixgbevf/mbx.c
+++ b/drivers/net/ixgbevf/mbx.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbevf/mbx.h b/drivers/net/ixgbevf/mbx.h
index 8c063bebee7f..b2b5bf5daa3d 100644
--- a/drivers/net/ixgbevf/mbx.h
+++ b/drivers/net/ixgbevf/mbx.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbevf/regs.h b/drivers/net/ixgbevf/regs.h
index 12f75960aec1..fb80ca1bcc93 100644
--- a/drivers/net/ixgbevf/regs.h
+++ b/drivers/net/ixgbevf/regs.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/ixgbevf/vf.c b/drivers/net/ixgbevf/vf.c
index bfe42c1fcfaf..eecd3bf6833f 100644
--- a/drivers/net/ixgbevf/vf.c
+++ b/drivers/net/ixgbevf/vf.c
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -381,8 +381,12 @@ static struct ixgbe_mac_operations ixgbevf_mac_ops = {
         .set_vfta            = ixgbevf_set_vfta_vf,
 };
 
-struct ixgbevf_info ixgbevf_vf_info = {
+struct ixgbevf_info ixgbevf_82599_vf_info = {
         .mac = ixgbe_mac_82599_vf,
         .mac_ops = &ixgbevf_mac_ops,
 };
 
+struct ixgbevf_info ixgbevf_X540_vf_info = {
+        .mac = ixgbe_mac_X540_vf,
+        .mac_ops = &ixgbevf_mac_ops,
+};
diff --git a/drivers/net/ixgbevf/vf.h b/drivers/net/ixgbevf/vf.h
index 61f9dc831424..23eb114c149f 100644
--- a/drivers/net/ixgbevf/vf.h
+++ b/drivers/net/ixgbevf/vf.h
@@ -1,7 +1,7 @@
 /*******************************************************************************
 
   Intel 82599 Virtual Function driver
-  Copyright(c) 1999 - 2009 Intel Corporation.
+  Copyright(c) 1999 - 2010 Intel Corporation.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
@@ -73,6 +73,7 @@ struct ixgbe_mac_operations {
 enum ixgbe_mac_type {
         ixgbe_mac_unknown = 0,
         ixgbe_mac_82599_vf,
+        ixgbe_mac_X540_vf,
         ixgbe_num_macs
 };
 
diff --git a/drivers/net/jme.c b/drivers/net/jme.c
index c57d9a43ceca..e97ebef3cf47 100644
--- a/drivers/net/jme.c
+++ b/drivers/net/jme.c
@@ -135,7 +135,7 @@ jme_reset_phy_processor(struct jme_adapter *jme)
 
 static void
 jme_setup_wakeup_frame(struct jme_adapter *jme,
-                u32 *mask, u32 crc, int fnr)
+                       const u32 *mask, u32 crc, int fnr)
 {
         int i;
 
@@ -163,7 +163,7 @@ jme_setup_wakeup_frame(struct jme_adapter *jme,
 static inline void
 jme_reset_mac_processor(struct jme_adapter *jme)
 {
-        u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
+        static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
         u32 crc = 0xCDCDCDCD;
         u32 gpreg0;
         int i;
@@ -2076,12 +2076,11 @@ jme_change_mtu(struct net_device *netdev, int new_mtu)
         }
 
         if (new_mtu > 1900) {
-                netdev->features &= ~(NETIF_F_HW_CSUM |
-                                NETIF_F_TSO |
-                                NETIF_F_TSO6);
+                netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
+                                NETIF_F_TSO | NETIF_F_TSO6);
         } else {
                 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
-                        netdev->features |= NETIF_F_HW_CSUM;
+                        netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
                 if (test_bit(JME_FLAG_TSO, &jme->flags))
                         netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
         }
@@ -2514,10 +2513,12 @@ jme_set_tx_csum(struct net_device *netdev, u32 on)
         if (on) {
                 set_bit(JME_FLAG_TXCSUM, &jme->flags);
                 if (netdev->mtu <= 1900)
-                        netdev->features |= NETIF_F_HW_CSUM;
+                        netdev->features |=
+                                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
         } else {
                 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
-                netdev->features &= ~NETIF_F_HW_CSUM;
+                netdev->features &=
+                                ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
         }
 
         return 0;
@@ -2797,7 +2798,8 @@ jme_init_one(struct pci_dev *pdev,
         netdev->netdev_ops = &jme_netdev_ops;
         netdev->ethtool_ops             = &jme_ethtool_ops;
         netdev->watchdog_timeo          = TX_TIMEOUT;
-        netdev->features                =       NETIF_F_HW_CSUM |
+        netdev->features                =       NETIF_F_IP_CSUM |
+                                                NETIF_F_IPV6_CSUM |
                                                 NETIF_F_SG |
                                                 NETIF_F_TSO |
                                                 NETIF_F_TSO6 |
diff --git a/drivers/net/ks8851.c b/drivers/net/ks8851.c
index 51919fcd50c2..0fa4a9887ba2 100644
--- a/drivers/net/ks8851.c
+++ b/drivers/net/ks8851.c
@@ -1545,6 +1545,37 @@ static int ks8851_read_selftest(struct ks8851_net *ks)
 
 /* driver bus management functions */
 
+#ifdef CONFIG_PM
+static int ks8851_suspend(struct spi_device *spi, pm_message_t state)
+{
+        struct ks8851_net *ks = dev_get_drvdata(&spi->dev);
+        struct net_device *dev = ks->netdev;
+
+        if (netif_running(dev)) {
+                netif_device_detach(dev);
+                ks8851_net_stop(dev);
+        }
+
+        return 0;
+}
+
+static int ks8851_resume(struct spi_device *spi)
+{
+        struct ks8851_net *ks = dev_get_drvdata(&spi->dev);
+        struct net_device *dev = ks->netdev;
+
+        if (netif_running(dev)) {
+                ks8851_net_open(dev);
+                netif_device_attach(dev);
+        }
+
+        return 0;
+}
+#else
+#define ks8851_suspend NULL
+#define ks8851_resume NULL
+#endif
+
 static int __devinit ks8851_probe(struct spi_device *spi)
 {
         struct net_device *ndev;
@@ -1679,6 +1710,8 @@ static struct spi_driver ks8851_driver = {
         },
         .probe = ks8851_probe,
         .remove = __devexit_p(ks8851_remove),
+        .suspend = ks8851_suspend,
+        .resume = ks8851_resume,
 };
 
 static int __init ks8851_init(void)
diff --git a/drivers/net/ksz884x.c b/drivers/net/ksz884x.c
index 37504a398906..540a8dcbcc46 100644
--- a/drivers/net/ksz884x.c
+++ b/drivers/net/ksz884x.c
@@ -3570,7 +3570,7 @@ static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
  * This routine is used to program Wake-on-LAN pattern.
  */
 static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
-        u8 *mask, uint frame_size, u8 *pattern)
+        const u8 *mask, uint frame_size, const u8 *pattern)
 {
         int bits;
         int from;
@@ -3626,9 +3626,9 @@ static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
  *
  * This routine is used to add ARP pattern for waking up the host.
  */
-static void hw_add_wol_arp(struct ksz_hw *hw, u8 *ip_addr)
+static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
 {
-        u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
+        static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
         u8 pattern[42] = {
                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -3651,8 +3651,8 @@ static void hw_add_wol_arp(struct ksz_hw *hw, u8 *ip_addr)
  */
 static void hw_add_wol_bcast(struct ksz_hw *hw)
 {
-        u8 mask[] = { 0x3F };
-        u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
+        static const u8 mask[] = { 0x3F };
+        static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
 
         hw_set_wol_frame(hw, 2, 1, mask, MAC_ADDR_LEN, pattern);
 }
@@ -3669,7 +3669,7 @@ static void hw_add_wol_bcast(struct ksz_hw *hw)
  */
 static void hw_add_wol_mcast(struct ksz_hw *hw)
 {
-        u8 mask[] = { 0x3F };
+        static const u8 mask[] = { 0x3F };
         u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
 
         memcpy(&pattern[3], &hw->override_addr[3], 3);
@@ -3687,7 +3687,7 @@ static void hw_add_wol_mcast(struct ksz_hw *hw)
  */
 static void hw_add_wol_ucast(struct ksz_hw *hw)
 {
-        u8 mask[] = { 0x3F };
+        static const u8 mask[] = { 0x3F };
 
         hw_set_wol_frame(hw, 0, 1, mask, MAC_ADDR_LEN, hw->override_addr);
 }
@@ -3700,7 +3700,7 @@ static void hw_add_wol_ucast(struct ksz_hw *hw)
  *
  * This routine is used to enable Wake-on-LAN depending on driver settings.
  */
-static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, u8 *net_addr)
+static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
 {
         hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
         hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
@@ -6208,7 +6208,7 @@ static int netdev_set_wol(struct net_device *dev,
         struct dev_info *hw_priv = priv->adapter;
 
         /* Need to find a way to retrieve the device IP address. */
-        u8 net_addr[] = { 192, 168, 1, 1 };
+        static const u8 net_addr[] = { 192, 168, 1, 1 };
 
         if (wol->wolopts & ~hw_priv->wol_support)
                 return -EINVAL;
@@ -6953,7 +6953,7 @@ static void read_other_addr(struct ksz_hw *hw)
 #define PCI_VENDOR_ID_MICREL_KS         0x16c6
 #endif
 
-static int __init pcidev_init(struct pci_dev *pdev,
+static int __devinit pcidev_init(struct pci_dev *pdev,
         const struct pci_device_id *id)
 {
         struct net_device *dev;
@@ -7241,7 +7241,7 @@ static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
         struct ksz_hw *hw = &hw_priv->hw;
 
         /* Need to find a way to retrieve the device IP address. */
-        u8 net_addr[] = { 192, 168, 1, 1 };
+        static const u8 net_addr[] = { 192, 168, 1, 1 };
 
         for (i = 0; i < hw->dev_count; i++) {
                 if (info->netdev[i]) {
diff --git a/drivers/net/lance.c b/drivers/net/lance.c
index f06296bfe293..02336edce748 100644
--- a/drivers/net/lance.c
+++ b/drivers/net/lance.c
@@ -207,7 +207,7 @@ tx_full and tbusy flags.
 #define LANCE_BUS_IF 0x16
 #define LANCE_TOTAL_SIZE 0x18
 
-#define TX_TIMEOUT      20
+#define TX_TIMEOUT      (HZ/5)
 
 /* The LANCE Rx and Tx ring descriptors. */
 struct lance_rx_head {
diff --git a/drivers/net/lib82596.c b/drivers/net/lib82596.c
index c27f4291b350..9e042894479b 100644
--- a/drivers/net/lib82596.c
+++ b/drivers/net/lib82596.c
@@ -161,7 +161,7 @@ enum commands {
 #define  RX_SUSPEND     0x0030
 #define  RX_ABORT       0x0040
 
-#define TX_TIMEOUT      5
+#define TX_TIMEOUT      (HZ/20)
 
 
 struct i596_reg {
diff --git a/drivers/net/lib8390.c b/drivers/net/lib8390.c
index e7030ceb178b..da74db4a03d4 100644
--- a/drivers/net/lib8390.c
+++ b/drivers/net/lib8390.c
@@ -203,7 +203,7 @@ static void __NS8390_init(struct net_device *dev, int startp);
 static int __ei_open(struct net_device *dev)
 {
         unsigned long flags;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 
         if (dev->watchdog_timeo <= 0)
                  dev->watchdog_timeo = TX_TIMEOUT;
@@ -231,7 +231,7 @@ static int __ei_open(struct net_device *dev)
  */
 static int __ei_close(struct net_device *dev)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned long flags;
 
         /*
@@ -256,7 +256,7 @@ static int __ei_close(struct net_device *dev)
 static void __ei_tx_timeout(struct net_device *dev)
 {
         unsigned long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int txsr, isr, tickssofar = jiffies - dev_trans_start(dev);
         unsigned long flags;
 
@@ -303,7 +303,7 @@ static netdev_tx_t __ei_start_xmit(struct sk_buff *skb,
                                    struct net_device *dev)
 {
         unsigned long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int send_length = skb->len, output_page;
         unsigned long flags;
         char buf[ETH_ZLEN];
@@ -592,7 +592,7 @@ static void ei_tx_err(struct net_device *dev)
 static void ei_tx_intr(struct net_device *dev)
 {
         unsigned long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int status = ei_inb(e8390_base + EN0_TSR);
 
         ei_outb_p(ENISR_TX, e8390_base + EN0_ISR); /* Ack intr. */
@@ -675,7 +675,7 @@ static void ei_tx_intr(struct net_device *dev)
 static void ei_receive(struct net_device *dev)
 {
         unsigned long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned char rxing_page, this_frame, next_frame;
         unsigned short current_offset;
         int rx_pkt_count = 0;
@@ -879,7 +879,7 @@ static void ei_rx_overrun(struct net_device *dev)
 static struct net_device_stats *__ei_get_stats(struct net_device *dev)
 {
         unsigned long ioaddr = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned long flags;
 
         /* If the card is stopped, just return the present stats. */
@@ -927,7 +927,7 @@ static void do_set_multicast_list(struct net_device *dev)
 {
         unsigned long e8390_base = dev->base_addr;
         int i;
-        struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 
         if (!(dev->flags&(IFF_PROMISC|IFF_ALLMULTI)))
         {
@@ -981,7 +981,7 @@ static void do_set_multicast_list(struct net_device *dev)
 static void __ei_set_multicast_list(struct net_device *dev)
 {
         unsigned long flags;
-        struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 
         spin_lock_irqsave(&ei_local->page_lock, flags);
         do_set_multicast_list(dev);
@@ -998,7 +998,7 @@ static void __ei_set_multicast_list(struct net_device *dev)
 
 static void ethdev_setup(struct net_device *dev)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         if (ei_debug > 1)
                 printk(version);
 
@@ -1036,7 +1036,7 @@ static struct net_device *____alloc_ei_netdev(int size)
 static void __NS8390_init(struct net_device *dev, int startp)
 {
         unsigned long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int i;
         int endcfg = ei_local->word16
             ? (0x48 | ENDCFG_WTS | (ei_local->bigendian ? ENDCFG_BOS : 0))
@@ -1099,7 +1099,7 @@ static void NS8390_trigger_send(struct net_device *dev, unsigned int length,
                                                                 int start_page)
 {
         unsigned long e8390_base = dev->base_addr;
-        struct ei_device *ei_local __attribute((unused)) = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local __attribute((unused)) = netdev_priv(dev);
 
         ei_outb_p(E8390_NODMA+E8390_PAGE0, e8390_base+E8390_CMD);
 
diff --git a/drivers/net/ll_temac_main.c b/drivers/net/ll_temac_main.c
index 661ed1ff4c2e..f35554d11441 100644
--- a/drivers/net/ll_temac_main.c
+++ b/drivers/net/ll_temac_main.c
@@ -692,7 +692,7 @@ static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 
         cur_p->app0 = 0;
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                unsigned int csum_start_off = skb_transport_offset(skb);
+                unsigned int csum_start_off = skb_checksum_start_offset(skb);
                 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
 
                 cur_p->app0 |= 1; /* TX Checksum Enabled */
@@ -952,7 +952,7 @@ static const struct attribute_group temac_attr_group = {
         .attrs = temac_device_attrs,
 };
 
-static int __init
+static int __devinit
 temac_of_probe(struct platform_device *op, const struct of_device_id *match)
 {
         struct device_node *np;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 0fc9dc7f20db..6ed577b065df 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -38,6 +38,7 @@ struct macvlan_port {
         struct hlist_head       vlan_hash[MACVLAN_HASH_SIZE];
         struct list_head        vlans;
         struct rcu_head         rcu;
+        bool                    passthru;
 };
 
 #define macvlan_port_get_rcu(dev) \
@@ -169,6 +170,7 @@ static struct sk_buff *macvlan_handle_frame(struct sk_buff *skb)
                         macvlan_broadcast(skb, port, NULL,
                                           MACVLAN_MODE_PRIVATE |
                                           MACVLAN_MODE_VEPA    |
+                                          MACVLAN_MODE_PASSTHRU|
                                           MACVLAN_MODE_BRIDGE);
                 else if (src->mode == MACVLAN_MODE_VEPA)
                         /* flood to everyone except source */
@@ -185,7 +187,10 @@ static struct sk_buff *macvlan_handle_frame(struct sk_buff *skb)
                 return skb;
         }
 
-        vlan = macvlan_hash_lookup(port, eth->h_dest);
+        if (port->passthru)
+                vlan = list_first_entry(&port->vlans, struct macvlan_dev, list);
+        else
+                vlan = macvlan_hash_lookup(port, eth->h_dest);
         if (vlan == NULL)
                 return skb;
 
@@ -243,18 +248,22 @@ xmit_world:
 netdev_tx_t macvlan_start_xmit(struct sk_buff *skb,
                                struct net_device *dev)
 {
-        int i = skb_get_queue_mapping(skb);
-        struct netdev_queue *txq = netdev_get_tx_queue(dev, i);
         unsigned int len = skb->len;
         int ret;
+        const struct macvlan_dev *vlan = netdev_priv(dev);
 
         ret = macvlan_queue_xmit(skb, dev);
         if (likely(ret == NET_XMIT_SUCCESS || ret == NET_XMIT_CN)) {
-                txq->tx_packets++;
-                txq->tx_bytes += len;
-        } else
-                txq->tx_dropped++;
+                struct macvlan_pcpu_stats *pcpu_stats;
 
+                pcpu_stats = this_cpu_ptr(vlan->pcpu_stats);
+                u64_stats_update_begin(&pcpu_stats->syncp);
+                pcpu_stats->tx_packets++;
+                pcpu_stats->tx_bytes += len;
+                u64_stats_update_end(&pcpu_stats->syncp);
+        } else {
+                this_cpu_inc(vlan->pcpu_stats->tx_dropped);
+        }
         return ret;
 }
 EXPORT_SYMBOL_GPL(macvlan_start_xmit);
@@ -284,6 +293,11 @@ static int macvlan_open(struct net_device *dev)
         struct net_device *lowerdev = vlan->lowerdev;
         int err;
 
+        if (vlan->port->passthru) {
+                dev_set_promiscuity(lowerdev, 1);
+                goto hash_add;
+        }
+
         err = -EBUSY;
         if (macvlan_addr_busy(vlan->port, dev->dev_addr))
                 goto out;
@@ -296,6 +310,8 @@ static int macvlan_open(struct net_device *dev)
                 if (err < 0)
                         goto del_unicast;
         }
+
+hash_add:
         macvlan_hash_add(vlan);
         return 0;
 
@@ -310,12 +326,18 @@ static int macvlan_stop(struct net_device *dev)
         struct macvlan_dev *vlan = netdev_priv(dev);
         struct net_device *lowerdev = vlan->lowerdev;
 
+        if (vlan->port->passthru) {
+                dev_set_promiscuity(lowerdev, -1);
+                goto hash_del;
+        }
+
         dev_mc_unsync(lowerdev, dev);
         if (dev->flags & IFF_ALLMULTI)
                 dev_set_allmulti(lowerdev, -1);
 
         dev_uc_del(lowerdev, dev->dev_addr);
 
+hash_del:
         macvlan_hash_del(vlan);
         return 0;
 }
@@ -414,14 +436,15 @@ static int macvlan_init(struct net_device *dev)
         dev->state              = (dev->state & ~MACVLAN_STATE_MASK) |
                                   (lowerdev->state & MACVLAN_STATE_MASK);
         dev->features           = lowerdev->features & MACVLAN_FEATURES;
+        dev->features           |= NETIF_F_LLTX;
         dev->gso_max_size       = lowerdev->gso_max_size;
         dev->iflink             = lowerdev->ifindex;
         dev->hard_header_len    = lowerdev->hard_header_len;
 
         macvlan_set_lockdep_class(dev);
 
-        vlan->rx_stats = alloc_percpu(struct macvlan_rx_stats);
-        if (!vlan->rx_stats)
+        vlan->pcpu_stats = alloc_percpu(struct macvlan_pcpu_stats);
+        if (!vlan->pcpu_stats)
                 return -ENOMEM;
 
         return 0;
@@ -431,7 +454,7 @@ static void macvlan_uninit(struct net_device *dev)
 {
         struct macvlan_dev *vlan = netdev_priv(dev);
 
-        free_percpu(vlan->rx_stats);
+        free_percpu(vlan->pcpu_stats);
 }
 
 static struct rtnl_link_stats64 *macvlan_dev_get_stats64(struct net_device *dev,
@@ -439,33 +462,38 @@ static struct rtnl_link_stats64 *macvlan_dev_get_stats64(struct net_device *dev,
 {
         struct macvlan_dev *vlan = netdev_priv(dev);
 
-        dev_txq_stats_fold(dev, stats);
-
-        if (vlan->rx_stats) {
-                struct macvlan_rx_stats *p, accum = {0};
-                u64 rx_packets, rx_bytes, rx_multicast;
+        if (vlan->pcpu_stats) {
+                struct macvlan_pcpu_stats *p;
+                u64 rx_packets, rx_bytes, rx_multicast, tx_packets, tx_bytes;
+                u32 rx_errors = 0, tx_dropped = 0;
                 unsigned int start;
                 int i;
 
                 for_each_possible_cpu(i) {
-                        p = per_cpu_ptr(vlan->rx_stats, i);
+                        p = per_cpu_ptr(vlan->pcpu_stats, i);
                         do {
                                 start = u64_stats_fetch_begin_bh(&p->syncp);
                                 rx_packets      = p->rx_packets;
                                 rx_bytes        = p->rx_bytes;
                                 rx_multicast    = p->rx_multicast;
+                                tx_packets      = p->tx_packets;
+                                tx_bytes        = p->tx_bytes;
                         } while (u64_stats_fetch_retry_bh(&p->syncp, start));
-                        accum.rx_packets        += rx_packets;
-                        accum.rx_bytes          += rx_bytes;
-                        accum.rx_multicast      += rx_multicast;
-                        /* rx_errors is an ulong, updated without syncp protection */
-                        accum.rx_errors         += p->rx_errors;
+
+                        stats->rx_packets       += rx_packets;
+                        stats->rx_bytes         += rx_bytes;
+                        stats->multicast        += rx_multicast;
+                        stats->tx_packets       += tx_packets;
+                        stats->tx_bytes         += tx_bytes;
+                        /* rx_errors & tx_dropped are u32, updated
+                         * without syncp protection.
+                         */
+                        rx_errors       += p->rx_errors;
+                        tx_dropped      += p->tx_dropped;
                 }
-                stats->rx_packets = accum.rx_packets;
-                stats->rx_bytes   = accum.rx_bytes;
-                stats->rx_errors  = accum.rx_errors;
-                stats->rx_dropped = accum.rx_errors;
-                stats->multicast  = accum.rx_multicast;
+                stats->rx_errors        = rx_errors;
+                stats->rx_dropped       = rx_errors;
+                stats->tx_dropped       = tx_dropped;
         }
         return stats;
 }
@@ -549,6 +577,7 @@ static int macvlan_port_create(struct net_device *dev)
         if (port == NULL)
                 return -ENOMEM;
 
+        port->passthru = false;
         port->dev = dev;
         INIT_LIST_HEAD(&port->vlans);
         for (i = 0; i < MACVLAN_HASH_SIZE; i++)
@@ -593,6 +622,7 @@ static int macvlan_validate(struct nlattr *tb[], struct nlattr *data[])
                 case MACVLAN_MODE_PRIVATE:
                 case MACVLAN_MODE_VEPA:
                 case MACVLAN_MODE_BRIDGE:
+                case MACVLAN_MODE_PASSTHRU:
                         break;
                 default:
                         return -EINVAL;
@@ -601,25 +631,6 @@ static int macvlan_validate(struct nlattr *tb[], struct nlattr *data[])
         return 0;
 }
 
-static int macvlan_get_tx_queues(struct net *net,
-                                 struct nlattr *tb[],
-                                 unsigned int *num_tx_queues,
-                                 unsigned int *real_num_tx_queues)
-{
-        struct net_device *real_dev;
-
-        if (!tb[IFLA_LINK])
-                return -EINVAL;
-
-        real_dev = __dev_get_by_index(net, nla_get_u32(tb[IFLA_LINK]));
-        if (!real_dev)
-                return -ENODEV;
-
-        *num_tx_queues      = real_dev->num_tx_queues;
-        *real_num_tx_queues = real_dev->real_num_tx_queues;
-        return 0;
-}
-
 int macvlan_common_newlink(struct net *src_net, struct net_device *dev,
                            struct nlattr *tb[], struct nlattr *data[],
                            int (*receive)(struct sk_buff *skb),
@@ -661,6 +672,10 @@ int macvlan_common_newlink(struct net *src_net, struct net_device *dev,
         }
         port = macvlan_port_get(lowerdev);
 
+        /* Only 1 macvlan device can be created in passthru mode */
+        if (port->passthru)
+                return -EINVAL;
+
         vlan->lowerdev = lowerdev;
         vlan->dev      = dev;
         vlan->port     = port;
@@ -671,6 +686,13 @@ int macvlan_common_newlink(struct net *src_net, struct net_device *dev,
         if (data && data[IFLA_MACVLAN_MODE])
                 vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
 
+        if (vlan->mode == MACVLAN_MODE_PASSTHRU) {
+                if (!list_empty(&port->vlans))
+                        return -EINVAL;
+                port->passthru = true;
+                memcpy(dev->dev_addr, lowerdev->dev_addr, ETH_ALEN);
+        }
+
         err = register_netdevice(dev);
         if (err < 0)
                 goto destroy_port;
@@ -743,7 +765,6 @@ int macvlan_link_register(struct rtnl_link_ops *ops)
 {
         /* common fields */
         ops->priv_size          = sizeof(struct macvlan_dev);
-        ops->get_tx_queues      = macvlan_get_tx_queues;
         ops->validate           = macvlan_validate;
         ops->maxtype            = IFLA_MACVLAN_MAX;
         ops->policy             = macvlan_policy;
diff --git a/drivers/net/macvtap.c b/drivers/net/macvtap.c
index 42567279843e..21845affea13 100644
--- a/drivers/net/macvtap.c
+++ b/drivers/net/macvtap.c
@@ -504,8 +504,7 @@ static int macvtap_skb_to_vnet_hdr(const struct sk_buff *skb,
 
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
                 vnet_hdr->flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
-                vnet_hdr->csum_start = skb->csum_start -
-                                        skb_headroom(skb);
+                vnet_hdr->csum_start = skb_checksum_start_offset(skb);
                 vnet_hdr->csum_offset = skb->csum_offset;
         } /* else everything is zero */
 
diff --git a/drivers/net/mlx4/alloc.c b/drivers/net/mlx4/alloc.c
index 8f4bf1f07c11..3a4277f6fac4 100644
--- a/drivers/net/mlx4/alloc.c
+++ b/drivers/net/mlx4/alloc.c
@@ -178,6 +178,7 @@ int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
         } else {
                 int i;
 
+                buf->direct.buf  = NULL;
                 buf->nbufs       = (size + PAGE_SIZE - 1) / PAGE_SIZE;
                 buf->npages      = buf->nbufs;
                 buf->page_shift  = PAGE_SHIFT;
@@ -229,7 +230,7 @@ void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf)
                 dma_free_coherent(&dev->pdev->dev, size, buf->direct.buf,
                                   buf->direct.map);
         else {
-                if (BITS_PER_LONG == 64)
+                if (BITS_PER_LONG == 64 && buf->direct.buf)
                         vunmap(buf->direct.buf);
 
                 for (i = 0; i < buf->nbufs; ++i)
diff --git a/drivers/net/mlx4/en_netdev.c b/drivers/net/mlx4/en_netdev.c
index 6d6806b361e3..897f576b8b17 100644
--- a/drivers/net/mlx4/en_netdev.c
+++ b/drivers/net/mlx4/en_netdev.c
@@ -972,7 +972,8 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         int i;
         int err;
 
-        dev = alloc_etherdev_mq(sizeof(struct mlx4_en_priv), prof->tx_ring_num);
+        dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
+            prof->tx_ring_num, prof->rx_ring_num);
         if (dev == NULL) {
                 mlx4_err(mdev, "Net device allocation failed\n");
                 return -ENOMEM;
diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c
index 7a7e18ba278a..5de1db897835 100644
--- a/drivers/net/mlx4/fw.c
+++ b/drivers/net/mlx4/fw.c
@@ -289,10 +289,8 @@ int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
                 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
                 dev_cap->bf_reg_size = 1 << (field & 0x1f);
                 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
-                if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) {
-                        mlx4_warn(dev, "firmware bug: log2 # of blue flame regs is invalid (%d), forcing 3\n", field & 0x1f);
+                if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
                         field = 3;
-                }
                 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
                 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
                          dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index dd2b6a71c6d7..02076e16542a 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -1514,11 +1514,6 @@ static int mv643xx_eth_nway_reset(struct net_device *dev)
         return genphy_restart_aneg(mp->phy);
 }
 
-static u32 mv643xx_eth_get_link(struct net_device *dev)
-{
-        return !!netif_carrier_ok(dev);
-}
-
 static int
 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
 {
@@ -1658,7 +1653,7 @@ static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
         .set_settings           = mv643xx_eth_set_settings,
         .get_drvinfo            = mv643xx_eth_get_drvinfo,
         .nway_reset             = mv643xx_eth_nway_reset,
-        .get_link               = mv643xx_eth_get_link,
+        .get_link               = ethtool_op_get_link,
         .get_coalesce           = mv643xx_eth_get_coalesce,
         .set_coalesce           = mv643xx_eth_set_coalesce,
         .get_ringparam          = mv643xx_eth_get_ringparam,
@@ -2983,7 +2978,7 @@ static int mv643xx_eth_remove(struct platform_device *pdev)
         unregister_netdev(mp->dev);
         if (mp->phy != NULL)
                 phy_detach(mp->phy);
-        flush_scheduled_work();
+        cancel_work_sync(&mp->tx_timeout_task);
         free_netdev(mp->dev);
 
         platform_set_drvdata(pdev, NULL);
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 8524cc40ec57..a37fcf11ab36 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -2736,7 +2736,7 @@ again:
         odd_flag = 0;
         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
-                cksum_offset = skb_transport_offset(skb);
+                cksum_offset = skb_checksum_start_offset(skb);
                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
                 /* If the headers are excessively large, then we must
                  * fall back to a software checksum */
@@ -4067,7 +4067,7 @@ static void myri10ge_remove(struct pci_dev *pdev)
         if (mgp == NULL)
                 return;
 
-        flush_scheduled_work();
+        cancel_work_sync(&mgp->watchdog_work);
         netdev = mgp->dev;
         unregister_netdev(netdev);
 
diff --git a/drivers/net/ne-h8300.c b/drivers/net/ne-h8300.c
index e0b0ef11f110..30be8c634ebd 100644
--- a/drivers/net/ne-h8300.c
+++ b/drivers/net/ne-h8300.c
@@ -86,7 +86,7 @@ static u32 reg_offset[16];
 
 static int __init init_reg_offset(struct net_device *dev,unsigned long base_addr)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int i;
         unsigned char bus_width;
 
@@ -218,7 +218,7 @@ static int __init ne_probe1(struct net_device *dev, int ioaddr)
         int start_page, stop_page;
         int reg0, ret;
         static unsigned version_printed;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned char bus_width;
 
         if (!request_region(ioaddr, NE_IO_EXTENT, DRV_NAME))
@@ -371,7 +371,7 @@ static int ne_close(struct net_device *dev)
 static void ne_reset_8390(struct net_device *dev)
 {
         unsigned long reset_start_time = jiffies;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 
         if (ei_debug > 1)
                 printk(KERN_DEBUG "resetting the 8390 t=%ld...", jiffies);
@@ -397,7 +397,7 @@ static void ne_reset_8390(struct net_device *dev)
 
 static void ne_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr, int ring_page)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         /* This *shouldn't* happen. If it does, it's the last thing you'll see */
 
         if (ei_status.dmaing)
@@ -437,7 +437,7 @@ static void ne_get_8390_hdr(struct net_device *dev, struct e8390_pkt_hdr *hdr, i
 
 static void ne_block_input(struct net_device *dev, int count, struct sk_buff *skb, int ring_offset)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 #ifdef NE_SANITY_CHECK
         int xfer_count = count;
 #endif
@@ -507,7 +507,7 @@ static void ne_block_input(struct net_device *dev, int count, struct sk_buff *sk
 static void ne_block_output(struct net_device *dev, int count,
                 const unsigned char *buf, const int start_page)
 {
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned long dma_start;
 #ifdef NE_SANITY_CHECK
         int retries = 0;
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c
index 94255f09093d..dfb67eb2a94b 100644
--- a/drivers/net/netconsole.c
+++ b/drivers/net/netconsole.c
@@ -664,6 +664,7 @@ static int netconsole_netdev_event(struct notifier_block *this,
         unsigned long flags;
         struct netconsole_target *nt;
         struct net_device *dev = ptr;
+        bool stopped = false;
 
         if (!(event == NETDEV_CHANGENAME || event == NETDEV_UNREGISTER ||
               event == NETDEV_BONDING_DESLAVE || event == NETDEV_GOING_DOWN))
@@ -690,15 +691,16 @@ static int netconsole_netdev_event(struct notifier_block *this,
                         case NETDEV_GOING_DOWN:
                         case NETDEV_BONDING_DESLAVE:
                                 nt->enabled = 0;
+                                stopped = true;
                                 break;
                         }
                 }
                 netconsole_target_put(nt);
         }
         spin_unlock_irqrestore(&target_list_lock, flags);
-        if (event == NETDEV_UNREGISTER || event == NETDEV_BONDING_DESLAVE)
-                printk(KERN_INFO "netconsole: network logging stopped, "
-                        "interface %s %s\n",  dev->name,
+        if (stopped && (event == NETDEV_UNREGISTER || event == NETDEV_BONDING_DESLAVE))
+                printk(KERN_INFO "netconsole: network logging stopped on "
+                        "interface %s as it %s\n",  dev->name,
                         event == NETDEV_UNREGISTER ? "unregistered" : "released slaves");
 
 done:
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h
index 8e8a97839cb0..a11380544e6c 100644
--- a/drivers/net/netxen/netxen_nic.h
+++ b/drivers/net/netxen/netxen_nic.h
@@ -53,8 +53,8 @@
 
 #define _NETXEN_NIC_LINUX_MAJOR 4
 #define _NETXEN_NIC_LINUX_MINOR 0
-#define _NETXEN_NIC_LINUX_SUBVERSION 74
-#define NETXEN_NIC_LINUX_VERSIONID  "4.0.74"
+#define _NETXEN_NIC_LINUX_SUBVERSION 75
+#define NETXEN_NIC_LINUX_VERSIONID  "4.0.75"
 
 #define NETXEN_VERSION_CODE(a, b, c)    (((a) << 24) + ((b) << 16) + (c))
 #define _major(v)       (((v) >> 24) & 0xff)
@@ -1132,6 +1132,7 @@ typedef struct {
 #define NETXEN_NIC_MSI_ENABLED          0x02
 #define NETXEN_NIC_MSIX_ENABLED         0x04
 #define NETXEN_NIC_LRO_ENABLED          0x08
+#define NETXEN_NIC_LRO_DISABLED         0x00
 #define NETXEN_NIC_BRIDGE_ENABLED       0X10
 #define NETXEN_NIC_DIAG_ENABLED         0x20
 #define NETXEN_IS_MSI_FAMILY(adapter) \
diff --git a/drivers/net/netxen/netxen_nic_ethtool.c b/drivers/net/netxen/netxen_nic_ethtool.c
index b30de24f4a52..587498e140bb 100644
--- a/drivers/net/netxen/netxen_nic_ethtool.c
+++ b/drivers/net/netxen/netxen_nic_ethtool.c
@@ -720,7 +720,21 @@ static u32 netxen_nic_get_rx_csum(struct net_device *dev)
 static int netxen_nic_set_rx_csum(struct net_device *dev, u32 data)
 {
         struct netxen_adapter *adapter = netdev_priv(dev);
-        adapter->rx_csum = !!data;
+
+        if (data) {
+                adapter->rx_csum = data;
+                return 0;
+        }
+
+        if (dev->features & NETIF_F_LRO) {
+                if (netxen_config_hw_lro(adapter, NETXEN_NIC_LRO_DISABLED))
+                        return -EIO;
+
+                dev->features &= ~NETIF_F_LRO;
+                netxen_send_lro_cleanup(adapter);
+                netdev_info(dev, "disabling LRO as rx_csum is off\n");
+        }
+        adapter->rx_csum = data;
         return 0;
 }
 
@@ -893,11 +907,19 @@ static int netxen_nic_set_flags(struct net_device *netdev, u32 data)
         if (!(adapter->capabilities & NX_FW_CAPABILITY_HW_LRO))
                 return -EINVAL;
 
+        if (!adapter->rx_csum) {
+                netdev_info(netdev, "rx csum is off, cannot toggle LRO\n");
+                return -EINVAL;
+        }
+
+        if (!!(data & ETH_FLAG_LRO) == !!(netdev->features & NETIF_F_LRO))
+                return 0;
+
         if (data & ETH_FLAG_LRO) {
                 hw_lro = NETXEN_NIC_LRO_ENABLED;
                 netdev->features |= NETIF_F_LRO;
         } else {
-                hw_lro = 0;
+                hw_lro = NETXEN_NIC_LRO_DISABLED;
                 netdev->features &= ~NETIF_F_LRO;
         }
 
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c
index 37d3ebd65be8..5cef718fe35f 100644
--- a/drivers/net/netxen/netxen_nic_hw.c
+++ b/drivers/net/netxen/netxen_nic_hw.c
@@ -655,7 +655,7 @@ nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
 }
 
 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
-                u8 *addr, struct list_head *del_list)
+                const u8 *addr, struct list_head *del_list)
 {
         struct list_head *head;
         nx_mac_list_t *cur;
@@ -686,7 +686,9 @@ static void netxen_p3_nic_set_multi(struct net_device *netdev)
 {
         struct netxen_adapter *adapter = netdev_priv(netdev);
         struct netdev_hw_addr *ha;
-        u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+        static const u8 bcast_addr[ETH_ALEN] = {
+                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+        };
         u32 mode = VPORT_MISS_MODE_DROP;
         LIST_HEAD(del_list);
         struct list_head *head;
@@ -807,9 +809,6 @@ int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
         u64 word;
         int rv = 0;
 
-        if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
-                return 0;
-
         memset(&req, 0, sizeof(nx_nic_req_t));
 
         req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
@@ -825,8 +824,6 @@ int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
                         "configure hw lro request\n");
         }
 
-        adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
-
         return rv;
 }
 
@@ -869,9 +866,11 @@ int netxen_config_rss(struct netxen_adapter *adapter, int enable)
         u64 word;
         int i, rv;
 
-        u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
-                        0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
-                        0x255b0ec26d5a56daULL };
+        static const u64 key[] = {
+                0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
+                0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
+                0x255b0ec26d5a56daULL
+        };
 
 
         memset(&req, 0, sizeof(nx_nic_req_t));
@@ -895,7 +894,7 @@ int netxen_config_rss(struct netxen_adapter *adapter, int enable)
                 ((u64)(enable & 0x1) << 8) |
                 ((0x7ULL) << 48);
         req.words[0] = cpu_to_le64(word);
-        for (i = 0; i < 5; i++)
+        for (i = 0; i < ARRAY_SIZE(key); i++)
                 req.words[i+1] = cpu_to_le64(key[i]);
 
 
diff --git a/drivers/net/netxen/netxen_nic_init.c b/drivers/net/netxen/netxen_nic_init.c
index 95fe552aa279..731077d8d962 100644
--- a/drivers/net/netxen/netxen_nic_init.c
+++ b/drivers/net/netxen/netxen_nic_init.c
@@ -214,13 +214,12 @@ int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
         tx_ring->num_desc = adapter->num_txd;
         tx_ring->txq = netdev_get_tx_queue(netdev, 0);
 
-        cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
+        cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
         if (cmd_buf_arr == NULL) {
                 dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
                        netdev->name);
                 goto err_out;
         }
-        memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
         tx_ring->cmd_buf_arr = cmd_buf_arr;
 
         recv_ctx = &adapter->recv_ctx;
@@ -279,8 +278,7 @@ int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
                         break;
 
                 }
-                rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
-                        vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
+                rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
                 if (rds_ring->rx_buf_arr == NULL) {
                         printk(KERN_ERR "%s: Failed to allocate "
                                 "rx buffer ring %d\n",
@@ -288,7 +286,6 @@ int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
                         /* free whatever was already allocated */
                         goto err_out;
                 }
-                memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
                 INIT_LIST_HEAD(&rds_ring->free_list);
                 /*
                  * Now go through all of them, set reference handles
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c
index e1d30d7f2071..33fac32e0d9f 100644
--- a/drivers/net/netxen/netxen_nic_main.c
+++ b/drivers/net/netxen/netxen_nic_main.c
@@ -38,7 +38,7 @@
 #include <linux/sysfs.h>
 #include <linux/aer.h>
 
-MODULE_DESCRIPTION("QLogic/NetXen (1/10) GbE Converged Ethernet Driver");
+MODULE_DESCRIPTION("QLogic/NetXen (1/10) GbE Intelligent Ethernet Driver");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(NETXEN_NIC_LINUX_VERSIONID);
 MODULE_FIRMWARE(NX_UNIFIED_ROMIMAGE_NAME);
@@ -762,8 +762,6 @@ netxen_check_options(struct netxen_adapter *adapter)
         if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
                 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
 
-        adapter->flags &= ~NETXEN_NIC_LRO_ENABLED;
-
         if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
@@ -990,7 +988,7 @@ __netxen_nic_up(struct netxen_adapter *adapter, struct net_device *netdev)
         if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
                 netxen_config_intr_coalesce(adapter);
 
-        if (adapter->capabilities & NX_FW_CAPABILITY_HW_LRO)
+        if (netdev->features & NETIF_F_LRO)
                 netxen_config_hw_lro(adapter, NETXEN_NIC_LRO_ENABLED);
 
         netxen_napi_enable(adapter);
@@ -1277,6 +1275,7 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         int i = 0, err;
         int pci_func_id = PCI_FUNC(pdev->devfn);
         uint8_t revision_id;
+        u32 val;
 
         if (pdev->revision >= NX_P3_A0 && pdev->revision <= NX_P3_B1) {
                 pr_warning("%s: chip revisions between 0x%x-0x%x "
@@ -1352,8 +1351,9 @@ netxen_nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 break;
         }
 
-        if (reset_devices) {
-                if (adapter->portnum == 0) {
+        if (adapter->portnum == 0) {
+                val = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);
+                if (val != 0xffffffff && val != 0) {
                         NXWR32(adapter, NX_CRB_DEV_REF_COUNT, 0);
                         adapter->need_fw_reset = 1;
                 }
diff --git a/drivers/net/ni52.c b/drivers/net/ni52.c
index 33618edc61f9..d973fc6c6b88 100644
--- a/drivers/net/ni52.c
+++ b/drivers/net/ni52.c
@@ -388,9 +388,9 @@ static long memend;	/* e.g 0xd4000 */
 struct net_device * __init ni52_probe(int unit)
 {
         struct net_device *dev = alloc_etherdev(sizeof(struct priv));
-        static int ports[] = {0x300, 0x280, 0x360 , 0x320 , 0x340, 0};
+        static const int ports[] = {0x300, 0x280, 0x360, 0x320, 0x340, 0};
+        const int *port;
         struct priv *p;
-        int *port;
         int err = 0;
 
         if (!dev)
diff --git a/drivers/net/ni65.c b/drivers/net/ni65.c
index da228a0dd6cd..c75ae85eb918 100644
--- a/drivers/net/ni65.c
+++ b/drivers/net/ni65.c
@@ -361,8 +361,8 @@ static int dma;
 struct net_device * __init ni65_probe(int unit)
 {
         struct net_device *dev = alloc_etherdev(0);
-        static int ports[] = {0x360,0x300,0x320,0x340, 0};
-        int *port;
+        static const int ports[] = { 0x360, 0x300, 0x320, 0x340, 0 };
+        const int *port;
         int err = 0;
 
         if (!dev)
diff --git a/drivers/net/niu.c b/drivers/net/niu.c
index 781e368329f9..2541321bad82 100644
--- a/drivers/net/niu.c
+++ b/drivers/net/niu.c
@@ -6589,7 +6589,7 @@ static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
                              (ip_proto == IPPROTO_UDP ?
                               TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
 
-                start = skb_transport_offset(skb) -
+                start = skb_checksum_start_offset(skb) -
                         (pad_bytes + sizeof(struct tx_pkt_hdr));
                 stuff = start + skb->csum_offset;
 
@@ -9917,7 +9917,7 @@ static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
         if (!netif_running(dev))
                 return 0;
 
-        flush_scheduled_work();
+        flush_work_sync(&np->reset_task);
         niu_netif_stop(np);
 
         del_timer_sync(&np->timer);
diff --git a/drivers/net/pch_gbe/pch_gbe_ethtool.c b/drivers/net/pch_gbe/pch_gbe_ethtool.c
index c8cc32c0edc9..c8c873b31a89 100644
--- a/drivers/net/pch_gbe/pch_gbe_ethtool.c
+++ b/drivers/net/pch_gbe/pch_gbe_ethtool.c
@@ -469,18 +469,6 @@ static int pch_gbe_set_rx_csum(struct net_device *netdev, u32 data)
 }
 
 /**
- * pch_gbe_get_tx_csum - Report whether transmit checksums are turned on or off
- * @netdev:  Network interface device structure
- * Returns
- *      true(1):  Checksum On
- *      false(0): Checksum Off
- */
-static u32 pch_gbe_get_tx_csum(struct net_device *netdev)
-{
-        return (netdev->features & NETIF_F_HW_CSUM) != 0;
-}
-
-/**
  * pch_gbe_set_tx_csum - Turn transmit checksums on or off
  * @netdev: Network interface device structure
  * @data:   Checksum on[true] or off[false]
@@ -493,11 +481,7 @@ static int pch_gbe_set_tx_csum(struct net_device *netdev, u32 data)
         struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 
         adapter->tx_csum = data;
-        if (data)
-                netdev->features |= NETIF_F_HW_CSUM;
-        else
-                netdev->features &= ~NETIF_F_HW_CSUM;
-        return 0;
+        return ethtool_op_set_tx_ipv6_csum(netdev, data);
 }
 
 /**
@@ -572,7 +556,6 @@ static const struct ethtool_ops pch_gbe_ethtool_ops = {
         .set_pauseparam = pch_gbe_set_pauseparam,
         .get_rx_csum = pch_gbe_get_rx_csum,
         .set_rx_csum = pch_gbe_set_rx_csum,
-        .get_tx_csum = pch_gbe_get_tx_csum,
         .set_tx_csum = pch_gbe_set_tx_csum,
         .get_strings = pch_gbe_get_strings,
         .get_ethtool_stats = pch_gbe_get_ethtool_stats,
diff --git a/drivers/net/pch_gbe/pch_gbe_main.c b/drivers/net/pch_gbe/pch_gbe_main.c
index 03a1d280105f..d7355306a738 100644
--- a/drivers/net/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/pch_gbe/pch_gbe_main.c
@@ -1523,12 +1523,11 @@ int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
         int desNo;
 
         size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
-        tx_ring->buffer_info = vmalloc(size);
+        tx_ring->buffer_info = vzalloc(size);
         if (!tx_ring->buffer_info) {
                 pr_err("Unable to allocate memory for the buffer infomation\n");
                 return -ENOMEM;
         }
-        memset(tx_ring->buffer_info, 0, size);
 
         tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
 
@@ -1573,12 +1572,11 @@ int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
         int desNo;
 
         size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
-        rx_ring->buffer_info = vmalloc(size);
+        rx_ring->buffer_info = vzalloc(size);
         if (!rx_ring->buffer_info) {
                 pr_err("Unable to allocate memory for the receive descriptor ring\n");
                 return -ENOMEM;
         }
-        memset(rx_ring->buffer_info, 0, size);
         rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
                                            &rx_ring->dma, GFP_KERNEL);
@@ -2321,7 +2319,7 @@ static int pch_gbe_probe(struct pci_dev *pdev,
         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
         netif_napi_add(netdev, &adapter->napi,
                        pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
-        netdev->features = NETIF_F_HW_CSUM | NETIF_F_GRO;
+        netdev->features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_GRO;
         pch_gbe_set_ethtool_ops(netdev);
 
         pch_gbe_mac_reset_hw(&adapter->hw);
@@ -2360,9 +2358,9 @@ static int pch_gbe_probe(struct pci_dev *pdev,
         pch_gbe_check_options(adapter);
 
         if (adapter->tx_csum)
-                netdev->features |= NETIF_F_HW_CSUM;
+                netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
         else
-                netdev->features &= ~NETIF_F_HW_CSUM;
+                netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 
         /* initialize the wol settings based on the eeprom settings */
         adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c
index 8a4d19e5de06..1f42f6ac8551 100644
--- a/drivers/net/pcmcia/axnet_cs.c
+++ b/drivers/net/pcmcia/axnet_cs.c
@@ -690,6 +690,7 @@ static void block_output(struct net_device *dev, int count,
 static struct pcmcia_device_id axnet_ids[] = {
         PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x016c, 0x0081),
         PCMCIA_DEVICE_MANF_CARD(0x018a, 0x0301),
+        PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x2328),
         PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0301),
         PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0303),
         PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0309),
@@ -875,7 +876,7 @@ static void do_set_multicast_list(struct net_device *dev);
 static int ax_open(struct net_device *dev)
 {
         unsigned long flags;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 
         /*
          *      Grab the page lock so we own the register set, then call
@@ -926,7 +927,7 @@ static int ax_close(struct net_device *dev)
 static void axnet_tx_timeout(struct net_device *dev)
 {
         long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int txsr, isr, tickssofar = jiffies - dev_trans_start(dev);
         unsigned long flags;
 
@@ -973,7 +974,7 @@ static netdev_tx_t axnet_start_xmit(struct sk_buff *skb,
                                           struct net_device *dev)
 {
         long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int length, send_length, output_page;
         unsigned long flags;
         u8 packet[ETH_ZLEN];
@@ -1270,7 +1271,7 @@ static void ei_tx_err(struct net_device *dev)
 static void ei_tx_intr(struct net_device *dev)
 {
         long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int status = inb(e8390_base + EN0_TSR);
     
         /*
@@ -1354,7 +1355,7 @@ static void ei_tx_intr(struct net_device *dev)
 static void ei_receive(struct net_device *dev)
 {
         long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned char rxing_page, this_frame, next_frame;
         unsigned short current_offset;
         int rx_pkt_count = 0;
@@ -1539,7 +1540,7 @@ static void ei_rx_overrun(struct net_device *dev)
 static struct net_device_stats *get_stats(struct net_device *dev)
 {
         long ioaddr = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         unsigned long flags;
     
         /* If the card is stopped, just return the present stats. */
@@ -1588,7 +1589,7 @@ static void do_set_multicast_list(struct net_device *dev)
 {
         long e8390_base = dev->base_addr;
         int i;
-        struct ei_device *ei_local = (struct ei_device*)netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
 
         if (!(dev->flags&(IFF_PROMISC|IFF_ALLMULTI))) {
                 memset(ei_local->mcfilter, 0, 8);
@@ -1646,7 +1647,7 @@ static void AX88190_init(struct net_device *dev, int startp)
 {
         axnet_dev_t *info = PRIV(dev);
         long e8390_base = dev->base_addr;
-        struct ei_device *ei_local = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local = netdev_priv(dev);
         int i;
         int endcfg = ei_local->word16 ? (0x48 | ENDCFG_WTS) : 0x48;
     
@@ -1712,7 +1713,7 @@ static void NS8390_trigger_send(struct net_device *dev, unsigned int length,
                                                                 int start_page)
 {
         long e8390_base = dev->base_addr;
-        struct ei_device *ei_local __attribute((unused)) = (struct ei_device *) netdev_priv(dev);
+        struct ei_device *ei_local __attribute((unused)) = netdev_priv(dev);
     
         if (inb_p(e8390_base) & E8390_TRANS) 
         {
diff --git a/drivers/net/pcmcia/nmclan_cs.c b/drivers/net/pcmcia/nmclan_cs.c
index 0a2b0f9cdf33..76683d97d83b 100644
--- a/drivers/net/pcmcia/nmclan_cs.c
+++ b/drivers/net/pcmcia/nmclan_cs.c
@@ -1291,7 +1291,7 @@ updateCRC
 
 static void updateCRC(int *CRC, int bit)
 {
-  int poly[]={
+  static const int poly[]={
     1,1,1,0, 1,1,0,1,
     1,0,1,1, 1,0,0,0,
     1,0,0,0, 0,0,1,1,
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index d05c44692f08..e953793a33ff 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1493,7 +1493,6 @@ static struct pcmcia_device_id pcnet_ids[] = {
         PCMCIA_DEVICE_MANF_CARD(0x0149, 0x4530),
         PCMCIA_DEVICE_MANF_CARD(0x0149, 0xc1ab),
         PCMCIA_DEVICE_MANF_CARD(0x0186, 0x0110),
-        PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x2328),
         PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x8041),
         PCMCIA_DEVICE_MANF_CARD(0x0213, 0x2452),
         PCMCIA_DEVICE_MANF_CARD(0x026f, 0x0300),
@@ -1537,6 +1536,7 @@ static struct pcmcia_device_id pcnet_ids[] = {
         PCMCIA_DEVICE_PROD_ID12("CONTEC", "C-NET(PC)C-10L", 0x21cab552, 0xf6f90722),
         PCMCIA_DEVICE_PROD_ID12("corega", "FEther PCC-TXF", 0x0a21501a, 0xa51564a2),
         PCMCIA_DEVICE_PROD_ID12("corega", "Ether CF-TD", 0x0a21501a, 0x6589340a),
+        PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega Ether CF-TD LAN Card", 0x5261440f, 0x8797663b),
         PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega EtherII PCC-T", 0x5261440f, 0xfa9d85bd),
         PCMCIA_DEVICE_PROD_ID12("corega K.K.", "corega EtherII PCC-TD", 0x5261440f, 0xc49bd73d),
         PCMCIA_DEVICE_PROD_ID12("Corega K.K.", "corega EtherII PCC-TD", 0xd4fdcbd8, 0xc49bd73d),
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 7670aac0e93f..a8445c72fc13 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -47,11 +47,11 @@ void phy_print_status(struct phy_device *phydev)
         pr_info("PHY: %s - Link is %s", dev_name(&phydev->dev),
                         phydev->link ? "Up" : "Down");
         if (phydev->link)
-                printk(" - %d/%s", phydev->speed,
+                printk(KERN_CONT " - %d/%s", phydev->speed,
                                 DUPLEX_FULL == phydev->duplex ?
                                 "Full" : "Half");
 
-        printk("\n");
+        printk(KERN_CONT "\n");
 }
 EXPORT_SYMBOL(phy_print_status);
 
diff --git a/drivers/net/ppp_async.c b/drivers/net/ppp_async.c
index 78d70a6481bf..a1b82c9c67d2 100644
--- a/drivers/net/ppp_async.c
+++ b/drivers/net/ppp_async.c
@@ -32,6 +32,7 @@
 #include <linux/init.h>
 #include <linux/jiffies.h>
 #include <linux/slab.h>
+#include <asm/unaligned.h>
 #include <asm/uaccess.h>
 #include <asm/string.h>
 
@@ -542,7 +543,7 @@ ppp_async_encode(struct asyncppp *ap)
         data = ap->tpkt->data;
         count = ap->tpkt->len;
         fcs = ap->tfcs;
-        proto = (data[0] << 8) + data[1];
+        proto = get_unaligned_be16(data);
 
         /*
          * LCP packets with code values between 1 (configure-reqest)
@@ -963,7 +964,7 @@ static void async_lcp_peek(struct asyncppp *ap, unsigned char *data,
         code = data[0];
         if (code != CONFACK && code != CONFREQ)
                 return;
-        dlen = (data[2] << 8) + data[3];
+        dlen = get_unaligned_be16(data + 2);
         if (len < dlen)
                 return;         /* packet got truncated or length is bogus */
 
@@ -997,15 +998,14 @@ static void async_lcp_peek(struct asyncppp *ap, unsigned char *data,
         while (dlen >= 2 && dlen >= data[1] && data[1] >= 2) {
                 switch (data[0]) {
                 case LCP_MRU:
-                        val = (data[2] << 8) + data[3];
+                        val = get_unaligned_be16(data + 2);
                         if (inbound)
                                 ap->mru = val;
                         else
                                 ap->chan.mtu = val;
                         break;
                 case LCP_ASYNCMAP:
-                        val = (data[2] << 24) + (data[3] << 16)
-                                + (data[4] << 8) + data[5];
+                        val = get_unaligned_be32(data + 2);
                         if (inbound)
                                 ap->raccm = val;
                         else
diff --git a/drivers/net/ppp_deflate.c b/drivers/net/ppp_deflate.c
index 695bc83e0cfd..43583309a65d 100644
--- a/drivers/net/ppp_deflate.c
+++ b/drivers/net/ppp_deflate.c
@@ -41,6 +41,7 @@
 #include <linux/ppp-comp.h>
 
 #include <linux/zlib.h>
+#include <asm/unaligned.h>
 
 /*
  * State for a Deflate (de)compressor.
@@ -232,11 +233,9 @@ static int z_compress(void *arg, unsigned char *rptr, unsigned char *obuf,
          */
         wptr[0] = PPP_ADDRESS(rptr);
         wptr[1] = PPP_CONTROL(rptr);
-        wptr[2] = PPP_COMP >> 8;
-        wptr[3] = PPP_COMP;
+        put_unaligned_be16(PPP_COMP, wptr + 2);
         wptr += PPP_HDRLEN;
-        wptr[0] = state->seqno >> 8;
-        wptr[1] = state->seqno;
+        put_unaligned_be16(state->seqno, wptr);
         wptr += DEFLATE_OVHD;
         olen = PPP_HDRLEN + DEFLATE_OVHD;
         state->strm.next_out = wptr;
@@ -451,7 +450,7 @@ static int z_decompress(void *arg, unsigned char *ibuf, int isize,
         }
 
         /* Check the sequence number. */
-        seq = (ibuf[PPP_HDRLEN] << 8) + ibuf[PPP_HDRLEN+1];
+        seq = get_unaligned_be16(ibuf + PPP_HDRLEN);
         if (seq != (state->seqno & 0xffff)) {
                 if (state->debug)
                         printk(KERN_DEBUG "z_decompress%d: bad seq # %d, expected %d\n",
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c
index 39659976a1ac..c7a6c4466978 100644
--- a/drivers/net/ppp_generic.c
+++ b/drivers/net/ppp_generic.c
@@ -46,6 +46,7 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
+#include <asm/unaligned.h>
 #include <net/slhc_vj.h>
 #include <asm/atomic.h>
 
@@ -210,7 +211,7 @@ struct ppp_net {
 };
 
 /* Get the PPP protocol number from a skb */
-#define PPP_PROTO(skb)  (((skb)->data[0] << 8) + (skb)->data[1])
+#define PPP_PROTO(skb)  get_unaligned_be16((skb)->data)
 
 /* We limit the length of ppp->file.rq to this (arbitrary) value */
 #define PPP_MAX_RQLEN   32
@@ -964,8 +965,7 @@ ppp_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         pp = skb_push(skb, 2);
         proto = npindex_to_proto[npi];
-        pp[0] = proto >> 8;
-        pp[1] = proto;
+        put_unaligned_be16(proto, pp);
 
         netif_stop_queue(dev);
         skb_queue_tail(&ppp->file.xq, skb);
@@ -1136,8 +1136,7 @@ ppp_send_frame(struct ppp *ppp, struct sk_buff *skb)
                    a four-byte PPP header on each packet */
                 *skb_push(skb, 2) = 1;
                 if (ppp->pass_filter &&
-                    sk_run_filter(skb, ppp->pass_filter,
-                                  ppp->pass_len) == 0) {
+                    sk_run_filter(skb, ppp->pass_filter) == 0) {
                         if (ppp->debug & 1)
                                 printk(KERN_DEBUG "PPP: outbound frame not passed\n");
                         kfree_skb(skb);
@@ -1145,8 +1144,7 @@ ppp_send_frame(struct ppp *ppp, struct sk_buff *skb)
                 }
                 /* if this packet passes the active filter, record the time */
                 if (!(ppp->active_filter &&
-                      sk_run_filter(skb, ppp->active_filter,
-                                    ppp->active_len) == 0))
+                      sk_run_filter(skb, ppp->active_filter) == 0))
                         ppp->last_xmit = jiffies;
                 skb_pull(skb, 2);
 #else
@@ -1285,6 +1283,11 @@ ppp_push(struct ppp *ppp)
 }
 
 #ifdef CONFIG_PPP_MULTILINK
+static bool mp_protocol_compress __read_mostly = true;
+module_param(mp_protocol_compress, bool, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(mp_protocol_compress,
+                 "compress protocol id in multilink fragments");
+
 /*
  * Divide a packet to be transmitted into fragments and
  * send them out the individual links.
@@ -1347,10 +1350,10 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
         if (nfree == 0 || nfree < navail / 2)
                 return 0; /* can't take now, leave it in xmit_pending */
 
-        /* Do protocol field compression (XXX this should be optional) */
+        /* Do protocol field compression */
         p = skb->data;
         len = skb->len;
-        if (*p == 0) {
+        if (*p == 0 && mp_protocol_compress) {
                 ++p;
                 --len;
         }
@@ -1470,8 +1473,7 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb)
                 q = skb_put(frag, flen + hdrlen);
 
                 /* make the MP header */
-                q[0] = PPP_MP >> 8;
-                q[1] = PPP_MP;
+                put_unaligned_be16(PPP_MP, q);
                 if (ppp->flags & SC_MP_XSHORTSEQ) {
                         q[2] = bits + ((ppp->nxseq >> 8) & 0xf);
                         q[3] = ppp->nxseq;
@@ -1758,8 +1760,7 @@ ppp_receive_nonmp_frame(struct ppp *ppp, struct sk_buff *skb)
 
                         *skb_push(skb, 2) = 0;
                         if (ppp->pass_filter &&
-                            sk_run_filter(skb, ppp->pass_filter,
-                                          ppp->pass_len) == 0) {
+                            sk_run_filter(skb, ppp->pass_filter) == 0) {
                                 if (ppp->debug & 1)
                                         printk(KERN_DEBUG "PPP: inbound frame "
                                                "not passed\n");
@@ -1767,8 +1768,7 @@ ppp_receive_nonmp_frame(struct ppp *ppp, struct sk_buff *skb)
                                 return;
                         }
                         if (!(ppp->active_filter &&
-                              sk_run_filter(skb, ppp->active_filter,
-                                            ppp->active_len) == 0))
+                              sk_run_filter(skb, ppp->active_filter) == 0))
                                 ppp->last_recv = jiffies;
                         __skb_pull(skb, 2);
                 } else
diff --git a/drivers/net/ppp_mppe.c b/drivers/net/ppp_mppe.c
index 6d1a1b80cc3e..9a1849a83e2a 100644
--- a/drivers/net/ppp_mppe.c
+++ b/drivers/net/ppp_mppe.c
@@ -55,6 +55,7 @@
 #include <linux/ppp_defs.h>
 #include <linux/ppp-comp.h>
 #include <linux/scatterlist.h>
+#include <asm/unaligned.h>
 
 #include "ppp_mppe.h"
 
@@ -395,16 +396,14 @@ mppe_compress(void *arg, unsigned char *ibuf, unsigned char *obuf,
          */
         obuf[0] = PPP_ADDRESS(ibuf);
         obuf[1] = PPP_CONTROL(ibuf);
-        obuf[2] = PPP_COMP >> 8;        /* isize + MPPE_OVHD + 1 */
-        obuf[3] = PPP_COMP;     /* isize + MPPE_OVHD + 2 */
+        put_unaligned_be16(PPP_COMP, obuf + 2);
         obuf += PPP_HDRLEN;
 
         state->ccount = (state->ccount + 1) % MPPE_CCOUNT_SPACE;
         if (state->debug >= 7)
                 printk(KERN_DEBUG "mppe_compress[%d]: ccount %d\n", state->unit,
                        state->ccount);
-        obuf[0] = state->ccount >> 8;
-        obuf[1] = state->ccount & 0xff;
+        put_unaligned_be16(state->ccount, obuf);
 
         if (!state->stateful || /* stateless mode     */
             ((state->ccount & 0xff) == 0xff) || /* "flag" packet      */
diff --git a/drivers/net/ppp_synctty.c b/drivers/net/ppp_synctty.c
index 4c95ec3fb8d4..4e6b72f57de8 100644
--- a/drivers/net/ppp_synctty.c
+++ b/drivers/net/ppp_synctty.c
@@ -45,6 +45,7 @@
 #include <linux/completion.h>
 #include <linux/init.h>
 #include <linux/slab.h>
+#include <asm/unaligned.h>
 #include <asm/uaccess.h>
 
 #define PPP_VERSION     "2.4.2"
@@ -563,7 +564,7 @@ ppp_sync_txmunge(struct syncppp *ap, struct sk_buff *skb)
         int islcp;
 
         data  = skb->data;
-        proto = (data[0] << 8) + data[1];
+        proto = get_unaligned_be16(data);
 
         /* LCP packets with codes between 1 (configure-request)
          * and 7 (code-reject) must be sent as though no options
diff --git a/drivers/net/pptp.c b/drivers/net/pptp.c
index ccbc91326bfa..164cfad6ce79 100644
--- a/drivers/net/pptp.c
+++ b/drivers/net/pptp.c
@@ -277,7 +277,7 @@ static int pptp_xmit(struct ppp_channel *chan, struct sk_buff *skb)
         iph->tos      = 0;
         iph->daddr    = rt->rt_dst;
         iph->saddr    = rt->rt_src;
-        iph->ttl      = dst_metric(&rt->dst, RTAX_HOPLIMIT);
+        iph->ttl      = ip4_dst_hoplimit(&rt->dst);
         iph->tot_len  = htons(skb->len);
 
         skb_dst_drop(skb);
@@ -673,8 +673,7 @@ static int __init pptp_init_module(void)
         int err = 0;
         pr_info("PPTP driver version " PPTP_DRIVER_VERSION "\n");
 
-        callid_sock = __vmalloc((MAX_CALLID + 1) * sizeof(void *),
-                GFP_KERNEL | __GFP_ZERO, PAGE_KERNEL);
+        callid_sock = vzalloc((MAX_CALLID + 1) * sizeof(void *));
         if (!callid_sock) {
                 pr_err("PPTP: cann't allocate memory\n");
                 return -ENOMEM;
diff --git a/drivers/net/pxa168_eth.c b/drivers/net/pxa168_eth.c
index 18c0297743f1..1b63c8aef121 100644
--- a/drivers/net/pxa168_eth.c
+++ b/drivers/net/pxa168_eth.c
@@ -1450,16 +1450,11 @@ static void pxa168_get_drvinfo(struct net_device *dev,
         strncpy(info->bus_info, "N/A", 32);
 }
 
-static u32 pxa168_get_link(struct net_device *dev)
-{
-        return !!netif_carrier_ok(dev);
-}
-
 static const struct ethtool_ops pxa168_ethtool_ops = {
         .get_settings = pxa168_get_settings,
         .set_settings = pxa168_set_settings,
         .get_drvinfo = pxa168_get_drvinfo,
-        .get_link = pxa168_get_link,
+        .get_link = ethtool_op_get_link,
 };
 
 static const struct net_device_ops pxa168_eth_netdev_ops = {
@@ -1607,7 +1602,7 @@ static int pxa168_eth_remove(struct platform_device *pdev)
         mdiobus_unregister(pep->smi_bus);
         mdiobus_free(pep->smi_bus);
         unregister_netdev(dev);
-        flush_scheduled_work();
+        cancel_work_sync(&pep->tx_timeout_task);
         free_netdev(dev);
         platform_set_drvdata(pdev, NULL);
         return 0;
diff --git a/drivers/net/qla3xxx.c b/drivers/net/qla3xxx.c
index 7496ed2c34ab..1a3584edd79c 100644
--- a/drivers/net/qla3xxx.c
+++ b/drivers/net/qla3xxx.c
@@ -2467,7 +2467,7 @@ map_error:
 static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
                                struct net_device *ndev)
 {
-        struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
+        struct ql3_adapter *qdev = netdev_priv(ndev);
         struct ql3xxx_port_registers __iomem *port_regs =
                         qdev->mem_map_registers;
         struct ql_tx_buf_cb *tx_cb;
@@ -3390,7 +3390,7 @@ static void ql_set_mac_info(struct ql3_adapter *qdev)
 
 static void ql_display_dev_info(struct net_device *ndev)
 {
-        struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
+        struct ql3_adapter *qdev = netdev_priv(ndev);
         struct pci_dev *pdev = qdev->pdev;
 
         netdev_info(ndev,
@@ -3573,7 +3573,7 @@ static int ql3xxx_open(struct net_device *ndev)
 
 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
 {
-        struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
+        struct ql3_adapter *qdev = netdev_priv(ndev);
         struct ql3xxx_port_registers __iomem *port_regs =
                         qdev->mem_map_registers;
         struct sockaddr *addr = p;
@@ -3608,7 +3608,7 @@ static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
 
 static void ql3xxx_tx_timeout(struct net_device *ndev)
 {
-        struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
+        struct ql3_adapter *qdev = netdev_priv(ndev);
 
         netdev_err(ndev, "Resetting...\n");
         /*
diff --git a/drivers/net/qlcnic/qlcnic.h b/drivers/net/qlcnic/qlcnic.h
index 8ecc170c9b74..44e316fd67b8 100644
--- a/drivers/net/qlcnic/qlcnic.h
+++ b/drivers/net/qlcnic/qlcnic.h
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #ifndef _QLCNIC_H_
@@ -51,8 +34,8 @@
 
 #define _QLCNIC_LINUX_MAJOR 5
 #define _QLCNIC_LINUX_MINOR 0
-#define _QLCNIC_LINUX_SUBVERSION 11
-#define QLCNIC_LINUX_VERSIONID  "5.0.11"
+#define _QLCNIC_LINUX_SUBVERSION 15
+#define QLCNIC_LINUX_VERSIONID  "5.0.15"
 #define QLCNIC_DRV_IDC_VER  0x01
 #define QLCNIC_DRIVER_VERSION  ((_QLCNIC_LINUX_MAJOR << 16) |\
                  (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
@@ -306,6 +289,26 @@ struct uni_data_desc{
         u32     reserved[5];
 };
 
+/* Flash Defines and Structures */
+#define QLCNIC_FLT_LOCATION     0x3F1000
+#define QLCNIC_FW_IMAGE_REGION  0x74
+struct qlcnic_flt_header {
+        u16 version;
+        u16 len;
+        u16 checksum;
+        u16 reserved;
+};
+
+struct qlcnic_flt_entry {
+        u8 region;
+        u8 reserved0;
+        u8 attrib;
+        u8 reserved1;
+        u32 size;
+        u32 start_addr;
+        u32 end_add;
+};
+
 /* Magic number to let user know flash is programmed */
 #define QLCNIC_BDINFO_MAGIC 0x12345678
 
@@ -798,7 +801,6 @@ struct qlcnic_nic_intr_coalesce {
 #define QLCNIC_H2C_OPCODE_GET_NET_STATS                 16
 #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V              17
 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR                 18
-#define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK               19
 #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE               20
 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT                 21
 #define QLCNIC_C2C_OPCODE                               22
@@ -923,6 +925,7 @@ struct qlcnic_ipaddr {
 #define QLCNIC_MACSPOOF                 0x200
 #define QLCNIC_MAC_OVERRIDE_DISABLED    0x400
 #define QLCNIC_PROMISC_DISABLED         0x800
+#define QLCNIC_NEED_FLR                 0x1000
 #define QLCNIC_IS_MSI_FAMILY(adapter) \
         ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
 
@@ -942,6 +945,7 @@ struct qlcnic_ipaddr {
 
 #define QLCNIC_INTERRUPT_TEST           1
 #define QLCNIC_LOOPBACK_TEST            2
+#define QLCNIC_LED_TEST         3
 
 #define QLCNIC_FILTER_AGE       80
 #define QLCNIC_READD_AGE        20
@@ -1126,8 +1130,7 @@ struct qlcnic_eswitch {
 /* Return codes for Error handling */
 #define QL_STATUS_INVALID_PARAM -1
 
-#define MAX_BW                  100
-#define MIN_BW                  1
+#define MAX_BW                  100     /* % of link speed */
 #define MAX_VLAN_ID             4095
 #define MIN_VLAN_ID             2
 #define MAX_TX_QUEUES           1
@@ -1135,7 +1138,7 @@ struct qlcnic_eswitch {
 #define DEFAULT_MAC_LEARN       1
 
 #define IS_VALID_VLAN(vlan)     (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
-#define IS_VALID_BW(bw)         (bw >= MIN_BW && bw <= MAX_BW)
+#define IS_VALID_BW(bw)         (bw <= MAX_BW)
 #define IS_VALID_TX_QUEUES(que) (que > 0 && que <= MAX_TX_QUEUES)
 #define IS_VALID_RX_QUEUES(que) (que > 0 && que <= MAX_RX_QUEUES)
 
@@ -1314,21 +1317,15 @@ int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
                 struct qlcnic_host_tx_ring *tx_ring);
-void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter);
-int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter);
 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
 
 /* Functions from qlcnic_main.c */
-int qlcnic_request_quiscent_mode(struct qlcnic_adapter *adapter);
-void qlcnic_clear_quiscent_mode(struct qlcnic_adapter *adapter);
 int qlcnic_reset_context(struct qlcnic_adapter *);
 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
         u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
-int qlcnic_check_loopback_buff(unsigned char *data);
 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
-void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring);
 
 /* Management functions */
 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
@@ -1377,6 +1374,8 @@ static const struct qlcnic_brdinfo qlcnic_boards[] = {
                 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
         {0x1077, 0x8020, 0x103c, 0x3733,
                 "NC523SFP 10Gb 2-port Server Adapter"},
+        {0x1077, 0x8020, 0x103c, 0x3346,
+                "CN1000Q Dual Port Converged Network Adapter"},
         {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
 };
 
diff --git a/drivers/net/qlcnic/qlcnic_ctx.c b/drivers/net/qlcnic/qlcnic_ctx.c
index 1cdc05dade6b..27631f23b3fd 100644
--- a/drivers/net/qlcnic/qlcnic_ctx.c
+++ b/drivers/net/qlcnic/qlcnic_ctx.c
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #include "qlcnic.h"
@@ -480,6 +463,11 @@ int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter)
 {
         int err;
 
+        if (adapter->flags & QLCNIC_NEED_FLR) {
+                pci_reset_function(adapter->pdev);
+                adapter->flags &= ~QLCNIC_NEED_FLR;
+        }
+
         err = qlcnic_fw_cmd_create_rx_ctx(adapter);
         if (err)
                 return err;
diff --git a/drivers/net/qlcnic/qlcnic_ethtool.c b/drivers/net/qlcnic/qlcnic_ethtool.c
index ec21d24015c4..4c14510e2a87 100644
--- a/drivers/net/qlcnic/qlcnic_ethtool.c
+++ b/drivers/net/qlcnic/qlcnic_ethtool.c
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #include <linux/types.h>
@@ -101,8 +84,7 @@ static const char qlcnic_device_gstrings_stats[][ETH_GSTRING_LEN] = {
 static const char qlcnic_gstrings_test[][ETH_GSTRING_LEN] = {
         "Register_Test_on_offline",
         "Link_Test_on_offline",
-        "Interrupt_Test_offline",
-        "Loopback_Test_offline"
+        "Interrupt_Test_offline"
 };
 
 #define QLCNIC_TEST_LEN ARRAY_SIZE(qlcnic_gstrings_test)
@@ -643,104 +625,6 @@ static int qlcnic_get_sset_count(struct net_device *dev, int sset)
         }
 }
 
-#define QLC_ILB_PKT_SIZE 64
-#define QLC_NUM_ILB_PKT 16
-#define QLC_ILB_MAX_RCV_LOOP 10
-
-static void qlcnic_create_loopback_buff(unsigned char *data)
-{
-        unsigned char random_data[] = {0xa8, 0x06, 0x45, 0x00};
-        memset(data, 0x4e, QLC_ILB_PKT_SIZE);
-        memset(data, 0xff, 12);
-        memcpy(data + 12, random_data, sizeof(random_data));
-}
-
-int qlcnic_check_loopback_buff(unsigned char *data)
-{
-        unsigned char buff[QLC_ILB_PKT_SIZE];
-        qlcnic_create_loopback_buff(buff);
-        return memcmp(data, buff, QLC_ILB_PKT_SIZE);
-}
-
-static int qlcnic_do_ilb_test(struct qlcnic_adapter *adapter)
-{
-        struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
-        struct qlcnic_host_sds_ring *sds_ring = &recv_ctx->sds_rings[0];
-        struct sk_buff *skb;
-        int i, loop, cnt = 0;
-
-        for (i = 0; i < QLC_NUM_ILB_PKT; i++) {
-                skb = dev_alloc_skb(QLC_ILB_PKT_SIZE);
-                qlcnic_create_loopback_buff(skb->data);
-                skb_put(skb, QLC_ILB_PKT_SIZE);
-
-                adapter->diag_cnt = 0;
-                qlcnic_xmit_frame(skb, adapter->netdev);
-
-                loop = 0;
-                do {
-                        msleep(1);
-                        qlcnic_process_rcv_ring_diag(sds_ring);
-                } while (loop++ < QLC_ILB_MAX_RCV_LOOP &&
-                         !adapter->diag_cnt);
-
-                dev_kfree_skb_any(skb);
-
-                if (!adapter->diag_cnt)
-                        dev_warn(&adapter->pdev->dev, "ILB Test: %dth packet"
-                                " not recevied\n", i + 1);
-                else
-                        cnt++;
-        }
-        if (cnt != i) {
-                dev_warn(&adapter->pdev->dev, "ILB Test failed\n");
-                return -1;
-        }
-        return 0;
-}
-
-static int qlcnic_loopback_test(struct net_device *netdev)
-{
-        struct qlcnic_adapter *adapter = netdev_priv(netdev);
-        int max_sds_rings = adapter->max_sds_rings;
-        int ret;
-
-        if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC) {
-                dev_warn(&adapter->pdev->dev, "Loopback test not supported"
-                                "for non privilege function\n");
-                return 0;
-        }
-
-        if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
-                return -EIO;
-
-        if (qlcnic_request_quiscent_mode(adapter)) {
-                clear_bit(__QLCNIC_RESETTING, &adapter->state);
-                return -EIO;
-        }
-
-        ret = qlcnic_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST);
-        if (ret)
-                goto clear_it;
-
-        ret = qlcnic_set_ilb_mode(adapter);
-        if (ret)
-                goto done;
-
-        ret = qlcnic_do_ilb_test(adapter);
-
-        qlcnic_clear_ilb_mode(adapter);
-
-done:
-        qlcnic_diag_free_res(netdev, max_sds_rings);
-
-clear_it:
-        qlcnic_clear_quiscent_mode(adapter);
-        adapter->max_sds_rings = max_sds_rings;
-        clear_bit(__QLCNIC_RESETTING, &adapter->state);
-        return ret;
-}
-
 static int qlcnic_irq_test(struct net_device *netdev)
 {
         struct qlcnic_adapter *adapter = netdev_priv(netdev);
@@ -788,14 +672,11 @@ qlcnic_diag_test(struct net_device *dev, struct ethtool_test *eth_test,
         if (data[1])
                 eth_test->flags |= ETH_TEST_FL_FAILED;
 
-        if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
+        if (eth_test->flags & ETH_TEST_FL_OFFLINE) {
                 data[2] = qlcnic_irq_test(dev);
                 if (data[2])
                         eth_test->flags |= ETH_TEST_FL_FAILED;
 
-                data[3] = qlcnic_loopback_test(dev);
-                if (data[3])
-                        eth_test->flags |= ETH_TEST_FL_FAILED;
 
         }
 }
@@ -925,9 +806,10 @@ static int qlcnic_set_rx_csum(struct net_device *dev, u32 data)
 
                 dev->features &= ~NETIF_F_LRO;
                 qlcnic_send_lro_cleanup(adapter);
+                dev_info(&adapter->pdev->dev,
+                                        "disabling LRO as rx_csum is off\n");
         }
         adapter->rx_csum = !!data;
-        dev_info(&adapter->pdev->dev, "disabling LRO as rx_csum is off\n");
         return 0;
 }
 
@@ -952,16 +834,27 @@ static int qlcnic_set_tso(struct net_device *dev, u32 data)
 static int qlcnic_blink_led(struct net_device *dev, u32 val)
 {
         struct qlcnic_adapter *adapter = netdev_priv(dev);
+        int max_sds_rings = adapter->max_sds_rings;
+        int dev_down = 0;
         int ret;
 
-        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state))
-                return -EIO;
+        if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
+                dev_down = 1;
+                if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
+                        return -EIO;
+
+                ret = qlcnic_diag_alloc_res(dev, QLCNIC_LED_TEST);
+                if (ret) {
+                        clear_bit(__QLCNIC_RESETTING, &adapter->state);
+                        return ret;
+                }
+        }
 
         ret = adapter->nic_ops->config_led(adapter, 1, 0xf);
         if (ret) {
                 dev_err(&adapter->pdev->dev,
                         "Failed to set LED blink state.\n");
-                return ret;
+                goto done;
         }
 
         msleep_interruptible(val * 1000);
@@ -970,10 +863,16 @@ static int qlcnic_blink_led(struct net_device *dev, u32 val)
         if (ret) {
                 dev_err(&adapter->pdev->dev,
                         "Failed to reset LED blink state.\n");
-                return ret;
+                goto done;
         }
 
-        return 0;
+done:
+        if (dev_down) {
+                qlcnic_diag_free_res(dev, max_sds_rings);
+                clear_bit(__QLCNIC_RESETTING, &adapter->state);
+        }
+        return ret;
+
 }
 
 static void
diff --git a/drivers/net/qlcnic/qlcnic_hdr.h b/drivers/net/qlcnic/qlcnic_hdr.h
index 4290b80cde1a..726ef555b6bc 100644
--- a/drivers/net/qlcnic/qlcnic_hdr.h
+++ b/drivers/net/qlcnic/qlcnic_hdr.h
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #ifndef __QLCNIC_HDR_H_
@@ -638,7 +621,7 @@ enum {
 #define PCIX_INT_MASK           (0x10104)
 
 #define PCIX_OCM_WINDOW         (0x10800)
-#define PCIX_OCM_WINDOW_REG(func)       (PCIX_OCM_WINDOW + 0x20 * (func))
+#define PCIX_OCM_WINDOW_REG(func)       (PCIX_OCM_WINDOW + 0x4 * (func))
 
 #define PCIX_TARGET_STATUS      (0x10118)
 #define PCIX_TARGET_STATUS_F1   (0x10160)
@@ -722,7 +705,7 @@ enum {
 #define QLCNIC_DEV_NPAR_OPER            1 /* NPAR Operational */
 #define QLCNIC_DEV_NPAR_OPER_TIMEO      30 /* Operational time out */
 
-#define QLC_DEV_CHECK_ACTIVE(VAL, FN)           ((VAL) &= (1 << (FN * 4)))
+#define QLC_DEV_CHECK_ACTIVE(VAL, FN)           ((VAL) & (1 << (FN * 4)))
 #define QLC_DEV_SET_REF_CNT(VAL, FN)            ((VAL) |= (1 << (FN * 4)))
 #define QLC_DEV_CLR_REF_CNT(VAL, FN)            ((VAL) &= ~(1 << (FN * 4)))
 #define QLC_DEV_SET_RST_RDY(VAL, FN)            ((VAL) |= (1 << (FN * 4)))
diff --git a/drivers/net/qlcnic/qlcnic_hw.c b/drivers/net/qlcnic/qlcnic_hw.c
index 7a47a2a7ee27..616940f0a8d0 100644
--- a/drivers/net/qlcnic/qlcnic_hw.c
+++ b/drivers/net/qlcnic/qlcnic_hw.c
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #include "qlcnic.h"
@@ -398,7 +381,7 @@ qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 }
 
-static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
+static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 {
         struct list_head *head;
         struct qlcnic_mac_list_s *cur;
@@ -432,7 +415,9 @@ void qlcnic_set_multi(struct net_device *netdev)
 {
         struct qlcnic_adapter *adapter = netdev_priv(netdev);
         struct netdev_hw_addr *ha;
-        u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+        static const u8 bcast_addr[ETH_ALEN] = {
+                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+        };
         u32 mode = VPORT_MISS_MODE_DROP;
 
         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
@@ -638,10 +623,11 @@ int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
         u64 word;
         int i, rv;
 
-        const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
-                        0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
-                        0x255b0ec26d5a56daULL };
-
+        static const u64 key[] = {
+                0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
+                0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
+                0x255b0ec26d5a56daULL
+        };
 
         memset(&req, 0, sizeof(struct qlcnic_nic_req));
         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
@@ -1234,56 +1220,3 @@ int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
 
         return rv;
 }
-
-static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
-{
-        struct qlcnic_nic_req   req;
-        int                     rv;
-        u64                     word;
-
-        memset(&req, 0, sizeof(struct qlcnic_nic_req));
-        req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
-
-        word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
-                        ((u64)adapter->portnum << 16);
-        req.req_hdr = cpu_to_le64(word);
-        req.words[0] = cpu_to_le64(flag);
-
-        rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
-        if (rv)
-                dev_err(&adapter->pdev->dev,
-                        "%sting loopback mode failed.\n",
-                                        flag ? "Set" : "Reset");
-        return rv;
-}
-
-int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
-{
-        if (qlcnic_set_fw_loopback(adapter, 1))
-                return -EIO;
-
-        if (qlcnic_nic_set_promisc(adapter,
-                                VPORT_MISS_MODE_ACCEPT_ALL)) {
-                qlcnic_set_fw_loopback(adapter, 0);
-                return -EIO;
-        }
-
-        msleep(1000);
-        return 0;
-}
-
-void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
-{
-        int mode = VPORT_MISS_MODE_DROP;
-        struct net_device *netdev = adapter->netdev;
-
-        qlcnic_set_fw_loopback(adapter, 0);
-
-        if (netdev->flags & IFF_PROMISC)
-                mode = VPORT_MISS_MODE_ACCEPT_ALL;
-        else if (netdev->flags & IFF_ALLMULTI)
-                mode = VPORT_MISS_MODE_ACCEPT_MULTI;
-
-        qlcnic_nic_set_promisc(adapter, mode);
-        msleep(1000);
-}
diff --git a/drivers/net/qlcnic/qlcnic_init.c b/drivers/net/qlcnic/qlcnic_init.c
index 0d180c6e41fe..a7f1d5b7e811 100644
--- a/drivers/net/qlcnic/qlcnic_init.c
+++ b/drivers/net/qlcnic/qlcnic_init.c
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #include <linux/netdevice.h>
@@ -236,12 +219,11 @@ int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
         tx_ring->num_desc = adapter->num_txd;
         tx_ring->txq = netdev_get_tx_queue(netdev, 0);
 
-        cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
+        cmd_buf_arr = vzalloc(TX_BUFF_RINGSIZE(tx_ring));
         if (cmd_buf_arr == NULL) {
                 dev_err(&netdev->dev, "failed to allocate cmd buffer ring\n");
                 goto err_out;
         }
-        memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
         tx_ring->cmd_buf_arr = cmd_buf_arr;
 
         recv_ctx = &adapter->recv_ctx;
@@ -275,14 +257,12 @@ int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter)
                                 rds_ring->dma_size + NET_IP_ALIGN;
                         break;
                 }
-                rds_ring->rx_buf_arr = (struct qlcnic_rx_buffer *)
-                        vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
+                rds_ring->rx_buf_arr = vzalloc(RCV_BUFF_RINGSIZE(rds_ring));
                 if (rds_ring->rx_buf_arr == NULL) {
                         dev_err(&netdev->dev, "Failed to allocate "
                                 "rx buffer ring %d\n", ring);
                         goto err_out;
                 }
-                memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
                 INIT_LIST_HEAD(&rds_ring->free_list);
                 /*
                  * Now go through all of them, set reference handles
@@ -647,12 +627,73 @@ qlcnic_setup_idc_param(struct qlcnic_adapter *adapter) {
         return 0;
 }
 
+static int qlcnic_get_flt_entry(struct qlcnic_adapter *adapter, u8 region,
+                                struct qlcnic_flt_entry *region_entry)
+{
+        struct qlcnic_flt_header flt_hdr;
+        struct qlcnic_flt_entry *flt_entry;
+        int i = 0, ret;
+        u32 entry_size;
+
+        memset(region_entry, 0, sizeof(struct qlcnic_flt_entry));
+        ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION,
+                                         (u8 *)&flt_hdr,
+                                         sizeof(struct qlcnic_flt_header));
+        if (ret) {
+                dev_warn(&adapter->pdev->dev,
+                         "error reading flash layout header\n");
+                return -EIO;
+        }
+
+        entry_size = flt_hdr.len - sizeof(struct qlcnic_flt_header);
+        flt_entry = (struct qlcnic_flt_entry *)vzalloc(entry_size);
+        if (flt_entry == NULL) {
+                dev_warn(&adapter->pdev->dev, "error allocating memory\n");
+                return -EIO;
+        }
+
+        ret = qlcnic_rom_fast_read_words(adapter, QLCNIC_FLT_LOCATION +
+                                         sizeof(struct qlcnic_flt_header),
+                                         (u8 *)flt_entry, entry_size);
+        if (ret) {
+                dev_warn(&adapter->pdev->dev,
+                         "error reading flash layout entries\n");
+                goto err_out;
+        }
+
+        while (i < (entry_size/sizeof(struct qlcnic_flt_entry))) {
+                if (flt_entry[i].region == region)
+                        break;
+                i++;
+        }
+        if (i >= (entry_size/sizeof(struct qlcnic_flt_entry))) {
+                dev_warn(&adapter->pdev->dev,
+                         "region=%x not found in %d regions\n", region, i);
+                ret = -EIO;
+                goto err_out;
+        }
+        memcpy(region_entry, &flt_entry[i], sizeof(struct qlcnic_flt_entry));
+
+err_out:
+        vfree(flt_entry);
+        return ret;
+}
+
 int
 qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter)
 {
+        struct qlcnic_flt_entry fw_entry;
         u32 ver = -1, min_ver;
+        int ret;
 
-        qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET, (int *)&ver);
+        ret = qlcnic_get_flt_entry(adapter, QLCNIC_FW_IMAGE_REGION, &fw_entry);
+        if (!ret)
+                /* 0-4:-signature,  4-8:-fw version */
+                qlcnic_rom_fast_read(adapter, fw_entry.start_addr + 4,
+                                     (int *)&ver);
+        else
+                qlcnic_rom_fast_read(adapter, QLCNIC_FW_VERSION_OFFSET,
+                                     (int *)&ver);
 
         ver = QLCNIC_DECODE_VERSION(ver);
         min_ver = QLCNIC_MIN_FW_VERSION;
@@ -1693,99 +1734,6 @@ qlcnic_post_rx_buffers_nodb(struct qlcnic_adapter *adapter,
         spin_unlock(&rds_ring->lock);
 }
 
-static void dump_skb(struct sk_buff *skb)
-{
-        int i;
-        unsigned char *data = skb->data;
-
-        for (i = 0; i < skb->len; i++) {
-                printk("%02x ", data[i]);
-                if ((i & 0x0f) == 8)
-                        printk("\n");
-        }
-}
-
-static struct qlcnic_rx_buffer *
-qlcnic_process_rcv_diag(struct qlcnic_adapter *adapter,
-                struct qlcnic_host_sds_ring *sds_ring,
-                int ring, u64 sts_data0)
-{
-        struct qlcnic_recv_context *recv_ctx = &adapter->recv_ctx;
-        struct qlcnic_rx_buffer *buffer;
-        struct sk_buff *skb;
-        struct qlcnic_host_rds_ring *rds_ring;
-        int index, length, cksum, pkt_offset;
-
-        if (unlikely(ring >= adapter->max_rds_rings))
-                return NULL;
-
-        rds_ring = &recv_ctx->rds_rings[ring];
-
-        index = qlcnic_get_sts_refhandle(sts_data0);
-        if (unlikely(index >= rds_ring->num_desc))
-                return NULL;
-
-        buffer = &rds_ring->rx_buf_arr[index];
-
-        length = qlcnic_get_sts_totallength(sts_data0);
-        cksum  = qlcnic_get_sts_status(sts_data0);
-        pkt_offset = qlcnic_get_sts_pkt_offset(sts_data0);
-
-        skb = qlcnic_process_rxbuf(adapter, rds_ring, index, cksum);
-        if (!skb)
-                return buffer;
-
-        if (length > rds_ring->skb_size)
-                skb_put(skb, rds_ring->skb_size);
-        else
-                skb_put(skb, length);
-
-        if (pkt_offset)
-                skb_pull(skb, pkt_offset);
-
-        if (!qlcnic_check_loopback_buff(skb->data))
-                adapter->diag_cnt++;
-        else
-                dump_skb(skb);
-
-        dev_kfree_skb_any(skb);
-        adapter->stats.rx_pkts++;
-        adapter->stats.rxbytes += length;
-
-        return buffer;
-}
-
-void
-qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
-{
-        struct qlcnic_adapter *adapter = sds_ring->adapter;
-        struct status_desc *desc;
-        struct qlcnic_rx_buffer *rxbuf;
-        u64 sts_data0;
-
-        int opcode, ring, desc_cnt;
-        u32 consumer = sds_ring->consumer;
-
-        desc = &sds_ring->desc_head[consumer];
-        sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
-
-        if (!(sts_data0 & STATUS_OWNER_HOST))
-                return;
-
-        desc_cnt = qlcnic_get_sts_desc_cnt(sts_data0);
-        opcode = qlcnic_get_sts_opcode(sts_data0);
-
-        ring = qlcnic_get_sts_type(sts_data0);
-        rxbuf = qlcnic_process_rcv_diag(adapter, sds_ring,
-                                        ring, sts_data0);
-
-        desc->status_desc_data[0] = cpu_to_le64(STATUS_OWNER_PHANTOM);
-        consumer = get_next_index(consumer, sds_ring->num_desc);
-
-        sds_ring->consumer = consumer;
-        writel(consumer, sds_ring->crb_sts_consumer);
-}
-
 void
 qlcnic_fetch_mac(struct qlcnic_adapter *adapter, u32 off1, u32 off2,
                         u8 alt_mac, u8 *mac)
diff --git a/drivers/net/qlcnic/qlcnic_main.c b/drivers/net/qlcnic/qlcnic_main.c
index a3dcd04be22f..37c04b4fade3 100644
--- a/drivers/net/qlcnic/qlcnic_main.c
+++ b/drivers/net/qlcnic/qlcnic_main.c
@@ -1,25 +1,8 @@
 /*
- * Copyright (C) 2009 - QLogic Corporation.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
- * MA  02111-1307, USA.
- *
- * The full GNU General Public License is included in this distribution
- * in the file called "COPYING".
+ * QLogic qlcnic NIC Driver
+ * Copyright (c)  2009-2010 QLogic Corporation
  *
+ * See LICENSE.qlcnic for copyright and licensing details.
  */
 
 #include <linux/slab.h>
@@ -48,15 +31,15 @@ static const char qlcnic_driver_string[] = "QLogic 1/10 GbE "
 
 static struct workqueue_struct *qlcnic_wq;
 static int qlcnic_mac_learn;
-module_param(qlcnic_mac_learn, int, 0644);
+module_param(qlcnic_mac_learn, int, 0444);
 MODULE_PARM_DESC(qlcnic_mac_learn, "Mac Filter (0=disabled, 1=enabled)");
 
 static int use_msi = 1;
-module_param(use_msi, int, 0644);
+module_param(use_msi, int, 0444);
 MODULE_PARM_DESC(use_msi, "MSI interrupt (0=disabled, 1=enabled");
 
 static int use_msi_x = 1;
-module_param(use_msi_x, int, 0644);
+module_param(use_msi_x, int, 0444);
 MODULE_PARM_DESC(use_msi_x, "MSI-X interrupt (0=disabled, 1=enabled");
 
 static int auto_fw_reset = AUTO_FW_RESET_ENABLED;
@@ -64,11 +47,11 @@ module_param(auto_fw_reset, int, 0644);
 MODULE_PARM_DESC(auto_fw_reset, "Auto firmware reset (0=disabled, 1=enabled");
 
 static int load_fw_file;
-module_param(load_fw_file, int, 0644);
+module_param(load_fw_file, int, 0444);
 MODULE_PARM_DESC(load_fw_file, "Load firmware from (0=flash, 1=file");
 
 static int qlcnic_config_npars;
-module_param(qlcnic_config_npars, int, 0644);
+module_param(qlcnic_config_npars, int, 0444);
 MODULE_PARM_DESC(qlcnic_config_npars, "Configure NPARs (0=disabled, 1=enabled");
 
 static int __devinit qlcnic_probe(struct pci_dev *pdev,
@@ -1546,6 +1529,8 @@ qlcnic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (err)
                 goto err_out_iounmap;
 
+        adapter->flags |= QLCNIC_NEED_FLR;
+
         err = adapter->nic_ops->start_firmware(adapter);
         if (err) {
                 dev_err(&pdev->dev, "Loading fw failed.Please Reboot\n");
@@ -2854,61 +2839,6 @@ qlcnic_set_npar_non_operational(struct qlcnic_adapter *adapter)
         qlcnic_api_unlock(adapter);
 }
 
-/* Caller should held RESETTING bit.
- * This should be call in sync with qlcnic_request_quiscent_mode.
- */
-void qlcnic_clear_quiscent_mode(struct qlcnic_adapter *adapter)
-{
-        qlcnic_clr_drv_state(adapter);
-        qlcnic_api_lock(adapter);
-        QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_READY);
-        qlcnic_api_unlock(adapter);
-}
-
-/* Caller should held RESETTING bit.
- */
-int qlcnic_request_quiscent_mode(struct qlcnic_adapter *adapter)
-{
-        u8 timeo = adapter->dev_init_timeo / 2;
-        u32 state;
-
-        if (qlcnic_api_lock(adapter))
-                return -EIO;
-
-        state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
-        if (state != QLCNIC_DEV_READY)
-                return -EIO;
-
-        QLCWR32(adapter, QLCNIC_CRB_DEV_STATE, QLCNIC_DEV_NEED_QUISCENT);
-        qlcnic_api_unlock(adapter);
-        QLCDB(adapter, DRV, "NEED QUISCENT state set\n");
-        qlcnic_idc_debug_info(adapter, 0);
-
-        qlcnic_set_drv_state(adapter, QLCNIC_DEV_NEED_QUISCENT);
-
-        do {
-                msleep(2000);
-                state = QLCRD32(adapter, QLCNIC_CRB_DEV_STATE);
-                if (state == QLCNIC_DEV_QUISCENT)
-                        return 0;
-                if (!qlcnic_check_drv_state(adapter)) {
-                        if (qlcnic_api_lock(adapter))
-                                return -EIO;
-                        QLCWR32(adapter, QLCNIC_CRB_DEV_STATE,
-                                                        QLCNIC_DEV_QUISCENT);
-                        qlcnic_api_unlock(adapter);
-                        QLCDB(adapter, DRV, "QUISCENT mode set\n");
-                        return 0;
-                }
-        } while (--timeo);
-
-        dev_err(&adapter->pdev->dev, "Failed to quiesce device, DRV_STATE=%08x"
-                " DRV_ACTIVE=%08x\n", QLCRD32(adapter, QLCNIC_CRB_DRV_STATE),
-                QLCRD32(adapter, QLCNIC_CRB_DRV_ACTIVE));
-        qlcnic_clear_quiscent_mode(adapter);
-        return -EIO;
-}
-
 /*Transit to RESET state from READY state only */
 static void
 qlcnic_dev_request_reset(struct qlcnic_adapter *adapter)
@@ -3587,9 +3517,12 @@ validate_esw_config(struct qlcnic_adapter *adapter,
                 case QLCNIC_PORT_DEFAULTS:
                         if (QLC_DEV_GET_DRV(op_mode, pci_func) !=
                                                 QLCNIC_NON_PRIV_FUNC) {
-                                esw_cfg[i].mac_anti_spoof = 0;
-                                esw_cfg[i].mac_override = 1;
-                                esw_cfg[i].promisc_mode = 1;
+                                if (esw_cfg[i].mac_anti_spoof != 0)
+                                        return QL_STATUS_INVALID_PARAM;
+                                if (esw_cfg[i].mac_override != 1)
+                                        return QL_STATUS_INVALID_PARAM;
+                                if (esw_cfg[i].promisc_mode != 1)
+                                        return QL_STATUS_INVALID_PARAM;
                         }
                         break;
                 case QLCNIC_ADD_VLAN:
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h
index 9787dff90d3f..4757c59a07a2 100644
--- a/drivers/net/qlge/qlge.h
+++ b/drivers/net/qlge/qlge.h
@@ -16,7 +16,7 @@
  */
 #define DRV_NAME        "qlge"
 #define DRV_STRING      "QLogic 10 Gigabit PCI-E Ethernet Driver "
-#define DRV_VERSION     "v1.00.00.25.00.00-01"
+#define DRV_VERSION     "v1.00.00.27.00.00-01"
 
 #define WQ_ADDR_ALIGN   0x3     /* 4 byte alignment */
 
@@ -2222,6 +2222,7 @@ int ql_write_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 data);
 int ql_unpause_mpi_risc(struct ql_adapter *qdev);
 int ql_pause_mpi_risc(struct ql_adapter *qdev);
 int ql_hard_reset_mpi_risc(struct ql_adapter *qdev);
+int ql_soft_reset_mpi_risc(struct ql_adapter *qdev);
 int ql_dump_risc_ram_area(struct ql_adapter *qdev, void *buf,
                 u32 ram_addr, int word_count);
 int ql_core_dump(struct ql_adapter *qdev,
@@ -2237,6 +2238,7 @@ int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
 int ql_mb_get_port_cfg(struct ql_adapter *qdev);
 int ql_mb_set_port_cfg(struct ql_adapter *qdev);
 int ql_wait_fifo_empty(struct ql_adapter *qdev);
+void ql_get_dump(struct ql_adapter *qdev, void *buff);
 void ql_gen_reg_dump(struct ql_adapter *qdev,
                         struct ql_reg_dump *mpi_coredump);
 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev);
diff --git a/drivers/net/qlge/qlge_dbg.c b/drivers/net/qlge/qlge_dbg.c
index 4747492935ef..fca804f36d61 100644
--- a/drivers/net/qlge/qlge_dbg.c
+++ b/drivers/net/qlge/qlge_dbg.c
@@ -1317,9 +1317,28 @@ void ql_gen_reg_dump(struct ql_adapter *qdev,
         status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
         if (status)
                 return;
+}
+
+void ql_get_dump(struct ql_adapter *qdev, void *buff)
+{
+        /*
+         * If the dump has already been taken and is stored
+         * in our internal buffer and if force dump is set then
+         * just start the spool to dump it to the log file
+         * and also, take a snapshot of the general regs to
+         * to the user's buffer or else take complete dump
+         * to the user's buffer if force is not set.
+         */
 
-        if (test_bit(QL_FRC_COREDUMP, &qdev->flags))
+        if (!test_bit(QL_FRC_COREDUMP, &qdev->flags)) {
+                if (!ql_core_dump(qdev, buff))
+                        ql_soft_reset_mpi_risc(qdev);
+                else
+                        netif_err(qdev, drv, qdev->ndev, "coredump failed!\n");
+        } else {
+                ql_gen_reg_dump(qdev, buff);
                 ql_get_core_dump(qdev);
+        }
 }
 
 /* Coredump to messages log file using separate worker thread */
diff --git a/drivers/net/qlge/qlge_ethtool.c b/drivers/net/qlge/qlge_ethtool.c
index 4892d64f4e05..8149cc9de4ca 100644
--- a/drivers/net/qlge/qlge_ethtool.c
+++ b/drivers/net/qlge/qlge_ethtool.c
@@ -375,7 +375,10 @@ static void ql_get_drvinfo(struct net_device *ndev,
         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
         drvinfo->n_stats = 0;
         drvinfo->testinfo_len = 0;
-        drvinfo->regdump_len = 0;
+        if (!test_bit(QL_FRC_COREDUMP, &qdev->flags))
+                drvinfo->regdump_len = sizeof(struct ql_mpi_coredump);
+        else
+                drvinfo->regdump_len = sizeof(struct ql_reg_dump);
         drvinfo->eedump_len = 0;
 }
 
@@ -547,7 +550,12 @@ static void ql_self_test(struct net_device *ndev,
 
 static int ql_get_regs_len(struct net_device *ndev)
 {
-        return sizeof(struct ql_reg_dump);
+        struct ql_adapter *qdev = netdev_priv(ndev);
+
+        if (!test_bit(QL_FRC_COREDUMP, &qdev->flags))
+                return sizeof(struct ql_mpi_coredump);
+        else
+                return sizeof(struct ql_reg_dump);
 }
 
 static void ql_get_regs(struct net_device *ndev,
@@ -555,7 +563,12 @@ static void ql_get_regs(struct net_device *ndev,
 {
         struct ql_adapter *qdev = netdev_priv(ndev);
 
-        ql_gen_reg_dump(qdev, p);
+        ql_get_dump(qdev, p);
+        qdev->core_is_dumped = 0;
+        if (!test_bit(QL_FRC_COREDUMP, &qdev->flags))
+                regs->len = sizeof(struct ql_mpi_coredump);
+        else
+                regs->len = sizeof(struct ql_reg_dump);
 }
 
 static int ql_get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c
index 2555b1d34f34..49bfa5813068 100644
--- a/drivers/net/qlge/qlge_main.c
+++ b/drivers/net/qlge/qlge_main.c
@@ -3548,12 +3548,13 @@ err_irq:
 
 static int ql_start_rss(struct ql_adapter *qdev)
 {
-        u8 init_hash_seed[] = {0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
-                                0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f,
-                                0xb0, 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b,
-                                0x30, 0xb4, 0x77, 0xcb, 0x2d, 0xa3, 0x80,
-                                0x30, 0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b,
-                                0xbe, 0xac, 0x01, 0xfa};
+        static const u8 init_hash_seed[] = {
+                0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
+                0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
+                0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
+                0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
+                0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
+        };
         struct ricb *ricb = &qdev->ricb;
         int status = 0;
         int i;
@@ -3844,7 +3845,7 @@ static int ql_adapter_reset(struct ql_adapter *qdev)
 
 static void ql_display_dev_info(struct net_device *ndev)
 {
-        struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
+        struct ql_adapter *qdev = netdev_priv(ndev);
 
         netif_info(qdev, probe, qdev->ndev,
                    "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
@@ -4264,7 +4265,7 @@ static struct net_device_stats *qlge_get_stats(struct net_device
 
 static void qlge_set_multicast_list(struct net_device *ndev)
 {
-        struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
+        struct ql_adapter *qdev = netdev_priv(ndev);
         struct netdev_hw_addr *ha;
         int i, status;
 
@@ -4354,7 +4355,7 @@ exit:
 
 static int qlge_set_mac_address(struct net_device *ndev, void *p)
 {
-        struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
+        struct ql_adapter *qdev = netdev_priv(ndev);
         struct sockaddr *addr = p;
         int status;
 
@@ -4377,7 +4378,7 @@ static int qlge_set_mac_address(struct net_device *ndev, void *p)
 
 static void qlge_tx_timeout(struct net_device *ndev)
 {
-        struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
+        struct ql_adapter *qdev = netdev_priv(ndev);
         ql_queue_asic_error(qdev);
 }
 
diff --git a/drivers/net/qlge/qlge_mpi.c b/drivers/net/qlge/qlge_mpi.c
index a2e919bcb3c6..ff2bf8a4e247 100644
--- a/drivers/net/qlge/qlge_mpi.c
+++ b/drivers/net/qlge/qlge_mpi.c
@@ -87,7 +87,7 @@ exit:
         return status;
 }
 
-static int ql_soft_reset_mpi_risc(struct ql_adapter *qdev)
+int ql_soft_reset_mpi_risc(struct ql_adapter *qdev)
 {
         int status;
         status = ql_write_mpi_reg(qdev, 0x00001010, 1);
diff --git a/drivers/net/r6040.c b/drivers/net/r6040.c
index 0b014c894686..27e6f6d43cac 100644
--- a/drivers/net/r6040.c
+++ b/drivers/net/r6040.c
@@ -1153,6 +1153,7 @@ static int __devinit r6040_init_one(struct pci_dev *pdev,
         lp->mii_bus = mdiobus_alloc();
         if (!lp->mii_bus) {
                 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
+                err = -ENOMEM;
                 goto err_out_unmap;
         }
 
@@ -1165,6 +1166,7 @@ static int __devinit r6040_init_one(struct pci_dev *pdev,
         lp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
         if (!lp->mii_bus->irq) {
                 dev_err(&pdev->dev, "mii_bus irq allocation failed\n");
+                err = -ENOMEM;
                 goto err_out_mdio;
         }
 
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 53b13deade95..bb8645ab247c 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/dma-mapping.h>
 #include <linux/pm_runtime.h>
+#include <linux/firmware.h>
 
 #include <asm/system.h>
 #include <asm/io.h>
@@ -33,6 +34,9 @@
 #define MODULENAME "r8169"
 #define PFX MODULENAME ": "
 
+#define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
+#define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
+
 #ifdef RTL8169_DEBUG
 #define assert(expr) \
         if (!(expr)) {                                  \
@@ -63,7 +67,6 @@ static const int multicast_filter_limit = 32;
 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
-#define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
 
@@ -118,7 +121,8 @@ enum mac_version {
         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
         RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
         RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
-        RTL_GIGA_MAC_VER_27 = 0x1b  // 8168DP
+        RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
+        RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
 };
 
 #define _R(NAME,MAC,MASK) \
@@ -155,7 +159,8 @@ static const struct {
         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
-        _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880)  // PCI-E
+        _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
+        _R("RTL8168dp/8111dp",  RTL_GIGA_MAC_VER_28, 0xff7e1880)  // PCI-E
 };
 #undef _R
 
@@ -227,7 +232,14 @@ enum rtl_registers {
         IntrMitigate    = 0xe2,
         RxDescAddrLow   = 0xe4,
         RxDescAddrHigh  = 0xe8,
-        EarlyTxThres    = 0xec,
+        EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
+
+#define NoEarlyTx       0x3f    /* Max value : no early transmit. */
+
+        MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
+
+#define TxPacketMax     (8064 >> 7)
+
         FuncEvent       = 0xf0,
         FuncEventMask   = 0xf4,
         FuncPresetState = 0xf8,
@@ -248,7 +260,7 @@ enum rtl8168_8101_registers {
 #define CSIAR_BYTE_ENABLE               0x0f
 #define CSIAR_BYTE_ENABLE_SHIFT         12
 #define CSIAR_ADDR_MASK                 0x0fff
-
+        PMCH                    = 0x6f,
         EPHYAR                  = 0x80,
 #define EPHYAR_FLAG                     0x80000000
 #define EPHYAR_WRITE_CMD                0x80000000
@@ -267,6 +279,33 @@ enum rtl8168_8101_registers {
 #define EFUSEAR_DATA_MASK               0xff
 };
 
+enum rtl8168_registers {
+        ERIDR                   = 0x70,
+        ERIAR                   = 0x74,
+#define ERIAR_FLAG                      0x80000000
+#define ERIAR_WRITE_CMD                 0x80000000
+#define ERIAR_READ_CMD                  0x00000000
+#define ERIAR_ADDR_BYTE_ALIGN           4
+#define ERIAR_EXGMAC                    0
+#define ERIAR_MSIX                      1
+#define ERIAR_ASF                       2
+#define ERIAR_TYPE_SHIFT                16
+#define ERIAR_BYTEEN                    0x0f
+#define ERIAR_BYTEEN_SHIFT              12
+        EPHY_RXER_NUM           = 0x7c,
+        OCPDR                   = 0xb0, /* OCP GPHY access */
+#define OCPDR_WRITE_CMD                 0x80000000
+#define OCPDR_READ_CMD                  0x00000000
+#define OCPDR_REG_MASK                  0x7f
+#define OCPDR_GPHY_REG_SHIFT            16
+#define OCPDR_DATA_MASK                 0xffff
+        OCPAR                   = 0xb4,
+#define OCPAR_FLAG                      0x80000000
+#define OCPAR_GPHY_WRITE_CMD            0x8000f060
+#define OCPAR_GPHY_READ_CMD             0x0000f060
+        RDSAR1                  = 0xd0  /* 8168c only. Undocumented on 8168dp */
+};
+
 enum rtl_register_content {
         /* InterruptStatusBits */
         SYSErr          = 0x8000,
@@ -490,11 +529,22 @@ struct rtl8169_private {
 #ifdef CONFIG_R8169_VLAN
         struct vlan_group *vlgrp;
 #endif
+
+        struct mdio_ops {
+                void (*write)(void __iomem *, int, int);
+                int (*read)(void __iomem *, int);
+        } mdio_ops;
+
+        struct pll_power_ops {
+                void (*down)(struct rtl8169_private *);
+                void (*up)(struct rtl8169_private *);
+        } pll_power_ops;
+
         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
-        void (*phy_reset_enable)(void __iomem *);
+        void (*phy_reset_enable)(struct rtl8169_private *tp);
         void (*hw_start)(struct net_device *);
-        unsigned int (*phy_reset_pending)(void __iomem *);
+        unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
         unsigned int (*link_ok)(void __iomem *);
         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
         int pcie_cap;
@@ -514,6 +564,8 @@ module_param_named(debug, debug.msg_enable, int, 0);
 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 MODULE_LICENSE("GPL");
 MODULE_VERSION(RTL8169_VERSION);
+MODULE_FIRMWARE(FIRMWARE_8168D_1);
+MODULE_FIRMWARE(FIRMWARE_8168D_2);
 
 static int rtl8169_open(struct net_device *dev);
 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
@@ -535,7 +587,82 @@ static int rtl8169_poll(struct napi_struct *napi, int budget);
 static const unsigned int rtl8169_rx_config =
         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 
-static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
+static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+        int i;
+
+        RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
+        for (i = 0; i < 20; i++) {
+                udelay(100);
+                if (RTL_R32(OCPAR) & OCPAR_FLAG)
+                        break;
+        }
+        return RTL_R32(OCPDR);
+}
+
+static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+        int i;
+
+        RTL_W32(OCPDR, data);
+        RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
+        for (i = 0; i < 20; i++) {
+                udelay(100);
+                if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
+                        break;
+        }
+}
+
+static void rtl8168_oob_notify(void __iomem *ioaddr, u8 cmd)
+{
+        int i;
+
+        RTL_W8(ERIDR, cmd);
+        RTL_W32(ERIAR, 0x800010e8);
+        msleep(2);
+        for (i = 0; i < 5; i++) {
+                udelay(100);
+                if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
+                        break;
+        }
+
+        ocp_write(ioaddr, 0x1, 0x30, 0x00000001);
+}
+
+#define OOB_CMD_RESET           0x00
+#define OOB_CMD_DRIVER_START    0x05
+#define OOB_CMD_DRIVER_STOP     0x06
+
+static void rtl8168_driver_start(struct rtl8169_private *tp)
+{
+        int i;
+
+        rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
+
+        for (i = 0; i < 10; i++) {
+                msleep(10);
+                if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
+                        break;
+        }
+}
+
+static void rtl8168_driver_stop(struct rtl8169_private *tp)
+{
+        int i;
+
+        rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
+
+        for (i = 0; i < 10; i++) {
+                msleep(10);
+                if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
+                        break;
+        }
+}
+
+
+static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 {
         int i;
 
@@ -557,7 +684,7 @@ static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
         udelay(20);
 }
 
-static int mdio_read(void __iomem *ioaddr, int reg_addr)
+static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 {
         int i, value = -1;
 
@@ -583,34 +710,117 @@ static int mdio_read(void __iomem *ioaddr, int reg_addr)
         return value;
 }
 
-static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
+static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
+{
+        int i;
+
+        RTL_W32(OCPDR, data |
+                ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
+        RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
+        RTL_W32(EPHY_RXER_NUM, 0);
+
+        for (i = 0; i < 100; i++) {
+                mdelay(1);
+                if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
+                        break;
+        }
+}
+
+static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
+{
+        r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
+                (value & OCPDR_DATA_MASK));
+}
+
+static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
+{
+        int i;
+
+        r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
+
+        mdelay(1);
+        RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
+        RTL_W32(EPHY_RXER_NUM, 0);
+
+        for (i = 0; i < 100; i++) {
+                mdelay(1);
+                if (RTL_R32(OCPAR) & OCPAR_FLAG)
+                        break;
+        }
+
+        return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
+}
+
+#define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
+
+static void r8168dp_2_mdio_start(void __iomem *ioaddr)
+{
+        RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
+}
+
+static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
+{
+        RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
+}
+
+static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
+{
+        r8168dp_2_mdio_start(ioaddr);
+
+        r8169_mdio_write(ioaddr, reg_addr, value);
+
+        r8168dp_2_mdio_stop(ioaddr);
+}
+
+static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 {
-        mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
+        int value;
+
+        r8168dp_2_mdio_start(ioaddr);
+
+        value = r8169_mdio_read(ioaddr, reg_addr);
+
+        r8168dp_2_mdio_stop(ioaddr);
+
+        return value;
 }
 
-static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
+static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
+{
+        tp->mdio_ops.write(tp->mmio_addr, location, val);
+}
+
+static int rtl_readphy(struct rtl8169_private *tp, int location)
+{
+        return tp->mdio_ops.read(tp->mmio_addr, location);
+}
+
+static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
+{
+        rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
+}
+
+static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 {
         int val;
 
-        val = mdio_read(ioaddr, reg_addr);
-        mdio_write(ioaddr, reg_addr, (val | p) & ~m);
+        val = rtl_readphy(tp, reg_addr);
+        rtl_writephy(tp, reg_addr, (val | p) & ~m);
 }
 
 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
                            int val)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
-        void __iomem *ioaddr = tp->mmio_addr;
 
-        mdio_write(ioaddr, location, val);
+        rtl_writephy(tp, location, val);
 }
 
 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
-        void __iomem *ioaddr = tp->mmio_addr;
 
-        return mdio_read(ioaddr, location);
+        return rtl_readphy(tp, location);
 }
 
 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
@@ -711,14 +921,16 @@ static void rtl8169_asic_down(void __iomem *ioaddr)
         RTL_R16(CPlusCmd);
 }
 
-static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
+static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
 {
+        void __iomem *ioaddr = tp->mmio_addr;
+
         return RTL_R32(TBICSR) & TBIReset;
 }
 
-static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
+static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
 {
-        return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
+        return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
 }
 
 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
@@ -731,17 +943,19 @@ static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
         return RTL_R8(PHYstatus) & LinkStatus;
 }
 
-static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
+static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
 {
+        void __iomem *ioaddr = tp->mmio_addr;
+
         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 }
 
-static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
+static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
 {
         unsigned int val;
 
-        val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
-        mdio_write(ioaddr, MII_BMCR, val & 0xffff);
+        val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
+        rtl_writephy(tp, MII_BMCR, val & 0xffff);
 }
 
 static void __rtl8169_check_link_status(struct net_device *dev,
@@ -905,18 +1119,17 @@ static int rtl8169_set_speed_xmii(struct net_device *dev,
                                   u8 autoneg, u16 speed, u8 duplex)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
-        void __iomem *ioaddr = tp->mmio_addr;
         int giga_ctrl, bmcr;
 
         if (autoneg == AUTONEG_ENABLE) {
                 int auto_nego;
 
-                auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
+                auto_nego = rtl_readphy(tp, MII_ADVERTISE);
                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
                               ADVERTISE_100HALF | ADVERTISE_100FULL);
                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 
-                giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
+                giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 
                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
@@ -944,12 +1157,12 @@ static int rtl8169_set_speed_xmii(struct net_device *dev,
                          * Vendor specific (0x1f) and reserved (0x0e) MII
                          * registers.
                          */
-                        mdio_write(ioaddr, 0x1f, 0x0000);
-                        mdio_write(ioaddr, 0x0e, 0x0000);
+                        rtl_writephy(tp, 0x1f, 0x0000);
+                        rtl_writephy(tp, 0x0e, 0x0000);
                 }
 
-                mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
-                mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
+                rtl_writephy(tp, MII_ADVERTISE, auto_nego);
+                rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
         } else {
                 giga_ctrl = 0;
 
@@ -963,21 +1176,21 @@ static int rtl8169_set_speed_xmii(struct net_device *dev,
                 if (duplex == DUPLEX_FULL)
                         bmcr |= BMCR_FULLDPLX;
 
-                mdio_write(ioaddr, 0x1f, 0x0000);
+                rtl_writephy(tp, 0x1f, 0x0000);
         }
 
         tp->phy_1000_ctrl_reg = giga_ctrl;
 
-        mdio_write(ioaddr, MII_BMCR, bmcr);
+        rtl_writephy(tp, MII_BMCR, bmcr);
 
         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
-                        mdio_write(ioaddr, 0x17, 0x2138);
-                        mdio_write(ioaddr, 0x0e, 0x0260);
+                        rtl_writephy(tp, 0x17, 0x2138);
+                        rtl_writephy(tp, 0x0e, 0x0260);
                 } else {
-                        mdio_write(ioaddr, 0x17, 0x2108);
-                        mdio_write(ioaddr, 0x0e, 0x0000);
+                        rtl_writephy(tp, 0x17, 0x2108);
+                        rtl_writephy(tp, 0x0e, 0x0000);
                 }
         }
 
@@ -1319,9 +1532,12 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
                 /* 8168D family. */
                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
-                { 0x7c800000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
 
+                /* 8168DP family. */
+                { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
+                { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
+
                 /* 8168C family. */
                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
@@ -1385,15 +1601,172 @@ struct phy_reg {
         u16 val;
 };
 
-static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
+static void rtl_writephy_batch(struct rtl8169_private *tp,
+                               const struct phy_reg *regs, int len)
 {
         while (len-- > 0) {
-                mdio_write(ioaddr, regs->reg, regs->val);
+                rtl_writephy(tp, regs->reg, regs->val);
                 regs++;
         }
 }
 
-static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
+#define PHY_READ                0x00000000
+#define PHY_DATA_OR             0x10000000
+#define PHY_DATA_AND            0x20000000
+#define PHY_BJMPN               0x30000000
+#define PHY_READ_EFUSE          0x40000000
+#define PHY_READ_MAC_BYTE       0x50000000
+#define PHY_WRITE_MAC_BYTE      0x60000000
+#define PHY_CLEAR_READCOUNT     0x70000000
+#define PHY_WRITE               0x80000000
+#define PHY_READCOUNT_EQ_SKIP   0x90000000
+#define PHY_COMP_EQ_SKIPN       0xa0000000
+#define PHY_COMP_NEQ_SKIPN      0xb0000000
+#define PHY_WRITE_PREVIOUS      0xc0000000
+#define PHY_SKIPN               0xd0000000
+#define PHY_DELAY_MS            0xe0000000
+#define PHY_WRITE_ERI_WORD      0xf0000000
+
+static void
+rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
+{
+        __le32 *phytable = (__le32 *)fw->data;
+        struct net_device *dev = tp->dev;
+        size_t index, fw_size = fw->size / sizeof(*phytable);
+        u32 predata, count;
+
+        if (fw->size % sizeof(*phytable)) {
+                netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
+                return;
+        }
+
+        for (index = 0; index < fw_size; index++) {
+                u32 action = le32_to_cpu(phytable[index]);
+                u32 regno = (action & 0x0fff0000) >> 16;
+
+                switch(action & 0xf0000000) {
+                case PHY_READ:
+                case PHY_DATA_OR:
+                case PHY_DATA_AND:
+                case PHY_READ_EFUSE:
+                case PHY_CLEAR_READCOUNT:
+                case PHY_WRITE:
+                case PHY_WRITE_PREVIOUS:
+                case PHY_DELAY_MS:
+                        break;
+
+                case PHY_BJMPN:
+                        if (regno > index) {
+                                netif_err(tp, probe, tp->dev,
+                                        "Out of range of firmware\n");
+                                return;
+                        }
+                        break;
+                case PHY_READCOUNT_EQ_SKIP:
+                        if (index + 2 >= fw_size) {
+                                netif_err(tp, probe, tp->dev,
+                                        "Out of range of firmware\n");
+                                return;
+                        }
+                        break;
+                case PHY_COMP_EQ_SKIPN:
+                case PHY_COMP_NEQ_SKIPN:
+                case PHY_SKIPN:
+                        if (index + 1 + regno >= fw_size) {
+                                netif_err(tp, probe, tp->dev,
+                                        "Out of range of firmware\n");
+                                return;
+                        }
+                        break;
+
+                case PHY_READ_MAC_BYTE:
+                case PHY_WRITE_MAC_BYTE:
+                case PHY_WRITE_ERI_WORD:
+                default:
+                        netif_err(tp, probe, tp->dev,
+                                  "Invalid action 0x%08x\n", action);
+                        return;
+                }
+        }
+
+        predata = 0;
+        count = 0;
+
+        for (index = 0; index < fw_size; ) {
+                u32 action = le32_to_cpu(phytable[index]);
+                u32 data = action & 0x0000ffff;
+                u32 regno = (action & 0x0fff0000) >> 16;
+
+                if (!action)
+                        break;
+
+                switch(action & 0xf0000000) {
+                case PHY_READ:
+                        predata = rtl_readphy(tp, regno);
+                        count++;
+                        index++;
+                        break;
+                case PHY_DATA_OR:
+                        predata |= data;
+                        index++;
+                        break;
+                case PHY_DATA_AND:
+                        predata &= data;
+                        index++;
+                        break;
+                case PHY_BJMPN:
+                        index -= regno;
+                        break;
+                case PHY_READ_EFUSE:
+                        predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
+                        index++;
+                        break;
+                case PHY_CLEAR_READCOUNT:
+                        count = 0;
+                        index++;
+                        break;
+                case PHY_WRITE:
+                        rtl_writephy(tp, regno, data);
+                        index++;
+                        break;
+                case PHY_READCOUNT_EQ_SKIP:
+                        if (count == data)
+                                index += 2;
+                        else
+                                index += 1;
+                        break;
+                case PHY_COMP_EQ_SKIPN:
+                        if (predata == data)
+                                index += regno;
+                        index++;
+                        break;
+                case PHY_COMP_NEQ_SKIPN:
+                        if (predata != data)
+                                index += regno;
+                        index++;
+                        break;
+                case PHY_WRITE_PREVIOUS:
+                        rtl_writephy(tp, regno, predata);
+                        index++;
+                        break;
+                case PHY_SKIPN:
+                        index += regno + 1;
+                        break;
+                case PHY_DELAY_MS:
+                        mdelay(data);
+                        index++;
+                        break;
+
+                case PHY_READ_MAC_BYTE:
+                case PHY_WRITE_MAC_BYTE:
+                case PHY_WRITE_ERI_WORD:
+                default:
+                        BUG();
+                }
+        }
+}
+
+static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1457,10 +1830,10 @@ static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
                 { 0x00, 0x9200 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
+static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0002 },
@@ -1468,11 +1841,10 @@ static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
-                                           void __iomem *ioaddr)
+static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
 {
         struct pci_dev *pdev = tp->pci_dev;
         u16 vendor_id, device_id;
@@ -1483,13 +1855,12 @@ static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
                 return;
 
-        mdio_write(ioaddr, 0x1f, 0x0001);
-        mdio_write(ioaddr, 0x10, 0xf01b);
-        mdio_write(ioaddr, 0x1f, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0001);
+        rtl_writephy(tp, 0x10, 0xf01b);
+        rtl_writephy(tp, 0x1f, 0x0000);
 }
 
-static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
-                                     void __iomem *ioaddr)
+static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1531,12 +1902,12 @@ static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 
-        rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
+        rtl8169scd_hw_phy_config_quirk(tp);
 }
 
-static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
+static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1586,23 +1957,23 @@ static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x10, 0xf41b },
                 { 0x1f, 0x0000 }
         };
 
-        mdio_write(ioaddr, 0x1f, 0x0001);
-        mdio_patch(ioaddr, 0x16, 1 << 0);
+        rtl_writephy(tp, 0x1f, 0x0001);
+        rtl_patchphy(tp, 0x16, 1 << 0);
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1610,10 +1981,10 @@ static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0000 },
@@ -1623,10 +1994,10 @@ static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1634,14 +2005,14 @@ static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        mdio_write(ioaddr, 0x1f, 0x0000);
-        mdio_patch(ioaddr, 0x14, 1 << 5);
-        mdio_patch(ioaddr, 0x0d, 1 << 5);
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_patchphy(tp, 0x14, 1 << 5);
+        rtl_patchphy(tp, 0x0d, 1 << 5);
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1663,14 +2034,14 @@ static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
                 { 0x09, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 
-        mdio_patch(ioaddr, 0x14, 1 << 5);
-        mdio_patch(ioaddr, 0x0d, 1 << 5);
-        mdio_write(ioaddr, 0x1f, 0x0000);
+        rtl_patchphy(tp, 0x14, 1 << 5);
+        rtl_patchphy(tp, 0x0d, 1 << 5);
+        rtl_writephy(tp, 0x1f, 0x0000);
 }
 
-static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1690,15 +2061,15 @@ static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 
-        mdio_patch(ioaddr, 0x16, 1 << 0);
-        mdio_patch(ioaddr, 0x14, 1 << 5);
-        mdio_patch(ioaddr, 0x0d, 1 << 5);
-        mdio_write(ioaddr, 0x1f, 0x0000);
+        rtl_patchphy(tp, 0x16, 1 << 0);
+        rtl_patchphy(tp, 0x14, 1 << 5);
+        rtl_patchphy(tp, 0x0d, 1 << 5);
+        rtl_writephy(tp, 0x1f, 0x0000);
 }
 
-static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0001 },
@@ -1712,22 +2083,23 @@ static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 
-        mdio_patch(ioaddr, 0x16, 1 << 0);
-        mdio_patch(ioaddr, 0x14, 1 << 5);
-        mdio_patch(ioaddr, 0x0d, 1 << 5);
-        mdio_write(ioaddr, 0x1f, 0x0000);
+        rtl_patchphy(tp, 0x16, 1 << 0);
+        rtl_patchphy(tp, 0x14, 1 << 5);
+        rtl_patchphy(tp, 0x0d, 1 << 5);
+        rtl_writephy(tp, 0x1f, 0x0000);
 }
 
-static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
 {
-        rtl8168c_3_hw_phy_config(ioaddr);
+        rtl8168c_3_hw_phy_config(tp);
 }
 
-static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init_0[] = {
+                /* Channel Estimation */
                 { 0x1f, 0x0001 },
                 { 0x06, 0x4064 },
                 { 0x07, 0x2863 },
@@ -1744,378 +2116,40 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
                 { 0x12, 0xf49f },
                 { 0x13, 0x070b },
                 { 0x1a, 0x05ad },
-                { 0x14, 0x94c0 }
-        };
-        static const struct phy_reg phy_reg_init_1[] = {
+                { 0x14, 0x94c0 },
+
+                /*
+                 * Tx Error Issue
+                 * enhance line driver power
+                 */
                 { 0x1f, 0x0002 },
                 { 0x06, 0x5561 },
                 { 0x1f, 0x0005 },
                 { 0x05, 0x8332 },
-                { 0x06, 0x5561 }
-        };
-        static const struct phy_reg phy_reg_init_2[] = {
-                { 0x1f, 0x0005 },
-                { 0x05, 0xffc2 },
-                { 0x1f, 0x0005 },
-                { 0x05, 0x8000 },
-                { 0x06, 0xf8f9 },
-                { 0x06, 0xfaef },
-                { 0x06, 0x59ee },
-                { 0x06, 0xf8ea },
-                { 0x06, 0x00ee },
-                { 0x06, 0xf8eb },
-                { 0x06, 0x00e0 },
-                { 0x06, 0xf87c },
-                { 0x06, 0xe1f8 },
-                { 0x06, 0x7d59 },
-                { 0x06, 0x0fef },
-                { 0x06, 0x0139 },
-                { 0x06, 0x029e },
-                { 0x06, 0x06ef },
-                { 0x06, 0x1039 },
-                { 0x06, 0x089f },
-                { 0x06, 0x2aee },
-                { 0x06, 0xf8ea },
-                { 0x06, 0x00ee },
-                { 0x06, 0xf8eb },
-                { 0x06, 0x01e0 },
-                { 0x06, 0xf87c },
-                { 0x06, 0xe1f8 },
-                { 0x06, 0x7d58 },
-                { 0x06, 0x409e },
-                { 0x06, 0x0f39 },
-                { 0x06, 0x46aa },
-                { 0x06, 0x0bbf },
-                { 0x06, 0x8290 },
-                { 0x06, 0xd682 },
-                { 0x06, 0x9802 },
-                { 0x06, 0x014f },
-                { 0x06, 0xae09 },
-                { 0x06, 0xbf82 },
-                { 0x06, 0x98d6 },
-                { 0x06, 0x82a0 },
-                { 0x06, 0x0201 },
-                { 0x06, 0x4fef },
-                { 0x06, 0x95fe },
-                { 0x06, 0xfdfc },
-                { 0x06, 0x05f8 },
-                { 0x06, 0xf9fa },
-                { 0x06, 0xeef8 },
-                { 0x06, 0xea00 },
-                { 0x06, 0xeef8 },
-                { 0x06, 0xeb00 },
-                { 0x06, 0xe2f8 },
-                { 0x06, 0x7ce3 },
-                { 0x06, 0xf87d },
-                { 0x06, 0xa511 },
-                { 0x06, 0x1112 },
-                { 0x06, 0xd240 },
-                { 0x06, 0xd644 },
-                { 0x06, 0x4402 },
-                { 0x06, 0x8217 },
-                { 0x06, 0xd2a0 },
-                { 0x06, 0xd6aa },
-                { 0x06, 0xaa02 },
-                { 0x06, 0x8217 },
-                { 0x06, 0xae0f },
-                { 0x06, 0xa544 },
-                { 0x06, 0x4402 },
-                { 0x06, 0xae4d },
-                { 0x06, 0xa5aa },
-                { 0x06, 0xaa02 },
-                { 0x06, 0xae47 },
-                { 0x06, 0xaf82 },
-                { 0x06, 0x13ee },
-                { 0x06, 0x834e },
-                { 0x06, 0x00ee },
-                { 0x06, 0x834d },
-                { 0x06, 0x0fee },
-                { 0x06, 0x834c },
-                { 0x06, 0x0fee },
-                { 0x06, 0x834f },
-                { 0x06, 0x00ee },
-                { 0x06, 0x8351 },
-                { 0x06, 0x00ee },
-                { 0x06, 0x834a },
-                { 0x06, 0xffee },
-                { 0x06, 0x834b },
-                { 0x06, 0xffe0 },
-                { 0x06, 0x8330 },
-                { 0x06, 0xe183 },
-                { 0x06, 0x3158 },
-                { 0x06, 0xfee4 },
-                { 0x06, 0xf88a },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x8be0 },
-                { 0x06, 0x8332 },
-                { 0x06, 0xe183 },
-                { 0x06, 0x3359 },
-                { 0x06, 0x0fe2 },
-                { 0x06, 0x834d },
-                { 0x06, 0x0c24 },
-                { 0x06, 0x5af0 },
-                { 0x06, 0x1e12 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x8ce5 },
-                { 0x06, 0xf88d },
-                { 0x06, 0xaf82 },
-                { 0x06, 0x13e0 },
-                { 0x06, 0x834f },
-                { 0x06, 0x10e4 },
-                { 0x06, 0x834f },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x009f },
-                { 0x06, 0x0ae0 },
-                { 0x06, 0x834f },
-                { 0x06, 0xa010 },
-                { 0x06, 0xa5ee },
-                { 0x06, 0x834e },
-                { 0x06, 0x01e0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7805 },
-                { 0x06, 0x9e9a },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x049e },
-                { 0x06, 0x10e0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7803 },
-                { 0x06, 0x9e0f },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x019e },
-                { 0x06, 0x05ae },
-                { 0x06, 0x0caf },
-                { 0x06, 0x81f8 },
-                { 0x06, 0xaf81 },
-                { 0x06, 0xa3af },
-                { 0x06, 0x81dc },
-                { 0x06, 0xaf82 },
-                { 0x06, 0x13ee },
-                { 0x06, 0x8348 },
-                { 0x06, 0x00ee },
-                { 0x06, 0x8349 },
-                { 0x06, 0x00e0 },
-                { 0x06, 0x8351 },
-                { 0x06, 0x10e4 },
-                { 0x06, 0x8351 },
-                { 0x06, 0x5801 },
-                { 0x06, 0x9fea },
-                { 0x06, 0xd000 },
-                { 0x06, 0xd180 },
-                { 0x06, 0x1f66 },
-                { 0x06, 0xe2f8 },
-                { 0x06, 0xeae3 },
-                { 0x06, 0xf8eb },
-                { 0x06, 0x5af8 },
-                { 0x06, 0x1e20 },
-                { 0x06, 0xe6f8 },
-                { 0x06, 0xeae5 },
-                { 0x06, 0xf8eb },
-                { 0x06, 0xd302 },
-                { 0x06, 0xb3fe },
-                { 0x06, 0xe2f8 },
-                { 0x06, 0x7cef },
-                { 0x06, 0x325b },
-                { 0x06, 0x80e3 },
-                { 0x06, 0xf87d },
-                { 0x06, 0x9e03 },
-                { 0x06, 0x7dff },
-                { 0x06, 0xff0d },
-                { 0x06, 0x581c },
-                { 0x06, 0x551a },
-                { 0x06, 0x6511 },
-                { 0x06, 0xa190 },
-                { 0x06, 0xd3e2 },
-                { 0x06, 0x8348 },
-                { 0x06, 0xe383 },
-                { 0x06, 0x491b },
-                { 0x06, 0x56ab },
-                { 0x06, 0x08ef },
-                { 0x06, 0x56e6 },
-                { 0x06, 0x8348 },
-                { 0x06, 0xe783 },
-                { 0x06, 0x4910 },
-                { 0x06, 0xd180 },
-                { 0x06, 0x1f66 },
-                { 0x06, 0xa004 },
-                { 0x06, 0xb9e2 },
-                { 0x06, 0x8348 },
-                { 0x06, 0xe383 },
-                { 0x06, 0x49ef },
-                { 0x06, 0x65e2 },
-                { 0x06, 0x834a },
-                { 0x06, 0xe383 },
-                { 0x06, 0x4b1b },
-                { 0x06, 0x56aa },
-                { 0x06, 0x0eef },
-                { 0x06, 0x56e6 },
-                { 0x06, 0x834a },
-                { 0x06, 0xe783 },
-                { 0x06, 0x4be2 },
-                { 0x06, 0x834d },
-                { 0x06, 0xe683 },
-                { 0x06, 0x4ce0 },
-                { 0x06, 0x834d },
-                { 0x06, 0xa000 },
-                { 0x06, 0x0caf },
-                { 0x06, 0x81dc },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4d10 },
-                { 0x06, 0xe483 },
-                { 0x06, 0x4dae },
-                { 0x06, 0x0480 },
-                { 0x06, 0xe483 },
-                { 0x06, 0x4de0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7803 },
-                { 0x06, 0x9e0b },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x049e },
-                { 0x06, 0x04ee },
-                { 0x06, 0x834e },
-                { 0x06, 0x02e0 },
-                { 0x06, 0x8332 },
-                { 0x06, 0xe183 },
-                { 0x06, 0x3359 },
-                { 0x06, 0x0fe2 },
-                { 0x06, 0x834d },
-                { 0x06, 0x0c24 },
-                { 0x06, 0x5af0 },
-                { 0x06, 0x1e12 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x8ce5 },
-                { 0x06, 0xf88d },
-                { 0x06, 0xe083 },
-                { 0x06, 0x30e1 },
-                { 0x06, 0x8331 },
-                { 0x06, 0x6801 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x8ae5 },
-                { 0x06, 0xf88b },
-                { 0x06, 0xae37 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4e03 },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4ce1 },
-                { 0x06, 0x834d },
-                { 0x06, 0x1b01 },
-                { 0x06, 0x9e04 },
-                { 0x06, 0xaaa1 },
-                { 0x06, 0xaea8 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4e04 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4f00 },
-                { 0x06, 0xaeab },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4f78 },
-                { 0x06, 0x039f },
-                { 0x06, 0x14ee },
-                { 0x06, 0x834e },
-                { 0x06, 0x05d2 },
-                { 0x06, 0x40d6 },
-                { 0x06, 0x5554 },
-                { 0x06, 0x0282 },
-                { 0x06, 0x17d2 },
-                { 0x06, 0xa0d6 },
-                { 0x06, 0xba00 },
-                { 0x06, 0x0282 },
-                { 0x06, 0x17fe },
-                { 0x06, 0xfdfc },
-                { 0x06, 0x05f8 },
-                { 0x06, 0xe0f8 },
-                { 0x06, 0x60e1 },
-                { 0x06, 0xf861 },
-                { 0x06, 0x6802 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x60e5 },
-                { 0x06, 0xf861 },
-                { 0x06, 0xe0f8 },
-                { 0x06, 0x48e1 },
-                { 0x06, 0xf849 },
-                { 0x06, 0x580f },
-                { 0x06, 0x1e02 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x48e5 },
-                { 0x06, 0xf849 },
-                { 0x06, 0xd000 },
-                { 0x06, 0x0282 },
-                { 0x06, 0x5bbf },
-                { 0x06, 0x8350 },
-                { 0x06, 0xef46 },
-                { 0x06, 0xdc19 },
-                { 0x06, 0xddd0 },
-                { 0x06, 0x0102 },
-                { 0x06, 0x825b },
-                { 0x06, 0x0282 },
-                { 0x06, 0x77e0 },
-                { 0x06, 0xf860 },
-                { 0x06, 0xe1f8 },
-                { 0x06, 0x6158 },
-                { 0x06, 0xfde4 },
-                { 0x06, 0xf860 },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x61fc },
-                { 0x06, 0x04f9 },
-                { 0x06, 0xfafb },
-                { 0x06, 0xc6bf },
-                { 0x06, 0xf840 },
-                { 0x06, 0xbe83 },
-                { 0x06, 0x50a0 },
-                { 0x06, 0x0101 },
-                { 0x06, 0x071b },
-                { 0x06, 0x89cf },
-                { 0x06, 0xd208 },
-                { 0x06, 0xebdb },
-                { 0x06, 0x19b2 },
-                { 0x06, 0xfbff },
-                { 0x06, 0xfefd },
-                { 0x06, 0x04f8 },
-                { 0x06, 0xe0f8 },
-                { 0x06, 0x48e1 },
-                { 0x06, 0xf849 },
-                { 0x06, 0x6808 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x48e5 },
-                { 0x06, 0xf849 },
-                { 0x06, 0x58f7 },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x48e5 },
-                { 0x06, 0xf849 },
-                { 0x06, 0xfc04 },
-                { 0x06, 0x4d20 },
-                { 0x06, 0x0002 },
-                { 0x06, 0x4e22 },
-                { 0x06, 0x0002 },
-                { 0x06, 0x4ddf },
-                { 0x06, 0xff01 },
-                { 0x06, 0x4edd },
-                { 0x06, 0xff01 },
-                { 0x05, 0x83d4 },
-                { 0x06, 0x8000 },
-                { 0x05, 0x83d8 },
-                { 0x06, 0x8051 },
-                { 0x02, 0x6010 },
-                { 0x03, 0xdc00 },
-                { 0x05, 0xfff6 },
-                { 0x06, 0x00fc },
-                { 0x1f, 0x0000 },
+                { 0x06, 0x5561 },
+
+                /*
+                 * Can not link to 1Gbps with bad cable
+                 * Decrease SNR threshold form 21.07dB to 19.04dB
+                 */
+                { 0x1f, 0x0001 },
+                { 0x17, 0x0cc0 },
 
                 { 0x1f, 0x0000 },
-                { 0x0d, 0xf880 },
-                { 0x1f, 0x0000 }
+                { 0x0d, 0xf880 }
         };
+        void __iomem *ioaddr = tp->mmio_addr;
+        const struct firmware *fw;
 
-        rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
-
-        mdio_write(ioaddr, 0x1f, 0x0002);
-        mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
-        mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
+        rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
 
-        rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
+        /*
+         * Rx Error Issue
+         * Fine Tune Switching regulator parameter
+         */
+        rtl_writephy(tp, 0x1f, 0x0002);
+        rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
+        rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
 
         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
                 static const struct phy_reg phy_reg_init[] = {
@@ -2128,9 +2162,9 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
                 };
                 int val;
 
-                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+                rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 
-                val = mdio_read(ioaddr, 0x0d);
+                val = rtl_readphy(tp, 0x0d);
 
                 if ((val & 0x00ff) != 0x006c) {
                         static const u32 set[] = {
@@ -2139,11 +2173,11 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
                         };
                         int i;
 
-                        mdio_write(ioaddr, 0x1f, 0x0002);
+                        rtl_writephy(tp, 0x1f, 0x0002);
 
                         val &= 0xff00;
                         for (i = 0; i < ARRAY_SIZE(set); i++)
-                                mdio_write(ioaddr, 0x0d, val | set[i]);
+                                rtl_writephy(tp, 0x0d, val | set[i]);
                 }
         } else {
                 static const struct phy_reg phy_reg_init[] = {
@@ -2154,23 +2188,36 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
                         { 0x06, 0x6662 }
                 };
 
-                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+                rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
         }
 
-        mdio_write(ioaddr, 0x1f, 0x0002);
-        mdio_patch(ioaddr, 0x0d, 0x0300);
-        mdio_patch(ioaddr, 0x0f, 0x0010);
-
-        mdio_write(ioaddr, 0x1f, 0x0002);
-        mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
-        mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
+        /* RSET couple improve */
+        rtl_writephy(tp, 0x1f, 0x0002);
+        rtl_patchphy(tp, 0x0d, 0x0300);
+        rtl_patchphy(tp, 0x0f, 0x0010);
+
+        /* Fine tune PLL performance */
+        rtl_writephy(tp, 0x1f, 0x0002);
+        rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
+        rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
+
+        rtl_writephy(tp, 0x1f, 0x0005);
+        rtl_writephy(tp, 0x05, 0x001b);
+        if (rtl_readphy(tp, 0x06) == 0xbf00 &&
+            request_firmware(&fw, FIRMWARE_8168D_1, &tp->pci_dev->dev) == 0) {
+                rtl_phy_write_fw(tp, fw);
+                release_firmware(fw);
+        } else {
+                netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
+        }
 
-        rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
+        rtl_writephy(tp, 0x1f, 0x0000);
 }
 
-static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init_0[] = {
+                /* Channel Estimation */
                 { 0x1f, 0x0001 },
                 { 0x06, 0x4064 },
                 { 0x07, 0x2863 },
@@ -2189,326 +2236,30 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
                 { 0x1a, 0x05ad },
                 { 0x14, 0x94c0 },
 
+                /*
+                 * Tx Error Issue
+                 * enhance line driver power
+                 */
                 { 0x1f, 0x0002 },
                 { 0x06, 0x5561 },
                 { 0x1f, 0x0005 },
                 { 0x05, 0x8332 },
-                { 0x06, 0x5561 }
-        };
-        static const struct phy_reg phy_reg_init_1[] = {
-                { 0x1f, 0x0005 },
-                { 0x05, 0xffc2 },
-                { 0x1f, 0x0005 },
-                { 0x05, 0x8000 },
-                { 0x06, 0xf8f9 },
-                { 0x06, 0xfaee },
-                { 0x06, 0xf8ea },
-                { 0x06, 0x00ee },
-                { 0x06, 0xf8eb },
-                { 0x06, 0x00e2 },
-                { 0x06, 0xf87c },
-                { 0x06, 0xe3f8 },
-                { 0x06, 0x7da5 },
-                { 0x06, 0x1111 },
-                { 0x06, 0x12d2 },
-                { 0x06, 0x40d6 },
-                { 0x06, 0x4444 },
-                { 0x06, 0x0281 },
-                { 0x06, 0xc6d2 },
-                { 0x06, 0xa0d6 },
-                { 0x06, 0xaaaa },
-                { 0x06, 0x0281 },
-                { 0x06, 0xc6ae },
-                { 0x06, 0x0fa5 },
-                { 0x06, 0x4444 },
-                { 0x06, 0x02ae },
-                { 0x06, 0x4da5 },
-                { 0x06, 0xaaaa },
-                { 0x06, 0x02ae },
-                { 0x06, 0x47af },
-                { 0x06, 0x81c2 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4e00 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4d0f },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4c0f },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4f00 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x5100 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4aff },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4bff },
-                { 0x06, 0xe083 },
-                { 0x06, 0x30e1 },
-                { 0x06, 0x8331 },
-                { 0x06, 0x58fe },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x8ae5 },
-                { 0x06, 0xf88b },
-                { 0x06, 0xe083 },
-                { 0x06, 0x32e1 },
-                { 0x06, 0x8333 },
-                { 0x06, 0x590f },
-                { 0x06, 0xe283 },
-                { 0x06, 0x4d0c },
-                { 0x06, 0x245a },
-                { 0x06, 0xf01e },
-                { 0x06, 0x12e4 },
-                { 0x06, 0xf88c },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x8daf },
-                { 0x06, 0x81c2 },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4f10 },
-                { 0x06, 0xe483 },
-                { 0x06, 0x4fe0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7800 },
-                { 0x06, 0x9f0a },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4fa0 },
-                { 0x06, 0x10a5 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4e01 },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x059e },
-                { 0x06, 0x9ae0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7804 },
-                { 0x06, 0x9e10 },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x039e },
-                { 0x06, 0x0fe0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7801 },
-                { 0x06, 0x9e05 },
-                { 0x06, 0xae0c },
-                { 0x06, 0xaf81 },
-                { 0x06, 0xa7af },
-                { 0x06, 0x8152 },
-                { 0x06, 0xaf81 },
-                { 0x06, 0x8baf },
-                { 0x06, 0x81c2 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4800 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4900 },
-                { 0x06, 0xe083 },
-                { 0x06, 0x5110 },
-                { 0x06, 0xe483 },
-                { 0x06, 0x5158 },
-                { 0x06, 0x019f },
-                { 0x06, 0xead0 },
-                { 0x06, 0x00d1 },
-                { 0x06, 0x801f },
-                { 0x06, 0x66e2 },
-                { 0x06, 0xf8ea },
-                { 0x06, 0xe3f8 },
-                { 0x06, 0xeb5a },
-                { 0x06, 0xf81e },
-                { 0x06, 0x20e6 },
-                { 0x06, 0xf8ea },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0xebd3 },
-                { 0x06, 0x02b3 },
-                { 0x06, 0xfee2 },
-                { 0x06, 0xf87c },
-                { 0x06, 0xef32 },
-                { 0x06, 0x5b80 },
-                { 0x06, 0xe3f8 },
-                { 0x06, 0x7d9e },
-                { 0x06, 0x037d },
-                { 0x06, 0xffff },
-                { 0x06, 0x0d58 },
-                { 0x06, 0x1c55 },
-                { 0x06, 0x1a65 },
-                { 0x06, 0x11a1 },
-                { 0x06, 0x90d3 },
-                { 0x06, 0xe283 },
-                { 0x06, 0x48e3 },
-                { 0x06, 0x8349 },
-                { 0x06, 0x1b56 },
-                { 0x06, 0xab08 },
-                { 0x06, 0xef56 },
-                { 0x06, 0xe683 },
-                { 0x06, 0x48e7 },
-                { 0x06, 0x8349 },
-                { 0x06, 0x10d1 },
-                { 0x06, 0x801f },
-                { 0x06, 0x66a0 },
-                { 0x06, 0x04b9 },
-                { 0x06, 0xe283 },
-                { 0x06, 0x48e3 },
-                { 0x06, 0x8349 },
-                { 0x06, 0xef65 },
-                { 0x06, 0xe283 },
-                { 0x06, 0x4ae3 },
-                { 0x06, 0x834b },
-                { 0x06, 0x1b56 },
-                { 0x06, 0xaa0e },
-                { 0x06, 0xef56 },
-                { 0x06, 0xe683 },
-                { 0x06, 0x4ae7 },
-                { 0x06, 0x834b },
-                { 0x06, 0xe283 },
-                { 0x06, 0x4de6 },
-                { 0x06, 0x834c },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4da0 },
-                { 0x06, 0x000c },
-                { 0x06, 0xaf81 },
-                { 0x06, 0x8be0 },
-                { 0x06, 0x834d },
-                { 0x06, 0x10e4 },
-                { 0x06, 0x834d },
-                { 0x06, 0xae04 },
-                { 0x06, 0x80e4 },
-                { 0x06, 0x834d },
-                { 0x06, 0xe083 },
-                { 0x06, 0x4e78 },
-                { 0x06, 0x039e },
-                { 0x06, 0x0be0 },
-                { 0x06, 0x834e },
-                { 0x06, 0x7804 },
-                { 0x06, 0x9e04 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4e02 },
-                { 0x06, 0xe083 },
-                { 0x06, 0x32e1 },
-                { 0x06, 0x8333 },
-                { 0x06, 0x590f },
-                { 0x06, 0xe283 },
-                { 0x06, 0x4d0c },
-                { 0x06, 0x245a },
-                { 0x06, 0xf01e },
-                { 0x06, 0x12e4 },
-                { 0x06, 0xf88c },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x8de0 },
-                { 0x06, 0x8330 },
-                { 0x06, 0xe183 },
-                { 0x06, 0x3168 },
-                { 0x06, 0x01e4 },
-                { 0x06, 0xf88a },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x8bae },
-                { 0x06, 0x37ee },
-                { 0x06, 0x834e },
-                { 0x06, 0x03e0 },
-                { 0x06, 0x834c },
-                { 0x06, 0xe183 },
-                { 0x06, 0x4d1b },
-                { 0x06, 0x019e },
-                { 0x06, 0x04aa },
-                { 0x06, 0xa1ae },
-                { 0x06, 0xa8ee },
-                { 0x06, 0x834e },
-                { 0x06, 0x04ee },
-                { 0x06, 0x834f },
-                { 0x06, 0x00ae },
-                { 0x06, 0xabe0 },
-                { 0x06, 0x834f },
-                { 0x06, 0x7803 },
-                { 0x06, 0x9f14 },
-                { 0x06, 0xee83 },
-                { 0x06, 0x4e05 },
-                { 0x06, 0xd240 },
-                { 0x06, 0xd655 },
-                { 0x06, 0x5402 },
-                { 0x06, 0x81c6 },
-                { 0x06, 0xd2a0 },
-                { 0x06, 0xd6ba },
-                { 0x06, 0x0002 },
-                { 0x06, 0x81c6 },
-                { 0x06, 0xfefd },
-                { 0x06, 0xfc05 },
-                { 0x06, 0xf8e0 },
-                { 0x06, 0xf860 },
-                { 0x06, 0xe1f8 },
-                { 0x06, 0x6168 },
-                { 0x06, 0x02e4 },
-                { 0x06, 0xf860 },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x61e0 },
-                { 0x06, 0xf848 },
-                { 0x06, 0xe1f8 },
-                { 0x06, 0x4958 },
-                { 0x06, 0x0f1e },
-                { 0x06, 0x02e4 },
-                { 0x06, 0xf848 },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x49d0 },
-                { 0x06, 0x0002 },
-                { 0x06, 0x820a },
-                { 0x06, 0xbf83 },
-                { 0x06, 0x50ef },
-                { 0x06, 0x46dc },
-                { 0x06, 0x19dd },
-                { 0x06, 0xd001 },
-                { 0x06, 0x0282 },
-                { 0x06, 0x0a02 },
-                { 0x06, 0x8226 },
-                { 0x06, 0xe0f8 },
-                { 0x06, 0x60e1 },
-                { 0x06, 0xf861 },
-                { 0x06, 0x58fd },
-                { 0x06, 0xe4f8 },
-                { 0x06, 0x60e5 },
-                { 0x06, 0xf861 },
-                { 0x06, 0xfc04 },
-                { 0x06, 0xf9fa },
-                { 0x06, 0xfbc6 },
-                { 0x06, 0xbff8 },
-                { 0x06, 0x40be },
-                { 0x06, 0x8350 },
-                { 0x06, 0xa001 },
-                { 0x06, 0x0107 },
-                { 0x06, 0x1b89 },
-                { 0x06, 0xcfd2 },
-                { 0x06, 0x08eb },
-                { 0x06, 0xdb19 },
-                { 0x06, 0xb2fb },
-                { 0x06, 0xfffe },
-                { 0x06, 0xfd04 },
-                { 0x06, 0xf8e0 },
-                { 0x06, 0xf848 },
-                { 0x06, 0xe1f8 },
-                { 0x06, 0x4968 },
-                { 0x06, 0x08e4 },
-                { 0x06, 0xf848 },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x4958 },
-                { 0x06, 0xf7e4 },
-                { 0x06, 0xf848 },
-                { 0x06, 0xe5f8 },
-                { 0x06, 0x49fc },
-                { 0x06, 0x044d },
-                { 0x06, 0x2000 },
-                { 0x06, 0x024e },
-                { 0x06, 0x2200 },
-                { 0x06, 0x024d },
-                { 0x06, 0xdfff },
-                { 0x06, 0x014e },
-                { 0x06, 0xddff },
-                { 0x06, 0x0100 },
-                { 0x05, 0x83d8 },
-                { 0x06, 0x8000 },
-                { 0x03, 0xdc00 },
-                { 0x05, 0xfff6 },
-                { 0x06, 0x00fc },
-                { 0x1f, 0x0000 },
+                { 0x06, 0x5561 },
+
+                /*
+                 * Can not link to 1Gbps with bad cable
+                 * Decrease SNR threshold form 21.07dB to 19.04dB
+                 */
+                { 0x1f, 0x0001 },
+                { 0x17, 0x0cc0 },
 
                 { 0x1f, 0x0000 },
-                { 0x0d, 0xf880 },
-                { 0x1f, 0x0000 }
+                { 0x0d, 0xf880 }
         };
+        void __iomem *ioaddr = tp->mmio_addr;
+        const struct firmware *fw;
 
-        rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
+        rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
 
         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
                 static const struct phy_reg phy_reg_init[] = {
@@ -2522,21 +2273,21 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
                 };
                 int val;
 
-                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+                rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 
-                val = mdio_read(ioaddr, 0x0d);
+                val = rtl_readphy(tp, 0x0d);
                 if ((val & 0x00ff) != 0x006c) {
-                        u32 set[] = {
+                        static const u32 set[] = {
                                 0x0065, 0x0066, 0x0067, 0x0068,
                                 0x0069, 0x006a, 0x006b, 0x006c
                         };
                         int i;
 
-                        mdio_write(ioaddr, 0x1f, 0x0002);
+                        rtl_writephy(tp, 0x1f, 0x0002);
 
                         val &= 0xff00;
                         for (i = 0; i < ARRAY_SIZE(set); i++)
-                                mdio_write(ioaddr, 0x0d, val | set[i]);
+                                rtl_writephy(tp, 0x0d, val | set[i]);
                 }
         } else {
                 static const struct phy_reg phy_reg_init[] = {
@@ -2547,23 +2298,32 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
                         { 0x06, 0x2642 }
                 };
 
-                rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+                rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
         }
 
-        mdio_write(ioaddr, 0x1f, 0x0002);
-        mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
-        mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
-
-        mdio_write(ioaddr, 0x1f, 0x0001);
-        mdio_write(ioaddr, 0x17, 0x0cc0);
-
-        mdio_write(ioaddr, 0x1f, 0x0002);
-        mdio_patch(ioaddr, 0x0f, 0x0017);
+        /* Fine tune PLL performance */
+        rtl_writephy(tp, 0x1f, 0x0002);
+        rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
+        rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
+
+        /* Switching regulator Slew rate */
+        rtl_writephy(tp, 0x1f, 0x0002);
+        rtl_patchphy(tp, 0x0f, 0x0017);
+
+        rtl_writephy(tp, 0x1f, 0x0005);
+        rtl_writephy(tp, 0x05, 0x001b);
+        if (rtl_readphy(tp, 0x06) == 0xb300 &&
+            request_firmware(&fw, FIRMWARE_8168D_2, &tp->pci_dev->dev) == 0) {
+                rtl_phy_write_fw(tp, fw);
+                release_firmware(fw);
+        } else {
+                netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
+        }
 
-        rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
+        rtl_writephy(tp, 0x1f, 0x0000);
 }
 
-static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0002 },
@@ -2621,10 +2381,26 @@ static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
-static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
+static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
+{
+        static const struct phy_reg phy_reg_init[] = {
+                { 0x1f, 0x0001 },
+                { 0x17, 0x0cc0 },
+
+                { 0x1f, 0x0007 },
+                { 0x1e, 0x002d },
+                { 0x18, 0x0040 },
+                { 0x1f, 0x0000 }
+        };
+
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_patchphy(tp, 0x0d, 1 << 5);
+}
+
+static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
                 { 0x1f, 0x0003 },
@@ -2633,18 +2409,17 @@ static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
                 { 0x1f, 0x0000 }
         };
 
-        mdio_write(ioaddr, 0x1f, 0x0000);
-        mdio_patch(ioaddr, 0x11, 1 << 12);
-        mdio_patch(ioaddr, 0x19, 1 << 13);
-        mdio_patch(ioaddr, 0x10, 1 << 15);
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_patchphy(tp, 0x11, 1 << 12);
+        rtl_patchphy(tp, 0x19, 1 << 13);
+        rtl_patchphy(tp, 0x10, 1 << 15);
 
-        rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
+        rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 }
 
 static void rtl_hw_phy_config(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
-        void __iomem *ioaddr = tp->mmio_addr;
 
         rtl8169_print_mac_version(tp);
 
@@ -2653,58 +2428,61 @@ static void rtl_hw_phy_config(struct net_device *dev)
                 break;
         case RTL_GIGA_MAC_VER_02:
         case RTL_GIGA_MAC_VER_03:
-                rtl8169s_hw_phy_config(ioaddr);
+                rtl8169s_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_04:
-                rtl8169sb_hw_phy_config(ioaddr);
+                rtl8169sb_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_05:
-                rtl8169scd_hw_phy_config(tp, ioaddr);
+                rtl8169scd_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_06:
-                rtl8169sce_hw_phy_config(ioaddr);
+                rtl8169sce_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_07:
         case RTL_GIGA_MAC_VER_08:
         case RTL_GIGA_MAC_VER_09:
-                rtl8102e_hw_phy_config(ioaddr);
+                rtl8102e_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_11:
-                rtl8168bb_hw_phy_config(ioaddr);
+                rtl8168bb_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_12:
-                rtl8168bef_hw_phy_config(ioaddr);
+                rtl8168bef_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_17:
-                rtl8168bef_hw_phy_config(ioaddr);
+                rtl8168bef_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_18:
-                rtl8168cp_1_hw_phy_config(ioaddr);
+                rtl8168cp_1_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_19:
-                rtl8168c_1_hw_phy_config(ioaddr);
+                rtl8168c_1_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_20:
-                rtl8168c_2_hw_phy_config(ioaddr);
+                rtl8168c_2_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_21:
-                rtl8168c_3_hw_phy_config(ioaddr);
+                rtl8168c_3_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_22:
-                rtl8168c_4_hw_phy_config(ioaddr);
+                rtl8168c_4_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_23:
         case RTL_GIGA_MAC_VER_24:
-                rtl8168cp_2_hw_phy_config(ioaddr);
+                rtl8168cp_2_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_25:
-                rtl8168d_1_hw_phy_config(ioaddr);
+                rtl8168d_1_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_26:
-                rtl8168d_2_hw_phy_config(ioaddr);
+                rtl8168d_2_hw_phy_config(tp);
                 break;
         case RTL_GIGA_MAC_VER_27:
-                rtl8168d_3_hw_phy_config(ioaddr);
+                rtl8168d_3_hw_phy_config(tp);
+                break;
+        case RTL_GIGA_MAC_VER_28:
+                rtl8168d_4_hw_phy_config(tp);
                 break;
 
         default:
@@ -2727,7 +2505,7 @@ static void rtl8169_phy_timer(unsigned long __opaque)
 
         spin_lock_irq(&tp->lock);
 
-        if (tp->phy_reset_pending(ioaddr)) {
+        if (tp->phy_reset_pending(tp)) {
                 /*
                  * A busy loop could burn quite a few cycles on nowadays CPU.
                  * Let's delay the execution of the timer for a few ticks.
@@ -2741,7 +2519,7 @@ static void rtl8169_phy_timer(unsigned long __opaque)
 
         netif_warn(tp, link, dev, "PHY reset until link up\n");
 
-        tp->phy_reset_enable(ioaddr);
+        tp->phy_reset_enable(tp);
 
 out_mod_timer:
         mod_timer(timer, jiffies + timeout);
@@ -2801,12 +2579,11 @@ static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
 static void rtl8169_phy_reset(struct net_device *dev,
                               struct rtl8169_private *tp)
 {
-        void __iomem *ioaddr = tp->mmio_addr;
         unsigned int i;
 
-        tp->phy_reset_enable(ioaddr);
+        tp->phy_reset_enable(tp);
         for (i = 0; i < 100; i++) {
-                if (!tp->phy_reset_pending(ioaddr))
+                if (!tp->phy_reset_pending(tp))
                         return;
                 msleep(1);
         }
@@ -2833,7 +2610,7 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
                 RTL_W8(0x82, 0x01);
                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
-                mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
+                rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
         }
 
         rtl8169_phy_reset(dev, tp);
@@ -2903,11 +2680,11 @@ static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *dat
                 return 0;
 
         case SIOCGMIIREG:
-                data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
+                data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
                 return 0;
 
         case SIOCSMIIREG:
-                mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
+                rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
                 return 0;
         }
         return -EOPNOTSUPP;
@@ -3007,6 +2784,173 @@ static const struct net_device_ops rtl8169_netdev_ops = {
 
 };
 
+static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
+{
+        struct mdio_ops *ops = &tp->mdio_ops;
+
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_27:
+                ops->write      = r8168dp_1_mdio_write;
+                ops->read       = r8168dp_1_mdio_read;
+                break;
+        case RTL_GIGA_MAC_VER_28:
+                ops->write      = r8168dp_2_mdio_write;
+                ops->read       = r8168dp_2_mdio_read;
+                break;
+        default:
+                ops->write      = r8169_mdio_write;
+                ops->read       = r8169_mdio_read;
+                break;
+        }
+}
+
+static void r810x_phy_power_down(struct rtl8169_private *tp)
+{
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
+}
+
+static void r810x_phy_power_up(struct rtl8169_private *tp)
+{
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
+}
+
+static void r810x_pll_power_down(struct rtl8169_private *tp)
+{
+        if (__rtl8169_get_wol(tp) & WAKE_ANY) {
+                rtl_writephy(tp, 0x1f, 0x0000);
+                rtl_writephy(tp, MII_BMCR, 0x0000);
+                return;
+        }
+
+        r810x_phy_power_down(tp);
+}
+
+static void r810x_pll_power_up(struct rtl8169_private *tp)
+{
+        r810x_phy_power_up(tp);
+}
+
+static void r8168_phy_power_up(struct rtl8169_private *tp)
+{
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_writephy(tp, 0x0e, 0x0000);
+        rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
+}
+
+static void r8168_phy_power_down(struct rtl8169_private *tp)
+{
+        rtl_writephy(tp, 0x1f, 0x0000);
+        rtl_writephy(tp, 0x0e, 0x0200);
+        rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
+}
+
+static void r8168_pll_power_down(struct rtl8169_private *tp)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+
+        if (tp->mac_version == RTL_GIGA_MAC_VER_27)
+                return;
+
+        if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
+             (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
+            (RTL_R16(CPlusCmd) & ASF)) {
+                return;
+        }
+
+        if (__rtl8169_get_wol(tp) & WAKE_ANY) {
+                rtl_writephy(tp, 0x1f, 0x0000);
+                rtl_writephy(tp, MII_BMCR, 0x0000);
+
+                RTL_W32(RxConfig, RTL_R32(RxConfig) |
+                        AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
+                return;
+        }
+
+        r8168_phy_power_down(tp);
+
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_25:
+        case RTL_GIGA_MAC_VER_26:
+                RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
+                break;
+        }
+}
+
+static void r8168_pll_power_up(struct rtl8169_private *tp)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+
+        if (tp->mac_version == RTL_GIGA_MAC_VER_27)
+                return;
+
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_25:
+        case RTL_GIGA_MAC_VER_26:
+                RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
+                break;
+        }
+
+        r8168_phy_power_up(tp);
+}
+
+static void rtl_pll_power_op(struct rtl8169_private *tp,
+                             void (*op)(struct rtl8169_private *))
+{
+        if (op)
+                op(tp);
+}
+
+static void rtl_pll_power_down(struct rtl8169_private *tp)
+{
+        rtl_pll_power_op(tp, tp->pll_power_ops.down);
+}
+
+static void rtl_pll_power_up(struct rtl8169_private *tp)
+{
+        rtl_pll_power_op(tp, tp->pll_power_ops.up);
+}
+
+static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
+{
+        struct pll_power_ops *ops = &tp->pll_power_ops;
+
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_07:
+        case RTL_GIGA_MAC_VER_08:
+        case RTL_GIGA_MAC_VER_09:
+        case RTL_GIGA_MAC_VER_10:
+        case RTL_GIGA_MAC_VER_16:
+                ops->down       = r810x_pll_power_down;
+                ops->up         = r810x_pll_power_up;
+                break;
+
+        case RTL_GIGA_MAC_VER_11:
+        case RTL_GIGA_MAC_VER_12:
+        case RTL_GIGA_MAC_VER_17:
+        case RTL_GIGA_MAC_VER_18:
+        case RTL_GIGA_MAC_VER_19:
+        case RTL_GIGA_MAC_VER_20:
+        case RTL_GIGA_MAC_VER_21:
+        case RTL_GIGA_MAC_VER_22:
+        case RTL_GIGA_MAC_VER_23:
+        case RTL_GIGA_MAC_VER_24:
+        case RTL_GIGA_MAC_VER_25:
+        case RTL_GIGA_MAC_VER_26:
+        case RTL_GIGA_MAC_VER_27:
+        case RTL_GIGA_MAC_VER_28:
+                ops->down       = r8168_pll_power_down;
+                ops->up         = r8168_pll_power_up;
+                break;
+
+        default:
+                ops->down       = NULL;
+                ops->up         = NULL;
+                break;
+        }
+}
+
 static int __devinit
 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 {
@@ -3125,6 +3069,9 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         /* Identify chip attached to board */
         rtl8169_get_mac_version(tp, ioaddr);
 
+        rtl_init_mdio_ops(tp);
+        rtl_init_pll_power_ops(tp);
+
         /* Use appropriate default if unknown */
         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
                 netif_notice(tp, probe, dev,
@@ -3215,14 +3162,10 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
                    dev->base_addr, dev->dev_addr,
                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
 
-        rtl8169_init_phy(dev, tp);
-
-        /*
-         * Pretend we are using VLANs; This bypasses a nasty bug where
-         * Interrupts stop flowing on high load on 8110SCd controllers.
-         */
-        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
-                RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
+        if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
+            (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
+                rtl8168_driver_start(tp);
+        }
 
         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
 
@@ -3250,7 +3193,12 @@ static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
         struct net_device *dev = pci_get_drvdata(pdev);
         struct rtl8169_private *tp = netdev_priv(dev);
 
-        flush_scheduled_work();
+        if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
+            (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
+                rtl8168_driver_stop(tp);
+        }
+
+        cancel_delayed_work_sync(&tp->task);
 
         unregister_netdev(dev);
 
@@ -3268,6 +3216,7 @@ static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
 static int rtl8169_open(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
+        void __iomem *ioaddr = tp->mmio_addr;
         struct pci_dev *pdev = tp->pci_dev;
         int retval = -ENOMEM;
 
@@ -3303,6 +3252,17 @@ static int rtl8169_open(struct net_device *dev)
 
         napi_enable(&tp->napi);
 
+        rtl8169_init_phy(dev, tp);
+
+        /*
+         * Pretend we are using VLANs; This bypasses a nasty bug where
+         * Interrupts stop flowing on high load on 8110SCd controllers.
+         */
+        if (tp->mac_version == RTL_GIGA_MAC_VER_05)
+                RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
+
+        rtl_pll_power_up(tp);
+
         rtl_hw_start(dev);
 
         rtl8169_request_timer(dev);
@@ -3310,7 +3270,7 @@ static int rtl8169_open(struct net_device *dev)
         tp->saved_wolopts = 0;
         pm_runtime_put_noidle(&pdev->dev);
 
-        rtl8169_check_link_status(dev, tp, tp->mmio_addr);
+        rtl8169_check_link_status(dev, tp, ioaddr);
 out:
         return retval;
 
@@ -3329,11 +3289,19 @@ err_pm_runtime_put:
         goto out;
 }
 
-static void rtl8169_hw_reset(void __iomem *ioaddr)
+static void rtl8169_hw_reset(struct rtl8169_private *tp)
 {
+        void __iomem *ioaddr = tp->mmio_addr;
+
         /* Disable interrupts */
         rtl8169_irq_mask_and_ack(ioaddr);
 
+        if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
+                while (RTL_R8(TxPoll) & NPQ)
+                        udelay(20);
+
+        }
+
         /* Reset the chipset */
         RTL_W8(ChipCmd, CmdReset);
 
@@ -3447,7 +3415,7 @@ static void rtl_hw_start_8169(struct net_device *dev)
             (tp->mac_version == RTL_GIGA_MAC_VER_04))
                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 
-        RTL_W8(EarlyTxThres, EarlyTxThld);
+        RTL_W8(EarlyTxThres, NoEarlyTx);
 
         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
 
@@ -3517,12 +3485,22 @@ static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
         }
 }
 
-static void rtl_csi_access_enable(void __iomem *ioaddr)
+static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
 {
         u32 csi;
 
         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
-        rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
+        rtl_csi_write(ioaddr, 0x070c, csi | bits);
+}
+
+static void rtl_csi_access_enable_1(void __iomem *ioaddr)
+{
+        rtl_csi_access_enable(ioaddr, 0x17000000);
+}
+
+static void rtl_csi_access_enable_2(void __iomem *ioaddr)
+{
+        rtl_csi_access_enable(ioaddr, 0x27000000);
 }
 
 struct ephy_info {
@@ -3557,6 +3535,21 @@ static void rtl_disable_clock_request(struct pci_dev *pdev)
         }
 }
 
+static void rtl_enable_clock_request(struct pci_dev *pdev)
+{
+        struct net_device *dev = pci_get_drvdata(pdev);
+        struct rtl8169_private *tp = netdev_priv(dev);
+        int cap = tp->pcie_cap;
+
+        if (cap) {
+                u16 ctl;
+
+                pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
+                ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
+                pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
+        }
+}
+
 #define R8168_CPCMD_QUIRK_MASK (\
         EnableBist | \
         Mac_dbgo_oe | \
@@ -3582,7 +3575,7 @@ static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
 {
         rtl_hw_start_8168bb(ioaddr, pdev);
 
-        RTL_W8(EarlyTxThres, EarlyTxThld);
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
 
         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
 }
@@ -3610,7 +3603,7 @@ static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
                 { 0x07, 0,      0x2000 }
         };
 
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
 
@@ -3619,7 +3612,7 @@ static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
 
 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
 {
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
 
@@ -3630,14 +3623,14 @@ static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
 
 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
 {
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
 
         /* Magic. */
         RTL_W8(DBG_REG, 0x20);
 
-        RTL_W8(EarlyTxThres, EarlyTxThld);
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
 
         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
 
@@ -3652,7 +3645,7 @@ static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
                 { 0x06, 0x0080, 0x0000 }
         };
 
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
 
@@ -3668,7 +3661,7 @@ static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
                 { 0x03, 0x0400, 0x0220 }
         };
 
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
 
@@ -3682,24 +3675,50 @@ static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
 
 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
 {
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         __rtl_hw_start_8168cp(ioaddr, pdev);
 }
 
 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
 {
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         rtl_disable_clock_request(pdev);
 
-        RTL_W8(EarlyTxThres, EarlyTxThld);
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
 
         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
 
         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
 }
 
+static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
+{
+        static const struct ephy_info e_info_8168d_4[] = {
+                { 0x0b, ~0,     0x48 },
+                { 0x19, 0x20,   0x50 },
+                { 0x0c, ~0,     0x20 }
+        };
+        int i;
+
+        rtl_csi_access_enable_1(ioaddr);
+
+        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
+
+        for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
+                const struct ephy_info *e = e_info_8168d_4 + i;
+                u16 w;
+
+                w = rtl_ephy_read(ioaddr, e->offset);
+                rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
+        }
+
+        rtl_enable_clock_request(pdev);
+}
+
 static void rtl_hw_start_8168(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
@@ -3708,7 +3727,7 @@ static void rtl_hw_start_8168(struct net_device *dev)
 
         RTL_W8(Cfg9346, Cfg9346_Unlock);
 
-        RTL_W8(EarlyTxThres, EarlyTxThld);
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
 
         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
 
@@ -3777,6 +3796,10 @@ static void rtl_hw_start_8168(struct net_device *dev)
                 rtl_hw_start_8168d(ioaddr, pdev);
         break;
 
+        case RTL_GIGA_MAC_VER_28:
+                rtl_hw_start_8168d_4(ioaddr, pdev);
+        break;
+
         default:
                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
                         dev->name, tp->mac_version);
@@ -3818,7 +3841,7 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
         };
         u8 cfg1;
 
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         RTL_W8(DBG_REG, FIX_NAK_1);
 
@@ -3839,7 +3862,7 @@ static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
 
 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
 {
-        rtl_csi_access_enable(ioaddr);
+        rtl_csi_access_enable_2(ioaddr);
 
         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
 
@@ -3888,7 +3911,7 @@ static void rtl_hw_start_8101(struct net_device *dev)
 
         RTL_W8(Cfg9346, Cfg9346_Unlock);
 
-        RTL_W8(EarlyTxThres, EarlyTxThld);
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
 
         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
 
@@ -4189,7 +4212,7 @@ static void rtl8169_tx_timeout(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
 
-        rtl8169_hw_reset(tp->mmio_addr);
+        rtl8169_hw_reset(tp);
 
         /* Let's wait a bit while any (async) irq lands on */
         rtl8169_schedule_work(dev, rtl8169_reset_task);
@@ -4347,7 +4370,6 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
         struct pci_dev *pdev = tp->pci_dev;
-        void __iomem *ioaddr = tp->mmio_addr;
         u16 pci_status, pci_cmd;
 
         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
@@ -4378,13 +4400,15 @@ static void rtl8169_pcierr_interrupt(struct net_device *dev)
 
         /* The infamous DAC f*ckup only happens at boot time */
         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
+                void __iomem *ioaddr = tp->mmio_addr;
+
                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
                 tp->cp_cmd &= ~PCIDAC;
                 RTL_W16(CPlusCmd, tp->cp_cmd);
                 dev->features &= ~NETIF_F_HIGHDMA;
         }
 
-        rtl8169_hw_reset(ioaddr);
+        rtl8169_hw_reset(tp);
 
         rtl8169_schedule_work(dev, rtl8169_reinit_task);
 }
@@ -4711,6 +4735,8 @@ static void rtl8169_down(struct net_device *dev)
         rtl8169_tx_clear(tp);
 
         rtl8169_rx_clear(tp);
+
+        rtl_pll_power_down(tp);
 }
 
 static int rtl8169_close(struct net_device *dev)
@@ -4815,9 +4841,13 @@ static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
 
 static void rtl8169_net_suspend(struct net_device *dev)
 {
+        struct rtl8169_private *tp = netdev_priv(dev);
+
         if (!netif_running(dev))
                 return;
 
+        rtl_pll_power_down(tp);
+
         netif_device_detach(dev);
         netif_stop_queue(dev);
 }
@@ -4836,7 +4866,12 @@ static int rtl8169_suspend(struct device *device)
 
 static void __rtl8169_resume(struct net_device *dev)
 {
+        struct rtl8169_private *tp = netdev_priv(dev);
+
         netif_device_attach(dev);
+
+        rtl_pll_power_up(tp);
+
         rtl8169_schedule_work(dev, rtl8169_reset_task);
 }
 
diff --git a/drivers/net/s2io.c b/drivers/net/s2io.c
index ecc25aab896a..39c17cecb8b9 100644
--- a/drivers/net/s2io.c
+++ b/drivers/net/s2io.c
@@ -88,14 +88,14 @@
 #include "s2io.h"
 #include "s2io-regs.h"
 
-#define DRV_VERSION "2.0.26.27"
+#define DRV_VERSION "2.0.26.28"
 
 /* S2io Driver name & version. */
-static char s2io_driver_name[] = "Neterion";
-static char s2io_driver_version[] = DRV_VERSION;
+static const char s2io_driver_name[] = "Neterion";
+static const char s2io_driver_version[] = DRV_VERSION;
 
-static int rxd_size[2] = {32, 48};
-static int rxd_count[2] = {127, 85};
+static const int rxd_size[2] = {32, 48};
+static const int rxd_count[2] = {127, 85};
 
 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
 {
@@ -3598,10 +3598,12 @@ static int s2io_set_swapper(struct s2io_nic *sp)
         val64 = readq(&bar0->pif_rd_swapper_fb);
         if (val64 != 0x0123456789ABCDEFULL) {
                 int i = 0;
-                u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
-                                0x8100008181000081ULL,  /* FE=1, SE=0 */
-                                0x4200004242000042ULL,  /* FE=0, SE=1 */
-                                0};                     /* FE=0, SE=0 */
+                static const u64 value[] = {
+                        0xC30000C3C30000C3ULL,  /* FE=1, SE=1 */
+                        0x8100008181000081ULL,  /* FE=1, SE=0 */
+                        0x4200004242000042ULL,  /* FE=0, SE=1 */
+                        0                       /* FE=0, SE=0 */
+                };
 
                 while (i < 4) {
                         writeq(value[i], &bar0->swapper_ctrl);
@@ -3627,10 +3629,12 @@ static int s2io_set_swapper(struct s2io_nic *sp)
 
         if (val64 != valt) {
                 int i = 0;
-                u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
-                                0x0081810000818100ULL,  /* FE=1, SE=0 */
-                                0x0042420000424200ULL,  /* FE=0, SE=1 */
-                                0};                     /* FE=0, SE=0 */
+                static const u64 value[] = {
+                        0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
+                        0x0081810000818100ULL,  /* FE=1, SE=0 */
+                        0x0042420000424200ULL,  /* FE=0, SE=1 */
+                        0                       /* FE=0, SE=0 */
+                };
 
                 while (i < 4) {
                         writeq((value[i] | valr), &bar0->swapper_ctrl);
@@ -5568,30 +5572,27 @@ static void s2io_ethtool_gringparam(struct net_device *dev,
         struct s2io_nic *sp = netdev_priv(dev);
         int i, tx_desc_count = 0, rx_desc_count = 0;
 
-        if (sp->rxd_mode == RXD_MODE_1)
+        if (sp->rxd_mode == RXD_MODE_1) {
                 ering->rx_max_pending = MAX_RX_DESC_1;
-        else if (sp->rxd_mode == RXD_MODE_3B)
+                ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
+        } else {
                 ering->rx_max_pending = MAX_RX_DESC_2;
+                ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
+        }
 
+        ering->rx_mini_max_pending = 0;
         ering->tx_max_pending = MAX_TX_DESC;
-        for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
-                tx_desc_count += sp->config.tx_cfg[i].fifo_len;
 
-        DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
-        ering->tx_pending = tx_desc_count;
-        rx_desc_count = 0;
-        for (i = 0 ; i < sp->config.rx_ring_num ; i++)
+        for (i = 0; i < sp->config.rx_ring_num; i++)
                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
-
         ering->rx_pending = rx_desc_count;
-
-        ering->rx_mini_max_pending = 0;
-        ering->rx_mini_pending = 0;
-        if (sp->rxd_mode == RXD_MODE_1)
-                ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
-        else if (sp->rxd_mode == RXD_MODE_3B)
-                ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
         ering->rx_jumbo_pending = rx_desc_count;
+        ering->rx_mini_pending = 0;
+
+        for (i = 0; i < sp->config.tx_fifo_num; i++)
+                tx_desc_count += sp->config.tx_cfg[i].fifo_len;
+        ering->tx_pending = tx_desc_count;
+        DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
 }
 
 /**
@@ -7692,6 +7693,8 @@ static void s2io_init_pci(struct s2io_nic *sp)
 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
                             u8 *dev_multiq)
 {
+        int i;
+
         if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
                 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
                           "(%d) not supported\n", tx_fifo_num);
@@ -7750,6 +7753,15 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
                 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
                 rx_ring_mode = 1;
         }
+
+        for (i = 0; i < MAX_RX_RINGS; i++)
+                if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
+                        DBG_PRINT(ERR_DBG, "Requested rx ring size not "
+                                  "supported\nDefaulting to %d\n",
+                                  MAX_RX_BLOCKS_PER_RING);
+                        rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
+                }
+
         return SUCCESS;
 }
 
@@ -8321,8 +8333,7 @@ mem_alloc_failed:
 
 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
 {
-        struct net_device *dev =
-                (struct net_device *)pci_get_drvdata(pdev);
+        struct net_device *dev = pci_get_drvdata(pdev);
         struct s2io_nic *sp;
 
         if (dev == NULL) {
@@ -8330,9 +8341,11 @@ static void __devexit s2io_rem_nic(struct pci_dev *pdev)
                 return;
         }
 
-        flush_scheduled_work();
-
         sp = netdev_priv(dev);
+
+        cancel_work_sync(&sp->rst_timer_task);
+        cancel_work_sync(&sp->set_link_task);
+
         unregister_netdev(dev);
 
         free_shared_mem(sp);
diff --git a/drivers/net/s2io.h b/drivers/net/s2io.h
index 00b8614efe48..7d160306b651 100644
--- a/drivers/net/s2io.h
+++ b/drivers/net/s2io.h
@@ -355,13 +355,12 @@ struct stat_block {
 #define FIFO_OTHER_MAX_NUM                      1
 
 
-#define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 )
-#define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
-#define MAX_RX_DESC_3  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 )
+#define MAX_RX_DESC_1  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128)
+#define MAX_RX_DESC_2  (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86)
 #define MAX_TX_DESC    (MAX_AVAILABLE_TXDS)
 
 /* FIFO mappings for all possible number of fifos configured */
-static int fifo_map[][MAX_TX_FIFOS] = {
+static const int fifo_map[][MAX_TX_FIFOS] = {
         {0, 0, 0, 0, 0, 0, 0, 0},
         {0, 0, 0, 0, 1, 1, 1, 1},
         {0, 0, 0, 1, 1, 1, 2, 2},
@@ -372,7 +371,7 @@ static int fifo_map[][MAX_TX_FIFOS] = {
         {0, 1, 2, 3, 4, 5, 6, 7},
 };
 
-static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
+static const u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7};
 
 /* Maintains Per FIFO related information. */
 struct tx_fifo_config {
diff --git a/drivers/net/sc92031.c b/drivers/net/sc92031.c
index 417adf372828..76290a8c3c14 100644
--- a/drivers/net/sc92031.c
+++ b/drivers/net/sc92031.c
@@ -1449,7 +1449,8 @@ static int __devinit sc92031_probe(struct pci_dev *pdev,
         dev->irq = pdev->irq;
 
         /* faked with skb_copy_and_csum_dev */
-        dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
+        dev->features = NETIF_F_SG | NETIF_F_HIGHDMA |
+                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
 
         dev->netdev_ops         = &sc92031_netdev_ops;
         dev->watchdog_timeo     = TX_TIMEOUT;
diff --git a/drivers/net/sfc/efx.c b/drivers/net/sfc/efx.c
index fb83cdd94643..711449c6e675 100644
--- a/drivers/net/sfc/efx.c
+++ b/drivers/net/sfc/efx.c
@@ -23,7 +23,6 @@
 #include <linux/gfp.h>
 #include "net_driver.h"
 #include "efx.h"
-#include "mdio_10g.h"
 #include "nic.h"
 
 #include "mcdi.h"
@@ -462,9 +461,6 @@ efx_alloc_channel(struct efx_nic *efx, int i, struct efx_channel *old_channel)
                 }
         }
 
-        spin_lock_init(&channel->tx_stop_lock);
-        atomic_set(&channel->tx_stop_count, 1);
-
         rx_queue = &channel->rx_queue;
         rx_queue->efx = efx;
         setup_timer(&rx_queue->slow_fill, efx_rx_slow_fill,
@@ -921,6 +917,7 @@ static void efx_mac_work(struct work_struct *data)
 
 static int efx_probe_port(struct efx_nic *efx)
 {
+        unsigned char *perm_addr;
         int rc;
 
         netif_dbg(efx, probe, efx->net_dev, "create port\n");
@@ -934,11 +931,12 @@ static int efx_probe_port(struct efx_nic *efx)
                 return rc;
 
         /* Sanity check MAC address */
-        if (is_valid_ether_addr(efx->mac_address)) {
-                memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN);
+        perm_addr = efx->net_dev->perm_addr;
+        if (is_valid_ether_addr(perm_addr)) {
+                memcpy(efx->net_dev->dev_addr, perm_addr, ETH_ALEN);
         } else {
                 netif_err(efx, probe, efx->net_dev, "invalid MAC address %pM\n",
-                          efx->mac_address);
+                          perm_addr);
                 if (!allow_bad_hwaddr) {
                         rc = -EINVAL;
                         goto err;
@@ -1405,11 +1403,11 @@ static void efx_start_all(struct efx_nic *efx)
          * restart the transmit interface early so the watchdog timer stops */
         efx_start_port(efx);
 
-        efx_for_each_channel(channel, efx) {
-                if (efx_dev_registered(efx))
-                        efx_wake_queue(channel);
+        if (efx_dev_registered(efx))
+                netif_tx_wake_all_queues(efx->net_dev);
+
+        efx_for_each_channel(channel, efx)
                 efx_start_channel(channel);
-        }
 
         if (efx->legacy_irq)
                 efx->legacy_irq_enabled = true;
@@ -1497,9 +1495,7 @@ static void efx_stop_all(struct efx_nic *efx)
         /* Stop the kernel transmit interface late, so the watchdog
          * timer isn't ticking over the flush */
         if (efx_dev_registered(efx)) {
-                struct efx_channel *channel;
-                efx_for_each_channel(channel, efx)
-                        efx_stop_queue(channel);
+                netif_tx_stop_all_queues(efx->net_dev);
                 netif_tx_lock_bh(efx->net_dev);
                 netif_tx_unlock_bh(efx->net_dev);
         }
@@ -1895,6 +1891,7 @@ static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
 static int efx_register_netdev(struct efx_nic *efx)
 {
         struct net_device *net_dev = efx->net_dev;
+        struct efx_channel *channel;
         int rc;
 
         net_dev->watchdog_timeo = 5 * HZ;
@@ -1917,6 +1914,14 @@ static int efx_register_netdev(struct efx_nic *efx)
         if (rc)
                 goto fail_locked;
 
+        efx_for_each_channel(channel, efx) {
+                struct efx_tx_queue *tx_queue;
+                efx_for_each_channel_tx_queue(tx_queue, channel) {
+                        tx_queue->core_txq = netdev_get_tx_queue(
+                                efx->net_dev, tx_queue->queue / EFX_TXQ_TYPES);
+                }
+        }
+
         /* Always start with carrier off; PHY events will detect the link */
         netif_carrier_off(efx->net_dev);
 
@@ -1980,7 +1985,6 @@ void efx_reset_down(struct efx_nic *efx, enum reset_type method)
 
         efx_stop_all(efx);
         mutex_lock(&efx->mac_lock);
-        mutex_lock(&efx->spi_lock);
 
         efx_fini_channels(efx);
         if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
@@ -2022,7 +2026,6 @@ int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
         efx_init_channels(efx);
         efx_restore_filters(efx);
 
-        mutex_unlock(&efx->spi_lock);
         mutex_unlock(&efx->mac_lock);
 
         efx_start_all(efx);
@@ -2032,7 +2035,6 @@ int efx_reset_up(struct efx_nic *efx, enum reset_type method, bool ok)
 fail:
         efx->port_initialized = false;
 
-        mutex_unlock(&efx->spi_lock);
         mutex_unlock(&efx->mac_lock);
 
         return rc;
@@ -2220,8 +2222,6 @@ static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
         /* Initialise common structures */
         memset(efx, 0, sizeof(*efx));
         spin_lock_init(&efx->biu_lock);
-        mutex_init(&efx->mdio_lock);
-        mutex_init(&efx->spi_lock);
 #ifdef CONFIG_SFC_MTD
         INIT_LIST_HEAD(&efx->mtd_list);
 #endif
diff --git a/drivers/net/sfc/efx.h b/drivers/net/sfc/efx.h
index 10a1bf40da96..d43a7e5212b1 100644
--- a/drivers/net/sfc/efx.h
+++ b/drivers/net/sfc/efx.h
@@ -36,8 +36,6 @@ efx_hard_start_xmit(struct sk_buff *skb, struct net_device *net_dev);
 extern netdev_tx_t
 efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb);
 extern void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index);
-extern void efx_stop_queue(struct efx_channel *channel);
-extern void efx_wake_queue(struct efx_channel *channel);
 
 /* RX */
 extern int efx_probe_rx_queue(struct efx_rx_queue *rx_queue);
@@ -74,9 +72,8 @@ extern int efx_filter_insert_filter(struct efx_nic *efx,
                                     bool replace);
 extern int efx_filter_remove_filter(struct efx_nic *efx,
                                     struct efx_filter_spec *spec);
-extern void efx_filter_table_clear(struct efx_nic *efx,
-                                   enum efx_filter_table_id table_id,
-                                   enum efx_filter_priority priority);
+extern void efx_filter_clear_rx(struct efx_nic *efx,
+                                enum efx_filter_priority priority);
 
 /* Channels */
 extern void efx_process_channel_now(struct efx_channel *channel);
diff --git a/drivers/net/sfc/ethtool.c b/drivers/net/sfc/ethtool.c
index edb9d16b8b47..0e8bb19ed60d 100644
--- a/drivers/net/sfc/ethtool.c
+++ b/drivers/net/sfc/ethtool.c
@@ -11,14 +11,13 @@
 #include <linux/netdevice.h>
 #include <linux/ethtool.h>
 #include <linux/rtnetlink.h>
+#include <linux/in.h>
 #include "net_driver.h"
 #include "workarounds.h"
 #include "selftest.h"
 #include "efx.h"
 #include "filter.h"
 #include "nic.h"
-#include "spi.h"
-#include "mdio_10g.h"
 
 struct ethtool_string {
         char name[ETH_GSTRING_LEN];
@@ -560,12 +559,8 @@ static int efx_ethtool_set_flags(struct net_device *net_dev, u32 data)
         if (rc)
                 return rc;
 
-        if (!(data & ETH_FLAG_NTUPLE)) {
-                efx_filter_table_clear(efx, EFX_FILTER_TABLE_RX_IP,
-                                       EFX_FILTER_PRI_MANUAL);
-                efx_filter_table_clear(efx, EFX_FILTER_TABLE_RX_MAC,
-                                       EFX_FILTER_PRI_MANUAL);
-        }
+        if (!(data & ETH_FLAG_NTUPLE))
+                efx_filter_clear_rx(efx, EFX_FILTER_PRI_MANUAL);
 
         return 0;
 }
@@ -584,6 +579,9 @@ static void efx_ethtool_self_test(struct net_device *net_dev,
                 goto fail1;
         }
 
+        netif_info(efx, drv, efx->net_dev, "starting %sline testing\n",
+                   (test->flags & ETH_TEST_FL_OFFLINE) ? "off" : "on");
+
         /* We need rx buffers and interrupts. */
         already_up = (efx->net_dev->flags & IFF_UP);
         if (!already_up) {
@@ -602,9 +600,9 @@ static void efx_ethtool_self_test(struct net_device *net_dev,
         if (!already_up)
                 dev_close(efx->net_dev);
 
-        netif_dbg(efx, drv, efx->net_dev, "%s %sline self-tests\n",
-                  rc == 0 ? "passed" : "failed",
-                  (test->flags & ETH_TEST_FL_OFFLINE) ? "off" : "on");
+        netif_info(efx, drv, efx->net_dev, "%s %sline self-tests\n",
+                   rc == 0 ? "passed" : "failed",
+                   (test->flags & ETH_TEST_FL_OFFLINE) ? "off" : "on");
 
  fail2:
  fail1:
@@ -622,68 +620,6 @@ static int efx_ethtool_nway_reset(struct net_device *net_dev)
         return mdio45_nway_restart(&efx->mdio);
 }
 
-static u32 efx_ethtool_get_link(struct net_device *net_dev)
-{
-        struct efx_nic *efx = netdev_priv(net_dev);
-
-        return efx->link_state.up;
-}
-
-static int efx_ethtool_get_eeprom_len(struct net_device *net_dev)
-{
-        struct efx_nic *efx = netdev_priv(net_dev);
-        struct efx_spi_device *spi = efx->spi_eeprom;
-
-        if (!spi)
-                return 0;
-        return min(spi->size, EFX_EEPROM_BOOTCONFIG_END) -
-                min(spi->size, EFX_EEPROM_BOOTCONFIG_START);
-}
-
-static int efx_ethtool_get_eeprom(struct net_device *net_dev,
-                                  struct ethtool_eeprom *eeprom, u8 *buf)
-{
-        struct efx_nic *efx = netdev_priv(net_dev);
-        struct efx_spi_device *spi = efx->spi_eeprom;
-        size_t len;
-        int rc;
-
-        rc = mutex_lock_interruptible(&efx->spi_lock);
-        if (rc)
-                return rc;
-        rc = falcon_spi_read(efx, spi,
-                             eeprom->offset + EFX_EEPROM_BOOTCONFIG_START,
-                             eeprom->len, &len, buf);
-        mutex_unlock(&efx->spi_lock);
-
-        eeprom->magic = EFX_ETHTOOL_EEPROM_MAGIC;
-        eeprom->len = len;
-        return rc;
-}
-
-static int efx_ethtool_set_eeprom(struct net_device *net_dev,
-                                  struct ethtool_eeprom *eeprom, u8 *buf)
-{
-        struct efx_nic *efx = netdev_priv(net_dev);
-        struct efx_spi_device *spi = efx->spi_eeprom;
-        size_t len;
-        int rc;
-
-        if (eeprom->magic != EFX_ETHTOOL_EEPROM_MAGIC)
-                return -EINVAL;
-
-        rc = mutex_lock_interruptible(&efx->spi_lock);
-        if (rc)
-                return rc;
-        rc = falcon_spi_write(efx, spi,
-                              eeprom->offset + EFX_EEPROM_BOOTCONFIG_START,
-                              eeprom->len, &len, buf);
-        mutex_unlock(&efx->spi_lock);
-
-        eeprom->len = len;
-        return rc;
-}
-
 static int efx_ethtool_get_coalesce(struct net_device *net_dev,
                                     struct ethtool_coalesce *coalesce)
 {
@@ -978,6 +914,7 @@ static int efx_ethtool_set_rx_ntuple(struct net_device *net_dev,
         struct ethhdr *mac_entry = &ntuple->fs.h_u.ether_spec;
         struct ethhdr *mac_mask = &ntuple->fs.m_u.ether_spec;
         struct efx_filter_spec filter;
+        int rc;
 
         /* Range-check action */
         if (ntuple->fs.action < ETHTOOL_RXNTUPLE_ACTION_CLEAR ||
@@ -987,9 +924,16 @@ static int efx_ethtool_set_rx_ntuple(struct net_device *net_dev,
         if (~ntuple->fs.data_mask)
                 return -EINVAL;
 
+        efx_filter_init_rx(&filter, EFX_FILTER_PRI_MANUAL, 0,
+                           (ntuple->fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP) ?
+                           0xfff : ntuple->fs.action);
+
         switch (ntuple->fs.flow_type) {
         case TCP_V4_FLOW:
-        case UDP_V4_FLOW:
+        case UDP_V4_FLOW: {
+                u8 proto = (ntuple->fs.flow_type == TCP_V4_FLOW ?
+                            IPPROTO_TCP : IPPROTO_UDP);
+
                 /* Must match all of destination, */
                 if (ip_mask->ip4dst | ip_mask->pdst)
                         return -EINVAL;
@@ -1001,7 +945,22 @@ static int efx_ethtool_set_rx_ntuple(struct net_device *net_dev,
                 /* and nothing else */
                 if ((u8)~ip_mask->tos | (u16)~ntuple->fs.vlan_tag_mask)
                         return -EINVAL;
+
+                if (!ip_mask->ip4src)
+                        rc = efx_filter_set_ipv4_full(&filter, proto,
+                                                      ip_entry->ip4dst,
+                                                      ip_entry->pdst,
+                                                      ip_entry->ip4src,
+                                                      ip_entry->psrc);
+                else
+                        rc = efx_filter_set_ipv4_local(&filter, proto,
+                                                       ip_entry->ip4dst,
+                                                       ip_entry->pdst);
+                if (rc)
+                        return rc;
                 break;
+        }
+
         case ETHER_FLOW:
                 /* Must match all of destination, */
                 if (!is_zero_ether_addr(mac_mask->h_dest))
@@ -1014,58 +973,24 @@ static int efx_ethtool_set_rx_ntuple(struct net_device *net_dev,
                 if (!is_broadcast_ether_addr(mac_mask->h_source) ||
                     mac_mask->h_proto != htons(0xffff))
                         return -EINVAL;
+
+                rc = efx_filter_set_eth_local(
+                        &filter,
+                        (ntuple->fs.vlan_tag_mask == 0xf000) ?
+                        ntuple->fs.vlan_tag : EFX_FILTER_VID_UNSPEC,
+                        mac_entry->h_dest);
+                if (rc)
+                        return rc;
                 break;
+
         default:
                 return -EINVAL;
         }
 
-        filter.priority = EFX_FILTER_PRI_MANUAL;
-        filter.flags = 0;
-
-        switch (ntuple->fs.flow_type) {
-        case TCP_V4_FLOW:
-                if (!ip_mask->ip4src)
-                        efx_filter_set_rx_tcp_full(&filter,
-                                                   htonl(ip_entry->ip4src),
-                                                   htons(ip_entry->psrc),
-                                                   htonl(ip_entry->ip4dst),
-                                                   htons(ip_entry->pdst));
-                else
-                        efx_filter_set_rx_tcp_wild(&filter,
-                                                   htonl(ip_entry->ip4dst),
-                                                   htons(ip_entry->pdst));
-                break;
-        case UDP_V4_FLOW:
-                if (!ip_mask->ip4src)
-                        efx_filter_set_rx_udp_full(&filter,
-                                                   htonl(ip_entry->ip4src),
-                                                   htons(ip_entry->psrc),
-                                                   htonl(ip_entry->ip4dst),
-                                                   htons(ip_entry->pdst));
-                else
-                        efx_filter_set_rx_udp_wild(&filter,
-                                                   htonl(ip_entry->ip4dst),
-                                                   htons(ip_entry->pdst));
-                break;
-        case ETHER_FLOW:
-                if (ntuple->fs.vlan_tag_mask == 0xf000)
-                        efx_filter_set_rx_mac_full(&filter,
-                                                   ntuple->fs.vlan_tag & 0xfff,
-                                                   mac_entry->h_dest);
-                else
-                        efx_filter_set_rx_mac_wild(&filter, mac_entry->h_dest);
-                break;
-        }
-
-        if (ntuple->fs.action == ETHTOOL_RXNTUPLE_ACTION_CLEAR) {
+        if (ntuple->fs.action == ETHTOOL_RXNTUPLE_ACTION_CLEAR)
                 return efx_filter_remove_filter(efx, &filter);
-        } else {
-                if (ntuple->fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
-                        filter.dmaq_id = 0xfff;
-                else
-                        filter.dmaq_id = ntuple->fs.action;
+        else
                 return efx_filter_insert_filter(efx, &filter, true);
-        }
 }
 
 static int efx_ethtool_get_rxfh_indir(struct net_device *net_dev,
@@ -1115,10 +1040,7 @@ const struct ethtool_ops efx_ethtool_ops = {
         .get_msglevel           = efx_ethtool_get_msglevel,
         .set_msglevel           = efx_ethtool_set_msglevel,
         .nway_reset             = efx_ethtool_nway_reset,
-        .get_link               = efx_ethtool_get_link,
-        .get_eeprom_len         = efx_ethtool_get_eeprom_len,
-        .get_eeprom             = efx_ethtool_get_eeprom,
-        .set_eeprom             = efx_ethtool_set_eeprom,
+        .get_link               = ethtool_op_get_link,
         .get_coalesce           = efx_ethtool_get_coalesce,
         .set_coalesce           = efx_ethtool_set_coalesce,
         .get_ringparam          = efx_ethtool_get_ringparam,
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index 267019bb2b15..70e4f7dcce81 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -24,7 +24,6 @@
 #include "nic.h"
 #include "regs.h"
 #include "io.h"
-#include "mdio_10g.h"
 #include "phy.h"
 #include "workarounds.h"
 
@@ -255,7 +254,6 @@ int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
         /* Input validation */
         if (len > FALCON_SPI_MAX_LEN)
                 return -EINVAL;
-        BUG_ON(!mutex_is_locked(&efx->spi_lock));
 
         /* Check that previous command is not still running */
         rc = falcon_spi_poll(efx);
@@ -719,6 +717,7 @@ static int falcon_mdio_write(struct net_device *net_dev,
                              int prtad, int devad, u16 addr, u16 value)
 {
         struct efx_nic *efx = netdev_priv(net_dev);
+        struct falcon_nic_data *nic_data = efx->nic_data;
         efx_oword_t reg;
         int rc;
 
@@ -726,7 +725,7 @@ static int falcon_mdio_write(struct net_device *net_dev,
                    "writing MDIO %d register %d.%d with 0x%04x\n",
                     prtad, devad, addr, value);
 
-        mutex_lock(&efx->mdio_lock);
+        mutex_lock(&nic_data->mdio_lock);
 
         /* Check MDIO not currently being accessed */
         rc = falcon_gmii_wait(efx);
@@ -762,7 +761,7 @@ static int falcon_mdio_write(struct net_device *net_dev,
         }
 
 out:
-        mutex_unlock(&efx->mdio_lock);
+        mutex_unlock(&nic_data->mdio_lock);
         return rc;
 }
 
@@ -771,10 +770,11 @@ static int falcon_mdio_read(struct net_device *net_dev,
                             int prtad, int devad, u16 addr)
 {
         struct efx_nic *efx = netdev_priv(net_dev);
+        struct falcon_nic_data *nic_data = efx->nic_data;
         efx_oword_t reg;
         int rc;
 
-        mutex_lock(&efx->mdio_lock);
+        mutex_lock(&nic_data->mdio_lock);
 
         /* Check MDIO not currently being accessed */
         rc = falcon_gmii_wait(efx);
@@ -813,7 +813,7 @@ static int falcon_mdio_read(struct net_device *net_dev,
         }
 
 out:
-        mutex_unlock(&efx->mdio_lock);
+        mutex_unlock(&nic_data->mdio_lock);
         return rc;
 }
 
@@ -841,6 +841,7 @@ static int falcon_probe_port(struct efx_nic *efx)
         }
 
         /* Fill out MDIO structure and loopback modes */
+        mutex_init(&nic_data->mdio_lock);
         efx->mdio.mdio_read = falcon_mdio_read;
         efx->mdio.mdio_write = falcon_mdio_write;
         rc = efx->phy_op->probe(efx);
@@ -880,6 +881,41 @@ static void falcon_remove_port(struct efx_nic *efx)
         efx_nic_free_buffer(efx, &efx->stats_buffer);
 }
 
+/* Global events are basically PHY events */
+static bool
+falcon_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
+{
+        struct efx_nic *efx = channel->efx;
+        struct falcon_nic_data *nic_data = efx->nic_data;
+
+        if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
+            EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
+            EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR))
+                /* Ignored */
+                return true;
+
+        if ((efx_nic_rev(efx) == EFX_REV_FALCON_B0) &&
+            EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
+                nic_data->xmac_poll_required = true;
+                return true;
+        }
+
+        if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
+            EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
+            EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
+                netif_err(efx, rx_err, efx->net_dev,
+                          "channel %d seen global RX_RESET event. Resetting.\n",
+                          channel->channel);
+
+                atomic_inc(&efx->rx_reset);
+                efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
+                                   RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
+                return true;
+        }
+
+        return false;
+}
+
 /**************************************************************************
  *
  * Falcon test code
@@ -889,6 +925,7 @@ static void falcon_remove_port(struct efx_nic *efx)
 static int
 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
         struct falcon_nvconfig *nvconfig;
         struct efx_spi_device *spi;
         void *region;
@@ -896,8 +933,11 @@ falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
         __le16 *word, *limit;
         u32 csum;
 
-        spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
-        if (!spi)
+        if (efx_spi_present(&nic_data->spi_flash))
+                spi = &nic_data->spi_flash;
+        else if (efx_spi_present(&nic_data->spi_eeprom))
+                spi = &nic_data->spi_eeprom;
+        else
                 return -EINVAL;
 
         region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
@@ -905,12 +945,13 @@ falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
                 return -ENOMEM;
         nvconfig = region + FALCON_NVCONFIG_OFFSET;
 
-        mutex_lock(&efx->spi_lock);
+        mutex_lock(&nic_data->spi_lock);
         rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
-        mutex_unlock(&efx->spi_lock);
+        mutex_unlock(&nic_data->spi_lock);
         if (rc) {
                 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
-                          efx->spi_flash ? "flash" : "EEPROM");
+                          efx_spi_present(&nic_data->spi_flash) ?
+                          "flash" : "EEPROM");
                 rc = -EIO;
                 goto out;
         }
@@ -1012,7 +1053,7 @@ static int falcon_b0_test_registers(struct efx_nic *efx)
 
 /* Resets NIC to known state.  This routine must be called in process
  * context and is allowed to sleep. */
-static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
+static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
 {
         struct falcon_nic_data *nic_data = efx->nic_data;
         efx_oword_t glb_ctl_reg_ker;
@@ -1108,6 +1149,18 @@ fail5:
         return rc;
 }
 
+static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
+{
+        struct falcon_nic_data *nic_data = efx->nic_data;
+        int rc;
+
+        mutex_lock(&nic_data->spi_lock);
+        rc = __falcon_reset_hw(efx, method);
+        mutex_unlock(&nic_data->spi_lock);
+
+        return rc;
+}
+
 static void falcon_monitor(struct efx_nic *efx)
 {
         bool link_changed;
@@ -1189,16 +1242,11 @@ static int falcon_reset_sram(struct efx_nic *efx)
         return -ETIMEDOUT;
 }
 
-static int falcon_spi_device_init(struct efx_nic *efx,
-                                  struct efx_spi_device **spi_device_ret,
+static void falcon_spi_device_init(struct efx_nic *efx,
+                                  struct efx_spi_device *spi_device,
                                   unsigned int device_id, u32 device_type)
 {
-        struct efx_spi_device *spi_device;
-
         if (device_type != 0) {
-                spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
-                if (!spi_device)
-                        return -ENOMEM;
                 spi_device->device_id = device_id;
                 spi_device->size =
                         1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
@@ -1215,27 +1263,15 @@ static int falcon_spi_device_init(struct efx_nic *efx,
                         1 << SPI_DEV_TYPE_FIELD(device_type,
                                                 SPI_DEV_TYPE_BLOCK_SIZE);
         } else {
-                spi_device = NULL;
+                spi_device->size = 0;
         }
-
-        kfree(*spi_device_ret);
-        *spi_device_ret = spi_device;
-        return 0;
-}
-
-static void falcon_remove_spi_devices(struct efx_nic *efx)
-{
-        kfree(efx->spi_eeprom);
-        efx->spi_eeprom = NULL;
-        kfree(efx->spi_flash);
-        efx->spi_flash = NULL;
 }
 
 /* Extract non-volatile configuration */
 static int falcon_probe_nvconfig(struct efx_nic *efx)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
         struct falcon_nvconfig *nvconfig;
-        int board_rev;
         int rc;
 
         nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
@@ -1243,55 +1279,32 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
                 return -ENOMEM;
 
         rc = falcon_read_nvram(efx, nvconfig);
-        if (rc == -EINVAL) {
-                netif_err(efx, probe, efx->net_dev,
-                          "NVRAM is invalid therefore using defaults\n");
-                efx->phy_type = PHY_TYPE_NONE;
-                efx->mdio.prtad = MDIO_PRTAD_NONE;
-                board_rev = 0;
-                rc = 0;
-        } else if (rc) {
-                goto fail1;
-        } else {
-                struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
-                struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
-
-                efx->phy_type = v2->port0_phy_type;
-                efx->mdio.prtad = v2->port0_phy_addr;
-                board_rev = le16_to_cpu(v2->board_revision);
-
-                if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
-                        rc = falcon_spi_device_init(
-                                efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
-                                le32_to_cpu(v3->spi_device_type
-                                            [FFE_AB_SPI_DEVICE_FLASH]));
-                        if (rc)
-                                goto fail2;
-                        rc = falcon_spi_device_init(
-                                efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
-                                le32_to_cpu(v3->spi_device_type
-                                            [FFE_AB_SPI_DEVICE_EEPROM]));
-                        if (rc)
-                                goto fail2;
-                }
+        if (rc)
+                goto out;
+
+        efx->phy_type = nvconfig->board_v2.port0_phy_type;
+        efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr;
+
+        if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
+                falcon_spi_device_init(
+                        efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
+                        le32_to_cpu(nvconfig->board_v3
+                                    .spi_device_type[FFE_AB_SPI_DEVICE_FLASH]));
+                falcon_spi_device_init(
+                        efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
+                        le32_to_cpu(nvconfig->board_v3
+                                    .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM]));
         }
 
         /* Read the MAC addresses */
-        memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
+        memcpy(efx->net_dev->perm_addr, nvconfig->mac_address[0], ETH_ALEN);
 
         netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
                   efx->phy_type, efx->mdio.prtad);
 
-        rc = falcon_probe_board(efx, board_rev);
-        if (rc)
-                goto fail2;
-
-        kfree(nvconfig);
-        return 0;
-
- fail2:
-        falcon_remove_spi_devices(efx);
- fail1:
+        rc = falcon_probe_board(efx,
+                                le16_to_cpu(nvconfig->board_v2.board_revision));
+out:
         kfree(nvconfig);
         return rc;
 }
@@ -1299,6 +1312,7 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
 /* Probe all SPI devices on the NIC */
 static void falcon_probe_spi_devices(struct efx_nic *efx)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
         efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
         int boot_dev;
 
@@ -1327,12 +1341,14 @@ static void falcon_probe_spi_devices(struct efx_nic *efx)
                 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
         }
 
+        mutex_init(&nic_data->spi_lock);
+
         if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
-                falcon_spi_device_init(efx, &efx->spi_flash,
+                falcon_spi_device_init(efx, &nic_data->spi_flash,
                                        FFE_AB_SPI_DEVICE_FLASH,
                                        default_flash_type);
         if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
-                falcon_spi_device_init(efx, &efx->spi_eeprom,
+                falcon_spi_device_init(efx, &nic_data->spi_eeprom,
                                        FFE_AB_SPI_DEVICE_EEPROM,
                                        large_eeprom_type);
 }
@@ -1397,7 +1413,7 @@ static int falcon_probe_nic(struct efx_nic *efx)
         }
 
         /* Now we can reset the NIC */
-        rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
+        rc = __falcon_reset_hw(efx, RESET_TYPE_ALL);
         if (rc) {
                 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
                 goto fail3;
@@ -1419,8 +1435,11 @@ static int falcon_probe_nic(struct efx_nic *efx)
 
         /* Read in the non-volatile configuration */
         rc = falcon_probe_nvconfig(efx);
-        if (rc)
+        if (rc) {
+                if (rc == -EINVAL)
+                        netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n");
                 goto fail5;
+        }
 
         /* Initialise I2C adapter */
         board = falcon_board(efx);
@@ -1452,7 +1471,6 @@ static int falcon_probe_nic(struct efx_nic *efx)
         BUG_ON(i2c_del_adapter(&board->i2c_adap));
         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
  fail5:
-        falcon_remove_spi_devices(efx);
         efx_nic_free_buffer(efx, &efx->irq_status);
  fail4:
  fail3:
@@ -1606,10 +1624,9 @@ static void falcon_remove_nic(struct efx_nic *efx)
         BUG_ON(rc);
         memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
 
-        falcon_remove_spi_devices(efx);
         efx_nic_free_buffer(efx, &efx->irq_status);
 
-        falcon_reset_hw(efx, RESET_TYPE_ALL);
+        __falcon_reset_hw(efx, RESET_TYPE_ALL);
 
         /* Release the second function after the reset */
         if (nic_data->pci_dev2) {
@@ -1720,6 +1737,7 @@ struct efx_nic_type falcon_a1_nic_type = {
         .reset = falcon_reset_hw,
         .probe_port = falcon_probe_port,
         .remove_port = falcon_remove_port,
+        .handle_global_event = falcon_handle_global_event,
         .prepare_flush = falcon_prepare_flush,
         .update_stats = falcon_update_nic_stats,
         .start_stats = falcon_start_nic_stats,
@@ -1760,6 +1778,7 @@ struct efx_nic_type falcon_b0_nic_type = {
         .reset = falcon_reset_hw,
         .probe_port = falcon_probe_port,
         .remove_port = falcon_remove_port,
+        .handle_global_event = falcon_handle_global_event,
         .prepare_flush = falcon_prepare_flush,
         .update_stats = falcon_update_nic_stats,
         .start_stats = falcon_start_nic_stats,
diff --git a/drivers/net/sfc/falcon_boards.c b/drivers/net/sfc/falcon_boards.c
index cfc6a5b5a477..2dd16f0b3ced 100644
--- a/drivers/net/sfc/falcon_boards.c
+++ b/drivers/net/sfc/falcon_boards.c
@@ -13,8 +13,6 @@
 #include "phy.h"
 #include "efx.h"
 #include "nic.h"
-#include "regs.h"
-#include "io.h"
 #include "workarounds.h"
 
 /* Macros for unpacking the board revision */
@@ -30,17 +28,28 @@
 #define FALCON_BOARD_SFN4112F 0x52
 
 /* Board temperature is about 15°C above ambient when air flow is
- * limited. */
+ * limited.  The maximum acceptable ambient temperature varies
+ * depending on the PHY specifications but the critical temperature
+ * above which we should shut down to avoid damage is 80°C. */
 #define FALCON_BOARD_TEMP_BIAS  15
+#define FALCON_BOARD_TEMP_CRIT  (80 + FALCON_BOARD_TEMP_BIAS)
 
 /* SFC4000 datasheet says: 'The maximum permitted junction temperature
  * is 125°C; the thermal design of the environment for the SFC4000
  * should aim to keep this well below 100°C.' */
+#define FALCON_JUNC_TEMP_MIN    0
 #define FALCON_JUNC_TEMP_MAX    90
+#define FALCON_JUNC_TEMP_CRIT   125
 
 /*****************************************************************************
  * Support for LM87 sensor chip used on several boards
  */
+#define LM87_REG_TEMP_HW_INT_LOCK       0x13
+#define LM87_REG_TEMP_HW_EXT_LOCK       0x14
+#define LM87_REG_TEMP_HW_INT            0x17
+#define LM87_REG_TEMP_HW_EXT            0x18
+#define LM87_REG_TEMP_EXT1              0x26
+#define LM87_REG_TEMP_INT               0x27
 #define LM87_REG_ALARMS1                0x41
 #define LM87_REG_ALARMS2                0x42
 #define LM87_IN_LIMITS(nr, _min, _max)                  \
@@ -57,6 +66,27 @@
 
 #if defined(CONFIG_SENSORS_LM87) || defined(CONFIG_SENSORS_LM87_MODULE)
 
+static int efx_poke_lm87(struct i2c_client *client, const u8 *reg_values)
+{
+        while (*reg_values) {
+                u8 reg = *reg_values++;
+                u8 value = *reg_values++;
+                int rc = i2c_smbus_write_byte_data(client, reg, value);
+                if (rc)
+                        return rc;
+        }
+        return 0;
+}
+
+static const u8 falcon_lm87_common_regs[] = {
+        LM87_REG_TEMP_HW_INT_LOCK, FALCON_BOARD_TEMP_CRIT,
+        LM87_REG_TEMP_HW_INT, FALCON_BOARD_TEMP_CRIT,
+        LM87_TEMP_EXT1_LIMITS(FALCON_JUNC_TEMP_MIN, FALCON_JUNC_TEMP_MAX),
+        LM87_REG_TEMP_HW_EXT_LOCK, FALCON_JUNC_TEMP_CRIT,
+        LM87_REG_TEMP_HW_EXT, FALCON_JUNC_TEMP_CRIT,
+        0
+};
+
 static int efx_init_lm87(struct efx_nic *efx, struct i2c_board_info *info,
                          const u8 *reg_values)
 {
@@ -67,13 +97,16 @@ static int efx_init_lm87(struct efx_nic *efx, struct i2c_board_info *info,
         if (!client)
                 return -EIO;
 
-        while (*reg_values) {
-                u8 reg = *reg_values++;
-                u8 value = *reg_values++;
-                rc = i2c_smbus_write_byte_data(client, reg, value);
-                if (rc)
-                        goto err;
-        }
+        /* Read-to-clear alarm/interrupt status */
+        i2c_smbus_read_byte_data(client, LM87_REG_ALARMS1);
+        i2c_smbus_read_byte_data(client, LM87_REG_ALARMS2);
+
+        rc = efx_poke_lm87(client, reg_values);
+        if (rc)
+                goto err;
+        rc = efx_poke_lm87(client, falcon_lm87_common_regs);
+        if (rc)
+                goto err;
 
         board->hwmon_client = client;
         return 0;
@@ -91,36 +124,56 @@ static void efx_fini_lm87(struct efx_nic *efx)
 static int efx_check_lm87(struct efx_nic *efx, unsigned mask)
 {
         struct i2c_client *client = falcon_board(efx)->hwmon_client;
-        s32 alarms1, alarms2;
+        bool temp_crit, elec_fault, is_failure;
+        u16 alarms;
+        s32 reg;
 
         /* If link is up then do not monitor temperature */
         if (EFX_WORKAROUND_7884(efx) && efx->link_state.up)
                 return 0;
 
-        alarms1 = i2c_smbus_read_byte_data(client, LM87_REG_ALARMS1);
-        alarms2 = i2c_smbus_read_byte_data(client, LM87_REG_ALARMS2);
-        if (alarms1 < 0)
-                return alarms1;
-        if (alarms2 < 0)
-                return alarms2;
-        alarms1 &= mask;
-        alarms2 &= mask >> 8;
-        if (alarms1 || alarms2) {
+        reg = i2c_smbus_read_byte_data(client, LM87_REG_ALARMS1);
+        if (reg < 0)
+                return reg;
+        alarms = reg;
+        reg = i2c_smbus_read_byte_data(client, LM87_REG_ALARMS2);
+        if (reg < 0)
+                return reg;
+        alarms |= reg << 8;
+        alarms &= mask;
+
+        temp_crit = false;
+        if (alarms & LM87_ALARM_TEMP_INT) {
+                reg = i2c_smbus_read_byte_data(client, LM87_REG_TEMP_INT);
+                if (reg < 0)
+                        return reg;
+                if (reg > FALCON_BOARD_TEMP_CRIT)
+                        temp_crit = true;
+        }
+        if (alarms & LM87_ALARM_TEMP_EXT1) {
+                reg = i2c_smbus_read_byte_data(client, LM87_REG_TEMP_EXT1);
+                if (reg < 0)
+                        return reg;
+                if (reg > FALCON_JUNC_TEMP_CRIT)
+                        temp_crit = true;
+        }
+        elec_fault = alarms & ~(LM87_ALARM_TEMP_INT | LM87_ALARM_TEMP_EXT1);
+        is_failure = temp_crit || elec_fault;
+
+        if (alarms)
                 netif_err(efx, hw, efx->net_dev,
-                          "LM87 detected a hardware failure (status %02x:%02x)"
-                          "%s%s%s\n",
-                          alarms1, alarms2,
-                          (alarms1 & LM87_ALARM_TEMP_INT) ?
+                          "LM87 detected a hardware %s (status %02x:%02x)"
+                          "%s%s%s%s\n",
+                          is_failure ? "failure" : "problem",
+                          alarms & 0xff, alarms >> 8,
+                          (alarms & LM87_ALARM_TEMP_INT) ?
                           "; board is overheating" : "",
-                          (alarms1 & LM87_ALARM_TEMP_EXT1) ?
+                          (alarms & LM87_ALARM_TEMP_EXT1) ?
                           "; controller is overheating" : "",
-                          (alarms1 & ~(LM87_ALARM_TEMP_INT | LM87_ALARM_TEMP_EXT1)
-                           || alarms2) ?
-                          "; electrical fault" : "");
-                return -ERANGE;
-        }
+                          temp_crit ? "; reached critical temperature" : "",
+                          elec_fault ? "; electrical fault" : "");
 
-        return 0;
+        return is_failure ? -ERANGE : 0;
 }
 
 #else /* !CONFIG_SENSORS_LM87 */
@@ -325,7 +378,7 @@ static ssize_t set_phy_flash_cfg(struct device *dev,
                 new_mode = old_mode & ~PHY_MODE_SPECIAL;
         else
                 new_mode = PHY_MODE_SPECIAL;
-        if (old_mode == new_mode) {
+        if (!((old_mode ^ new_mode) & PHY_MODE_SPECIAL)) {
                 err = 0;
         } else if (efx->state != STATE_RUNNING || netif_running(efx->net_dev)) {
                 err = -EBUSY;
@@ -362,10 +415,11 @@ static void sfe4001_fini(struct efx_nic *efx)
 
 static int sfe4001_check_hw(struct efx_nic *efx)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
         s32 status;
 
         /* If XAUI link is up then do not monitor */
-        if (EFX_WORKAROUND_7884(efx) && !efx->xmac_poll_required)
+        if (EFX_WORKAROUND_7884(efx) && !nic_data->xmac_poll_required)
                 return 0;
 
         /* Check the powered status of the PHY. Lack of power implies that
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c
index b31f595ebb5b..b49e84394641 100644
--- a/drivers/net/sfc/falcon_xmac.c
+++ b/drivers/net/sfc/falcon_xmac.c
@@ -16,7 +16,6 @@
 #include "io.h"
 #include "mac.h"
 #include "mdio_10g.h"
-#include "phy.h"
 #include "workarounds.h"
 
 /**************************************************************************
@@ -88,6 +87,7 @@ int falcon_reset_xaui(struct efx_nic *efx)
 
 static void falcon_ack_status_intr(struct efx_nic *efx)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
         efx_oword_t reg;
 
         if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
@@ -99,7 +99,7 @@ static void falcon_ack_status_intr(struct efx_nic *efx)
 
         /* We can only use this interrupt to signal the negative edge of
          * xaui_align [we have to poll the positive edge]. */
-        if (efx->xmac_poll_required)
+        if (nic_data->xmac_poll_required)
                 return;
 
         efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
@@ -277,12 +277,14 @@ static bool falcon_xmac_check_fault(struct efx_nic *efx)
 
 static int falcon_reconfigure_xmac(struct efx_nic *efx)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
+
         falcon_reconfigure_xgxs_core(efx);
         falcon_reconfigure_xmac_core(efx);
 
         falcon_reconfigure_mac_wrapper(efx);
 
-        efx->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
+        nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
         falcon_ack_status_intr(efx);
 
         return 0;
@@ -350,11 +352,13 @@ static void falcon_update_stats_xmac(struct efx_nic *efx)
 
 void falcon_poll_xmac(struct efx_nic *efx)
 {
+        struct falcon_nic_data *nic_data = efx->nic_data;
+
         if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
-            !efx->xmac_poll_required)
+            !nic_data->xmac_poll_required)
                 return;
 
-        efx->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
+        nic_data->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
         falcon_ack_status_intr(efx);
 }
 
diff --git a/drivers/net/sfc/filter.c b/drivers/net/sfc/filter.c
index 52cb6082b910..d4722c41c4ce 100644
--- a/drivers/net/sfc/filter.c
+++ b/drivers/net/sfc/filter.c
@@ -7,6 +7,7 @@
  * by the Free Software Foundation, incorporated herein by reference.
  */
 
+#include <linux/in.h>
 #include "efx.h"
 #include "filter.h"
 #include "io.h"
@@ -26,19 +27,26 @@
  */
 #define FILTER_CTL_SRCH_MAX 200
 
+enum efx_filter_table_id {
+        EFX_FILTER_TABLE_RX_IP = 0,
+        EFX_FILTER_TABLE_RX_MAC,
+        EFX_FILTER_TABLE_COUNT,
+};
+
 struct efx_filter_table {
+        enum efx_filter_table_id id;
         u32             offset;         /* address of table relative to BAR */
         unsigned        size;           /* number of entries */
         unsigned        step;           /* step between entries */
         unsigned        used;           /* number currently used */
         unsigned long   *used_bitmap;
         struct efx_filter_spec *spec;
+        unsigned        search_depth[EFX_FILTER_TYPE_COUNT];
 };
 
 struct efx_filter_state {
         spinlock_t      lock;
         struct efx_filter_table table[EFX_FILTER_TABLE_COUNT];
-        unsigned        search_depth[EFX_FILTER_TYPE_COUNT];
 };
 
 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
@@ -65,68 +73,203 @@ static u16 efx_filter_increment(u32 key)
 }
 
 static enum efx_filter_table_id
-efx_filter_type_table_id(enum efx_filter_type type)
+efx_filter_spec_table_id(const struct efx_filter_spec *spec)
+{
+        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_TCP_FULL >> 2));
+        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_TCP_WILD >> 2));
+        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_UDP_FULL >> 2));
+        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_UDP_WILD >> 2));
+        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_MAC != (EFX_FILTER_MAC_FULL >> 2));
+        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_MAC != (EFX_FILTER_MAC_WILD >> 2));
+        EFX_BUG_ON_PARANOID(spec->type == EFX_FILTER_UNSPEC);
+        return spec->type >> 2;
+}
+
+static struct efx_filter_table *
+efx_filter_spec_table(struct efx_filter_state *state,
+                      const struct efx_filter_spec *spec)
 {
-        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_RX_TCP_FULL >> 2));
-        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_RX_TCP_WILD >> 2));
-        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_RX_UDP_FULL >> 2));
-        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_IP != (EFX_FILTER_RX_UDP_WILD >> 2));
-        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_MAC != (EFX_FILTER_RX_MAC_FULL >> 2));
-        BUILD_BUG_ON(EFX_FILTER_TABLE_RX_MAC != (EFX_FILTER_RX_MAC_WILD >> 2));
-        return type >> 2;
+        if (spec->type == EFX_FILTER_UNSPEC)
+                return NULL;
+        else
+                return &state->table[efx_filter_spec_table_id(spec)];
 }
 
-static void
-efx_filter_table_reset_search_depth(struct efx_filter_state *state,
-                                    enum efx_filter_table_id table_id)
+static void efx_filter_table_reset_search_depth(struct efx_filter_table *table)
 {
-        memset(state->search_depth + (table_id << 2), 0,
-               sizeof(state->search_depth[0]) << 2);
+        memset(table->search_depth, 0, sizeof(table->search_depth));
 }
 
 static void efx_filter_push_rx_limits(struct efx_nic *efx)
 {
         struct efx_filter_state *state = efx->filter_state;
+        struct efx_filter_table *table;
         efx_oword_t filter_ctl;
 
         efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
 
+        table = &state->table[EFX_FILTER_TABLE_RX_IP];
         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
-                            state->search_depth[EFX_FILTER_RX_TCP_FULL] +
+                            table->search_depth[EFX_FILTER_TCP_FULL] +
                             FILTER_CTL_SRCH_FUDGE_FULL);
         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
-                            state->search_depth[EFX_FILTER_RX_TCP_WILD] +
+                            table->search_depth[EFX_FILTER_TCP_WILD] +
                             FILTER_CTL_SRCH_FUDGE_WILD);
         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
-                            state->search_depth[EFX_FILTER_RX_UDP_FULL] +
+                            table->search_depth[EFX_FILTER_UDP_FULL] +
                             FILTER_CTL_SRCH_FUDGE_FULL);
         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
-                            state->search_depth[EFX_FILTER_RX_UDP_WILD] +
+                            table->search_depth[EFX_FILTER_UDP_WILD] +
                             FILTER_CTL_SRCH_FUDGE_WILD);
 
-        if (state->table[EFX_FILTER_TABLE_RX_MAC].size) {
+        table = &state->table[EFX_FILTER_TABLE_RX_MAC];
+        if (table->size) {
                 EFX_SET_OWORD_FIELD(
                         filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
-                        state->search_depth[EFX_FILTER_RX_MAC_FULL] +
+                        table->search_depth[EFX_FILTER_MAC_FULL] +
                         FILTER_CTL_SRCH_FUDGE_FULL);
                 EFX_SET_OWORD_FIELD(
                         filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
-                        state->search_depth[EFX_FILTER_RX_MAC_WILD] +
+                        table->search_depth[EFX_FILTER_MAC_WILD] +
                         FILTER_CTL_SRCH_FUDGE_WILD);
         }
 
         efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
 }
 
+static inline void __efx_filter_set_ipv4(struct efx_filter_spec *spec,
+                                         __be32 host1, __be16 port1,
+                                         __be32 host2, __be16 port2)
+{
+        spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
+        spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
+        spec->data[2] = ntohl(host2);
+}
+
+/**
+ * efx_filter_set_ipv4_local - specify IPv4 host, transport protocol and port
+ * @spec: Specification to initialise
+ * @proto: Transport layer protocol number
+ * @host: Local host address (network byte order)
+ * @port: Local port (network byte order)
+ */
+int efx_filter_set_ipv4_local(struct efx_filter_spec *spec, u8 proto,
+                              __be32 host, __be16 port)
+{
+        __be32 host1;
+        __be16 port1;
+
+        EFX_BUG_ON_PARANOID(!(spec->flags & EFX_FILTER_FLAG_RX));
+
+        /* This cannot currently be combined with other filtering */
+        if (spec->type != EFX_FILTER_UNSPEC)
+                return -EPROTONOSUPPORT;
+
+        if (port == 0)
+                return -EINVAL;
+
+        switch (proto) {
+        case IPPROTO_TCP:
+                spec->type = EFX_FILTER_TCP_WILD;
+                break;
+        case IPPROTO_UDP:
+                spec->type = EFX_FILTER_UDP_WILD;
+                break;
+        default:
+                return -EPROTONOSUPPORT;
+        }
+
+        /* Filter is constructed in terms of source and destination,
+         * with the odd wrinkle that the ports are swapped in a UDP
+         * wildcard filter.  We need to convert from local and remote
+         * (= zero for wildcard) addresses.
+         */
+        host1 = 0;
+        if (proto != IPPROTO_UDP) {
+                port1 = 0;
+        } else {
+                port1 = port;
+                port = 0;
+        }
+
+        __efx_filter_set_ipv4(spec, host1, port1, host, port);
+        return 0;
+}
+
+/**
+ * efx_filter_set_ipv4_full - specify IPv4 hosts, transport protocol and ports
+ * @spec: Specification to initialise
+ * @proto: Transport layer protocol number
+ * @host: Local host address (network byte order)
+ * @port: Local port (network byte order)
+ * @rhost: Remote host address (network byte order)
+ * @rport: Remote port (network byte order)
+ */
+int efx_filter_set_ipv4_full(struct efx_filter_spec *spec, u8 proto,
+                             __be32 host, __be16 port,
+                             __be32 rhost, __be16 rport)
+{
+        EFX_BUG_ON_PARANOID(!(spec->flags & EFX_FILTER_FLAG_RX));
+
+        /* This cannot currently be combined with other filtering */
+        if (spec->type != EFX_FILTER_UNSPEC)
+                return -EPROTONOSUPPORT;
+
+        if (port == 0 || rport == 0)
+                return -EINVAL;
+
+        switch (proto) {
+        case IPPROTO_TCP:
+                spec->type = EFX_FILTER_TCP_FULL;
+                break;
+        case IPPROTO_UDP:
+                spec->type = EFX_FILTER_UDP_FULL;
+                break;
+        default:
+                return -EPROTONOSUPPORT;
+        }
+
+        __efx_filter_set_ipv4(spec, rhost, rport, host, port);
+        return 0;
+}
+
+/**
+ * efx_filter_set_eth_local - specify local Ethernet address and optional VID
+ * @spec: Specification to initialise
+ * @vid: VLAN ID to match, or %EFX_FILTER_VID_UNSPEC
+ * @addr: Local Ethernet MAC address
+ */
+int efx_filter_set_eth_local(struct efx_filter_spec *spec,
+                             u16 vid, const u8 *addr)
+{
+        EFX_BUG_ON_PARANOID(!(spec->flags & EFX_FILTER_FLAG_RX));
+
+        /* This cannot currently be combined with other filtering */
+        if (spec->type != EFX_FILTER_UNSPEC)
+                return -EPROTONOSUPPORT;
+
+        if (vid == EFX_FILTER_VID_UNSPEC) {
+                spec->type = EFX_FILTER_MAC_WILD;
+                spec->data[0] = 0;
+        } else {
+                spec->type = EFX_FILTER_MAC_FULL;
+                spec->data[0] = vid;
+        }
+
+        spec->data[1] = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5];
+        spec->data[2] = addr[0] << 8 | addr[1];
+        return 0;
+}
+
 /* Build a filter entry and return its n-tuple key. */
 static u32 efx_filter_build(efx_oword_t *filter, struct efx_filter_spec *spec)
 {
         u32 data3;
 
-        switch (efx_filter_type_table_id(spec->type)) {
+        switch (efx_filter_spec_table_id(spec)) {
         case EFX_FILTER_TABLE_RX_IP: {
-                bool is_udp = (spec->type == EFX_FILTER_RX_UDP_FULL ||
-                               spec->type == EFX_FILTER_RX_UDP_WILD);
+                bool is_udp = (spec->type == EFX_FILTER_UDP_FULL ||
+                               spec->type == EFX_FILTER_UDP_WILD);
                 EFX_POPULATE_OWORD_7(
                         *filter,
                         FRF_BZ_RSS_EN,
@@ -143,7 +286,7 @@ static u32 efx_filter_build(efx_oword_t *filter, struct efx_filter_spec *spec)
         }
 
         case EFX_FILTER_TABLE_RX_MAC: {
-                bool is_wild = spec->type == EFX_FILTER_RX_MAC_WILD;
+                bool is_wild = spec->type == EFX_FILTER_MAC_WILD;
                 EFX_POPULATE_OWORD_8(
                         *filter,
                         FRF_CZ_RMFT_RSS_EN,
@@ -206,6 +349,14 @@ found:
         return filter_idx;
 }
 
+/* Construct/deconstruct external filter IDs */
+
+static inline int
+efx_filter_make_id(enum efx_filter_table_id table_id, unsigned index)
+{
+        return table_id << 16 | index;
+}
+
 /**
  * efx_filter_insert_filter - add or replace a filter
  * @efx: NIC in which to insert the filter
@@ -213,30 +364,28 @@ found:
  * @replace: Flag for whether the specified filter may replace a filter
  *      with an identical match expression and equal or lower priority
  *
- * On success, return the filter index within its table.
+ * On success, return the filter ID.
  * On failure, return a negative error code.
  */
 int efx_filter_insert_filter(struct efx_nic *efx, struct efx_filter_spec *spec,
                              bool replace)
 {
         struct efx_filter_state *state = efx->filter_state;
-        enum efx_filter_table_id table_id =
-                efx_filter_type_table_id(spec->type);
-        struct efx_filter_table *table = &state->table[table_id];
+        struct efx_filter_table *table = efx_filter_spec_table(state, spec);
         struct efx_filter_spec *saved_spec;
         efx_oword_t filter;
         int filter_idx, depth;
         u32 key;
         int rc;
 
-        if (table->size == 0)
+        if (!table || table->size == 0)
                 return -EINVAL;
 
         key = efx_filter_build(&filter, spec);
 
         netif_vdbg(efx, hw, efx->net_dev,
                    "%s: type %d search_depth=%d", __func__, spec->type,
-                   state->search_depth[spec->type]);
+                   table->search_depth[spec->type]);
 
         spin_lock_bh(&state->lock);
 
@@ -263,8 +412,8 @@ int efx_filter_insert_filter(struct efx_nic *efx, struct efx_filter_spec *spec,
         }
         *saved_spec = *spec;
 
-        if (state->search_depth[spec->type] < depth) {
-                state->search_depth[spec->type] = depth;
+        if (table->search_depth[spec->type] < depth) {
+                table->search_depth[spec->type] = depth;
                 efx_filter_push_rx_limits(efx);
         }
 
@@ -273,6 +422,7 @@ int efx_filter_insert_filter(struct efx_nic *efx, struct efx_filter_spec *spec,
         netif_vdbg(efx, hw, efx->net_dev,
                    "%s: filter type %d index %d rxq %u set",
                    __func__, spec->type, filter_idx, spec->dmaq_id);
+        rc = efx_filter_make_id(table->id, filter_idx);
 
 out:
         spin_unlock_bh(&state->lock);
@@ -306,15 +456,16 @@ static void efx_filter_table_clear_entry(struct efx_nic *efx,
 int efx_filter_remove_filter(struct efx_nic *efx, struct efx_filter_spec *spec)
 {
         struct efx_filter_state *state = efx->filter_state;
-        enum efx_filter_table_id table_id =
-                efx_filter_type_table_id(spec->type);
-        struct efx_filter_table *table = &state->table[table_id];
+        struct efx_filter_table *table = efx_filter_spec_table(state, spec);
         struct efx_filter_spec *saved_spec;
         efx_oword_t filter;
         int filter_idx, depth;
         u32 key;
         int rc;
 
+        if (!table)
+                return -EINVAL;
+
         key = efx_filter_build(&filter, spec);
 
         spin_lock_bh(&state->lock);
@@ -332,7 +483,7 @@ int efx_filter_remove_filter(struct efx_nic *efx, struct efx_filter_spec *spec)
 
         efx_filter_table_clear_entry(efx, table, filter_idx);
         if (table->used == 0)
-                efx_filter_table_reset_search_depth(state, table_id);
+                efx_filter_table_reset_search_depth(table);
         rc = 0;
 
 out:
@@ -340,15 +491,9 @@ out:
         return rc;
 }
 
-/**
- * efx_filter_table_clear - remove filters from a table by priority
- * @efx: NIC from which to remove the filters
- * @table_id: Table from which to remove the filters
- * @priority: Maximum priority to remove
- */
-void efx_filter_table_clear(struct efx_nic *efx,
-                            enum efx_filter_table_id table_id,
-                            enum efx_filter_priority priority)
+static void efx_filter_table_clear(struct efx_nic *efx,
+                                   enum efx_filter_table_id table_id,
+                                   enum efx_filter_priority priority)
 {
         struct efx_filter_state *state = efx->filter_state;
         struct efx_filter_table *table = &state->table[table_id];
@@ -360,11 +505,22 @@ void efx_filter_table_clear(struct efx_nic *efx,
                 if (table->spec[filter_idx].priority <= priority)
                         efx_filter_table_clear_entry(efx, table, filter_idx);
         if (table->used == 0)
-                efx_filter_table_reset_search_depth(state, table_id);
+                efx_filter_table_reset_search_depth(table);
 
         spin_unlock_bh(&state->lock);
 }
 
+/**
+ * efx_filter_clear_rx - remove RX filters by priority
+ * @efx: NIC from which to remove the filters
+ * @priority: Maximum priority to remove
+ */
+void efx_filter_clear_rx(struct efx_nic *efx, enum efx_filter_priority priority)
+{
+        efx_filter_table_clear(efx, EFX_FILTER_TABLE_RX_IP, priority);
+        efx_filter_table_clear(efx, EFX_FILTER_TABLE_RX_MAC, priority);
+}
+
 /* Restore filter stater after reset */
 void efx_restore_filters(struct efx_nic *efx)
 {
@@ -407,6 +563,7 @@ int efx_probe_filters(struct efx_nic *efx)
 
         if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
                 table = &state->table[EFX_FILTER_TABLE_RX_IP];
+                table->id = EFX_FILTER_TABLE_RX_IP;
                 table->offset = FR_BZ_RX_FILTER_TBL0;
                 table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
                 table->step = FR_BZ_RX_FILTER_TBL0_STEP;
@@ -414,6 +571,7 @@ int efx_probe_filters(struct efx_nic *efx)
 
         if (efx_nic_rev(efx) >= EFX_REV_SIENA_A0) {
                 table = &state->table[EFX_FILTER_TABLE_RX_MAC];
+                table->id = EFX_FILTER_TABLE_RX_MAC;
                 table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
                 table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
                 table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
@@ -428,10 +586,9 @@ int efx_probe_filters(struct efx_nic *efx)
                                              GFP_KERNEL);
                 if (!table->used_bitmap)
                         goto fail;
-                table->spec = vmalloc(table->size * sizeof(*table->spec));
+                table->spec = vzalloc(table->size * sizeof(*table->spec));
                 if (!table->spec)
                         goto fail;
-                memset(table->spec, 0, table->size * sizeof(*table->spec));
         }
 
         return 0;
diff --git a/drivers/net/sfc/filter.h b/drivers/net/sfc/filter.h
index a53319ded79c..872f2132a496 100644
--- a/drivers/net/sfc/filter.h
+++ b/drivers/net/sfc/filter.h
@@ -12,31 +12,27 @@
 
 #include <linux/types.h>
 
-enum efx_filter_table_id {
-        EFX_FILTER_TABLE_RX_IP = 0,
-        EFX_FILTER_TABLE_RX_MAC,
-        EFX_FILTER_TABLE_COUNT,
-};
-
 /**
  * enum efx_filter_type - type of hardware filter
- * @EFX_FILTER_RX_TCP_FULL: RX, matching TCP/IPv4 4-tuple
- * @EFX_FILTER_RX_TCP_WILD: RX, matching TCP/IPv4 destination (host, port)
- * @EFX_FILTER_RX_UDP_FULL: RX, matching UDP/IPv4 4-tuple
- * @EFX_FILTER_RX_UDP_WILD: RX, matching UDP/IPv4 destination (host, port)
- * @EFX_FILTER_RX_MAC_FULL: RX, matching Ethernet destination MAC address, VID
- * @EFX_FILTER_RX_MAC_WILD: RX, matching Ethernet destination MAC address
+ * @EFX_FILTER_TCP_FULL: Matching TCP/IPv4 4-tuple
+ * @EFX_FILTER_TCP_WILD: Matching TCP/IPv4 destination (host, port)
+ * @EFX_FILTER_UDP_FULL: Matching UDP/IPv4 4-tuple
+ * @EFX_FILTER_UDP_WILD: Matching UDP/IPv4 destination (host, port)
+ * @EFX_FILTER_MAC_FULL: Matching Ethernet destination MAC address, VID
+ * @EFX_FILTER_MAC_WILD: Matching Ethernet destination MAC address
+ * @EFX_FILTER_UNSPEC: Match type is unspecified
  *
- * Falcon NICs only support the RX TCP/IPv4 and UDP/IPv4 filter types.
+ * Falcon NICs only support the TCP/IPv4 and UDP/IPv4 filter types.
  */
 enum efx_filter_type {
-        EFX_FILTER_RX_TCP_FULL = 0,
-        EFX_FILTER_RX_TCP_WILD,
-        EFX_FILTER_RX_UDP_FULL,
-        EFX_FILTER_RX_UDP_WILD,
-        EFX_FILTER_RX_MAC_FULL = 4,
-        EFX_FILTER_RX_MAC_WILD,
-        EFX_FILTER_TYPE_COUNT,
+        EFX_FILTER_TCP_FULL = 0,
+        EFX_FILTER_TCP_WILD,
+        EFX_FILTER_UDP_FULL,
+        EFX_FILTER_UDP_WILD,
+        EFX_FILTER_MAC_FULL = 4,
+        EFX_FILTER_MAC_WILD,
+        EFX_FILTER_TYPE_COUNT,          /* number of specific types */
+        EFX_FILTER_UNSPEC = 0xf,
 };
 
 /**
@@ -63,13 +59,13 @@ enum efx_filter_priority {
  * @EFX_FILTER_FLAG_RX_OVERRIDE_IP: Enables a MAC filter to override
  *      any IP filter that matches the same packet.  By default, IP
  *      filters take precedence.
- *
- * Currently, no flags are defined for TX filters.
+ * @EFX_FILTER_FLAG_RX: Filter is for RX
  */
 enum efx_filter_flags {
         EFX_FILTER_FLAG_RX_RSS = 0x01,
         EFX_FILTER_FLAG_RX_SCATTER = 0x02,
         EFX_FILTER_FLAG_RX_OVERRIDE_IP = 0x04,
+        EFX_FILTER_FLAG_RX = 0x08,
 };
 
 /**
@@ -91,99 +87,26 @@ struct efx_filter_spec {
         u32     data[3];
 };
 
-/**
- * efx_filter_set_rx_tcp_full - specify RX filter with TCP/IPv4 full match
- * @spec: Specification to initialise
- * @shost: Source host address (host byte order)
- * @sport: Source port (host byte order)
- * @dhost: Destination host address (host byte order)
- * @dport: Destination port (host byte order)
- */
-static inline void
-efx_filter_set_rx_tcp_full(struct efx_filter_spec *spec,
-                           u32 shost, u16 sport, u32 dhost, u16 dport)
-{
-        spec->type = EFX_FILTER_RX_TCP_FULL;
-        spec->data[0] = sport | shost << 16;
-        spec->data[1] = dport << 16 | shost >> 16;
-        spec->data[2] = dhost;
-}
-
-/**
- * efx_filter_set_rx_tcp_wild - specify RX filter with TCP/IPv4 wildcard match
- * @spec: Specification to initialise
- * @dhost: Destination host address (host byte order)
- * @dport: Destination port (host byte order)
- */
-static inline void
-efx_filter_set_rx_tcp_wild(struct efx_filter_spec *spec, u32 dhost, u16 dport)
-{
-        spec->type = EFX_FILTER_RX_TCP_WILD;
-        spec->data[0] = 0;
-        spec->data[1] = dport << 16;
-        spec->data[2] = dhost;
-}
-
-/**
- * efx_filter_set_rx_udp_full - specify RX filter with UDP/IPv4 full match
- * @spec: Specification to initialise
- * @shost: Source host address (host byte order)
- * @sport: Source port (host byte order)
- * @dhost: Destination host address (host byte order)
- * @dport: Destination port (host byte order)
- */
-static inline void
-efx_filter_set_rx_udp_full(struct efx_filter_spec *spec,
-                           u32 shost, u16 sport, u32 dhost, u16 dport)
-{
-        spec->type = EFX_FILTER_RX_UDP_FULL;
-        spec->data[0] = sport | shost << 16;
-        spec->data[1] = dport << 16 | shost >> 16;
-        spec->data[2] = dhost;
-}
-
-/**
- * efx_filter_set_rx_udp_wild - specify RX filter with UDP/IPv4 wildcard match
- * @spec: Specification to initialise
- * @dhost: Destination host address (host byte order)
- * @dport: Destination port (host byte order)
- */
-static inline void
-efx_filter_set_rx_udp_wild(struct efx_filter_spec *spec, u32 dhost, u16 dport)
+static inline void efx_filter_init_rx(struct efx_filter_spec *spec,
+                                      enum efx_filter_priority priority,
+                                      enum efx_filter_flags flags,
+                                      unsigned rxq_id)
 {
-        spec->type = EFX_FILTER_RX_UDP_WILD;
-        spec->data[0] = dport;
-        spec->data[1] = 0;
-        spec->data[2] = dhost;
+        spec->type = EFX_FILTER_UNSPEC;
+        spec->priority = priority;
+        spec->flags = EFX_FILTER_FLAG_RX | flags;
+        spec->dmaq_id = rxq_id;
 }
 
-/**
- * efx_filter_set_rx_mac_full - specify RX filter with MAC full match
- * @spec: Specification to initialise
- * @vid: VLAN ID
- * @addr: Destination MAC address
- */
-static inline void efx_filter_set_rx_mac_full(struct efx_filter_spec *spec,
-                                              u16 vid, const u8 *addr)
-{
-        spec->type = EFX_FILTER_RX_MAC_FULL;
-        spec->data[0] = vid;
-        spec->data[1] = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5];
-        spec->data[2] = addr[0] << 8 | addr[1];
-}
-
-/**
- * efx_filter_set_rx_mac_full - specify RX filter with MAC wildcard match
- * @spec: Specification to initialise
- * @addr: Destination MAC address
- */
-static inline void efx_filter_set_rx_mac_wild(struct efx_filter_spec *spec,
-                                              const u8 *addr)
-{
-        spec->type = EFX_FILTER_RX_MAC_WILD;
-        spec->data[0] = 0;
-        spec->data[1] = addr[2] << 24 | addr[3] << 16 | addr[4] << 8 | addr[5];
-        spec->data[2] = addr[0] << 8 | addr[1];
-}
+extern int efx_filter_set_ipv4_local(struct efx_filter_spec *spec, u8 proto,
+                                     __be32 host, __be16 port);
+extern int efx_filter_set_ipv4_full(struct efx_filter_spec *spec, u8 proto,
+                                    __be32 host, __be16 port,
+                                    __be32 rhost, __be16 rport);
+extern int efx_filter_set_eth_local(struct efx_filter_spec *spec,
+                                    u16 vid, const u8 *addr);
+enum {
+        EFX_FILTER_VID_UNSPEC = 0xffff,
+};
 
 #endif /* EFX_FILTER_H */
diff --git a/drivers/net/sfc/io.h b/drivers/net/sfc/io.h
index 85a99fe87437..6da4ae20a039 100644
--- a/drivers/net/sfc/io.h
+++ b/drivers/net/sfc/io.h
@@ -22,28 +22,39 @@
  *
  * Notes on locking strategy:
  *
- * Most NIC registers require 16-byte (or 8-byte, for SRAM) atomic writes
- * which necessitates locking.
- * Under normal operation few writes to NIC registers are made and these
- * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
- * cased to allow 4-byte (hence lockless) accesses.
+ * Most CSRs are 128-bit (oword) and therefore cannot be read or
+ * written atomically.  Access from the host is buffered by the Bus
+ * Interface Unit (BIU).  Whenever the host reads from the lowest
+ * address of such a register, or from the address of a different such
+ * register, the BIU latches the register's value.  Subsequent reads
+ * from higher addresses of the same register will read the latched
+ * value.  Whenever the host writes part of such a register, the BIU
+ * collects the written value and does not write to the underlying
+ * register until all 4 dwords have been written.  A similar buffering
+ * scheme applies to host access to the NIC's 64-bit SRAM.
  *
- * It *is* safe to write to these 4-byte registers in the middle of an
- * access to an 8-byte or 16-byte register.  We therefore use a
- * spinlock to protect accesses to the larger registers, but no locks
- * for the 4-byte registers.
+ * Access to different CSRs and 64-bit SRAM words must be serialised,
+ * since interleaved access can result in lost writes or lost
+ * information from read-to-clear fields.  We use efx_nic::biu_lock
+ * for this.  (We could use separate locks for read and write, but
+ * this is not normally a performance bottleneck.)
  *
- * A write barrier is needed to ensure that DW3 is written after DW0/1/2
- * due to the way the 16byte registers are "collected" in the BIU.
+ * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
+ * 128-bit but are special-cased in the BIU to avoid the need for
+ * locking in the host:
  *
- * We also lock when carrying out reads, to ensure consistency of the
- * data (made possible since the BIU reads all 128 bits into a cache).
- * Reads are very rare, so this isn't a significant performance
- * impact.  (Most data transferred from NIC to host is DMAed directly
- * into host memory).
- *
- * I/O BAR access uses locks for both reads and writes (but is only provided
- * for testing purposes).
+ * - They are write-only.
+ * - The semantics of writing to these registers are such that
+ *   replacing the low 96 bits with zero does not affect functionality.
+ * - If the host writes to the last dword address of such a register
+ *   (i.e. the high 32 bits) the underlying register will always be
+ *   written.  If the collector does not hold values for the low 96
+ *   bits of the register, they will be written as zero.  Writing to
+ *   the last qword does not have this effect and must not be done.
+ * - If the host writes to the address of any other part of such a
+ *   register while the collector already holds values for some other
+ *   register, the write is discarded and the collector maintains its
+ *   current state.
  */
 
 #if BITS_PER_LONG == 64
@@ -72,7 +83,7 @@ static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
         return (__force __le32)__raw_readl(efx->membase + reg);
 }
 
-/* Writes to a normal 16-byte Efx register, locking as appropriate. */
+/* Write a normal 128-bit CSR, locking as appropriate. */
 static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
                               unsigned int reg)
 {
@@ -85,21 +96,18 @@ static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
         spin_lock_irqsave(&efx->biu_lock, flags);
 #ifdef EFX_USE_QWORD_IO
         _efx_writeq(efx, value->u64[0], reg + 0);
-        wmb();
         _efx_writeq(efx, value->u64[1], reg + 8);
 #else
         _efx_writed(efx, value->u32[0], reg + 0);
         _efx_writed(efx, value->u32[1], reg + 4);
         _efx_writed(efx, value->u32[2], reg + 8);
-        wmb();
         _efx_writed(efx, value->u32[3], reg + 12);
 #endif
         mmiowb();
         spin_unlock_irqrestore(&efx->biu_lock, flags);
 }
 
-/* Write an 8-byte NIC SRAM entry through the supplied mapping,
- * locking as appropriate. */
+/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
                                    efx_qword_t *value, unsigned int index)
 {
@@ -115,36 +123,25 @@ static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
         __raw_writeq((__force u64)value->u64[0], membase + addr);
 #else
         __raw_writel((__force u32)value->u32[0], membase + addr);
-        wmb();
         __raw_writel((__force u32)value->u32[1], membase + addr + 4);
 #endif
         mmiowb();
         spin_unlock_irqrestore(&efx->biu_lock, flags);
 }
 
-/* Write dword to NIC register that allows partial writes
- *
- * Some registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
- * TX_DESC_UPD_REG) can be written to as a single dword.  This allows
- * for lockless writes.
- */
+/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
 static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
                               unsigned int reg)
 {
         netif_vdbg(efx, hw, efx->net_dev,
-                   "writing partial register %x with "EFX_DWORD_FMT"\n",
+                   "writing register %x with "EFX_DWORD_FMT"\n",
                    reg, EFX_DWORD_VAL(*value));
 
         /* No lock required */
         _efx_writed(efx, value->u32[0], reg);
 }
 
-/* Read from a NIC register
- *
- * This reads an entire 16-byte register in one go, locking as
- * appropriate.  It is essential to read the first dword first, as this
- * prompts the NIC to load the current value into the shadow register.
- */
+/* Read a 128-bit CSR, locking as appropriate. */
 static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
                              unsigned int reg)
 {
@@ -152,7 +149,6 @@ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
 
         spin_lock_irqsave(&efx->biu_lock, flags);
         value->u32[0] = _efx_readd(efx, reg + 0);
-        rmb();
         value->u32[1] = _efx_readd(efx, reg + 4);
         value->u32[2] = _efx_readd(efx, reg + 8);
         value->u32[3] = _efx_readd(efx, reg + 12);
@@ -163,8 +159,7 @@ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
                    EFX_OWORD_VAL(*value));
 }
 
-/* Read an 8-byte SRAM entry through supplied mapping,
- * locking as appropriate. */
+/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
                                   efx_qword_t *value, unsigned int index)
 {
@@ -176,7 +171,6 @@ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
         value->u64[0] = (__force __le64)__raw_readq(membase + addr);
 #else
         value->u32[0] = (__force __le32)__raw_readl(membase + addr);
-        rmb();
         value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
 #endif
         spin_unlock_irqrestore(&efx->biu_lock, flags);
@@ -186,7 +180,7 @@ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
                    addr, EFX_QWORD_VAL(*value));
 }
 
-/* Read dword from register that allows partial writes (sic) */
+/* Read a 32-bit CSR or SRAM */
 static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
                                 unsigned int reg)
 {
@@ -196,28 +190,28 @@ static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
                    reg, EFX_DWORD_VAL(*value));
 }
 
-/* Write to a register forming part of a table */
+/* Write a 128-bit CSR forming part of a table */
 static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
                                       unsigned int reg, unsigned int index)
 {
         efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
 }
 
-/* Read to a register forming part of a table */
+/* Read a 128-bit CSR forming part of a table */
 static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
                                      unsigned int reg, unsigned int index)
 {
         efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
 }
 
-/* Write to a dword register forming part of a table */
+/* Write a 32-bit CSR forming part of a table, or 32-bit SRAM */
 static inline void efx_writed_table(struct efx_nic *efx, efx_dword_t *value,
                                        unsigned int reg, unsigned int index)
 {
         efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
 }
 
-/* Read from a dword register forming part of a table */
+/* Read a 32-bit CSR forming part of a table, or 32-bit SRAM */
 static inline void efx_readd_table(struct efx_nic *efx, efx_dword_t *value,
                                    unsigned int reg, unsigned int index)
 {
@@ -231,29 +225,54 @@ static inline void efx_readd_table(struct efx_nic *efx, efx_dword_t *value,
 #define EFX_PAGED_REG(page, reg) \
         ((page) * EFX_PAGE_BLOCK_SIZE + (reg))
 
-/* As for efx_writeo(), but for a page-mapped register. */
-static inline void efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
-                                   unsigned int reg, unsigned int page)
+/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
+static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
+                                    unsigned int reg, unsigned int page)
 {
-        efx_writeo(efx, value, EFX_PAGED_REG(page, reg));
-}
+        reg = EFX_PAGED_REG(page, reg);
 
-/* As for efx_writed(), but for a page-mapped register. */
-static inline void efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
-                                   unsigned int reg, unsigned int page)
+        netif_vdbg(efx, hw, efx->net_dev,
+                   "writing register %x with " EFX_OWORD_FMT "\n", reg,
+                   EFX_OWORD_VAL(*value));
+
+#ifdef EFX_USE_QWORD_IO
+        _efx_writeq(efx, value->u64[0], reg + 0);
+#else
+        _efx_writed(efx, value->u32[0], reg + 0);
+        _efx_writed(efx, value->u32[1], reg + 4);
+#endif
+        _efx_writed(efx, value->u32[2], reg + 8);
+        _efx_writed(efx, value->u32[3], reg + 12);
+}
+#define efx_writeo_page(efx, value, reg, page)                          \
+        _efx_writeo_page(efx, value,                                    \
+                         reg +                                          \
+                         BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
+                         page)
+
+/* Write a page-mapped 32-bit CSR (EVQ_RPTR or the high bits of
+ * RX_DESC_UPD or TX_DESC_UPD)
+ */
+static inline void _efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
+                                    unsigned int reg, unsigned int page)
 {
         efx_writed(efx, value, EFX_PAGED_REG(page, reg));
 }
-
-/* Write dword to page-mapped register with an extra lock.
- *
- * As for efx_writed_page(), but for a register that suffers from
- * SFC bug 3181. Take out a lock so the BIU collector cannot be
- * confused. */
-static inline void efx_writed_page_locked(struct efx_nic *efx,
-                                          efx_dword_t *value,
-                                          unsigned int reg,
-                                          unsigned int page)
+#define efx_writed_page(efx, value, reg, page)                          \
+        _efx_writed_page(efx, value,                                    \
+                         reg +                                          \
+                         BUILD_BUG_ON_ZERO((reg) != 0x400 && (reg) != 0x83c \
+                                           && (reg) != 0xa1c),          \
+                         page)
+
+/* Write TIMER_COMMAND.  This is a page-mapped 32-bit CSR, but a bug
+ * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
+ * collector register.
+ */
+static inline void _efx_writed_page_locked(struct efx_nic *efx,
+                                           efx_dword_t *value,
+                                           unsigned int reg,
+                                           unsigned int page)
 {
         unsigned long flags __attribute__ ((unused));
 
@@ -265,5 +284,9 @@ static inline void efx_writed_page_locked(struct efx_nic *efx,
                 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
         }
 }
+#define efx_writed_page_locked(efx, value, reg, page)                   \
+        _efx_writed_page_locked(efx, value,                             \
+                                reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
+                                page)
 
 #endif /* EFX_IO_H */
diff --git a/drivers/net/sfc/mcdi.c b/drivers/net/sfc/mcdi.c
index 12cf910c2ce7..b716e827b291 100644
--- a/drivers/net/sfc/mcdi.c
+++ b/drivers/net/sfc/mcdi.c
@@ -381,7 +381,7 @@ int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
                                   -rc);
                         efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
                 } else
-                        netif_err(efx, hw, efx->net_dev,
+                        netif_dbg(efx, hw, efx->net_dev,
                                   "MC command 0x%x inlen %d failed rc=%d\n",
                                   cmd, (int)inlen, -rc);
         }
@@ -463,6 +463,7 @@ static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
                 if (mcdi->mode == MCDI_MODE_EVENTS) {
                         mcdi->resprc = rc;
                         mcdi->resplen = 0;
+                        ++mcdi->credits;
                 }
         } else
                 /* Nobody was waiting for an MCDI request, so trigger a reset */
diff --git a/drivers/net/sfc/mcdi_phy.c b/drivers/net/sfc/mcdi_phy.c
index c992742446b1..0e97eed663c6 100644
--- a/drivers/net/sfc/mcdi_phy.c
+++ b/drivers/net/sfc/mcdi_phy.c
@@ -16,7 +16,6 @@
 #include "phy.h"
 #include "mcdi.h"
 #include "mcdi_pcol.h"
-#include "mdio_10g.h"
 #include "nic.h"
 #include "selftest.h"
 
diff --git a/drivers/net/sfc/mdio_10g.c b/drivers/net/sfc/mdio_10g.c
index 98d946020429..56b0266b441f 100644
--- a/drivers/net/sfc/mdio_10g.c
+++ b/drivers/net/sfc/mdio_10g.c
@@ -15,7 +15,6 @@
 #include "net_driver.h"
 #include "mdio_10g.h"
 #include "workarounds.h"
-#include "nic.h"
 
 unsigned efx_mdio_id_oui(u32 id)
 {
diff --git a/drivers/net/sfc/mtd.c b/drivers/net/sfc/mtd.c
index 02e54b4f701f..d38627448c22 100644
--- a/drivers/net/sfc/mtd.c
+++ b/drivers/net/sfc/mtd.c
@@ -321,14 +321,15 @@ static int falcon_mtd_read(struct mtd_info *mtd, loff_t start,
         struct efx_mtd *efx_mtd = mtd->priv;
         const struct efx_spi_device *spi = efx_mtd->spi;
         struct efx_nic *efx = efx_mtd->efx;
+        struct falcon_nic_data *nic_data = efx->nic_data;
         int rc;
 
-        rc = mutex_lock_interruptible(&efx->spi_lock);
+        rc = mutex_lock_interruptible(&nic_data->spi_lock);
         if (rc)
                 return rc;
         rc = falcon_spi_read(efx, spi, part->offset + start, len,
                              retlen, buffer);
-        mutex_unlock(&efx->spi_lock);
+        mutex_unlock(&nic_data->spi_lock);
         return rc;
 }
 
@@ -337,13 +338,14 @@ static int falcon_mtd_erase(struct mtd_info *mtd, loff_t start, size_t len)
         struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
         struct efx_mtd *efx_mtd = mtd->priv;
         struct efx_nic *efx = efx_mtd->efx;
+        struct falcon_nic_data *nic_data = efx->nic_data;
         int rc;
 
-        rc = mutex_lock_interruptible(&efx->spi_lock);
+        rc = mutex_lock_interruptible(&nic_data->spi_lock);
         if (rc)
                 return rc;
         rc = efx_spi_erase(part, part->offset + start, len);
-        mutex_unlock(&efx->spi_lock);
+        mutex_unlock(&nic_data->spi_lock);
         return rc;
 }
 
@@ -354,14 +356,15 @@ static int falcon_mtd_write(struct mtd_info *mtd, loff_t start,
         struct efx_mtd *efx_mtd = mtd->priv;
         const struct efx_spi_device *spi = efx_mtd->spi;
         struct efx_nic *efx = efx_mtd->efx;
+        struct falcon_nic_data *nic_data = efx->nic_data;
         int rc;
 
-        rc = mutex_lock_interruptible(&efx->spi_lock);
+        rc = mutex_lock_interruptible(&nic_data->spi_lock);
         if (rc)
                 return rc;
         rc = falcon_spi_write(efx, spi, part->offset + start, len,
                               retlen, buffer);
-        mutex_unlock(&efx->spi_lock);
+        mutex_unlock(&nic_data->spi_lock);
         return rc;
 }
 
@@ -370,11 +373,12 @@ static int falcon_mtd_sync(struct mtd_info *mtd)
         struct efx_mtd_partition *part = to_efx_mtd_partition(mtd);
         struct efx_mtd *efx_mtd = mtd->priv;
         struct efx_nic *efx = efx_mtd->efx;
+        struct falcon_nic_data *nic_data = efx->nic_data;
         int rc;
 
-        mutex_lock(&efx->spi_lock);
+        mutex_lock(&nic_data->spi_lock);
         rc = efx_spi_slow_wait(part, true);
-        mutex_unlock(&efx->spi_lock);
+        mutex_unlock(&nic_data->spi_lock);
         return rc;
 }
 
@@ -387,35 +391,67 @@ static struct efx_mtd_ops falcon_mtd_ops = {
 
 static int falcon_mtd_probe(struct efx_nic *efx)
 {
-        struct efx_spi_device *spi = efx->spi_flash;
+        struct falcon_nic_data *nic_data = efx->nic_data;
+        struct efx_spi_device *spi;
         struct efx_mtd *efx_mtd;
-        int rc;
+        int rc = -ENODEV;
 
         ASSERT_RTNL();
 
-        if (!spi || spi->size <= FALCON_FLASH_BOOTCODE_START)
-                return -ENODEV;
-
-        efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]),
-                          GFP_KERNEL);
-        if (!efx_mtd)
-                return -ENOMEM;
-
-        efx_mtd->spi = spi;
-        efx_mtd->name = "flash";
-        efx_mtd->ops = &falcon_mtd_ops;
+        spi = &nic_data->spi_flash;
+        if (efx_spi_present(spi) && spi->size > FALCON_FLASH_BOOTCODE_START) {
+                efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]),
+                                  GFP_KERNEL);
+                if (!efx_mtd)
+                        return -ENOMEM;
+
+                efx_mtd->spi = spi;
+                efx_mtd->name = "flash";
+                efx_mtd->ops = &falcon_mtd_ops;
+
+                efx_mtd->n_parts = 1;
+                efx_mtd->part[0].mtd.type = MTD_NORFLASH;
+                efx_mtd->part[0].mtd.flags = MTD_CAP_NORFLASH;
+                efx_mtd->part[0].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
+                efx_mtd->part[0].mtd.erasesize = spi->erase_size;
+                efx_mtd->part[0].offset = FALCON_FLASH_BOOTCODE_START;
+                efx_mtd->part[0].type_name = "sfc_flash_bootrom";
+
+                rc = efx_mtd_probe_device(efx, efx_mtd);
+                if (rc) {
+                        kfree(efx_mtd);
+                        return rc;
+                }
+        }
 
-        efx_mtd->n_parts = 1;
-        efx_mtd->part[0].mtd.type = MTD_NORFLASH;
-        efx_mtd->part[0].mtd.flags = MTD_CAP_NORFLASH;
-        efx_mtd->part[0].mtd.size = spi->size - FALCON_FLASH_BOOTCODE_START;
-        efx_mtd->part[0].mtd.erasesize = spi->erase_size;
-        efx_mtd->part[0].offset = FALCON_FLASH_BOOTCODE_START;
-        efx_mtd->part[0].type_name = "sfc_flash_bootrom";
+        spi = &nic_data->spi_eeprom;
+        if (efx_spi_present(spi) && spi->size > EFX_EEPROM_BOOTCONFIG_START) {
+                efx_mtd = kzalloc(sizeof(*efx_mtd) + sizeof(efx_mtd->part[0]),
+                                  GFP_KERNEL);
+                if (!efx_mtd)
+                        return -ENOMEM;
+
+                efx_mtd->spi = spi;
+                efx_mtd->name = "EEPROM";
+                efx_mtd->ops = &falcon_mtd_ops;
+
+                efx_mtd->n_parts = 1;
+                efx_mtd->part[0].mtd.type = MTD_RAM;
+                efx_mtd->part[0].mtd.flags = MTD_CAP_RAM;
+                efx_mtd->part[0].mtd.size =
+                        min(spi->size, EFX_EEPROM_BOOTCONFIG_END) -
+                        EFX_EEPROM_BOOTCONFIG_START;
+                efx_mtd->part[0].mtd.erasesize = spi->erase_size;
+                efx_mtd->part[0].offset = EFX_EEPROM_BOOTCONFIG_START;
+                efx_mtd->part[0].type_name = "sfc_bootconfig";
+
+                rc = efx_mtd_probe_device(efx, efx_mtd);
+                if (rc) {
+                        kfree(efx_mtd);
+                        return rc;
+                }
+        }
 
-        rc = efx_mtd_probe_device(efx, efx_mtd);
-        if (rc)
-                kfree(efx_mtd);
         return rc;
 }
 
diff --git a/drivers/net/sfc/net_driver.h b/drivers/net/sfc/net_driver.h
index b137c889152b..bdce66ddf93a 100644
--- a/drivers/net/sfc/net_driver.h
+++ b/drivers/net/sfc/net_driver.h
@@ -136,14 +136,19 @@ struct efx_tx_buffer {
  * @efx: The associated Efx NIC
  * @queue: DMA queue number
  * @channel: The associated channel
+ * @core_txq: The networking core TX queue structure
  * @buffer: The software buffer ring
  * @txd: The hardware descriptor ring
  * @ptr_mask: The size of the ring minus 1.
  * @flushed: Used when handling queue flushing
  * @read_count: Current read pointer.
  *      This is the number of buffers that have been removed from both rings.
- * @stopped: Stopped count.
- *      Set if this TX queue is currently stopping its port.
+ * @old_write_count: The value of @write_count when last checked.
+ *      This is here for performance reasons.  The xmit path will
+ *      only get the up-to-date value of @write_count if this
+ *      variable indicates that the queue is empty.  This is to
+ *      avoid cache-line ping-pong between the xmit path and the
+ *      completion path.
  * @insert_count: Current insert pointer
  *      This is the number of buffers that have been added to the
  *      software ring.
@@ -163,13 +168,17 @@ struct efx_tx_buffer {
  * @tso_long_headers: Number of packets with headers too long for standard
  *      blocks
  * @tso_packets: Number of packets via the TSO xmit path
+ * @pushes: Number of times the TX push feature has been used
+ * @empty_read_count: If the completion path has seen the queue as empty
+ *      and the transmission path has not yet checked this, the value of
+ *      @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
  */
 struct efx_tx_queue {
         /* Members which don't change on the fast path */
         struct efx_nic *efx ____cacheline_aligned_in_smp;
         unsigned queue;
         struct efx_channel *channel;
-        struct efx_nic *nic;
+        struct netdev_queue *core_txq;
         struct efx_tx_buffer *buffer;
         struct efx_special_buffer txd;
         unsigned int ptr_mask;
@@ -177,7 +186,7 @@ struct efx_tx_queue {
 
         /* Members used mainly on the completion path */
         unsigned int read_count ____cacheline_aligned_in_smp;
-        int stopped;
+        unsigned int old_write_count;
 
         /* Members used only on the xmit path */
         unsigned int insert_count ____cacheline_aligned_in_smp;
@@ -187,6 +196,11 @@ struct efx_tx_queue {
         unsigned int tso_bursts;
         unsigned int tso_long_headers;
         unsigned int tso_packets;
+        unsigned int pushes;
+
+        /* Members shared between paths and sometimes updated */
+        unsigned int empty_read_count ____cacheline_aligned_in_smp;
+#define EFX_EMPTY_COUNT_VALID 0x80000000
 };
 
 /**
@@ -305,7 +319,6 @@ enum efx_rx_alloc_method {
  * @irq_moderation: IRQ moderation value (in hardware ticks)
  * @napi_dev: Net device used with NAPI
  * @napi_str: NAPI control structure
- * @reset_work: Scheduled reset work thread
  * @work_pending: Is work pending via NAPI?
  * @eventq: Event queue buffer
  * @eventq_mask: Event queue pointer mask
@@ -326,8 +339,6 @@ enum efx_rx_alloc_method {
  * @n_rx_overlength: Count of RX_OVERLENGTH errors
  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
  * @rx_queue: RX queue for this channel
- * @tx_stop_count: Core TX queue stop count
- * @tx_stop_lock: Core TX queue stop lock
  * @tx_queue: TX queues for this channel
  */
 struct efx_channel {
@@ -366,10 +377,6 @@ struct efx_channel {
         bool rx_pkt_csummed;
 
         struct efx_rx_queue rx_queue;
-
-        atomic_t tx_stop_count;
-        spinlock_t tx_stop_lock;
-
         struct efx_tx_queue tx_queue[2];
 };
 
@@ -626,10 +633,8 @@ struct efx_filter_state;
  *      Work items do not hold and must not acquire RTNL.
  * @workqueue_name: Name of workqueue
  * @reset_work: Scheduled reset workitem
- * @monitor_work: Hardware monitor workitem
  * @membase_phys: Memory BAR value as physical address
  * @membase: Memory BAR value
- * @biu_lock: BIU (bus interface unit) lock
  * @interrupt_mode: Interrupt mode
  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
  * @irq_rx_moderation: IRQ moderation time for RX event queues
@@ -648,23 +653,14 @@ struct efx_filter_state;
  * @n_tx_channels: Number of channels used for TX
  * @rx_buffer_len: RX buffer length
  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
+ * @rx_hash_key: Toeplitz hash key for RSS
  * @rx_indir_table: Indirection table for RSS
  * @int_error_count: Number of internal errors seen recently
  * @int_error_expire: Time at which error count will be expired
  * @irq_status: Interrupt status buffer
- * @last_irq_cpu: Last CPU to handle interrupt.
- *      This register is written with the SMP processor ID whenever an
- *      interrupt is handled.  It is used by efx_nic_test_interrupt()
- *      to verify that an interrupt has occurred.
  * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
  * @fatal_irq_level: IRQ level (bit number) used for serious errors
- * @spi_flash: SPI flash device
- *      This field will be %NULL if no flash device is present (or for Siena).
- * @spi_eeprom: SPI EEPROM device
- *      This field will be %NULL if no EEPROM device is present (or for Siena).
- * @spi_lock: SPI bus lock
  * @mtd_list: List of MTDs attached to the NIC
- * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
  * @nic_data: Hardware dependant state
  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
  *      @port_inhibited, efx_monitor() and efx_reconfigure_port()
@@ -677,21 +673,14 @@ struct efx_filter_state;
  * @port_initialized: Port initialized?
  * @net_dev: Operating system network device. Consider holding the rtnl lock
  * @rx_checksum_enabled: RX checksumming enabled
- * @mac_stats: MAC statistics. These include all statistics the MACs
- *      can provide.  Generic code converts these into a standard
- *      &struct net_device_stats.
  * @stats_buffer: DMA buffer for statistics
- * @stats_lock: Statistics update lock. Serialises statistics fetches
  * @mac_op: MAC interface
- * @mac_address: Permanent MAC address
  * @phy_type: PHY type
- * @mdio_lock: MDIO lock
  * @phy_op: PHY interface
  * @phy_data: PHY private data (including PHY-specific stats)
  * @mdio: PHY MDIO interface
  * @mdio_bus: PHY MDIO bus ID (only used by Siena)
  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
- * @xmac_poll_required: XMAC link state needs polling
  * @link_advertising: Autonegotiation advertising flags
  * @link_state: Current state of the link
  * @n_link_state_changes: Number of times the link has changed state
@@ -702,10 +691,23 @@ struct efx_filter_state;
  * @loopback_mode: Loopback status
  * @loopback_modes: Supported loopback mode bitmask
  * @loopback_selftest: Offline self-test private state
+ * @monitor_work: Hardware monitor workitem
+ * @biu_lock: BIU (bus interface unit) lock
+ * @last_irq_cpu: Last CPU to handle interrupt.
+ *      This register is written with the SMP processor ID whenever an
+ *      interrupt is handled.  It is used by efx_nic_test_interrupt()
+ *      to verify that an interrupt has occurred.
+ * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
+ * @mac_stats: MAC statistics. These include all statistics the MACs
+ *      can provide.  Generic code converts these into a standard
+ *      &struct net_device_stats.
+ * @stats_lock: Statistics update lock. Serialises statistics fetches
  *
  * This is stored in the private area of the &struct net_device.
  */
 struct efx_nic {
+        /* The following fields should be written very rarely */
+
         char name[IFNAMSIZ];
         struct pci_dev *pci_dev;
         const struct efx_nic_type *type;
@@ -714,10 +716,9 @@ struct efx_nic {
         struct workqueue_struct *workqueue;
         char workqueue_name[16];
         struct work_struct reset_work;
-        struct delayed_work monitor_work;
         resource_size_t membase_phys;
         void __iomem *membase;
-        spinlock_t biu_lock;
+
         enum efx_int_mode interrupt_mode;
         bool irq_rx_adaptive;
         unsigned int irq_rx_moderation;
@@ -744,19 +745,13 @@ struct efx_nic {
         unsigned long int_error_expire;
 
         struct efx_buffer irq_status;
-        volatile signed int last_irq_cpu;
         unsigned irq_zero_count;
         unsigned fatal_irq_level;
 
-        struct efx_spi_device *spi_flash;
-        struct efx_spi_device *spi_eeprom;
-        struct mutex spi_lock;
 #ifdef CONFIG_SFC_MTD
         struct list_head mtd_list;
 #endif
 
-        unsigned n_rx_nodesc_drop_cnt;
-
         void *nic_data;
 
         struct mutex mac_lock;
@@ -768,22 +763,17 @@ struct efx_nic {
         struct net_device *net_dev;
         bool rx_checksum_enabled;
 
-        struct efx_mac_stats mac_stats;
         struct efx_buffer stats_buffer;
-        spinlock_t stats_lock;
 
         struct efx_mac_operations *mac_op;
-        unsigned char mac_address[ETH_ALEN];
 
         unsigned int phy_type;
-        struct mutex mdio_lock;
         struct efx_phy_operations *phy_op;
         void *phy_data;
         struct mdio_if_info mdio;
         unsigned int mdio_bus;
         enum efx_phy_mode phy_mode;
 
-        bool xmac_poll_required;
         u32 link_advertising;
         struct efx_link_state link_state;
         unsigned int n_link_state_changes;
@@ -799,6 +789,15 @@ struct efx_nic {
         void *loopback_selftest;
 
         struct efx_filter_state *filter_state;
+
+        /* The following fields may be written more often */
+
+        struct delayed_work monitor_work ____cacheline_aligned_in_smp;
+        spinlock_t biu_lock;
+        volatile signed int last_irq_cpu;
+        unsigned n_rx_nodesc_drop_cnt;
+        struct efx_mac_stats mac_stats;
+        spinlock_t stats_lock;
 };
 
 static inline int efx_dev_registered(struct efx_nic *efx)
@@ -831,6 +830,7 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
  *      be called while the controller is uninitialised.
  * @probe_port: Probe the MAC and PHY
  * @remove_port: Free resources allocated by probe_port()
+ * @handle_global_event: Handle a "global" event (may be %NULL)
  * @prepare_flush: Prepare the hardware for flushing the DMA queues
  * @update_stats: Update statistics not provided by event handling
  * @start_stats: Start the regular fetching of statistics
@@ -875,6 +875,7 @@ struct efx_nic_type {
         int (*reset)(struct efx_nic *efx, enum reset_type method);
         int (*probe_port)(struct efx_nic *efx);
         void (*remove_port)(struct efx_nic *efx);
+        bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
         void (*prepare_flush)(struct efx_nic *efx);
         void (*update_stats)(struct efx_nic *efx);
         void (*start_stats)(struct efx_nic *efx);
diff --git a/drivers/net/sfc/nic.c b/drivers/net/sfc/nic.c
index 67cb0c96838c..da386599ab68 100644
--- a/drivers/net/sfc/nic.c
+++ b/drivers/net/sfc/nic.c
@@ -362,6 +362,35 @@ static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue)
                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 }
 
+/* Write pointer and first descriptor for TX descriptor ring */
+static inline void efx_push_tx_desc(struct efx_tx_queue *tx_queue,
+                                    const efx_qword_t *txd)
+{
+        unsigned write_ptr;
+        efx_oword_t reg;
+
+        BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
+        BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
+
+        write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
+        EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
+                             FRF_AZ_TX_DESC_WPTR, write_ptr);
+        reg.qword[0] = *txd;
+        efx_writeo_page(tx_queue->efx, &reg,
+                        FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
+}
+
+static inline bool
+efx_may_push_tx_desc(struct efx_tx_queue *tx_queue, unsigned int write_count)
+{
+        unsigned empty_read_count = ACCESS_ONCE(tx_queue->empty_read_count);
+
+        if (empty_read_count == 0)
+                return false;
+
+        tx_queue->empty_read_count = 0;
+        return ((empty_read_count ^ write_count) & ~EFX_EMPTY_COUNT_VALID) == 0;
+}
 
 /* For each entry inserted into the software descriptor ring, create a
  * descriptor in the hardware TX descriptor ring (in host memory), and
@@ -373,6 +402,7 @@ void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
         struct efx_tx_buffer *buffer;
         efx_qword_t *txd;
         unsigned write_ptr;
+        unsigned old_write_count = tx_queue->write_count;
 
         BUG_ON(tx_queue->write_count == tx_queue->insert_count);
 
@@ -391,7 +421,15 @@ void efx_nic_push_buffers(struct efx_tx_queue *tx_queue)
         } while (tx_queue->write_count != tx_queue->insert_count);
 
         wmb(); /* Ensure descriptors are written before they are fetched */
-        efx_notify_tx_desc(tx_queue);
+
+        if (efx_may_push_tx_desc(tx_queue, old_write_count)) {
+                txd = efx_tx_desc(tx_queue,
+                                  old_write_count & tx_queue->ptr_mask);
+                efx_push_tx_desc(tx_queue, txd);
+                ++tx_queue->pushes;
+        } else {
+                efx_notify_tx_desc(tx_queue);
+        }
 }
 
 /* Allocate hardware resources for a TX queue */
@@ -894,46 +932,6 @@ efx_handle_generated_event(struct efx_channel *channel, efx_qword_t *event)
                           channel->channel, EFX_QWORD_VAL(*event));
 }
 
-/* Global events are basically PHY events */
-static void
-efx_handle_global_event(struct efx_channel *channel, efx_qword_t *event)
-{
-        struct efx_nic *efx = channel->efx;
-        bool handled = false;
-
-        if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) ||
-            EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) ||
-            EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) {
-                /* Ignored */
-                handled = true;
-        }
-
-        if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
-            EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
-                efx->xmac_poll_required = true;
-                handled = true;
-        }
-
-        if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
-            EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
-            EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
-                netif_err(efx, rx_err, efx->net_dev,
-                          "channel %d seen global RX_RESET event. Resetting.\n",
-                          channel->channel);
-
-                atomic_inc(&efx->rx_reset);
-                efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
-                                   RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
-                handled = true;
-        }
-
-        if (!handled)
-                netif_err(efx, hw, efx->net_dev,
-                          "channel %d unknown global event "
-                          EFX_QWORD_FMT "\n", channel->channel,
-                          EFX_QWORD_VAL(*event));
-}
-
 static void
 efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
 {
@@ -1050,15 +1048,17 @@ int efx_nic_process_eventq(struct efx_channel *channel, int budget)
                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
                         efx_handle_generated_event(channel, &event);
                         break;
-                case FSE_AZ_EV_CODE_GLOBAL_EV:
-                        efx_handle_global_event(channel, &event);
-                        break;
                 case FSE_AZ_EV_CODE_DRIVER_EV:
                         efx_handle_driver_event(channel, &event);
                         break;
                 case FSE_CZ_EV_CODE_MCDI_EV:
                         efx_mcdi_process_event(channel, &event);
                         break;
+                case FSE_AZ_EV_CODE_GLOBAL_EV:
+                        if (efx->type->handle_global_event &&
+                            efx->type->handle_global_event(channel, &event))
+                                break;
+                        /* else fall through */
                 default:
                         netif_err(channel->efx, hw, channel->efx->net_dev,
                                   "channel %d unknown event type %d (data "
@@ -1670,7 +1670,7 @@ void efx_nic_init_common(struct efx_nic *efx)
         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
-        EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0);
+        EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
         /* Enable SW_EV to inherit in char driver - assume harmless here */
         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
diff --git a/drivers/net/sfc/nic.h b/drivers/net/sfc/nic.h
index 0438dc98722d..eb0586925b51 100644
--- a/drivers/net/sfc/nic.h
+++ b/drivers/net/sfc/nic.h
@@ -15,6 +15,7 @@
 #include "net_driver.h"
 #include "efx.h"
 #include "mcdi.h"
+#include "spi.h"
 
 /*
  * Falcon hardware control
@@ -113,6 +114,11 @@ struct falcon_board {
  * @stats_pending: Is there a pending DMA of MAC statistics.
  * @stats_timer: A timer for regularly fetching MAC statistics.
  * @stats_dma_done: Pointer to the flag which indicates DMA completion.
+ * @spi_flash: SPI flash device
+ * @spi_eeprom: SPI EEPROM device
+ * @spi_lock: SPI bus lock
+ * @mdio_lock: MDIO bus lock
+ * @xmac_poll_required: XMAC link state needs polling
  */
 struct falcon_nic_data {
         struct pci_dev *pci_dev2;
@@ -121,6 +127,11 @@ struct falcon_nic_data {
         bool stats_pending;
         struct timer_list stats_timer;
         u32 *stats_dma_done;
+        struct efx_spi_device spi_flash;
+        struct efx_spi_device spi_eeprom;
+        struct mutex spi_lock;
+        struct mutex mdio_lock;
+        bool xmac_poll_required;
 };
 
 static inline struct falcon_board *falcon_board(struct efx_nic *efx)
@@ -135,7 +146,6 @@ static inline struct falcon_board *falcon_board(struct efx_nic *efx)
  * @fw_build: Firmware build number
  * @mcdi: Management-Controller-to-Driver Interface
  * @wol_filter_id: Wake-on-LAN packet filter id
- * @ipv6_rss_key: Toeplitz hash key for IPv6 RSS
  */
 struct siena_nic_data {
         u64 fw_version;
diff --git a/drivers/net/sfc/qt202x_phy.c b/drivers/net/sfc/qt202x_phy.c
index 68813d1d85f3..ea3ae0089315 100644
--- a/drivers/net/sfc/qt202x_phy.c
+++ b/drivers/net/sfc/qt202x_phy.c
@@ -41,6 +41,8 @@
 #define PCS_UC_STATUS_LBN       0
 #define PCS_UC_STATUS_WIDTH     8
 #define PCS_UC_STATUS_FW_SAVE   0x20
+#define PMA_PMD_MODE_REG        0xc301
+#define PMA_PMD_RXIN_SEL_LBN    6
 #define PMA_PMD_FTX_CTRL2_REG   0xc309
 #define PMA_PMD_FTX_STATIC_LBN  13
 #define PMA_PMD_VEND1_REG       0xc001
@@ -282,6 +284,10 @@ static int qt2025c_select_phy_mode(struct efx_nic *efx)
          * slow) reload of the firmware image (the microcontroller's code
          * memory is not affected by the microcontroller reset). */
         efx_mdio_write(efx, 1, 0xc317, 0x00ff);
+        /* PMA/PMD loopback sets RXIN to inverse polarity and the firmware
+         * restart doesn't reset it. We need to do that ourselves. */
+        efx_mdio_set_flag(efx, 1, PMA_PMD_MODE_REG,
+                          1 << PMA_PMD_RXIN_SEL_LBN, false);
         efx_mdio_write(efx, 1, 0xc300, 0x0002);
         msleep(20);
 
diff --git a/drivers/net/sfc/rx.c b/drivers/net/sfc/rx.c
index 6d0959b5158e..3925fd621177 100644
--- a/drivers/net/sfc/rx.c
+++ b/drivers/net/sfc/rx.c
@@ -37,7 +37,7 @@
  * This driver supports two methods for allocating and using RX buffers:
  * each RX buffer may be backed by an skb or by an order-n page.
  *
- * When LRO is in use then the second method has a lower overhead,
+ * When GRO is in use then the second method has a lower overhead,
  * since we don't have to allocate then free skbs on reassembled frames.
  *
  * Values:
@@ -50,25 +50,25 @@
  *
  *   - Since pushing and popping descriptors are separated by the rx_queue
  *     size, so the watermarks should be ~rxd_size.
- *   - The performance win by using page-based allocation for LRO is less
- *     than the performance hit of using page-based allocation of non-LRO,
+ *   - The performance win by using page-based allocation for GRO is less
+ *     than the performance hit of using page-based allocation of non-GRO,
  *     so the watermarks should reflect this.
  *
  * Per channel we maintain a single variable, updated by each channel:
  *
- *   rx_alloc_level += (lro_performed ? RX_ALLOC_FACTOR_LRO :
+ *   rx_alloc_level += (gro_performed ? RX_ALLOC_FACTOR_GRO :
  *                      RX_ALLOC_FACTOR_SKB)
  * Per NAPI poll interval, we constrain rx_alloc_level to 0..MAX (which
  * limits the hysteresis), and update the allocation strategy:
  *
- *   rx_alloc_method = (rx_alloc_level > RX_ALLOC_LEVEL_LRO ?
+ *   rx_alloc_method = (rx_alloc_level > RX_ALLOC_LEVEL_GRO ?
  *                      RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB)
  */
 static int rx_alloc_method = RX_ALLOC_METHOD_AUTO;
 
-#define RX_ALLOC_LEVEL_LRO 0x2000
+#define RX_ALLOC_LEVEL_GRO 0x2000
 #define RX_ALLOC_LEVEL_MAX 0x3000
-#define RX_ALLOC_FACTOR_LRO 1
+#define RX_ALLOC_FACTOR_GRO 1
 #define RX_ALLOC_FACTOR_SKB (-2)
 
 /* This is the percentage fill level below which new RX descriptors
@@ -441,19 +441,19 @@ static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
         efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
 }
 
-/* Pass a received packet up through the generic LRO stack
+/* Pass a received packet up through the generic GRO stack
  *
  * Handles driverlink veto, and passes the fragment up via
- * the appropriate LRO method
+ * the appropriate GRO method
  */
-static void efx_rx_packet_lro(struct efx_channel *channel,
+static void efx_rx_packet_gro(struct efx_channel *channel,
                               struct efx_rx_buffer *rx_buf,
                               bool checksummed)
 {
         struct napi_struct *napi = &channel->napi_str;
         gro_result_t gro_result;
 
-        /* Pass the skb/page into the LRO engine */
+        /* Pass the skb/page into the GRO engine */
         if (rx_buf->page) {
                 struct efx_nic *efx = channel->efx;
                 struct page *page = rx_buf->page;
@@ -499,7 +499,7 @@ static void efx_rx_packet_lro(struct efx_channel *channel,
         if (gro_result == GRO_NORMAL) {
                 channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
         } else if (gro_result != GRO_DROP) {
-                channel->rx_alloc_level += RX_ALLOC_FACTOR_LRO;
+                channel->rx_alloc_level += RX_ALLOC_FACTOR_GRO;
                 channel->irq_mod_score += 2;
         }
 }
@@ -605,7 +605,7 @@ void __efx_rx_packet(struct efx_channel *channel,
         }
 
         if (likely(checksummed || rx_buf->page)) {
-                efx_rx_packet_lro(channel, rx_buf, checksummed);
+                efx_rx_packet_gro(channel, rx_buf, checksummed);
                 return;
         }
 
@@ -628,7 +628,7 @@ void efx_rx_strategy(struct efx_channel *channel)
 {
         enum efx_rx_alloc_method method = rx_alloc_method;
 
-        /* Only makes sense to use page based allocation if LRO is enabled */
+        /* Only makes sense to use page based allocation if GRO is enabled */
         if (!(channel->efx->net_dev->features & NETIF_F_GRO)) {
                 method = RX_ALLOC_METHOD_SKB;
         } else if (method == RX_ALLOC_METHOD_AUTO) {
@@ -639,7 +639,7 @@ void efx_rx_strategy(struct efx_channel *channel)
                         channel->rx_alloc_level = RX_ALLOC_LEVEL_MAX;
 
                 /* Decide on the allocation method */
-                method = ((channel->rx_alloc_level > RX_ALLOC_LEVEL_LRO) ?
+                method = ((channel->rx_alloc_level > RX_ALLOC_LEVEL_GRO) ?
                           RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB);
         }
 
diff --git a/drivers/net/sfc/siena.c b/drivers/net/sfc/siena.c
index 45236f58a258..bf8456176443 100644
--- a/drivers/net/sfc/siena.c
+++ b/drivers/net/sfc/siena.c
@@ -194,13 +194,7 @@ static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
 
 static int siena_probe_nvconfig(struct efx_nic *efx)
 {
-        int rc;
-
-        rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
-        if (rc)
-                return rc;
-
-        return 0;
+        return efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL);
 }
 
 static int siena_probe_nic(struct efx_nic *efx)
@@ -562,7 +556,7 @@ static int siena_set_wol(struct efx_nic *efx, u32 type)
                 if (nic_data->wol_filter_id != -1)
                         efx_mcdi_wol_filter_remove(efx,
                                                    nic_data->wol_filter_id);
-                rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
+                rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
                                                    &nic_data->wol_filter_id);
                 if (rc)
                         goto fail;
diff --git a/drivers/net/sfc/spi.h b/drivers/net/sfc/spi.h
index 8bf4fce0813a..879b7f6bde3d 100644
--- a/drivers/net/sfc/spi.h
+++ b/drivers/net/sfc/spi.h
@@ -61,6 +61,11 @@ struct efx_spi_device {
         unsigned int block_size;
 };
 
+static inline bool efx_spi_present(const struct efx_spi_device *spi)
+{
+        return spi->size != 0;
+}
+
 int falcon_spi_cmd(struct efx_nic *efx,
                    const struct efx_spi_device *spi, unsigned int command,
                    int address, const void* in, void *out, size_t len);
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c
index 1bc6c48c96ee..f102912eba91 100644
--- a/drivers/net/sfc/tenxpress.c
+++ b/drivers/net/sfc/tenxpress.c
@@ -15,9 +15,7 @@
 #include "mdio_10g.h"
 #include "nic.h"
 #include "phy.h"
-#include "regs.h"
 #include "workarounds.h"
-#include "selftest.h"
 
 /* We expect these MMDs to be in the package. */
 #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD       | \
diff --git a/drivers/net/sfc/tx.c b/drivers/net/sfc/tx.c
index 11726989fe2d..2f5e9da657bf 100644
--- a/drivers/net/sfc/tx.c
+++ b/drivers/net/sfc/tx.c
@@ -30,50 +30,6 @@
  */
 #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u)
 
-/* We need to be able to nest calls to netif_tx_stop_queue(), partly
- * because of the 2 hardware queues associated with each core queue,
- * but also so that we can inhibit TX for reasons other than a full
- * hardware queue. */
-void efx_stop_queue(struct efx_channel *channel)
-{
-        struct efx_nic *efx = channel->efx;
-        struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
-
-        if (!tx_queue)
-                return;
-
-        spin_lock_bh(&channel->tx_stop_lock);
-        netif_vdbg(efx, tx_queued, efx->net_dev, "stop TX queue\n");
-
-        atomic_inc(&channel->tx_stop_count);
-        netif_tx_stop_queue(
-                netdev_get_tx_queue(efx->net_dev,
-                                    tx_queue->queue / EFX_TXQ_TYPES));
-
-        spin_unlock_bh(&channel->tx_stop_lock);
-}
-
-/* Decrement core TX queue stop count and wake it if the count is 0 */
-void efx_wake_queue(struct efx_channel *channel)
-{
-        struct efx_nic *efx = channel->efx;
-        struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
-
-        if (!tx_queue)
-                return;
-
-        local_bh_disable();
-        if (atomic_dec_and_lock(&channel->tx_stop_count,
-                                &channel->tx_stop_lock)) {
-                netif_vdbg(efx, tx_queued, efx->net_dev, "waking TX queue\n");
-                netif_tx_wake_queue(
-                        netdev_get_tx_queue(efx->net_dev,
-                                            tx_queue->queue / EFX_TXQ_TYPES));
-                spin_unlock(&channel->tx_stop_lock);
-        }
-        local_bh_enable();
-}
-
 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
                                struct efx_tx_buffer *buffer)
 {
@@ -234,21 +190,22 @@ netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
                                  * checked.  Update the xmit path's
                                  * copy of read_count.
                                  */
-                                ++tx_queue->stopped;
+                                netif_tx_stop_queue(tx_queue->core_txq);
                                 /* This memory barrier protects the
-                                 * change of stopped from the access
+                                 * change of queue state from the access
                                  * of read_count. */
                                 smp_mb();
                                 tx_queue->old_read_count =
-                                        *(volatile unsigned *)
-                                        &tx_queue->read_count;
+                                        ACCESS_ONCE(tx_queue->read_count);
                                 fill_level = (tx_queue->insert_count
                                               - tx_queue->old_read_count);
                                 q_space = efx->txq_entries - 1 - fill_level;
-                                if (unlikely(q_space-- <= 0))
-                                        goto stop;
+                                if (unlikely(q_space-- <= 0)) {
+                                        rc = NETDEV_TX_BUSY;
+                                        goto unwind;
+                                }
                                 smp_mb();
-                                --tx_queue->stopped;
+                                netif_tx_start_queue(tx_queue->core_txq);
                         }
 
                         insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
@@ -308,13 +265,6 @@ netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
 
         /* Mark the packet as transmitted, and free the SKB ourselves */
         dev_kfree_skb_any(skb);
-        goto unwind;
-
- stop:
-        rc = NETDEV_TX_BUSY;
-
-        if (tx_queue->stopped == 1)
-                efx_stop_queue(tx_queue->channel);
 
  unwind:
         /* Work backwards until we hit the original insert pointer value */
@@ -407,22 +357,25 @@ void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
         efx_dequeue_buffers(tx_queue, index);
 
         /* See if we need to restart the netif queue.  This barrier
-         * separates the update of read_count from the test of
-         * stopped. */
+         * separates the update of read_count from the test of the
+         * queue state. */
         smp_mb();
-        if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
+        if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
+            likely(efx->port_enabled)) {
                 fill_level = tx_queue->insert_count - tx_queue->read_count;
                 if (fill_level < EFX_TXQ_THRESHOLD(efx)) {
                         EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
+                        netif_tx_wake_queue(tx_queue->core_txq);
+                }
+        }
 
-                        /* Do this under netif_tx_lock(), to avoid racing
-                         * with efx_xmit(). */
-                        netif_tx_lock(efx->net_dev);
-                        if (tx_queue->stopped) {
-                                tx_queue->stopped = 0;
-                                efx_wake_queue(tx_queue->channel);
-                        }
-                        netif_tx_unlock(efx->net_dev);
+        /* Check whether the hardware queue is now empty */
+        if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
+                tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
+                if (tx_queue->read_count == tx_queue->old_write_count) {
+                        smp_mb();
+                        tx_queue->empty_read_count =
+                                tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
                 }
         }
 }
@@ -470,9 +423,10 @@ void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
 
         tx_queue->insert_count = 0;
         tx_queue->write_count = 0;
+        tx_queue->old_write_count = 0;
         tx_queue->read_count = 0;
         tx_queue->old_read_count = 0;
-        BUG_ON(tx_queue->stopped);
+        tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
 
         /* Set up TX descriptor ring */
         efx_nic_init_tx(tx_queue);
@@ -508,12 +462,6 @@ void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
 
         /* Free up TSO header cache */
         efx_fini_tso(tx_queue);
-
-        /* Release queue's stop on port, if any */
-        if (tx_queue->stopped) {
-                tx_queue->stopped = 0;
-                efx_wake_queue(tx_queue->channel);
-        }
 }
 
 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
@@ -755,12 +703,12 @@ static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
                          * since the xmit path last checked.  Update
                          * the xmit path's copy of read_count.
                          */
-                        ++tx_queue->stopped;
+                        netif_tx_stop_queue(tx_queue->core_txq);
                         /* This memory barrier protects the change of
-                         * stopped from the access of read_count. */
+                         * queue state from the access of read_count. */
                         smp_mb();
                         tx_queue->old_read_count =
-                                *(volatile unsigned *)&tx_queue->read_count;
+                                ACCESS_ONCE(tx_queue->read_count);
                         fill_level = (tx_queue->insert_count
                                       - tx_queue->old_read_count);
                         q_space = efx->txq_entries - 1 - fill_level;
@@ -769,7 +717,7 @@ static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
                                 return 1;
                         }
                         smp_mb();
-                        --tx_queue->stopped;
+                        netif_tx_start_queue(tx_queue->core_txq);
                 }
 
                 insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
@@ -1109,8 +1057,10 @@ static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
 
         while (1) {
                 rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
-                if (unlikely(rc))
-                        goto stop;
+                if (unlikely(rc)) {
+                        rc2 = NETDEV_TX_BUSY;
+                        goto unwind;
+                }
 
                 /* Move onto the next fragment? */
                 if (state.in_len == 0) {
@@ -1139,14 +1089,6 @@ static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
         netif_err(efx, tx_err, efx->net_dev,
                   "Out of memory for TSO headers, or PCI mapping error\n");
         dev_kfree_skb_any(skb);
-        goto unwind;
-
- stop:
-        rc2 = NETDEV_TX_BUSY;
-
-        /* Stop the queue if it wasn't stopped before. */
-        if (tx_queue->stopped == 1)
-                efx_stop_queue(tx_queue->channel);
 
  unwind:
         /* Free the DMA mapping we were in the process of writing out */
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 50259dfec583..819c1750e2ab 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -45,9 +45,9 @@ static void sh_eth_set_duplex(struct net_device *ndev)
         u32 ioaddr = ndev->base_addr;
 
         if (mdp->duplex) /* Full */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
         else            /* Half */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
 }
 
 static void sh_eth_set_rate(struct net_device *ndev)
@@ -57,10 +57,10 @@ static void sh_eth_set_rate(struct net_device *ndev)
 
         switch (mdp->speed) {
         case 10: /* 10BASE */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
                 break;
         case 100:/* 100BASE */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
                 break;
         default:
                 break;
@@ -96,9 +96,9 @@ static void sh_eth_set_duplex(struct net_device *ndev)
         u32 ioaddr = ndev->base_addr;
 
         if (mdp->duplex) /* Full */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
         else            /* Half */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
 }
 
 static void sh_eth_set_rate(struct net_device *ndev)
@@ -108,10 +108,10 @@ static void sh_eth_set_rate(struct net_device *ndev)
 
         switch (mdp->speed) {
         case 10: /* 10BASE */
-                ctrl_outl(0, ioaddr + RTRATE);
+                writel(0, ioaddr + RTRATE);
                 break;
         case 100:/* 100BASE */
-                ctrl_outl(1, ioaddr + RTRATE);
+                writel(1, ioaddr + RTRATE);
                 break;
         default:
                 break;
@@ -143,7 +143,7 @@ static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
 static void sh_eth_chip_reset(struct net_device *ndev)
 {
         /* reset device */
-        ctrl_outl(ARSTR_ARSTR, ARSTR);
+        writel(ARSTR_ARSTR, ARSTR);
         mdelay(1);
 }
 
@@ -152,10 +152,10 @@ static void sh_eth_reset(struct net_device *ndev)
         u32 ioaddr = ndev->base_addr;
         int cnt = 100;
 
-        ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
-        ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
+        writel(EDSR_ENALL, ioaddr + EDSR);
+        writel(readl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
         while (cnt > 0) {
-                if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
+                if (!(readl(ioaddr + EDMR) & 0x3))
                         break;
                 mdelay(1);
                 cnt--;
@@ -164,14 +164,14 @@ static void sh_eth_reset(struct net_device *ndev)
                 printk(KERN_ERR "Device reset fail\n");
 
         /* Table Init */
-        ctrl_outl(0x0, ioaddr + TDLAR);
-        ctrl_outl(0x0, ioaddr + TDFAR);
-        ctrl_outl(0x0, ioaddr + TDFXR);
-        ctrl_outl(0x0, ioaddr + TDFFR);
-        ctrl_outl(0x0, ioaddr + RDLAR);
-        ctrl_outl(0x0, ioaddr + RDFAR);
-        ctrl_outl(0x0, ioaddr + RDFXR);
-        ctrl_outl(0x0, ioaddr + RDFFR);
+        writel(0x0, ioaddr + TDLAR);
+        writel(0x0, ioaddr + TDFAR);
+        writel(0x0, ioaddr + TDFXR);
+        writel(0x0, ioaddr + TDFFR);
+        writel(0x0, ioaddr + RDLAR);
+        writel(0x0, ioaddr + RDFAR);
+        writel(0x0, ioaddr + RDFXR);
+        writel(0x0, ioaddr + RDFFR);
 }
 
 static void sh_eth_set_duplex(struct net_device *ndev)
@@ -180,9 +180,9 @@ static void sh_eth_set_duplex(struct net_device *ndev)
         u32 ioaddr = ndev->base_addr;
 
         if (mdp->duplex) /* Full */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
         else            /* Half */
-                ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
+                writel(readl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
 }
 
 static void sh_eth_set_rate(struct net_device *ndev)
@@ -192,13 +192,13 @@ static void sh_eth_set_rate(struct net_device *ndev)
 
         switch (mdp->speed) {
         case 10: /* 10BASE */
-                ctrl_outl(GECMR_10, ioaddr + GECMR);
+                writel(GECMR_10, ioaddr + GECMR);
                 break;
         case 100:/* 100BASE */
-                ctrl_outl(GECMR_100, ioaddr + GECMR);
+                writel(GECMR_100, ioaddr + GECMR);
                 break;
         case 1000: /* 1000BASE */
-                ctrl_outl(GECMR_1000, ioaddr + GECMR);
+                writel(GECMR_1000, ioaddr + GECMR);
                 break;
         default:
                 break;
@@ -283,9 +283,9 @@ static void sh_eth_reset(struct net_device *ndev)
 {
         u32 ioaddr = ndev->base_addr;
 
-        ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
+        writel(readl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
         mdelay(3);
-        ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
+        writel(readl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
 }
 #endif
 
@@ -336,10 +336,10 @@ static void update_mac_address(struct net_device *ndev)
 {
         u32 ioaddr = ndev->base_addr;
 
-        ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
+        writel((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
                   (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
                   ioaddr + MAHR);
-        ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
+        writel((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
                   ioaddr + MALR);
 }
 
@@ -358,12 +358,12 @@ static void read_mac_address(struct net_device *ndev, unsigned char *mac)
         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
                 memcpy(ndev->dev_addr, mac, 6);
         } else {
-                ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
-                ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
-                ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
-                ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
-                ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
-                ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
+                ndev->dev_addr[0] = (readl(ioaddr + MAHR) >> 24);
+                ndev->dev_addr[1] = (readl(ioaddr + MAHR) >> 16) & 0xFF;
+                ndev->dev_addr[2] = (readl(ioaddr + MAHR) >> 8) & 0xFF;
+                ndev->dev_addr[3] = (readl(ioaddr + MAHR) & 0xFF);
+                ndev->dev_addr[4] = (readl(ioaddr + MALR) >> 8) & 0xFF;
+                ndev->dev_addr[5] = (readl(ioaddr + MALR) & 0xFF);
         }
 }
 
@@ -379,19 +379,19 @@ struct bb_info {
 /* PHY bit set */
 static void bb_set(u32 addr, u32 msk)
 {
-        ctrl_outl(ctrl_inl(addr) | msk, addr);
+        writel(readl(addr) | msk, addr);
 }
 
 /* PHY bit clear */
 static void bb_clr(u32 addr, u32 msk)
 {
-        ctrl_outl((ctrl_inl(addr) & ~msk), addr);
+        writel((readl(addr) & ~msk), addr);
 }
 
 /* PHY bit read */
 static int bb_read(u32 addr, u32 msk)
 {
-        return (ctrl_inl(addr) & msk) != 0;
+        return (readl(addr) & msk) != 0;
 }
 
 /* Data I/O pin control */
@@ -506,9 +506,9 @@ static void sh_eth_ring_format(struct net_device *ndev)
                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
                 /* Rx descriptor address set */
                 if (i == 0) {
-                        ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
+                        writel(mdp->rx_desc_dma, ioaddr + RDLAR);
 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
-                        ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
+                        writel(mdp->rx_desc_dma, ioaddr + RDFAR);
 #endif
                 }
         }
@@ -528,9 +528,9 @@ static void sh_eth_ring_format(struct net_device *ndev)
                 txdesc->buffer_length = 0;
                 if (i == 0) {
                         /* Tx descriptor address set */
-                        ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
+                        writel(mdp->tx_desc_dma, ioaddr + TDLAR);
 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
-                        ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
+                        writel(mdp->tx_desc_dma, ioaddr + TDFAR);
 #endif
                 }
         }
@@ -623,71 +623,71 @@ static int sh_eth_dev_init(struct net_device *ndev)
         /* Descriptor format */
         sh_eth_ring_format(ndev);
         if (mdp->cd->rpadir)
-                ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
+                writel(mdp->cd->rpadir_value, ioaddr + RPADIR);
 
         /* all sh_eth int mask */
-        ctrl_outl(0, ioaddr + EESIPR);
+        writel(0, ioaddr + EESIPR);
 
 #if defined(__LITTLE_ENDIAN__)
         if (mdp->cd->hw_swap)
-                ctrl_outl(EDMR_EL, ioaddr + EDMR);
+                writel(EDMR_EL, ioaddr + EDMR);
         else
 #endif
-                ctrl_outl(0, ioaddr + EDMR);
+                writel(0, ioaddr + EDMR);
 
         /* FIFO size set */
-        ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
-        ctrl_outl(0, ioaddr + TFTR);
+        writel(mdp->cd->fdr_value, ioaddr + FDR);
+        writel(0, ioaddr + TFTR);
 
         /* Frame recv control */
-        ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
+        writel(mdp->cd->rmcr_value, ioaddr + RMCR);
 
         rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
         tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
-        ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
+        writel(rx_int_var | tx_int_var, ioaddr + TRSCER);
 
         if (mdp->cd->bculr)
-                ctrl_outl(0x800, ioaddr + BCULR);       /* Burst sycle set */
+                writel(0x800, ioaddr + BCULR);  /* Burst sycle set */
 
-        ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
+        writel(mdp->cd->fcftr_value, ioaddr + FCFTR);
 
         if (!mdp->cd->no_trimd)
-                ctrl_outl(0, ioaddr + TRIMD);
+                writel(0, ioaddr + TRIMD);
 
         /* Recv frame limit set register */
-        ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
+        writel(RFLR_VALUE, ioaddr + RFLR);
 
-        ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
-        ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
+        writel(readl(ioaddr + EESR), ioaddr + EESR);
+        writel(mdp->cd->eesipr_value, ioaddr + EESIPR);
 
         /* PAUSE Prohibition */
-        val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
+        val = (readl(ioaddr + ECMR) & ECMR_DM) |
                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
 
-        ctrl_outl(val, ioaddr + ECMR);
+        writel(val, ioaddr + ECMR);
 
         if (mdp->cd->set_rate)
                 mdp->cd->set_rate(ndev);
 
         /* E-MAC Status Register clear */
-        ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
+        writel(mdp->cd->ecsr_value, ioaddr + ECSR);
 
         /* E-MAC Interrupt Enable register */
-        ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
+        writel(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
 
         /* Set MAC address */
         update_mac_address(ndev);
 
         /* mask reset */
         if (mdp->cd->apr)
-                ctrl_outl(APR_AP, ioaddr + APR);
+                writel(APR_AP, ioaddr + APR);
         if (mdp->cd->mpr)
-                ctrl_outl(MPR_MP, ioaddr + MPR);
+                writel(MPR_MP, ioaddr + MPR);
         if (mdp->cd->tpauser)
-                ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
+                writel(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
 
         /* Setting the Rx mode will start the Rx process. */
-        ctrl_outl(EDRRR_R, ioaddr + EDRRR);
+        writel(EDRRR_R, ioaddr + EDRRR);
 
         netif_start_queue(ndev);
 
@@ -811,8 +811,8 @@ static int sh_eth_rx(struct net_device *ndev)
 
         /* Restart Rx engine if stopped. */
         /* If we don't need to check status, don't. -KDU */
-        if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
-                ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
+        if (!(readl(ndev->base_addr + EDRRR) & EDRRR_R))
+                writel(EDRRR_R, ndev->base_addr + EDRRR);
 
         return 0;
 }
@@ -827,8 +827,8 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
         u32 mask;
 
         if (intr_status & EESR_ECI) {
-                felic_stat = ctrl_inl(ioaddr + ECSR);
-                ctrl_outl(felic_stat, ioaddr + ECSR);   /* clear int */
+                felic_stat = readl(ioaddr + ECSR);
+                writel(felic_stat, ioaddr + ECSR);      /* clear int */
                 if (felic_stat & ECSR_ICD)
                         mdp->stats.tx_carrier_errors++;
                 if (felic_stat & ECSR_LCHNG) {
@@ -839,25 +839,25 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                                 else
                                         link_stat = PHY_ST_LINK;
                         } else {
-                                link_stat = (ctrl_inl(ioaddr + PSR));
+                                link_stat = (readl(ioaddr + PSR));
                                 if (mdp->ether_link_active_low)
                                         link_stat = ~link_stat;
                         }
                         if (!(link_stat & PHY_ST_LINK)) {
                                 /* Link Down : disable tx and rx */
-                                ctrl_outl(ctrl_inl(ioaddr + ECMR) &
+                                writel(readl(ioaddr + ECMR) &
                                           ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
                         } else {
                                 /* Link Up */
-                                ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
+                                writel(readl(ioaddr + EESIPR) &
                                           ~DMAC_M_ECI, ioaddr + EESIPR);
                                 /*clear int */
-                                ctrl_outl(ctrl_inl(ioaddr + ECSR),
+                                writel(readl(ioaddr + ECSR),
                                           ioaddr + ECSR);
-                                ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
+                                writel(readl(ioaddr + EESIPR) |
                                           DMAC_M_ECI, ioaddr + EESIPR);
                                 /* enable tx and rx */
-                                ctrl_outl(ctrl_inl(ioaddr + ECMR) |
+                                writel(readl(ioaddr + ECMR) |
                                           (ECMR_RE | ECMR_TE), ioaddr + ECMR);
                         }
                 }
@@ -888,8 +888,8 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 /* Receive Descriptor Empty int */
                 mdp->stats.rx_over_errors++;
 
-                if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
-                        ctrl_outl(EDRRR_R, ioaddr + EDRRR);
+                if (readl(ioaddr + EDRRR) ^ EDRRR_R)
+                        writel(EDRRR_R, ioaddr + EDRRR);
                 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
         }
         if (intr_status & EESR_RFE) {
@@ -903,7 +903,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 mask &= ~EESR_ADE;
         if (intr_status & mask) {
                 /* Tx error */
-                u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
+                u32 edtrr = readl(ndev->base_addr + EDTRR);
                 /* dmesg */
                 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
                                 intr_status, mdp->cur_tx);
@@ -915,7 +915,7 @@ static void sh_eth_error(struct net_device *ndev, int intr_status)
                 /* SH7712 BUG */
                 if (edtrr ^ EDTRR_TRNS) {
                         /* tx dma start */
-                        ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
+                        writel(EDTRR_TRNS, ndev->base_addr + EDTRR);
                 }
                 /* wakeup */
                 netif_wake_queue(ndev);
@@ -934,12 +934,12 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
         spin_lock(&mdp->lock);
 
         /* Get interrpt stat */
-        intr_status = ctrl_inl(ioaddr + EESR);
+        intr_status = readl(ioaddr + EESR);
         /* Clear interrupt */
         if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
                         EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
                         cd->tx_check | cd->eesr_err_check)) {
-                ctrl_outl(intr_status, ioaddr + EESR);
+                writel(intr_status, ioaddr + EESR);
                 ret = IRQ_HANDLED;
         } else
                 goto other_irq;
@@ -1000,7 +1000,7 @@ static void sh_eth_adjust_link(struct net_device *ndev)
                                 mdp->cd->set_rate(ndev);
                 }
                 if (mdp->link == PHY_DOWN) {
-                        ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
+                        writel((readl(ioaddr + ECMR) & ~ECMR_TXF)
                                         | ECMR_DM, ioaddr + ECMR);
                         new_state = 1;
                         mdp->link = phydev->link;
@@ -1125,7 +1125,7 @@ static void sh_eth_tx_timeout(struct net_device *ndev)
 
         /* worning message out. */
         printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
-               " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
+               " resetting...\n", ndev->name, (int)readl(ioaddr + EESR));
 
         /* tx_errors count up */
         mdp->stats.tx_errors++;
@@ -1196,8 +1196,8 @@ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
 
         mdp->cur_tx++;
 
-        if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
-                ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
+        if (!(readl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
+                writel(EDTRR_TRNS, ndev->base_addr + EDTRR);
 
         return NETDEV_TX_OK;
 }
@@ -1212,11 +1212,11 @@ static int sh_eth_close(struct net_device *ndev)
         netif_stop_queue(ndev);
 
         /* Disable interrupts by clearing the interrupt mask. */
-        ctrl_outl(0x0000, ioaddr + EESIPR);
+        writel(0x0000, ioaddr + EESIPR);
 
         /* Stop the chip's Tx and Rx processes. */
-        ctrl_outl(0, ioaddr + EDTRR);
-        ctrl_outl(0, ioaddr + EDRRR);
+        writel(0, ioaddr + EDTRR);
+        writel(0, ioaddr + EDRRR);
 
         /* PHY Disconnect */
         if (mdp->phydev) {
@@ -1251,20 +1251,20 @@ static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
 
         pm_runtime_get_sync(&mdp->pdev->dev);
 
-        mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
-        ctrl_outl(0, ioaddr + TROCR);   /* (write clear) */
-        mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
-        ctrl_outl(0, ioaddr + CDCR);    /* (write clear) */
-        mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
-        ctrl_outl(0, ioaddr + LCCR);    /* (write clear) */
+        mdp->stats.tx_dropped += readl(ioaddr + TROCR);
+        writel(0, ioaddr + TROCR);      /* (write clear) */
+        mdp->stats.collisions += readl(ioaddr + CDCR);
+        writel(0, ioaddr + CDCR);       /* (write clear) */
+        mdp->stats.tx_carrier_errors += readl(ioaddr + LCCR);
+        writel(0, ioaddr + LCCR);       /* (write clear) */
 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
-        mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
-        ctrl_outl(0, ioaddr + CERCR);   /* (write clear) */
-        mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
-        ctrl_outl(0, ioaddr + CEECR);   /* (write clear) */
+        mdp->stats.tx_carrier_errors += readl(ioaddr + CERCR);/* CERCR */
+        writel(0, ioaddr + CERCR);      /* (write clear) */
+        mdp->stats.tx_carrier_errors += readl(ioaddr + CEECR);/* CEECR */
+        writel(0, ioaddr + CEECR);      /* (write clear) */
 #else
-        mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
-        ctrl_outl(0, ioaddr + CNDCR);   /* (write clear) */
+        mdp->stats.tx_carrier_errors += readl(ioaddr + CNDCR);
+        writel(0, ioaddr + CNDCR);      /* (write clear) */
 #endif
         pm_runtime_put_sync(&mdp->pdev->dev);
 
@@ -1295,11 +1295,11 @@ static void sh_eth_set_multicast_list(struct net_device *ndev)
 
         if (ndev->flags & IFF_PROMISC) {
                 /* Set promiscuous. */
-                ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
+                writel((readl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
                           ioaddr + ECMR);
         } else {
                 /* Normal, unicast/broadcast-only mode. */
-                ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
+                writel((readl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
                           ioaddr + ECMR);
         }
 }
@@ -1307,30 +1307,30 @@ static void sh_eth_set_multicast_list(struct net_device *ndev)
 /* SuperH's TSU register init function */
 static void sh_eth_tsu_init(u32 ioaddr)
 {
-        ctrl_outl(0, ioaddr + TSU_FWEN0);       /* Disable forward(0->1) */
-        ctrl_outl(0, ioaddr + TSU_FWEN1);       /* Disable forward(1->0) */
-        ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
-        ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
-        ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
-        ctrl_outl(0, ioaddr + TSU_PRISL0);
-        ctrl_outl(0, ioaddr + TSU_PRISL1);
-        ctrl_outl(0, ioaddr + TSU_FWSL0);
-        ctrl_outl(0, ioaddr + TSU_FWSL1);
-        ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
+        writel(0, ioaddr + TSU_FWEN0);  /* Disable forward(0->1) */
+        writel(0, ioaddr + TSU_FWEN1);  /* Disable forward(1->0) */
+        writel(0, ioaddr + TSU_FCM);    /* forward fifo 3k-3k */
+        writel(0xc, ioaddr + TSU_BSYSL0);
+        writel(0xc, ioaddr + TSU_BSYSL1);
+        writel(0, ioaddr + TSU_PRISL0);
+        writel(0, ioaddr + TSU_PRISL1);
+        writel(0, ioaddr + TSU_FWSL0);
+        writel(0, ioaddr + TSU_FWSL1);
+        writel(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
-        ctrl_outl(0, ioaddr + TSU_QTAG0);       /* Disable QTAG(0->1) */
-        ctrl_outl(0, ioaddr + TSU_QTAG1);       /* Disable QTAG(1->0) */
+        writel(0, ioaddr + TSU_QTAG0);  /* Disable QTAG(0->1) */
+        writel(0, ioaddr + TSU_QTAG1);  /* Disable QTAG(1->0) */
 #else
-        ctrl_outl(0, ioaddr + TSU_QTAGM0);      /* Disable QTAG(0->1) */
-        ctrl_outl(0, ioaddr + TSU_QTAGM1);      /* Disable QTAG(1->0) */
+        writel(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
+        writel(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
 #endif
-        ctrl_outl(0, ioaddr + TSU_FWSR);        /* all interrupt status clear */
-        ctrl_outl(0, ioaddr + TSU_FWINMK);      /* Disable all interrupt */
-        ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
-        ctrl_outl(0, ioaddr + TSU_POST1);       /* Disable CAM entry [ 0- 7] */
-        ctrl_outl(0, ioaddr + TSU_POST2);       /* Disable CAM entry [ 8-15] */
-        ctrl_outl(0, ioaddr + TSU_POST3);       /* Disable CAM entry [16-23] */
-        ctrl_outl(0, ioaddr + TSU_POST4);       /* Disable CAM entry [24-31] */
+        writel(0, ioaddr + TSU_FWSR);   /* all interrupt status clear */
+        writel(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
+        writel(0, ioaddr + TSU_TEN);    /* Disable all CAM entry */
+        writel(0, ioaddr + TSU_POST1);  /* Disable CAM entry [ 0- 7] */
+        writel(0, ioaddr + TSU_POST2);  /* Disable CAM entry [ 8-15] */
+        writel(0, ioaddr + TSU_POST3);  /* Disable CAM entry [16-23] */
+        writel(0, ioaddr + TSU_POST4);  /* Disable CAM entry [24-31] */
 }
 #endif /* SH_ETH_HAS_TSU */
 
@@ -1552,7 +1552,6 @@ static int sh_eth_drv_remove(struct platform_device *pdev)
 
         sh_mdio_release(ndev);
         unregister_netdev(ndev);
-        flush_scheduled_work();
         pm_runtime_disable(&pdev->dev);
         free_netdev(ndev);
         platform_set_drvdata(pdev, NULL);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 8b47763958f2..efa64221eede 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -26,7 +26,6 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
-#include <linux/workqueue.h>
 #include <linux/netdevice.h>
 #include <linux/phy.h>
 
diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c
index a5d6a6bd0c1a..3406ed870917 100644
--- a/drivers/net/sis190.c
+++ b/drivers/net/sis190.c
@@ -1915,9 +1915,10 @@ err_release_board:
 static void __devexit sis190_remove_one(struct pci_dev *pdev)
 {
         struct net_device *dev = pci_get_drvdata(pdev);
+        struct sis190_private *tp = netdev_priv(dev);
 
         sis190_mii_remove(dev);
-        flush_scheduled_work();
+        cancel_work_sync(&tp->phy_task);
         unregister_netdev(dev);
         sis190_release_board(pdev);
         pci_set_drvdata(pdev, NULL);
diff --git a/drivers/net/skfp/skfddi.c b/drivers/net/skfp/skfddi.c
index 0a66fed52e8e..16c62659cdd9 100644
--- a/drivers/net/skfp/skfddi.c
+++ b/drivers/net/skfp/skfddi.c
@@ -412,7 +412,7 @@ static  int skfp_driver_init(struct net_device *dev)
                 bp->SharedMemAddr = pci_alloc_consistent(&bp->pdev,
                                                          bp->SharedMemSize,
                                                          &bp->SharedMemDMA);
-                if (!bp->SharedMemSize) {
+                if (!bp->SharedMemAddr) {
                         printk("could not allocate mem for ");
                         printk("hardware module: %ld byte\n",
                                bp->SharedMemSize);
diff --git a/drivers/net/skfp/smt.c b/drivers/net/skfp/smt.c
index 2d9941c045bc..1e1bd0c201c8 100644
--- a/drivers/net/skfp/smt.c
+++ b/drivers/net/skfp/smt.c
@@ -1263,7 +1263,7 @@ void smt_set_timestamp(struct s_smc *smc, u_char *p)
 static void smt_fill_policy(struct s_smc *smc, struct smt_p_policy *policy)
 {
         int     i ;
-        u_char  *map ;
+        const u_char *map ;
         u_short in ;
         u_short out ;
 
@@ -1271,7 +1271,7 @@ static void smt_fill_policy(struct s_smc *smc, struct smt_p_policy *policy)
          * MIB para 101b (fddiSMTConnectionPolicy) coding
          * is different from 0005 coding
          */
-        static u_char   ansi_weirdness[16] = {
+        static const u_char ansi_weirdness[16] = {
                 0,7,5,3,8,1,6,4,9,10,2,11,12,13,14,15
         } ;
         SMTSETPARA(policy,SMT_P_POLICY) ;
diff --git a/drivers/net/skge.c b/drivers/net/skge.c
index 220e0398f1d5..42daf98ba736 100644
--- a/drivers/net/skge.c
+++ b/drivers/net/skge.c
@@ -1191,7 +1191,7 @@ static void genesis_init(struct skge_hw *hw)
 
 static void genesis_reset(struct skge_hw *hw, int port)
 {
-        const u8 zero[8]  = { 0 };
+        static const u8 zero[8]  = { 0 };
         u32 reg;
 
         skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
@@ -1557,7 +1557,7 @@ static void genesis_mac_init(struct skge_hw *hw, int port)
         int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
         int i;
         u32 r;
-        const u8 zero[6]  = { 0 };
+        static const u8 zero[6]  = { 0 };
 
         for (i = 0; i < 10; i++) {
                 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
@@ -2764,7 +2764,7 @@ static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
         td->dma_hi = map >> 32;
 
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                const int offset = skb_transport_offset(skb);
+                const int offset = skb_checksum_start_offset(skb);
 
                 /* This seems backwards, but it is what the sk98lin
                  * does.  Looks like hardware is wrong?
@@ -4012,8 +4012,6 @@ static void __devexit skge_remove(struct pci_dev *pdev)
         if (!hw)
                 return;
 
-        flush_scheduled_work();
-
         dev1 = hw->dev[1];
         if (dev1)
                 unregister_netdev(dev1);
@@ -4044,53 +4042,40 @@ static void __devexit skge_remove(struct pci_dev *pdev)
 }
 
 #ifdef CONFIG_PM
-static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
+static int skge_suspend(struct device *dev)
 {
+        struct pci_dev *pdev = to_pci_dev(dev);
         struct skge_hw *hw  = pci_get_drvdata(pdev);
-        int i, err, wol = 0;
+        int i;
 
         if (!hw)
                 return 0;
 
-        err = pci_save_state(pdev);
-        if (err)
-                return err;
-
         for (i = 0; i < hw->ports; i++) {
                 struct net_device *dev = hw->dev[i];
                 struct skge_port *skge = netdev_priv(dev);
 
                 if (netif_running(dev))
                         skge_down(dev);
+
                 if (skge->wol)
                         skge_wol_init(skge);
-
-                wol |= skge->wol;
         }
 
         skge_write32(hw, B0_IMSK, 0);
 
-        pci_prepare_to_sleep(pdev);
-
         return 0;
 }
 
-static int skge_resume(struct pci_dev *pdev)
+static int skge_resume(struct device *dev)
 {
+        struct pci_dev *pdev = to_pci_dev(dev);
         struct skge_hw *hw  = pci_get_drvdata(pdev);
         int i, err;
 
         if (!hw)
                 return 0;
 
-        err = pci_back_from_sleep(pdev);
-        if (err)
-                goto out;
-
-        err = pci_restore_state(pdev);
-        if (err)
-                goto out;
-
         err = skge_reset(hw);
         if (err)
                 goto out;
@@ -4111,12 +4096,19 @@ static int skge_resume(struct pci_dev *pdev)
 out:
         return err;
 }
+
+static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
+#define SKGE_PM_OPS (&skge_pm_ops)
+
+#else
+
+#define SKGE_PM_OPS NULL
 #endif
 
 static void skge_shutdown(struct pci_dev *pdev)
 {
         struct skge_hw *hw  = pci_get_drvdata(pdev);
-        int i, wol = 0;
+        int i;
 
         if (!hw)
                 return;
@@ -4127,15 +4119,10 @@ static void skge_shutdown(struct pci_dev *pdev)
 
                 if (skge->wol)
                         skge_wol_init(skge);
-                wol |= skge->wol;
         }
 
-        if (pci_enable_wake(pdev, PCI_D3cold, wol))
-                pci_enable_wake(pdev, PCI_D3hot, wol);
-
-        pci_disable_device(pdev);
+        pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
         pci_set_power_state(pdev, PCI_D3hot);
-
 }
 
 static struct pci_driver skge_driver = {
@@ -4143,11 +4130,8 @@ static struct pci_driver skge_driver = {
         .id_table =     skge_id_table,
         .probe =        skge_probe,
         .remove =       __devexit_p(skge_remove),
-#ifdef CONFIG_PM
-        .suspend =      skge_suspend,
-        .resume =       skge_resume,
-#endif
         .shutdown =     skge_shutdown,
+        .driver.pm =    SKGE_PM_OPS,
 };
 
 static struct dmi_system_id skge_32bit_dma_boards[] = {
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index d6577084ce70..7d85a38377a1 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -46,10 +46,6 @@
 
 #include <asm/irq.h>
 
-#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
-#define SKY2_VLAN_TAG_USED 1
-#endif
-
 #include "sky2.h"
 
 #define DRV_NAME                "sky2"
@@ -1326,39 +1322,34 @@ static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
         return err;
 }
 
-#ifdef SKY2_VLAN_TAG_USED
-static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
-{
-        if (onoff) {
-                sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
-                             RX_VLAN_STRIP_ON);
-                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
-                             TX_VLAN_TAG_ON);
-        } else {
-                sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
-                             RX_VLAN_STRIP_OFF);
-                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
-                             TX_VLAN_TAG_OFF);
-        }
-}
+#define NETIF_F_ALL_VLAN (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX)
 
-static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
+static void sky2_vlan_mode(struct net_device *dev)
 {
         struct sky2_port *sky2 = netdev_priv(dev);
         struct sky2_hw *hw = sky2->hw;
         u16 port = sky2->port;
 
-        netif_tx_lock_bh(dev);
-        napi_disable(&hw->napi);
+        if (dev->features & NETIF_F_HW_VLAN_RX)
+                sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
+                             RX_VLAN_STRIP_ON);
+        else
+                sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
+                             RX_VLAN_STRIP_OFF);
 
-        sky2->vlgrp = grp;
-        sky2_set_vlan_mode(hw, port, grp != NULL);
+        dev->vlan_features = dev->features &~ NETIF_F_ALL_VLAN;
+        if (dev->features & NETIF_F_HW_VLAN_TX)
+                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
+                             TX_VLAN_TAG_ON);
+        else {
+                sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
+                             TX_VLAN_TAG_OFF);
 
-        sky2_read32(hw, B0_Y2_SP_LISR);
-        napi_enable(&hw->napi);
-        netif_tx_unlock_bh(dev);
+                /* Can't do transmit offload of vlan without hw vlan */
+                dev->vlan_features &= ~(NETIF_F_TSO | NETIF_F_SG
+                                        | NETIF_F_ALL_CSUM);
+        }
 }
-#endif
 
 /* Amount of required worst case padding in rx buffer */
 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
@@ -1635,9 +1626,7 @@ static void sky2_hw_up(struct sky2_port *sky2)
         sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
                            sky2->tx_ring_size - 1);
 
-#ifdef SKY2_VLAN_TAG_USED
-        sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
-#endif
+        sky2_vlan_mode(sky2->netdev);
 
         sky2_rx_start(sky2);
 }
@@ -1780,7 +1769,7 @@ static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
         }
 
         ctrl = 0;
-#ifdef SKY2_VLAN_TAG_USED
+
         /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
         if (vlan_tx_tag_present(skb)) {
                 if (!le) {
@@ -1792,7 +1781,6 @@ static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
                 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
                 ctrl |= INS_VLAN;
         }
-#endif
 
         /* Handle TCP checksum offload */
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
@@ -1917,8 +1905,10 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
                         netif_printk(sky2, tx_done, KERN_DEBUG, dev,
                                      "tx done %u\n", idx);
 
-                        dev->stats.tx_packets++;
-                        dev->stats.tx_bytes += skb->len;
+                        u64_stats_update_begin(&sky2->tx_stats.syncp);
+                        ++sky2->tx_stats.packets;
+                        sky2->tx_stats.bytes += skb->len;
+                        u64_stats_update_end(&sky2->tx_stats.syncp);
 
                         re->skb = NULL;
                         dev_kfree_skb_any(skb);
@@ -2430,11 +2420,8 @@ static struct sk_buff *sky2_receive(struct net_device *dev,
         struct sk_buff *skb = NULL;
         u16 count = (status & GMR_FS_LEN) >> 16;
 
-#ifdef SKY2_VLAN_TAG_USED
-        /* Account for vlan tag */
-        if (sky2->vlgrp && (status & GMR_FS_VLAN))
-                count -= VLAN_HLEN;
-#endif
+        if (status & GMR_FS_VLAN)
+                count -= VLAN_HLEN;     /* Account for vlan tag */
 
         netif_printk(sky2, rx_status, KERN_DEBUG, dev,
                      "rx slot %u status 0x%x len %d\n",
@@ -2460,7 +2447,7 @@ static struct sk_buff *sky2_receive(struct net_device *dev,
 
         /* if length reported by DMA does not match PHY, packet was truncated */
         if (length != count)
-                goto len_error;
+                goto error;
 
 okay:
         if (length < copybreak)
@@ -2475,34 +2462,13 @@ resubmit:
 
         return skb;
 
-len_error:
-        /* Truncation of overlength packets
-           causes PHY length to not match MAC length */
-        ++dev->stats.rx_length_errors;
-        if (net_ratelimit())
-                netif_info(sky2, rx_err, dev,
-                           "rx length error: status %#x length %d\n",
-                           status, length);
-        goto resubmit;
-
 error:
         ++dev->stats.rx_errors;
-        if (status & GMR_FS_RX_FF_OV) {
-                dev->stats.rx_over_errors++;
-                goto resubmit;
-        }
 
         if (net_ratelimit())
                 netif_info(sky2, rx_err, dev,
                            "rx error, status 0x%x length %d\n", status, length);
 
-        if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
-                dev->stats.rx_length_errors++;
-        if (status & GMR_FS_FRAGMENT)
-                dev->stats.rx_frame_errors++;
-        if (status & GMR_FS_CRC_ERR)
-                dev->stats.rx_crc_errors++;
-
         goto resubmit;
 }
 
@@ -2523,17 +2489,9 @@ static inline void sky2_tx_done(struct net_device *dev, u16 last)
 static inline void sky2_skb_rx(const struct sky2_port *sky2,
                                u32 status, struct sk_buff *skb)
 {
-#ifdef SKY2_VLAN_TAG_USED
-        u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
-        if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
-                if (skb->ip_summed == CHECKSUM_NONE)
-                        vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
-                else
-                        vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
-                                         vlan_tag, skb);
-                return;
-        }
-#endif
+        if (status & GMR_FS_VLAN)
+                __vlan_hwaccel_put_tag(skb, be16_to_cpu(sky2->rx_tag));
+
         if (skb->ip_summed == CHECKSUM_NONE)
                 netif_receive_skb(skb);
         else
@@ -2543,14 +2501,19 @@ static inline void sky2_skb_rx(const struct sky2_port *sky2,
 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
                                 unsigned packets, unsigned bytes)
 {
-        if (packets) {
-                struct net_device *dev = hw->dev[port];
+        struct net_device *dev = hw->dev[port];
+        struct sky2_port *sky2 = netdev_priv(dev);
 
-                dev->stats.rx_packets += packets;
-                dev->stats.rx_bytes += bytes;
-                dev->last_rx = jiffies;
-                sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
-        }
+        if (packets == 0)
+                return;
+
+        u64_stats_update_begin(&sky2->rx_stats.syncp);
+        sky2->rx_stats.packets += packets;
+        sky2->rx_stats.bytes += bytes;
+        u64_stats_update_end(&sky2->rx_stats.syncp);
+
+        dev->last_rx = jiffies;
+        sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
 }
 
 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
@@ -2645,7 +2608,6 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
                                 goto exit_loop;
                         break;
 
-#ifdef SKY2_VLAN_TAG_USED
                 case OP_RXVLAN:
                         sky2->rx_tag = length;
                         break;
@@ -2653,7 +2615,6 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
                 case OP_RXCHKSVLAN:
                         sky2->rx_tag = length;
                         /* fall through */
-#endif
                 case OP_RXCHKS:
                         if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
                                 sky2_rx_checksum(sky2, status);
@@ -3056,6 +3017,10 @@ static int __devinit sky2_init(struct sky2_hw *hw)
                         | SKY2_HW_NEW_LE
                         | SKY2_HW_AUTO_TX_SUM
                         | SKY2_HW_ADV_POWER_CTL;
+
+                /* The workaround for status conflicts VLAN tag detection. */
+                if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
+                        hw->flags |= SKY2_HW_VLAN_BROKEN;
                 break;
 
         case CHIP_ID_YUKON_SUPR:
@@ -3398,12 +3363,24 @@ static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 {
         struct sky2_port *sky2 = netdev_priv(dev);
         struct sky2_hw *hw = sky2->hw;
+        bool enable_wakeup = false;
+        int i;
 
         if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
             !device_can_wakeup(&hw->pdev->dev))
                 return -EOPNOTSUPP;
 
         sky2->wol = wol->wolopts;
+
+        for (i = 0; i < hw->ports; i++) {
+                struct net_device *dev = hw->dev[i];
+                struct sky2_port *sky2 = netdev_priv(dev);
+
+                if (sky2->wol)
+                        enable_wakeup = true;
+        }
+        device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
+
         return 0;
 }
 
@@ -3413,18 +3390,15 @@ static u32 sky2_supported_modes(const struct sky2_hw *hw)
                 u32 modes = SUPPORTED_10baseT_Half
                         | SUPPORTED_10baseT_Full
                         | SUPPORTED_100baseT_Half
-                        | SUPPORTED_100baseT_Full
-                        | SUPPORTED_Autoneg | SUPPORTED_TP;
+                        | SUPPORTED_100baseT_Full;
 
                 if (hw->flags & SKY2_HW_GIGABIT)
                         modes |= SUPPORTED_1000baseT_Half
                                 | SUPPORTED_1000baseT_Full;
                 return modes;
         } else
-                return  SUPPORTED_1000baseT_Half
-                        | SUPPORTED_1000baseT_Full
-                        | SUPPORTED_Autoneg
-                        | SUPPORTED_FIBRE;
+                return SUPPORTED_1000baseT_Half
+                        | SUPPORTED_1000baseT_Full;
 }
 
 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
@@ -3438,9 +3412,11 @@ static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         if (sky2_is_copper(hw)) {
                 ecmd->port = PORT_TP;
                 ecmd->speed = sky2->speed;
+                ecmd->supported |=  SUPPORTED_Autoneg | SUPPORTED_TP;
         } else {
                 ecmd->speed = SPEED_1000;
                 ecmd->port = PORT_FIBRE;
+                ecmd->supported |=  SUPPORTED_Autoneg | SUPPORTED_FIBRE;
         }
 
         ecmd->advertising = sky2->advertising;
@@ -3457,8 +3433,19 @@ static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
         u32 supported = sky2_supported_modes(hw);
 
         if (ecmd->autoneg == AUTONEG_ENABLE) {
+                if (ecmd->advertising & ~supported)
+                        return -EINVAL;
+
+                if (sky2_is_copper(hw))
+                        sky2->advertising = ecmd->advertising |
+                                            ADVERTISED_TP |
+                                            ADVERTISED_Autoneg;
+                else
+                        sky2->advertising = ecmd->advertising |
+                                            ADVERTISED_FIBRE |
+                                            ADVERTISED_Autoneg;
+
                 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
-                ecmd->advertising = supported;
                 sky2->duplex = -1;
                 sky2->speed = -1;
         } else {
@@ -3502,8 +3489,6 @@ static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
                 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
         }
 
-        sky2->advertising = ecmd->advertising;
-
         if (netif_running(dev)) {
                 sky2_phy_reinit(sky2);
                 sky2_set_multicast(dev);
@@ -3614,13 +3599,11 @@ static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
         unsigned port = sky2->port;
         int i;
 
-        data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
-            | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
-        data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
-            | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
+        data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
+        data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
 
         for (i = 2; i < count; i++)
-                data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
+                data[i] = get_stats32(hw, port, sky2_stats[i].offset);
 }
 
 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
@@ -3738,6 +3721,51 @@ static void sky2_set_multicast(struct net_device *dev)
         gma_write16(hw, port, GM_RX_CTRL, reg);
 }
 
+static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
+                                                struct rtnl_link_stats64 *stats)
+{
+        struct sky2_port *sky2 = netdev_priv(dev);
+        struct sky2_hw *hw = sky2->hw;
+        unsigned port = sky2->port;
+        unsigned int start;
+        u64 _bytes, _packets;
+
+        do {
+                start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
+                _bytes = sky2->rx_stats.bytes;
+                _packets = sky2->rx_stats.packets;
+        } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
+
+        stats->rx_packets = _packets;
+        stats->rx_bytes = _bytes;
+
+        do {
+                start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
+                _bytes = sky2->tx_stats.bytes;
+                _packets = sky2->tx_stats.packets;
+        } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
+
+        stats->tx_packets = _packets;
+        stats->tx_bytes = _bytes;
+
+        stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
+                + get_stats32(hw, port, GM_RXF_BC_OK);
+
+        stats->collisions = get_stats32(hw, port, GM_TXF_COL);
+
+        stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
+        stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
+        stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
+                + get_stats32(hw, port, GM_RXE_FRAG);
+        stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
+
+        stats->rx_dropped = dev->stats.rx_dropped;
+        stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
+        stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
+
+        return stats;
+}
+
 /* Can have one global because blinking is controlled by
  * ethtool and that is always under RTNL mutex
  */
@@ -4188,15 +4216,28 @@ static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom
 static int sky2_set_flags(struct net_device *dev, u32 data)
 {
         struct sky2_port *sky2 = netdev_priv(dev);
-        u32 supported =
-                (sky2->hw->flags & SKY2_HW_RSS_BROKEN) ? 0 : ETH_FLAG_RXHASH;
+        unsigned long old_feat = dev->features;
+        u32 supported = 0;
         int rc;
 
+        if (!(sky2->hw->flags & SKY2_HW_RSS_BROKEN))
+                supported |= ETH_FLAG_RXHASH;
+
+        if (!(sky2->hw->flags & SKY2_HW_VLAN_BROKEN))
+                supported |= ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN;
+
+        printk(KERN_DEBUG "sky2 set_flags: supported %x data %x\n",
+               supported, data);
+
         rc = ethtool_op_set_flags(dev, data, supported);
         if (rc)
                 return rc;
 
-        rx_set_rss(dev);
+        if ((old_feat ^ dev->features) & NETIF_F_RXHASH)
+                rx_set_rss(dev);
+
+        if ((old_feat ^ dev->features) & NETIF_F_ALL_VLAN)
+                sky2_vlan_mode(dev);
 
         return 0;
 }
@@ -4232,6 +4273,7 @@ static const struct ethtool_ops sky2_ethtool_ops = {
         .get_sset_count = sky2_get_sset_count,
         .get_ethtool_stats = sky2_get_ethtool_stats,
         .set_flags      = sky2_set_flags,
+        .get_flags      = ethtool_op_get_flags,
 };
 
 #ifdef CONFIG_SKY2_DEBUG
@@ -4512,9 +4554,7 @@ static const struct net_device_ops sky2_netdev_ops[2] = {
         .ndo_set_multicast_list = sky2_set_multicast,
         .ndo_change_mtu         = sky2_change_mtu,
         .ndo_tx_timeout         = sky2_tx_timeout,
-#ifdef SKY2_VLAN_TAG_USED
-        .ndo_vlan_rx_register   = sky2_vlan_rx_register,
-#endif
+        .ndo_get_stats64        = sky2_get_stats,
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller    = sky2_netpoll,
 #endif
@@ -4529,9 +4569,7 @@ static const struct net_device_ops sky2_netdev_ops[2] = {
         .ndo_set_multicast_list = sky2_set_multicast,
         .ndo_change_mtu         = sky2_change_mtu,
         .ndo_tx_timeout         = sky2_tx_timeout,
-#ifdef SKY2_VLAN_TAG_USED
-        .ndo_vlan_rx_register   = sky2_vlan_rx_register,
-#endif
+        .ndo_get_stats64        = sky2_get_stats,
   },
 };
 
@@ -4582,7 +4620,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
         sky2->port = port;
 
         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG
-                | NETIF_F_TSO  | NETIF_F_GRO;
+                | NETIF_F_TSO | NETIF_F_GRO;
+
         if (highmem)
                 dev->features |= NETIF_F_HIGHDMA;
 
@@ -4590,13 +4629,8 @@ static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
         if (!(hw->flags & SKY2_HW_RSS_BROKEN))
                 dev->features |= NETIF_F_RXHASH;
 
-#ifdef SKY2_VLAN_TAG_USED
-        /* The workaround for FE+ status conflicts with VLAN tag detection. */
-        if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
-              sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
+        if (!(hw->flags & SKY2_HW_VLAN_BROKEN))
                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
-        }
-#endif
 
         /* read the mac address */
         memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
@@ -4920,10 +4954,11 @@ static void __devexit sky2_remove(struct pci_dev *pdev)
         pci_set_drvdata(pdev, NULL);
 }
 
-static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
+static int sky2_suspend(struct device *dev)
 {
+        struct pci_dev *pdev = to_pci_dev(dev);
         struct sky2_hw *hw = pci_get_drvdata(pdev);
-        int i, wol = 0;
+        int i;
 
         if (!hw)
                 return 0;
@@ -4940,41 +4975,24 @@ static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
 
                 if (sky2->wol)
                         sky2_wol_init(sky2);
-
-                wol |= sky2->wol;
         }
 
-        device_set_wakeup_enable(&pdev->dev, wol != 0);
-
         sky2_power_aux(hw);
         rtnl_unlock();
 
-        pci_save_state(pdev);
-        pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
-        pci_set_power_state(pdev, pci_choose_state(pdev, state));
-
         return 0;
 }
 
 #ifdef CONFIG_PM
-static int sky2_resume(struct pci_dev *pdev)
+static int sky2_resume(struct device *dev)
 {
+        struct pci_dev *pdev = to_pci_dev(dev);
         struct sky2_hw *hw = pci_get_drvdata(pdev);
         int err;
 
         if (!hw)
                 return 0;
 
-        err = pci_set_power_state(pdev, PCI_D0);
-        if (err)
-                goto out;
-
-        err = pci_restore_state(pdev);
-        if (err)
-                goto out;
-
-        pci_enable_wake(pdev, PCI_D0, 0);
-
         /* Re-enable all clocks */
         err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
         if (err) {
@@ -4994,11 +5012,20 @@ out:
         pci_disable_device(pdev);
         return err;
 }
+
+static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
+#define SKY2_PM_OPS (&sky2_pm_ops)
+
+#else
+
+#define SKY2_PM_OPS NULL
 #endif
 
 static void sky2_shutdown(struct pci_dev *pdev)
 {
-        sky2_suspend(pdev, PMSG_SUSPEND);
+        sky2_suspend(&pdev->dev);
+        pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
+        pci_set_power_state(pdev, PCI_D3hot);
 }
 
 static struct pci_driver sky2_driver = {
@@ -5006,11 +5033,8 @@ static struct pci_driver sky2_driver = {
         .id_table = sky2_id_table,
         .probe = sky2_probe,
         .remove = __devexit_p(sky2_remove),
-#ifdef CONFIG_PM
-        .suspend = sky2_suspend,
-        .resume = sky2_resume,
-#endif
         .shutdown = sky2_shutdown,
+        .driver.pm = SKY2_PM_OPS,
 };
 
 static int __init sky2_init_module(void)
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 61891a6cacc2..6861b0e8db9a 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -2200,6 +2200,12 @@ enum flow_control {
         FC_BOTH = 3,
 };
 
+struct sky2_stats {
+        struct u64_stats_sync syncp;
+        u64             packets;
+        u64             bytes;
+};
+
 struct sky2_port {
         struct sky2_hw       *hw;
         struct net_device    *netdev;
@@ -2209,6 +2215,8 @@ struct sky2_port {
 
         struct tx_ring_info  *tx_ring;
         struct sky2_tx_le    *tx_le;
+        struct sky2_stats    tx_stats;
+
         u16                  tx_ring_size;
         u16                  tx_cons;           /* next le to check */
         u16                  tx_prod;           /* next le to use */
@@ -2221,17 +2229,15 @@ struct sky2_port {
 
         struct rx_ring_info  *rx_ring ____cacheline_aligned_in_smp;
         struct sky2_rx_le    *rx_le;
+        struct sky2_stats    rx_stats;
 
         u16                  rx_next;           /* next re to check */
         u16                  rx_put;            /* next le index to use */
         u16                  rx_pending;
         u16                  rx_data_size;
         u16                  rx_nfrags;
-
-#ifdef SKY2_VLAN_TAG_USED
         u16                  rx_tag;
-        struct vlan_group    *vlgrp;
-#endif
+
         struct {
                 unsigned long last;
                 u32     mac_rp;
@@ -2275,6 +2281,7 @@ struct sky2_hw {
 #define SKY2_HW_AUTO_TX_SUM     0x00000040      /* new IP decode for Tx */
 #define SKY2_HW_ADV_POWER_CTL   0x00000080      /* additional PHY power regs */
 #define SKY2_HW_RSS_BROKEN      0x00000100
+#define SKY2_HW_VLAN_BROKEN     0x00000200
 
         u8                   chip_id;
         u8                   chip_rev;
@@ -2346,6 +2353,39 @@ static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
                 | (u32) sky2_read16(hw, base+4) << 16;
 }
 
+static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg)
+{
+        unsigned base = SK_GMAC_REG(port, reg);
+
+        return (u64) sky2_read16(hw, base)
+                | (u64) sky2_read16(hw, base+4) << 16
+                | (u64) sky2_read16(hw, base+8) << 32
+                | (u64) sky2_read16(hw, base+12) << 48;
+}
+
+/* There is no way to atomically read32 bit values from PHY, so retry */
+static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg)
+{
+        u32 val;
+
+        do {
+                val = gma_read32(hw, port, reg);
+        } while (gma_read32(hw, port, reg) != val);
+
+        return val;
+}
+
+static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg)
+{
+        u64 val;
+
+        do {
+                val = gma_read64(hw, port, reg);
+        } while (gma_read64(hw, port, reg) != val);
+
+        return val;
+}
+
 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
 {
         sky2_write16(hw, SK_GMAC_REG(port,r), v);
diff --git a/drivers/net/smc-ultra.c b/drivers/net/smc-ultra.c
index d2dd8e6113ab..235a3c6c9f91 100644
--- a/drivers/net/smc-ultra.c
+++ b/drivers/net/smc-ultra.c
@@ -277,8 +277,12 @@ static int __init ultra_probe1(struct net_device *dev, int ioaddr)
         dev->base_addr = ioaddr+ULTRA_NIC_OFFSET;
 
         {
-                int addr_tbl[4] = {0x0C0000, 0x0E0000, 0xFC0000, 0xFE0000};
-                short num_pages_tbl[4] = {0x20, 0x40, 0x80, 0xff};
+                static const int addr_tbl[4] = {
+                        0x0C0000, 0x0E0000, 0xFC0000, 0xFE0000
+                };
+                static const short num_pages_tbl[4] = {
+                        0x20, 0x40, 0x80, 0xff
+                };
 
                 dev->mem_start = ((addr & 0x0f) << 13) + addr_tbl[(addr >> 6) & 3] ;
                 num_pages = num_pages_tbl[(addr >> 4) & 3];
diff --git a/drivers/net/starfire.c b/drivers/net/starfire.c
index 4adf12422787..a4f2bd52e546 100644
--- a/drivers/net/starfire.c
+++ b/drivers/net/starfire.c
@@ -148,7 +148,7 @@ static int full_duplex[MAX_UNITS] = {0, };
  * This SUCKS.
  * We need a much better method to determine if dma_addr_t is 64-bit.
  */
-#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) || (defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT))
+#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || (defined(CONFIG_MIPS) && ((defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) || defined(CONFIG_64BIT))) || (defined(__powerpc64__) || defined(CONFIG_PHYS_64BIT))
 /* 64-bit dma_addr_t */
 #define ADDR_64BITS     /* This chip uses 64 bit addresses. */
 #define netdrv_addr_t __le64
diff --git a/drivers/net/stmmac/stmmac.h b/drivers/net/stmmac/stmmac.h
index 79bdc2e13224..5f06c4706abe 100644
--- a/drivers/net/stmmac/stmmac.h
+++ b/drivers/net/stmmac/stmmac.h
@@ -20,7 +20,7 @@
   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 *******************************************************************************/
 
-#define DRV_MODULE_VERSION      "Apr_2010"
+#define DRV_MODULE_VERSION      "Nov_2010"
 #include <linux/platform_device.h>
 #include <linux/stmmac.h>
 
@@ -37,7 +37,6 @@ struct stmmac_priv {
         unsigned int cur_tx;
         unsigned int dirty_tx;
         unsigned int dma_tx_size;
-        int tx_coe;
         int tx_coalesce;
 
         struct dma_desc *dma_rx ;
@@ -48,7 +47,6 @@ struct stmmac_priv {
         struct sk_buff_head rx_recycle;
 
         struct net_device *dev;
-        int is_gmac;
         dma_addr_t dma_rx_phy;
         unsigned int dma_rx_size;
         unsigned int dma_buf_sz;
@@ -60,14 +58,11 @@ struct stmmac_priv {
         struct napi_struct napi;
 
         phy_interface_t phy_interface;
-        int pbl;
-        int bus_id;
         int phy_addr;
         int phy_mask;
         int (*phy_reset) (void *priv);
-        void (*fix_mac_speed) (void *priv, unsigned int speed);
-        void (*bus_setup)(void __iomem *ioaddr);
-        void *bsp_priv;
+        int rx_coe;
+        int no_csum_insertion;
 
         int phy_irq;
         struct phy_device *phydev;
@@ -77,47 +72,20 @@ struct stmmac_priv {
         unsigned int flow_ctrl;
         unsigned int pause;
         struct mii_bus *mii;
-        int mii_clk_csr;
 
         u32 msg_enable;
         spinlock_t lock;
         int wolopts;
         int wolenabled;
-        int shutdown;
 #ifdef CONFIG_STMMAC_TIMER
         struct stmmac_timer *tm;
 #endif
 #ifdef STMMAC_VLAN_TAG_USED
         struct vlan_group *vlgrp;
 #endif
-        int enh_desc;
-        int rx_coe;
-        int bugged_jumbo;
-        int no_csum_insertion;
+        struct plat_stmmacenet_data *plat;
 };
 
-#ifdef CONFIG_STM_DRIVERS
-#include <linux/stm/pad.h>
-static inline int stmmac_claim_resource(struct platform_device *pdev)
-{
-        int ret = 0;
-        struct plat_stmmacenet_data *plat_dat = pdev->dev.platform_data;
-
-        /* Pad routing setup */
-        if (IS_ERR(devm_stm_pad_claim(&pdev->dev, plat_dat->pad_config,
-                        dev_name(&pdev->dev)))) {
-                printk(KERN_ERR "%s: Failed to request pads!\n", __func__);
-                ret = -ENODEV;
-        }
-        return ret;
-}
-#else
-static inline int stmmac_claim_resource(struct platform_device *pdev)
-{
-        return 0;
-}
-#endif
-
 extern int stmmac_mdio_unregister(struct net_device *ndev);
 extern int stmmac_mdio_register(struct net_device *ndev);
 extern void stmmac_set_ethtool_ops(struct net_device *netdev);
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index 6d65482e789a..fd719edc7f7c 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -94,7 +94,7 @@ static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
 {
         struct stmmac_priv *priv = netdev_priv(dev);
 
-        if (!priv->is_gmac)
+        if (!priv->plat->has_gmac)
                 strcpy(info->driver, MAC100_ETHTOOL_NAME);
         else
                 strcpy(info->driver, GMAC_ETHTOOL_NAME);
@@ -176,7 +176,7 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
 
         memset(reg_space, 0x0, REG_SPACE_SIZE);
 
-        if (!priv->is_gmac) {
+        if (!priv->plat->has_gmac) {
                 /* MAC registers */
                 for (i = 0; i < 12; i++)
                         reg_space[i] = readl(priv->ioaddr + (i * 4));
@@ -197,16 +197,6 @@ static void stmmac_ethtool_gregs(struct net_device *dev,
         }
 }
 
-static int stmmac_ethtool_set_tx_csum(struct net_device *netdev, u32 data)
-{
-        if (data)
-                netdev->features |= NETIF_F_HW_CSUM;
-        else
-                netdev->features &= ~NETIF_F_HW_CSUM;
-
-        return 0;
-}
-
 static u32 stmmac_ethtool_get_rx_csum(struct net_device *dev)
 {
         struct stmmac_priv *priv = netdev_priv(dev);
@@ -370,7 +360,7 @@ static struct ethtool_ops stmmac_ethtool_ops = {
         .get_link = ethtool_op_get_link,
         .get_rx_csum = stmmac_ethtool_get_rx_csum,
         .get_tx_csum = ethtool_op_get_tx_csum,
-        .set_tx_csum = stmmac_ethtool_set_tx_csum,
+        .set_tx_csum = ethtool_op_set_tx_ipv6_csum,
         .get_sg = ethtool_op_get_sg,
         .set_sg = ethtool_op_set_sg,
         .get_pauseparam = stmmac_get_pauseparam,
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 2114837809e7..34a0af3837f9 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -186,6 +186,18 @@ static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 }
 
+/* On some ST platforms, some HW system configuraton registers have to be
+ * set according to the link speed negotiated.
+ */
+static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
+{
+        struct phy_device *phydev = priv->phydev;
+
+        if (likely(priv->plat->fix_mac_speed))
+                priv->plat->fix_mac_speed(priv->plat->bsp_priv,
+                                          phydev->speed);
+}
+
 /**
  * stmmac_adjust_link
  * @dev: net device structure
@@ -228,15 +240,13 @@ static void stmmac_adjust_link(struct net_device *dev)
                         new_state = 1;
                         switch (phydev->speed) {
                         case 1000:
-                                if (likely(priv->is_gmac))
+                                if (likely(priv->plat->has_gmac))
                                         ctrl &= ~priv->hw->link.port;
-                                if (likely(priv->fix_mac_speed))
-                                        priv->fix_mac_speed(priv->bsp_priv,
-                                                            phydev->speed);
+                                stmmac_hw_fix_mac_speed(priv);
                                 break;
                         case 100:
                         case 10:
-                                if (priv->is_gmac) {
+                                if (priv->plat->has_gmac) {
                                         ctrl |= priv->hw->link.port;
                                         if (phydev->speed == SPEED_100) {
                                                 ctrl |= priv->hw->link.speed;
@@ -246,9 +256,7 @@ static void stmmac_adjust_link(struct net_device *dev)
                                 } else {
                                         ctrl &= ~priv->hw->link.port;
                                 }
-                                if (likely(priv->fix_mac_speed))
-                                        priv->fix_mac_speed(priv->bsp_priv,
-                                                            phydev->speed);
+                                stmmac_hw_fix_mac_speed(priv);
                                 break;
                         default:
                                 if (netif_msg_link(priv))
@@ -305,7 +313,7 @@ static int stmmac_init_phy(struct net_device *dev)
                 return 0;
         }
 
-        snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
+        snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
                  priv->phy_addr);
         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
@@ -552,7 +560,7 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
  */
 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 {
-        if (likely((priv->tx_coe) && (!priv->no_csum_insertion))) {
+        if (likely((priv->plat->tx_coe) && (!priv->no_csum_insertion))) {
                 /* In case of GMAC, SF mode has to be enabled
                  * to perform the TX COE. This depends on:
                  * 1) TX COE if actually supported
@@ -814,7 +822,7 @@ static int stmmac_open(struct net_device *dev)
         init_dma_desc_rings(dev);
 
         /* DMA initialization and SW reset */
-        if (unlikely(priv->hw->dma->init(priv->ioaddr, priv->pbl,
+        if (unlikely(priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
                                          priv->dma_tx_phy,
                                          priv->dma_rx_phy) < 0)) {
 
@@ -825,19 +833,17 @@ static int stmmac_open(struct net_device *dev)
         /* Copy the MAC addr into the HW  */
         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
         /* If required, perform hw setup of the bus. */
-        if (priv->bus_setup)
-                priv->bus_setup(priv->ioaddr);
+        if (priv->plat->bus_setup)
+                priv->plat->bus_setup(priv->ioaddr);
         /* Initialize the MAC Core */
         priv->hw->mac->core_init(priv->ioaddr);
 
         priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
         if (priv->rx_coe)
                 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
-        if (priv->tx_coe)
+        if (priv->plat->tx_coe)
                 pr_info("\tTX Checksum insertion supported\n");
 
-        priv->shutdown = 0;
-
         /* Initialise the MMC (if present) to disable all interrupts. */
         writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK);
         writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK);
@@ -943,7 +949,7 @@ static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
                skb, skb->len);
 
         segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
-        if (unlikely(IS_ERR(segs)))
+        if (IS_ERR(segs))
                 goto sw_tso_end;
 
         do {
@@ -1042,7 +1048,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
                 return stmmac_sw_tso(priv, skb);
 
         if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
-                if (unlikely((!priv->tx_coe) || (priv->no_csum_insertion)))
+                if (unlikely((!priv->plat->tx_coe) ||
+                             (priv->no_csum_insertion)))
                         skb_checksum_help(skb);
                 else
                         csum_insertion = 1;
@@ -1146,7 +1153,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv)
                                            DMA_FROM_DEVICE);
 
                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
-                        if (unlikely(priv->is_gmac)) {
+                        if (unlikely(priv->plat->has_gmac)) {
                                 if (bfsize >= BUF_SIZE_8KiB)
                                         (p + entry)->des3 =
                                             (p + entry)->des2 + BUF_SIZE_8KiB;
@@ -1356,7 +1363,7 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
                 return -EBUSY;
         }
 
-        if (priv->is_gmac)
+        if (priv->plat->has_gmac)
                 max_mtu = JUMBO_LEN;
         else
                 max_mtu = ETH_DATA_LEN;
@@ -1370,7 +1377,7 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
          * needs to have the Tx COE disabled for oversized frames
          * (due to limited buffer sizes). In this case we disable
          * the TX csum insertionin the TDES and not use SF. */
-        if ((priv->bugged_jumbo) && (priv->dev->mtu > ETH_DATA_LEN))
+        if ((priv->plat->bugged_jumbo) && (priv->dev->mtu > ETH_DATA_LEN))
                 priv->no_csum_insertion = 1;
         else
                 priv->no_csum_insertion = 0;
@@ -1390,7 +1397,7 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
                 return IRQ_NONE;
         }
 
-        if (priv->is_gmac)
+        if (priv->plat->has_gmac)
                 /* To handle GMAC own interrupts */
                 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
 
@@ -1487,7 +1494,8 @@ static int stmmac_probe(struct net_device *dev)
         dev->netdev_ops = &stmmac_netdev_ops;
         stmmac_set_ethtool_ops(dev);
 
-        dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
+        dev->features |= NETIF_F_SG | NETIF_F_HIGHDMA |
+                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
         dev->watchdog_timeo = msecs_to_jiffies(watchdog);
 #ifdef STMMAC_VLAN_TAG_USED
         /* Both mac100 and gmac support receive VLAN tag detection */
@@ -1520,7 +1528,7 @@ static int stmmac_probe(struct net_device *dev)
 
         DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
             dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
-            (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
+            (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
 
         return ret;
 }
@@ -1536,7 +1544,7 @@ static int stmmac_mac_device_setup(struct net_device *dev)
 
         struct mac_device_info *device;
 
-        if (priv->is_gmac)
+        if (priv->plat->has_gmac)
                 device = dwmac1000_setup(priv->ioaddr);
         else
                 device = dwmac100_setup(priv->ioaddr);
@@ -1544,7 +1552,7 @@ static int stmmac_mac_device_setup(struct net_device *dev)
         if (!device)
                 return -ENOMEM;
 
-        if (priv->enh_desc) {
+        if (priv->plat->enh_desc) {
                 device->desc = &enh_desc_ops;
                 pr_info("\tEnhanced descriptor structure\n");
         } else
@@ -1598,7 +1606,7 @@ static int stmmac_associate_phy(struct device *dev, void *data)
                 plat_dat->bus_id);
 
         /* Check that this phy is for the MAC being initialised */
-        if (priv->bus_id != plat_dat->bus_id)
+        if (priv->plat->bus_id != plat_dat->bus_id)
                 return 0;
 
         /* OK, this PHY is connected to the MAC.
@@ -1634,15 +1642,13 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
         struct resource *res;
         void __iomem *addr = NULL;
         struct net_device *ndev = NULL;
-        struct stmmac_priv *priv;
+        struct stmmac_priv *priv = NULL;
         struct plat_stmmacenet_data *plat_dat;
 
         pr_info("STMMAC driver:\n\tplatform registration... ");
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                ret = -ENODEV;
-                goto out;
-        }
+        if (!res)
+                return -ENODEV;
         pr_info("\tdone!\n");
 
         if (!request_mem_region(res->start, resource_size(res),
@@ -1650,22 +1656,21 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
                 pr_err("%s: ERROR: memory allocation failed"
                        "cannot get the I/O addr 0x%x\n",
                        __func__, (unsigned int)res->start);
-                ret = -EBUSY;
-                goto out;
+                return -EBUSY;
         }
 
         addr = ioremap(res->start, resource_size(res));
         if (!addr) {
                 pr_err("%s: ERROR: memory mapping failed\n", __func__);
                 ret = -ENOMEM;
-                goto out;
+                goto out_release_region;
         }
 
         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
         if (!ndev) {
                 pr_err("%s: ERROR: allocating the device\n", __func__);
                 ret = -ENOMEM;
-                goto out;
+                goto out_unmap;
         }
 
         SET_NETDEV_DEV(ndev, &pdev->dev);
@@ -1675,21 +1680,17 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
         if (ndev->irq == -ENXIO) {
                 pr_err("%s: ERROR: MAC IRQ configuration "
                        "information not found\n", __func__);
-                ret = -ENODEV;
-                goto out;
+                ret = -ENXIO;
+                goto out_free_ndev;
         }
 
         priv = netdev_priv(ndev);
         priv->device = &(pdev->dev);
         priv->dev = ndev;
         plat_dat = pdev->dev.platform_data;
-        priv->bus_id = plat_dat->bus_id;
-        priv->pbl = plat_dat->pbl;      /* TLI */
-        priv->mii_clk_csr = plat_dat->clk_csr;
-        priv->tx_coe = plat_dat->tx_coe;
-        priv->bugged_jumbo = plat_dat->bugged_jumbo;
-        priv->is_gmac = plat_dat->has_gmac;     /* GMAC is on board */
-        priv->enh_desc = plat_dat->enh_desc;
+
+        priv->plat = plat_dat;
+
         priv->ioaddr = addr;
 
         /* PMT module is not integrated in all the MAC devices. */
@@ -1703,20 +1704,22 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
         /* Set the I/O base addr */
         ndev->base_addr = (unsigned long)addr;
 
-        /* Verify embedded resource for the platform */
-        ret = stmmac_claim_resource(pdev);
-        if (ret < 0)
-                goto out;
+        /* Custom initialisation */
+        if (priv->plat->init) {
+                ret = priv->plat->init(pdev);
+                if (unlikely(ret))
+                        goto out_free_ndev;
+        }
 
         /* MAC HW revice detection */
         ret = stmmac_mac_device_setup(ndev);
         if (ret < 0)
-                goto out;
+                goto out_plat_exit;
 
         /* Network Device Registration */
         ret = stmmac_probe(ndev);
         if (ret < 0)
-                goto out;
+                goto out_plat_exit;
 
         /* associate a PHY - it is provided by another platform bus */
         if (!driver_for_each_device
@@ -1724,31 +1727,33 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
              stmmac_associate_phy)) {
                 pr_err("No PHY device is associated with this MAC!\n");
                 ret = -ENODEV;
-                goto out;
+                goto out_unregister;
         }
 
-        priv->fix_mac_speed = plat_dat->fix_mac_speed;
-        priv->bus_setup = plat_dat->bus_setup;
-        priv->bsp_priv = plat_dat->bsp_priv;
-
         pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
                "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
                pdev->id, ndev->irq, addr);
 
         /* MDIO bus Registration */
-        pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
+        pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
         ret = stmmac_mdio_register(ndev);
         if (ret < 0)
-                goto out;
+                goto out_unregister;
         pr_debug("registered!\n");
+        return 0;
 
-out:
-        if (ret < 0) {
-                platform_set_drvdata(pdev, NULL);
-                release_mem_region(res->start, resource_size(res));
-                if (addr != NULL)
-                        iounmap(addr);
-        }
+out_unregister:
+        unregister_netdev(ndev);
+out_plat_exit:
+        if (priv->plat->exit)
+                priv->plat->exit(pdev);
+out_free_ndev:
+        free_netdev(ndev);
+        platform_set_drvdata(pdev, NULL);
+out_unmap:
+        iounmap(addr);
+out_release_region:
+        release_mem_region(res->start, resource_size(res));
 
         return ret;
 }
@@ -1777,6 +1782,9 @@ static int stmmac_dvr_remove(struct platform_device *pdev)
 
         stmmac_mdio_unregister(ndev);
 
+        if (priv->plat->exit)
+                priv->plat->exit(pdev);
+
         platform_set_drvdata(pdev, NULL);
         unregister_netdev(ndev);
 
@@ -1790,69 +1798,54 @@ static int stmmac_dvr_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
+static int stmmac_suspend(struct device *dev)
 {
-        struct net_device *dev = platform_get_drvdata(pdev);
-        struct stmmac_priv *priv = netdev_priv(dev);
+        struct net_device *ndev = dev_get_drvdata(dev);
+        struct stmmac_priv *priv = netdev_priv(ndev);
         int dis_ic = 0;
 
-        if (!dev || !netif_running(dev))
+        if (!ndev || !netif_running(ndev))
                 return 0;
 
         spin_lock(&priv->lock);
 
-        if (state.event == PM_EVENT_SUSPEND) {
-                netif_device_detach(dev);
-                netif_stop_queue(dev);
-                if (priv->phydev)
-                        phy_stop(priv->phydev);
+        netif_device_detach(ndev);
+        netif_stop_queue(ndev);
+        if (priv->phydev)
+                phy_stop(priv->phydev);
 
 #ifdef CONFIG_STMMAC_TIMER
-                priv->tm->timer_stop();
-                if (likely(priv->tm->enable))
-                        dis_ic = 1;
+        priv->tm->timer_stop();
+        if (likely(priv->tm->enable))
+                dis_ic = 1;
 #endif
-                napi_disable(&priv->napi);
-
-                /* Stop TX/RX DMA */
-                priv->hw->dma->stop_tx(priv->ioaddr);
-                priv->hw->dma->stop_rx(priv->ioaddr);
-                /* Clear the Rx/Tx descriptors */
-                priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
-                                             dis_ic);
-                priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
-
-                /* Enable Power down mode by programming the PMT regs */
-                if (device_can_wakeup(priv->device))
-                        priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
-                else
-                        stmmac_disable_mac(priv->ioaddr);
-        } else {
-                priv->shutdown = 1;
-                /* Although this can appear slightly redundant it actually
-                 * makes fast the standby operation and guarantees the driver
-                 * working if hibernation is on media. */
-                stmmac_release(dev);
-        }
+        napi_disable(&priv->napi);
+
+        /* Stop TX/RX DMA */
+        priv->hw->dma->stop_tx(priv->ioaddr);
+        priv->hw->dma->stop_rx(priv->ioaddr);
+        /* Clear the Rx/Tx descriptors */
+        priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
+                                     dis_ic);
+        priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
+
+        /* Enable Power down mode by programming the PMT regs */
+        if (device_may_wakeup(priv->device))
+                priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
+        else
+                stmmac_disable_mac(priv->ioaddr);
 
         spin_unlock(&priv->lock);
         return 0;
 }
 
-static int stmmac_resume(struct platform_device *pdev)
+static int stmmac_resume(struct device *dev)
 {
-        struct net_device *dev = platform_get_drvdata(pdev);
-        struct stmmac_priv *priv = netdev_priv(dev);
-
-        if (!netif_running(dev))
-                return 0;
+        struct net_device *ndev = dev_get_drvdata(dev);
+        struct stmmac_priv *priv = netdev_priv(ndev);
 
-        if (priv->shutdown) {
-                /* Re-open the interface and re-init the MAC/DMA
-                   and the rings (i.e. on hibernation stage) */
-                stmmac_open(dev);
+        if (!netif_running(ndev))
                 return 0;
-        }
 
         spin_lock(&priv->lock);
 
@@ -1861,10 +1854,10 @@ static int stmmac_resume(struct platform_device *pdev)
          * is received. Anyway, it's better to manually clear
          * this bit because it can generate problems while resuming
          * from another devices (e.g. serial console). */
-        if (device_can_wakeup(priv->device))
+        if (device_may_wakeup(priv->device))
                 priv->hw->mac->pmt(priv->ioaddr, 0);
 
-        netif_device_attach(dev);
+        netif_device_attach(ndev);
 
         /* Enable the MAC and DMA */
         stmmac_enable_mac(priv->ioaddr);
@@ -1872,31 +1865,59 @@ static int stmmac_resume(struct platform_device *pdev)
         priv->hw->dma->start_rx(priv->ioaddr);
 
 #ifdef CONFIG_STMMAC_TIMER
-        priv->tm->timer_start(tmrate);
+        if (likely(priv->tm->enable))
+                priv->tm->timer_start(tmrate);
 #endif
         napi_enable(&priv->napi);
 
         if (priv->phydev)
                 phy_start(priv->phydev);
 
-        netif_start_queue(dev);
+        netif_start_queue(ndev);
 
         spin_unlock(&priv->lock);
         return 0;
 }
-#endif
 
-static struct platform_driver stmmac_driver = {
-        .driver = {
-                   .name = STMMAC_RESOURCE_NAME,
-                   },
-        .probe = stmmac_dvr_probe,
-        .remove = stmmac_dvr_remove,
-#ifdef CONFIG_PM
+static int stmmac_freeze(struct device *dev)
+{
+        struct net_device *ndev = dev_get_drvdata(dev);
+
+        if (!ndev || !netif_running(ndev))
+                return 0;
+
+        return stmmac_release(ndev);
+}
+
+static int stmmac_restore(struct device *dev)
+{
+        struct net_device *ndev = dev_get_drvdata(dev);
+
+        if (!ndev || !netif_running(ndev))
+                return 0;
+
+        return stmmac_open(ndev);
+}
+
+static const struct dev_pm_ops stmmac_pm_ops = {
         .suspend = stmmac_suspend,
         .resume = stmmac_resume,
-#endif
+        .freeze = stmmac_freeze,
+        .thaw = stmmac_restore,
+        .restore = stmmac_restore,
+};
+#else
+static const struct dev_pm_ops stmmac_pm_ops;
+#endif /* CONFIG_PM */
 
+static struct platform_driver stmmac_driver = {
+        .probe = stmmac_dvr_probe,
+        .remove = stmmac_dvr_remove,
+        .driver = {
+                .name = STMMAC_RESOURCE_NAME,
+                .owner = THIS_MODULE,
+                .pm = &stmmac_pm_ops,
+        },
 };
 
 /**
diff --git a/drivers/net/stmmac/stmmac_mdio.c b/drivers/net/stmmac/stmmac_mdio.c
index d7441616357d..234b4068a1fc 100644
--- a/drivers/net/stmmac/stmmac_mdio.c
+++ b/drivers/net/stmmac/stmmac_mdio.c
@@ -53,7 +53,7 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
         int data;
         u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
                         ((phyreg << 6) & (0x000007C0)));
-        regValue |= MII_BUSY | ((priv->mii_clk_csr & 7) << 2);
+        regValue |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
 
         do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1);
         writel(regValue, priv->ioaddr + mii_address);
@@ -85,7 +85,7 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
             (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
             | MII_WRITE;
 
-        value |= MII_BUSY | ((priv->mii_clk_csr & 7) << 2);
+        value |= MII_BUSY | ((priv->plat->clk_csr & 7) << 2);
 
 
         /* Wait until any existing MII operation is complete */
@@ -114,7 +114,7 @@ static int stmmac_mdio_reset(struct mii_bus *bus)
 
         if (priv->phy_reset) {
                 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
-                priv->phy_reset(priv->bsp_priv);
+                priv->phy_reset(priv->plat->bsp_priv);
         }
 
         /* This is a workaround for problems with the STE101P PHY.
@@ -157,7 +157,7 @@ int stmmac_mdio_register(struct net_device *ndev)
         new_bus->read = &stmmac_mdio_read;
         new_bus->write = &stmmac_mdio_write;
         new_bus->reset = &stmmac_mdio_reset;
-        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
+        snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
         new_bus->priv = ndev;
         new_bus->irq = irqlist;
         new_bus->phy_mask = priv->phy_mask;
diff --git a/drivers/net/sundance.c b/drivers/net/sundance.c
index 3ed2a67bd6d3..4793df843c24 100644
--- a/drivers/net/sundance.c
+++ b/drivers/net/sundance.c
@@ -294,6 +294,9 @@ enum alta_offsets {
         /* Aliased and bogus values! */
         RxStatus = 0x0c,
 };
+
+#define ASIC_HI_WORD(x) ((x) + 2)
+
 enum ASICCtrl_HiWord_bit {
         GlobalReset = 0x0001,
         RxReset = 0x0002,
@@ -431,6 +434,7 @@ static void netdev_error(struct net_device *dev, int intr_status);
 static void netdev_error(struct net_device *dev, int intr_status);
 static void set_rx_mode(struct net_device *dev);
 static int __set_mac_addr(struct net_device *dev);
+static int sundance_set_mac_addr(struct net_device *dev, void *data);
 static struct net_device_stats *get_stats(struct net_device *dev);
 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 static int  netdev_close(struct net_device *dev);
@@ -464,7 +468,7 @@ static const struct net_device_ops netdev_ops = {
         .ndo_do_ioctl           = netdev_ioctl,
         .ndo_tx_timeout         = tx_timeout,
         .ndo_change_mtu         = change_mtu,
-        .ndo_set_mac_address    = eth_mac_addr,
+        .ndo_set_mac_address    = sundance_set_mac_addr,
         .ndo_validate_addr      = eth_validate_addr,
 };
 
@@ -1016,7 +1020,7 @@ static void init_ring(struct net_device *dev)
 
         /* Fill in the Rx buffers.  Handle allocation failure gracefully. */
         for (i = 0; i < RX_RING_SIZE; i++) {
-                struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
+                struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + 2);
                 np->rx_skbuff[i] = skb;
                 if (skb == NULL)
                         break;
@@ -1407,7 +1411,7 @@ static void refill_rx (struct net_device *dev)
                 struct sk_buff *skb;
                 entry = np->dirty_rx % RX_RING_SIZE;
                 if (np->rx_skbuff[entry] == NULL) {
-                        skb = dev_alloc_skb(np->rx_buf_sz);
+                        skb = dev_alloc_skb(np->rx_buf_sz + 2);
                         np->rx_skbuff[entry] = skb;
                         if (skb == NULL)
                                 break;          /* Better luck next round. */
@@ -1592,6 +1596,19 @@ static int __set_mac_addr(struct net_device *dev)
         return 0;
 }
 
+/* Invoked with rtnl_lock held */
+static int sundance_set_mac_addr(struct net_device *dev, void *data)
+{
+        const struct sockaddr *addr = data;
+
+        if (!is_valid_ether_addr(addr->sa_data))
+                return -EINVAL;
+        memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
+        __set_mac_addr(dev);
+
+        return 0;
+}
+
 static const struct {
         const char name[ETH_GSTRING_LEN];
 } sundance_stats[] = {
@@ -1772,10 +1789,10 @@ static int netdev_close(struct net_device *dev)
         }
 
         iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
-                        ioaddr +ASICCtrl + 2);
+                        ioaddr + ASIC_HI_WORD(ASICCtrl));
 
         for (i = 2000; i > 0; i--) {
-                if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
+                if ((ioread16(ioaddr + ASIC_HI_WORD(ASICCtrl)) & ResetBusy) == 0)
                         break;
                 mdelay(1);
         }
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
index 4ceb3cf6a9a9..1c5408f83937 100644
--- a/drivers/net/sungem.c
+++ b/drivers/net/sungem.c
@@ -1004,7 +1004,7 @@ static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
 
         ctrl = 0;
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                const u64 csum_start_off = skb_transport_offset(skb);
+                const u64 csum_start_off = skb_checksum_start_offset(skb);
                 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
 
                 ctrl = (TXDCTRL_CENAB |
@@ -2380,10 +2380,8 @@ static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
          */
         mutex_unlock(&gp->pm_mutex);
 
-        /* Wait for a pending reset task to complete */
-        while (gp->reset_task_pending)
-                yield();
-        flush_scheduled_work();
+        /* Wait for the pending reset task to complete */
+        flush_work_sync(&gp->reset_task);
 
         /* Shut the PHY down eventually and setup WOL */
         gem_stop_phy(gp, gp->asleep_wol);
@@ -2928,10 +2926,8 @@ static void gem_remove_one(struct pci_dev *pdev)
                 /* We shouldn't need any locking here */
                 gem_get_cell(gp);
 
-                /* Wait for a pending reset task to complete */
-                while (gp->reset_task_pending)
-                        yield();
-                flush_scheduled_work();
+                /* Cancel reset task */
+                cancel_work_sync(&gp->reset_task);
 
                 /* Shut the PHY down */
                 gem_stop_phy(gp, 0);
diff --git a/drivers/net/sunhme.c b/drivers/net/sunhme.c
index 5e28c414421a..55bbb9c15d96 100644
--- a/drivers/net/sunhme.c
+++ b/drivers/net/sunhme.c
@@ -2266,7 +2266,7 @@ static netdev_tx_t happy_meal_start_xmit(struct sk_buff *skb,
 
         tx_flags = TXFLAG_OWN;
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                const u32 csum_start_off = skb_transport_offset(skb);
+                const u32 csum_start_off = skb_checksum_start_offset(skb);
                 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
 
                 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
diff --git a/drivers/net/sunlance.c b/drivers/net/sunlance.c
index 2cf84e5968b2..767e1e2b210d 100644
--- a/drivers/net/sunlance.c
+++ b/drivers/net/sunlance.c
@@ -1295,17 +1295,9 @@ static void sparc_lance_get_drvinfo(struct net_device *dev, struct ethtool_drvin
         strcpy(info->version, "2.02");
 }
 
-static u32 sparc_lance_get_link(struct net_device *dev)
-{
-        /* We really do not keep track of this, but this
-         * is better than not reporting anything at all.
-         */
-        return 1;
-}
-
 static const struct ethtool_ops sparc_lance_ethtool_ops = {
         .get_drvinfo            = sparc_lance_get_drvinfo,
-        .get_link               = sparc_lance_get_link,
+        .get_link               = ethtool_op_get_link,
 };
 
 static const struct net_device_ops sparc_lance_ops = {
diff --git a/drivers/net/tehuti.c b/drivers/net/tehuti.c
index 474652a2f70d..3397618d4d96 100644
--- a/drivers/net/tehuti.c
+++ b/drivers/net/tehuti.c
@@ -324,7 +324,7 @@ static int bdx_fw_load(struct bdx_priv *priv)
         ENTER;
         master = READ_REG(priv, regINIT_SEMAPHORE);
         if (!READ_REG(priv, regINIT_STATUS) && master) {
-                rc = request_firmware(&fw, "tehuti/firmware.bin", &priv->pdev->dev);
+                rc = request_firmware(&fw, "tehuti/bdx.bin", &priv->pdev->dev);
                 if (rc)
                         goto out;
                 bdx_tx_push_desc_safe(priv, (char *)fw->data, fw->size);
@@ -2510,4 +2510,4 @@ module_exit(bdx_module_exit);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR(DRIVER_AUTHOR);
 MODULE_DESCRIPTION(BDX_DRV_DESC);
-MODULE_FIRMWARE("tehuti/firmware.bin");
+MODULE_FIRMWARE("tehuti/bdx.bin");
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 30ccbb6d097a..7841a8f69998 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -32,6 +32,7 @@
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/ethtool.h>
+#include <linux/mdio.h>
 #include <linux/mii.h>
 #include <linux/phy.h>
 #include <linux/brcmphy.h>
@@ -69,10 +70,10 @@
 
 #define DRV_MODULE_NAME         "tg3"
 #define TG3_MAJ_NUM                     3
-#define TG3_MIN_NUM                     115
+#define TG3_MIN_NUM                     116
 #define DRV_MODULE_VERSION      \
         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
-#define DRV_MODULE_RELDATE      "October 14, 2010"
+#define DRV_MODULE_RELDATE      "December 3, 2010"
 
 #define TG3_DEF_MAC_MODE        0
 #define TG3_DEF_RX_MODE         0
@@ -1769,9 +1770,9 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
 
         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
             current_link_up == 1 &&
-            (tp->link_config.active_speed == SPEED_1000 ||
-             (tp->link_config.active_speed == SPEED_100 &&
-              tp->link_config.active_duplex == DUPLEX_FULL))) {
+            tp->link_config.active_duplex == DUPLEX_FULL &&
+            (tp->link_config.active_speed == SPEED_100 ||
+             tp->link_config.active_speed == SPEED_1000)) {
                 u32 eeectl;
 
                 if (tp->link_config.active_speed == SPEED_1000)
@@ -1781,7 +1782,8 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
 
                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
 
-                tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
+                tg3_phy_cl45_read(tp, MDIO_MMD_AN,
+                                  TG3_CL45_D7_EEERES_STAT, &val);
 
                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
@@ -2549,39 +2551,35 @@ static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
         tw32(MAC_TX_BACKOFF_SEED, addr_high);
 }
 
-static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
+static void tg3_enable_register_access(struct tg3 *tp)
 {
-        u32 misc_host_ctrl;
-        bool device_should_wake, do_low_power;
-
-        /* Make sure register accesses (indirect or otherwise)
-         * will function correctly.
+        /*
+         * Make sure register accesses (indirect or otherwise) will function
+         * correctly.
          */
         pci_write_config_dword(tp->pdev,
-                               TG3PCI_MISC_HOST_CTRL,
-                               tp->misc_host_ctrl);
+                               TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
+}
 
-        switch (state) {
-        case PCI_D0:
-                pci_enable_wake(tp->pdev, state, false);
-                pci_set_power_state(tp->pdev, PCI_D0);
+static int tg3_power_up(struct tg3 *tp)
+{
+        tg3_enable_register_access(tp);
 
-                /* Switch out of Vaux if it is a NIC */
-                if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
-                        tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
+        pci_set_power_state(tp->pdev, PCI_D0);
 
-                return 0;
+        /* Switch out of Vaux if it is a NIC */
+        if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
+                tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
 
-        case PCI_D1:
-        case PCI_D2:
-        case PCI_D3hot:
-                break;
+        return 0;
+}
 
-        default:
-                netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
-                           state);
-                return -EINVAL;
-        }
+static int tg3_power_down_prepare(struct tg3 *tp)
+{
+        u32 misc_host_ctrl;
+        bool device_should_wake, do_low_power;
+
+        tg3_enable_register_access(tp);
 
         /* Restore the CLKREQ setting. */
         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
@@ -2600,8 +2598,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
         tw32(TG3PCI_MISC_HOST_CTRL,
              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
 
-        device_should_wake = pci_pme_capable(tp->pdev, state) &&
-                             device_may_wakeup(&tp->pdev->dev) &&
+        device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
 
         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
@@ -2728,12 +2725,10 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
 
-                if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
-                        mac_mode |= tp->mac_mode &
-                                    (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
-                        if (mac_mode & MAC_MODE_APE_TX_EN)
-                                mac_mode |= MAC_MODE_TDE_ENABLE;
-                }
+                if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+                        mac_mode |= MAC_MODE_APE_TX_EN |
+                                    MAC_MODE_APE_RX_EN |
+                                    MAC_MODE_TDE_ENABLE;
 
                 tw32_f(MAC_MODE, mac_mode);
                 udelay(100);
@@ -2823,13 +2818,15 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
 
         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
 
-        if (device_should_wake)
-                pci_enable_wake(tp->pdev, state, true);
+        return 0;
+}
 
-        /* Finally, set the new power state. */
-        pci_set_power_state(tp->pdev, state);
+static void tg3_power_down(struct tg3 *tp)
+{
+        tg3_power_down_prepare(tp);
 
-        return 0;
+        pci_wake_from_d3(tp->pdev, tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
+        pci_set_power_state(tp->pdev, PCI_D3hot);
 }
 
 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
@@ -2969,7 +2966,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
         }
 
         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-                u32 val = 0;
+                u32 val;
 
                 tw32(TG3_CPMU_EEE_MODE,
                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
@@ -2986,19 +2983,18 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
 
+                val = 0;
                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
                         /* Advertise 100-BaseTX EEE ability */
                         if (tp->link_config.advertising &
-                            (ADVERTISED_100baseT_Half |
-                             ADVERTISED_100baseT_Full))
-                                val |= TG3_CL45_D7_EEEADV_CAP_100TX;
+                            ADVERTISED_100baseT_Full)
+                                val |= MDIO_AN_EEE_ADV_100TX;
                         /* Advertise 1000-BaseT EEE ability */
                         if (tp->link_config.advertising &
-                            (ADVERTISED_1000baseT_Half |
-                             ADVERTISED_1000baseT_Full))
-                                val |= TG3_CL45_D7_EEEADV_CAP_1000T;
+                            ADVERTISED_1000baseT_Full)
+                                val |= MDIO_AN_EEE_ADV_1000T;
                 }
-                tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
+                tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
 
                 /* Turn off SM_DSP clock. */
                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
@@ -5763,7 +5759,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
 
         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
-            !mss && skb->len > ETH_DATA_LEN)
+            !mss && skb->len > VLAN_ETH_FRAME_LEN)
                 base_flags |= TXD_FLAG_JMB_PKT;
 
         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
@@ -5997,7 +5993,7 @@ static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
 #endif
 
         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
-            !mss && skb->len > ETH_DATA_LEN)
+            !mss && skb->len > VLAN_ETH_FRAME_LEN)
                 base_flags |= TXD_FLAG_JMB_PKT;
 
         len = skb_headlen(skb);
@@ -6339,13 +6335,13 @@ static void tg3_rx_prodring_fini(struct tg3 *tp,
         kfree(tpr->rx_jmb_buffers);
         tpr->rx_jmb_buffers = NULL;
         if (tpr->rx_std) {
-                pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
-                                    tpr->rx_std, tpr->rx_std_mapping);
+                dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
+                                  tpr->rx_std, tpr->rx_std_mapping);
                 tpr->rx_std = NULL;
         }
         if (tpr->rx_jmb) {
-                pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
-                                    tpr->rx_jmb, tpr->rx_jmb_mapping);
+                dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
+                                  tpr->rx_jmb, tpr->rx_jmb_mapping);
                 tpr->rx_jmb = NULL;
         }
 }
@@ -6358,8 +6354,10 @@ static int tg3_rx_prodring_init(struct tg3 *tp,
         if (!tpr->rx_std_buffers)
                 return -ENOMEM;
 
-        tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
-                                           &tpr->rx_std_mapping);
+        tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
+                                         TG3_RX_STD_RING_BYTES(tp),
+                                         &tpr->rx_std_mapping,
+                                         GFP_KERNEL);
         if (!tpr->rx_std)
                 goto err_out;
 
@@ -6370,9 +6368,10 @@ static int tg3_rx_prodring_init(struct tg3 *tp,
                 if (!tpr->rx_jmb_buffers)
                         goto err_out;
 
-                tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
-                                                   TG3_RX_JMB_RING_BYTES(tp),
-                                                   &tpr->rx_jmb_mapping);
+                tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
+                                                 TG3_RX_JMB_RING_BYTES(tp),
+                                                 &tpr->rx_jmb_mapping,
+                                                 GFP_KERNEL);
                 if (!tpr->rx_jmb)
                         goto err_out;
         }
@@ -6491,7 +6490,7 @@ static void tg3_free_consistent(struct tg3 *tp)
                 struct tg3_napi *tnapi = &tp->napi[i];
 
                 if (tnapi->tx_ring) {
-                        pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
+                        dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
                         tnapi->tx_ring = NULL;
                 }
@@ -6500,25 +6499,26 @@ static void tg3_free_consistent(struct tg3 *tp)
                 tnapi->tx_buffers = NULL;
 
                 if (tnapi->rx_rcb) {
-                        pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
-                                            tnapi->rx_rcb,
-                                            tnapi->rx_rcb_mapping);
+                        dma_free_coherent(&tp->pdev->dev,
+                                          TG3_RX_RCB_RING_BYTES(tp),
+                                          tnapi->rx_rcb,
+                                          tnapi->rx_rcb_mapping);
                         tnapi->rx_rcb = NULL;
                 }
 
                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
 
                 if (tnapi->hw_status) {
-                        pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
-                                            tnapi->hw_status,
-                                            tnapi->status_mapping);
+                        dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
+                                          tnapi->hw_status,
+                                          tnapi->status_mapping);
                         tnapi->hw_status = NULL;
                 }
         }
 
         if (tp->hw_stats) {
-                pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
-                                    tp->hw_stats, tp->stats_mapping);
+                dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
+                                  tp->hw_stats, tp->stats_mapping);
                 tp->hw_stats = NULL;
         }
 }
@@ -6531,9 +6531,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
 {
         int i;
 
-        tp->hw_stats = pci_alloc_consistent(tp->pdev,
-                                            sizeof(struct tg3_hw_stats),
-                                            &tp->stats_mapping);
+        tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
+                                          sizeof(struct tg3_hw_stats),
+                                          &tp->stats_mapping,
+                                          GFP_KERNEL);
         if (!tp->hw_stats)
                 goto err_out;
 
@@ -6543,9 +6544,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                 struct tg3_napi *tnapi = &tp->napi[i];
                 struct tg3_hw_status *sblk;
 
-                tnapi->hw_status = pci_alloc_consistent(tp->pdev,
-                                                        TG3_HW_STATUS_SIZE,
-                                                        &tnapi->status_mapping);
+                tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
+                                                      TG3_HW_STATUS_SIZE,
+                                                      &tnapi->status_mapping,
+                                                      GFP_KERNEL);
                 if (!tnapi->hw_status)
                         goto err_out;
 
@@ -6566,9 +6568,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                         if (!tnapi->tx_buffers)
                                 goto err_out;
 
-                        tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
-                                                              TG3_TX_RING_BYTES,
-                                                       &tnapi->tx_desc_mapping);
+                        tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
+                                                            TG3_TX_RING_BYTES,
+                                                        &tnapi->tx_desc_mapping,
+                                                            GFP_KERNEL);
                         if (!tnapi->tx_ring)
                                 goto err_out;
                 }
@@ -6601,9 +6604,10 @@ static int tg3_alloc_consistent(struct tg3 *tp)
                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
                         continue;
 
-                tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
-                                                     TG3_RX_RCB_RING_BYTES(tp),
-                                                     &tnapi->rx_rcb_mapping);
+                tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
+                                                   TG3_RX_RCB_RING_BYTES(tp),
+                                                   &tnapi->rx_rcb_mapping,
+                                                   GFP_KERNEL);
                 if (!tnapi->rx_rcb)
                         goto err_out;
 
@@ -6987,7 +6991,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
 
         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
-                        pcie_set_readrq(tp->pdev, 4096);
+                        pcie_set_readrq(tp->pdev, tp->pcie_readrq);
                 else {
                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
                                               tp->pci_cacheline_sz);
@@ -7181,7 +7185,7 @@ static int tg3_chip_reset(struct tg3 *tp)
                                       tp->pcie_cap + PCI_EXP_DEVCTL,
                                       val16);
 
-                pcie_set_readrq(tp->pdev, 4096);
+                pcie_set_readrq(tp->pdev, tp->pcie_readrq);
 
                 /* Clear error status */
                 pci_write_config_word(tp->pdev,
@@ -7222,19 +7226,21 @@ static int tg3_chip_reset(struct tg3 *tp)
                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
         }
 
+        if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+                tp->mac_mode = MAC_MODE_APE_TX_EN |
+                               MAC_MODE_APE_RX_EN |
+                               MAC_MODE_TDE_ENABLE;
+
         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
-                tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
-                tw32_f(MAC_MODE, tp->mac_mode);
+                tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
+                val = tp->mac_mode;
         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
-                tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
-                tw32_f(MAC_MODE, tp->mac_mode);
-        } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
-                tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
-                if (tp->mac_mode & MAC_MODE_APE_TX_EN)
-                        tp->mac_mode |= MAC_MODE_TDE_ENABLE;
-                tw32_f(MAC_MODE, tp->mac_mode);
+                tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
+                val = tp->mac_mode;
         } else
-                tw32_f(MAC_MODE, 0);
+                val = 0;
+
+        tw32_f(MAC_MODE, val);
         udelay(40);
 
         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
@@ -7801,6 +7807,37 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
                 tg3_abort_hw(tp, 1);
 
+        /* Enable MAC control of LPI */
+        if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
+                tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
+                       TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
+                       TG3_CPMU_EEE_LNKIDL_UART_IDL);
+
+                tw32_f(TG3_CPMU_EEE_CTRL,
+                       TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
+
+                val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
+                      TG3_CPMU_EEEMD_LPI_IN_TX |
+                      TG3_CPMU_EEEMD_LPI_IN_RX |
+                      TG3_CPMU_EEEMD_EEE_ENABLE;
+
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
+                        val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
+
+                if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
+                        val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
+
+                tw32_f(TG3_CPMU_EEE_MODE, val);
+
+                tw32_f(TG3_CPMU_EEE_DBTMR1,
+                       TG3_CPMU_DBTMR1_PCIEXIT_2047US |
+                       TG3_CPMU_DBTMR1_LNKIDLE_2047US);
+
+                tw32_f(TG3_CPMU_EEE_DBTMR2,
+                       TG3_CPMU_DBTMR1_APE_TX_2047US |
+                       TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
+        }
+
         if (reset_phy)
                 tg3_phy_reset(tp);
 
@@ -7860,18 +7897,21 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 tw32(GRC_MODE, grc_mode);
         }
 
-        if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
-                u32 grc_mode = tr32(GRC_MODE);
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
+                if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
+                        u32 grc_mode = tr32(GRC_MODE);
 
-                /* Access the lower 1K of PL PCIE block registers. */
-                val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
-                tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
+                        /* Access the lower 1K of PL PCIE block registers. */
+                        val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+                        tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
 
-                val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
-                tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
-                     val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
+                        val = tr32(TG3_PCIE_TLDLPL_PORT +
+                                   TG3_PCIE_PL_LO_PHYCTL5);
+                        tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
+                             val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
 
-                tw32(GRC_MODE, grc_mode);
+                        tw32(GRC_MODE, grc_mode);
+                }
 
                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
@@ -7879,22 +7919,6 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
         }
 
-        /* Enable MAC control of LPI */
-        if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
-                tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
-                       TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
-                       TG3_CPMU_EEE_LNKIDL_UART_IDL);
-
-                tw32_f(TG3_CPMU_EEE_CTRL,
-                       TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
-
-                tw32_f(TG3_CPMU_EEE_MODE,
-                       TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
-                       TG3_CPMU_EEEMD_LPI_IN_TX |
-                       TG3_CPMU_EEEMD_LPI_IN_RX |
-                       TG3_CPMU_EEEMD_EEE_ENABLE);
-        }
-
         /* This works around an issue with Athlon chipsets on
          * B3 tigon3 silicon.  This bit has no effect on any
          * other revision.  But do not set this on PCI Express
@@ -8162,8 +8186,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
                       RDMAC_MODE_LNGREAD_ENAB);
 
-        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
-            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
+        if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
 
         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
@@ -8203,6 +8226,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                        val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
+                        val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
+                }
                 tw32(TG3_RDMA_RSRVCTRL_REG,
                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
         }
@@ -8280,7 +8307,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
         }
 
         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
-                tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+                tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
         else
                 tp->mac_mode = 0;
         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
@@ -9031,8 +9058,14 @@ static bool tg3_enable_msix(struct tg3 *tp)
                 pci_disable_msix(tp->pdev);
                 return false;
         }
-        if (tp->irq_cnt > 1)
+
+        if (tp->irq_cnt > 1) {
                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                        tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
+                        netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
+                }
+        }
 
         return true;
 }
@@ -9101,7 +9134,7 @@ static int tg3_open(struct net_device *dev)
 
         netif_carrier_off(tp->dev);
 
-        err = tg3_set_power_state(tp, PCI_D0);
+        err = tg3_power_up(tp);
         if (err)
                 return err;
 
@@ -9266,7 +9299,7 @@ static int tg3_close(struct net_device *dev)
 
         tg3_free_consistent(tp);
 
-        tg3_set_power_state(tp, PCI_D3hot);
+        tg3_power_down(tp);
 
         netif_carrier_off(tp->dev);
 
@@ -11068,7 +11101,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
         struct tg3 *tp = netdev_priv(dev);
 
         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-                tg3_set_power_state(tp, PCI_D0);
+                tg3_power_up(tp);
 
         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
 
@@ -11136,7 +11169,7 @@ static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
                         tg3_phy_start(tp);
         }
         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
-                tg3_set_power_state(tp, PCI_D3hot);
+                tg3_power_down(tp);
 
 }
 
@@ -12411,8 +12444,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
                 if (cfg2 & (1 << 18))
                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
 
-                if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
-                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
+                if (((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) ||
+                    ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
+                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX))) &&
                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
 
@@ -12548,9 +12582,11 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
                 }
         }
 
-        if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
-            (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
-             tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
+        if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
+            ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
+              tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
+             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
+              tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
 
         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
@@ -12658,7 +12694,7 @@ static void __devinit tg3_read_vpd(struct tg3 *tp)
                         cnt = pci_read_vpd(tp->pdev, pos,
                                            TG3_NVM_VPD_LEN - pos,
                                            &vpd_data[pos]);
-                        if (cnt == -ETIMEDOUT || -EINTR)
+                        if (cnt == -ETIMEDOUT || cnt == -EINTR)
                                 cnt = 0;
                         else if (cnt < 0)
                                 goto out_not_found;
@@ -13047,17 +13083,15 @@ static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
                 return 512;
 }
 
+DEFINE_PCI_DEVICE_TABLE(write_reorder_chipsets) = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
+        { },
+};
+
 static int __devinit tg3_get_invariants(struct tg3 *tp)
 {
-        static struct pci_device_id write_reorder_chipsets[] = {
-                { PCI_DEVICE(PCI_VENDOR_ID_AMD,
-                             PCI_DEVICE_ID_AMD_FE_GATE_700C) },
-                { PCI_DEVICE(PCI_VENDOR_ID_AMD,
-                             PCI_DEVICE_ID_AMD_8131_BRIDGE) },
-                { PCI_DEVICE(PCI_VENDOR_ID_VIA,
-                             PCI_DEVICE_ID_VIA_8385_0) },
-                { },
-        };
         u32 misc_ctrl_reg;
         u32 pci_state_reg, grc_misc_cfg;
         u32 val;
@@ -13359,7 +13393,45 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
 
-                pcie_set_readrq(tp->pdev, 4096);
+                tp->pcie_readrq = 4096;
+                if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
+                        u16 word;
+
+                        pci_read_config_word(tp->pdev,
+                                             tp->pcie_cap + PCI_EXP_LNKSTA,
+                                             &word);
+                        switch (word & PCI_EXP_LNKSTA_CLS) {
+                        case PCI_EXP_LNKSTA_CLS_2_5GB:
+                                word &= PCI_EXP_LNKSTA_NLW;
+                                word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
+                                switch (word) {
+                                case 2:
+                                        tp->pcie_readrq = 2048;
+                                        break;
+                                case 4:
+                                        tp->pcie_readrq = 1024;
+                                        break;
+                                }
+                                break;
+
+                        case PCI_EXP_LNKSTA_CLS_5_0GB:
+                                word &= PCI_EXP_LNKSTA_NLW;
+                                word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
+                                switch (word) {
+                                case 1:
+                                        tp->pcie_readrq = 2048;
+                                        break;
+                                case 2:
+                                        tp->pcie_readrq = 1024;
+                                        break;
+                                case 4:
+                                        tp->pcie_readrq = 512;
+                                        break;
+                                }
+                        }
+                }
+
+                pcie_set_readrq(tp->pdev, tp->pcie_readrq);
 
                 pci_read_config_word(tp->pdev,
                                      tp->pcie_cap + PCI_EXP_LNKCTL,
@@ -13546,7 +13618,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
 
-        /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
+        /* Set up tp->grc_local_ctrl before calling tg_power_up().
          * GPIO1 driven high will bring 5700's external PHY out of reset.
          * It is also used as eeprom write protect on LOMs.
          */
@@ -13577,7 +13649,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
         }
 
         /* Force the chip into D0. */
-        err = tg3_set_power_state(tp, PCI_D0);
+        err = tg3_power_up(tp);
         if (err) {
                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
                 return err;
@@ -13722,8 +13794,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
 
         /* Preserve the APE MAC_MODE bits */
         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
-                tp->mac_mode = tr32(MAC_MODE) |
-                               MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+                tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
         else
                 tp->mac_mode = TG3_DEF_MAC_MODE;
 
@@ -14153,13 +14224,19 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
 
 #define TEST_BUFFER_SIZE        0x2000
 
+DEFINE_PCI_DEVICE_TABLE(dma_wait_state_chipsets) = {
+        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
+        { },
+};
+
 static int __devinit tg3_test_dma(struct tg3 *tp)
 {
         dma_addr_t buf_dma;
         u32 *buf, saved_dma_rwctrl;
         int ret = 0;
 
-        buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
+        buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
+                                 &buf_dma, GFP_KERNEL);
         if (!buf) {
                 ret = -ENOMEM;
                 goto out_nofree;
@@ -14321,11 +14398,6 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
         }
         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
             DMA_RWCTRL_WRITE_BNDRY_16) {
-                static struct pci_device_id dma_wait_state_chipsets[] = {
-                        { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
-                                     PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
-                        { },
-                };
 
                 /* DMA test passed without adjusting DMA boundary,
                  * now look for chipsets that are known to expose the
@@ -14343,7 +14415,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
         }
 
 out:
-        pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
+        dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
 out_nofree:
         return ret;
 }
@@ -14957,7 +15029,7 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
                 if (tp->fw)
                         release_firmware(tp->fw);
 
-                flush_scheduled_work();
+                cancel_work_sync(&tp->reset_task);
 
                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
                         tg3_phy_fini(tp);
@@ -14980,23 +15052,18 @@ static void __devexit tg3_remove_one(struct pci_dev *pdev)
         }
 }
 
-static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
+#ifdef CONFIG_PM_SLEEP
+static int tg3_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct net_device *dev = pci_get_drvdata(pdev);
         struct tg3 *tp = netdev_priv(dev);
-        pci_power_t target_state;
         int err;
 
-        /* PCI register 4 needs to be saved whether netif_running() or not.
-         * MSI address and data need to be saved if using MSI and
-         * netif_running().
-         */
-        pci_save_state(pdev);
-
         if (!netif_running(dev))
                 return 0;
 
-        flush_scheduled_work();
+        flush_work_sync(&tp->reset_task);
         tg3_phy_stop(tp);
         tg3_netif_stop(tp);
 
@@ -15013,9 +15080,7 @@ static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
         tg3_full_unlock(tp);
 
-        target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
-
-        err = tg3_set_power_state(tp, target_state);
+        err = tg3_power_down_prepare(tp);
         if (err) {
                 int err2;
 
@@ -15042,21 +15107,16 @@ out:
         return err;
 }
 
-static int tg3_resume(struct pci_dev *pdev)
+static int tg3_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct net_device *dev = pci_get_drvdata(pdev);
         struct tg3 *tp = netdev_priv(dev);
         int err;
 
-        pci_restore_state(tp->pdev);
-
         if (!netif_running(dev))
                 return 0;
 
-        err = tg3_set_power_state(tp, PCI_D0);
-        if (err)
-                return err;
-
         netif_device_attach(dev);
 
         tg3_full_lock(tp, 0);
@@ -15080,13 +15140,21 @@ out:
         return err;
 }
 
+static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
+#define TG3_PM_OPS (&tg3_pm_ops)
+
+#else
+
+#define TG3_PM_OPS NULL
+
+#endif /* CONFIG_PM_SLEEP */
+
 static struct pci_driver tg3_driver = {
         .name           = DRV_MODULE_NAME,
         .id_table       = tg3_pci_tbl,
         .probe          = tg3_init_one,
         .remove         = __devexit_p(tg3_remove_one),
-        .suspend        = tg3_suspend,
-        .resume         = tg3_resume
+        .driver.pm      = TG3_PM_OPS,
 };
 
 static int __init tg3_init(void)
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 4a1974804b9f..d62c8d937c82 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1094,13 +1094,19 @@
 /* 0x3664 --> 0x36b0 unused */
 
 #define TG3_CPMU_EEE_MODE               0x000036b0
-#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET   0x00000008
-#define TG3_CPMU_EEEMD_LPI_ENABLE        0x00000080
-#define TG3_CPMU_EEEMD_LPI_IN_TX         0x00000100
-#define TG3_CPMU_EEEMD_LPI_IN_RX         0x00000200
-#define TG3_CPMU_EEEMD_EEE_ENABLE        0x00100000
-/* 0x36b4 --> 0x36b8 unused */
-
+#define  TG3_CPMU_EEEMD_APE_TX_DET_EN    0x00000004
+#define  TG3_CPMU_EEEMD_ERLY_L1_XIT_DET  0x00000008
+#define  TG3_CPMU_EEEMD_SND_IDX_DET_EN   0x00000040
+#define  TG3_CPMU_EEEMD_LPI_ENABLE       0x00000080
+#define  TG3_CPMU_EEEMD_LPI_IN_TX        0x00000100
+#define  TG3_CPMU_EEEMD_LPI_IN_RX        0x00000200
+#define  TG3_CPMU_EEEMD_EEE_ENABLE       0x00100000
+#define TG3_CPMU_EEE_DBTMR1             0x000036b4
+#define  TG3_CPMU_DBTMR1_PCIEXIT_2047US  0x07ff0000
+#define  TG3_CPMU_DBTMR1_LNKIDLE_2047US  0x000070ff
+#define TG3_CPMU_EEE_DBTMR2             0x000036b8
+#define  TG3_CPMU_DBTMR1_APE_TX_2047US   0x07ff0000
+#define  TG3_CPMU_DBTMR2_TXIDXEQ_2047US  0x000070ff
 #define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
 #define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
 #define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004
@@ -1327,6 +1333,8 @@
 
 #define TG3_RDMA_RSRVCTRL_REG           0x00004900
 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX  0x00000004
+#define TG3_RDMA_RSRVCTRL_TXMRGN_320B    0x28000000
+#define TG3_RDMA_RSRVCTRL_TXMRGN_MASK    0xffe00000
 /* 0x4904 --> 0x4910 unused */
 
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
@@ -2170,9 +2178,6 @@
 #define MII_TG3_TEST1_CRC_EN            0x8000
 
 /* Clause 45 expansion registers */
-#define TG3_CL45_D7_EEEADV_CAP          0x003c
-#define TG3_CL45_D7_EEEADV_CAP_100TX    0x0002
-#define TG3_CL45_D7_EEEADV_CAP_1000T    0x0004
 #define TG3_CL45_D7_EEERES_STAT         0x803e
 #define TG3_CL45_D7_EEERES_STAT_LP_100TX        0x0002
 #define TG3_CL45_D7_EEERES_STAT_LP_1000T        0x0004
@@ -2562,10 +2567,6 @@ struct ring_info {
         DEFINE_DMA_UNMAP_ADDR(mapping);
 };
 
-struct tg3_config_info {
-        u32                             flags;
-};
-
 struct tg3_link_config {
         /* Describes what we're trying to get. */
         u32                             advertising;
@@ -2713,17 +2714,17 @@ struct tg3_napi {
         u32                             last_irq_tag;
         u32                             int_mbox;
         u32                             coal_now;
-        u32                             tx_prod;
-        u32                             tx_cons;
-        u32                             tx_pending;
-        u32                             prodmbox;
 
-        u32                             consmbox;
+        u32                             consmbox ____cacheline_aligned;
         u32                             rx_rcb_ptr;
         u16                             *rx_rcb_prod_idx;
         struct tg3_rx_prodring_set      prodring;
-
         struct tg3_rx_buffer_desc       *rx_rcb;
+
+        u32                             tx_prod ____cacheline_aligned;
+        u32                             tx_cons;
+        u32                             tx_pending;
+        u32                             prodmbox;
         struct tg3_tx_buffer_desc       *tx_ring;
         struct ring_info                *tx_buffers;
 
@@ -2946,6 +2947,7 @@ struct tg3 {
         int                             pcix_cap;
         int                             pcie_cap;
         };
+        int                             pcie_readrq;
 
         struct mii_bus                  *mdio_bus;
         int                             mdio_irq[PHY_MAX_ADDR];
diff --git a/drivers/net/tokenring/ibmtr.c b/drivers/net/tokenring/ibmtr.c
index 91e6c78271a3..4786497de03e 100644
--- a/drivers/net/tokenring/ibmtr.c
+++ b/drivers/net/tokenring/ibmtr.c
@@ -657,8 +657,9 @@ static int __devinit ibmtr_probe1(struct net_device *dev, int PIOaddr)
 #ifndef PCMCIA
         /* finish figuring the shared RAM address */
         if (cardpresent == TR_ISA) {
-                static __u32 ram_bndry_mask[] =
-                        { 0xffffe000, 0xffffc000, 0xffff8000, 0xffff0000 };
+                static const __u32 ram_bndry_mask[] = {
+                        0xffffe000, 0xffffc000, 0xffff8000, 0xffff0000
+                };
                 __u32 new_base, rrr_32, chk_base, rbm;
 
                 rrr_32=readb(ti->mmio+ACA_OFFSET+ACA_RW+RRR_ODD) >> 2 & 0x03;
diff --git a/drivers/net/tulip/de2104x.c b/drivers/net/tulip/de2104x.c
index c78a50586c1d..b13c6b040be3 100644
--- a/drivers/net/tulip/de2104x.c
+++ b/drivers/net/tulip/de2104x.c
@@ -964,7 +964,7 @@ static void de_set_media (struct de_private *de)
                 dw32(MacMode, macmode);
 }
 
-static void de_next_media (struct de_private *de, u32 *media,
+static void de_next_media (struct de_private *de, const u32 *media,
                            unsigned int n_media)
 {
         unsigned int i;
@@ -1008,10 +1008,10 @@ static void de21040_media_timer (unsigned long data)
                 return;
 
         if (de->media_type == DE_MEDIA_AUI) {
-                u32 next_state = DE_MEDIA_TP;
+                static const u32 next_state = DE_MEDIA_TP;
                 de_next_media(de, &next_state, 1);
         } else {
-                u32 next_state = DE_MEDIA_AUI;
+                static const u32 next_state = DE_MEDIA_AUI;
                 de_next_media(de, &next_state, 1);
         }
 
@@ -1136,13 +1136,19 @@ static void de21041_media_timer (unsigned long data)
          * simply resets the PHY and reloads the current media settings.
          */
         if (de->media_type == DE_MEDIA_AUI) {
-                u32 next_states[] = { DE_MEDIA_BNC, DE_MEDIA_TP_AUTO };
+                static const u32 next_states[] = {
+                        DE_MEDIA_BNC, DE_MEDIA_TP_AUTO
+                };
                 de_next_media(de, next_states, ARRAY_SIZE(next_states));
         } else if (de->media_type == DE_MEDIA_BNC) {
-                u32 next_states[] = { DE_MEDIA_TP_AUTO, DE_MEDIA_AUI };
+                static const u32 next_states[] = {
+                        DE_MEDIA_TP_AUTO, DE_MEDIA_AUI
+                };
                 de_next_media(de, next_states, ARRAY_SIZE(next_states));
         } else {
-                u32 next_states[] = { DE_MEDIA_AUI, DE_MEDIA_BNC, DE_MEDIA_TP_AUTO };
+                static const u32 next_states[] = {
+                        DE_MEDIA_AUI, DE_MEDIA_BNC, DE_MEDIA_TP_AUTO
+                };
                 de_next_media(de, next_states, ARRAY_SIZE(next_states));
         }
 
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c
index 2c39f2591216..5c01e260f1ba 100644
--- a/drivers/net/tulip/tulip_core.c
+++ b/drivers/net/tulip/tulip_core.c
@@ -1302,17 +1302,18 @@ static const struct net_device_ops tulip_netdev_ops = {
 #endif
 };
 
+DEFINE_PCI_DEVICE_TABLE(early_486_chipsets) = {
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
+        { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
+        { },
+};
+
 static int __devinit tulip_init_one (struct pci_dev *pdev,
                                      const struct pci_device_id *ent)
 {
         struct tulip_private *tp;
         /* See note below on the multiport cards. */
         static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
-        static struct pci_device_id early_486_chipsets[] = {
-                { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
-                { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
-                { },
-        };
         static int last_irq;
         static int multiport_cnt;       /* For four-port boards w/one EEPROM */
         int i, irq;
@@ -1682,7 +1683,9 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
                 tp->full_duplex_lock = 1;
 
         if (tulip_media_cap[tp->default_port] & MediaIsMII) {
-                u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
+                static const u16 media2advert[] = {
+                        0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
+                };
                 tp->mii_advertise = media2advert[tp->default_port - 9];
                 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
         }
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index e625f9530cf9..b100bd50a0d7 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -757,7 +757,7 @@ static __inline__ ssize_t tun_put_user(struct tun_struct *tun,
 
                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
                         gso.flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
-                        gso.csum_start = skb->csum_start - skb_headroom(skb);
+                        gso.csum_start = skb_checksum_start_offset(skb);
                         gso.csum_offset = skb->csum_offset;
                 } /* else everything is zero */
 
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c
index 5b83c3f35f47..a3c46f6a15e7 100644
--- a/drivers/net/typhoon.c
+++ b/drivers/net/typhoon.c
@@ -1004,7 +1004,6 @@ typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
         }
 
         strcpy(info->driver, KBUILD_MODNAME);
-        strcpy(info->version, UTS_RELEASE);
         strcpy(info->bus_info, pci_name(pci_dev));
 }
 
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index acbdab3d66ca..73a3e0d93237 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -28,6 +28,7 @@
 #include <linux/phy.h>
 #include <linux/workqueue.h>
 #include <linux/of_mdio.h>
+#include <linux/of_net.h>
 #include <linux/of_platform.h>
 
 #include <asm/uaccess.h>
diff --git a/drivers/net/usb/Kconfig b/drivers/net/usb/Kconfig
index 52ffabe6db0e..6f600cced6e1 100644
--- a/drivers/net/usb/Kconfig
+++ b/drivers/net/usb/Kconfig
@@ -196,6 +196,25 @@ config USB_NET_CDC_EEM
           IEEE 802 "local assignment" bit is set in the address, a "usbX"
           name is used instead.
 
+config USB_NET_CDC_NCM
+        tristate "CDC NCM support"
+        depends on USB_USBNET
+        default y
+        help
+          This driver provides support for CDC NCM (Network Control Model
+          Device USB Class Specification). The CDC NCM specification is
+          available from <http://www.usb.org/>.
+
+          Say "y" to link the driver statically, or "m" to build a
+          dynamically linked module.
+
+          This driver should work with at least the following devices:
+            * ST-Ericsson M700 LTE FDD/TDD Mobile Broadband Modem (ref. design)
+            * ST-Ericsson M5730 HSPA+ Mobile Broadband Modem (reference design)
+            * ST-Ericsson M570 HSPA+ Mobile Broadband Modem (reference design)
+            * ST-Ericsson M343 HSPA Mobile Broadband Modem (reference design)
+            * Ericsson F5521gw Mobile Broadband Module
+
 config USB_NET_DM9601
         tristate "Davicom DM9601 based USB 1.1 10/100 ethernet devices"
         depends on USB_USBNET
diff --git a/drivers/net/usb/Makefile b/drivers/net/usb/Makefile
index a19b0259ae16..cac170301187 100644
--- a/drivers/net/usb/Makefile
+++ b/drivers/net/usb/Makefile
@@ -26,4 +26,5 @@ obj-$(CONFIG_USB_CDC_PHONET)	+= cdc-phonet.o
 obj-$(CONFIG_USB_IPHETH)        += ipheth.o
 obj-$(CONFIG_USB_SIERRA_NET)    += sierra_net.o
 obj-$(CONFIG_USB_NET_CX82310_ETH)       += cx82310_eth.o
+obj-$(CONFIG_USB_NET_CDC_NCM)   += cdc_ncm.o
 
diff --git a/drivers/net/usb/asix.c b/drivers/net/usb/asix.c
index aea4645be7f6..6140b56cce53 100644
--- a/drivers/net/usb/asix.c
+++ b/drivers/net/usb/asix.c
@@ -1508,6 +1508,10 @@ static const struct usb_device_id	products [] = {
         USB_DEVICE (0x0b95, 0x1780),
         .driver_info = (unsigned long) &ax88178_info,
 }, {
+        // Logitec LAN-GTJ/U2A
+        USB_DEVICE (0x0789, 0x0160),
+        .driver_info = (unsigned long) &ax88178_info,
+}, {
         // Linksys USB200M Rev 2
         USB_DEVICE (0x13b1, 0x0018),
         .driver_info = (unsigned long) &ax88772_info,
diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c
index b3fe0de40469..9a60e415d76b 100644
--- a/drivers/net/usb/cdc_ether.c
+++ b/drivers/net/usb/cdc_ether.c
@@ -99,9 +99,7 @@ int usbnet_generic_cdc_bind(struct usbnet *dev, struct usb_interface *intf)
                  */
                 buf = dev->udev->actconfig->extra;
                 len = dev->udev->actconfig->extralen;
-                if (len)
-                        dev_dbg(&intf->dev,
-                                "CDC descriptors on config\n");
+                dev_dbg(&intf->dev, "CDC descriptors on config\n");
         }
 
         /* Maybe CDC descriptors are after the endpoint?  This bug has
diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c
new file mode 100644
index 000000000000..593c104ab199
--- /dev/null
+++ b/drivers/net/usb/cdc_ncm.c
@@ -0,0 +1,1213 @@
+/*
+ * cdc_ncm.c
+ *
+ * Copyright (C) ST-Ericsson 2010
+ * Contact: Alexey Orishko <alexey.orishko@stericsson.com>
+ * Original author: Hans Petter Selasky <hans.petter.selasky@stericsson.com>
+ *
+ * USB Host Driver for Network Control Model (NCM)
+ * http://www.usb.org/developers/devclass_docs/NCM10.zip
+ *
+ * The NCM encoding, decoding and initialization logic
+ * derives from FreeBSD 8.x. if_cdce.c and if_cdcereg.h
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose this file to be licensed under the terms
+ * of the GNU General Public License (GPL) Version 2 or the 2-clause
+ * BSD license listed below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/ctype.h>
+#include <linux/ethtool.h>
+#include <linux/workqueue.h>
+#include <linux/mii.h>
+#include <linux/crc32.h>
+#include <linux/usb.h>
+#include <linux/version.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/atomic.h>
+#include <linux/usb/usbnet.h>
+#include <linux/usb/cdc.h>
+
+#define DRIVER_VERSION                          "30-Nov-2010"
+
+/* CDC NCM subclass 3.2.1 */
+#define USB_CDC_NCM_NDP16_LENGTH_MIN            0x10
+
+/* Maximum NTB length */
+#define CDC_NCM_NTB_MAX_SIZE_TX                 16384   /* bytes */
+#define CDC_NCM_NTB_MAX_SIZE_RX                 16384   /* bytes */
+
+/* Minimum value for MaxDatagramSize, ch. 6.2.9 */
+#define CDC_NCM_MIN_DATAGRAM_SIZE               1514    /* bytes */
+
+#define CDC_NCM_MIN_TX_PKT                      512     /* bytes */
+
+/* Default value for MaxDatagramSize */
+#define CDC_NCM_MAX_DATAGRAM_SIZE               2048    /* bytes */
+
+/*
+ * Maximum amount of datagrams in NCM Datagram Pointer Table, not counting
+ * the last NULL entry. Any additional datagrams in NTB would be discarded.
+ */
+#define CDC_NCM_DPT_DATAGRAMS_MAX               32
+
+/* Restart the timer, if amount of datagrams is less than given value */
+#define CDC_NCM_RESTART_TIMER_DATAGRAM_CNT      3
+
+/* The following macro defines the minimum header space */
+#define CDC_NCM_MIN_HDR_SIZE \
+        (sizeof(struct usb_cdc_ncm_nth16) + sizeof(struct usb_cdc_ncm_ndp16) + \
+        (CDC_NCM_DPT_DATAGRAMS_MAX + 1) * sizeof(struct usb_cdc_ncm_dpe16))
+
+struct connection_speed_change {
+        __le32  USBitRate; /* holds 3GPP downlink value, bits per second */
+        __le32  DSBitRate; /* holds 3GPP uplink value, bits per second */
+} __attribute__ ((packed));
+
+struct cdc_ncm_data {
+        struct usb_cdc_ncm_nth16 nth16;
+        struct usb_cdc_ncm_ndp16 ndp16;
+        struct usb_cdc_ncm_dpe16 dpe16[CDC_NCM_DPT_DATAGRAMS_MAX + 1];
+};
+
+struct cdc_ncm_ctx {
+        struct cdc_ncm_data rx_ncm;
+        struct cdc_ncm_data tx_ncm;
+        struct usb_cdc_ncm_ntb_parameters ncm_parm;
+        struct timer_list tx_timer;
+
+        const struct usb_cdc_ncm_desc *func_desc;
+        const struct usb_cdc_header_desc *header_desc;
+        const struct usb_cdc_union_desc *union_desc;
+        const struct usb_cdc_ether_desc *ether_desc;
+
+        struct net_device *netdev;
+        struct usb_device *udev;
+        struct usb_host_endpoint *in_ep;
+        struct usb_host_endpoint *out_ep;
+        struct usb_host_endpoint *status_ep;
+        struct usb_interface *intf;
+        struct usb_interface *control;
+        struct usb_interface *data;
+
+        struct sk_buff *tx_curr_skb;
+        struct sk_buff *tx_rem_skb;
+
+        spinlock_t mtx;
+
+        u32 tx_timer_pending;
+        u32 tx_curr_offset;
+        u32 tx_curr_last_offset;
+        u32 tx_curr_frame_num;
+        u32 rx_speed;
+        u32 tx_speed;
+        u32 rx_max;
+        u32 tx_max;
+        u32 max_datagram_size;
+        u16 tx_max_datagrams;
+        u16 tx_remainder;
+        u16 tx_modulus;
+        u16 tx_ndp_modulus;
+        u16 tx_seq;
+        u16 connected;
+        u8 data_claimed;
+        u8 control_claimed;
+};
+
+static void cdc_ncm_tx_timeout(unsigned long arg);
+static const struct driver_info cdc_ncm_info;
+static struct usb_driver cdc_ncm_driver;
+static struct ethtool_ops cdc_ncm_ethtool_ops;
+
+static const struct usb_device_id cdc_devs[] = {
+        { USB_INTERFACE_INFO(USB_CLASS_COMM,
+                USB_CDC_SUBCLASS_NCM, USB_CDC_PROTO_NONE),
+                .driver_info = (unsigned long)&cdc_ncm_info,
+        },
+        {
+        },
+};
+
+MODULE_DEVICE_TABLE(usb, cdc_devs);
+
+static void
+cdc_ncm_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info)
+{
+        struct usbnet *dev = netdev_priv(net);
+
+        strncpy(info->driver, dev->driver_name, sizeof(info->driver));
+        strncpy(info->version, DRIVER_VERSION, sizeof(info->version));
+        strncpy(info->fw_version, dev->driver_info->description,
+                sizeof(info->fw_version));
+        usb_make_path(dev->udev, info->bus_info, sizeof(info->bus_info));
+}
+
+static int
+cdc_ncm_do_request(struct cdc_ncm_ctx *ctx, struct usb_cdc_notification *req,
+                   void *data, u16 flags, u16 *actlen, u16 timeout)
+{
+        int err;
+
+        err = usb_control_msg(ctx->udev, (req->bmRequestType & USB_DIR_IN) ?
+                                usb_rcvctrlpipe(ctx->udev, 0) :
+                                usb_sndctrlpipe(ctx->udev, 0),
+                                req->bNotificationType, req->bmRequestType,
+                                req->wValue,
+                                req->wIndex, data,
+                                req->wLength, timeout);
+
+        if (err < 0) {
+                if (actlen)
+                        *actlen = 0;
+                return err;
+        }
+
+        if (actlen)
+                *actlen = err;
+
+        return 0;
+}
+
+static u8 cdc_ncm_setup(struct cdc_ncm_ctx *ctx)
+{
+        struct usb_cdc_notification req;
+        u32 val;
+        __le16 max_datagram_size;
+        u8 flags;
+        u8 iface_no;
+        int err;
+
+        iface_no = ctx->control->cur_altsetting->desc.bInterfaceNumber;
+
+        req.bmRequestType = USB_TYPE_CLASS | USB_DIR_IN | USB_RECIP_INTERFACE;
+        req.bNotificationType = USB_CDC_GET_NTB_PARAMETERS;
+        req.wValue = 0;
+        req.wIndex = cpu_to_le16(iface_no);
+        req.wLength = cpu_to_le16(sizeof(ctx->ncm_parm));
+
+        err = cdc_ncm_do_request(ctx, &req, &ctx->ncm_parm, 0, NULL, 1000);
+        if (err) {
+                pr_debug("failed GET_NTB_PARAMETERS\n");
+                return 1;
+        }
+
+        /* read correct set of parameters according to device mode */
+        ctx->rx_max = le32_to_cpu(ctx->ncm_parm.dwNtbInMaxSize);
+        ctx->tx_max = le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize);
+        ctx->tx_remainder = le16_to_cpu(ctx->ncm_parm.wNdpOutPayloadRemainder);
+        ctx->tx_modulus = le16_to_cpu(ctx->ncm_parm.wNdpOutDivisor);
+        ctx->tx_ndp_modulus = le16_to_cpu(ctx->ncm_parm.wNdpOutAlignment);
+
+        if (ctx->func_desc != NULL)
+                flags = ctx->func_desc->bmNetworkCapabilities;
+        else
+                flags = 0;
+
+        pr_debug("dwNtbInMaxSize=%u dwNtbOutMaxSize=%u "
+                 "wNdpOutPayloadRemainder=%u wNdpOutDivisor=%u "
+                 "wNdpOutAlignment=%u flags=0x%x\n",
+                 ctx->rx_max, ctx->tx_max, ctx->tx_remainder, ctx->tx_modulus,
+                 ctx->tx_ndp_modulus, flags);
+
+        /* max count of tx datagrams without terminating NULL entry */
+        ctx->tx_max_datagrams = CDC_NCM_DPT_DATAGRAMS_MAX;
+
+        /* verify maximum size of received NTB in bytes */
+        if ((ctx->rx_max <
+            (CDC_NCM_MIN_HDR_SIZE + CDC_NCM_MIN_DATAGRAM_SIZE)) ||
+            (ctx->rx_max > CDC_NCM_NTB_MAX_SIZE_RX)) {
+                pr_debug("Using default maximum receive length=%d\n",
+                                                CDC_NCM_NTB_MAX_SIZE_RX);
+                ctx->rx_max = CDC_NCM_NTB_MAX_SIZE_RX;
+        }
+
+        /* verify maximum size of transmitted NTB in bytes */
+        if ((ctx->tx_max <
+            (CDC_NCM_MIN_HDR_SIZE + CDC_NCM_MIN_DATAGRAM_SIZE)) ||
+            (ctx->tx_max > CDC_NCM_NTB_MAX_SIZE_TX)) {
+                pr_debug("Using default maximum transmit length=%d\n",
+                                                CDC_NCM_NTB_MAX_SIZE_TX);
+                ctx->tx_max = CDC_NCM_NTB_MAX_SIZE_TX;
+        }
+
+        /*
+         * verify that the structure alignment is:
+         * - power of two
+         * - not greater than the maximum transmit length
+         * - not less than four bytes
+         */
+        val = ctx->tx_ndp_modulus;
+
+        if ((val < USB_CDC_NCM_NDP_ALIGN_MIN_SIZE) ||
+            (val != ((-val) & val)) || (val >= ctx->tx_max)) {
+                pr_debug("Using default alignment: 4 bytes\n");
+                ctx->tx_ndp_modulus = USB_CDC_NCM_NDP_ALIGN_MIN_SIZE;
+        }
+
+        /*
+         * verify that the payload alignment is:
+         * - power of two
+         * - not greater than the maximum transmit length
+         * - not less than four bytes
+         */
+        val = ctx->tx_modulus;
+
+        if ((val < USB_CDC_NCM_NDP_ALIGN_MIN_SIZE) ||
+            (val != ((-val) & val)) || (val >= ctx->tx_max)) {
+                pr_debug("Using default transmit modulus: 4 bytes\n");
+                ctx->tx_modulus = USB_CDC_NCM_NDP_ALIGN_MIN_SIZE;
+        }
+
+        /* verify the payload remainder */
+        if (ctx->tx_remainder >= ctx->tx_modulus) {
+                pr_debug("Using default transmit remainder: 0 bytes\n");
+                ctx->tx_remainder = 0;
+        }
+
+        /* adjust TX-remainder according to NCM specification. */
+        ctx->tx_remainder = ((ctx->tx_remainder - ETH_HLEN) &
+                                                (ctx->tx_modulus - 1));
+
+        /* additional configuration */
+
+        /* set CRC Mode */
+        req.bmRequestType = USB_TYPE_CLASS | USB_DIR_OUT | USB_RECIP_INTERFACE;
+        req.bNotificationType = USB_CDC_SET_CRC_MODE;
+        req.wValue = cpu_to_le16(USB_CDC_NCM_CRC_NOT_APPENDED);
+        req.wIndex = cpu_to_le16(iface_no);
+        req.wLength = 0;
+
+        err = cdc_ncm_do_request(ctx, &req, NULL, 0, NULL, 1000);
+        if (err)
+                pr_debug("Setting CRC mode off failed\n");
+
+        /* set NTB format */
+        req.bmRequestType = USB_TYPE_CLASS | USB_DIR_OUT | USB_RECIP_INTERFACE;
+        req.bNotificationType = USB_CDC_SET_NTB_FORMAT;
+        req.wValue = cpu_to_le16(USB_CDC_NCM_NTB16_FORMAT);
+        req.wIndex = cpu_to_le16(iface_no);
+        req.wLength = 0;
+
+        err = cdc_ncm_do_request(ctx, &req, NULL, 0, NULL, 1000);
+        if (err)
+                pr_debug("Setting NTB format to 16-bit failed\n");
+
+        /* set Max Datagram Size (MTU) */
+        req.bmRequestType = USB_TYPE_CLASS | USB_DIR_IN | USB_RECIP_INTERFACE;
+        req.bNotificationType = USB_CDC_GET_MAX_DATAGRAM_SIZE;
+        req.wValue = 0;
+        req.wIndex = cpu_to_le16(iface_no);
+        req.wLength = cpu_to_le16(2);
+
+        err = cdc_ncm_do_request(ctx, &req, &max_datagram_size, 0, NULL, 1000);
+        if (err) {
+                pr_debug(" GET_MAX_DATAGRAM_SIZE failed, using size=%u\n",
+                         CDC_NCM_MIN_DATAGRAM_SIZE);
+                /* use default */
+                ctx->max_datagram_size = CDC_NCM_MIN_DATAGRAM_SIZE;
+        } else {
+                ctx->max_datagram_size = le16_to_cpu(max_datagram_size);
+
+                if (ctx->max_datagram_size < CDC_NCM_MIN_DATAGRAM_SIZE)
+                        ctx->max_datagram_size = CDC_NCM_MIN_DATAGRAM_SIZE;
+                else if (ctx->max_datagram_size > CDC_NCM_MAX_DATAGRAM_SIZE)
+                        ctx->max_datagram_size = CDC_NCM_MAX_DATAGRAM_SIZE;
+        }
+
+        if (ctx->netdev->mtu != (ctx->max_datagram_size - ETH_HLEN))
+                ctx->netdev->mtu = ctx->max_datagram_size - ETH_HLEN;
+
+        return 0;
+}
+
+static void
+cdc_ncm_find_endpoints(struct cdc_ncm_ctx *ctx, struct usb_interface *intf)
+{
+        struct usb_host_endpoint *e;
+        u8 ep;
+
+        for (ep = 0; ep < intf->cur_altsetting->desc.bNumEndpoints; ep++) {
+
+                e = intf->cur_altsetting->endpoint + ep;
+                switch (e->desc.bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
+                case USB_ENDPOINT_XFER_INT:
+                        if (usb_endpoint_dir_in(&e->desc)) {
+                                if (ctx->status_ep == NULL)
+                                        ctx->status_ep = e;
+                        }
+                        break;
+
+                case USB_ENDPOINT_XFER_BULK:
+                        if (usb_endpoint_dir_in(&e->desc)) {
+                                if (ctx->in_ep == NULL)
+                                        ctx->in_ep = e;
+                        } else {
+                                if (ctx->out_ep == NULL)
+                                        ctx->out_ep = e;
+                        }
+                        break;
+
+                default:
+                        break;
+                }
+        }
+}
+
+static void cdc_ncm_free(struct cdc_ncm_ctx *ctx)
+{
+        if (ctx == NULL)
+                return;
+
+        del_timer_sync(&ctx->tx_timer);
+
+        if (ctx->data_claimed) {
+                usb_set_intfdata(ctx->data, NULL);
+                usb_driver_release_interface(driver_of(ctx->intf), ctx->data);
+        }
+
+        if (ctx->control_claimed) {
+                usb_set_intfdata(ctx->control, NULL);
+                usb_driver_release_interface(driver_of(ctx->intf),
+                                                                ctx->control);
+        }
+
+        if (ctx->tx_rem_skb != NULL) {
+                dev_kfree_skb_any(ctx->tx_rem_skb);
+                ctx->tx_rem_skb = NULL;
+        }
+
+        if (ctx->tx_curr_skb != NULL) {
+                dev_kfree_skb_any(ctx->tx_curr_skb);
+                ctx->tx_curr_skb = NULL;
+        }
+
+        kfree(ctx);
+}
+
+static int cdc_ncm_bind(struct usbnet *dev, struct usb_interface *intf)
+{
+        struct cdc_ncm_ctx *ctx;
+        struct usb_driver *driver;
+        u8 *buf;
+        int len;
+        int temp;
+        u8 iface_no;
+
+        ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
+        if (ctx == NULL)
+                goto error;
+
+        memset(ctx, 0, sizeof(*ctx));
+
+        init_timer(&ctx->tx_timer);
+        spin_lock_init(&ctx->mtx);
+        ctx->netdev = dev->net;
+
+        /* store ctx pointer in device data field */
+        dev->data[0] = (unsigned long)ctx;
+
+        /* get some pointers */
+        driver = driver_of(intf);
+        buf = intf->cur_altsetting->extra;
+        len = intf->cur_altsetting->extralen;
+
+        ctx->udev = dev->udev;
+        ctx->intf = intf;
+
+        /* parse through descriptors associated with control interface */
+        while ((len > 0) && (buf[0] > 2) && (buf[0] <= len)) {
+
+                if (buf[1] != USB_DT_CS_INTERFACE)
+                        goto advance;
+
+                switch (buf[2]) {
+                case USB_CDC_UNION_TYPE:
+                        if (buf[0] < sizeof(*(ctx->union_desc)))
+                                break;
+
+                        ctx->union_desc =
+                                        (const struct usb_cdc_union_desc *)buf;
+
+                        ctx->control = usb_ifnum_to_if(dev->udev,
+                                        ctx->union_desc->bMasterInterface0);
+                        ctx->data = usb_ifnum_to_if(dev->udev,
+                                        ctx->union_desc->bSlaveInterface0);
+                        break;
+
+                case USB_CDC_ETHERNET_TYPE:
+                        if (buf[0] < sizeof(*(ctx->ether_desc)))
+                                break;
+
+                        ctx->ether_desc =
+                                        (const struct usb_cdc_ether_desc *)buf;
+
+                        dev->hard_mtu =
+                                le16_to_cpu(ctx->ether_desc->wMaxSegmentSize);
+
+                        if (dev->hard_mtu <
+                            (CDC_NCM_MIN_DATAGRAM_SIZE - ETH_HLEN))
+                                dev->hard_mtu =
+                                        CDC_NCM_MIN_DATAGRAM_SIZE - ETH_HLEN;
+
+                        else if (dev->hard_mtu >
+                                 (CDC_NCM_MAX_DATAGRAM_SIZE - ETH_HLEN))
+                                dev->hard_mtu =
+                                        CDC_NCM_MAX_DATAGRAM_SIZE - ETH_HLEN;
+                        break;
+
+                case USB_CDC_NCM_TYPE:
+                        if (buf[0] < sizeof(*(ctx->func_desc)))
+                                break;
+
+                        ctx->func_desc = (const struct usb_cdc_ncm_desc *)buf;
+                        break;
+
+                default:
+                        break;
+                }
+advance:
+                /* advance to next descriptor */
+                temp = buf[0];
+                buf += temp;
+                len -= temp;
+        }
+
+        /* check if we got everything */
+        if ((ctx->control == NULL) || (ctx->data == NULL) ||
+            (ctx->ether_desc == NULL))
+                goto error;
+
+        /* claim interfaces, if any */
+        if (ctx->data != intf) {
+                temp = usb_driver_claim_interface(driver, ctx->data, dev);
+                if (temp)
+                        goto error;
+                ctx->data_claimed = 1;
+        }
+
+        if (ctx->control != intf) {
+                temp = usb_driver_claim_interface(driver, ctx->control, dev);
+                if (temp)
+                        goto error;
+                ctx->control_claimed = 1;
+        }
+
+        iface_no = ctx->data->cur_altsetting->desc.bInterfaceNumber;
+
+        /* reset data interface */
+        temp = usb_set_interface(dev->udev, iface_no, 0);
+        if (temp)
+                goto error;
+
+        /* initialize data interface */
+        if (cdc_ncm_setup(ctx))
+                goto error;
+
+        /* configure data interface */
+        temp = usb_set_interface(dev->udev, iface_no, 1);
+        if (temp)
+                goto error;
+
+        cdc_ncm_find_endpoints(ctx, ctx->data);
+        cdc_ncm_find_endpoints(ctx, ctx->control);
+
+        if ((ctx->in_ep == NULL) || (ctx->out_ep == NULL) ||
+            (ctx->status_ep == NULL))
+                goto error;
+
+        dev->net->ethtool_ops = &cdc_ncm_ethtool_ops;
+
+        usb_set_intfdata(ctx->data, dev);
+        usb_set_intfdata(ctx->control, dev);
+        usb_set_intfdata(ctx->intf, dev);
+
+        temp = usbnet_get_ethernet_addr(dev, ctx->ether_desc->iMACAddress);
+        if (temp)
+                goto error;
+
+        dev_info(&dev->udev->dev, "MAC-Address: "
+                                "0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n",
+                                dev->net->dev_addr[0], dev->net->dev_addr[1],
+                                dev->net->dev_addr[2], dev->net->dev_addr[3],
+                                dev->net->dev_addr[4], dev->net->dev_addr[5]);
+
+        dev->in = usb_rcvbulkpipe(dev->udev,
+                ctx->in_ep->desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
+        dev->out = usb_sndbulkpipe(dev->udev,
+                ctx->out_ep->desc.bEndpointAddress & USB_ENDPOINT_NUMBER_MASK);
+        dev->status = ctx->status_ep;
+        dev->rx_urb_size = ctx->rx_max;
+
+        /*
+         * We should get an event when network connection is "connected" or
+         * "disconnected". Set network connection in "disconnected" state
+         * (carrier is OFF) during attach, so the IP network stack does not
+         * start IPv6 negotiation and more.
+         */
+        netif_carrier_off(dev->net);
+        ctx->tx_speed = ctx->rx_speed = 0;
+        return 0;
+
+error:
+        cdc_ncm_free((struct cdc_ncm_ctx *)dev->data[0]);
+        dev->data[0] = 0;
+        dev_info(&dev->udev->dev, "Descriptor failure\n");
+        return -ENODEV;
+}
+
+static void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf)
+{
+        struct cdc_ncm_ctx *ctx = (struct cdc_ncm_ctx *)dev->data[0];
+        struct usb_driver *driver;
+
+        if (ctx == NULL)
+                return;         /* no setup */
+
+        driver = driver_of(intf);
+
+        usb_set_intfdata(ctx->data, NULL);
+        usb_set_intfdata(ctx->control, NULL);
+        usb_set_intfdata(ctx->intf, NULL);
+
+        /* release interfaces, if any */
+        if (ctx->data_claimed) {
+                usb_driver_release_interface(driver, ctx->data);
+                ctx->data_claimed = 0;
+        }
+
+        if (ctx->control_claimed) {
+                usb_driver_release_interface(driver, ctx->control);
+                ctx->control_claimed = 0;
+        }
+
+        cdc_ncm_free(ctx);
+}
+
+static void cdc_ncm_zero_fill(u8 *ptr, u32 first, u32 end, u32 max)
+{
+        if (first >= max)
+                return;
+        if (first >= end)
+                return;
+        if (end > max)
+                end = max;
+        memset(ptr + first, 0, end - first);
+}
+
+static struct sk_buff *
+cdc_ncm_fill_tx_frame(struct cdc_ncm_ctx *ctx, struct sk_buff *skb)
+{
+        struct sk_buff *skb_out;
+        u32 rem;
+        u32 offset;
+        u32 last_offset;
+        u16 n = 0;
+        u8 timeout = 0;
+
+        /* if there is a remaining skb, it gets priority */
+        if (skb != NULL)
+                swap(skb, ctx->tx_rem_skb);
+        else
+                timeout = 1;
+
+        /*
+         * +----------------+
+         * | skb_out        |
+         * +----------------+
+         *           ^ offset
+         *        ^ last_offset
+         */
+
+        /* check if we are resuming an OUT skb */
+        if (ctx->tx_curr_skb != NULL) {
+                /* pop variables */
+                skb_out = ctx->tx_curr_skb;
+                offset = ctx->tx_curr_offset;
+                last_offset = ctx->tx_curr_last_offset;
+                n = ctx->tx_curr_frame_num;
+
+        } else {
+                /* reset variables */
+                skb_out = alloc_skb(ctx->tx_max, GFP_ATOMIC);
+                if (skb_out == NULL) {
+                        if (skb != NULL) {
+                                dev_kfree_skb_any(skb);
+                                ctx->netdev->stats.tx_dropped++;
+                        }
+                        goto exit_no_skb;
+                }
+
+                /* make room for NTH and NDP */
+                offset = ALIGN(sizeof(struct usb_cdc_ncm_nth16),
+                                        ctx->tx_ndp_modulus) +
+                                        sizeof(struct usb_cdc_ncm_ndp16) +
+                                        (ctx->tx_max_datagrams + 1) *
+                                        sizeof(struct usb_cdc_ncm_dpe16);
+
+                /* store last valid offset before alignment */
+                last_offset = offset;
+                /* align first Datagram offset correctly */
+                offset = ALIGN(offset, ctx->tx_modulus) + ctx->tx_remainder;
+                /* zero buffer till the first IP datagram */
+                cdc_ncm_zero_fill(skb_out->data, 0, offset, offset);
+                n = 0;
+                ctx->tx_curr_frame_num = 0;
+        }
+
+        for (; n < ctx->tx_max_datagrams; n++) {
+                /* check if end of transmit buffer is reached */
+                if (offset >= ctx->tx_max)
+                        break;
+
+                /* compute maximum buffer size */
+                rem = ctx->tx_max - offset;
+
+                if (skb == NULL) {
+                        skb = ctx->tx_rem_skb;
+                        ctx->tx_rem_skb = NULL;
+
+                        /* check for end of skb */
+                        if (skb == NULL)
+                                break;
+                }
+
+                if (skb->len > rem) {
+                        if (n == 0) {
+                                /* won't fit, MTU problem? */
+                                dev_kfree_skb_any(skb);
+                                skb = NULL;
+                                ctx->netdev->stats.tx_dropped++;
+                        } else {
+                                /* no room for skb - store for later */
+                                if (ctx->tx_rem_skb != NULL) {
+                                        dev_kfree_skb_any(ctx->tx_rem_skb);
+                                        ctx->netdev->stats.tx_dropped++;
+                                }
+                                ctx->tx_rem_skb = skb;
+                                skb = NULL;
+
+                                /* loop one more time */
+                                timeout = 1;
+                        }
+                        break;
+                }
+
+                memcpy(((u8 *)skb_out->data) + offset, skb->data, skb->len);
+
+                ctx->tx_ncm.dpe16[n].wDatagramLength = cpu_to_le16(skb->len);
+                ctx->tx_ncm.dpe16[n].wDatagramIndex = cpu_to_le16(offset);
+
+                /* update offset */
+                offset += skb->len;
+
+                /* store last valid offset before alignment */
+                last_offset = offset;
+
+                /* align offset correctly */
+                offset = ALIGN(offset, ctx->tx_modulus) + ctx->tx_remainder;
+
+                /* zero padding */
+                cdc_ncm_zero_fill(skb_out->data, last_offset, offset,
+                                                                ctx->tx_max);
+                dev_kfree_skb_any(skb);
+                skb = NULL;
+        }
+
+        /* free up any dangling skb */
+        if (skb != NULL) {
+                dev_kfree_skb_any(skb);
+                skb = NULL;
+                ctx->netdev->stats.tx_dropped++;
+        }
+
+        ctx->tx_curr_frame_num = n;
+
+        if (n == 0) {
+                /* wait for more frames */
+                /* push variables */
+                ctx->tx_curr_skb = skb_out;
+                ctx->tx_curr_offset = offset;
+                ctx->tx_curr_last_offset = last_offset;
+                goto exit_no_skb;
+
+        } else if ((n < ctx->tx_max_datagrams) && (timeout == 0)) {
+                /* wait for more frames */
+                /* push variables */
+                ctx->tx_curr_skb = skb_out;
+                ctx->tx_curr_offset = offset;
+                ctx->tx_curr_last_offset = last_offset;
+                /* set the pending count */
+                if (n < CDC_NCM_RESTART_TIMER_DATAGRAM_CNT)
+                        ctx->tx_timer_pending = 2;
+                goto exit_no_skb;
+
+        } else {
+                /* frame goes out */
+                /* variables will be reset at next call */
+        }
+
+        /* check for overflow */
+        if (last_offset > ctx->tx_max)
+                last_offset = ctx->tx_max;
+
+        /* revert offset */
+        offset = last_offset;
+
+        /*
+         * If collected data size is less or equal CDC_NCM_MIN_TX_PKT bytes,
+         * we send buffers as it is. If we get more data, it would be more
+         * efficient for USB HS mobile device with DMA engine to receive a full
+         * size NTB, than canceling DMA transfer and receiving a short packet.
+         */
+        if (offset > CDC_NCM_MIN_TX_PKT)
+                offset = ctx->tx_max;
+
+        /* final zero padding */
+        cdc_ncm_zero_fill(skb_out->data, last_offset, offset, ctx->tx_max);
+
+        /* store last offset */
+        last_offset = offset;
+
+        if ((last_offset < ctx->tx_max) && ((last_offset %
+                        le16_to_cpu(ctx->out_ep->desc.wMaxPacketSize)) == 0)) {
+                /* force short packet */
+                *(((u8 *)skb_out->data) + last_offset) = 0;
+                last_offset++;
+        }
+
+        /* zero the rest of the DPEs plus the last NULL entry */
+        for (; n <= CDC_NCM_DPT_DATAGRAMS_MAX; n++) {
+                ctx->tx_ncm.dpe16[n].wDatagramLength = 0;
+                ctx->tx_ncm.dpe16[n].wDatagramIndex = 0;
+        }
+
+        /* fill out 16-bit NTB header */
+        ctx->tx_ncm.nth16.dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN);
+        ctx->tx_ncm.nth16.wHeaderLength =
+                                        cpu_to_le16(sizeof(ctx->tx_ncm.nth16));
+        ctx->tx_ncm.nth16.wSequence = cpu_to_le16(ctx->tx_seq);
+        ctx->tx_ncm.nth16.wBlockLength = cpu_to_le16(last_offset);
+        ctx->tx_ncm.nth16.wFpIndex = ALIGN(sizeof(struct usb_cdc_ncm_nth16),
+                                                        ctx->tx_ndp_modulus);
+
+        memcpy(skb_out->data, &(ctx->tx_ncm.nth16), sizeof(ctx->tx_ncm.nth16));
+        ctx->tx_seq++;
+
+        /* fill out 16-bit NDP table */
+        ctx->tx_ncm.ndp16.dwSignature =
+                                cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN);
+        rem = sizeof(ctx->tx_ncm.ndp16) + ((ctx->tx_curr_frame_num + 1) *
+                                        sizeof(struct usb_cdc_ncm_dpe16));
+        ctx->tx_ncm.ndp16.wLength = cpu_to_le16(rem);
+        ctx->tx_ncm.ndp16.wNextFpIndex = 0; /* reserved */
+
+        memcpy(((u8 *)skb_out->data) + ctx->tx_ncm.nth16.wFpIndex,
+                                                &(ctx->tx_ncm.ndp16),
+                                                sizeof(ctx->tx_ncm.ndp16));
+
+        memcpy(((u8 *)skb_out->data) + ctx->tx_ncm.nth16.wFpIndex +
+                                        sizeof(ctx->tx_ncm.ndp16),
+                                        &(ctx->tx_ncm.dpe16),
+                                        (ctx->tx_curr_frame_num + 1) *
+                                        sizeof(struct usb_cdc_ncm_dpe16));
+
+        /* set frame length */
+        skb_put(skb_out, last_offset);
+
+        /* return skb */
+        ctx->tx_curr_skb = NULL;
+        return skb_out;
+
+exit_no_skb:
+        return NULL;
+}
+
+static void cdc_ncm_tx_timeout_start(struct cdc_ncm_ctx *ctx)
+{
+        /* start timer, if not already started */
+        if (timer_pending(&ctx->tx_timer) == 0) {
+                ctx->tx_timer.function = &cdc_ncm_tx_timeout;
+                ctx->tx_timer.data = (unsigned long)ctx;
+                ctx->tx_timer.expires = jiffies + ((HZ + 999) / 1000);
+                add_timer(&ctx->tx_timer);
+        }
+}
+
+static void cdc_ncm_tx_timeout(unsigned long arg)
+{
+        struct cdc_ncm_ctx *ctx = (struct cdc_ncm_ctx *)arg;
+        u8 restart;
+
+        spin_lock(&ctx->mtx);
+        if (ctx->tx_timer_pending != 0) {
+                ctx->tx_timer_pending--;
+                restart = 1;
+        } else
+                restart = 0;
+
+        spin_unlock(&ctx->mtx);
+
+        if (restart)
+                cdc_ncm_tx_timeout_start(ctx);
+        else if (ctx->netdev != NULL)
+                usbnet_start_xmit(NULL, ctx->netdev);
+}
+
+static struct sk_buff *
+cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags)
+{
+        struct sk_buff *skb_out;
+        struct cdc_ncm_ctx *ctx = (struct cdc_ncm_ctx *)dev->data[0];
+        u8 need_timer = 0;
+
+        /*
+         * The Ethernet API we are using does not support transmitting
+         * multiple Ethernet frames in a single call. This driver will
+         * accumulate multiple Ethernet frames and send out a larger
+         * USB frame when the USB buffer is full or when a single jiffies
+         * timeout happens.
+         */
+        if (ctx == NULL)
+                goto error;
+
+        spin_lock(&ctx->mtx);
+        skb_out = cdc_ncm_fill_tx_frame(ctx, skb);
+        if (ctx->tx_curr_skb != NULL)
+                need_timer = 1;
+        spin_unlock(&ctx->mtx);
+
+        /* Start timer, if there is a remaining skb */
+        if (need_timer)
+                cdc_ncm_tx_timeout_start(ctx);
+
+        if (skb_out)
+                dev->net->stats.tx_packets += ctx->tx_curr_frame_num;
+        return skb_out;
+
+error:
+        if (skb != NULL)
+                dev_kfree_skb_any(skb);
+
+        return NULL;
+}
+
+static int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in)
+{
+        struct sk_buff *skb;
+        struct cdc_ncm_ctx *ctx;
+        int sumlen;
+        int actlen;
+        int temp;
+        int nframes;
+        int x;
+        int offset;
+
+        ctx = (struct cdc_ncm_ctx *)dev->data[0];
+        if (ctx == NULL)
+                goto error;
+
+        actlen = skb_in->len;
+        sumlen = CDC_NCM_NTB_MAX_SIZE_RX;
+
+        if (actlen < (sizeof(ctx->rx_ncm.nth16) + sizeof(ctx->rx_ncm.ndp16))) {
+                pr_debug("frame too short\n");
+                goto error;
+        }
+
+        memcpy(&(ctx->rx_ncm.nth16), ((u8 *)skb_in->data),
+                                                sizeof(ctx->rx_ncm.nth16));
+
+        if (le32_to_cpu(ctx->rx_ncm.nth16.dwSignature) !=
+            USB_CDC_NCM_NTH16_SIGN) {
+                pr_debug("invalid NTH16 signature <%u>\n",
+                         le32_to_cpu(ctx->rx_ncm.nth16.dwSignature));
+                goto error;
+        }
+
+        temp = le16_to_cpu(ctx->rx_ncm.nth16.wBlockLength);
+        if (temp > sumlen) {
+                pr_debug("unsupported NTB block length %u/%u\n", temp, sumlen);
+                goto error;
+        }
+
+        temp = le16_to_cpu(ctx->rx_ncm.nth16.wFpIndex);
+        if ((temp + sizeof(ctx->rx_ncm.ndp16)) > actlen) {
+                pr_debug("invalid DPT16 index\n");
+                goto error;
+        }
+
+        memcpy(&(ctx->rx_ncm.ndp16), ((u8 *)skb_in->data) + temp,
+                                                sizeof(ctx->rx_ncm.ndp16));
+
+        if (le32_to_cpu(ctx->rx_ncm.ndp16.dwSignature) !=
+            USB_CDC_NCM_NDP16_NOCRC_SIGN) {
+                pr_debug("invalid DPT16 signature <%u>\n",
+                         le32_to_cpu(ctx->rx_ncm.ndp16.dwSignature));
+                goto error;
+        }
+
+        if (le16_to_cpu(ctx->rx_ncm.ndp16.wLength) <
+            USB_CDC_NCM_NDP16_LENGTH_MIN) {
+                pr_debug("invalid DPT16 length <%u>\n",
+                         le32_to_cpu(ctx->rx_ncm.ndp16.dwSignature));
+                goto error;
+        }
+
+        nframes = ((le16_to_cpu(ctx->rx_ncm.ndp16.wLength) -
+                                        sizeof(struct usb_cdc_ncm_ndp16)) /
+                                        sizeof(struct usb_cdc_ncm_dpe16));
+        nframes--; /* we process NDP entries except for the last one */
+
+        pr_debug("nframes = %u\n", nframes);
+
+        temp += sizeof(ctx->rx_ncm.ndp16);
+
+        if ((temp + nframes * (sizeof(struct usb_cdc_ncm_dpe16))) > actlen) {
+                pr_debug("Invalid nframes = %d\n", nframes);
+                goto error;
+        }
+
+        if (nframes > CDC_NCM_DPT_DATAGRAMS_MAX) {
+                pr_debug("Truncating number of frames from %u to %u\n",
+                                        nframes, CDC_NCM_DPT_DATAGRAMS_MAX);
+                nframes = CDC_NCM_DPT_DATAGRAMS_MAX;
+        }
+
+        memcpy(&(ctx->rx_ncm.dpe16), ((u8 *)skb_in->data) + temp,
+                                nframes * (sizeof(struct usb_cdc_ncm_dpe16)));
+
+        for (x = 0; x < nframes; x++) {
+                offset = le16_to_cpu(ctx->rx_ncm.dpe16[x].wDatagramIndex);
+                temp = le16_to_cpu(ctx->rx_ncm.dpe16[x].wDatagramLength);
+
+                /*
+                 * CDC NCM ch. 3.7
+                 * All entries after first NULL entry are to be ignored
+                 */
+                if ((offset == 0) || (temp == 0)) {
+                        if (!x)
+                                goto error; /* empty NTB */
+                        break;
+                }
+
+                /* sanity checking */
+                if (((offset + temp) > actlen) ||
+                    (temp > CDC_NCM_MAX_DATAGRAM_SIZE) || (temp < ETH_HLEN)) {
+                        pr_debug("invalid frame detected (ignored)"
+                                "offset[%u]=%u, length=%u, skb=%p\n",
+                                                        x, offset, temp, skb);
+                        if (!x)
+                                goto error;
+                        break;
+
+                } else {
+                        skb = skb_clone(skb_in, GFP_ATOMIC);
+                        skb->len = temp;
+                        skb->data = ((u8 *)skb_in->data) + offset;
+                        skb_set_tail_pointer(skb, temp);
+                        usbnet_skb_return(dev, skb);
+                }
+        }
+        return 1;
+error:
+        return 0;
+}
+
+static void
+cdc_ncm_speed_change(struct cdc_ncm_ctx *ctx,
+                     struct connection_speed_change *data)
+{
+        uint32_t rx_speed = le32_to_cpu(data->USBitRate);
+        uint32_t tx_speed = le32_to_cpu(data->DSBitRate);
+
+        /*
+         * Currently the USB-NET API does not support reporting the actual
+         * device speed. Do print it instead.
+         */
+        if ((tx_speed != ctx->tx_speed) || (rx_speed != ctx->rx_speed)) {
+                ctx->tx_speed = tx_speed;
+                ctx->rx_speed = rx_speed;
+
+                if ((tx_speed > 1000000) && (rx_speed > 1000000)) {
+                        printk(KERN_INFO KBUILD_MODNAME
+                                ": %s: %u mbit/s downlink "
+                                "%u mbit/s uplink\n",
+                                ctx->netdev->name,
+                                (unsigned int)(rx_speed / 1000000U),
+                                (unsigned int)(tx_speed / 1000000U));
+                } else {
+                        printk(KERN_INFO KBUILD_MODNAME
+                                ": %s: %u kbit/s downlink "
+                                "%u kbit/s uplink\n",
+                                ctx->netdev->name,
+                                (unsigned int)(rx_speed / 1000U),
+                                (unsigned int)(tx_speed / 1000U));
+                }
+        }
+}
+
+static void cdc_ncm_status(struct usbnet *dev, struct urb *urb)
+{
+        struct cdc_ncm_ctx *ctx;
+        struct usb_cdc_notification *event;
+
+        ctx = (struct cdc_ncm_ctx *)dev->data[0];
+
+        if (urb->actual_length < sizeof(*event))
+                return;
+
+        /* test for split data in 8-byte chunks */
+        if (test_and_clear_bit(EVENT_STS_SPLIT, &dev->flags)) {
+                cdc_ncm_speed_change(ctx,
+                      (struct connection_speed_change *)urb->transfer_buffer);
+                return;
+        }
+
+        event = urb->transfer_buffer;
+
+        switch (event->bNotificationType) {
+        case USB_CDC_NOTIFY_NETWORK_CONNECTION:
+                /*
+                 * According to the CDC NCM specification ch.7.1
+                 * USB_CDC_NOTIFY_NETWORK_CONNECTION notification shall be
+                 * sent by device after USB_CDC_NOTIFY_SPEED_CHANGE.
+                 */
+                ctx->connected = event->wValue;
+
+                printk(KERN_INFO KBUILD_MODNAME ": %s: network connection:"
+                        " %sconnected\n",
+                        ctx->netdev->name, ctx->connected ? "" : "dis");
+
+                if (ctx->connected)
+                        netif_carrier_on(dev->net);
+                else {
+                        netif_carrier_off(dev->net);
+                        ctx->tx_speed = ctx->rx_speed = 0;
+                }
+                break;
+
+        case USB_CDC_NOTIFY_SPEED_CHANGE:
+                if (urb->actual_length <
+                    (sizeof(*event) + sizeof(struct connection_speed_change)))
+                        set_bit(EVENT_STS_SPLIT, &dev->flags);
+                else
+                        cdc_ncm_speed_change(ctx,
+                                (struct connection_speed_change *) &event[1]);
+                break;
+
+        default:
+                dev_err(&dev->udev->dev, "NCM: unexpected "
+                        "notification 0x%02x!\n", event->bNotificationType);
+                break;
+        }
+}
+
+static int cdc_ncm_check_connect(struct usbnet *dev)
+{
+        struct cdc_ncm_ctx *ctx;
+
+        ctx = (struct cdc_ncm_ctx *)dev->data[0];
+        if (ctx == NULL)
+                return 1;       /* disconnected */
+
+        return !ctx->connected;
+}
+
+static int
+cdc_ncm_probe(struct usb_interface *udev, const struct usb_device_id *prod)
+{
+        return usbnet_probe(udev, prod);
+}
+
+static void cdc_ncm_disconnect(struct usb_interface *intf)
+{
+        struct usbnet *dev = usb_get_intfdata(intf);
+
+        if (dev == NULL)
+                return;         /* already disconnected */
+
+        usbnet_disconnect(intf);
+}
+
+static int cdc_ncm_manage_power(struct usbnet *dev, int status)
+{
+        dev->intf->needs_remote_wakeup = status;
+        return 0;
+}
+
+static const struct driver_info cdc_ncm_info = {
+        .description = "CDC NCM",
+        .flags = FLAG_NO_SETINT | FLAG_MULTI_PACKET,
+        .bind = cdc_ncm_bind,
+        .unbind = cdc_ncm_unbind,
+        .check_connect = cdc_ncm_check_connect,
+        .manage_power = cdc_ncm_manage_power,
+        .status = cdc_ncm_status,
+        .rx_fixup = cdc_ncm_rx_fixup,
+        .tx_fixup = cdc_ncm_tx_fixup,
+};
+
+static struct usb_driver cdc_ncm_driver = {
+        .name = "cdc_ncm",
+        .id_table = cdc_devs,
+        .probe = cdc_ncm_probe,
+        .disconnect = cdc_ncm_disconnect,
+        .suspend = usbnet_suspend,
+        .resume = usbnet_resume,
+        .supports_autosuspend = 1,
+};
+
+static struct ethtool_ops cdc_ncm_ethtool_ops = {
+        .get_drvinfo = cdc_ncm_get_drvinfo,
+        .get_link = usbnet_get_link,
+        .get_msglevel = usbnet_get_msglevel,
+        .set_msglevel = usbnet_set_msglevel,
+        .get_settings = usbnet_get_settings,
+        .set_settings = usbnet_set_settings,
+        .nway_reset = usbnet_nway_reset,
+};
+
+static int __init cdc_ncm_init(void)
+{
+        printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_VERSION "\n");
+        return usb_register(&cdc_ncm_driver);
+}
+
+module_init(cdc_ncm_init);
+
+static void __exit cdc_ncm_exit(void)
+{
+        usb_deregister(&cdc_ncm_driver);
+}
+
+module_exit(cdc_ncm_exit);
+
+MODULE_AUTHOR("Hans Petter Selasky");
+MODULE_DESCRIPTION("USB CDC NCM host driver");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/net/usb/hso.c b/drivers/net/usb/hso.c
index 812edf85d6d3..bed8fcedff49 100644
--- a/drivers/net/usb/hso.c
+++ b/drivers/net/usb/hso.c
@@ -997,6 +997,18 @@ static void packetizeRx(struct hso_net *odev, unsigned char *ip_pkt,
         }
 }
 
+static void fix_crc_bug(struct urb *urb, __le16 max_packet_size)
+{
+        static const u8 crc_check[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
+        u32 rest = urb->actual_length % le16_to_cpu(max_packet_size);
+
+        if (((rest == 5) || (rest == 6)) &&
+            !memcmp(((u8 *)urb->transfer_buffer) + urb->actual_length - 4,
+                    crc_check, 4)) {
+                urb->actual_length -= 4;
+        }
+}
+
 /* Moving data from usb to kernel (in interrupt state) */
 static void read_bulk_callback(struct urb *urb)
 {
@@ -1025,17 +1037,8 @@ static void read_bulk_callback(struct urb *urb)
                 return;
         }
 
-        if (odev->parent->port_spec & HSO_INFO_CRC_BUG) {
-                u32 rest;
-                u8 crc_check[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
-                rest = urb->actual_length %
-                        le16_to_cpu(odev->in_endp->wMaxPacketSize);
-                if (((rest == 5) || (rest == 6)) &&
-                    !memcmp(((u8 *) urb->transfer_buffer) +
-                            urb->actual_length - 4, crc_check, 4)) {
-                        urb->actual_length -= 4;
-                }
-        }
+        if (odev->parent->port_spec & HSO_INFO_CRC_BUG)
+                fix_crc_bug(urb, odev->in_endp->wMaxPacketSize);
 
         /* do we even have a packet? */
         if (urb->actual_length) {
@@ -1227,18 +1230,8 @@ static void hso_std_serial_read_bulk_callback(struct urb *urb)
                 return;
 
         if (status == 0) {
-                if (serial->parent->port_spec & HSO_INFO_CRC_BUG) {
-                        u32 rest;
-                        u8 crc_check[4] = { 0xDE, 0xAD, 0xBE, 0xEF };
-                        rest =
-                            urb->actual_length %
-                            le16_to_cpu(serial->in_endp->wMaxPacketSize);
-                        if (((rest == 5) || (rest == 6)) &&
-                            !memcmp(((u8 *) urb->transfer_buffer) +
-                                    urb->actual_length - 4, crc_check, 4)) {
-                                urb->actual_length -= 4;
-                        }
-                }
+                if (serial->parent->port_spec & HSO_INFO_CRC_BUG)
+                        fix_crc_bug(urb, serial->in_endp->wMaxPacketSize);
                 /* Valid data, handle RX data */
                 spin_lock(&serial->serial_lock);
                 serial->rx_urb_filled[hso_urb_to_index(serial, urb)] = 1;
@@ -1741,7 +1734,6 @@ static int hso_serial_ioctl(struct tty_struct *tty, struct file *file,
                             unsigned int cmd, unsigned long arg)
 {
         struct hso_serial *serial =  get_serial_by_tty(tty);
-        void __user *uarg = (void __user *)arg;
         int ret = 0;
         D4("IOCTL cmd: %d, arg: %ld", cmd, arg);
 
diff --git a/drivers/net/usb/ipheth.c b/drivers/net/usb/ipheth.c
index b2bcf99e6f08..7d42f9a2c068 100644
--- a/drivers/net/usb/ipheth.c
+++ b/drivers/net/usb/ipheth.c
@@ -363,7 +363,7 @@ static int ipheth_tx(struct sk_buff *skb, struct net_device *net)
 
         /* Paranoid */
         if (skb->len > IPHETH_BUF_SIZE) {
-                WARN(1, "%s: skb too large: %d bytes", __func__, skb->len);
+                WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len);
                 dev->net->stats.tx_dropped++;
                 dev_kfree_skb_irq(skb);
                 return NETDEV_TX_OK;
diff --git a/drivers/net/usb/mcs7830.c b/drivers/net/usb/mcs7830.c
index a6281e3987b5..2b791392e788 100644
--- a/drivers/net/usb/mcs7830.c
+++ b/drivers/net/usb/mcs7830.c
@@ -1,5 +1,5 @@
 /*
- * MOSCHIP MCS7830 based USB 2.0 Ethernet Devices
+ * MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices
  *
  * based on usbnet.c, asix.c and the vendor provided mcs7830 driver
  *
@@ -11,6 +11,9 @@
  *
  * Definitions gathered from MOSCHIP, Data Sheet_7830DA.pdf (thanks!).
  *
+ * 2010-12-19: add 7832 USB PID ("functionality same as MCS7830"),
+ *             per active notification by manufacturer
+ *
  * TODO:
  * - support HIF_REG_CONFIG_SLEEPMODE/HIF_REG_CONFIG_TXENABLE (via autopm?)
  * - implement ethtool_ops get_pauseparam/set_pauseparam
@@ -60,6 +63,7 @@
 #define MCS7830_MAX_MCAST       64
 
 #define MCS7830_VENDOR_ID       0x9710
+#define MCS7832_PRODUCT_ID      0x7832
 #define MCS7830_PRODUCT_ID      0x7830
 #define MCS7730_PRODUCT_ID      0x7730
 
@@ -351,7 +355,7 @@ static int mcs7830_set_autoneg(struct usbnet *dev, int ptrUserPhyMode)
         if (!ret)
                 ret = mcs7830_write_phy(dev, MII_BMCR,
                                 BMCR_ANENABLE | BMCR_ANRESTART  );
-        return ret < 0 ? : 0;
+        return ret;
 }
 
 
@@ -626,7 +630,7 @@ static int mcs7830_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
 }
 
 static const struct driver_info moschip_info = {
-        .description    = "MOSCHIP 7830/7730 usb-NET adapter",
+        .description    = "MOSCHIP 7830/7832/7730 usb-NET adapter",
         .bind           = mcs7830_bind,
         .rx_fixup       = mcs7830_rx_fixup,
         .flags          = FLAG_ETHER,
@@ -645,6 +649,10 @@ static const struct driver_info sitecom_info = {
 
 static const struct usb_device_id products[] = {
         {
+                USB_DEVICE(MCS7830_VENDOR_ID, MCS7832_PRODUCT_ID),
+                .driver_info = (unsigned long) &moschip_info,
+        },
+        {
                 USB_DEVICE(MCS7830_VENDOR_ID, MCS7830_PRODUCT_ID),
                 .driver_info = (unsigned long) &moschip_info,
         },
diff --git a/drivers/net/usb/pegasus.c b/drivers/net/usb/pegasus.c
index 6710f09346d6..ef3667690b12 100644
--- a/drivers/net/usb/pegasus.c
+++ b/drivers/net/usb/pegasus.c
@@ -359,7 +359,7 @@ fail:
 
 static int mdio_read(struct net_device *dev, int phy_id, int loc)
 {
-        pegasus_t *pegasus = (pegasus_t *) netdev_priv(dev);
+        pegasus_t *pegasus = netdev_priv(dev);
         u16 res;
 
         read_mii_word(pegasus, phy_id, loc, &res);
@@ -397,7 +397,7 @@ fail:
 
 static void mdio_write(struct net_device *dev, int phy_id, int loc, int val)
 {
-        pegasus_t *pegasus = (pegasus_t *) netdev_priv(dev);
+        pegasus_t *pegasus = netdev_priv(dev);
 
         write_mii_word(pegasus, phy_id, loc, val);
 }
diff --git a/drivers/net/usb/sierra_net.c b/drivers/net/usb/sierra_net.c
index d1ac15c95faf..ed1b43210584 100644
--- a/drivers/net/usb/sierra_net.c
+++ b/drivers/net/usb/sierra_net.c
@@ -802,10 +802,9 @@ static void sierra_net_unbind(struct usbnet *dev, struct usb_interface *intf)
 
         dev_dbg(&dev->udev->dev, "%s", __func__);
 
-        /* Kill the timer then flush the work queue */
+        /* kill the timer and work */
         del_timer_sync(&priv->sync_timer);
-
-        flush_scheduled_work();
+        cancel_work_sync(&priv->sierra_net_kevent);
 
         /* tell modem we are going away */
         status = sierra_net_send_cmd(dev, priv->shdwn_msg,
diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c
index 65cb1abfbe57..bc86f4b6ecc2 100644
--- a/drivers/net/usb/smsc95xx.c
+++ b/drivers/net/usb/smsc95xx.c
@@ -1163,9 +1163,8 @@ static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
 
 static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
 {
-        int len = skb->data - skb->head;
-        u16 high_16 = (u16)(skb->csum_offset + skb->csum_start - len);
-        u16 low_16 = (u16)(skb->csum_start - len);
+        u16 low_16 = (u16)skb_checksum_start_offset(skb);
+        u16 high_16 = low_16 + skb->csum_offset;
         return (high_16 << 16) | low_16;
 }
 
@@ -1193,7 +1192,7 @@ static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
                 if (skb->len <= 45) {
                         /* workaround - hardware tx checksum does not work
                          * properly with extremely small packets */
-                        long csstart = skb->csum_start - skb_headroom(skb);
+                        long csstart = skb_checksum_start_offset(skb);
                         __wsum calc = csum_partial(skb->data + csstart,
                                 skb->len - csstart, 0);
                         *((__sum16 *)(skb->data + csstart
diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c
index c04d49e31f81..ed9a41643ff4 100644
--- a/drivers/net/usb/usbnet.c
+++ b/drivers/net/usb/usbnet.c
@@ -391,14 +391,19 @@ static inline void rx_process (struct usbnet *dev, struct sk_buff *skb)
                 goto error;
         // else network stack removes extra byte if we forced a short packet
 
-        if (skb->len)
-                usbnet_skb_return (dev, skb);
-        else {
-                netif_dbg(dev, rx_err, dev->net, "drop\n");
-error:
-                dev->net->stats.rx_errors++;
-                skb_queue_tail (&dev->done, skb);
+        if (skb->len) {
+                /* all data was already cloned from skb inside the driver */
+                if (dev->driver_info->flags & FLAG_MULTI_PACKET)
+                        dev_kfree_skb_any(skb);
+                else
+                        usbnet_skb_return(dev, skb);
+                return;
         }
+
+        netif_dbg(dev, rx_err, dev->net, "drop\n");
+error:
+        dev->net->stats.rx_errors++;
+        skb_queue_tail(&dev->done, skb);
 }
 
 /*-------------------------------------------------------------------------*/
@@ -971,7 +976,8 @@ static void tx_complete (struct urb *urb)
         struct usbnet           *dev = entry->dev;
 
         if (urb->status == 0) {
-                dev->net->stats.tx_packets++;
+                if (!(dev->driver_info->flags & FLAG_MULTI_PACKET))
+                        dev->net->stats.tx_packets++;
                 dev->net->stats.tx_bytes += entry->length;
         } else {
                 dev->net->stats.tx_errors++;
@@ -1044,8 +1050,13 @@ netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
         if (info->tx_fixup) {
                 skb = info->tx_fixup (dev, skb, GFP_ATOMIC);
                 if (!skb) {
-                        netif_dbg(dev, tx_err, dev->net, "can't tx_fixup skb\n");
-                        goto drop;
+                        if (netif_msg_tx_err(dev)) {
+                                netif_dbg(dev, tx_err, dev->net, "can't tx_fixup skb\n");
+                                goto drop;
+                        } else {
+                                /* cdc_ncm collected packet; waits for more */
+                                goto not_drop;
+                        }
                 }
         }
         length = skb->len;
@@ -1067,13 +1078,18 @@ netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
         /* don't assume the hardware handles USB_ZERO_PACKET
          * NOTE:  strictly conforming cdc-ether devices should expect
          * the ZLP here, but ignore the one-byte packet.
+         * NOTE2: CDC NCM specification is different from CDC ECM when
+         * handling ZLP/short packets, so cdc_ncm driver will make short
+         * packet itself if needed.
          */
         if (length % dev->maxpacket == 0) {
                 if (!(info->flags & FLAG_SEND_ZLP)) {
-                        urb->transfer_buffer_length++;
-                        if (skb_tailroom(skb)) {
-                                skb->data[skb->len] = 0;
-                                __skb_put(skb, 1);
+                        if (!(info->flags & FLAG_MULTI_PACKET)) {
+                                urb->transfer_buffer_length++;
+                                if (skb_tailroom(skb)) {
+                                        skb->data[skb->len] = 0;
+                                        __skb_put(skb, 1);
+                                }
                         }
                 } else
                         urb->transfer_flags |= URB_ZERO_PACKET;
@@ -1122,6 +1138,7 @@ netdev_tx_t usbnet_start_xmit (struct sk_buff *skb,
                 netif_dbg(dev, tx_err, dev->net, "drop, code %d\n", retval);
 drop:
                 dev->net->stats.tx_dropped++;
+not_drop:
                 if (skb)
                         dev_kfree_skb_any (skb);
                 usb_free_urb (urb);
@@ -1231,8 +1248,7 @@ void usbnet_disconnect (struct usb_interface *intf)
         net = dev->net;
         unregister_netdev (net);
 
-        /* we don't hold rtnl here ... */
-        flush_scheduled_work ();
+        cancel_work_sync(&dev->kevent);
 
         if (dev->driver_info->unbind)
                 dev->driver_info->unbind (dev, intf);
diff --git a/drivers/net/veth.c b/drivers/net/veth.c
index 0bbc0c323135..cc83fa71c3ff 100644
--- a/drivers/net/veth.c
+++ b/drivers/net/veth.c
@@ -166,7 +166,9 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev)
         if (!(rcv->flags & IFF_UP))
                 goto tx_drop;
 
-        if (dev->features & NETIF_F_NO_CSUM)
+        /* don't change ip_summed == CHECKSUM_PARTIAL, as that
+           will cause bad checksum on forwarded packets */
+        if (skb->ip_summed == CHECKSUM_NONE)
                 skb->ip_summed = rcv_priv->ip_summed;
 
         length = skb->len + ETH_HLEN;
diff --git a/drivers/net/via-rhine.c b/drivers/net/via-rhine.c
index 4930f9dbc493..5e7f069eab53 100644
--- a/drivers/net/via-rhine.c
+++ b/drivers/net/via-rhine.c
@@ -30,8 +30,8 @@
 */
 
 #define DRV_NAME        "via-rhine"
-#define DRV_VERSION     "1.4.3"
-#define DRV_RELDATE     "2007-03-06"
+#define DRV_VERSION     "1.5.0"
+#define DRV_RELDATE     "2010-10-09"
 
 
 /* A few user-configurable values.
@@ -100,6 +100,7 @@ static const int multicast_filter_limit = 32;
 #include <linux/mii.h>
 #include <linux/ethtool.h>
 #include <linux/crc32.h>
+#include <linux/if_vlan.h>
 #include <linux/bitops.h>
 #include <linux/workqueue.h>
 #include <asm/processor.h>      /* Processor type for cache alignment. */
@@ -133,6 +134,9 @@ MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
 
+#define MCAM_SIZE       32
+#define VCAM_SIZE       32
+
 /*
                 Theory of Operation
 
@@ -279,15 +283,16 @@ MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
 /* Offsets to the device registers. */
 enum register_offsets {
         StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
-        ChipCmd1=0x09,
+        ChipCmd1=0x09, TQWake=0x0A,
         IntrStatus=0x0C, IntrEnable=0x0E,
         MulticastFilter0=0x10, MulticastFilter1=0x14,
         RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
-        MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
+        MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F,
         MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
         ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
         RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
         StickyHW=0x83, IntrStatus2=0x84,
+        CamMask=0x88, CamCon=0x92, CamAddr=0x93,
         WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
         WOLcrClr1=0xA6, WOLcgClr=0xA7,
         PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
@@ -299,6 +304,40 @@ enum backoff_bits {
         BackCaptureEffect=0x04, BackRandom=0x08
 };
 
+/* Bits in the TxConfig (TCR) register */
+enum tcr_bits {
+        TCR_PQEN=0x01,
+        TCR_LB0=0x02,           /* loopback[0] */
+        TCR_LB1=0x04,           /* loopback[1] */
+        TCR_OFSET=0x08,
+        TCR_RTGOPT=0x10,
+        TCR_RTFT0=0x20,
+        TCR_RTFT1=0x40,
+        TCR_RTSF=0x80,
+};
+
+/* Bits in the CamCon (CAMC) register */
+enum camcon_bits {
+        CAMC_CAMEN=0x01,
+        CAMC_VCAMSL=0x02,
+        CAMC_CAMWR=0x04,
+        CAMC_CAMRD=0x08,
+};
+
+/* Bits in the PCIBusConfig1 (BCR1) register */
+enum bcr1_bits {
+        BCR1_POT0=0x01,
+        BCR1_POT1=0x02,
+        BCR1_POT2=0x04,
+        BCR1_CTFT0=0x08,
+        BCR1_CTFT1=0x10,
+        BCR1_CTSF=0x20,
+        BCR1_TXQNOBK=0x40,      /* for VT6105 */
+        BCR1_VIDFR=0x80,        /* for VT6105 */
+        BCR1_MED0=0x40,         /* for VT6102 */
+        BCR1_MED1=0x80,         /* for VT6102 */
+};
+
 #ifdef USE_MMIO
 /* Registers we check that mmio and reg are the same. */
 static const int mmio_verify_registers[] = {
@@ -356,6 +395,11 @@ enum desc_status_bits {
         DescOwn=0x80000000
 };
 
+/* Bits in *_desc.*_length */
+enum desc_length_bits {
+        DescTag=0x00010000
+};
+
 /* Bits in ChipCmd. */
 enum chip_cmd_bits {
         CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
@@ -365,6 +409,9 @@ enum chip_cmd_bits {
 };
 
 struct rhine_private {
+        /* Bit mask for configured VLAN ids */
+        unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
+
         /* Descriptor rings */
         struct rx_desc *rx_ring;
         struct tx_desc *tx_ring;
@@ -405,6 +452,23 @@ struct rhine_private {
         void __iomem *base;
 };
 
+#define BYTE_REG_BITS_ON(x, p)      do { iowrite8((ioread8((p))|(x)), (p)); } while (0)
+#define WORD_REG_BITS_ON(x, p)      do { iowrite16((ioread16((p))|(x)), (p)); } while (0)
+#define DWORD_REG_BITS_ON(x, p)     do { iowrite32((ioread32((p))|(x)), (p)); } while (0)
+
+#define BYTE_REG_BITS_IS_ON(x, p)   (ioread8((p)) & (x))
+#define WORD_REG_BITS_IS_ON(x, p)   (ioread16((p)) & (x))
+#define DWORD_REG_BITS_IS_ON(x, p)  (ioread32((p)) & (x))
+
+#define BYTE_REG_BITS_OFF(x, p)     do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0)
+#define WORD_REG_BITS_OFF(x, p)     do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0)
+#define DWORD_REG_BITS_OFF(x, p)    do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0)
+
+#define BYTE_REG_BITS_SET(x, m, p)   do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0)
+#define WORD_REG_BITS_SET(x, m, p)   do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0)
+#define DWORD_REG_BITS_SET(x, m, p)  do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0)
+
+
 static int  mdio_read(struct net_device *dev, int phy_id, int location);
 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
 static int  rhine_open(struct net_device *dev);
@@ -422,6 +486,14 @@ static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 static const struct ethtool_ops netdev_ethtool_ops;
 static int  rhine_close(struct net_device *dev);
 static void rhine_shutdown (struct pci_dev *pdev);
+static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid);
+static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
+static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr);
+static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr);
+static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask);
+static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask);
+static void rhine_init_cam_filter(struct net_device *dev);
+static void rhine_update_vcam(struct net_device *dev);
 
 #define RHINE_WAIT_FOR(condition) do {                                  \
         int i=1024;                                                     \
@@ -629,6 +701,8 @@ static const struct net_device_ops rhine_netdev_ops = {
         .ndo_set_mac_address     = eth_mac_addr,
         .ndo_do_ioctl            = netdev_ioctl,
         .ndo_tx_timeout          = rhine_tx_timeout,
+        .ndo_vlan_rx_add_vid     = rhine_vlan_rx_add_vid,
+        .ndo_vlan_rx_kill_vid    = rhine_vlan_rx_kill_vid,
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller     = rhine_poll,
 #endif
@@ -795,6 +869,10 @@ static int __devinit rhine_init_one(struct pci_dev *pdev,
         if (rp->quirks & rqRhineI)
                 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
 
+        if (pdev->revision >= VT6105M)
+                dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
+                NETIF_F_HW_VLAN_FILTER;
+
         /* dev->name not defined before register_netdev()! */
         rc = register_netdev(dev);
         if (rc)
@@ -1040,6 +1118,167 @@ static void rhine_set_carrier(struct mii_if_info *mii)
                        netif_carrier_ok(mii->dev));
 }
 
+/**
+ * rhine_set_cam - set CAM multicast filters
+ * @ioaddr: register block of this Rhine
+ * @idx: multicast CAM index [0..MCAM_SIZE-1]
+ * @addr: multicast address (6 bytes)
+ *
+ * Load addresses into multicast filters.
+ */
+static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr)
+{
+        int i;
+
+        iowrite8(CAMC_CAMEN, ioaddr + CamCon);
+        wmb();
+
+        /* Paranoid -- idx out of range should never happen */
+        idx &= (MCAM_SIZE - 1);
+
+        iowrite8((u8) idx, ioaddr + CamAddr);
+
+        for (i = 0; i < 6; i++, addr++)
+                iowrite8(*addr, ioaddr + MulticastFilter0 + i);
+        udelay(10);
+        wmb();
+
+        iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
+        udelay(10);
+
+        iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_set_vlan_cam - set CAM VLAN filters
+ * @ioaddr: register block of this Rhine
+ * @idx: VLAN CAM index [0..VCAM_SIZE-1]
+ * @addr: VLAN ID (2 bytes)
+ *
+ * Load addresses into VLAN filters.
+ */
+static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr)
+{
+        iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
+        wmb();
+
+        /* Paranoid -- idx out of range should never happen */
+        idx &= (VCAM_SIZE - 1);
+
+        iowrite8((u8) idx, ioaddr + CamAddr);
+
+        iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6);
+        udelay(10);
+        wmb();
+
+        iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon);
+        udelay(10);
+
+        iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_set_cam_mask - set multicast CAM mask
+ * @ioaddr: register block of this Rhine
+ * @mask: multicast CAM mask
+ *
+ * Mask sets multicast filters active/inactive.
+ */
+static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask)
+{
+        iowrite8(CAMC_CAMEN, ioaddr + CamCon);
+        wmb();
+
+        /* write mask */
+        iowrite32(mask, ioaddr + CamMask);
+
+        /* disable CAMEN */
+        iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_set_vlan_cam_mask - set VLAN CAM mask
+ * @ioaddr: register block of this Rhine
+ * @mask: VLAN CAM mask
+ *
+ * Mask sets VLAN filters active/inactive.
+ */
+static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask)
+{
+        iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon);
+        wmb();
+
+        /* write mask */
+        iowrite32(mask, ioaddr + CamMask);
+
+        /* disable CAMEN */
+        iowrite8(0, ioaddr + CamCon);
+}
+
+/**
+ * rhine_init_cam_filter - initialize CAM filters
+ * @dev: network device
+ *
+ * Initialize (disable) hardware VLAN and multicast support on this
+ * Rhine.
+ */
+static void rhine_init_cam_filter(struct net_device *dev)
+{
+        struct rhine_private *rp = netdev_priv(dev);
+        void __iomem *ioaddr = rp->base;
+
+        /* Disable all CAMs */
+        rhine_set_vlan_cam_mask(ioaddr, 0);
+        rhine_set_cam_mask(ioaddr, 0);
+
+        /* disable hardware VLAN support */
+        BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig);
+        BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
+}
+
+/**
+ * rhine_update_vcam - update VLAN CAM filters
+ * @rp: rhine_private data of this Rhine
+ *
+ * Update VLAN CAM filters to match configuration change.
+ */
+static void rhine_update_vcam(struct net_device *dev)
+{
+        struct rhine_private *rp = netdev_priv(dev);
+        void __iomem *ioaddr = rp->base;
+        u16 vid;
+        u32 vCAMmask = 0;       /* 32 vCAMs (6105M and better) */
+        unsigned int i = 0;
+
+        for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) {
+                rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid);
+                vCAMmask |= 1 << i;
+                if (++i >= VCAM_SIZE)
+                        break;
+        }
+        rhine_set_vlan_cam_mask(ioaddr, vCAMmask);
+}
+
+static void rhine_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
+{
+        struct rhine_private *rp = netdev_priv(dev);
+
+        spin_lock_irq(&rp->lock);
+        set_bit(vid, rp->active_vlans);
+        rhine_update_vcam(dev);
+        spin_unlock_irq(&rp->lock);
+}
+
+static void rhine_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
+{
+        struct rhine_private *rp = netdev_priv(dev);
+
+        spin_lock_irq(&rp->lock);
+        clear_bit(vid, rp->active_vlans);
+        rhine_update_vcam(dev);
+        spin_unlock_irq(&rp->lock);
+}
+
 static void init_registers(struct net_device *dev)
 {
         struct rhine_private *rp = netdev_priv(dev);
@@ -1061,6 +1300,9 @@ static void init_registers(struct net_device *dev)
 
         rhine_set_rx_mode(dev);
 
+        if (rp->pdev->revision >= VT6105M)
+                rhine_init_cam_filter(dev);
+
         napi_enable(&rp->napi);
 
         /* Enable interrupts by setting the interrupt mask. */
@@ -1276,16 +1518,28 @@ static netdev_tx_t rhine_start_tx(struct sk_buff *skb,
         rp->tx_ring[entry].desc_length =
                 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
 
+        if (unlikely(vlan_tx_tag_present(skb))) {
+                rp->tx_ring[entry].tx_status = cpu_to_le32((vlan_tx_tag_get(skb)) << 16);
+                /* request tagging */
+                rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000);
+        }
+        else
+                rp->tx_ring[entry].tx_status = 0;
+
         /* lock eth irq */
         spin_lock_irqsave(&rp->lock, flags);
         wmb();
-        rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
+        rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn);
         wmb();
 
         rp->cur_tx++;
 
         /* Non-x86 Todo: explicitly flush cache lines here. */
 
+        if (vlan_tx_tag_present(skb))
+                /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
+                BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
+
         /* Wake the potentially-idle transmit channel */
         iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
                ioaddr + ChipCmd1);
@@ -1437,6 +1691,21 @@ static void rhine_tx(struct net_device *dev)
         spin_unlock(&rp->lock);
 }
 
+/**
+ * rhine_get_vlan_tci - extract TCI from Rx data buffer
+ * @skb: pointer to sk_buff
+ * @data_size: used data area of the buffer including CRC
+ *
+ * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q
+ * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte
+ * aligned following the CRC.
+ */
+static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size)
+{
+        u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2;
+        return ntohs(*(u16 *)trailer);
+}
+
 /* Process up to limit frames from receive ring */
 static int rhine_rx(struct net_device *dev, int limit)
 {
@@ -1454,6 +1723,7 @@ static int rhine_rx(struct net_device *dev, int limit)
         for (count = 0; count < limit; ++count) {
                 struct rx_desc *desc = rp->rx_head_desc;
                 u32 desc_status = le32_to_cpu(desc->rx_status);
+                u32 desc_length = le32_to_cpu(desc->desc_length);
                 int data_size = desc_status >> 16;
 
                 if (desc_status & DescOwn)
@@ -1498,6 +1768,7 @@ static int rhine_rx(struct net_device *dev, int limit)
                         struct sk_buff *skb = NULL;
                         /* Length should omit the CRC */
                         int pkt_len = data_size - 4;
+                        u16 vlan_tci = 0;
 
                         /* Check if the packet is long enough to accept without
                            copying to a minimally-sized skbuff. */
@@ -1532,7 +1803,14 @@ static int rhine_rx(struct net_device *dev, int limit)
                                                  rp->rx_buf_sz,
                                                  PCI_DMA_FROMDEVICE);
                         }
+
+                        if (unlikely(desc_length & DescTag))
+                                vlan_tci = rhine_get_vlan_tci(skb, data_size);
+
                         skb->protocol = eth_type_trans(skb, dev);
+
+                        if (unlikely(desc_length & DescTag))
+                                __vlan_hwaccel_put_tag(skb, vlan_tci);
                         netif_receive_skb(skb);
                         dev->stats.rx_bytes += pkt_len;
                         dev->stats.rx_packets++;
@@ -1596,6 +1874,11 @@ static void rhine_restart_tx(struct net_device *dev) {
 
                 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
                        ioaddr + ChipCmd);
+
+                if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000))
+                        /* Tx queues are bits 7-0 (first Tx queue: bit 7) */
+                        BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake);
+
                 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
                        ioaddr + ChipCmd1);
                 IOSYNC;
@@ -1631,7 +1914,7 @@ static void rhine_error(struct net_device *dev, int intr_status)
         }
         if (intr_status & IntrTxUnderrun) {
                 if (rp->tx_thresh < 0xE0)
-                        iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
+                        BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
                 if (debug > 1)
                         printk(KERN_INFO "%s: Transmitter underrun, Tx "
                                "threshold now %2.2x.\n",
@@ -1646,7 +1929,7 @@ static void rhine_error(struct net_device *dev, int intr_status)
             (intr_status & (IntrTxAborted |
              IntrTxUnderrun | IntrTxDescRace)) == 0) {
                 if (rp->tx_thresh < 0xE0) {
-                        iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
+                        BYTE_REG_BITS_SET((rp->tx_thresh += 0x20), 0x80, ioaddr + TxConfig);
                 }
                 if (debug > 1)
                         printk(KERN_INFO "%s: Unspecified error. Tx "
@@ -1688,7 +1971,8 @@ static void rhine_set_rx_mode(struct net_device *dev)
         struct rhine_private *rp = netdev_priv(dev);
         void __iomem *ioaddr = rp->base;
         u32 mc_filter[2];       /* Multicast hash filter */
-        u8 rx_mode;             /* Note: 0x02=accept runt, 0x01=accept errs */
+        u8 rx_mode = 0x0C;      /* Note: 0x02=accept runt, 0x01=accept errs */
+        struct netdev_hw_addr *ha;
 
         if (dev->flags & IFF_PROMISC) {         /* Set promiscuous. */
                 rx_mode = 0x1C;
@@ -1699,10 +1983,18 @@ static void rhine_set_rx_mode(struct net_device *dev)
                 /* Too many to match, or accept all multicasts. */
                 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
                 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
-                rx_mode = 0x0C;
+        } else if (rp->pdev->revision >= VT6105M) {
+                int i = 0;
+                u32 mCAMmask = 0;       /* 32 mCAMs (6105M and better) */
+                netdev_for_each_mc_addr(ha, dev) {
+                        if (i == MCAM_SIZE)
+                                break;
+                        rhine_set_cam(ioaddr, i, ha->addr);
+                        mCAMmask |= 1 << i;
+                        i++;
+                }
+                rhine_set_cam_mask(ioaddr, mCAMmask);
         } else {
-                struct netdev_hw_addr *ha;
-
                 memset(mc_filter, 0, sizeof(mc_filter));
                 netdev_for_each_mc_addr(ha, dev) {
                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
@@ -1711,9 +2003,15 @@ static void rhine_set_rx_mode(struct net_device *dev)
                 }
                 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
                 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
-                rx_mode = 0x0C;
         }
-        iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
+        /* enable/disable VLAN receive filtering */
+        if (rp->pdev->revision >= VT6105M) {
+                if (dev->flags & IFF_PROMISC)
+                        BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1);
+                else
+                        BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1);
+        }
+        BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig);
 }
 
 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
@@ -1966,7 +2264,7 @@ static int rhine_resume(struct pci_dev *pdev)
         if (!netif_running(dev))
                 return 0;
 
-        if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
+        if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
                 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
 
         ret = pci_set_power_state(pdev, PCI_D0);
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index b6d402806ae6..90a23e410d1b 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -519,7 +519,7 @@ static int xmit_skb(struct virtnet_info *vi, struct sk_buff *skb)
 
         if (skb->ip_summed == CHECKSUM_PARTIAL) {
                 hdr->hdr.flags = VIRTIO_NET_HDR_F_NEEDS_CSUM;
-                hdr->hdr.csum_start = skb->csum_start - skb_headroom(skb);
+                hdr->hdr.csum_start = skb_checksum_start_offset(skb);
                 hdr->hdr.csum_offset = skb->csum_offset;
         } else {
                 hdr->hdr.flags = 0;
diff --git a/drivers/net/vmxnet3/vmxnet3_drv.c b/drivers/net/vmxnet3/vmxnet3_drv.c
index 21314e06e6d7..d143e8b72b5b 100644
--- a/drivers/net/vmxnet3/vmxnet3_drv.c
+++ b/drivers/net/vmxnet3/vmxnet3_drv.c
@@ -44,6 +44,9 @@ MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
 
 static atomic_t devices_found;
 
+#define VMXNET3_MAX_DEVICES 10
+static int enable_mq = 1;
+static int irq_share_mode;
 
 /*
  *    Enable/Disable the given intr
@@ -99,7 +102,7 @@ vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
 static bool
 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 {
-        return netif_queue_stopped(adapter->netdev);
+        return tq->stopped;
 }
 
 
@@ -107,7 +110,7 @@ static void
 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 {
         tq->stopped = false;
-        netif_start_queue(adapter->netdev);
+        netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
 }
 
 
@@ -115,7 +118,7 @@ static void
 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 {
         tq->stopped = false;
-        netif_wake_queue(adapter->netdev);
+        netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
 }
 
 
@@ -124,7 +127,7 @@ vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
 {
         tq->stopped = true;
         tq->num_stop++;
-        netif_stop_queue(adapter->netdev);
+        netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
 }
 
 
@@ -135,6 +138,7 @@ static void
 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
 {
         u32 ret;
+        int i;
 
         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
         ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
@@ -145,22 +149,28 @@ vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
                 if (!netif_carrier_ok(adapter->netdev))
                         netif_carrier_on(adapter->netdev);
 
-                if (affectTxQueue)
-                        vmxnet3_tq_start(&adapter->tx_queue, adapter);
+                if (affectTxQueue) {
+                        for (i = 0; i < adapter->num_tx_queues; i++)
+                                vmxnet3_tq_start(&adapter->tx_queue[i],
+                                                 adapter);
+                }
         } else {
                 printk(KERN_INFO "%s: NIC Link is Down\n",
                        adapter->netdev->name);
                 if (netif_carrier_ok(adapter->netdev))
                         netif_carrier_off(adapter->netdev);
 
-                if (affectTxQueue)
-                        vmxnet3_tq_stop(&adapter->tx_queue, adapter);
+                if (affectTxQueue) {
+                        for (i = 0; i < adapter->num_tx_queues; i++)
+                                vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
+                }
         }
 }
 
 static void
 vmxnet3_process_events(struct vmxnet3_adapter *adapter)
 {
+        int i;
         u32 events = le32_to_cpu(adapter->shared->ecr);
         if (!events)
                 return;
@@ -176,16 +186,18 @@ vmxnet3_process_events(struct vmxnet3_adapter *adapter)
                 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
                                        VMXNET3_CMD_GET_QUEUE_STATUS);
 
-                if (adapter->tqd_start->status.stopped) {
-                        printk(KERN_ERR "%s: tq error 0x%x\n",
-                               adapter->netdev->name,
-                               le32_to_cpu(adapter->tqd_start->status.error));
-                }
-                if (adapter->rqd_start->status.stopped) {
-                        printk(KERN_ERR "%s: rq error 0x%x\n",
-                               adapter->netdev->name,
-                               adapter->rqd_start->status.error);
-                }
+                for (i = 0; i < adapter->num_tx_queues; i++)
+                        if (adapter->tqd_start[i].status.stopped)
+                                dev_err(&adapter->netdev->dev,
+                                        "%s: tq[%d] error 0x%x\n",
+                                        adapter->netdev->name, i, le32_to_cpu(
+                                        adapter->tqd_start[i].status.error));
+                for (i = 0; i < adapter->num_rx_queues; i++)
+                        if (adapter->rqd_start[i].status.stopped)
+                                dev_err(&adapter->netdev->dev,
+                                        "%s: rq[%d] error 0x%x\n",
+                                        adapter->netdev->name, i,
+                                        adapter->rqd_start[i].status.error);
 
                 schedule_work(&adapter->work);
         }
@@ -410,7 +422,7 @@ vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
 }
 
 
-void
+static void
 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
                    struct vmxnet3_adapter *adapter)
 {
@@ -437,6 +449,17 @@ vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
 }
 
 
+/* Destroy all tx queues */
+void
+vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
+{
+        int i;
+
+        for (i = 0; i < adapter->num_tx_queues; i++)
+                vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
+}
+
+
 static void
 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
                 struct vmxnet3_adapter *adapter)
@@ -518,6 +541,14 @@ err:
         return -ENOMEM;
 }
 
+static void
+vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
+{
+        int i;
+
+        for (i = 0; i < adapter->num_tx_queues; i++)
+                vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
+}
 
 /*
  *    starting from ring->next2fill, allocate rx buffers for the given ring
@@ -732,6 +763,17 @@ vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
 }
 
 
+/* Init all tx queues */
+static void
+vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
+{
+        int i;
+
+        for (i = 0; i < adapter->num_tx_queues; i++)
+                vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
+}
+
+
 /*
  *    parse and copy relevant protocol headers:
  *      For a tso pkt, relevant headers are L2/3/4 including options
@@ -756,7 +798,7 @@ vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
 {
         struct Vmxnet3_TxDataDesc *tdd;
 
-        if (ctx->mss) {
+        if (ctx->mss) { /* TSO */
                 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
                 ctx->l4_hdr_size = ((struct tcphdr *)
                                    skb_transport_header(skb))->doff * 4;
@@ -765,7 +807,7 @@ vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
                 unsigned int pull_size;
 
                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
-                        ctx->eth_ip_hdr_size = skb_transport_offset(skb);
+                        ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
 
                         if (ctx->ipv4) {
                                 struct iphdr *iph = (struct iphdr *)
@@ -903,6 +945,21 @@ vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
                 }
         }
 
+        spin_lock_irqsave(&tq->tx_lock, flags);
+
+        if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
+                tq->stats.tx_ring_full++;
+                dev_dbg(&adapter->netdev->dev,
+                        "tx queue stopped on %s, next2comp %u"
+                        " next2fill %u\n", adapter->netdev->name,
+                        tq->tx_ring.next2comp, tq->tx_ring.next2fill);
+
+                vmxnet3_tq_stop(tq, adapter);
+                spin_unlock_irqrestore(&tq->tx_lock, flags);
+                return NETDEV_TX_BUSY;
+        }
+
+
         ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
         if (ret >= 0) {
                 BUG_ON(ret <= 0 && ctx.copy_size != 0);
@@ -923,21 +980,7 @@ vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
                 }
         } else {
                 tq->stats.drop_hdr_inspect_err++;
-                goto drop_pkt;
-        }
-
-        spin_lock_irqsave(&tq->tx_lock, flags);
-
-        if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
-                tq->stats.tx_ring_full++;
-                dev_dbg(&adapter->netdev->dev,
-                        "tx queue stopped on %s, next2comp %u"
-                        " next2fill %u\n", adapter->netdev->name,
-                        tq->tx_ring.next2comp, tq->tx_ring.next2fill);
-
-                vmxnet3_tq_stop(tq, adapter);
-                spin_unlock_irqrestore(&tq->tx_lock, flags);
-                return NETDEV_TX_BUSY;
+                goto unlock_drop_pkt;
         }
 
         /* fill tx descs related to addr & len */
@@ -1000,7 +1043,8 @@ vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
         if (le32_to_cpu(tq->shared->txNumDeferred) >=
                                         le32_to_cpu(tq->shared->txThreshold)) {
                 tq->shared->txNumDeferred = 0;
-                VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_TXPROD,
+                VMXNET3_WRITE_BAR0_REG(adapter,
+                                       VMXNET3_REG_TXPROD + tq->qid * 8,
                                        tq->tx_ring.next2fill);
         }
 
@@ -1008,6 +1052,8 @@ vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
 
 hdr_too_big:
         tq->stats.drop_oversized_hdr++;
+unlock_drop_pkt:
+        spin_unlock_irqrestore(&tq->tx_lock, flags);
 drop_pkt:
         tq->stats.drop_total++;
         dev_kfree_skb(skb);
@@ -1020,7 +1066,10 @@ vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
 {
         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
 
-        return vmxnet3_tq_xmit(skb, &adapter->tx_queue, adapter, netdev);
+                BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
+                return vmxnet3_tq_xmit(skb,
+                                       &adapter->tx_queue[skb->queue_mapping],
+                                       adapter, netdev);
 }
 
 
@@ -1082,7 +1131,9 @@ static int
 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
                        struct vmxnet3_adapter *adapter, int quota)
 {
-        static u32 rxprod_reg[2] = {VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2};
+        static const u32 rxprod_reg[2] = {
+                VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
+        };
         u32 num_rxd = 0;
         struct Vmxnet3_RxCompDesc *rcd;
         struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
@@ -1106,9 +1157,9 @@ vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
                         break;
                 }
                 num_rxd++;
-
+                BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
                 idx = rcd->rxdIdx;
-                ring_idx = rcd->rqID == rq->qid ? 0 : 1;
+                ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
                 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
                                   &rxCmdDesc);
                 rbi = rq->buf_info[ring_idx] + idx;
@@ -1260,6 +1311,16 @@ vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
 }
 
 
+static void
+vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
+{
+        int i;
+
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
+}
+
+
 void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
                         struct vmxnet3_adapter *adapter)
 {
@@ -1351,6 +1412,25 @@ vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
 
 
 static int
+vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
+{
+        int i, err = 0;
+
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
+                if (unlikely(err)) {
+                        dev_err(&adapter->netdev->dev, "%s: failed to "
+                                "initialize rx queue%i\n",
+                                adapter->netdev->name, i);
+                        break;
+                }
+        }
+        return err;
+
+}
+
+
+static int
 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
 {
         int i;
@@ -1398,33 +1478,177 @@ err:
 
 
 static int
+vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
+{
+        int i, err = 0;
+
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
+                if (unlikely(err)) {
+                        dev_err(&adapter->netdev->dev,
+                                "%s: failed to create rx queue%i\n",
+                                adapter->netdev->name, i);
+                        goto err_out;
+                }
+        }
+        return err;
+err_out:
+        vmxnet3_rq_destroy_all(adapter);
+        return err;
+
+}
+
+/* Multiple queue aware polling function for tx and rx */
+
+static int
 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
 {
+        int rcd_done = 0, i;
         if (unlikely(adapter->shared->ecr))
                 vmxnet3_process_events(adapter);
+        for (i = 0; i < adapter->num_tx_queues; i++)
+                vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
 
-        vmxnet3_tq_tx_complete(&adapter->tx_queue, adapter);
-        return vmxnet3_rq_rx_complete(&adapter->rx_queue, adapter, budget);
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
+                                                   adapter, budget);
+        return rcd_done;
 }
 
 
 static int
 vmxnet3_poll(struct napi_struct *napi, int budget)
 {
-        struct vmxnet3_adapter *adapter = container_of(napi,
-                                          struct vmxnet3_adapter, napi);
+        struct vmxnet3_rx_queue *rx_queue = container_of(napi,
+                                          struct vmxnet3_rx_queue, napi);
+        int rxd_done;
+
+        rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
+
+        if (rxd_done < budget) {
+                napi_complete(napi);
+                vmxnet3_enable_all_intrs(rx_queue->adapter);
+        }
+        return rxd_done;
+}
+
+/*
+ * NAPI polling function for MSI-X mode with multiple Rx queues
+ * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
+ */
+
+static int
+vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
+{
+        struct vmxnet3_rx_queue *rq = container_of(napi,
+                                                struct vmxnet3_rx_queue, napi);
+        struct vmxnet3_adapter *adapter = rq->adapter;
         int rxd_done;
 
-        rxd_done = vmxnet3_do_poll(adapter, budget);
+        /* When sharing interrupt with corresponding tx queue, process
+         * tx completions in that queue as well
+         */
+        if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
+                struct vmxnet3_tx_queue *tq =
+                                &adapter->tx_queue[rq - adapter->rx_queue];
+                vmxnet3_tq_tx_complete(tq, adapter);
+        }
+
+        rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
 
         if (rxd_done < budget) {
                 napi_complete(napi);
-                vmxnet3_enable_intr(adapter, 0);
+                vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
         }
         return rxd_done;
 }
 
 
+#ifdef CONFIG_PCI_MSI
+
+/*
+ * Handle completion interrupts on tx queues
+ * Returns whether or not the intr is handled
+ */
+
+static irqreturn_t
+vmxnet3_msix_tx(int irq, void *data)
+{
+        struct vmxnet3_tx_queue *tq = data;
+        struct vmxnet3_adapter *adapter = tq->adapter;
+
+        if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
+                vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
+
+        /* Handle the case where only one irq is allocate for all tx queues */
+        if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
+                int i;
+                for (i = 0; i < adapter->num_tx_queues; i++) {
+                        struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
+                        vmxnet3_tq_tx_complete(txq, adapter);
+                }
+        } else {
+                vmxnet3_tq_tx_complete(tq, adapter);
+        }
+        vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
+
+        return IRQ_HANDLED;
+}
+
+
+/*
+ * Handle completion interrupts on rx queues. Returns whether or not the
+ * intr is handled
+ */
+
+static irqreturn_t
+vmxnet3_msix_rx(int irq, void *data)
+{
+        struct vmxnet3_rx_queue *rq = data;
+        struct vmxnet3_adapter *adapter = rq->adapter;
+
+        /* disable intr if needed */
+        if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
+                vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
+        napi_schedule(&rq->napi);
+
+        return IRQ_HANDLED;
+}
+
+/*
+ *----------------------------------------------------------------------------
+ *
+ * vmxnet3_msix_event --
+ *
+ *    vmxnet3 msix event intr handler
+ *
+ * Result:
+ *    whether or not the intr is handled
+ *
+ *----------------------------------------------------------------------------
+ */
+
+static irqreturn_t
+vmxnet3_msix_event(int irq, void *data)
+{
+        struct net_device *dev = data;
+        struct vmxnet3_adapter *adapter = netdev_priv(dev);
+
+        /* disable intr if needed */
+        if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
+                vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
+
+        if (adapter->shared->ecr)
+                vmxnet3_process_events(adapter);
+
+        vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
+
+        return IRQ_HANDLED;
+}
+
+#endif /* CONFIG_PCI_MSI  */
+
+
 /* Interrupt handler for vmxnet3  */
 static irqreturn_t
 vmxnet3_intr(int irq, void *dev_id)
@@ -1432,7 +1656,7 @@ vmxnet3_intr(int irq, void *dev_id)
         struct net_device *dev = dev_id;
         struct vmxnet3_adapter *adapter = netdev_priv(dev);
 
-        if (unlikely(adapter->intr.type == VMXNET3_IT_INTX)) {
+        if (adapter->intr.type == VMXNET3_IT_INTX) {
                 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
                 if (unlikely(icr == 0))
                         /* not ours */
@@ -1442,77 +1666,144 @@ vmxnet3_intr(int irq, void *dev_id)
 
         /* disable intr if needed */
         if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
-                vmxnet3_disable_intr(adapter, 0);
+                vmxnet3_disable_all_intrs(adapter);
 
-        napi_schedule(&adapter->napi);
+        napi_schedule(&adapter->rx_queue[0].napi);
 
         return IRQ_HANDLED;
 }
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
 
-
 /* netpoll callback. */
 static void
 vmxnet3_netpoll(struct net_device *netdev)
 {
         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
-        int irq;
 
-#ifdef CONFIG_PCI_MSI
-        if (adapter->intr.type == VMXNET3_IT_MSIX)
-                irq = adapter->intr.msix_entries[0].vector;
-        else
-#endif
-                irq = adapter->pdev->irq;
+        if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
+                vmxnet3_disable_all_intrs(adapter);
+
+        vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
+        vmxnet3_enable_all_intrs(adapter);
 
-        disable_irq(irq);
-        vmxnet3_intr(irq, netdev);
-        enable_irq(irq);
 }
-#endif
+#endif  /* CONFIG_NET_POLL_CONTROLLER */
 
 static int
 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
 {
-        int err;
+        struct vmxnet3_intr *intr = &adapter->intr;
+        int err = 0, i;
+        int vector = 0;
 
 #ifdef CONFIG_PCI_MSI
         if (adapter->intr.type == VMXNET3_IT_MSIX) {
-                /* we only use 1 MSI-X vector */
-                err = request_irq(adapter->intr.msix_entries[0].vector,
-                                  vmxnet3_intr, 0, adapter->netdev->name,
-                                  adapter->netdev);
-        } else if (adapter->intr.type == VMXNET3_IT_MSI) {
+                for (i = 0; i < adapter->num_tx_queues; i++) {
+                        if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
+                                sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
+                                        adapter->netdev->name, vector);
+                                err = request_irq(
+                                              intr->msix_entries[vector].vector,
+                                              vmxnet3_msix_tx, 0,
+                                              adapter->tx_queue[i].name,
+                                              &adapter->tx_queue[i]);
+                        } else {
+                                sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
+                                        adapter->netdev->name, vector);
+                        }
+                        if (err) {
+                                dev_err(&adapter->netdev->dev,
+                                        "Failed to request irq for MSIX, %s, "
+                                        "error %d\n",
+                                        adapter->tx_queue[i].name, err);
+                                return err;
+                        }
+
+                        /* Handle the case where only 1 MSIx was allocated for
+                         * all tx queues */
+                        if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
+                                for (; i < adapter->num_tx_queues; i++)
+                                        adapter->tx_queue[i].comp_ring.intr_idx
+                                                                = vector;
+                                vector++;
+                                break;
+                        } else {
+                                adapter->tx_queue[i].comp_ring.intr_idx
+                                                                = vector++;
+                        }
+                }
+                if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
+                        vector = 0;
+
+                for (i = 0; i < adapter->num_rx_queues; i++) {
+                        if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
+                                sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
+                                        adapter->netdev->name, vector);
+                        else
+                                sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
+                                        adapter->netdev->name, vector);
+                        err = request_irq(intr->msix_entries[vector].vector,
+                                          vmxnet3_msix_rx, 0,
+                                          adapter->rx_queue[i].name,
+                                          &(adapter->rx_queue[i]));
+                        if (err) {
+                                printk(KERN_ERR "Failed to request irq for MSIX"
+                                       ", %s, error %d\n",
+                                       adapter->rx_queue[i].name, err);
+                                return err;
+                        }
+
+                        adapter->rx_queue[i].comp_ring.intr_idx = vector++;
+                }
+
+                sprintf(intr->event_msi_vector_name, "%s-event-%d",
+                        adapter->netdev->name, vector);
+                err = request_irq(intr->msix_entries[vector].vector,
+                                  vmxnet3_msix_event, 0,
+                                  intr->event_msi_vector_name, adapter->netdev);
+                intr->event_intr_idx = vector;
+
+        } else if (intr->type == VMXNET3_IT_MSI) {
+                adapter->num_rx_queues = 1;
                 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
                                   adapter->netdev->name, adapter->netdev);
-        } else
+        } else {
 #endif
-        {
+                adapter->num_rx_queues = 1;
                 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
                                   IRQF_SHARED, adapter->netdev->name,
                                   adapter->netdev);
+#ifdef CONFIG_PCI_MSI
         }
-
-        if (err)
+#endif
+        intr->num_intrs = vector + 1;
+        if (err) {
                 printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
-                       ":%d\n", adapter->netdev->name, adapter->intr.type, err);
+                       ":%d\n", adapter->netdev->name, intr->type, err);
+        } else {
+                /* Number of rx queues will not change after this */
+                for (i = 0; i < adapter->num_rx_queues; i++) {
+                        struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
+                        rq->qid = i;
+                        rq->qid2 = i + adapter->num_rx_queues;
+                }
 
 
-        if (!err) {
-                int i;
-                /* init our intr settings */
-                for (i = 0; i < adapter->intr.num_intrs; i++)
-                        adapter->intr.mod_levels[i] = UPT1_IML_ADAPTIVE;
 
-                /* next setup intr index for all intr sources */
-                adapter->tx_queue.comp_ring.intr_idx = 0;
-                adapter->rx_queue.comp_ring.intr_idx = 0;
-                adapter->intr.event_intr_idx = 0;
+                /* init our intr settings */
+                for (i = 0; i < intr->num_intrs; i++)
+                        intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
+                if (adapter->intr.type != VMXNET3_IT_MSIX) {
+                        adapter->intr.event_intr_idx = 0;
+                        for (i = 0; i < adapter->num_tx_queues; i++)
+                                adapter->tx_queue[i].comp_ring.intr_idx = 0;
+                        adapter->rx_queue[0].comp_ring.intr_idx = 0;
+                }
 
                 printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
-                       "allocated\n", adapter->netdev->name, adapter->intr.type,
-                       adapter->intr.mask_mode, adapter->intr.num_intrs);
+                       "allocated\n", adapter->netdev->name, intr->type,
+                       intr->mask_mode, intr->num_intrs);
         }
 
         return err;
@@ -1522,18 +1813,32 @@ vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
 static void
 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
 {
-        BUG_ON(adapter->intr.type == VMXNET3_IT_AUTO ||
-               adapter->intr.num_intrs <= 0);
+        struct vmxnet3_intr *intr = &adapter->intr;
+        BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
 
-        switch (adapter->intr.type) {
+        switch (intr->type) {
 #ifdef CONFIG_PCI_MSI
         case VMXNET3_IT_MSIX:
         {
-                int i;
+                int i, vector = 0;
+
+                if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
+                        for (i = 0; i < adapter->num_tx_queues; i++) {
+                                free_irq(intr->msix_entries[vector++].vector,
+                                         &(adapter->tx_queue[i]));
+                                if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
+                                        break;
+                        }
+                }
 
-                for (i = 0; i < adapter->intr.num_intrs; i++)
-                        free_irq(adapter->intr.msix_entries[i].vector,
-                                 adapter->netdev);
+                for (i = 0; i < adapter->num_rx_queues; i++) {
+                        free_irq(intr->msix_entries[vector++].vector,
+                                 &(adapter->rx_queue[i]));
+                }
+
+                free_irq(intr->msix_entries[vector].vector,
+                         adapter->netdev);
+                BUG_ON(vector >= intr->num_intrs);
                 break;
         }
 #endif
@@ -1727,6 +2032,15 @@ vmxnet3_set_mc(struct net_device *netdev)
         kfree(new_table);
 }
 
+void
+vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
+{
+        int i;
+
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
+}
+
 
 /*
  *   Set up driver_shared based on settings in adapter.
@@ -1774,40 +2088,72 @@ vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
         devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
         devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
         devRead->misc.queueDescLen = cpu_to_le32(
-                                     sizeof(struct Vmxnet3_TxQueueDesc) +
-                                     sizeof(struct Vmxnet3_RxQueueDesc));
+                adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
+                adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
 
         /* tx queue settings */
-        BUG_ON(adapter->tx_queue.tx_ring.base == NULL);
-
-        devRead->misc.numTxQueues = 1;
-        tqc = &adapter->tqd_start->conf;
-        tqc->txRingBasePA   = cpu_to_le64(adapter->tx_queue.tx_ring.basePA);
-        tqc->dataRingBasePA = cpu_to_le64(adapter->tx_queue.data_ring.basePA);
-        tqc->compRingBasePA = cpu_to_le64(adapter->tx_queue.comp_ring.basePA);
-        tqc->ddPA           = cpu_to_le64(virt_to_phys(
-                                                adapter->tx_queue.buf_info));
-        tqc->txRingSize     = cpu_to_le32(adapter->tx_queue.tx_ring.size);
-        tqc->dataRingSize   = cpu_to_le32(adapter->tx_queue.data_ring.size);
-        tqc->compRingSize   = cpu_to_le32(adapter->tx_queue.comp_ring.size);
-        tqc->ddLen          = cpu_to_le32(sizeof(struct vmxnet3_tx_buf_info) *
-                              tqc->txRingSize);
-        tqc->intrIdx        = adapter->tx_queue.comp_ring.intr_idx;
+        devRead->misc.numTxQueues =  adapter->num_tx_queues;
+        for (i = 0; i < adapter->num_tx_queues; i++) {
+                struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
+                BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
+                tqc = &adapter->tqd_start[i].conf;
+                tqc->txRingBasePA   = cpu_to_le64(tq->tx_ring.basePA);
+                tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
+                tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
+                tqc->ddPA           = cpu_to_le64(virt_to_phys(tq->buf_info));
+                tqc->txRingSize     = cpu_to_le32(tq->tx_ring.size);
+                tqc->dataRingSize   = cpu_to_le32(tq->data_ring.size);
+                tqc->compRingSize   = cpu_to_le32(tq->comp_ring.size);
+                tqc->ddLen          = cpu_to_le32(
+                                        sizeof(struct vmxnet3_tx_buf_info) *
+                                        tqc->txRingSize);
+                tqc->intrIdx        = tq->comp_ring.intr_idx;
+        }
 
         /* rx queue settings */
-        devRead->misc.numRxQueues = 1;
-        rqc = &adapter->rqd_start->conf;
-        rqc->rxRingBasePA[0] = cpu_to_le64(adapter->rx_queue.rx_ring[0].basePA);
-        rqc->rxRingBasePA[1] = cpu_to_le64(adapter->rx_queue.rx_ring[1].basePA);
-        rqc->compRingBasePA  = cpu_to_le64(adapter->rx_queue.comp_ring.basePA);
-        rqc->ddPA            = cpu_to_le64(virt_to_phys(
-                                                adapter->rx_queue.buf_info));
-        rqc->rxRingSize[0]   = cpu_to_le32(adapter->rx_queue.rx_ring[0].size);
-        rqc->rxRingSize[1]   = cpu_to_le32(adapter->rx_queue.rx_ring[1].size);
-        rqc->compRingSize    = cpu_to_le32(adapter->rx_queue.comp_ring.size);
-        rqc->ddLen           = cpu_to_le32(sizeof(struct vmxnet3_rx_buf_info) *
-                               (rqc->rxRingSize[0] + rqc->rxRingSize[1]));
-        rqc->intrIdx         = adapter->rx_queue.comp_ring.intr_idx;
+        devRead->misc.numRxQueues = adapter->num_rx_queues;
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
+                rqc = &adapter->rqd_start[i].conf;
+                rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
+                rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
+                rqc->compRingBasePA  = cpu_to_le64(rq->comp_ring.basePA);
+                rqc->ddPA            = cpu_to_le64(virt_to_phys(
+                                                        rq->buf_info));
+                rqc->rxRingSize[0]   = cpu_to_le32(rq->rx_ring[0].size);
+                rqc->rxRingSize[1]   = cpu_to_le32(rq->rx_ring[1].size);
+                rqc->compRingSize    = cpu_to_le32(rq->comp_ring.size);
+                rqc->ddLen           = cpu_to_le32(
+                                        sizeof(struct vmxnet3_rx_buf_info) *
+                                        (rqc->rxRingSize[0] +
+                                         rqc->rxRingSize[1]));
+                rqc->intrIdx         = rq->comp_ring.intr_idx;
+        }
+
+#ifdef VMXNET3_RSS
+        memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
+
+        if (adapter->rss) {
+                struct UPT1_RSSConf *rssConf = adapter->rss_conf;
+                devRead->misc.uptFeatures |= UPT1_F_RSS;
+                devRead->misc.numRxQueues = adapter->num_rx_queues;
+                rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
+                                    UPT1_RSS_HASH_TYPE_IPV4 |
+                                    UPT1_RSS_HASH_TYPE_TCP_IPV6 |
+                                    UPT1_RSS_HASH_TYPE_IPV6;
+                rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
+                rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
+                rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
+                get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
+                for (i = 0; i < rssConf->indTableSize; i++)
+                        rssConf->indTable[i] = i % adapter->num_rx_queues;
+
+                devRead->rssConfDesc.confVer = 1;
+                devRead->rssConfDesc.confLen = sizeof(*rssConf);
+                devRead->rssConfDesc.confPA  = virt_to_phys(rssConf);
+        }
+
+#endif /* VMXNET3_RSS */
 
         /* intr settings */
         devRead->intrConf.autoMask = adapter->intr.mask_mode ==
@@ -1829,18 +2175,18 @@ vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
 int
 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
 {
-        int err;
+        int err, i;
         u32 ret;
 
-        dev_dbg(&adapter->netdev->dev,
-                "%s: skb_buf_size %d, rx_buf_per_pkt %d, ring sizes"
-                " %u %u %u\n", adapter->netdev->name, adapter->skb_buf_size,
-                adapter->rx_buf_per_pkt, adapter->tx_queue.tx_ring.size,
-                adapter->rx_queue.rx_ring[0].size,
-                adapter->rx_queue.rx_ring[1].size);
-
-        vmxnet3_tq_init(&adapter->tx_queue, adapter);
-        err = vmxnet3_rq_init(&adapter->rx_queue, adapter);
+        dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
+                " ring sizes %u %u %u\n", adapter->netdev->name,
+                adapter->skb_buf_size, adapter->rx_buf_per_pkt,
+                adapter->tx_queue[0].tx_ring.size,
+                adapter->rx_queue[0].rx_ring[0].size,
+                adapter->rx_queue[0].rx_ring[1].size);
+
+        vmxnet3_tq_init_all(adapter);
+        err = vmxnet3_rq_init_all(adapter);
         if (err) {
                 printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
                        adapter->netdev->name, err);
@@ -1870,10 +2216,15 @@ vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
                 err = -EINVAL;
                 goto activate_err;
         }
-        VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_RXPROD,
-                               adapter->rx_queue.rx_ring[0].next2fill);
-        VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_RXPROD2,
-                               adapter->rx_queue.rx_ring[1].next2fill);
+
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                VMXNET3_WRITE_BAR0_REG(adapter,
+                                VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
+                                adapter->rx_queue[i].rx_ring[0].next2fill);
+                VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
+                                (i * VMXNET3_REG_ALIGN)),
+                                adapter->rx_queue[i].rx_ring[1].next2fill);
+        }
 
         /* Apply the rx filter settins last. */
         vmxnet3_set_mc(adapter->netdev);
@@ -1883,8 +2234,8 @@ vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
          * tx queue if the link is up.
          */
         vmxnet3_check_link(adapter, true);
-
-        napi_enable(&adapter->napi);
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                napi_enable(&adapter->rx_queue[i].napi);
         vmxnet3_enable_all_intrs(adapter);
         clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
         return 0;
@@ -1896,7 +2247,7 @@ activate_err:
 irq_err:
 rq_err:
         /* free up buffers we allocated */
-        vmxnet3_rq_cleanup(&adapter->rx_queue, adapter);
+        vmxnet3_rq_cleanup_all(adapter);
         return err;
 }
 
@@ -1911,6 +2262,7 @@ vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
 int
 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
 {
+        int i;
         if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
                 return 0;
 
@@ -1919,13 +2271,14 @@ vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
                                VMXNET3_CMD_QUIESCE_DEV);
         vmxnet3_disable_all_intrs(adapter);
 
-        napi_disable(&adapter->napi);
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                napi_disable(&adapter->rx_queue[i].napi);
         netif_tx_disable(adapter->netdev);
         adapter->link_speed = 0;
         netif_carrier_off(adapter->netdev);
 
-        vmxnet3_tq_cleanup(&adapter->tx_queue, adapter);
-        vmxnet3_rq_cleanup(&adapter->rx_queue, adapter);
+        vmxnet3_tq_cleanup_all(adapter);
+        vmxnet3_rq_cleanup_all(adapter);
         vmxnet3_free_irqs(adapter);
         return 0;
 }
@@ -2047,7 +2400,9 @@ vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
 static void
 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
 {
-        size_t sz;
+        size_t sz, i, ring0_size, ring1_size, comp_size;
+        struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
+
 
         if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
                                     VMXNET3_MAX_ETH_HDR_SIZE) {
@@ -2069,11 +2424,19 @@ vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
          * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
          */
         sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
-        adapter->rx_queue.rx_ring[0].size = (adapter->rx_queue.rx_ring[0].size +
-                                             sz - 1) / sz * sz;
-        adapter->rx_queue.rx_ring[0].size = min_t(u32,
-                                            adapter->rx_queue.rx_ring[0].size,
-                                            VMXNET3_RX_RING_MAX_SIZE / sz * sz);
+        ring0_size = adapter->rx_queue[0].rx_ring[0].size;
+        ring0_size = (ring0_size + sz - 1) / sz * sz;
+        ring0_size = min_t(u32, rq->rx_ring[0].size, VMXNET3_RX_RING_MAX_SIZE /
+                           sz * sz);
+        ring1_size = adapter->rx_queue[0].rx_ring[1].size;
+        comp_size = ring0_size + ring1_size;
+
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                rq = &adapter->rx_queue[i];
+                rq->rx_ring[0].size = ring0_size;
+                rq->rx_ring[1].size = ring1_size;
+                rq->comp_ring.size = comp_size;
+        }
 }
 
 
@@ -2081,29 +2444,53 @@ int
 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
                       u32 rx_ring_size, u32 rx_ring2_size)
 {
-        int err;
-
-        adapter->tx_queue.tx_ring.size   = tx_ring_size;
-        adapter->tx_queue.data_ring.size = tx_ring_size;
-        adapter->tx_queue.comp_ring.size = tx_ring_size;
-        adapter->tx_queue.shared = &adapter->tqd_start->ctrl;
-        adapter->tx_queue.stopped = true;
-        err = vmxnet3_tq_create(&adapter->tx_queue, adapter);
-        if (err)
-                return err;
+        int err = 0, i;
+
+        for (i = 0; i < adapter->num_tx_queues; i++) {
+                struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
+                tq->tx_ring.size   = tx_ring_size;
+                tq->data_ring.size = tx_ring_size;
+                tq->comp_ring.size = tx_ring_size;
+                tq->shared = &adapter->tqd_start[i].ctrl;
+                tq->stopped = true;
+                tq->adapter = adapter;
+                tq->qid = i;
+                err = vmxnet3_tq_create(tq, adapter);
+                /*
+                 * Too late to change num_tx_queues. We cannot do away with
+                 * lesser number of queues than what we asked for
+                 */
+                if (err)
+                        goto queue_err;
+        }
 
-        adapter->rx_queue.rx_ring[0].size = rx_ring_size;
-        adapter->rx_queue.rx_ring[1].size = rx_ring2_size;
+        adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
+        adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
         vmxnet3_adjust_rx_ring_size(adapter);
-        adapter->rx_queue.comp_ring.size  = adapter->rx_queue.rx_ring[0].size +
-                                            adapter->rx_queue.rx_ring[1].size;
-        adapter->rx_queue.qid  = 0;
-        adapter->rx_queue.qid2 = 1;
-        adapter->rx_queue.shared = &adapter->rqd_start->ctrl;
-        err = vmxnet3_rq_create(&adapter->rx_queue, adapter);
-        if (err)
-                vmxnet3_tq_destroy(&adapter->tx_queue, adapter);
-
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
+                /* qid and qid2 for rx queues will be assigned later when num
+                 * of rx queues is finalized after allocating intrs */
+                rq->shared = &adapter->rqd_start[i].ctrl;
+                rq->adapter = adapter;
+                err = vmxnet3_rq_create(rq, adapter);
+                if (err) {
+                        if (i == 0) {
+                                printk(KERN_ERR "Could not allocate any rx"
+                                       "queues. Aborting.\n");
+                                goto queue_err;
+                        } else {
+                                printk(KERN_INFO "Number of rx queues changed "
+                                       "to : %d.\n", i);
+                                adapter->num_rx_queues = i;
+                                err = 0;
+                                break;
+                        }
+                }
+        }
+        return err;
+queue_err:
+        vmxnet3_tq_destroy_all(adapter);
         return err;
 }
 
@@ -2111,11 +2498,12 @@ static int
 vmxnet3_open(struct net_device *netdev)
 {
         struct vmxnet3_adapter *adapter;
-        int err;
+        int err, i;
 
         adapter = netdev_priv(netdev);
 
-        spin_lock_init(&adapter->tx_queue.tx_lock);
+        for (i = 0; i < adapter->num_tx_queues; i++)
+                spin_lock_init(&adapter->tx_queue[i].tx_lock);
 
         err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
                                     VMXNET3_DEF_RX_RING_SIZE,
@@ -2130,8 +2518,8 @@ vmxnet3_open(struct net_device *netdev)
         return 0;
 
 activate_err:
-        vmxnet3_rq_destroy(&adapter->rx_queue, adapter);
-        vmxnet3_tq_destroy(&adapter->tx_queue, adapter);
+        vmxnet3_rq_destroy_all(adapter);
+        vmxnet3_tq_destroy_all(adapter);
 queue_err:
         return err;
 }
@@ -2151,8 +2539,8 @@ vmxnet3_close(struct net_device *netdev)
 
         vmxnet3_quiesce_dev(adapter);
 
-        vmxnet3_rq_destroy(&adapter->rx_queue, adapter);
-        vmxnet3_tq_destroy(&adapter->tx_queue, adapter);
+        vmxnet3_rq_destroy_all(adapter);
+        vmxnet3_tq_destroy_all(adapter);
 
         clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
 
@@ -2164,6 +2552,8 @@ vmxnet3_close(struct net_device *netdev)
 void
 vmxnet3_force_close(struct vmxnet3_adapter *adapter)
 {
+        int i;
+
         /*
          * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
          * vmxnet3_close() will deadlock.
@@ -2171,7 +2561,8 @@ vmxnet3_force_close(struct vmxnet3_adapter *adapter)
         BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
 
         /* we need to enable NAPI, otherwise dev_close will deadlock */
-        napi_enable(&adapter->napi);
+        for (i = 0; i < adapter->num_rx_queues; i++)
+                napi_enable(&adapter->rx_queue[i].napi);
         dev_close(adapter->netdev);
 }
 
@@ -2202,14 +2593,11 @@ vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
                 vmxnet3_reset_dev(adapter);
 
                 /* we need to re-create the rx queue based on the new mtu */
-                vmxnet3_rq_destroy(&adapter->rx_queue, adapter);
+                vmxnet3_rq_destroy_all(adapter);
                 vmxnet3_adjust_rx_ring_size(adapter);
-                adapter->rx_queue.comp_ring.size  =
-                                        adapter->rx_queue.rx_ring[0].size +
-                                        adapter->rx_queue.rx_ring[1].size;
-                err = vmxnet3_rq_create(&adapter->rx_queue, adapter);
+                err = vmxnet3_rq_create_all(adapter);
                 if (err) {
-                        printk(KERN_ERR "%s: failed to re-create rx queue,"
+                        printk(KERN_ERR "%s: failed to re-create rx queues,"
                                 " error %d. Closing it.\n", netdev->name, err);
                         goto out;
                 }
@@ -2274,6 +2662,55 @@ vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
         mac[5] = (tmp >> 8) & 0xff;
 }
 
+#ifdef CONFIG_PCI_MSI
+
+/*
+ * Enable MSIx vectors.
+ * Returns :
+ *      0 on successful enabling of required vectors,
+ *      VMXNET3_LINUX_MIN_MSIX_VECT when only minumum number of vectors required
+ *       could be enabled.
+ *      number of vectors which can be enabled otherwise (this number is smaller
+ *       than VMXNET3_LINUX_MIN_MSIX_VECT)
+ */
+
+static int
+vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
+                             int vectors)
+{
+        int err = 0, vector_threshold;
+        vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
+
+        while (vectors >= vector_threshold) {
+                err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
+                                      vectors);
+                if (!err) {
+                        adapter->intr.num_intrs = vectors;
+                        return 0;
+                } else if (err < 0) {
+                        printk(KERN_ERR "Failed to enable MSI-X for %s, error"
+                               " %d\n", adapter->netdev->name, err);
+                        vectors = 0;
+                } else if (err < vector_threshold) {
+                        break;
+                } else {
+                        /* If fails to enable required number of MSI-x vectors
+                         * try enabling 3 of them. One each for rx, tx and event
+                         */
+                        vectors = vector_threshold;
+                        printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
+                               " %d instead\n", vectors, adapter->netdev->name,
+                               vector_threshold);
+                }
+        }
+
+        printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
+               " are lower than min threshold required.\n");
+        return err;
+}
+
+
+#endif /* CONFIG_PCI_MSI */
 
 static void
 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
@@ -2293,16 +2730,47 @@ vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
 
 #ifdef CONFIG_PCI_MSI
         if (adapter->intr.type == VMXNET3_IT_MSIX) {
-                int err;
-
-                adapter->intr.msix_entries[0].entry = 0;
-                err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
-                                      VMXNET3_LINUX_MAX_MSIX_VECT);
-                if (!err) {
-                        adapter->intr.num_intrs = 1;
-                        adapter->intr.type = VMXNET3_IT_MSIX;
+                int vector, err = 0;
+
+                adapter->intr.num_intrs = (adapter->share_intr ==
+                                           VMXNET3_INTR_TXSHARE) ? 1 :
+                                           adapter->num_tx_queues;
+                adapter->intr.num_intrs += (adapter->share_intr ==
+                                           VMXNET3_INTR_BUDDYSHARE) ? 0 :
+                                           adapter->num_rx_queues;
+                adapter->intr.num_intrs += 1;           /* for link event */
+
+                adapter->intr.num_intrs = (adapter->intr.num_intrs >
+                                           VMXNET3_LINUX_MIN_MSIX_VECT
+                                           ? adapter->intr.num_intrs :
+                                           VMXNET3_LINUX_MIN_MSIX_VECT);
+
+                for (vector = 0; vector < adapter->intr.num_intrs; vector++)
+                        adapter->intr.msix_entries[vector].entry = vector;
+
+                err = vmxnet3_acquire_msix_vectors(adapter,
+                                                   adapter->intr.num_intrs);
+                /* If we cannot allocate one MSIx vector per queue
+                 * then limit the number of rx queues to 1
+                 */
+                if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
+                        if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
+                            || adapter->num_rx_queues != 2) {
+                                adapter->share_intr = VMXNET3_INTR_TXSHARE;
+                                printk(KERN_ERR "Number of rx queues : 1\n");
+                                adapter->num_rx_queues = 1;
+                                adapter->intr.num_intrs =
+                                                VMXNET3_LINUX_MIN_MSIX_VECT;
+                        }
                         return;
                 }
+                if (!err)
+                        return;
+
+                /* If we cannot allocate MSIx vectors use only one rx queue */
+                printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
+                       "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
+
                 adapter->intr.type = VMXNET3_IT_MSI;
         }
 
@@ -2310,12 +2778,15 @@ vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
                 int err;
                 err = pci_enable_msi(adapter->pdev);
                 if (!err) {
+                        adapter->num_rx_queues = 1;
                         adapter->intr.num_intrs = 1;
                         return;
                 }
         }
 #endif /* CONFIG_PCI_MSI */
 
+        adapter->num_rx_queues = 1;
+        printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
         adapter->intr.type = VMXNET3_IT_INTX;
 
         /* INT-X related setting */
@@ -2343,6 +2814,7 @@ vmxnet3_tx_timeout(struct net_device *netdev)
 
         printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
         schedule_work(&adapter->work);
+        netif_wake_queue(adapter->netdev);
 }
 
 
@@ -2399,8 +2871,29 @@ vmxnet3_probe_device(struct pci_dev *pdev,
         struct net_device *netdev;
         struct vmxnet3_adapter *adapter;
         u8 mac[ETH_ALEN];
+        int size;
+        int num_tx_queues;
+        int num_rx_queues;
+
+#ifdef VMXNET3_RSS
+        if (enable_mq)
+                num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
+                                    (int)num_online_cpus());
+        else
+#endif
+                num_rx_queues = 1;
+
+        if (enable_mq)
+                num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
+                                    (int)num_online_cpus());
+        else
+                num_tx_queues = 1;
+
+        netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
+                                   max(num_tx_queues, num_rx_queues));
+        printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
+               num_tx_queues, num_rx_queues);
 
-        netdev = alloc_etherdev(sizeof(struct vmxnet3_adapter));
         if (!netdev) {
                 printk(KERN_ERR "Failed to alloc ethernet device for adapter "
                         "%s\n", pci_name(pdev));
@@ -2422,9 +2915,12 @@ vmxnet3_probe_device(struct pci_dev *pdev,
                 goto err_alloc_shared;
         }
 
-        adapter->tqd_start = pci_alloc_consistent(adapter->pdev,
-                             sizeof(struct Vmxnet3_TxQueueDesc) +
-                             sizeof(struct Vmxnet3_RxQueueDesc),
+        adapter->num_rx_queues = num_rx_queues;
+        adapter->num_tx_queues = num_tx_queues;
+
+        size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
+        size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
+        adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
                              &adapter->queue_desc_pa);
 
         if (!adapter->tqd_start) {
@@ -2433,8 +2929,8 @@ vmxnet3_probe_device(struct pci_dev *pdev,
                 err = -ENOMEM;
                 goto err_alloc_queue_desc;
         }
-        adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start
-                                                            + 1);
+        adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
+                                                        adapter->num_tx_queues);
 
         adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
         if (adapter->pm_conf == NULL) {
@@ -2444,6 +2940,17 @@ vmxnet3_probe_device(struct pci_dev *pdev,
                 goto err_alloc_pm;
         }
 
+#ifdef VMXNET3_RSS
+
+        adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
+        if (adapter->rss_conf == NULL) {
+                printk(KERN_ERR "Failed to allocate memory for %s\n",
+                       pci_name(pdev));
+                err = -ENOMEM;
+                goto err_alloc_rss;
+        }
+#endif /* VMXNET3_RSS */
+
         err = vmxnet3_alloc_pci_resources(adapter, &dma64);
         if (err < 0)
                 goto err_alloc_pci;
@@ -2471,18 +2978,48 @@ vmxnet3_probe_device(struct pci_dev *pdev,
         vmxnet3_declare_features(adapter, dma64);
 
         adapter->dev_number = atomic_read(&devices_found);
+
+         adapter->share_intr = irq_share_mode;
+        if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
+            adapter->num_tx_queues != adapter->num_rx_queues)
+                adapter->share_intr = VMXNET3_INTR_DONTSHARE;
+
         vmxnet3_alloc_intr_resources(adapter);
 
+#ifdef VMXNET3_RSS
+        if (adapter->num_rx_queues > 1 &&
+            adapter->intr.type == VMXNET3_IT_MSIX) {
+                adapter->rss = true;
+                printk(KERN_INFO "RSS is enabled.\n");
+        } else {
+                adapter->rss = false;
+        }
+#endif
+
         vmxnet3_read_mac_addr(adapter, mac);
         memcpy(netdev->dev_addr,  mac, netdev->addr_len);
 
         netdev->netdev_ops = &vmxnet3_netdev_ops;
-        netdev->watchdog_timeo = 5 * HZ;
         vmxnet3_set_ethtool_ops(netdev);
+        netdev->watchdog_timeo = 5 * HZ;
 
         INIT_WORK(&adapter->work, vmxnet3_reset_work);
 
-        netif_napi_add(netdev, &adapter->napi, vmxnet3_poll, 64);
+        if (adapter->intr.type == VMXNET3_IT_MSIX) {
+                int i;
+                for (i = 0; i < adapter->num_rx_queues; i++) {
+                        netif_napi_add(adapter->netdev,
+                                       &adapter->rx_queue[i].napi,
+                                       vmxnet3_poll_rx_only, 64);
+                }
+        } else {
+                netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
+                               vmxnet3_poll, 64);
+        }
+
+        netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
+        netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
+
         SET_NETDEV_DEV(netdev, &pdev->dev);
         err = register_netdev(netdev);
 
@@ -2502,11 +3039,14 @@ err_register:
 err_ver:
         vmxnet3_free_pci_resources(adapter);
 err_alloc_pci:
+#ifdef VMXNET3_RSS
+        kfree(adapter->rss_conf);
+err_alloc_rss:
+#endif
         kfree(adapter->pm_conf);
 err_alloc_pm:
-        pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_TxQueueDesc) +
-                            sizeof(struct Vmxnet3_RxQueueDesc),
-                            adapter->tqd_start, adapter->queue_desc_pa);
+        pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
+                            adapter->queue_desc_pa);
 err_alloc_queue_desc:
         pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
                             adapter->shared, adapter->shared_pa);
@@ -2522,17 +3062,32 @@ vmxnet3_remove_device(struct pci_dev *pdev)
 {
         struct net_device *netdev = pci_get_drvdata(pdev);
         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
+        int size = 0;
+        int num_rx_queues;
 
-        flush_scheduled_work();
+#ifdef VMXNET3_RSS
+        if (enable_mq)
+                num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
+                                    (int)num_online_cpus());
+        else
+#endif
+                num_rx_queues = 1;
+
+        cancel_work_sync(&adapter->work);
 
         unregister_netdev(netdev);
 
         vmxnet3_free_intr_resources(adapter);
         vmxnet3_free_pci_resources(adapter);
+#ifdef VMXNET3_RSS
+        kfree(adapter->rss_conf);
+#endif
         kfree(adapter->pm_conf);
-        pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_TxQueueDesc) +
-                            sizeof(struct Vmxnet3_RxQueueDesc),
-                            adapter->tqd_start, adapter->queue_desc_pa);
+
+        size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
+        size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
+        pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
+                            adapter->queue_desc_pa);
         pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
                             adapter->shared, adapter->shared_pa);
         free_netdev(netdev);
@@ -2563,7 +3118,7 @@ vmxnet3_suspend(struct device *device)
         vmxnet3_free_intr_resources(adapter);
 
         netif_device_detach(netdev);
-        netif_stop_queue(netdev);
+        netif_tx_stop_all_queues(netdev);
 
         /* Create wake-up filters. */
         pmConf = adapter->pm_conf;
diff --git a/drivers/net/vmxnet3/vmxnet3_ethtool.c b/drivers/net/vmxnet3/vmxnet3_ethtool.c
index b79070bcc92e..8e17fc8a7fe7 100644
--- a/drivers/net/vmxnet3/vmxnet3_ethtool.c
+++ b/drivers/net/vmxnet3/vmxnet3_ethtool.c
@@ -151,44 +151,42 @@ vmxnet3_get_stats(struct net_device *netdev)
         struct UPT1_TxStats *devTxStats;
         struct UPT1_RxStats *devRxStats;
         struct net_device_stats *net_stats = &netdev->stats;
+        int i;
 
         adapter = netdev_priv(netdev);
 
         /* Collect the dev stats into the shared area */
         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
 
-        /* Assuming that we have a single queue device */
-        devTxStats = &adapter->tqd_start->stats;
-        devRxStats = &adapter->rqd_start->stats;
-
-        /* Get access to the driver stats per queue */
-        drvTxStats = &adapter->tx_queue.stats;
-        drvRxStats = &adapter->rx_queue.stats;
-
         memset(net_stats, 0, sizeof(*net_stats));
+        for (i = 0; i < adapter->num_tx_queues; i++) {
+                devTxStats = &adapter->tqd_start[i].stats;
+                drvTxStats = &adapter->tx_queue[i].stats;
+                net_stats->tx_packets += devTxStats->ucastPktsTxOK +
+                                        devTxStats->mcastPktsTxOK +
+                                        devTxStats->bcastPktsTxOK;
+                net_stats->tx_bytes += devTxStats->ucastBytesTxOK +
+                                      devTxStats->mcastBytesTxOK +
+                                      devTxStats->bcastBytesTxOK;
+                net_stats->tx_errors += devTxStats->pktsTxError;
+                net_stats->tx_dropped += drvTxStats->drop_total;
+        }
 
-        net_stats->rx_packets = devRxStats->ucastPktsRxOK +
-                                devRxStats->mcastPktsRxOK +
-                                devRxStats->bcastPktsRxOK;
-
-        net_stats->tx_packets = devTxStats->ucastPktsTxOK +
-                                devTxStats->mcastPktsTxOK +
-                                devTxStats->bcastPktsTxOK;
-
-        net_stats->rx_bytes = devRxStats->ucastBytesRxOK +
-                              devRxStats->mcastBytesRxOK +
-                              devRxStats->bcastBytesRxOK;
-
-        net_stats->tx_bytes = devTxStats->ucastBytesTxOK +
-                              devTxStats->mcastBytesTxOK +
-                              devTxStats->bcastBytesTxOK;
+        for (i = 0; i < adapter->num_rx_queues; i++) {
+                devRxStats = &adapter->rqd_start[i].stats;
+                drvRxStats = &adapter->rx_queue[i].stats;
+                net_stats->rx_packets += devRxStats->ucastPktsRxOK +
+                                        devRxStats->mcastPktsRxOK +
+                                        devRxStats->bcastPktsRxOK;
 
-        net_stats->rx_errors = devRxStats->pktsRxError;
-        net_stats->tx_errors = devTxStats->pktsTxError;
-        net_stats->rx_dropped = drvRxStats->drop_total;
-        net_stats->tx_dropped = drvTxStats->drop_total;
-        net_stats->multicast =  devRxStats->mcastPktsRxOK;
+                net_stats->rx_bytes += devRxStats->ucastBytesRxOK +
+                                      devRxStats->mcastBytesRxOK +
+                                      devRxStats->bcastBytesRxOK;
 
+                net_stats->rx_errors += devRxStats->pktsRxError;
+                net_stats->rx_dropped += drvRxStats->drop_total;
+                net_stats->multicast +=  devRxStats->mcastPktsRxOK;
+        }
         return net_stats;
 }
 
@@ -307,24 +305,26 @@ vmxnet3_get_ethtool_stats(struct net_device *netdev,
         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
         u8 *base;
         int i;
+        int j = 0;
 
         VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);
 
         /* this does assume each counter is 64-bit wide */
+/* TODO change this for multiple queues */
 
-        base = (u8 *)&adapter->tqd_start->stats;
+        base = (u8 *)&adapter->tqd_start[j].stats;
         for (i = 0; i < ARRAY_SIZE(vmxnet3_tq_dev_stats); i++)
                 *buf++ = *(u64 *)(base + vmxnet3_tq_dev_stats[i].offset);
 
-        base = (u8 *)&adapter->tx_queue.stats;
+        base = (u8 *)&adapter->tx_queue[j].stats;
         for (i = 0; i < ARRAY_SIZE(vmxnet3_tq_driver_stats); i++)
                 *buf++ = *(u64 *)(base + vmxnet3_tq_driver_stats[i].offset);
 
-        base = (u8 *)&adapter->rqd_start->stats;
+        base = (u8 *)&adapter->rqd_start[j].stats;
         for (i = 0; i < ARRAY_SIZE(vmxnet3_rq_dev_stats); i++)
                 *buf++ = *(u64 *)(base + vmxnet3_rq_dev_stats[i].offset);
 
-        base = (u8 *)&adapter->rx_queue.stats;
+        base = (u8 *)&adapter->rx_queue[j].stats;
         for (i = 0; i < ARRAY_SIZE(vmxnet3_rq_driver_stats); i++)
                 *buf++ = *(u64 *)(base + vmxnet3_rq_driver_stats[i].offset);
 
@@ -339,6 +339,7 @@ vmxnet3_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
 {
         struct vmxnet3_adapter *adapter = netdev_priv(netdev);
         u32 *buf = p;
+        int i = 0;
 
         memset(p, 0, vmxnet3_get_regs_len(netdev));
 
@@ -347,28 +348,29 @@ vmxnet3_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
         /* Update vmxnet3_get_regs_len if we want to dump more registers */
 
         /* make each ring use multiple of 16 bytes */
-        buf[0] = adapter->tx_queue.tx_ring.next2fill;
-        buf[1] = adapter->tx_queue.tx_ring.next2comp;
-        buf[2] = adapter->tx_queue.tx_ring.gen;
+/* TODO change this for multiple queues */
+        buf[0] = adapter->tx_queue[i].tx_ring.next2fill;
+        buf[1] = adapter->tx_queue[i].tx_ring.next2comp;
+        buf[2] = adapter->tx_queue[i].tx_ring.gen;
         buf[3] = 0;
 
-        buf[4] = adapter->tx_queue.comp_ring.next2proc;
-        buf[5] = adapter->tx_queue.comp_ring.gen;
-        buf[6] = adapter->tx_queue.stopped;
+        buf[4] = adapter->tx_queue[i].comp_ring.next2proc;
+        buf[5] = adapter->tx_queue[i].comp_ring.gen;
+        buf[6] = adapter->tx_queue[i].stopped;
         buf[7] = 0;
 
-        buf[8] = adapter->rx_queue.rx_ring[0].next2fill;
-        buf[9] = adapter->rx_queue.rx_ring[0].next2comp;
-        buf[10] = adapter->rx_queue.rx_ring[0].gen;
+        buf[8] = adapter->rx_queue[i].rx_ring[0].next2fill;
+        buf[9] = adapter->rx_queue[i].rx_ring[0].next2comp;
+        buf[10] = adapter->rx_queue[i].rx_ring[0].gen;
         buf[11] = 0;
 
-        buf[12] = adapter->rx_queue.rx_ring[1].next2fill;
-        buf[13] = adapter->rx_queue.rx_ring[1].next2comp;
-        buf[14] = adapter->rx_queue.rx_ring[1].gen;
+        buf[12] = adapter->rx_queue[i].rx_ring[1].next2fill;
+        buf[13] = adapter->rx_queue[i].rx_ring[1].next2comp;
+        buf[14] = adapter->rx_queue[i].rx_ring[1].gen;
         buf[15] = 0;
 
-        buf[16] = adapter->rx_queue.comp_ring.next2proc;
-        buf[17] = adapter->rx_queue.comp_ring.gen;
+        buf[16] = adapter->rx_queue[i].comp_ring.next2proc;
+        buf[17] = adapter->rx_queue[i].comp_ring.gen;
         buf[18] = 0;
         buf[19] = 0;
 }
@@ -435,8 +437,10 @@ vmxnet3_get_ringparam(struct net_device *netdev,
         param->rx_mini_max_pending = 0;
         param->rx_jumbo_max_pending = 0;
 
-        param->rx_pending = adapter->rx_queue.rx_ring[0].size;
-        param->tx_pending = adapter->tx_queue.tx_ring.size;
+        param->rx_pending = adapter->rx_queue[0].rx_ring[0].size *
+                            adapter->num_rx_queues;
+        param->tx_pending = adapter->tx_queue[0].tx_ring.size *
+                            adapter->num_tx_queues;
         param->rx_mini_pending = 0;
         param->rx_jumbo_pending = 0;
 }
@@ -480,8 +484,8 @@ vmxnet3_set_ringparam(struct net_device *netdev,
                                                            sz) != 0)
                 return -EINVAL;
 
-        if (new_tx_ring_size == adapter->tx_queue.tx_ring.size &&
-                        new_rx_ring_size == adapter->rx_queue.rx_ring[0].size) {
+        if (new_tx_ring_size == adapter->tx_queue[0].tx_ring.size &&
+            new_rx_ring_size == adapter->rx_queue[0].rx_ring[0].size) {
                 return 0;
         }
 
@@ -498,11 +502,12 @@ vmxnet3_set_ringparam(struct net_device *netdev,
 
                 /* recreate the rx queue and the tx queue based on the
                  * new sizes */
-                vmxnet3_tq_destroy(&adapter->tx_queue, adapter);
-                vmxnet3_rq_destroy(&adapter->rx_queue, adapter);
+                vmxnet3_tq_destroy_all(adapter);
+                vmxnet3_rq_destroy_all(adapter);
 
                 err = vmxnet3_create_queues(adapter, new_tx_ring_size,
                         new_rx_ring_size, VMXNET3_DEF_RX_RING_SIZE);
+
                 if (err) {
                         /* failed, most likely because of OOM, try default
                          * size */
@@ -535,6 +540,66 @@ out:
 }
 
 
+static int
+vmxnet3_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *info,
+                  void *rules)
+{
+        struct vmxnet3_adapter *adapter = netdev_priv(netdev);
+        switch (info->cmd) {
+        case ETHTOOL_GRXRINGS:
+                info->data = adapter->num_rx_queues;
+                return 0;
+        }
+        return -EOPNOTSUPP;
+}
+
+#ifdef VMXNET3_RSS
+static int
+vmxnet3_get_rss_indir(struct net_device *netdev,
+                      struct ethtool_rxfh_indir *p)
+{
+        struct vmxnet3_adapter *adapter = netdev_priv(netdev);
+        struct UPT1_RSSConf *rssConf = adapter->rss_conf;
+        unsigned int n = min_t(unsigned int, p->size, rssConf->indTableSize);
+
+        p->size = rssConf->indTableSize;
+        while (n--)
+                p->ring_index[n] = rssConf->indTable[n];
+        return 0;
+
+}
+
+static int
+vmxnet3_set_rss_indir(struct net_device *netdev,
+                      const struct ethtool_rxfh_indir *p)
+{
+        unsigned int i;
+        struct vmxnet3_adapter *adapter = netdev_priv(netdev);
+        struct UPT1_RSSConf *rssConf = adapter->rss_conf;
+
+        if (p->size != rssConf->indTableSize)
+                return -EINVAL;
+        for (i = 0; i < rssConf->indTableSize; i++) {
+                /*
+                 * Return with error code if any of the queue indices
+                 * is out of range
+                 */
+                if (p->ring_index[i] < 0 ||
+                    p->ring_index[i] >= adapter->num_rx_queues)
+                        return -EINVAL;
+        }
+
+        for (i = 0; i < rssConf->indTableSize; i++)
+                rssConf->indTable[i] = p->ring_index[i];
+
+        VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
+                               VMXNET3_CMD_UPDATE_RSSIDT);
+
+        return 0;
+
+}
+#endif
+
 static struct ethtool_ops vmxnet3_ethtool_ops = {
         .get_settings      = vmxnet3_get_settings,
         .get_drvinfo       = vmxnet3_get_drvinfo,
@@ -558,6 +623,11 @@ static struct ethtool_ops vmxnet3_ethtool_ops = {
         .get_ethtool_stats = vmxnet3_get_ethtool_stats,
         .get_ringparam     = vmxnet3_get_ringparam,
         .set_ringparam     = vmxnet3_set_ringparam,
+        .get_rxnfc         = vmxnet3_get_rxnfc,
+#ifdef VMXNET3_RSS
+        .get_rxfh_indir    = vmxnet3_get_rss_indir,
+        .set_rxfh_indir    = vmxnet3_set_rss_indir,
+#endif
 };
 
 void vmxnet3_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/vmxnet3/vmxnet3_int.h b/drivers/net/vmxnet3/vmxnet3_int.h
index edf228843afc..7fadeed37f03 100644
--- a/drivers/net/vmxnet3/vmxnet3_int.h
+++ b/drivers/net/vmxnet3/vmxnet3_int.h
@@ -68,11 +68,15 @@
 /*
  * Version numbers
  */
-#define VMXNET3_DRIVER_VERSION_STRING   "1.0.14.0-k"
+#define VMXNET3_DRIVER_VERSION_STRING   "1.0.16.0-k"
 
 /* a 32-bit int, each byte encode a verion number in VMXNET3_DRIVER_VERSION */
-#define VMXNET3_DRIVER_VERSION_NUM      0x01000E00
+#define VMXNET3_DRIVER_VERSION_NUM      0x01001000
 
+#if defined(CONFIG_PCI_MSI)
+        /* RSS only makes sense if MSI-X is supported. */
+        #define VMXNET3_RSS
+#endif
 
 /*
  * Capabilities
@@ -218,16 +222,19 @@ struct vmxnet3_tx_ctx {
 };
 
 struct vmxnet3_tx_queue {
+        char                    name[IFNAMSIZ+8]; /* To identify interrupt */
+        struct vmxnet3_adapter          *adapter;
         spinlock_t                      tx_lock;
         struct vmxnet3_cmd_ring         tx_ring;
-        struct vmxnet3_tx_buf_info     *buf_info;
+        struct vmxnet3_tx_buf_info      *buf_info;
         struct vmxnet3_tx_data_ring     data_ring;
         struct vmxnet3_comp_ring        comp_ring;
-        struct Vmxnet3_TxQueueCtrl            *shared;
+        struct Vmxnet3_TxQueueCtrl      *shared;
         struct vmxnet3_tq_driver_stats  stats;
         bool                            stopped;
         int                             num_stop;  /* # of times the queue is
                                                     * stopped */
+        int                             qid;
 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
 enum vmxnet3_rx_buf_type {
@@ -259,6 +266,9 @@ struct vmxnet3_rq_driver_stats {
 };
 
 struct vmxnet3_rx_queue {
+        char                    name[IFNAMSIZ + 8]; /* To identify interrupt */
+        struct vmxnet3_adapter    *adapter;
+        struct napi_struct        napi;
         struct vmxnet3_cmd_ring   rx_ring[2];
         struct vmxnet3_comp_ring  comp_ring;
         struct vmxnet3_rx_ctx     rx_ctx;
@@ -271,7 +281,16 @@ struct vmxnet3_rx_queue {
         struct vmxnet3_rq_driver_stats  stats;
 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
-#define VMXNET3_LINUX_MAX_MSIX_VECT     1
+#define VMXNET3_DEVICE_MAX_TX_QUEUES 8
+#define VMXNET3_DEVICE_MAX_RX_QUEUES 8   /* Keep this value as a power of 2 */
+
+/* Should be less than UPT1_RSS_MAX_IND_TABLE_SIZE */
+#define VMXNET3_RSS_IND_TABLE_SIZE (VMXNET3_DEVICE_MAX_RX_QUEUES * 4)
+
+#define VMXNET3_LINUX_MAX_MSIX_VECT     (VMXNET3_DEVICE_MAX_TX_QUEUES + \
+                                         VMXNET3_DEVICE_MAX_RX_QUEUES + 1)
+#define VMXNET3_LINUX_MIN_MSIX_VECT     3    /* 1 for each : tx, rx and event */
+
 
 struct vmxnet3_intr {
         enum vmxnet3_intr_mask_mode  mask_mode;
@@ -279,27 +298,32 @@ struct vmxnet3_intr {
         u8  num_intrs;                  /* # of intr vectors */
         u8  event_intr_idx;             /* idx of the intr vector for event */
         u8  mod_levels[VMXNET3_LINUX_MAX_MSIX_VECT]; /* moderation level */
+        char    event_msi_vector_name[IFNAMSIZ+11];
 #ifdef CONFIG_PCI_MSI
         struct msix_entry msix_entries[VMXNET3_LINUX_MAX_MSIX_VECT];
 #endif
 };
 
+/* Interrupt sharing schemes, share_intr */
+#define VMXNET3_INTR_BUDDYSHARE 0    /* Corresponding tx,rx queues share irq */
+#define VMXNET3_INTR_TXSHARE 1       /* All tx queues share one irq */
+#define VMXNET3_INTR_DONTSHARE 2     /* each queue has its own irq */
+
+
 #define VMXNET3_STATE_BIT_RESETTING   0
 #define VMXNET3_STATE_BIT_QUIESCED    1
 struct vmxnet3_adapter {
-        struct vmxnet3_tx_queue         tx_queue;
-        struct vmxnet3_rx_queue         rx_queue;
-        struct napi_struct              napi;
-        struct vlan_group              *vlan_grp;
-
-        struct vmxnet3_intr             intr;
-
-        struct Vmxnet3_DriverShared    *shared;
-        struct Vmxnet3_PMConf          *pm_conf;
-        struct Vmxnet3_TxQueueDesc     *tqd_start;     /* first tx queue desc */
-        struct Vmxnet3_RxQueueDesc     *rqd_start;     /* first rx queue desc */
-        struct net_device              *netdev;
-        struct pci_dev                 *pdev;
+        struct vmxnet3_tx_queue         tx_queue[VMXNET3_DEVICE_MAX_TX_QUEUES];
+        struct vmxnet3_rx_queue         rx_queue[VMXNET3_DEVICE_MAX_RX_QUEUES];
+        struct vlan_group               *vlan_grp;
+        struct vmxnet3_intr             intr;
+        struct Vmxnet3_DriverShared     *shared;
+        struct Vmxnet3_PMConf           *pm_conf;
+        struct Vmxnet3_TxQueueDesc      *tqd_start;     /* all tx queue desc */
+        struct Vmxnet3_RxQueueDesc      *rqd_start;     /* all rx queue desc */
+        struct net_device               *netdev;
+        struct net_device_stats         net_stats;
+        struct pci_dev                  *pdev;
 
         u8                      __iomem *hw_addr0; /* for BAR 0 */
         u8                      __iomem *hw_addr1; /* for BAR 1 */
@@ -308,6 +332,12 @@ struct vmxnet3_adapter {
         bool                            rxcsum;
         bool                            lro;
         bool                            jumbo_frame;
+#ifdef VMXNET3_RSS
+        struct UPT1_RSSConf             *rss_conf;
+        bool                            rss;
+#endif
+        u32                             num_rx_queues;
+        u32                             num_tx_queues;
 
         /* rx buffer related */
         unsigned                        skb_buf_size;
@@ -327,6 +357,7 @@ struct vmxnet3_adapter {
         unsigned long  state;    /* VMXNET3_STATE_BIT_xxx */
 
         int dev_number;
+        int share_intr;
 };
 
 #define VMXNET3_WRITE_BAR0_REG(adapter, reg, val)  \
@@ -366,12 +397,10 @@ void
 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter);
 
 void
-vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
-                   struct vmxnet3_adapter *adapter);
+vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter);
 
 void
-vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
-                   struct vmxnet3_adapter *adapter);
+vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter);
 
 int
 vmxnet3_create_queues(struct vmxnet3_adapter *adapter,
diff --git a/drivers/net/vxge/vxge-config.c b/drivers/net/vxge/vxge-config.c
index 906a3ca3676b..01c05f53e2f9 100644
--- a/drivers/net/vxge/vxge-config.c
+++ b/drivers/net/vxge/vxge-config.c
@@ -19,109 +19,128 @@
 
 #include "vxge-traffic.h"
 #include "vxge-config.h"
-
-static enum vxge_hw_status
-__vxge_hw_fifo_create(
-        struct __vxge_hw_vpath_handle *vpath_handle,
-        struct vxge_hw_fifo_attr *attr);
-
-static enum vxge_hw_status
-__vxge_hw_fifo_abort(
-        struct __vxge_hw_fifo *fifoh);
-
-static enum vxge_hw_status
-__vxge_hw_fifo_reset(
-        struct __vxge_hw_fifo *ringh);
-
-static enum vxge_hw_status
-__vxge_hw_fifo_delete(
-        struct __vxge_hw_vpath_handle *vpath_handle);
-
-static struct __vxge_hw_blockpool_entry *
-__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev,
-                        u32 size);
+#include "vxge-main.h"
+
+#define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
+        status = __vxge_hw_vpath_stats_access(vpath,                    \
+                                              VXGE_HW_STATS_OP_READ,    \
+                                              offset,                   \
+                                              &val64);                  \
+        if (status != VXGE_HW_OK)                                       \
+                return status;                                          \
+}
 
 static void
-__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev,
-                        struct __vxge_hw_blockpool_entry *entry);
-
-static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
-                                        void *block_addr,
-                                        u32 length,
-                                        struct pci_dev *dma_h,
-                                        struct pci_dev *acc_handle);
-
-static enum vxge_hw_status
-__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
-                        struct __vxge_hw_blockpool  *blockpool,
-                        u32 pool_size,
-                        u32 pool_max);
+vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
+{
+        u64 val64;
 
-static void
-__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool  *blockpool);
+        val64 = readq(&vp_reg->rxmac_vcfg0);
+        val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
+        writeq(val64, &vp_reg->rxmac_vcfg0);
+        val64 = readq(&vp_reg->rxmac_vcfg0);
+}
 
-static void *
-__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev,
-                        u32 size,
-                        struct vxge_hw_mempool_dma *dma_object);
+/*
+ * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
+ */
+int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
+{
+        struct vxge_hw_vpath_reg __iomem *vp_reg;
+        struct __vxge_hw_virtualpath *vpath;
+        u64 val64, rxd_count, rxd_spat;
+        int count = 0, total_count = 0;
 
-static void
-__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev,
-                        void *memblock,
-                        u32 size,
-                        struct vxge_hw_mempool_dma *dma_object);
+        vpath = &hldev->virtual_paths[vp_id];
+        vp_reg = vpath->vp_reg;
 
+        vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
 
-static struct __vxge_hw_channel*
-__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
-                        enum __vxge_hw_channel_type type, u32 length,
-                        u32 per_dtr_space, void *userdata);
+        /* Check that the ring controller for this vpath has enough free RxDs
+         * to send frames to the host.  This is done by reading the
+         * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
+         * RXD_SPAT value for the vpath.
+         */
+        val64 = readq(&vp_reg->prc_cfg6);
+        rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
+        /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
+         * leg room.
+         */
+        rxd_spat *= 2;
 
-static void
-__vxge_hw_channel_free(
-        struct __vxge_hw_channel *channel);
+        do {
+                mdelay(1);
 
-static enum vxge_hw_status
-__vxge_hw_channel_initialize(
-        struct __vxge_hw_channel *channel);
+                rxd_count = readq(&vp_reg->prc_rxd_doorbell);
 
-static enum vxge_hw_status
-__vxge_hw_channel_reset(
-        struct __vxge_hw_channel *channel);
+                /* Check that the ring controller for this vpath does
+                 * not have any frame in its pipeline.
+                 */
+                val64 = readq(&vp_reg->frm_in_progress_cnt);
+                if ((rxd_count <= rxd_spat) || (val64 > 0))
+                        count = 0;
+                else
+                        count++;
+                total_count++;
+        } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
+                        (total_count < VXGE_HW_MAX_POLLING_COUNT));
 
-static enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp);
+        if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
+                printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
+                        __func__);
 
-static enum vxge_hw_status
-__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config);
+        return total_count;
+}
 
-static enum vxge_hw_status
-__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config);
+/* vxge_hw_device_wait_receive_idle - This function waits until all frames
+ * stored in the frame buffer for each vpath assigned to the given
+ * function (hldev) have been sent to the host.
+ */
+void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
+{
+        int i, total_count = 0;
 
-static void
-__vxge_hw_device_id_get(struct __vxge_hw_device *hldev);
+        for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
+                if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
+                        continue;
 
-static void
-__vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev);
+                total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
+                if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
+                        break;
+        }
+}
 
+/*
+ * __vxge_hw_device_register_poll
+ * Will poll certain register for specified amount of time.
+ * Will poll until masked bit is not cleared.
+ */
 static enum vxge_hw_status
-__vxge_hw_vpath_card_info_get(
-        u32 vp_id,
-        struct vxge_hw_vpath_reg __iomem *vpath_reg,
-        struct vxge_hw_device_hw_info *hw_info);
+__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
+{
+        u64 val64;
+        u32 i = 0;
+        enum vxge_hw_status ret = VXGE_HW_FAIL;
 
-static enum vxge_hw_status
-__vxge_hw_device_initialize(struct __vxge_hw_device *hldev);
+        udelay(10);
 
-static void
-__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev);
+        do {
+                val64 = readq(reg);
+                if (!(val64 & mask))
+                        return VXGE_HW_OK;
+                udelay(100);
+        } while (++i <= 9);
 
-static enum vxge_hw_status
-__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev);
+        i = 0;
+        do {
+                val64 = readq(reg);
+                if (!(val64 & mask))
+                        return VXGE_HW_OK;
+                mdelay(1);
+        } while (++i <= max_millis);
 
-static enum vxge_hw_status
-__vxge_hw_device_register_poll(
-        void __iomem    *reg,
-        u64 mask, u32 max_millis);
+        return ret;
+}
 
 static inline enum vxge_hw_status
 __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
@@ -129,139 +148,258 @@ __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
 {
         __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
         wmb();
-
         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
         wmb();
 
-        return  __vxge_hw_device_register_poll(addr, mask, max_millis);
+        return __vxge_hw_device_register_poll(addr, mask, max_millis);
 }
 
-static struct vxge_hw_mempool*
-__vxge_hw_mempool_create(struct __vxge_hw_device *devh, u32 memblock_size,
-                         u32 item_size, u32 private_size, u32 items_initial,
-                         u32 items_max, struct vxge_hw_mempool_cbs *mp_callback,
-                         void *userdata);
-static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool);
-
 static enum vxge_hw_status
-__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
-                          struct vxge_hw_vpath_stats_hw_info *hw_stats);
+vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
+                     u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
+                     u64 *steer_ctrl)
+{
+        struct vxge_hw_vpath_reg __iomem *vp_reg;
+        enum vxge_hw_status status;
+        u64 val64;
+        u32 retry = 0, max_retry = 100;
 
-static enum vxge_hw_status
-vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vpath_handle);
+        vp_reg = vpath->vp_reg;
 
-static enum vxge_hw_status
-__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg);
+        if (vpath->vp_open) {
+                max_retry = 3;
+                spin_lock(&vpath->lock);
+        }
 
-static u64
-__vxge_hw_vpath_pci_func_mode_get(u32  vp_id,
-                                  struct vxge_hw_vpath_reg __iomem *vpath_reg);
+        writeq(*data0, &vp_reg->rts_access_steer_data0);
+        writeq(*data1, &vp_reg->rts_access_steer_data1);
+        wmb();
 
-static u32
-__vxge_hw_vpath_func_id_get(u32 vp_id, struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg);
+        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
+                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
+                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
+                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
+                *steer_ctrl;
 
-static enum vxge_hw_status
-__vxge_hw_vpath_addr_get(u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg,
-                         u8 (macaddr)[ETH_ALEN], u8 (macaddr_mask)[ETH_ALEN]);
+        status = __vxge_hw_pio_mem_write64(val64,
+                                           &vp_reg->rts_access_steer_ctrl,
+                                           VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
+                                           VXGE_HW_DEF_DEVICE_POLL_MILLIS);
+
+        /* The __vxge_hw_device_register_poll can udelay for a significant
+         * amount of time, blocking other proccess from the CPU.  If it delays
+         * for ~5secs, a NMI error can occur.  A way around this is to give up
+         * the processor via msleep, but this is not allowed is under lock.
+         * So, only allow it to sleep for ~4secs if open.  Otherwise, delay for
+         * 1sec and sleep for 10ms until the firmware operation has completed
+         * or timed-out.
+         */
+        while ((status != VXGE_HW_OK) && retry++ < max_retry) {
+                if (!vpath->vp_open)
+                        msleep(20);
+                status = __vxge_hw_device_register_poll(
+                                        &vp_reg->rts_access_steer_ctrl,
+                                        VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
+                                        VXGE_HW_DEF_DEVICE_POLL_MILLIS);
+        }
 
-static enum vxge_hw_status
-__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath);
+        if (status != VXGE_HW_OK)
+                goto out;
 
+        val64 = readq(&vp_reg->rts_access_steer_ctrl);
+        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+                *data0 = readq(&vp_reg->rts_access_steer_data0);
+                *data1 = readq(&vp_reg->rts_access_steer_data1);
+                *steer_ctrl = val64;
+        } else
+                status = VXGE_HW_FAIL;
 
-static enum vxge_hw_status
-__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *devh, u32 vp_id);
+out:
+        if (vpath->vp_open)
+                spin_unlock(&vpath->lock);
+        return status;
+}
 
-static enum vxge_hw_status
-__vxge_hw_vpath_fw_ver_get(u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg,
-                           struct vxge_hw_device_hw_info *hw_info);
+enum vxge_hw_status
+vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
+                             u32 *minor, u32 *build)
+{
+        u64 data0 = 0, data1 = 0, steer_ctrl = 0;
+        struct __vxge_hw_virtualpath *vpath;
+        enum vxge_hw_status status;
 
-static enum vxge_hw_status
-__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *devh, u32 vp_id);
+        vpath = &hldev->virtual_paths[hldev->first_vp_id];
 
-static void
-__vxge_hw_vp_terminate(struct __vxge_hw_device *devh, u32 vp_id);
+        status = vxge_hw_vpath_fw_api(vpath,
+                                      VXGE_HW_FW_UPGRADE_ACTION,
+                                      VXGE_HW_FW_UPGRADE_MEMO,
+                                      VXGE_HW_FW_UPGRADE_OFFSET_READ,
+                                      &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK)
+                return status;
 
-static enum vxge_hw_status
-__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
-                             u32 operation, u32 offset, u64 *stat);
+        *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
+        *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
+        *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
 
-static enum vxge_hw_status
-__vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath  *vpath,
-                                  struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats);
+        return status;
+}
 
-static enum vxge_hw_status
-__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath  *vpath,
-                                  struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats);
+enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
+{
+        u64 data0 = 0, data1 = 0, steer_ctrl = 0;
+        struct __vxge_hw_virtualpath *vpath;
+        enum vxge_hw_status status;
+        u32 ret;
 
-/*
- * __vxge_hw_channel_allocate - Allocate memory for channel
- * This function allocates required memory for the channel and various arrays
- * in the channel
- */
-struct __vxge_hw_channel*
-__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
-                           enum __vxge_hw_channel_type type,
-        u32 length, u32 per_dtr_space, void *userdata)
+        vpath = &hldev->virtual_paths[hldev->first_vp_id];
+
+        status = vxge_hw_vpath_fw_api(vpath,
+                                      VXGE_HW_FW_UPGRADE_ACTION,
+                                      VXGE_HW_FW_UPGRADE_MEMO,
+                                      VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
+                                      &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
+                goto exit;
+        }
+
+        ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
+        if (ret != 1) {
+                vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
+                                __func__, ret);
+                status = VXGE_HW_FAIL;
+        }
+
+exit:
+        return status;
+}
+
+enum vxge_hw_status
+vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
 {
-        struct __vxge_hw_channel *channel;
-        struct __vxge_hw_device *hldev;
-        int size = 0;
-        u32 vp_id;
+        u64 data0 = 0, data1 = 0, steer_ctrl = 0;
+        struct __vxge_hw_virtualpath *vpath;
+        enum vxge_hw_status status;
+        int ret_code, sec_code;
 
-        hldev = vph->vpath->hldev;
-        vp_id = vph->vpath->vp_id;
+        vpath = &hldev->virtual_paths[hldev->first_vp_id];
 
-        switch (type) {
-        case VXGE_HW_CHANNEL_TYPE_FIFO:
-                size = sizeof(struct __vxge_hw_fifo);
-                break;
-        case VXGE_HW_CHANNEL_TYPE_RING:
-                size = sizeof(struct __vxge_hw_ring);
-                break;
-        default:
-                break;
+        /* send upgrade start command */
+        status = vxge_hw_vpath_fw_api(vpath,
+                                      VXGE_HW_FW_UPGRADE_ACTION,
+                                      VXGE_HW_FW_UPGRADE_MEMO,
+                                      VXGE_HW_FW_UPGRADE_OFFSET_START,
+                                      &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
+                                __func__);
+                return status;
         }
 
-        channel = kzalloc(size, GFP_KERNEL);
-        if (channel == NULL)
-                goto exit0;
-        INIT_LIST_HEAD(&channel->item);
+        /* Transfer fw image to adapter 16 bytes at a time */
+        for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
+                steer_ctrl = 0;
 
-        channel->common_reg = hldev->common_reg;
-        channel->first_vp_id = hldev->first_vp_id;
-        channel->type = type;
-        channel->devh = hldev;
-        channel->vph = vph;
-        channel->userdata = userdata;
-        channel->per_dtr_space = per_dtr_space;
-        channel->length = length;
-        channel->vp_id = vp_id;
+                /* The next 128bits of fwdata to be loaded onto the adapter */
+                data0 = *((u64 *)fwdata);
+                data1 = *((u64 *)fwdata + 1);
 
-        channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
-        if (channel->work_arr == NULL)
-                goto exit1;
+                status = vxge_hw_vpath_fw_api(vpath,
+                                              VXGE_HW_FW_UPGRADE_ACTION,
+                                              VXGE_HW_FW_UPGRADE_MEMO,
+                                              VXGE_HW_FW_UPGRADE_OFFSET_SEND,
+                                              &data0, &data1, &steer_ctrl);
+                if (status != VXGE_HW_OK) {
+                        vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
+                                        __func__);
+                        goto out;
+                }
 
-        channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
-        if (channel->free_arr == NULL)
-                goto exit1;
-        channel->free_ptr = length;
+                ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
+                switch (ret_code) {
+                case VXGE_HW_FW_UPGRADE_OK:
+                        /* All OK, send next 16 bytes. */
+                        break;
+                case VXGE_FW_UPGRADE_BYTES2SKIP:
+                        /* skip bytes in the stream */
+                        fwdata += (data0 >> 8) & 0xFFFFFFFF;
+                        break;
+                case VXGE_HW_FW_UPGRADE_DONE:
+                        goto out;
+                case VXGE_HW_FW_UPGRADE_ERR:
+                        sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
+                        switch (sec_code) {
+                        case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
+                        case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
+                                printk(KERN_ERR
+                                       "corrupted data from .ncf file\n");
+                                break;
+                        case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
+                        case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
+                        case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
+                        case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
+                        case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
+                                printk(KERN_ERR "invalid .ncf file\n");
+                                break;
+                        case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
+                                printk(KERN_ERR "buffer overflow\n");
+                                break;
+                        case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
+                                printk(KERN_ERR "failed to flash the image\n");
+                                break;
+                        case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
+                                printk(KERN_ERR
+                                       "generic error. Unknown error type\n");
+                                break;
+                        default:
+                                printk(KERN_ERR "Unknown error of type %d\n",
+                                       sec_code);
+                                break;
+                        }
+                        status = VXGE_HW_FAIL;
+                        goto out;
+                default:
+                        printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
+                        status = VXGE_HW_FAIL;
+                        goto out;
+                }
+                /* point to next 16 bytes */
+                fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
+        }
+out:
+        return status;
+}
 
-        channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
-        if (channel->reserve_arr == NULL)
-                goto exit1;
-        channel->reserve_ptr = length;
-        channel->reserve_top = 0;
+enum vxge_hw_status
+vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
+                                struct eprom_image *img)
+{
+        u64 data0 = 0, data1 = 0, steer_ctrl = 0;
+        struct __vxge_hw_virtualpath *vpath;
+        enum vxge_hw_status status;
+        int i;
 
-        channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
-        if (channel->orig_arr == NULL)
-                goto exit1;
+        vpath = &hldev->virtual_paths[hldev->first_vp_id];
 
-        return channel;
-exit1:
-        __vxge_hw_channel_free(channel);
+        for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
+                data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
+                data1 = steer_ctrl = 0;
 
-exit0:
-        return NULL;
+                status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        VXGE_HW_FW_API_GET_EPROM_REV,
+                        0, &data0, &data1, &steer_ctrl);
+                if (status != VXGE_HW_OK)
+                        break;
+
+                img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
+                img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
+                img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
+                img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
+        }
+
+        return status;
 }
 
 /*
@@ -269,7 +407,7 @@ exit0:
  * This function deallocates memory from the channel and various arrays
  * in the channel
  */
-void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
+static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
 {
         kfree(channel->work_arr);
         kfree(channel->free_arr);
@@ -283,7 +421,7 @@ void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
  * This function initializes a channel by properly setting the
  * various references
  */
-enum vxge_hw_status
+static enum vxge_hw_status
 __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
 {
         u32 i;
@@ -318,7 +456,7 @@ __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
  * __vxge_hw_channel_reset - Resets a channel
  * This function resets a channel by properly setting the various references
  */
-enum vxge_hw_status
+static enum vxge_hw_status
 __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
 {
         u32 i;
@@ -345,8 +483,7 @@ __vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
  * Initialize certain PCI/PCI-X configuration registers
  * with recommended values. Save config space for future hw resets.
  */
-void
-__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
+static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
 {
         u16 cmd = 0;
 
@@ -358,39 +495,7 @@ __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
         pci_save_state(hldev->pdev);
 }
 
-/*
- * __vxge_hw_device_register_poll
- * Will poll certain register for specified amount of time.
- * Will poll until masked bit is not cleared.
- */
-static enum vxge_hw_status
-__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
-{
-        u64 val64;
-        u32 i = 0;
-        enum vxge_hw_status ret = VXGE_HW_FAIL;
-
-        udelay(10);
-
-        do {
-                val64 = readq(reg);
-                if (!(val64 & mask))
-                        return VXGE_HW_OK;
-                udelay(100);
-        } while (++i <= 9);
-
-        i = 0;
-        do {
-                val64 = readq(reg);
-                if (!(val64 & mask))
-                        return VXGE_HW_OK;
-                mdelay(1);
-        } while (++i <= max_millis);
-
-        return ret;
-}
-
- /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
+/* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
  * in progress
  * This routine checks the vpath reset in progress register is turned zero
  */
@@ -405,6 +510,60 @@ __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
 }
 
 /*
+ * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
+ * Set the swapper bits appropriately for the lagacy section.
+ */
+static enum vxge_hw_status
+__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
+{
+        u64 val64;
+        enum vxge_hw_status status = VXGE_HW_OK;
+
+        val64 = readq(&legacy_reg->toc_swapper_fb);
+
+        wmb();
+
+        switch (val64) {
+        case VXGE_HW_SWAPPER_INITIAL_VALUE:
+                return status;
+
+        case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
+                writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
+                        &legacy_reg->pifm_rd_swap_en);
+                writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
+                        &legacy_reg->pifm_rd_flip_en);
+                writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
+                        &legacy_reg->pifm_wr_swap_en);
+                writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
+                        &legacy_reg->pifm_wr_flip_en);
+                break;
+
+        case VXGE_HW_SWAPPER_BYTE_SWAPPED:
+                writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
+                        &legacy_reg->pifm_rd_swap_en);
+                writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
+                        &legacy_reg->pifm_wr_swap_en);
+                break;
+
+        case VXGE_HW_SWAPPER_BIT_FLIPPED:
+                writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
+                        &legacy_reg->pifm_rd_flip_en);
+                writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
+                        &legacy_reg->pifm_wr_flip_en);
+                break;
+        }
+
+        wmb();
+
+        val64 = readq(&legacy_reg->toc_swapper_fb);
+
+        if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
+                status = VXGE_HW_ERR_SWAPPER_CTRL;
+
+        return status;
+}
+
+/*
  * __vxge_hw_device_toc_get
  * This routine sets the swapper and reads the toc pointer and returns the
  * memory mapped address of the toc
@@ -435,7 +594,7 @@ exit:
  * register location pointers in the device object. It waits until the ric is
  * completed initializing registers.
  */
-enum vxge_hw_status
+static enum vxge_hw_status
 __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
 {
         u64 val64;
@@ -496,26 +655,6 @@ exit:
 }
 
 /*
- * __vxge_hw_device_id_get
- * This routine returns sets the device id and revision numbers into the device
- * structure
- */
-void __vxge_hw_device_id_get(struct __vxge_hw_device *hldev)
-{
-        u64 val64;
-
-        val64 = readq(&hldev->common_reg->titan_asic_id);
-        hldev->device_id =
-                (u16)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(val64);
-
-        hldev->major_revision =
-                (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(val64);
-
-        hldev->minor_revision =
-                (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(val64);
-}
-
-/*
  * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
  * This routine returns the Access Rights of the driver
  */
@@ -568,10 +707,25 @@ __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
 }
 
 /*
+ * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
+ * Returns the function number of the vpath.
+ */
+static u32
+__vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
+{
+        u64 val64;
+
+        val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
+
+        return
+         (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
+}
+
+/*
  * __vxge_hw_device_host_info_get
  * This routine returns the host type assignments
  */
-void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
+static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
 {
         u64 val64;
         u32 i;
@@ -584,16 +738,18 @@ void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
         hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
 
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
                         continue;
 
                 hldev->func_id =
-                        __vxge_hw_vpath_func_id_get(i, hldev->vpmgmt_reg[i]);
+                        __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
 
                 hldev->access_rights = __vxge_hw_device_access_rights_get(
                         hldev->host_type, hldev->func_id);
 
+                hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
+                hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
+
                 hldev->first_vp_id = i;
                 break;
         }
@@ -634,7 +790,8 @@ __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
  * __vxge_hw_device_initialize
  * Initialize Titan-V hardware.
  */
-enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
+static enum vxge_hw_status
+__vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
 {
         enum vxge_hw_status status = VXGE_HW_OK;
 
@@ -650,6 +807,196 @@ exit:
         return status;
 }
 
+/*
+ * __vxge_hw_vpath_fw_ver_get - Get the fw version
+ * Returns FW Version
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
+                           struct vxge_hw_device_hw_info *hw_info)
+{
+        struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
+        struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
+        struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
+        struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
+        u64 data0, data1 = 0, steer_ctrl = 0;
+        enum vxge_hw_status status;
+
+        status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        0, &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK)
+                goto exit;
+
+        fw_date->day =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
+        fw_date->month =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
+        fw_date->year =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
+
+        snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
+                 fw_date->month, fw_date->day, fw_date->year);
+
+        fw_version->major =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
+        fw_version->minor =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
+        fw_version->build =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
+
+        snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
+                 fw_version->major, fw_version->minor, fw_version->build);
+
+        flash_date->day =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
+        flash_date->month =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
+        flash_date->year =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
+
+        snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
+                 flash_date->month, flash_date->day, flash_date->year);
+
+        flash_version->major =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
+        flash_version->minor =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
+        flash_version->build =
+            (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
+
+        snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
+                 flash_version->major, flash_version->minor,
+                 flash_version->build);
+
+exit:
+        return status;
+}
+
+/*
+ * __vxge_hw_vpath_card_info_get - Get the serial numbers,
+ * part number and product description.
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
+                              struct vxge_hw_device_hw_info *hw_info)
+{
+        enum vxge_hw_status status;
+        u64 data0, data1 = 0, steer_ctrl = 0;
+        u8 *serial_number = hw_info->serial_number;
+        u8 *part_number = hw_info->part_number;
+        u8 *product_desc = hw_info->product_desc;
+        u32 i, j = 0;
+
+        data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
+
+        status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        0, &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK)
+                return status;
+
+        ((u64 *)serial_number)[0] = be64_to_cpu(data0);
+        ((u64 *)serial_number)[1] = be64_to_cpu(data1);
+
+        data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
+        data1 = steer_ctrl = 0;
+
+        status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        0, &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK)
+                return status;
+
+        ((u64 *)part_number)[0] = be64_to_cpu(data0);
+        ((u64 *)part_number)[1] = be64_to_cpu(data1);
+
+        for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
+             i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
+                data0 = i;
+                data1 = steer_ctrl = 0;
+
+                status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        0, &data0, &data1, &steer_ctrl);
+                if (status != VXGE_HW_OK)
+                        return status;
+
+                ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
+                ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
+        }
+
+        return status;
+}
+
+/*
+ * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
+ * Returns pci function mode
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
+                                  struct vxge_hw_device_hw_info *hw_info)
+{
+        u64 data0, data1 = 0, steer_ctrl = 0;
+        enum vxge_hw_status status;
+
+        data0 = 0;
+
+        status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_FW_API_GET_FUNC_MODE,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        0, &data0, &data1, &steer_ctrl);
+        if (status != VXGE_HW_OK)
+                return status;
+
+        hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
+        return status;
+}
+
+/*
+ * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
+ *               from MAC address table.
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
+                         u8 *macaddr, u8 *macaddr_mask)
+{
+        u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
+            data0 = 0, data1 = 0, steer_ctrl = 0;
+        enum vxge_hw_status status;
+        int i;
+
+        do {
+                status = vxge_hw_vpath_fw_api(vpath, action,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
+                        0, &data0, &data1, &steer_ctrl);
+                if (status != VXGE_HW_OK)
+                        goto exit;
+
+                data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
+                data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
+                                                                        data1);
+
+                for (i = ETH_ALEN; i > 0; i--) {
+                        macaddr[i - 1] = (u8) (data0 & 0xFF);
+                        data0 >>= 8;
+
+                        macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
+                        data1 >>= 8;
+                }
+
+                action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
+                data0 = 0, data1 = 0, steer_ctrl = 0;
+
+        } while (!is_valid_ether_addr(macaddr));
+exit:
+        return status;
+}
+
 /**
  * vxge_hw_device_hw_info_get - Get the hw information
  * Returns the vpath mask that has the bits set for each vpath allocated
@@ -665,9 +1012,9 @@ vxge_hw_device_hw_info_get(void __iomem *bar0,
         struct vxge_hw_toc_reg __iomem *toc;
         struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
         struct vxge_hw_common_reg __iomem *common_reg;
-        struct vxge_hw_vpath_reg __iomem *vpath_reg;
         struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
         enum vxge_hw_status status;
+        struct __vxge_hw_virtualpath vpath;
 
         memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
 
@@ -693,7 +1040,6 @@ vxge_hw_device_hw_info_get(void __iomem *bar0,
            (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
 
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
                         continue;
 
@@ -702,7 +1048,7 @@ vxge_hw_device_hw_info_get(void __iomem *bar0,
                 vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *)
                                 (bar0 + val64);
 
-                hw_info->func_id = __vxge_hw_vpath_func_id_get(i, vpmgmt_reg);
+                hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
                 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
                         hw_info->func_id) &
                         VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
@@ -718,16 +1064,19 @@ vxge_hw_device_hw_info_get(void __iomem *bar0,
 
                 val64 = readq(&toc->toc_vpath_pointer[i]);
 
-                vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64);
+                vpath.vp_reg = (struct vxge_hw_vpath_reg __iomem *)
+                               (bar0 + val64);
+                vpath.vp_open = 0;
 
-                hw_info->function_mode =
-                        __vxge_hw_vpath_pci_func_mode_get(i, vpath_reg);
+                status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
+                if (status != VXGE_HW_OK)
+                        goto exit;
 
-                status = __vxge_hw_vpath_fw_ver_get(i, vpath_reg, hw_info);
+                status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
                 if (status != VXGE_HW_OK)
                         goto exit;
 
-                status = __vxge_hw_vpath_card_info_get(i, vpath_reg, hw_info);
+                status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
                 if (status != VXGE_HW_OK)
                         goto exit;
 
@@ -735,14 +1084,15 @@ vxge_hw_device_hw_info_get(void __iomem *bar0,
         }
 
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
                 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
                         continue;
 
                 val64 = readq(&toc->toc_vpath_pointer[i]);
-                vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64);
+                vpath.vp_reg = (struct vxge_hw_vpath_reg __iomem *)
+                               (bar0 + val64);
+                vpath.vp_open = 0;
 
-                status =  __vxge_hw_vpath_addr_get(i, vpath_reg,
+                status =  __vxge_hw_vpath_addr_get(&vpath,
                                 hw_info->mac_addrs[i],
                                 hw_info->mac_addr_masks[i]);
                 if (status != VXGE_HW_OK)
@@ -753,6 +1103,218 @@ exit:
 }
 
 /*
+ * __vxge_hw_blockpool_destroy - Deallocates the block pool
+ */
+static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
+{
+        struct __vxge_hw_device *hldev;
+        struct list_head *p, *n;
+        u16 ret;
+
+        if (blockpool == NULL) {
+                ret = 1;
+                goto exit;
+        }
+
+        hldev = blockpool->hldev;
+
+        list_for_each_safe(p, n, &blockpool->free_block_list) {
+                pci_unmap_single(hldev->pdev,
+                        ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
+                        ((struct __vxge_hw_blockpool_entry *)p)->length,
+                        PCI_DMA_BIDIRECTIONAL);
+
+                vxge_os_dma_free(hldev->pdev,
+                        ((struct __vxge_hw_blockpool_entry *)p)->memblock,
+                        &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
+
+                list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
+                kfree(p);
+                blockpool->pool_size--;
+        }
+
+        list_for_each_safe(p, n, &blockpool->free_entry_list) {
+                list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
+                kfree((void *)p);
+        }
+        ret = 0;
+exit:
+        return;
+}
+
+/*
+ * __vxge_hw_blockpool_create - Create block pool
+ */
+static enum vxge_hw_status
+__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
+                           struct __vxge_hw_blockpool *blockpool,
+                           u32 pool_size,
+                           u32 pool_max)
+{
+        u32 i;
+        struct __vxge_hw_blockpool_entry *entry = NULL;
+        void *memblock;
+        dma_addr_t dma_addr;
+        struct pci_dev *dma_handle;
+        struct pci_dev *acc_handle;
+        enum vxge_hw_status status = VXGE_HW_OK;
+
+        if (blockpool == NULL) {
+                status = VXGE_HW_FAIL;
+                goto blockpool_create_exit;
+        }
+
+        blockpool->hldev = hldev;
+        blockpool->block_size = VXGE_HW_BLOCK_SIZE;
+        blockpool->pool_size = 0;
+        blockpool->pool_max = pool_max;
+        blockpool->req_out = 0;
+
+        INIT_LIST_HEAD(&blockpool->free_block_list);
+        INIT_LIST_HEAD(&blockpool->free_entry_list);
+
+        for (i = 0; i < pool_size + pool_max; i++) {
+                entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
+                                GFP_KERNEL);
+                if (entry == NULL) {
+                        __vxge_hw_blockpool_destroy(blockpool);
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
+                        goto blockpool_create_exit;
+                }
+                list_add(&entry->item, &blockpool->free_entry_list);
+        }
+
+        for (i = 0; i < pool_size; i++) {
+                memblock = vxge_os_dma_malloc(
+                                hldev->pdev,
+                                VXGE_HW_BLOCK_SIZE,
+                                &dma_handle,
+                                &acc_handle);
+                if (memblock == NULL) {
+                        __vxge_hw_blockpool_destroy(blockpool);
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
+                        goto blockpool_create_exit;
+                }
+
+                dma_addr = pci_map_single(hldev->pdev, memblock,
+                                VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
+                if (unlikely(pci_dma_mapping_error(hldev->pdev,
+                                dma_addr))) {
+                        vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
+                        __vxge_hw_blockpool_destroy(blockpool);
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
+                        goto blockpool_create_exit;
+                }
+
+                if (!list_empty(&blockpool->free_entry_list))
+                        entry = (struct __vxge_hw_blockpool_entry *)
+                                list_first_entry(&blockpool->free_entry_list,
+                                        struct __vxge_hw_blockpool_entry,
+                                        item);
+
+                if (entry == NULL)
+                        entry =
+                            kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
+                                        GFP_KERNEL);
+                if (entry != NULL) {
+                        list_del(&entry->item);
+                        entry->length = VXGE_HW_BLOCK_SIZE;
+                        entry->memblock = memblock;
+                        entry->dma_addr = dma_addr;
+                        entry->acc_handle = acc_handle;
+                        entry->dma_handle = dma_handle;
+                        list_add(&entry->item,
+                                          &blockpool->free_block_list);
+                        blockpool->pool_size++;
+                } else {
+                        __vxge_hw_blockpool_destroy(blockpool);
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
+                        goto blockpool_create_exit;
+                }
+        }
+
+blockpool_create_exit:
+        return status;
+}
+
+/*
+ * __vxge_hw_device_fifo_config_check - Check fifo configuration.
+ * Check the fifo configuration
+ */
+static enum vxge_hw_status
+__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
+{
+        if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
+            (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
+                return VXGE_HW_BADCFG_FIFO_BLOCKS;
+
+        return VXGE_HW_OK;
+}
+
+/*
+ * __vxge_hw_device_vpath_config_check - Check vpath configuration.
+ * Check the vpath configuration
+ */
+static enum vxge_hw_status
+__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
+{
+        enum vxge_hw_status status;
+
+        if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
+            (vp_config->min_bandwidth > VXGE_HW_VPATH_BANDWIDTH_MAX))
+                return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
+
+        status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
+        if (status != VXGE_HW_OK)
+                return status;
+
+        if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
+                ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
+                (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
+                return VXGE_HW_BADCFG_VPATH_MTU;
+
+        if ((vp_config->rpa_strip_vlan_tag !=
+                VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
+                (vp_config->rpa_strip_vlan_tag !=
+                VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
+                (vp_config->rpa_strip_vlan_tag !=
+                VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
+                return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
+
+        return VXGE_HW_OK;
+}
+
+/*
+ * __vxge_hw_device_config_check - Check device configuration.
+ * Check the device configuration
+ */
+static enum vxge_hw_status
+__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
+{
+        u32 i;
+        enum vxge_hw_status status;
+
+        if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
+            (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
+            (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
+            (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
+                return VXGE_HW_BADCFG_INTR_MODE;
+
+        if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
+            (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
+                return VXGE_HW_BADCFG_RTS_MAC_EN;
+
+        for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
+                status = __vxge_hw_device_vpath_config_check(
+                                &new_config->vp_config[i]);
+                if (status != VXGE_HW_OK)
+                        return status;
+        }
+
+        return VXGE_HW_OK;
+}
+
+/*
  * vxge_hw_device_initialize - Initialize Titan device.
  * Initialize Titan device. Note that all the arguments of this public API
  * are 'IN', including @hldev. Driver cooperates with
@@ -776,14 +1338,12 @@ vxge_hw_device_initialize(
         if (status != VXGE_HW_OK)
                 goto exit;
 
-        hldev = (struct __vxge_hw_device *)
-                        vmalloc(sizeof(struct __vxge_hw_device));
+        hldev = vzalloc(sizeof(struct __vxge_hw_device));
         if (hldev == NULL) {
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 goto exit;
         }
 
-        memset(hldev, 0, sizeof(struct __vxge_hw_device));
         hldev->magic = VXGE_HW_DEVICE_MAGIC;
 
         vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
@@ -806,7 +1366,6 @@ vxge_hw_device_initialize(
                 vfree(hldev);
                 goto exit;
         }
-        __vxge_hw_device_id_get(hldev);
 
         __vxge_hw_device_host_info_get(hldev);
 
@@ -814,7 +1373,6 @@ vxge_hw_device_initialize(
         nblocks++;
 
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
                 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
                         continue;
 
@@ -839,7 +1397,6 @@ vxge_hw_device_initialize(
         }
 
         status = __vxge_hw_device_initialize(hldev);
-
         if (status != VXGE_HW_OK) {
                 vxge_hw_device_terminate(hldev);
                 goto exit;
@@ -865,6 +1422,242 @@ vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
 }
 
 /*
+ * __vxge_hw_vpath_stats_access - Get the statistics from the given location
+ *                           and offset and perform an operation
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
+                             u32 operation, u32 offset, u64 *stat)
+{
+        u64 val64;
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct vxge_hw_vpath_reg __iomem *vp_reg;
+
+        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
+                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
+                goto vpath_stats_access_exit;
+        }
+
+        vp_reg = vpath->vp_reg;
+
+        val64 =  VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
+                 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
+                 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
+
+        status = __vxge_hw_pio_mem_write64(val64,
+                                &vp_reg->xmac_stats_access_cmd,
+                                VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
+                                vpath->hldev->config.device_poll_millis);
+        if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
+                *stat = readq(&vp_reg->xmac_stats_access_data);
+        else
+                *stat = 0;
+
+vpath_stats_access_exit:
+        return status;
+}
+
+/*
+ * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
+                        struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
+{
+        u64 *val64;
+        int i;
+        u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
+        enum vxge_hw_status status = VXGE_HW_OK;
+
+        val64 = (u64 *)vpath_tx_stats;
+
+        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
+                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
+                goto exit;
+        }
+
+        for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
+                status = __vxge_hw_vpath_stats_access(vpath,
+                                        VXGE_HW_STATS_OP_READ,
+                                        offset, val64);
+                if (status != VXGE_HW_OK)
+                        goto exit;
+                offset++;
+                val64++;
+        }
+exit:
+        return status;
+}
+
+/*
+ * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
+                        struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
+{
+        u64 *val64;
+        enum vxge_hw_status status = VXGE_HW_OK;
+        int i;
+        u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
+        val64 = (u64 *) vpath_rx_stats;
+
+        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
+                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
+                goto exit;
+        }
+        for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
+                status = __vxge_hw_vpath_stats_access(vpath,
+                                        VXGE_HW_STATS_OP_READ,
+                                        offset >> 3, val64);
+                if (status != VXGE_HW_OK)
+                        goto exit;
+
+                offset += 8;
+                val64++;
+        }
+exit:
+        return status;
+}
+
+/*
+ * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
+                          struct vxge_hw_vpath_stats_hw_info *hw_stats)
+{
+        u64 val64;
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct vxge_hw_vpath_reg __iomem *vp_reg;
+
+        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
+                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
+                goto exit;
+        }
+        vp_reg = vpath->vp_reg;
+
+        val64 = readq(&vp_reg->vpath_debug_stats0);
+        hw_stats->ini_num_mwr_sent =
+                (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
+
+        val64 = readq(&vp_reg->vpath_debug_stats1);
+        hw_stats->ini_num_mrd_sent =
+                (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
+
+        val64 = readq(&vp_reg->vpath_debug_stats2);
+        hw_stats->ini_num_cpl_rcvd =
+                (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
+
+        val64 = readq(&vp_reg->vpath_debug_stats3);
+        hw_stats->ini_num_mwr_byte_sent =
+                VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
+
+        val64 = readq(&vp_reg->vpath_debug_stats4);
+        hw_stats->ini_num_cpl_byte_rcvd =
+                VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
+
+        val64 = readq(&vp_reg->vpath_debug_stats5);
+        hw_stats->wrcrdtarb_xoff =
+                (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
+
+        val64 = readq(&vp_reg->vpath_debug_stats6);
+        hw_stats->rdcrdtarb_xoff =
+                (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
+
+        val64 = readq(&vp_reg->vpath_genstats_count01);
+        hw_stats->vpath_genstats_count0 =
+        (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
+                val64);
+
+        val64 = readq(&vp_reg->vpath_genstats_count01);
+        hw_stats->vpath_genstats_count1 =
+        (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
+                val64);
+
+        val64 = readq(&vp_reg->vpath_genstats_count23);
+        hw_stats->vpath_genstats_count2 =
+        (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
+                val64);
+
+        val64 = readq(&vp_reg->vpath_genstats_count01);
+        hw_stats->vpath_genstats_count3 =
+        (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
+                val64);
+
+        val64 = readq(&vp_reg->vpath_genstats_count4);
+        hw_stats->vpath_genstats_count4 =
+        (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
+                val64);
+
+        val64 = readq(&vp_reg->vpath_genstats_count5);
+        hw_stats->vpath_genstats_count5 =
+        (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
+                val64);
+
+        status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
+        if (status != VXGE_HW_OK)
+                goto exit;
+
+        status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
+        if (status != VXGE_HW_OK)
+                goto exit;
+
+        VXGE_HW_VPATH_STATS_PIO_READ(
+                VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
+
+        hw_stats->prog_event_vnum0 =
+                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
+
+        hw_stats->prog_event_vnum1 =
+                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
+
+        VXGE_HW_VPATH_STATS_PIO_READ(
+                VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
+
+        hw_stats->prog_event_vnum2 =
+                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
+
+        hw_stats->prog_event_vnum3 =
+                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
+
+        val64 = readq(&vp_reg->rx_multi_cast_stats);
+        hw_stats->rx_multi_cast_frame_discard =
+                (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
+
+        val64 = readq(&vp_reg->rx_frm_transferred);
+        hw_stats->rx_frm_transferred =
+                (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
+
+        val64 = readq(&vp_reg->rxd_returned);
+        hw_stats->rxd_returned =
+                (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
+
+        val64 = readq(&vp_reg->dbg_stats_rx_mpa);
+        hw_stats->rx_mpa_len_fail_frms =
+                (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
+        hw_stats->rx_mpa_mrk_fail_frms =
+                (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
+        hw_stats->rx_mpa_crc_fail_frms =
+                (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
+
+        val64 = readq(&vp_reg->dbg_stats_rx_fau);
+        hw_stats->rx_permitted_frms =
+                (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
+        hw_stats->rx_vp_reset_discarded_frms =
+        (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
+        hw_stats->rx_wol_frms =
+                (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
+
+        val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
+        hw_stats->tx_vp_reset_discarded_frms =
+        (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
+                val64);
+exit:
+        return status;
+}
+
+/*
  * vxge_hw_device_stats_get - Get the device hw statistics.
  * Returns the vpath h/w stats for the device.
  */
@@ -876,7 +1669,6 @@ vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
         enum vxge_hw_status status = VXGE_HW_OK;
 
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
                 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
                         (hldev->virtual_paths[i].vp_open ==
                                 VXGE_HW_VP_NOT_OPEN))
@@ -1031,7 +1823,6 @@ vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
 
         status = vxge_hw_device_xmac_aggr_stats_get(hldev,
                                         0, &xmac_stats->aggr_stats[0]);
-
         if (status != VXGE_HW_OK)
                 goto exit;
 
@@ -1165,7 +1956,6 @@ exit:
  * It can be used to set or reset Pause frame generation or reception
  * support of the NIC.
  */
-
 enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
                                                  u32 port, u32 tx, u32 rx)
 {
@@ -1407,190 +2197,359 @@ exit:
 }
 
 /*
- * __vxge_hw_ring_create - Create a Ring
- * This function creates Ring and initializes it.
- *
+ * __vxge_hw_channel_allocate - Allocate memory for channel
+ * This function allocates required memory for the channel and various arrays
+ * in the channel
  */
-static enum vxge_hw_status
-__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
-                      struct vxge_hw_ring_attr *attr)
+static struct __vxge_hw_channel *
+__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
+                           enum __vxge_hw_channel_type type,
+                           u32 length, u32 per_dtr_space,
+                           void *userdata)
 {
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct __vxge_hw_ring *ring;
-        u32 ring_length;
-        struct vxge_hw_ring_config *config;
+        struct __vxge_hw_channel *channel;
         struct __vxge_hw_device *hldev;
+        int size = 0;
         u32 vp_id;
-        struct vxge_hw_mempool_cbs ring_mp_callback;
 
-        if ((vp == NULL) || (attr == NULL)) {
+        hldev = vph->vpath->hldev;
+        vp_id = vph->vpath->vp_id;
+
+        switch (type) {
+        case VXGE_HW_CHANNEL_TYPE_FIFO:
+                size = sizeof(struct __vxge_hw_fifo);
+                break;
+        case VXGE_HW_CHANNEL_TYPE_RING:
+                size = sizeof(struct __vxge_hw_ring);
+                break;
+        default:
+                break;
+        }
+
+        channel = kzalloc(size, GFP_KERNEL);
+        if (channel == NULL)
+                goto exit0;
+        INIT_LIST_HEAD(&channel->item);
+
+        channel->common_reg = hldev->common_reg;
+        channel->first_vp_id = hldev->first_vp_id;
+        channel->type = type;
+        channel->devh = hldev;
+        channel->vph = vph;
+        channel->userdata = userdata;
+        channel->per_dtr_space = per_dtr_space;
+        channel->length = length;
+        channel->vp_id = vp_id;
+
+        channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
+        if (channel->work_arr == NULL)
+                goto exit1;
+
+        channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
+        if (channel->free_arr == NULL)
+                goto exit1;
+        channel->free_ptr = length;
+
+        channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
+        if (channel->reserve_arr == NULL)
+                goto exit1;
+        channel->reserve_ptr = length;
+        channel->reserve_top = 0;
+
+        channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
+        if (channel->orig_arr == NULL)
+                goto exit1;
+
+        return channel;
+exit1:
+        __vxge_hw_channel_free(channel);
+
+exit0:
+        return NULL;
+}
+
+/*
+ * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
+ * Adds a block to block pool
+ */
+static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
+                                        void *block_addr,
+                                        u32 length,
+                                        struct pci_dev *dma_h,
+                                        struct pci_dev *acc_handle)
+{
+        struct __vxge_hw_blockpool *blockpool;
+        struct __vxge_hw_blockpool_entry *entry = NULL;
+        dma_addr_t dma_addr;
+        enum vxge_hw_status status = VXGE_HW_OK;
+        u32 req_out;
+
+        blockpool = &devh->block_pool;
+
+        if (block_addr == NULL) {
+                blockpool->req_out--;
                 status = VXGE_HW_FAIL;
                 goto exit;
         }
 
-        hldev = vp->vpath->hldev;
-        vp_id = vp->vpath->vp_id;
+        dma_addr = pci_map_single(devh->pdev, block_addr, length,
+                                PCI_DMA_BIDIRECTIONAL);
 
-        config = &hldev->config.vp_config[vp_id].ring;
+        if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
+                vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
+                blockpool->req_out--;
+                status = VXGE_HW_FAIL;
+                goto exit;
+        }
 
-        ring_length = config->ring_blocks *
-                        vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
+        if (!list_empty(&blockpool->free_entry_list))
+                entry = (struct __vxge_hw_blockpool_entry *)
+                        list_first_entry(&blockpool->free_entry_list,
+                                struct __vxge_hw_blockpool_entry,
+                                item);
 
-        ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
-                                                VXGE_HW_CHANNEL_TYPE_RING,
-                                                ring_length,
-                                                attr->per_rxd_space,
-                                                attr->userdata);
+        if (entry == NULL)
+                entry = vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
+        else
+                list_del(&entry->item);
 
-        if (ring == NULL) {
+        if (entry != NULL) {
+                entry->length = length;
+                entry->memblock = block_addr;
+                entry->dma_addr = dma_addr;
+                entry->acc_handle = acc_handle;
+                entry->dma_handle = dma_h;
+                list_add(&entry->item, &blockpool->free_block_list);
+                blockpool->pool_size++;
+                status = VXGE_HW_OK;
+        } else
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                goto exit;
-        }
 
-        vp->vpath->ringh = ring;
-        ring->vp_id = vp_id;
-        ring->vp_reg = vp->vpath->vp_reg;
-        ring->common_reg = hldev->common_reg;
-        ring->stats = &vp->vpath->sw_stats->ring_stats;
-        ring->config = config;
-        ring->callback = attr->callback;
-        ring->rxd_init = attr->rxd_init;
-        ring->rxd_term = attr->rxd_term;
-        ring->buffer_mode = config->buffer_mode;
-        ring->rxds_limit = config->rxds_limit;
+        blockpool->req_out--;
 
-        ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
-        ring->rxd_priv_size =
-                sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
-        ring->per_rxd_space = attr->per_rxd_space;
+        req_out = blockpool->req_out;
+exit:
+        return;
+}
 
-        ring->rxd_priv_size =
-                ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
-                VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
+static inline void
+vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, unsigned long size)
+{
+        gfp_t flags;
+        void *vaddr;
 
-        /* how many RxDs can fit into one block. Depends on configured
-         * buffer_mode. */
-        ring->rxds_per_block =
-                vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
+        if (in_interrupt())
+                flags = GFP_ATOMIC | GFP_DMA;
+        else
+                flags = GFP_KERNEL | GFP_DMA;
 
-        /* calculate actual RxD block private size */
-        ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
-        ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
-        ring->mempool = __vxge_hw_mempool_create(hldev,
-                                VXGE_HW_BLOCK_SIZE,
-                                VXGE_HW_BLOCK_SIZE,
-                                ring->rxdblock_priv_size,
-                                ring->config->ring_blocks,
-                                ring->config->ring_blocks,
-                                &ring_mp_callback,
-                                ring);
+        vaddr = kmalloc((size), flags);
 
-        if (ring->mempool == NULL) {
-                __vxge_hw_ring_delete(vp);
-                return VXGE_HW_ERR_OUT_OF_MEMORY;
-        }
+        vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
+}
 
-        status = __vxge_hw_channel_initialize(&ring->channel);
-        if (status != VXGE_HW_OK) {
-                __vxge_hw_ring_delete(vp);
-                goto exit;
+/*
+ * __vxge_hw_blockpool_blocks_add - Request additional blocks
+ */
+static
+void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
+{
+        u32 nreq = 0, i;
+
+        if ((blockpool->pool_size  +  blockpool->req_out) <
+                VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
+                nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
+                blockpool->req_out += nreq;
         }
 
-        /* Note:
-         * Specifying rxd_init callback means two things:
-         * 1) rxds need to be initialized by driver at channel-open time;
-         * 2) rxds need to be posted at channel-open time
-         *    (that's what the initial_replenish() below does)
-         * Currently we don't have a case when the 1) is done without the 2).
-         */
-        if (ring->rxd_init) {
-                status = vxge_hw_ring_replenish(ring);
-                if (status != VXGE_HW_OK) {
-                        __vxge_hw_ring_delete(vp);
+        for (i = 0; i < nreq; i++)
+                vxge_os_dma_malloc_async(
+                        ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
+                        blockpool->hldev, VXGE_HW_BLOCK_SIZE);
+}
+
+/*
+ * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
+ * Allocates a block of memory of given size, either from block pool
+ * or by calling vxge_os_dma_malloc()
+ */
+static void *__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
+                                        struct vxge_hw_mempool_dma *dma_object)
+{
+        struct __vxge_hw_blockpool_entry *entry = NULL;
+        struct __vxge_hw_blockpool  *blockpool;
+        void *memblock = NULL;
+        enum vxge_hw_status status = VXGE_HW_OK;
+
+        blockpool = &devh->block_pool;
+
+        if (size != blockpool->block_size) {
+
+                memblock = vxge_os_dma_malloc(devh->pdev, size,
+                                                &dma_object->handle,
+                                                &dma_object->acc_handle);
+
+                if (memblock == NULL) {
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
                         goto exit;
                 }
-        }
 
-        /* initial replenish will increment the counter in its post() routine,
-         * we have to reset it */
-        ring->stats->common_stats.usage_cnt = 0;
+                dma_object->addr = pci_map_single(devh->pdev, memblock, size,
+                                        PCI_DMA_BIDIRECTIONAL);
+
+                if (unlikely(pci_dma_mapping_error(devh->pdev,
+                                dma_object->addr))) {
+                        vxge_os_dma_free(devh->pdev, memblock,
+                                &dma_object->acc_handle);
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
+                        goto exit;
+                }
+
+        } else {
+
+                if (!list_empty(&blockpool->free_block_list))
+                        entry = (struct __vxge_hw_blockpool_entry *)
+                                list_first_entry(&blockpool->free_block_list,
+                                        struct __vxge_hw_blockpool_entry,
+                                        item);
+
+                if (entry != NULL) {
+                        list_del(&entry->item);
+                        dma_object->addr = entry->dma_addr;
+                        dma_object->handle = entry->dma_handle;
+                        dma_object->acc_handle = entry->acc_handle;
+                        memblock = entry->memblock;
+
+                        list_add(&entry->item,
+                                &blockpool->free_entry_list);
+                        blockpool->pool_size--;
+                }
+
+                if (memblock != NULL)
+                        __vxge_hw_blockpool_blocks_add(blockpool);
+        }
 exit:
-        return status;
+        return memblock;
 }
 
 /*
- * __vxge_hw_ring_abort - Returns the RxD
- * This function terminates the RxDs of ring
+ * __vxge_hw_blockpool_blocks_remove - Free additional blocks
  */
-static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
+static void
+__vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
 {
-        void *rxdh;
-        struct __vxge_hw_channel *channel;
-
-        channel = &ring->channel;
+        struct list_head *p, *n;
 
-        for (;;) {
-                vxge_hw_channel_dtr_try_complete(channel, &rxdh);
+        list_for_each_safe(p, n, &blockpool->free_block_list) {
 
-                if (rxdh == NULL)
+                if (blockpool->pool_size < blockpool->pool_max)
                         break;
 
-                vxge_hw_channel_dtr_complete(channel);
+                pci_unmap_single(
+                        ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
+                        ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
+                        ((struct __vxge_hw_blockpool_entry *)p)->length,
+                        PCI_DMA_BIDIRECTIONAL);
 
-                if (ring->rxd_term)
-                        ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
-                                channel->userdata);
+                vxge_os_dma_free(
+                        ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
+                        ((struct __vxge_hw_blockpool_entry *)p)->memblock,
+                        &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
 
-                vxge_hw_channel_dtr_free(channel, rxdh);
-        }
+                list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
 
-        return VXGE_HW_OK;
+                list_add(p, &blockpool->free_entry_list);
+
+                blockpool->pool_size--;
+
+        }
 }
 
 /*
- * __vxge_hw_ring_reset - Resets the ring
- * This function resets the ring during vpath reset operation
+ * __vxge_hw_blockpool_free - Frees the memory allcoated with
+ *                              __vxge_hw_blockpool_malloc
  */
-static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
+static void __vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
+                                     void *memblock, u32 size,
+                                     struct vxge_hw_mempool_dma *dma_object)
 {
+        struct __vxge_hw_blockpool_entry *entry = NULL;
+        struct __vxge_hw_blockpool  *blockpool;
         enum vxge_hw_status status = VXGE_HW_OK;
-        struct __vxge_hw_channel *channel;
 
-        channel = &ring->channel;
+        blockpool = &devh->block_pool;
 
-        __vxge_hw_ring_abort(ring);
+        if (size != blockpool->block_size) {
+                pci_unmap_single(devh->pdev, dma_object->addr, size,
+                        PCI_DMA_BIDIRECTIONAL);
+                vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
+        } else {
 
-        status = __vxge_hw_channel_reset(channel);
+                if (!list_empty(&blockpool->free_entry_list))
+                        entry = (struct __vxge_hw_blockpool_entry *)
+                                list_first_entry(&blockpool->free_entry_list,
+                                        struct __vxge_hw_blockpool_entry,
+                                        item);
 
-        if (status != VXGE_HW_OK)
-                goto exit;
+                if (entry == NULL)
+                        entry = vmalloc(sizeof(
+                                        struct __vxge_hw_blockpool_entry));
+                else
+                        list_del(&entry->item);
 
-        if (ring->rxd_init) {
-                status = vxge_hw_ring_replenish(ring);
-                if (status != VXGE_HW_OK)
-                        goto exit;
+                if (entry != NULL) {
+                        entry->length = size;
+                        entry->memblock = memblock;
+                        entry->dma_addr = dma_object->addr;
+                        entry->acc_handle = dma_object->acc_handle;
+                        entry->dma_handle = dma_object->handle;
+                        list_add(&entry->item,
+                                        &blockpool->free_block_list);
+                        blockpool->pool_size++;
+                        status = VXGE_HW_OK;
+                } else
+                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
+
+                if (status == VXGE_HW_OK)
+                        __vxge_hw_blockpool_blocks_remove(blockpool);
         }
-exit:
-        return status;
 }
 
 /*
- * __vxge_hw_ring_delete - Removes the ring
- * This function freeup the memory pool and removes the ring
+ * vxge_hw_mempool_destroy
  */
-static enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
+static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
 {
-        struct __vxge_hw_ring *ring = vp->vpath->ringh;
+        u32 i, j;
+        struct __vxge_hw_device *devh = mempool->devh;
 
-        __vxge_hw_ring_abort(ring);
+        for (i = 0; i < mempool->memblocks_allocated; i++) {
+                struct vxge_hw_mempool_dma *dma_object;
 
-        if (ring->mempool)
-                __vxge_hw_mempool_destroy(ring->mempool);
+                vxge_assert(mempool->memblocks_arr[i]);
+                vxge_assert(mempool->memblocks_dma_arr + i);
 
-        vp->vpath->ringh = NULL;
-        __vxge_hw_channel_free(&ring->channel);
+                dma_object = mempool->memblocks_dma_arr + i;
 
-        return VXGE_HW_OK;
+                for (j = 0; j < mempool->items_per_memblock; j++) {
+                        u32 index = i * mempool->items_per_memblock + j;
+
+                        /* to skip last partially filled(if any) memblock */
+                        if (index >= mempool->items_current)
+                                break;
+                }
+
+                vfree(mempool->memblocks_priv_arr[i]);
+
+                __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
+                                mempool->memblock_size, dma_object);
+        }
+
+        vfree(mempool->items_arr);
+        vfree(mempool->memblocks_dma_arr);
+        vfree(mempool->memblocks_priv_arr);
+        vfree(mempool->memblocks_arr);
+        vfree(mempool);
 }
 
 /*
@@ -1627,15 +2586,12 @@ __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
                  * allocate new memblock and its private part at once.
                  * This helps to minimize memory usage a lot. */
                 mempool->memblocks_priv_arr[i] =
-                                vmalloc(mempool->items_priv_size * n_items);
+                                vzalloc(mempool->items_priv_size * n_items);
                 if (mempool->memblocks_priv_arr[i] == NULL) {
                         status = VXGE_HW_ERR_OUT_OF_MEMORY;
                         goto exit;
                 }
 
-                memset(mempool->memblocks_priv_arr[i], 0,
-                             mempool->items_priv_size * n_items);
-
                 /* allocate DMA-capable memblock */
                 mempool->memblocks_arr[i] =
                         __vxge_hw_blockpool_malloc(mempool->devh,
@@ -1686,16 +2642,15 @@ exit:
  * with size enough to hold %items_initial number of items. Memory is
  * DMA-able but client must map/unmap before interoperating with the device.
  */
-static struct vxge_hw_mempool*
-__vxge_hw_mempool_create(
-        struct __vxge_hw_device *devh,
-        u32 memblock_size,
-        u32 item_size,
-        u32 items_priv_size,
-        u32 items_initial,
-        u32 items_max,
-        struct vxge_hw_mempool_cbs *mp_callback,
-        void *userdata)
+static struct vxge_hw_mempool *
+__vxge_hw_mempool_create(struct __vxge_hw_device *devh,
+                         u32 memblock_size,
+                         u32 item_size,
+                         u32 items_priv_size,
+                         u32 items_initial,
+                         u32 items_max,
+                         struct vxge_hw_mempool_cbs *mp_callback,
+                         void *userdata)
 {
         enum vxge_hw_status status = VXGE_HW_OK;
         u32 memblocks_to_allocate;
@@ -1707,13 +2662,11 @@ __vxge_hw_mempool_create(
                 goto exit;
         }
 
-        mempool = (struct vxge_hw_mempool *)
-                        vmalloc(sizeof(struct vxge_hw_mempool));
+        mempool = vzalloc(sizeof(struct vxge_hw_mempool));
         if (mempool == NULL) {
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 goto exit;
         }
-        memset(mempool, 0, sizeof(struct vxge_hw_mempool));
 
         mempool->devh                   = devh;
         mempool->memblock_size          = memblock_size;
@@ -1733,53 +2686,43 @@ __vxge_hw_mempool_create(
 
         /* allocate array of memblocks */
         mempool->memblocks_arr =
-                (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
+                vzalloc(sizeof(void *) * mempool->memblocks_max);
         if (mempool->memblocks_arr == NULL) {
                 __vxge_hw_mempool_destroy(mempool);
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 mempool = NULL;
                 goto exit;
         }
-        memset(mempool->memblocks_arr, 0,
-                sizeof(void *) * mempool->memblocks_max);
 
         /* allocate array of private parts of items per memblocks */
         mempool->memblocks_priv_arr =
-                (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
+                vzalloc(sizeof(void *) * mempool->memblocks_max);
         if (mempool->memblocks_priv_arr == NULL) {
                 __vxge_hw_mempool_destroy(mempool);
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 mempool = NULL;
                 goto exit;
         }
-        memset(mempool->memblocks_priv_arr, 0,
-                    sizeof(void *) * mempool->memblocks_max);
 
         /* allocate array of memblocks DMA objects */
-        mempool->memblocks_dma_arr = (struct vxge_hw_mempool_dma *)
-                vmalloc(sizeof(struct vxge_hw_mempool_dma) *
+        mempool->memblocks_dma_arr =
+                vzalloc(sizeof(struct vxge_hw_mempool_dma) *
                         mempool->memblocks_max);
-
         if (mempool->memblocks_dma_arr == NULL) {
                 __vxge_hw_mempool_destroy(mempool);
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 mempool = NULL;
                 goto exit;
         }
-        memset(mempool->memblocks_dma_arr, 0,
-                        sizeof(struct vxge_hw_mempool_dma) *
-                        mempool->memblocks_max);
 
         /* allocate hash array of items */
-        mempool->items_arr =
-                (void **) vmalloc(sizeof(void *) * mempool->items_max);
+        mempool->items_arr = vzalloc(sizeof(void *) * mempool->items_max);
         if (mempool->items_arr == NULL) {
                 __vxge_hw_mempool_destroy(mempool);
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 mempool = NULL;
                 goto exit;
         }
-        memset(mempool->items_arr, 0, sizeof(void *) * mempool->items_max);
 
         /* calculate initial number of memblocks */
         memblocks_to_allocate = (mempool->items_initial +
@@ -1801,122 +2744,188 @@ exit:
 }
 
 /*
- * vxge_hw_mempool_destroy
+ * __vxge_hw_ring_abort - Returns the RxD
+ * This function terminates the RxDs of ring
  */
-static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
+static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
 {
-        u32 i, j;
-        struct __vxge_hw_device *devh = mempool->devh;
-
-        for (i = 0; i < mempool->memblocks_allocated; i++) {
-                struct vxge_hw_mempool_dma *dma_object;
+        void *rxdh;
+        struct __vxge_hw_channel *channel;
 
-                vxge_assert(mempool->memblocks_arr[i]);
-                vxge_assert(mempool->memblocks_dma_arr + i);
+        channel = &ring->channel;
 
-                dma_object = mempool->memblocks_dma_arr + i;
+        for (;;) {
+                vxge_hw_channel_dtr_try_complete(channel, &rxdh);
 
-                for (j = 0; j < mempool->items_per_memblock; j++) {
-                        u32 index = i * mempool->items_per_memblock + j;
+                if (rxdh == NULL)
+                        break;
 
-                        /* to skip last partially filled(if any) memblock */
-                        if (index >= mempool->items_current)
-                                break;
-                }
+                vxge_hw_channel_dtr_complete(channel);
 
-                vfree(mempool->memblocks_priv_arr[i]);
+                if (ring->rxd_term)
+                        ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
+                                channel->userdata);
 
-                __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
-                                mempool->memblock_size, dma_object);
+                vxge_hw_channel_dtr_free(channel, rxdh);
         }
 
-        vfree(mempool->items_arr);
+        return VXGE_HW_OK;
+}
 
-        vfree(mempool->memblocks_dma_arr);
+/*
+ * __vxge_hw_ring_reset - Resets the ring
+ * This function resets the ring during vpath reset operation
+ */
+static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct __vxge_hw_channel *channel;
 
-        vfree(mempool->memblocks_priv_arr);
+        channel = &ring->channel;
 
-        vfree(mempool->memblocks_arr);
+        __vxge_hw_ring_abort(ring);
 
-        vfree(mempool);
+        status = __vxge_hw_channel_reset(channel);
+
+        if (status != VXGE_HW_OK)
+                goto exit;
+
+        if (ring->rxd_init) {
+                status = vxge_hw_ring_replenish(ring);
+                if (status != VXGE_HW_OK)
+                        goto exit;
+        }
+exit:
+        return status;
 }
 
 /*
- * __vxge_hw_device_fifo_config_check - Check fifo configuration.
- * Check the fifo configuration
+ * __vxge_hw_ring_delete - Removes the ring
+ * This function freeup the memory pool and removes the ring
  */
-enum vxge_hw_status
-__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
+static enum vxge_hw_status
+__vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
 {
-        if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
-             (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
-                return VXGE_HW_BADCFG_FIFO_BLOCKS;
+        struct __vxge_hw_ring *ring = vp->vpath->ringh;
+
+        __vxge_hw_ring_abort(ring);
+
+        if (ring->mempool)
+                __vxge_hw_mempool_destroy(ring->mempool);
+
+        vp->vpath->ringh = NULL;
+        __vxge_hw_channel_free(&ring->channel);
 
         return VXGE_HW_OK;
 }
 
 /*
- * __vxge_hw_device_vpath_config_check - Check vpath configuration.
- * Check the vpath configuration
+ * __vxge_hw_ring_create - Create a Ring
+ * This function creates Ring and initializes it.
  */
 static enum vxge_hw_status
-__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
+__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
+                      struct vxge_hw_ring_attr *attr)
 {
-        enum vxge_hw_status status;
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct __vxge_hw_ring *ring;
+        u32 ring_length;
+        struct vxge_hw_ring_config *config;
+        struct __vxge_hw_device *hldev;
+        u32 vp_id;
+        struct vxge_hw_mempool_cbs ring_mp_callback;
 
-        if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
-                (vp_config->min_bandwidth >
-                                        VXGE_HW_VPATH_BANDWIDTH_MAX))
-                return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
+        if ((vp == NULL) || (attr == NULL)) {
+                status = VXGE_HW_FAIL;
+                goto exit;
+        }
 
-        status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
-        if (status != VXGE_HW_OK)
-                return status;
+        hldev = vp->vpath->hldev;
+        vp_id = vp->vpath->vp_id;
 
-        if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
-                ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
-                (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
-                return VXGE_HW_BADCFG_VPATH_MTU;
+        config = &hldev->config.vp_config[vp_id].ring;
 
-        if ((vp_config->rpa_strip_vlan_tag !=
-                VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
-                (vp_config->rpa_strip_vlan_tag !=
-                VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
-                (vp_config->rpa_strip_vlan_tag !=
-                VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
-                return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
+        ring_length = config->ring_blocks *
+                        vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
 
-        return VXGE_HW_OK;
-}
+        ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
+                                                VXGE_HW_CHANNEL_TYPE_RING,
+                                                ring_length,
+                                                attr->per_rxd_space,
+                                                attr->userdata);
+        if (ring == NULL) {
+                status = VXGE_HW_ERR_OUT_OF_MEMORY;
+                goto exit;
+        }
 
-/*
- * __vxge_hw_device_config_check - Check device configuration.
- * Check the device configuration
- */
-enum vxge_hw_status
-__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
-{
-        u32 i;
-        enum vxge_hw_status status;
+        vp->vpath->ringh = ring;
+        ring->vp_id = vp_id;
+        ring->vp_reg = vp->vpath->vp_reg;
+        ring->common_reg = hldev->common_reg;
+        ring->stats = &vp->vpath->sw_stats->ring_stats;
+        ring->config = config;
+        ring->callback = attr->callback;
+        ring->rxd_init = attr->rxd_init;
+        ring->rxd_term = attr->rxd_term;
+        ring->buffer_mode = config->buffer_mode;
+        ring->rxds_limit = config->rxds_limit;
 
-        if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
-           (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
-           (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
-           (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
-                return VXGE_HW_BADCFG_INTR_MODE;
+        ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
+        ring->rxd_priv_size =
+                sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
+        ring->per_rxd_space = attr->per_rxd_space;
 
-        if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
-           (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
-                return VXGE_HW_BADCFG_RTS_MAC_EN;
+        ring->rxd_priv_size =
+                ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
+                VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
 
-        for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-                status = __vxge_hw_device_vpath_config_check(
-                                &new_config->vp_config[i]);
-                if (status != VXGE_HW_OK)
-                        return status;
+        /* how many RxDs can fit into one block. Depends on configured
+         * buffer_mode. */
+        ring->rxds_per_block =
+                vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
+
+        /* calculate actual RxD block private size */
+        ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
+        ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
+        ring->mempool = __vxge_hw_mempool_create(hldev,
+                                VXGE_HW_BLOCK_SIZE,
+                                VXGE_HW_BLOCK_SIZE,
+                                ring->rxdblock_priv_size,
+                                ring->config->ring_blocks,
+                                ring->config->ring_blocks,
+                                &ring_mp_callback,
+                                ring);
+        if (ring->mempool == NULL) {
+                __vxge_hw_ring_delete(vp);
+                return VXGE_HW_ERR_OUT_OF_MEMORY;
         }
 
-        return VXGE_HW_OK;
+        status = __vxge_hw_channel_initialize(&ring->channel);
+        if (status != VXGE_HW_OK) {
+                __vxge_hw_ring_delete(vp);
+                goto exit;
+        }
+
+        /* Note:
+         * Specifying rxd_init callback means two things:
+         * 1) rxds need to be initialized by driver at channel-open time;
+         * 2) rxds need to be posted at channel-open time
+         *    (that's what the initial_replenish() below does)
+         * Currently we don't have a case when the 1) is done without the 2).
+         */
+        if (ring->rxd_init) {
+                status = vxge_hw_ring_replenish(ring);
+                if (status != VXGE_HW_OK) {
+                        __vxge_hw_ring_delete(vp);
+                        goto exit;
+                }
+        }
+
+        /* initial replenish will increment the counter in its post() routine,
+         * we have to reset it */
+        ring->stats->common_stats.usage_cnt = 0;
+exit:
+        return status;
 }
 
 /*
@@ -1938,7 +2947,6 @@ vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
         device_config->rts_mac_en =  VXGE_HW_RTS_MAC_DEFAULT;
 
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
-
                 device_config->vp_config[i].vp_id = i;
 
                 device_config->vp_config[i].min_bandwidth =
@@ -2078,61 +3086,6 @@ vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
 }
 
 /*
- * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
- * Set the swapper bits appropriately for the lagacy section.
- */
-static enum vxge_hw_status
-__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
-{
-        u64 val64;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        val64 = readq(&legacy_reg->toc_swapper_fb);
-
-        wmb();
-
-        switch (val64) {
-
-        case VXGE_HW_SWAPPER_INITIAL_VALUE:
-                return status;
-
-        case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
-                writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
-                        &legacy_reg->pifm_rd_swap_en);
-                writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
-                        &legacy_reg->pifm_rd_flip_en);
-                writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
-                        &legacy_reg->pifm_wr_swap_en);
-                writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
-                        &legacy_reg->pifm_wr_flip_en);
-                break;
-
-        case VXGE_HW_SWAPPER_BYTE_SWAPPED:
-                writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
-                        &legacy_reg->pifm_rd_swap_en);
-                writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
-                        &legacy_reg->pifm_wr_swap_en);
-                break;
-
-        case VXGE_HW_SWAPPER_BIT_FLIPPED:
-                writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
-                        &legacy_reg->pifm_rd_flip_en);
-                writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
-                        &legacy_reg->pifm_wr_flip_en);
-                break;
-        }
-
-        wmb();
-
-        val64 = readq(&legacy_reg->toc_swapper_fb);
-
-        if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
-                status = VXGE_HW_ERR_SWAPPER_CTRL;
-
-        return status;
-}
-
-/*
  * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
  * Set the swapper bits appropriately for the vpath.
  */
@@ -2156,9 +3109,8 @@ __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
  * Set the swapper bits appropriately for the vpath.
  */
 static enum vxge_hw_status
-__vxge_hw_kdfc_swapper_set(
-        struct vxge_hw_legacy_reg __iomem *legacy_reg,
-        struct vxge_hw_vpath_reg __iomem *vpath_reg)
+__vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg,
+                           struct vxge_hw_vpath_reg __iomem *vpath_reg)
 {
         u64 val64;
 
@@ -2408,6 +3360,69 @@ exit:
 }
 
 /*
+ * __vxge_hw_fifo_abort - Returns the TxD
+ * This function terminates the TxDs of fifo
+ */
+static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
+{
+        void *txdlh;
+
+        for (;;) {
+                vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
+
+                if (txdlh == NULL)
+                        break;
+
+                vxge_hw_channel_dtr_complete(&fifo->channel);
+
+                if (fifo->txdl_term) {
+                        fifo->txdl_term(txdlh,
+                        VXGE_HW_TXDL_STATE_POSTED,
+                        fifo->channel.userdata);
+                }
+
+                vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
+        }
+
+        return VXGE_HW_OK;
+}
+
+/*
+ * __vxge_hw_fifo_reset - Resets the fifo
+ * This function resets the fifo during vpath reset operation
+ */
+static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+
+        __vxge_hw_fifo_abort(fifo);
+        status = __vxge_hw_channel_reset(&fifo->channel);
+
+        return status;
+}
+
+/*
+ * __vxge_hw_fifo_delete - Removes the FIFO
+ * This function freeup the memory pool and removes the FIFO
+ */
+static enum vxge_hw_status
+__vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
+{
+        struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
+
+        __vxge_hw_fifo_abort(fifo);
+
+        if (fifo->mempool)
+                __vxge_hw_mempool_destroy(fifo->mempool);
+
+        vp->vpath->fifoh = NULL;
+
+        __vxge_hw_channel_free(&fifo->channel);
+
+        return VXGE_HW_OK;
+}
+
+/*
  * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
  * list callback
  * This function is callback passed to __vxge_hw_mempool_create to create memory
@@ -2453,7 +3468,7 @@ __vxge_hw_fifo_mempool_item_alloc(
  * __vxge_hw_fifo_create - Create a FIFO
  * This function creates FIFO and initializes it.
  */
-enum vxge_hw_status
+static enum vxge_hw_status
 __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
                       struct vxge_hw_fifo_attr *attr)
 {
@@ -2572,68 +3587,6 @@ exit:
 }
 
 /*
- * __vxge_hw_fifo_abort - Returns the TxD
- * This function terminates the TxDs of fifo
- */
-static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
-{
-        void *txdlh;
-
-        for (;;) {
-                vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
-
-                if (txdlh == NULL)
-                        break;
-
-                vxge_hw_channel_dtr_complete(&fifo->channel);
-
-                if (fifo->txdl_term) {
-                        fifo->txdl_term(txdlh,
-                        VXGE_HW_TXDL_STATE_POSTED,
-                        fifo->channel.userdata);
-                }
-
-                vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
-        }
-
-        return VXGE_HW_OK;
-}
-
-/*
- * __vxge_hw_fifo_reset - Resets the fifo
- * This function resets the fifo during vpath reset operation
- */
-static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        __vxge_hw_fifo_abort(fifo);
-        status = __vxge_hw_channel_reset(&fifo->channel);
-
-        return status;
-}
-
-/*
- * __vxge_hw_fifo_delete - Removes the FIFO
- * This function freeup the memory pool and removes the FIFO
- */
-enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
-{
-        struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
-
-        __vxge_hw_fifo_abort(fifo);
-
-        if (fifo->mempool)
-                __vxge_hw_mempool_destroy(fifo->mempool);
-
-        vp->vpath->fifoh = NULL;
-
-        __vxge_hw_channel_free(&fifo->channel);
-
-        return VXGE_HW_OK;
-}
-
-/*
  * __vxge_hw_vpath_pci_read - Read the content of given address
  *                          in pci config space.
  * Read from the vpath pci config space.
@@ -2675,297 +3628,6 @@ exit:
         return status;
 }
 
-/*
- * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
- * Returns the function number of the vpath.
- */
-static u32
-__vxge_hw_vpath_func_id_get(u32 vp_id,
-        struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
-{
-        u64 val64;
-
-        val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
-
-        return
-         (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
-}
-
-/*
- * __vxge_hw_read_rts_ds - Program RTS steering critieria
- */
-static inline void
-__vxge_hw_read_rts_ds(struct vxge_hw_vpath_reg __iomem *vpath_reg,
-                      u64 dta_struct_sel)
-{
-        writeq(0, &vpath_reg->rts_access_steer_ctrl);
-        wmb();
-        writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0);
-        writeq(0, &vpath_reg->rts_access_steer_data1);
-        wmb();
-}
-
-
-/*
- * __vxge_hw_vpath_card_info_get - Get the serial numbers,
- * part number and product description.
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_card_info_get(
-        u32 vp_id,
-        struct vxge_hw_vpath_reg __iomem *vpath_reg,
-        struct vxge_hw_device_hw_info *hw_info)
-{
-        u32 i, j;
-        u64 val64;
-        u64 data1 = 0ULL;
-        u64 data2 = 0ULL;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        u8 *serial_number = hw_info->serial_number;
-        u8 *part_number = hw_info->part_number;
-        u8 *product_desc = hw_info->product_desc;
-
-        __vxge_hw_read_rts_ds(vpath_reg,
-                VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER);
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vpath_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
-
-        if (status != VXGE_HW_OK)
-                return status;
-
-        val64 = readq(&vpath_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
-                data1 = readq(&vpath_reg->rts_access_steer_data0);
-                ((u64 *)serial_number)[0] = be64_to_cpu(data1);
-
-                data2 = readq(&vpath_reg->rts_access_steer_data1);
-                ((u64 *)serial_number)[1] = be64_to_cpu(data2);
-                status = VXGE_HW_OK;
-        } else
-                *serial_number = 0;
-
-        __vxge_hw_read_rts_ds(vpath_reg,
-                        VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER);
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vpath_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
-
-        if (status != VXGE_HW_OK)
-                return status;
-
-        val64 = readq(&vpath_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
-
-                data1 = readq(&vpath_reg->rts_access_steer_data0);
-                ((u64 *)part_number)[0] = be64_to_cpu(data1);
-
-                data2 = readq(&vpath_reg->rts_access_steer_data1);
-                ((u64 *)part_number)[1] = be64_to_cpu(data2);
-
-                status = VXGE_HW_OK;
-
-        } else
-                *part_number = 0;
-
-        j = 0;
-
-        for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
-             i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
-
-                __vxge_hw_read_rts_ds(vpath_reg, i);
-
-                val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-                status = __vxge_hw_pio_mem_write64(val64,
-                                &vpath_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
-
-                if (status != VXGE_HW_OK)
-                        return status;
-
-                val64 = readq(&vpath_reg->rts_access_steer_ctrl);
-
-                if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
-
-                        data1 = readq(&vpath_reg->rts_access_steer_data0);
-                        ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
-
-                        data2 = readq(&vpath_reg->rts_access_steer_data1);
-                        ((u64 *)product_desc)[j++] = be64_to_cpu(data2);
-
-                        status = VXGE_HW_OK;
-                } else
-                        *product_desc = 0;
-        }
-
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_fw_ver_get - Get the fw version
- * Returns FW Version
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_fw_ver_get(
-        u32 vp_id,
-        struct vxge_hw_vpath_reg __iomem *vpath_reg,
-        struct vxge_hw_device_hw_info *hw_info)
-{
-        u64 val64;
-        u64 data1 = 0ULL;
-        u64 data2 = 0ULL;
-        struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
-        struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
-        struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
-        struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vpath_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
-
-        if (status != VXGE_HW_OK)
-                goto exit;
-
-        val64 = readq(&vpath_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
-
-                data1 = readq(&vpath_reg->rts_access_steer_data0);
-                data2 = readq(&vpath_reg->rts_access_steer_data1);
-
-                fw_date->day =
-                        (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(
-                                                data1);
-                fw_date->month =
-                        (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(
-                                                data1);
-                fw_date->year =
-                        (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(
-                                                data1);
-
-                snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
-                        fw_date->month, fw_date->day, fw_date->year);
-
-                fw_version->major =
-                    (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1);
-                fw_version->minor =
-                    (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1);
-                fw_version->build =
-                    (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1);
-
-                snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
-                    fw_version->major, fw_version->minor, fw_version->build);
-
-                flash_date->day =
-                  (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data2);
-                flash_date->month =
-                 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data2);
-                flash_date->year =
-                 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data2);
-
-                snprintf(flash_date->date, VXGE_HW_FW_STRLEN,
-                        "%2.2d/%2.2d/%4.4d",
-                        flash_date->month, flash_date->day, flash_date->year);
-
-                flash_version->major =
-                 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data2);
-                flash_version->minor =
-                 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data2);
-                flash_version->build =
-                 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data2);
-
-                snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
-                        flash_version->major, flash_version->minor,
-                        flash_version->build);
-
-                status = VXGE_HW_OK;
-
-        } else
-                status = VXGE_HW_FAIL;
-exit:
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
- * Returns pci function mode
- */
-static u64
-__vxge_hw_vpath_pci_func_mode_get(
-        u32  vp_id,
-        struct vxge_hw_vpath_reg __iomem *vpath_reg)
-{
-        u64 val64;
-        u64 data1 = 0ULL;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        __vxge_hw_read_rts_ds(vpath_reg,
-                VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE);
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vpath_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
-
-        if (status != VXGE_HW_OK)
-                goto exit;
-
-        val64 = readq(&vpath_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
-                data1 = readq(&vpath_reg->rts_access_steer_data0);
-                status = VXGE_HW_OK;
-        } else {
-                data1 = 0;
-                status = VXGE_HW_FAIL;
-        }
-exit:
-        return data1;
-}
-
 /**
  * vxge_hw_device_flick_link_led - Flick (blink) link LED.
  * @hldev: HW device.
@@ -2974,37 +3636,24 @@ exit:
  * Flicker the link LED.
  */
 enum vxge_hw_status
-vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev,
-                               u64 on_off)
+vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
 {
-        u64 val64;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
+        struct __vxge_hw_virtualpath *vpath;
+        u64 data0, data1 = 0, steer_ctrl = 0;
+        enum vxge_hw_status status;
 
         if (hldev == NULL) {
                 status = VXGE_HW_ERR_INVALID_DEVICE;
                 goto exit;
         }
 
-        vp_reg = hldev->vpath_reg[hldev->first_vp_id];
+        vpath = &hldev->virtual_paths[hldev->first_vp_id];
 
-        writeq(0, &vp_reg->rts_access_steer_ctrl);
-        wmb();
-        writeq(on_off, &vp_reg->rts_access_steer_data0);
-        writeq(0, &vp_reg->rts_access_steer_data1);
-        wmb();
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vp_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
+        data0 = on_off;
+        status = vxge_hw_vpath_fw_api(vpath,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
+                        VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
+                        0, &data0, &data1, &steer_ctrl);
 exit:
         return status;
 }
@@ -3013,63 +3662,38 @@ exit:
  * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
  */
 enum vxge_hw_status
-__vxge_hw_vpath_rts_table_get(
-        struct __vxge_hw_vpath_handle *vp,
-        u32 action, u32 rts_table, u32 offset, u64 *data1, u64 *data2)
+__vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
+                              u32 action, u32 rts_table, u32 offset,
+                              u64 *data0, u64 *data1)
 {
-        u64 val64;
-        struct __vxge_hw_virtualpath *vpath;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
-
-        enum vxge_hw_status status = VXGE_HW_OK;
+        enum vxge_hw_status status;
+        u64 steer_ctrl = 0;
 
         if (vp == NULL) {
                 status = VXGE_HW_ERR_INVALID_HANDLE;
                 goto exit;
         }
 
-        vpath = vp->vpath;
-        vp_reg = vpath->vp_reg;
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
-
         if ((rts_table ==
-                VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
+             VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
             (rts_table ==
-                VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
+             VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
             (rts_table ==
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
+             VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
             (rts_table ==
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
-                val64 = val64 | VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
+             VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
+                steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
         }
 
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vp_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                vpath->hldev->config.device_poll_millis);
-
+        status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
+                                      data0, data1, &steer_ctrl);
         if (status != VXGE_HW_OK)
                 goto exit;
 
-        val64 = readq(&vp_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
-
-                *data1 = readq(&vp_reg->rts_access_steer_data0);
-
-                if ((rts_table ==
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
-                (rts_table ==
-                VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
-                        *data2 = readq(&vp_reg->rts_access_steer_data1);
-                }
-                status = VXGE_HW_OK;
-        } else
-                status = VXGE_HW_FAIL;
+        if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
+            (rts_table !=
+             VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
+                *data1 = 0;
 exit:
         return status;
 }
@@ -3078,107 +3702,27 @@ exit:
  * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
  */
 enum vxge_hw_status
-__vxge_hw_vpath_rts_table_set(
-        struct __vxge_hw_vpath_handle *vp, u32 action, u32 rts_table,
-        u32 offset, u64 data1, u64 data2)
+__vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
+                              u32 rts_table, u32 offset, u64 steer_data0,
+                              u64 steer_data1)
 {
-        u64 val64;
-        struct __vxge_hw_virtualpath *vpath;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
+        u64 data0, data1 = 0, steer_ctrl = 0;
+        enum vxge_hw_status status;
 
         if (vp == NULL) {
                 status = VXGE_HW_ERR_INVALID_HANDLE;
                 goto exit;
         }
 
-        vpath = vp->vpath;
-        vp_reg = vpath->vp_reg;
-
-        writeq(data1, &vp_reg->rts_access_steer_data0);
-        wmb();
+        data0 = steer_data0;
 
         if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
             (rts_table ==
-                VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
-                writeq(data2, &vp_reg->rts_access_steer_data1);
-                wmb();
-        }
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vp_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                vpath->hldev->config.device_poll_millis);
-
-        if (status != VXGE_HW_OK)
-                goto exit;
-
-        val64 = readq(&vp_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)
-                status = VXGE_HW_OK;
-        else
-                status = VXGE_HW_FAIL;
-exit:
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
- *               from MAC address table.
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_addr_get(
-        u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg,
-        u8 (macaddr)[ETH_ALEN], u8 (macaddr_mask)[ETH_ALEN])
-{
-        u32 i;
-        u64 val64;
-        u64 data1 = 0ULL;
-        u64 data2 = 0ULL;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
-                VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vpath_reg->rts_access_steer_ctrl,
-                                VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
-                                VXGE_HW_DEF_DEVICE_POLL_MILLIS);
-
-        if (status != VXGE_HW_OK)
-                goto exit;
-
-        val64 = readq(&vpath_reg->rts_access_steer_ctrl);
-
-        if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
+             VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
+                data1 = steer_data1;
 
-                data1 = readq(&vpath_reg->rts_access_steer_data0);
-                data2 = readq(&vpath_reg->rts_access_steer_data1);
-
-                data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
-                data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
-                                                        data2);
-
-                for (i = ETH_ALEN; i > 0; i--) {
-                        macaddr[i-1] = (u8)(data1 & 0xFF);
-                        data1 >>= 8;
-
-                        macaddr_mask[i-1] = (u8)(data2 & 0xFF);
-                        data2 >>= 8;
-                }
-                status = VXGE_HW_OK;
-        } else
-                status = VXGE_HW_FAIL;
+        status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
+                                      &data0, &data1, &steer_ctrl);
 exit:
         return status;
 }
@@ -3204,6 +3748,8 @@ enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
                      VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
                      VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
                         0, &data0, &data1);
+        if (status != VXGE_HW_OK)
+                goto exit;
 
         data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
                         VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
@@ -3771,10 +4317,10 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
         vp_reg = vpath->vp_reg;
         config = vpath->vp_config;
 
-        writeq((u64)0, &vp_reg->tim_dest_addr);
-        writeq((u64)0, &vp_reg->tim_vpath_map);
-        writeq((u64)0, &vp_reg->tim_bitmap);
-        writeq((u64)0, &vp_reg->tim_remap);
+        writeq(0, &vp_reg->tim_dest_addr);
+        writeq(0, &vp_reg->tim_vpath_map);
+        writeq(0, &vp_reg->tim_bitmap);
+        writeq(0, &vp_reg->tim_remap);
 
         if (config->ring.enable == VXGE_HW_RING_ENABLE)
                 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
@@ -3876,8 +4422,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
 
                 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
-                        val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
-                                        config->tti.util_sel);
+                        val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
                 }
 
                 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
@@ -3981,8 +4526,7 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
 
                 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
                         val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
-                        val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
-                                        config->rti.util_sel);
+                        val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(vp_id);
                 }
 
                 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
@@ -4003,11 +4547,15 @@ __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
         writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
         writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
 
+        val64 = VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_PRD(150);
+        val64 |= VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(0);
+        val64 |= VXGE_HW_TIM_WRKLD_CLC_CNT_RX_TX(3);
+        writeq(val64, &vp_reg->tim_wrkld_clc);
+
         return status;
 }
 
-void
-vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
+void vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
 {
         struct __vxge_hw_virtualpath *vpath;
         struct vxge_hw_vpath_reg __iomem *vp_reg;
@@ -4018,17 +4566,15 @@ vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
         vp_reg = vpath->vp_reg;
         config = vpath->vp_config;
 
-        if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
+        if (config->fifo.enable == VXGE_HW_FIFO_ENABLE &&
+            config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
+                config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
                 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
-
-                if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
-                        config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
-                        val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
-                        writeq(val64,
-                        &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
-                }
+                val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
+                writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
         }
 }
+
 /*
  * __vxge_hw_vpath_initialize
  * This routine is the final phase of init which initializes the
@@ -4052,22 +4598,18 @@ __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
         vp_reg = vpath->vp_reg;
 
         status =  __vxge_hw_vpath_swapper_set(vpath->vp_reg);
-
         if (status != VXGE_HW_OK)
                 goto exit;
 
         status =  __vxge_hw_vpath_mac_configure(hldev, vp_id);
-
         if (status != VXGE_HW_OK)
                 goto exit;
 
         status =  __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
-
         if (status != VXGE_HW_OK)
                 goto exit;
 
         status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
-
         if (status != VXGE_HW_OK)
                 goto exit;
 
@@ -4075,7 +4617,6 @@ __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
 
         /* Get MRRS value from device control */
         status  = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
-
         if (status == VXGE_HW_OK) {
                 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
                 val64 &=
@@ -4099,6 +4640,28 @@ exit:
 }
 
 /*
+ * __vxge_hw_vp_terminate - Terminate Virtual Path structure
+ * This routine closes all channels it opened and freeup memory
+ */
+static void __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
+{
+        struct __vxge_hw_virtualpath *vpath;
+
+        vpath = &hldev->virtual_paths[vp_id];
+
+        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
+                goto exit;
+
+        VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
+                vpath->hldev->tim_int_mask1, vpath->vp_id);
+        hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
+
+        memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
+exit:
+        return;
+}
+
+/*
  * __vxge_hw_vp_initialize - Initialize Virtual Path structure
  * This routine is the initial phase of init which resets the vpath and
  * initializes the software support structures.
@@ -4117,6 +4680,7 @@ __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
 
         vpath = &hldev->virtual_paths[vp_id];
 
+        spin_lock_init(&hldev->virtual_paths[vp_id].lock);
         vpath->vp_id = vp_id;
         vpath->vp_open = VXGE_HW_VP_OPEN;
         vpath->hldev = hldev;
@@ -4127,14 +4691,12 @@ __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
         __vxge_hw_vpath_reset(hldev, vp_id);
 
         status = __vxge_hw_vpath_reset_check(vpath);
-
         if (status != VXGE_HW_OK) {
                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
                 goto exit;
         }
 
         status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
-
         if (status != VXGE_HW_OK) {
                 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
                 goto exit;
@@ -4148,7 +4710,6 @@ __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
                 hldev->tim_int_mask1, vp_id);
 
         status = __vxge_hw_vpath_initialize(hldev, vp_id);
-
         if (status != VXGE_HW_OK)
                 __vxge_hw_vp_terminate(hldev, vp_id);
 exit:
@@ -4156,29 +4717,6 @@ exit:
 }
 
 /*
- * __vxge_hw_vp_terminate - Terminate Virtual Path structure
- * This routine closes all channels it opened and freeup memory
- */
-static void
-__vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
-{
-        struct __vxge_hw_virtualpath *vpath;
-
-        vpath = &hldev->virtual_paths[vp_id];
-
-        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
-                goto exit;
-
-        VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
-                vpath->hldev->tim_int_mask1, vpath->vp_id);
-        hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
-
-        memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
-exit:
-        return;
-}
-
-/*
  * vxge_hw_vpath_mtu_set - Set MTU.
  * Set new MTU value. Example, to use jumbo frames:
  * vxge_hw_vpath_mtu_set(my_device, 9600);
@@ -4215,6 +4753,64 @@ exit:
 }
 
 /*
+ * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
+ * Enable the DMA vpath statistics. The function is to be called to re-enable
+ * the adapter to update stats into the host memory
+ */
+static enum vxge_hw_status
+vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct __vxge_hw_virtualpath *vpath;
+
+        vpath = vp->vpath;
+
+        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
+                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
+                goto exit;
+        }
+
+        memcpy(vpath->hw_stats_sav, vpath->hw_stats,
+                        sizeof(struct vxge_hw_vpath_stats_hw_info));
+
+        status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
+exit:
+        return status;
+}
+
+/*
+ * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
+ * This function allocates a block from block pool or from the system
+ */
+static struct __vxge_hw_blockpool_entry *
+__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
+{
+        struct __vxge_hw_blockpool_entry *entry = NULL;
+        struct __vxge_hw_blockpool  *blockpool;
+
+        blockpool = &devh->block_pool;
+
+        if (size == blockpool->block_size) {
+
+                if (!list_empty(&blockpool->free_block_list))
+                        entry = (struct __vxge_hw_blockpool_entry *)
+                                list_first_entry(&blockpool->free_block_list,
+                                        struct __vxge_hw_blockpool_entry,
+                                        item);
+
+                if (entry != NULL) {
+                        list_del(&entry->item);
+                        blockpool->pool_size--;
+                }
+        }
+
+        if (entry != NULL)
+                __vxge_hw_blockpool_blocks_add(blockpool);
+
+        return entry;
+}
+
+/*
  * vxge_hw_vpath_open - Open a virtual path on a given adapter
  * This function is used to open access to virtual path of an
  * adapter for offload, GRO operations. This function returns
@@ -4238,19 +4834,15 @@ vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
 
         status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
                         &hldev->config.vp_config[attr->vp_id]);
-
         if (status != VXGE_HW_OK)
                 goto vpath_open_exit1;
 
-        vp = (struct __vxge_hw_vpath_handle *)
-                vmalloc(sizeof(struct __vxge_hw_vpath_handle));
+        vp = vzalloc(sizeof(struct __vxge_hw_vpath_handle));
         if (vp == NULL) {
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 goto vpath_open_exit2;
         }
 
-        memset(vp, 0, sizeof(struct __vxge_hw_vpath_handle));
-
         vp->vpath = vpath;
 
         if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
@@ -4273,7 +4865,6 @@ vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
 
         vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
                                 VXGE_HW_BLOCK_SIZE);
-
         if (vpath->stats_block == NULL) {
                 status = VXGE_HW_ERR_OUT_OF_MEMORY;
                 goto vpath_open_exit8;
@@ -4332,19 +4923,20 @@ vpath_open_exit1:
  * This function is used to close access to virtual path opened
  * earlier.
  */
-void
-vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
+void vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
 {
-        struct __vxge_hw_virtualpath *vpath = NULL;
+        struct __vxge_hw_virtualpath *vpath = vp->vpath;
+        struct __vxge_hw_ring *ring = vpath->ringh;
+        struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
         u64 new_count, val64, val164;
-        struct __vxge_hw_ring *ring;
 
-        vpath = vp->vpath;
-        ring = vpath->ringh;
+        if (vdev->titan1) {
+                new_count = readq(&vpath->vp_reg->rxdmem_size);
+                new_count &= 0x1fff;
+        } else
+                new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
 
-        new_count = readq(&vpath->vp_reg->rxdmem_size);
-        new_count &= 0x1fff;
-        val164 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count));
+        val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
 
         writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
                 &vpath->vp_reg->prc_rxd_doorbell);
@@ -4367,6 +4959,29 @@ vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
 }
 
 /*
+ * __vxge_hw_blockpool_block_free - Frees a block from block pool
+ * @devh: Hal device
+ * @entry: Entry of block to be freed
+ *
+ * This function frees a block from block pool
+ */
+static void
+__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
+                               struct __vxge_hw_blockpool_entry *entry)
+{
+        struct __vxge_hw_blockpool  *blockpool;
+
+        blockpool = &devh->block_pool;
+
+        if (entry->length == blockpool->block_size) {
+                list_add(&entry->item, &blockpool->free_block_list);
+                blockpool->pool_size++;
+        }
+
+        __vxge_hw_blockpool_blocks_remove(blockpool);
+}
+
+/*
  * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
  * This function is used to close access to virtual path opened
  * earlier.
@@ -4414,7 +5029,9 @@ enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
 
         __vxge_hw_vp_terminate(devh, vp_id);
 
+        spin_lock(&vpath->lock);
         vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
+        spin_unlock(&vpath->lock);
 
 vpath_close_exit:
         return status;
@@ -4515,730 +5132,3 @@ vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
         __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
                 &hldev->common_reg->cmn_rsthdlr_cfg1);
 }
-
-/*
- * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
- * Enable the DMA vpath statistics. The function is to be called to re-enable
- * the adapter to update stats into the host memory
- */
-static enum vxge_hw_status
-vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct __vxge_hw_virtualpath *vpath;
-
-        vpath = vp->vpath;
-
-        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
-                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
-                goto exit;
-        }
-
-        memcpy(vpath->hw_stats_sav, vpath->hw_stats,
-                        sizeof(struct vxge_hw_vpath_stats_hw_info));
-
-        status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
-exit:
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_stats_access - Get the statistics from the given location
- *                           and offset and perform an operation
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
-                             u32 operation, u32 offset, u64 *stat)
-{
-        u64 val64;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
-
-        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
-                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
-                goto vpath_stats_access_exit;
-        }
-
-        vp_reg = vpath->vp_reg;
-
-        val64 =  VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
-                 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
-                 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
-
-        status = __vxge_hw_pio_mem_write64(val64,
-                                &vp_reg->xmac_stats_access_cmd,
-                                VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
-                                vpath->hldev->config.device_poll_millis);
-
-        if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
-                *stat = readq(&vp_reg->xmac_stats_access_data);
-        else
-                *stat = 0;
-
-vpath_stats_access_exit:
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_xmac_tx_stats_get(
-        struct __vxge_hw_virtualpath *vpath,
-        struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
-{
-        u64 *val64;
-        int i;
-        u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        val64 = (u64 *) vpath_tx_stats;
-
-        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
-                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
-                goto exit;
-        }
-
-        for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
-                status = __vxge_hw_vpath_stats_access(vpath,
-                                        VXGE_HW_STATS_OP_READ,
-                                        offset, val64);
-                if (status != VXGE_HW_OK)
-                        goto exit;
-                offset++;
-                val64++;
-        }
-exit:
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
-                                  struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
-{
-        u64 *val64;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        int i;
-        u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
-        val64 = (u64 *) vpath_rx_stats;
-
-        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
-                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
-                goto exit;
-        }
-        for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
-                status = __vxge_hw_vpath_stats_access(vpath,
-                                        VXGE_HW_STATS_OP_READ,
-                                        offset >> 3, val64);
-                if (status != VXGE_HW_OK)
-                        goto exit;
-
-                offset += 8;
-                val64++;
-        }
-exit:
-        return status;
-}
-
-/*
- * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
-                          struct vxge_hw_vpath_stats_hw_info *hw_stats)
-{
-        u64 val64;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
-
-        if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
-                status = VXGE_HW_ERR_VPATH_NOT_OPEN;
-                goto exit;
-        }
-        vp_reg = vpath->vp_reg;
-
-        val64 = readq(&vp_reg->vpath_debug_stats0);
-        hw_stats->ini_num_mwr_sent =
-                (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
-
-        val64 = readq(&vp_reg->vpath_debug_stats1);
-        hw_stats->ini_num_mrd_sent =
-                (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
-
-        val64 = readq(&vp_reg->vpath_debug_stats2);
-        hw_stats->ini_num_cpl_rcvd =
-                (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
-
-        val64 = readq(&vp_reg->vpath_debug_stats3);
-        hw_stats->ini_num_mwr_byte_sent =
-                VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
-
-        val64 = readq(&vp_reg->vpath_debug_stats4);
-        hw_stats->ini_num_cpl_byte_rcvd =
-                VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
-
-        val64 = readq(&vp_reg->vpath_debug_stats5);
-        hw_stats->wrcrdtarb_xoff =
-                (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
-
-        val64 = readq(&vp_reg->vpath_debug_stats6);
-        hw_stats->rdcrdtarb_xoff =
-                (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
-
-        val64 = readq(&vp_reg->vpath_genstats_count01);
-        hw_stats->vpath_genstats_count0 =
-        (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
-                val64);
-
-        val64 = readq(&vp_reg->vpath_genstats_count01);
-        hw_stats->vpath_genstats_count1 =
-        (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
-                val64);
-
-        val64 = readq(&vp_reg->vpath_genstats_count23);
-        hw_stats->vpath_genstats_count2 =
-        (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
-                val64);
-
-        val64 = readq(&vp_reg->vpath_genstats_count01);
-        hw_stats->vpath_genstats_count3 =
-        (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
-                val64);
-
-        val64 = readq(&vp_reg->vpath_genstats_count4);
-        hw_stats->vpath_genstats_count4 =
-        (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
-                val64);
-
-        val64 = readq(&vp_reg->vpath_genstats_count5);
-        hw_stats->vpath_genstats_count5 =
-        (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
-                val64);
-
-        status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
-        if (status != VXGE_HW_OK)
-                goto exit;
-
-        status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
-        if (status != VXGE_HW_OK)
-                goto exit;
-
-        VXGE_HW_VPATH_STATS_PIO_READ(
-                VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
-
-        hw_stats->prog_event_vnum0 =
-                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
-
-        hw_stats->prog_event_vnum1 =
-                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
-
-        VXGE_HW_VPATH_STATS_PIO_READ(
-                VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
-
-        hw_stats->prog_event_vnum2 =
-                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
-
-        hw_stats->prog_event_vnum3 =
-                        (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
-
-        val64 = readq(&vp_reg->rx_multi_cast_stats);
-        hw_stats->rx_multi_cast_frame_discard =
-                (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
-
-        val64 = readq(&vp_reg->rx_frm_transferred);
-        hw_stats->rx_frm_transferred =
-                (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
-
-        val64 = readq(&vp_reg->rxd_returned);
-        hw_stats->rxd_returned =
-                (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
-
-        val64 = readq(&vp_reg->dbg_stats_rx_mpa);
-        hw_stats->rx_mpa_len_fail_frms =
-                (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
-        hw_stats->rx_mpa_mrk_fail_frms =
-                (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
-        hw_stats->rx_mpa_crc_fail_frms =
-                (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
-
-        val64 = readq(&vp_reg->dbg_stats_rx_fau);
-        hw_stats->rx_permitted_frms =
-                (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
-        hw_stats->rx_vp_reset_discarded_frms =
-        (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
-        hw_stats->rx_wol_frms =
-                (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
-
-        val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
-        hw_stats->tx_vp_reset_discarded_frms =
-        (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
-                val64);
-exit:
-        return status;
-}
-
-
-static void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh,
-                                        unsigned long size)
-{
-        gfp_t flags;
-        void *vaddr;
-
-        if (in_interrupt())
-                flags = GFP_ATOMIC | GFP_DMA;
-        else
-                flags = GFP_KERNEL | GFP_DMA;
-
-        vaddr = kmalloc((size), flags);
-
-        vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
-}
-
-static void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr,
-                             struct pci_dev **p_dma_acch)
-{
-        unsigned long misaligned = *(unsigned long *)p_dma_acch;
-        u8 *tmp = (u8 *)vaddr;
-        tmp -= misaligned;
-        kfree((void *)tmp);
-}
-
-/*
- * __vxge_hw_blockpool_create - Create block pool
- */
-
-enum vxge_hw_status
-__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
-                           struct __vxge_hw_blockpool *blockpool,
-                           u32 pool_size,
-                           u32 pool_max)
-{
-        u32 i;
-        struct __vxge_hw_blockpool_entry *entry = NULL;
-        void *memblock;
-        dma_addr_t dma_addr;
-        struct pci_dev *dma_handle;
-        struct pci_dev *acc_handle;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        if (blockpool == NULL) {
-                status = VXGE_HW_FAIL;
-                goto blockpool_create_exit;
-        }
-
-        blockpool->hldev = hldev;
-        blockpool->block_size = VXGE_HW_BLOCK_SIZE;
-        blockpool->pool_size = 0;
-        blockpool->pool_max = pool_max;
-        blockpool->req_out = 0;
-
-        INIT_LIST_HEAD(&blockpool->free_block_list);
-        INIT_LIST_HEAD(&blockpool->free_entry_list);
-
-        for (i = 0; i < pool_size + pool_max; i++) {
-                entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
-                                GFP_KERNEL);
-                if (entry == NULL) {
-                        __vxge_hw_blockpool_destroy(blockpool);
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                        goto blockpool_create_exit;
-                }
-                list_add(&entry->item, &blockpool->free_entry_list);
-        }
-
-        for (i = 0; i < pool_size; i++) {
-
-                memblock = vxge_os_dma_malloc(
-                                hldev->pdev,
-                                VXGE_HW_BLOCK_SIZE,
-                                &dma_handle,
-                                &acc_handle);
-
-                if (memblock == NULL) {
-                        __vxge_hw_blockpool_destroy(blockpool);
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                        goto blockpool_create_exit;
-                }
-
-                dma_addr = pci_map_single(hldev->pdev, memblock,
-                                VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
-
-                if (unlikely(pci_dma_mapping_error(hldev->pdev,
-                                dma_addr))) {
-
-                        vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
-                        __vxge_hw_blockpool_destroy(blockpool);
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                        goto blockpool_create_exit;
-                }
-
-                if (!list_empty(&blockpool->free_entry_list))
-                        entry = (struct __vxge_hw_blockpool_entry *)
-                                list_first_entry(&blockpool->free_entry_list,
-                                        struct __vxge_hw_blockpool_entry,
-                                        item);
-
-                if (entry == NULL)
-                        entry =
-                            kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
-                                        GFP_KERNEL);
-                if (entry != NULL) {
-                        list_del(&entry->item);
-                        entry->length = VXGE_HW_BLOCK_SIZE;
-                        entry->memblock = memblock;
-                        entry->dma_addr = dma_addr;
-                        entry->acc_handle = acc_handle;
-                        entry->dma_handle = dma_handle;
-                        list_add(&entry->item,
-                                          &blockpool->free_block_list);
-                        blockpool->pool_size++;
-                } else {
-                        __vxge_hw_blockpool_destroy(blockpool);
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                        goto blockpool_create_exit;
-                }
-        }
-
-blockpool_create_exit:
-        return status;
-}
-
-/*
- * __vxge_hw_blockpool_destroy - Deallocates the block pool
- */
-
-void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
-{
-
-        struct __vxge_hw_device *hldev;
-        struct list_head *p, *n;
-        u16 ret;
-
-        if (blockpool == NULL) {
-                ret = 1;
-                goto exit;
-        }
-
-        hldev = blockpool->hldev;
-
-        list_for_each_safe(p, n, &blockpool->free_block_list) {
-
-                pci_unmap_single(hldev->pdev,
-                        ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
-                        ((struct __vxge_hw_blockpool_entry *)p)->length,
-                        PCI_DMA_BIDIRECTIONAL);
-
-                vxge_os_dma_free(hldev->pdev,
-                        ((struct __vxge_hw_blockpool_entry *)p)->memblock,
-                        &((struct __vxge_hw_blockpool_entry *) p)->acc_handle);
-
-                list_del(
-                        &((struct __vxge_hw_blockpool_entry *)p)->item);
-                kfree(p);
-                blockpool->pool_size--;
-        }
-
-        list_for_each_safe(p, n, &blockpool->free_entry_list) {
-                list_del(
-                        &((struct __vxge_hw_blockpool_entry *)p)->item);
-                kfree((void *)p);
-        }
-        ret = 0;
-exit:
-        return;
-}
-
-/*
- * __vxge_hw_blockpool_blocks_add - Request additional blocks
- */
-static
-void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
-{
-        u32 nreq = 0, i;
-
-        if ((blockpool->pool_size  +  blockpool->req_out) <
-                VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
-                nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
-                blockpool->req_out += nreq;
-        }
-
-        for (i = 0; i < nreq; i++)
-                vxge_os_dma_malloc_async(
-                        ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
-                        blockpool->hldev, VXGE_HW_BLOCK_SIZE);
-}
-
-/*
- * __vxge_hw_blockpool_blocks_remove - Free additional blocks
- */
-static
-void __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
-{
-        struct list_head *p, *n;
-
-        list_for_each_safe(p, n, &blockpool->free_block_list) {
-
-                if (blockpool->pool_size < blockpool->pool_max)
-                        break;
-
-                pci_unmap_single(
-                        ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
-                        ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
-                        ((struct __vxge_hw_blockpool_entry *)p)->length,
-                        PCI_DMA_BIDIRECTIONAL);
-
-                vxge_os_dma_free(
-                        ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
-                        ((struct __vxge_hw_blockpool_entry *)p)->memblock,
-                        &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
-
-                list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
-
-                list_add(p, &blockpool->free_entry_list);
-
-                blockpool->pool_size--;
-
-        }
-}
-
-/*
- * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
- * Adds a block to block pool
- */
-static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
-                                        void *block_addr,
-                                        u32 length,
-                                        struct pci_dev *dma_h,
-                                        struct pci_dev *acc_handle)
-{
-        struct __vxge_hw_blockpool  *blockpool;
-        struct __vxge_hw_blockpool_entry  *entry = NULL;
-        dma_addr_t dma_addr;
-        enum vxge_hw_status status = VXGE_HW_OK;
-        u32 req_out;
-
-        blockpool = &devh->block_pool;
-
-        if (block_addr == NULL) {
-                blockpool->req_out--;
-                status = VXGE_HW_FAIL;
-                goto exit;
-        }
-
-        dma_addr = pci_map_single(devh->pdev, block_addr, length,
-                                PCI_DMA_BIDIRECTIONAL);
-
-        if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
-
-                vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
-                blockpool->req_out--;
-                status = VXGE_HW_FAIL;
-                goto exit;
-        }
-
-
-        if (!list_empty(&blockpool->free_entry_list))
-                entry = (struct __vxge_hw_blockpool_entry *)
-                        list_first_entry(&blockpool->free_entry_list,
-                                struct __vxge_hw_blockpool_entry,
-                                item);
-
-        if (entry == NULL)
-                entry = (struct __vxge_hw_blockpool_entry *)
-                        vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
-        else
-                list_del(&entry->item);
-
-        if (entry != NULL) {
-                entry->length = length;
-                entry->memblock = block_addr;
-                entry->dma_addr = dma_addr;
-                entry->acc_handle = acc_handle;
-                entry->dma_handle = dma_h;
-                list_add(&entry->item, &blockpool->free_block_list);
-                blockpool->pool_size++;
-                status = VXGE_HW_OK;
-        } else
-                status = VXGE_HW_ERR_OUT_OF_MEMORY;
-
-        blockpool->req_out--;
-
-        req_out = blockpool->req_out;
-exit:
-        return;
-}
-
-/*
- * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
- * Allocates a block of memory of given size, either from block pool
- * or by calling vxge_os_dma_malloc()
- */
-void *
-__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
-                                struct vxge_hw_mempool_dma *dma_object)
-{
-        struct __vxge_hw_blockpool_entry *entry = NULL;
-        struct __vxge_hw_blockpool  *blockpool;
-        void *memblock = NULL;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        blockpool = &devh->block_pool;
-
-        if (size != blockpool->block_size) {
-
-                memblock = vxge_os_dma_malloc(devh->pdev, size,
-                                                &dma_object->handle,
-                                                &dma_object->acc_handle);
-
-                if (memblock == NULL) {
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                        goto exit;
-                }
-
-                dma_object->addr = pci_map_single(devh->pdev, memblock, size,
-                                        PCI_DMA_BIDIRECTIONAL);
-
-                if (unlikely(pci_dma_mapping_error(devh->pdev,
-                                dma_object->addr))) {
-                        vxge_os_dma_free(devh->pdev, memblock,
-                                &dma_object->acc_handle);
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-                        goto exit;
-                }
-
-        } else {
-
-                if (!list_empty(&blockpool->free_block_list))
-                        entry = (struct __vxge_hw_blockpool_entry *)
-                                list_first_entry(&blockpool->free_block_list,
-                                        struct __vxge_hw_blockpool_entry,
-                                        item);
-
-                if (entry != NULL) {
-                        list_del(&entry->item);
-                        dma_object->addr = entry->dma_addr;
-                        dma_object->handle = entry->dma_handle;
-                        dma_object->acc_handle = entry->acc_handle;
-                        memblock = entry->memblock;
-
-                        list_add(&entry->item,
-                                &blockpool->free_entry_list);
-                        blockpool->pool_size--;
-                }
-
-                if (memblock != NULL)
-                        __vxge_hw_blockpool_blocks_add(blockpool);
-        }
-exit:
-        return memblock;
-}
-
-/*
- * __vxge_hw_blockpool_free - Frees the memory allcoated with
-                                __vxge_hw_blockpool_malloc
- */
-void
-__vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
-                        void *memblock, u32 size,
-                        struct vxge_hw_mempool_dma *dma_object)
-{
-        struct __vxge_hw_blockpool_entry *entry = NULL;
-        struct __vxge_hw_blockpool  *blockpool;
-        enum vxge_hw_status status = VXGE_HW_OK;
-
-        blockpool = &devh->block_pool;
-
-        if (size != blockpool->block_size) {
-                pci_unmap_single(devh->pdev, dma_object->addr, size,
-                        PCI_DMA_BIDIRECTIONAL);
-                vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
-        } else {
-
-                if (!list_empty(&blockpool->free_entry_list))
-                        entry = (struct __vxge_hw_blockpool_entry *)
-                                list_first_entry(&blockpool->free_entry_list,
-                                        struct __vxge_hw_blockpool_entry,
-                                        item);
-
-                if (entry == NULL)
-                        entry = (struct __vxge_hw_blockpool_entry *)
-                                vmalloc(sizeof(
-                                        struct __vxge_hw_blockpool_entry));
-                else
-                        list_del(&entry->item);
-
-                if (entry != NULL) {
-                        entry->length = size;
-                        entry->memblock = memblock;
-                        entry->dma_addr = dma_object->addr;
-                        entry->acc_handle = dma_object->acc_handle;
-                        entry->dma_handle = dma_object->handle;
-                        list_add(&entry->item,
-                                        &blockpool->free_block_list);
-                        blockpool->pool_size++;
-                        status = VXGE_HW_OK;
-                } else
-                        status = VXGE_HW_ERR_OUT_OF_MEMORY;
-
-                if (status == VXGE_HW_OK)
-                        __vxge_hw_blockpool_blocks_remove(blockpool);
-        }
-}
-
-/*
- * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
- * This function allocates a block from block pool or from the system
- */
-struct __vxge_hw_blockpool_entry *
-__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
-{
-        struct __vxge_hw_blockpool_entry *entry = NULL;
-        struct __vxge_hw_blockpool  *blockpool;
-
-        blockpool = &devh->block_pool;
-
-        if (size == blockpool->block_size) {
-
-                if (!list_empty(&blockpool->free_block_list))
-                        entry = (struct __vxge_hw_blockpool_entry *)
-                                list_first_entry(&blockpool->free_block_list,
-                                        struct __vxge_hw_blockpool_entry,
-                                        item);
-
-                if (entry != NULL) {
-                        list_del(&entry->item);
-                        blockpool->pool_size--;
-                }
-        }
-
-        if (entry != NULL)
-                __vxge_hw_blockpool_blocks_add(blockpool);
-
-        return entry;
-}
-
-/*
- * __vxge_hw_blockpool_block_free - Frees a block from block pool
- * @devh: Hal device
- * @entry: Entry of block to be freed
- *
- * This function frees a block from block pool
- */
-void
-__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
-                        struct __vxge_hw_blockpool_entry *entry)
-{
-        struct __vxge_hw_blockpool  *blockpool;
-
-        blockpool = &devh->block_pool;
-
-        if (entry->length == blockpool->block_size) {
-                list_add(&entry->item, &blockpool->free_block_list);
-                blockpool->pool_size++;
-        }
-
-        __vxge_hw_blockpool_blocks_remove(blockpool);
-}
diff --git a/drivers/net/vxge/vxge-config.h b/drivers/net/vxge/vxge-config.h
index 5c00861b6c2c..e249e288d160 100644
--- a/drivers/net/vxge/vxge-config.h
+++ b/drivers/net/vxge/vxge-config.h
@@ -20,13 +20,6 @@
 #define VXGE_CACHE_LINE_SIZE 128
 #endif
 
-#define vxge_os_vaprintf(level, mask, fmt, ...) { \
-        char buff[255]; \
-                snprintf(buff, 255, fmt, __VA_ARGS__); \
-                printk(buff); \
-                printk("\n"); \
-}
-
 #ifndef VXGE_ALIGN
 #define VXGE_ALIGN(adrs, size) \
         (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1))
@@ -36,8 +29,16 @@
 #define VXGE_HW_MAX_MTU                         9600
 #define VXGE_HW_DEFAULT_MTU                     1500
 
-#ifdef VXGE_DEBUG_ASSERT
+#define VXGE_HW_MAX_ROM_IMAGES                  8
 
+struct eprom_image {
+        u8 is_valid:1;
+        u8 index;
+        u8 type;
+        u16 version;
+};
+
+#ifdef VXGE_DEBUG_ASSERT
 /**
  * vxge_assert
  * @test: C-condition to check
@@ -48,16 +49,13 @@
  * compilation
  * time.
  */
-#define vxge_assert(test) { \
-        if (!(test)) \
-                vxge_os_bug("bad cond: "#test" at %s:%d\n", \
-                                __FILE__, __LINE__); }
+#define vxge_assert(test) BUG_ON(!(test))
 #else
 #define vxge_assert(test)
 #endif /* end of VXGE_DEBUG_ASSERT */
 
 /**
- * enum enum vxge_debug_level
+ * enum vxge_debug_level
  * @VXGE_NONE: debug disabled
  * @VXGE_ERR: all errors going to be logged out
  * @VXGE_TRACE: all errors plus all kind of verbose tracing print outs
@@ -159,6 +157,47 @@ enum vxge_hw_device_link_state {
 };
 
 /**
+ * enum enum vxge_hw_fw_upgrade_code - FW upgrade return codes.
+ * @VXGE_HW_FW_UPGRADE_OK: All OK send next 16 bytes
+ * @VXGE_HW_FW_UPGRADE_DONE:  upload completed
+ * @VXGE_HW_FW_UPGRADE_ERR:  upload error
+ * @VXGE_FW_UPGRADE_BYTES2SKIP:  skip bytes in the stream
+ *
+ */
+enum vxge_hw_fw_upgrade_code {
+        VXGE_HW_FW_UPGRADE_OK           = 0,
+        VXGE_HW_FW_UPGRADE_DONE         = 1,
+        VXGE_HW_FW_UPGRADE_ERR          = 2,
+        VXGE_FW_UPGRADE_BYTES2SKIP      = 3
+};
+
+/**
+ * enum enum vxge_hw_fw_upgrade_err_code - FW upgrade error codes.
+ * @VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1: corrupt data
+ * @VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW: buffer overflow
+ * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3: invalid .ncf file
+ * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4: invalid .ncf file
+ * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5: invalid .ncf file
+ * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6: invalid .ncf file
+ * @VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7: corrupt data
+ * @VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8: invalid .ncf file
+ * @VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN: generic error unknown type
+ * @VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH: failed to flash image check failed
+ */
+enum vxge_hw_fw_upgrade_err_code {
+        VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1           = 1,
+        VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW          = 2,
+        VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3           = 3,
+        VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4           = 4,
+        VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5           = 5,
+        VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6           = 6,
+        VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7           = 7,
+        VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8           = 8,
+        VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN    = 9,
+        VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH          = 10
+};
+
+/**
  * struct vxge_hw_device_date - Date Format
  * @day: Day
  * @month: Month
@@ -275,9 +314,9 @@ struct vxge_hw_ring_config {
 #define VXGE_HW_RING_DEFAULT                                    1
 
         u32                             ring_blocks;
-#define VXGE_HW_MIN_RING_BLOCKS                         1
-#define VXGE_HW_MAX_RING_BLOCKS                         128
-#define VXGE_HW_DEF_RING_BLOCKS                         2
+#define VXGE_HW_MIN_RING_BLOCKS                                 1
+#define VXGE_HW_MAX_RING_BLOCKS                                 128
+#define VXGE_HW_DEF_RING_BLOCKS                                 2
 
         u32                             buffer_mode;
 #define VXGE_HW_RING_RXD_BUFFER_MODE_1                          1
@@ -465,7 +504,6 @@ struct vxge_hw_device_config {
  * See also: vxge_hw_driver_initialize().
  */
 struct vxge_hw_uld_cbs {
-
         void (*link_up)(struct __vxge_hw_device *devh);
         void (*link_down)(struct __vxge_hw_device *devh);
         void (*crit_err)(struct __vxge_hw_device *devh,
@@ -652,6 +690,7 @@ struct __vxge_hw_virtualpath {
         struct vxge_hw_vpath_stats_hw_info      *hw_stats;
         struct vxge_hw_vpath_stats_hw_info      *hw_stats_sav;
         struct vxge_hw_vpath_stats_sw_info      *sw_stats;
+        spinlock_t lock;
 };
 
 /*
@@ -661,7 +700,7 @@ struct __vxge_hw_virtualpath {
  *
  * This structure is used to store the callback information.
  */
-struct __vxge_hw_vpath_handle{
+struct __vxge_hw_vpath_handle {
         struct list_head        item;
         struct __vxge_hw_virtualpath    *vpath;
 };
@@ -674,9 +713,6 @@ struct __vxge_hw_vpath_handle{
 /**
  * struct __vxge_hw_device  - Hal device object
  * @magic: Magic Number
- * @device_id: PCI Device Id of the adapter
- * @major_revision: PCI Device major revision
- * @minor_revision: PCI Device minor revision
  * @bar0: BAR0 virtual address.
  * @pdev: Physical device handle
  * @config: Confguration passed by the LL driver at initialization
@@ -688,9 +724,6 @@ struct __vxge_hw_device {
         u32                             magic;
 #define VXGE_HW_DEVICE_MAGIC            0x12345678
 #define VXGE_HW_DEVICE_DEAD             0xDEADDEAD
-        u16                             device_id;
-        u8                              major_revision;
-        u8                              minor_revision;
         void __iomem                    *bar0;
         struct pci_dev                  *pdev;
         struct net_device               *ndev;
@@ -731,6 +764,7 @@ struct __vxge_hw_device {
         u32                             debug_level;
         u32                             level_err;
         u32                             level_trace;
+        u16 eprom_versions[VXGE_HW_MAX_ROM_IMAGES];
 };
 
 #define VXGE_HW_INFO_LEN        64
@@ -781,8 +815,8 @@ struct vxge_hw_device_hw_info {
         u8              serial_number[VXGE_HW_INFO_LEN];
         u8              part_number[VXGE_HW_INFO_LEN];
         u8              product_desc[VXGE_HW_INFO_LEN];
-        u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
-        u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
+        u8 mac_addrs[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
+        u8 mac_addr_masks[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN];
 };
 
 /**
@@ -829,20 +863,10 @@ struct vxge_hw_device_attr {
                                 loc, \
                                 offset, \
                                 &val64);                        \
-                                                                \
         if (status != VXGE_HW_OK)                               \
                 return status;                                          \
 }
 
-#define VXGE_HW_VPATH_STATS_PIO_READ(offset) {                          \
-        status = __vxge_hw_vpath_stats_access(vpath, \
-                        VXGE_HW_STATS_OP_READ, \
-                        offset, \
-                        &val64);                                        \
-        if (status != VXGE_HW_OK)                                       \
-                return status;                                          \
-}
-
 /*
  * struct __vxge_hw_ring - Ring channel.
  * @channel: Channel "base" of this ring, the common part of all HW
@@ -1114,7 +1138,7 @@ struct __vxge_hw_non_offload_db_wrapper {
  *             lookup to determine the transmit port.
  *             01: Send on physical Port1.
  *             10: Send on physical Port0.
-        *              11: Send on both ports.
+ *             11: Send on both ports.
  *             Bits 18 to 21 - Reserved
  *             Bits 22 to 23 - Gather_Code. This field is set by the host and
  *             is used to describe how individual buffers comprise a frame.
@@ -1413,12 +1437,12 @@ enum vxge_hw_rth_algoritms {
  * See also: vxge_hw_vpath_rts_rth_set(), vxge_hw_vpath_rts_rth_get().
  */
 struct vxge_hw_rth_hash_types {
-        u8 hash_type_tcpipv4_en;
-        u8 hash_type_ipv4_en;
-        u8 hash_type_tcpipv6_en;
-        u8 hash_type_ipv6_en;
-        u8 hash_type_tcpipv6ex_en;
-        u8 hash_type_ipv6ex_en;
+        u8 hash_type_tcpipv4_en:1,
+           hash_type_ipv4_en:1,
+           hash_type_tcpipv6_en:1,
+           hash_type_ipv6_en:1,
+           hash_type_tcpipv6ex_en:1,
+           hash_type_ipv6ex_en:1;
 };
 
 void vxge_hw_device_debug_set(
@@ -1893,6 +1917,15 @@ out:
         return vaddr;
 }
 
+static inline void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr,
+                        struct pci_dev **p_dma_acch)
+{
+        unsigned long misaligned = *(unsigned long *)p_dma_acch;
+        u8 *tmp = (u8 *)vaddr;
+        tmp -= misaligned;
+        kfree((void *)tmp);
+}
+
 /*
  * __vxge_hw_mempool_item_priv - will return pointer on per item private space
  */
@@ -1962,7 +1995,6 @@ enum vxge_hw_status vxge_hw_vpath_mtu_set(
 void
 vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp);
 
-
 #ifndef readq
 static inline u64 readq(void __iomem *addr)
 {
@@ -2000,7 +2032,7 @@ enum vxge_hw_status
 vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask);
 
 /**
- * vxge_debug
+ * vxge_debug_ll
  * @level: level of debug verbosity.
  * @mask: mask for the debug
  * @buf: Circular buffer for tracing
@@ -2012,26 +2044,13 @@ vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask);
  * may be compiled out if DEBUG macro was never defined.
  * See also: enum vxge_debug_level{}.
  */
-
-#define vxge_trace_aux(level, mask, fmt, ...) \
-{\
-                vxge_os_vaprintf(level, mask, fmt, __VA_ARGS__);\
-}
-
-#define vxge_debug(module, level, mask, fmt, ...) { \
-if ((level >= VXGE_TRACE && ((module & VXGE_DEBUG_TRACE_MASK) == module)) || \
-        (level >= VXGE_ERR && ((module & VXGE_DEBUG_ERR_MASK) == module))) {\
-        if ((mask & VXGE_DEBUG_MASK) == mask)\
-                vxge_trace_aux(level, mask, fmt, __VA_ARGS__); \
-} \
-}
-
 #if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK)
-#define vxge_debug_ll(level, mask, fmt, ...) \
-{\
-        vxge_debug(VXGE_COMPONENT_LL, level, mask, fmt, __VA_ARGS__);\
-}
-
+#define vxge_debug_ll(level, mask, fmt, ...) do {                              \
+        if ((level >= VXGE_ERR && VXGE_COMPONENT_LL & VXGE_DEBUG_ERR_MASK) ||  \
+            (level >= VXGE_TRACE && VXGE_COMPONENT_LL & VXGE_DEBUG_TRACE_MASK))\
+                if ((mask & VXGE_DEBUG_MASK) == mask)                          \
+                        printk(fmt "\n", __VA_ARGS__);                         \
+} while (0)
 #else
 #define vxge_debug_ll(level, mask, fmt, ...)
 #endif
@@ -2051,4 +2070,26 @@ enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
 
 enum vxge_hw_status
 __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id);
+
+#define VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT 5
+#define VXGE_HW_MAX_POLLING_COUNT 100
+
+void
+vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev);
+
+enum vxge_hw_status
+vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
+                             u32 *minor, u32 *build);
+
+enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev);
+
+enum vxge_hw_status
+vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *filebuf,
+                     int size);
+
+enum vxge_hw_status
+vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
+                                struct eprom_image *eprom_image_data);
+
+int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id);
 #endif
diff --git a/drivers/net/vxge/vxge-ethtool.c b/drivers/net/vxge/vxge-ethtool.c
index b67746eef923..1dd3a21b3a43 100644
--- a/drivers/net/vxge/vxge-ethtool.c
+++ b/drivers/net/vxge/vxge-ethtool.c
@@ -11,7 +11,7 @@
  *                 Virtualized Server Adapter.
  * Copyright(c) 2002-2010 Exar Corp.
  ******************************************************************************/
-#include<linux/ethtool.h>
+#include <linux/ethtool.h>
 #include <linux/slab.h>
 #include <linux/pci.h>
 #include <linux/etherdevice.h>
@@ -29,7 +29,6 @@
  * Return value:
  * 0 on success.
  */
-
 static int vxge_ethtool_sset(struct net_device *dev, struct ethtool_cmd *info)
 {
         /* We currently only support 10Gb/FULL */
@@ -79,10 +78,9 @@ static int vxge_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
  * Returns driver specefic information like name, version etc.. to ethtool.
  */
 static void vxge_ethtool_gdrvinfo(struct net_device *dev,
-                        struct ethtool_drvinfo *info)
+                                  struct ethtool_drvinfo *info)
 {
-        struct vxgedev *vdev;
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
         strlcpy(info->driver, VXGE_DRIVER_NAME, sizeof(VXGE_DRIVER_NAME));
         strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION));
         strlcpy(info->fw_version, vdev->fw_version, VXGE_HW_FW_STRLEN);
@@ -104,15 +102,14 @@ static void vxge_ethtool_gdrvinfo(struct net_device *dev,
  * buffer area.
  */
 static void vxge_ethtool_gregs(struct net_device *dev,
-                        struct ethtool_regs *regs, void *space)
+                               struct ethtool_regs *regs, void *space)
 {
         int index, offset;
         enum vxge_hw_status status;
         u64 reg;
-        u64 *reg_space = (u64 *) space;
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
-        struct __vxge_hw_device  *hldev = (struct __vxge_hw_device *)
-                                        pci_get_drvdata(vdev->pdev);
+        u64 *reg_space = (u64 *)space;
+        struct vxgedev *vdev = netdev_priv(dev);
+        struct __vxge_hw_device *hldev = vdev->devh;
 
         regs->len = sizeof(struct vxge_hw_vpath_reg) * vdev->no_of_vpath;
         regs->version = vdev->pdev->subsystem_device;
@@ -147,9 +144,8 @@ static void vxge_ethtool_gregs(struct net_device *dev,
  */
 static int vxge_ethtool_idnic(struct net_device *dev, u32 data)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
-        struct __vxge_hw_device  *hldev = (struct __vxge_hw_device  *)
-                        pci_get_drvdata(vdev->pdev);
+        struct vxgedev *vdev = netdev_priv(dev);
+        struct __vxge_hw_device *hldev = vdev->devh;
 
         vxge_hw_device_flick_link_led(hldev, VXGE_FLICKER_ON);
         msleep_interruptible(data ? (data * HZ) : VXGE_MAX_FLICKER_TIME);
@@ -168,11 +164,10 @@ static int vxge_ethtool_idnic(struct net_device *dev, u32 data)
  *  void
  */
 static void vxge_ethtool_getpause_data(struct net_device *dev,
-                                        struct ethtool_pauseparam *ep)
+                                       struct ethtool_pauseparam *ep)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
-        struct __vxge_hw_device  *hldev = (struct __vxge_hw_device  *)
-                        pci_get_drvdata(vdev->pdev);
+        struct vxgedev *vdev = netdev_priv(dev);
+        struct __vxge_hw_device *hldev = vdev->devh;
 
         vxge_hw_device_getpause_data(hldev, 0, &ep->tx_pause, &ep->rx_pause);
 }
@@ -188,11 +183,10 @@ static void vxge_ethtool_getpause_data(struct net_device *dev,
  * int, returns 0 on Success
  */
 static int vxge_ethtool_setpause_data(struct net_device *dev,
-                                        struct ethtool_pauseparam *ep)
+                                      struct ethtool_pauseparam *ep)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
-        struct __vxge_hw_device  *hldev = (struct __vxge_hw_device  *)
-                        pci_get_drvdata(vdev->pdev);
+        struct vxgedev *vdev = netdev_priv(dev);
+        struct __vxge_hw_device *hldev = vdev->devh;
 
         vxge_hw_device_setpause_data(hldev, 0, ep->tx_pause, ep->rx_pause);
 
@@ -209,9 +203,8 @@ static void vxge_get_ethtool_stats(struct net_device *dev,
         enum vxge_hw_status status;
         enum vxge_hw_status swstatus;
         struct vxge_vpath *vpath = NULL;
-
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
-        struct __vxge_hw_device  *hldev = vdev->devh;
+        struct vxgedev *vdev = netdev_priv(dev);
+        struct __vxge_hw_device *hldev = vdev->devh;
         struct vxge_hw_xmac_stats *xmac_stats;
         struct vxge_hw_device_stats_sw_info *sw_stats;
         struct vxge_hw_device_stats_hw_info *hw_stats;
@@ -574,12 +567,12 @@ static void vxge_get_ethtool_stats(struct net_device *dev,
         kfree(hw_stats);
 }
 
-static void vxge_ethtool_get_strings(struct net_device *dev,
-                              u32 stringset, u8 *data)
+static void vxge_ethtool_get_strings(struct net_device *dev, u32 stringset,
+                                     u8 *data)
 {
         int stat_size = 0;
         int i, j;
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
         switch (stringset) {
         case ETH_SS_STATS:
                 vxge_add_string("VPATH STATISTICS%s\t\t\t",
@@ -1066,21 +1059,21 @@ static void vxge_ethtool_get_strings(struct net_device *dev,
 
 static int vxge_ethtool_get_regs_len(struct net_device *dev)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
 
         return sizeof(struct vxge_hw_vpath_reg) * vdev->no_of_vpath;
 }
 
 static u32 vxge_get_rx_csum(struct net_device *dev)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
 
         return vdev->rx_csum;
 }
 
 static int vxge_set_rx_csum(struct net_device *dev, u32 data)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
 
         if (data)
                 vdev->rx_csum = 1;
@@ -1102,7 +1095,7 @@ static int vxge_ethtool_op_set_tso(struct net_device *dev, u32 data)
 
 static int vxge_ethtool_get_sset_count(struct net_device *dev, int sset)
 {
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
 
         switch (sset) {
         case ETH_SS_STATS:
@@ -1119,6 +1112,59 @@ static int vxge_ethtool_get_sset_count(struct net_device *dev, int sset)
         }
 }
 
+static int vxge_set_flags(struct net_device *dev, u32 data)
+{
+        struct vxgedev *vdev = netdev_priv(dev);
+        enum vxge_hw_status status;
+
+        if (data & ~ETH_FLAG_RXHASH)
+                return -EOPNOTSUPP;
+
+        if (!!(data & ETH_FLAG_RXHASH) == vdev->devh->config.rth_en)
+                return 0;
+
+        if (netif_running(dev) || (vdev->config.rth_steering == NO_STEERING))
+                return -EINVAL;
+
+        vdev->devh->config.rth_en = !!(data & ETH_FLAG_RXHASH);
+
+        /* Enabling RTH requires some of the logic in vxge_device_register and a
+         * vpath reset.  Due to these restrictions, only allow modification
+         * while the interface is down.
+         */
+        status = vxge_reset_all_vpaths(vdev);
+        if (status != VXGE_HW_OK) {
+                vdev->devh->config.rth_en = !vdev->devh->config.rth_en;
+                return -EFAULT;
+        }
+
+        if (vdev->devh->config.rth_en)
+                dev->features |= NETIF_F_RXHASH;
+        else
+                dev->features &= ~NETIF_F_RXHASH;
+
+        return 0;
+}
+
+static int vxge_fw_flash(struct net_device *dev, struct ethtool_flash *parms)
+{
+        struct vxgedev *vdev = netdev_priv(dev);
+
+        if (vdev->max_vpath_supported != VXGE_HW_MAX_VIRTUAL_PATHS) {
+                printk(KERN_INFO "Single Function Mode is required to flash the"
+                       " firmware\n");
+                return -EINVAL;
+        }
+
+        if (netif_running(dev)) {
+                printk(KERN_INFO "Interface %s must be down to flash the "
+                       "firmware\n", dev->name);
+                return -EBUSY;
+        }
+
+        return vxge_fw_upgrade(vdev, parms->data, 1);
+}
+
 static const struct ethtool_ops vxge_ethtool_ops = {
         .get_settings           = vxge_ethtool_gset,
         .set_settings           = vxge_ethtool_sset,
@@ -1131,7 +1177,7 @@ static const struct ethtool_ops vxge_ethtool_ops = {
         .get_rx_csum            = vxge_get_rx_csum,
         .set_rx_csum            = vxge_set_rx_csum,
         .get_tx_csum            = ethtool_op_get_tx_csum,
-        .set_tx_csum            = ethtool_op_set_tx_hw_csum,
+        .set_tx_csum            = ethtool_op_set_tx_ipv6_csum,
         .get_sg                 = ethtool_op_get_sg,
         .set_sg                 = ethtool_op_set_sg,
         .get_tso                = ethtool_op_get_tso,
@@ -1140,6 +1186,8 @@ static const struct ethtool_ops vxge_ethtool_ops = {
         .phys_id                = vxge_ethtool_idnic,
         .get_sset_count         = vxge_ethtool_get_sset_count,
         .get_ethtool_stats      = vxge_get_ethtool_stats,
+        .set_flags              = vxge_set_flags,
+        .flash_device           = vxge_fw_flash,
 };
 
 void vxge_initialize_ethtool_ops(struct net_device *ndev)
diff --git a/drivers/net/vxge/vxge-main.c b/drivers/net/vxge/vxge-main.c
index 813829f3d024..1ac9b568f1b0 100644
--- a/drivers/net/vxge/vxge-main.c
+++ b/drivers/net/vxge/vxge-main.c
@@ -50,6 +50,8 @@
 #include <net/ip.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
+#include <linux/firmware.h>
+#include <linux/net_tstamp.h>
 #include "vxge-main.h"
 #include "vxge-reg.h"
 
@@ -82,16 +84,6 @@ module_param_array(bw_percentage, uint, NULL, 0);
 
 static struct vxge_drv_config *driver_config;
 
-static enum vxge_hw_status vxge_add_mac_addr(struct vxgedev *vdev,
-                                             struct macInfo *mac);
-static enum vxge_hw_status vxge_del_mac_addr(struct vxgedev *vdev,
-                                             struct macInfo *mac);
-static int vxge_mac_list_add(struct vxge_vpath *vpath, struct macInfo *mac);
-static int vxge_mac_list_del(struct vxge_vpath *vpath, struct macInfo *mac);
-static enum vxge_hw_status vxge_restore_vpath_vid_table(struct vxge_vpath *vpath);
-static enum vxge_hw_status vxge_restore_vpath_mac_addr(struct vxge_vpath *vpath);
-static enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev);
-
 static inline int is_vxge_card_up(struct vxgedev *vdev)
 {
         return test_bit(__VXGE_STATE_CARD_UP, &vdev->state);
@@ -148,11 +140,10 @@ static inline void VXGE_COMPLETE_ALL_RX(struct vxgedev *vdev)
  * This function is called during interrupt context to notify link up state
  * change.
  */
-static void
-vxge_callback_link_up(struct __vxge_hw_device *hldev)
+static void vxge_callback_link_up(struct __vxge_hw_device *hldev)
 {
         struct net_device *dev = hldev->ndev;
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
 
         vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d",
                 vdev->ndev->name, __func__, __LINE__);
@@ -172,11 +163,10 @@ vxge_callback_link_up(struct __vxge_hw_device *hldev)
  * This function is called during interrupt context to notify link down state
  * change.
  */
-static void
-vxge_callback_link_down(struct __vxge_hw_device *hldev)
+static void vxge_callback_link_down(struct __vxge_hw_device *hldev)
 {
         struct net_device *dev = hldev->ndev;
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
 
         vxge_debug_entryexit(VXGE_TRACE,
                 "%s: %s:%d", vdev->ndev->name, __func__, __LINE__);
@@ -195,7 +185,7 @@ vxge_callback_link_down(struct __vxge_hw_device *hldev)
  *
  * Allocate SKB.
  */
-static struct sk_buff*
+static struct sk_buff *
 vxge_rx_alloc(void *dtrh, struct vxge_ring *ring, const int skb_size)
 {
         struct net_device    *dev;
@@ -369,7 +359,7 @@ vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
                  u8 t_code, void *userdata)
 {
         struct vxge_ring *ring = (struct vxge_ring *)userdata;
-        struct  net_device *dev = ring->ndev;
+        struct net_device *dev = ring->ndev;
         unsigned int dma_sizes;
         void *first_dtr = NULL;
         int dtr_cnt = 0;
@@ -413,7 +403,6 @@ vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
 
                 prefetch((char *)skb + L1_CACHE_BYTES);
                 if (unlikely(t_code)) {
-
                         if (vxge_hw_ring_handle_tcode(ringh, dtr, t_code) !=
                                 VXGE_HW_OK) {
 
@@ -436,9 +425,7 @@ vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
                 }
 
                 if (pkt_length > VXGE_LL_RX_COPY_THRESHOLD) {
-
                         if (vxge_rx_alloc(dtr, ring, data_size) != NULL) {
-
                                 if (!vxge_rx_map(dtr, ring)) {
                                         skb_put(skb, pkt_length);
 
@@ -513,6 +500,23 @@ vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
                 else
                         skb_checksum_none_assert(skb);
 
+
+                if (ring->rx_hwts) {
+                        struct skb_shared_hwtstamps *skb_hwts;
+                        u32 ns = *(u32 *)(skb->head + pkt_length);
+
+                        skb_hwts = skb_hwtstamps(skb);
+                        skb_hwts->hwtstamp = ns_to_ktime(ns);
+                        skb_hwts->syststamp.tv64 = 0;
+                }
+
+                /* rth_hash_type and rth_it_hit are non-zero regardless of
+                 * whether rss is enabled.  Only the rth_value is zero/non-zero
+                 * if rss is disabled/enabled, so key off of that.
+                 */
+                if (ext_info.rth_value)
+                        skb->rxhash = ext_info.rth_value;
+
                 vxge_rx_complete(ring, skb, ext_info.vlan,
                         pkt_length, &ext_info);
 
@@ -660,6 +664,65 @@ static enum vxge_hw_status vxge_search_mac_addr_in_list(
         return FALSE;
 }
 
+static int vxge_mac_list_add(struct vxge_vpath *vpath, struct macInfo *mac)
+{
+        struct vxge_mac_addrs *new_mac_entry;
+        u8 *mac_address = NULL;
+
+        if (vpath->mac_addr_cnt >= VXGE_MAX_LEARN_MAC_ADDR_CNT)
+                return TRUE;
+
+        new_mac_entry = kzalloc(sizeof(struct vxge_mac_addrs), GFP_ATOMIC);
+        if (!new_mac_entry) {
+                vxge_debug_mem(VXGE_ERR,
+                        "%s: memory allocation failed",
+                        VXGE_DRIVER_NAME);
+                return FALSE;
+        }
+
+        list_add(&new_mac_entry->item, &vpath->mac_addr_list);
+
+        /* Copy the new mac address to the list */
+        mac_address = (u8 *)&new_mac_entry->macaddr;
+        memcpy(mac_address, mac->macaddr, ETH_ALEN);
+
+        new_mac_entry->state = mac->state;
+        vpath->mac_addr_cnt++;
+
+        /* Is this a multicast address */
+        if (0x01 & mac->macaddr[0])
+                vpath->mcast_addr_cnt++;
+
+        return TRUE;
+}
+
+/* Add a mac address to DA table */
+static enum vxge_hw_status
+vxge_add_mac_addr(struct vxgedev *vdev, struct macInfo *mac)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct vxge_vpath *vpath;
+        enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode;
+
+        if (0x01 & mac->macaddr[0]) /* multicast address */
+                duplicate_mode = VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE;
+        else
+                duplicate_mode = VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE;
+
+        vpath = &vdev->vpaths[mac->vpath_no];
+        status = vxge_hw_vpath_mac_addr_add(vpath->handle, mac->macaddr,
+                                                mac->macmask, duplicate_mode);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR,
+                        "DA config add entry failed for vpath:%d",
+                        vpath->device_id);
+        } else
+                if (FALSE == vxge_mac_list_add(vpath, mac))
+                        status = -EPERM;
+
+        return status;
+}
+
 static int vxge_learn_mac(struct vxgedev *vdev, u8 *mac_header)
 {
         struct macInfo mac_info;
@@ -670,7 +733,7 @@ static int vxge_learn_mac(struct vxgedev *vdev, u8 *mac_header)
         struct vxge_vpath *vpath = NULL;
         struct __vxge_hw_device *hldev;
 
-        hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev);
+        hldev = pci_get_drvdata(vdev->pdev);
 
         mac_address = (u8 *)&mac_addr;
         memcpy(mac_address, mac_header, ETH_ALEN);
@@ -769,7 +832,7 @@ vxge_xmit(struct sk_buff *skb, struct net_device *dev)
                 return NETDEV_TX_OK;
         }
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
 
         if (unlikely(!is_vxge_card_up(vdev))) {
                 vxge_debug_tx(VXGE_ERR,
@@ -1005,6 +1068,50 @@ vxge_tx_term(void *dtrh, enum vxge_hw_txdl_state state, void *userdata)
                 "%s:%d  Exiting...", __func__, __LINE__);
 }
 
+static int vxge_mac_list_del(struct vxge_vpath *vpath, struct macInfo *mac)
+{
+        struct list_head *entry, *next;
+        u64 del_mac = 0;
+        u8 *mac_address = (u8 *) (&del_mac);
+
+        /* Copy the mac address to delete from the list */
+        memcpy(mac_address, mac->macaddr, ETH_ALEN);
+
+        list_for_each_safe(entry, next, &vpath->mac_addr_list) {
+                if (((struct vxge_mac_addrs *)entry)->macaddr == del_mac) {
+                        list_del(entry);
+                        kfree((struct vxge_mac_addrs *)entry);
+                        vpath->mac_addr_cnt--;
+
+                        /* Is this a multicast address */
+                        if (0x01 & mac->macaddr[0])
+                                vpath->mcast_addr_cnt--;
+                        return TRUE;
+                }
+        }
+
+        return FALSE;
+}
+
+/* delete a mac address from DA table */
+static enum vxge_hw_status
+vxge_del_mac_addr(struct vxgedev *vdev, struct macInfo *mac)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct vxge_vpath *vpath;
+
+        vpath = &vdev->vpaths[mac->vpath_no];
+        status = vxge_hw_vpath_mac_addr_delete(vpath->handle, mac->macaddr,
+                                                mac->macmask);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR,
+                        "DA config delete entry failed for vpath:%d",
+                        vpath->device_id);
+        } else
+                vxge_mac_list_del(vpath, mac);
+        return status;
+}
+
 /**
  * vxge_set_multicast
  * @dev: pointer to the device structure
@@ -1034,7 +1141,7 @@ static void vxge_set_multicast(struct net_device *dev)
         vxge_debug_entryexit(VXGE_TRACE,
                 "%s:%d", __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
         hldev = (struct __vxge_hw_device  *)vdev->devh;
 
         if (unlikely(!is_vxge_card_up(vdev)))
@@ -1094,7 +1201,7 @@ static void vxge_set_multicast(struct net_device *dev)
                 /* Delete previous MC's */
                 for (i = 0; i < mcast_cnt; i++) {
                         list_for_each_safe(entry, next, list_head) {
-                                mac_entry = (struct vxge_mac_addrs *) entry;
+                                mac_entry = (struct vxge_mac_addrs *)entry;
                                 /* Copy the mac address to delete */
                                 mac_address = (u8 *)&mac_entry->macaddr;
                                 memcpy(mac_info.macaddr, mac_address, ETH_ALEN);
@@ -1137,7 +1244,7 @@ _set_all_mcast:
                 /* Delete previous MC's */
                 for (i = 0; i < mcast_cnt; i++) {
                         list_for_each_safe(entry, next, list_head) {
-                                mac_entry = (struct vxge_mac_addrs *) entry;
+                                mac_entry = (struct vxge_mac_addrs *)entry;
                                 /* Copy the mac address to delete */
                                 mac_address = (u8 *)&mac_entry->macaddr;
                                 memcpy(mac_info.macaddr, mac_address, ETH_ALEN);
@@ -1184,14 +1291,14 @@ static int vxge_set_mac_addr(struct net_device *dev, void *p)
 {
         struct sockaddr *addr = p;
         struct vxgedev *vdev;
-        struct __vxge_hw_device  *hldev;
+        struct __vxge_hw_device *hldev;
         enum vxge_hw_status status = VXGE_HW_OK;
         struct macInfo mac_info_new, mac_info_old;
         int vpath_idx = 0;
 
         vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
         hldev = vdev->devh;
 
         if (!is_valid_ether_addr(addr->sa_data))
@@ -1292,8 +1399,13 @@ static void vxge_vpath_intr_enable(struct vxgedev *vdev, int vp_id)
 static void vxge_vpath_intr_disable(struct vxgedev *vdev, int vp_id)
 {
         struct vxge_vpath *vpath = &vdev->vpaths[vp_id];
+        struct __vxge_hw_device *hldev;
         int msix_id;
 
+        hldev = pci_get_drvdata(vdev->pdev);
+
+        vxge_hw_vpath_wait_receive_idle(hldev, vpath->device_id);
+
         vxge_hw_vpath_intr_disable(vpath->handle);
 
         if (vdev->config.intr_type == INTA)
@@ -1310,6 +1422,95 @@ static void vxge_vpath_intr_disable(struct vxgedev *vdev, int vp_id)
         }
 }
 
+/* list all mac addresses from DA table */
+static enum vxge_hw_status
+vxge_search_mac_addr_in_da_table(struct vxge_vpath *vpath, struct macInfo *mac)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        unsigned char macmask[ETH_ALEN];
+        unsigned char macaddr[ETH_ALEN];
+
+        status = vxge_hw_vpath_mac_addr_get(vpath->handle,
+                                macaddr, macmask);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR,
+                        "DA config list entry failed for vpath:%d",
+                        vpath->device_id);
+                return status;
+        }
+
+        while (memcmp(mac->macaddr, macaddr, ETH_ALEN)) {
+                status = vxge_hw_vpath_mac_addr_get_next(vpath->handle,
+                                macaddr, macmask);
+                if (status != VXGE_HW_OK)
+                        break;
+        }
+
+        return status;
+}
+
+/* Store all mac addresses from the list to the DA table */
+static enum vxge_hw_status vxge_restore_vpath_mac_addr(struct vxge_vpath *vpath)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct macInfo mac_info;
+        u8 *mac_address = NULL;
+        struct list_head *entry, *next;
+
+        memset(&mac_info, 0, sizeof(struct macInfo));
+
+        if (vpath->is_open) {
+                list_for_each_safe(entry, next, &vpath->mac_addr_list) {
+                        mac_address =
+                                (u8 *)&
+                                ((struct vxge_mac_addrs *)entry)->macaddr;
+                        memcpy(mac_info.macaddr, mac_address, ETH_ALEN);
+                        ((struct vxge_mac_addrs *)entry)->state =
+                                VXGE_LL_MAC_ADDR_IN_DA_TABLE;
+                        /* does this mac address already exist in da table? */
+                        status = vxge_search_mac_addr_in_da_table(vpath,
+                                &mac_info);
+                        if (status != VXGE_HW_OK) {
+                                /* Add this mac address to the DA table */
+                                status = vxge_hw_vpath_mac_addr_add(
+                                        vpath->handle, mac_info.macaddr,
+                                        mac_info.macmask,
+                                    VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE);
+                                if (status != VXGE_HW_OK) {
+                                        vxge_debug_init(VXGE_ERR,
+                                            "DA add entry failed for vpath:%d",
+                                            vpath->device_id);
+                                        ((struct vxge_mac_addrs *)entry)->state
+                                                = VXGE_LL_MAC_ADDR_IN_LIST;
+                                }
+                        }
+                }
+        }
+
+        return status;
+}
+
+/* Store all vlan ids from the list to the vid table */
+static enum vxge_hw_status
+vxge_restore_vpath_vid_table(struct vxge_vpath *vpath)
+{
+        enum vxge_hw_status status = VXGE_HW_OK;
+        struct vxgedev *vdev = vpath->vdev;
+        u16 vid;
+
+        if (vdev->vlgrp && vpath->is_open) {
+
+                for (vid = 0; vid < VLAN_N_VID; vid++) {
+                        if (!vlan_group_get_device(vdev->vlgrp, vid))
+                                continue;
+                        /* Add these vlan to the vid table */
+                        status = vxge_hw_vpath_vid_add(vpath->handle, vid);
+                }
+        }
+
+        return status;
+}
+
 /*
  * vxge_reset_vpath
  * @vdev: pointer to vdev
@@ -1405,12 +1606,16 @@ static int do_vxge_reset(struct vxgedev *vdev, int event)
         }
 
         if (event == VXGE_LL_FULL_RESET) {
+                netif_carrier_off(vdev->ndev);
+
                 /* wait for all the vpath reset to complete */
                 for (vp_id = 0; vp_id < vdev->no_of_vpath; vp_id++) {
                         while (test_bit(vp_id, &vdev->vp_reset))
                                 msleep(50);
                 }
 
+                netif_carrier_on(vdev->ndev);
+
                 /* if execution mode is set to debug, don't reset the adapter */
                 if (unlikely(vdev->exec_mode)) {
                         vxge_debug_init(VXGE_ERR,
@@ -1423,6 +1628,7 @@ static int do_vxge_reset(struct vxgedev *vdev, int event)
         }
 
         if (event == VXGE_LL_FULL_RESET) {
+                vxge_hw_device_wait_receive_idle(vdev->devh);
                 vxge_hw_device_intr_disable(vdev->devh);
 
                 switch (vdev->cric_err_event) {
@@ -1563,9 +1769,14 @@ out:
  *
  * driver may reset the chip on events of serr, eccerr, etc
  */
-static int vxge_reset(struct vxgedev *vdev)
+static void vxge_reset(struct work_struct *work)
 {
-        return do_vxge_reset(vdev, VXGE_LL_FULL_RESET);
+        struct vxgedev *vdev = container_of(work, struct vxgedev, reset_task);
+
+        if (!netif_running(vdev->ndev))
+                return;
+
+        do_vxge_reset(vdev, VXGE_LL_FULL_RESET);
 }
 
 /**
@@ -1608,8 +1819,7 @@ static int vxge_poll_inta(struct napi_struct *napi, int budget)
         int budget_org = budget;
         struct vxge_ring *ring;
 
-        struct __vxge_hw_device  *hldev = (struct __vxge_hw_device *)
-                pci_get_drvdata(vdev->pdev);
+        struct __vxge_hw_device *hldev = pci_get_drvdata(vdev->pdev);
 
         for (i = 0; i < vdev->no_of_vpath; i++) {
                 ring = &vdev->vpaths[i].ring;
@@ -1645,11 +1855,11 @@ static int vxge_poll_inta(struct napi_struct *napi, int budget)
  */
 static void vxge_netpoll(struct net_device *dev)
 {
-        struct __vxge_hw_device  *hldev;
+        struct __vxge_hw_device *hldev;
         struct vxgedev *vdev;
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
-        hldev = (struct __vxge_hw_device  *)pci_get_drvdata(vdev->pdev);
+        vdev = netdev_priv(dev);
+        hldev = pci_get_drvdata(vdev->pdev);
 
         vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__);
 
@@ -1689,15 +1899,6 @@ static enum vxge_hw_status vxge_rth_configure(struct vxgedev *vdev)
                 mtable[index] = index % vdev->no_of_vpath;
         }
 
-        /* Fill RTH hash types */
-        hash_types.hash_type_tcpipv4_en   = vdev->config.rth_hash_type_tcpipv4;
-        hash_types.hash_type_ipv4_en      = vdev->config.rth_hash_type_ipv4;
-        hash_types.hash_type_tcpipv6_en   = vdev->config.rth_hash_type_tcpipv6;
-        hash_types.hash_type_ipv6_en      = vdev->config.rth_hash_type_ipv6;
-        hash_types.hash_type_tcpipv6ex_en =
-                                        vdev->config.rth_hash_type_tcpipv6ex;
-        hash_types.hash_type_ipv6ex_en    = vdev->config.rth_hash_type_ipv6ex;
-
         /* set indirection table, bucket-to-vpath mapping */
         status = vxge_hw_vpath_rts_rth_itable_set(vdev->vp_handles,
                                                 vdev->no_of_vpath,
@@ -1710,19 +1911,27 @@ static enum vxge_hw_status vxge_rth_configure(struct vxgedev *vdev)
                 return status;
         }
 
+        /* Fill RTH hash types */
+        hash_types.hash_type_tcpipv4_en   = vdev->config.rth_hash_type_tcpipv4;
+        hash_types.hash_type_ipv4_en      = vdev->config.rth_hash_type_ipv4;
+        hash_types.hash_type_tcpipv6_en   = vdev->config.rth_hash_type_tcpipv6;
+        hash_types.hash_type_ipv6_en      = vdev->config.rth_hash_type_ipv6;
+        hash_types.hash_type_tcpipv6ex_en =
+                                        vdev->config.rth_hash_type_tcpipv6ex;
+        hash_types.hash_type_ipv6ex_en    = vdev->config.rth_hash_type_ipv6ex;
+
         /*
-        * Because the itable_set() method uses the active_table field
-        * for the target virtual path the RTH config should be updated
-        * for all VPATHs. The h/w only uses the lowest numbered VPATH
-        * when steering frames.
-        */
+         * Because the itable_set() method uses the active_table field
+         * for the target virtual path the RTH config should be updated
+         * for all VPATHs. The h/w only uses the lowest numbered VPATH
+         * when steering frames.
+         */
          for (index = 0; index < vdev->no_of_vpath; index++) {
                 status = vxge_hw_vpath_rts_rth_set(
                                 vdev->vpaths[index].handle,
                                 vdev->config.rth_algorithm,
                                 &hash_types,
                                 vdev->config.rth_bkt_sz);
-
                  if (status != VXGE_HW_OK) {
                         vxge_debug_init(VXGE_ERR,
                                 "RTH configuration failed for vpath:%d",
@@ -1734,201 +1943,8 @@ static enum vxge_hw_status vxge_rth_configure(struct vxgedev *vdev)
         return status;
 }
 
-static int vxge_mac_list_add(struct vxge_vpath *vpath, struct macInfo *mac)
-{
-        struct vxge_mac_addrs *new_mac_entry;
-        u8 *mac_address = NULL;
-
-        if (vpath->mac_addr_cnt >= VXGE_MAX_LEARN_MAC_ADDR_CNT)
-                return TRUE;
-
-        new_mac_entry = kzalloc(sizeof(struct vxge_mac_addrs), GFP_ATOMIC);
-        if (!new_mac_entry) {
-                vxge_debug_mem(VXGE_ERR,
-                        "%s: memory allocation failed",
-                        VXGE_DRIVER_NAME);
-                return FALSE;
-        }
-
-        list_add(&new_mac_entry->item, &vpath->mac_addr_list);
-
-        /* Copy the new mac address to the list */
-        mac_address = (u8 *)&new_mac_entry->macaddr;
-        memcpy(mac_address, mac->macaddr, ETH_ALEN);
-
-        new_mac_entry->state = mac->state;
-        vpath->mac_addr_cnt++;
-
-        /* Is this a multicast address */
-        if (0x01 & mac->macaddr[0])
-                vpath->mcast_addr_cnt++;
-
-        return TRUE;
-}
-
-/* Add a mac address to DA table */
-static enum vxge_hw_status vxge_add_mac_addr(struct vxgedev *vdev,
-                                             struct macInfo *mac)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxge_vpath *vpath;
-        enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode;
-
-        if (0x01 & mac->macaddr[0]) /* multicast address */
-                duplicate_mode = VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE;
-        else
-                duplicate_mode = VXGE_HW_VPATH_MAC_ADDR_REPLACE_DUPLICATE;
-
-        vpath = &vdev->vpaths[mac->vpath_no];
-        status = vxge_hw_vpath_mac_addr_add(vpath->handle, mac->macaddr,
-                                                mac->macmask, duplicate_mode);
-        if (status != VXGE_HW_OK) {
-                vxge_debug_init(VXGE_ERR,
-                        "DA config add entry failed for vpath:%d",
-                        vpath->device_id);
-        } else
-                if (FALSE == vxge_mac_list_add(vpath, mac))
-                        status = -EPERM;
-
-        return status;
-}
-
-static int vxge_mac_list_del(struct vxge_vpath *vpath, struct macInfo *mac)
-{
-        struct list_head *entry, *next;
-        u64 del_mac = 0;
-        u8 *mac_address = (u8 *) (&del_mac);
-
-        /* Copy the mac address to delete from the list */
-        memcpy(mac_address, mac->macaddr, ETH_ALEN);
-
-        list_for_each_safe(entry, next, &vpath->mac_addr_list) {
-                if (((struct vxge_mac_addrs *)entry)->macaddr == del_mac) {
-                        list_del(entry);
-                        kfree((struct vxge_mac_addrs *)entry);
-                        vpath->mac_addr_cnt--;
-
-                        /* Is this a multicast address */
-                        if (0x01 & mac->macaddr[0])
-                                vpath->mcast_addr_cnt--;
-                        return TRUE;
-                }
-        }
-
-        return FALSE;
-}
-/* delete a mac address from DA table */
-static enum vxge_hw_status vxge_del_mac_addr(struct vxgedev *vdev,
-                                             struct macInfo *mac)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxge_vpath *vpath;
-
-        vpath = &vdev->vpaths[mac->vpath_no];
-        status = vxge_hw_vpath_mac_addr_delete(vpath->handle, mac->macaddr,
-                                                mac->macmask);
-        if (status != VXGE_HW_OK) {
-                vxge_debug_init(VXGE_ERR,
-                        "DA config delete entry failed for vpath:%d",
-                        vpath->device_id);
-        } else
-                vxge_mac_list_del(vpath, mac);
-        return status;
-}
-
-/* list all mac addresses from DA table */
-enum vxge_hw_status
-static vxge_search_mac_addr_in_da_table(struct vxge_vpath *vpath,
-                                        struct macInfo *mac)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-        unsigned char macmask[ETH_ALEN];
-        unsigned char macaddr[ETH_ALEN];
-
-        status = vxge_hw_vpath_mac_addr_get(vpath->handle,
-                                macaddr, macmask);
-        if (status != VXGE_HW_OK) {
-                vxge_debug_init(VXGE_ERR,
-                        "DA config list entry failed for vpath:%d",
-                        vpath->device_id);
-                return status;
-        }
-
-        while (memcmp(mac->macaddr, macaddr, ETH_ALEN)) {
-
-                status = vxge_hw_vpath_mac_addr_get_next(vpath->handle,
-                                macaddr, macmask);
-                if (status != VXGE_HW_OK)
-                        break;
-        }
-
-        return status;
-}
-
-/* Store all vlan ids from the list to the vid table */
-static enum vxge_hw_status vxge_restore_vpath_vid_table(struct vxge_vpath *vpath)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct vxgedev *vdev = vpath->vdev;
-        u16 vid;
-
-        if (vdev->vlgrp && vpath->is_open) {
-
-                for (vid = 0; vid < VLAN_N_VID; vid++) {
-                        if (!vlan_group_get_device(vdev->vlgrp, vid))
-                                continue;
-                        /* Add these vlan to the vid table */
-                        status = vxge_hw_vpath_vid_add(vpath->handle, vid);
-                }
-        }
-
-        return status;
-}
-
-/* Store all mac addresses from the list to the DA table */
-static enum vxge_hw_status vxge_restore_vpath_mac_addr(struct vxge_vpath *vpath)
-{
-        enum vxge_hw_status status = VXGE_HW_OK;
-        struct macInfo mac_info;
-        u8 *mac_address = NULL;
-        struct list_head *entry, *next;
-
-        memset(&mac_info, 0, sizeof(struct macInfo));
-
-        if (vpath->is_open) {
-
-                list_for_each_safe(entry, next, &vpath->mac_addr_list) {
-                        mac_address =
-                                (u8 *)&
-                                ((struct vxge_mac_addrs *)entry)->macaddr;
-                        memcpy(mac_info.macaddr, mac_address, ETH_ALEN);
-                        ((struct vxge_mac_addrs *)entry)->state =
-                                VXGE_LL_MAC_ADDR_IN_DA_TABLE;
-                        /* does this mac address already exist in da table? */
-                        status = vxge_search_mac_addr_in_da_table(vpath,
-                                &mac_info);
-                        if (status != VXGE_HW_OK) {
-                                /* Add this mac address to the DA table */
-                                status = vxge_hw_vpath_mac_addr_add(
-                                        vpath->handle, mac_info.macaddr,
-                                        mac_info.macmask,
-                                    VXGE_HW_VPATH_MAC_ADDR_ADD_DUPLICATE);
-                                if (status != VXGE_HW_OK) {
-                                        vxge_debug_init(VXGE_ERR,
-                                            "DA add entry failed for vpath:%d",
-                                            vpath->device_id);
-                                        ((struct vxge_mac_addrs *)entry)->state
-                                                = VXGE_LL_MAC_ADDR_IN_LIST;
-                                }
-                        }
-                }
-        }
-
-        return status;
-}
-
 /* reset vpaths */
-static enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev)
+enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev)
 {
         enum vxge_hw_status status = VXGE_HW_OK;
         struct vxge_vpath *vpath;
@@ -1988,8 +2004,23 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
 
         for (i = 0; i < vdev->no_of_vpath; i++) {
                 vpath = &vdev->vpaths[i];
-
                 vxge_assert(vpath->is_configured);
+
+                if (!vdev->titan1) {
+                        struct vxge_hw_vp_config *vcfg;
+                        vcfg = &vdev->devh->config.vp_config[vpath->device_id];
+
+                        vcfg->rti.urange_a = RTI_T1A_RX_URANGE_A;
+                        vcfg->rti.urange_b = RTI_T1A_RX_URANGE_B;
+                        vcfg->rti.urange_c = RTI_T1A_RX_URANGE_C;
+                        vcfg->tti.uec_a = TTI_T1A_TX_UFC_A;
+                        vcfg->tti.uec_b = TTI_T1A_TX_UFC_B;
+                        vcfg->tti.uec_c = TTI_T1A_TX_UFC_C(vdev->mtu);
+                        vcfg->tti.uec_d = TTI_T1A_TX_UFC_D(vdev->mtu);
+                        vcfg->tti.ltimer_val = VXGE_T1A_TTI_LTIMER_VAL;
+                        vcfg->tti.rtimer_val = VXGE_T1A_TTI_RTIMER_VAL;
+                }
+
                 attr.vp_id = vpath->device_id;
                 attr.fifo_attr.callback = vxge_xmit_compl;
                 attr.fifo_attr.txdl_term = vxge_tx_term;
@@ -2004,6 +2035,7 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
 
                 vpath->ring.ndev = vdev->ndev;
                 vpath->ring.pdev = vdev->pdev;
+
                 status = vxge_hw_vpath_open(vdev->devh, &attr, &vpath->handle);
                 if (status == VXGE_HW_OK) {
                         vpath->fifo.handle =
@@ -2024,6 +2056,7 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
                                 vdev->config.fifo_indicate_max_pkts;
                         vpath->ring.rx_vector_no = 0;
                         vpath->ring.rx_csum = vdev->rx_csum;
+                        vpath->ring.rx_hwts = vdev->rx_hwts;
                         vpath->is_open = 1;
                         vdev->vp_handles[i] = vpath->handle;
                         vpath->ring.gro_enable = vdev->config.gro_enable;
@@ -2031,11 +2064,10 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
                         vdev->stats.vpaths_open++;
                 } else {
                         vdev->stats.vpath_open_fail++;
-                        vxge_debug_init(VXGE_ERR,
-                                "%s: vpath: %d failed to open "
-                                "with status: %d",
-                            vdev->ndev->name, vpath->device_id,
-                                status);
+                        vxge_debug_init(VXGE_ERR, "%s: vpath: %d failed to "
+                                        "open with status: %d",
+                                        vdev->ndev->name, vpath->device_id,
+                                        status);
                         vxge_close_vpaths(vdev, 0);
                         return -EPERM;
                 }
@@ -2043,6 +2075,7 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
                 vp_id = vpath->handle->vpath->vp_id;
                 vdev->vpaths_deployed |= vxge_mBIT(vp_id);
         }
+
         return VXGE_HW_OK;
 }
 
@@ -2062,21 +2095,20 @@ static irqreturn_t vxge_isr_napi(int irq, void *dev_id)
         struct __vxge_hw_device *hldev;
         u64 reason;
         enum vxge_hw_status status;
-        struct vxgedev *vdev = (struct vxgedev *) dev_id;;
+        struct vxgedev *vdev = (struct vxgedev *)dev_id;
 
         vxge_debug_intr(VXGE_TRACE, "%s:%d", __func__, __LINE__);
 
         dev = vdev->ndev;
-        hldev = (struct __vxge_hw_device *)pci_get_drvdata(vdev->pdev);
+        hldev = pci_get_drvdata(vdev->pdev);
 
         if (pci_channel_offline(vdev->pdev))
                 return IRQ_NONE;
 
         if (unlikely(!is_vxge_card_up(vdev)))
-                return IRQ_NONE;
+                return IRQ_HANDLED;
 
-        status = vxge_hw_device_begin_irq(hldev, vdev->exec_mode,
-                        &reason);
+        status = vxge_hw_device_begin_irq(hldev, vdev->exec_mode, &reason);
         if (status == VXGE_HW_OK) {
                 vxge_hw_device_mask_all(hldev);
 
@@ -2301,8 +2333,8 @@ static void vxge_rem_msix_isr(struct vxgedev *vdev)
 
 static void vxge_rem_isr(struct vxgedev *vdev)
 {
-        struct __vxge_hw_device  *hldev;
-        hldev = (struct __vxge_hw_device  *) pci_get_drvdata(vdev->pdev);
+        struct __vxge_hw_device *hldev;
+        hldev = pci_get_drvdata(vdev->pdev);
 
 #ifdef CONFIG_PCI_MSI
         if (vdev->config.intr_type == MSI_X) {
@@ -2529,8 +2561,7 @@ static void vxge_poll_vp_lockup(unsigned long data)
  * Return value: '0' on success and an appropriate (-)ve integer as
  * defined in errno.h file on failure.
  */
-static int
-vxge_open(struct net_device *dev)
+static int vxge_open(struct net_device *dev)
 {
         enum vxge_hw_status status;
         struct vxgedev *vdev;
@@ -2539,11 +2570,12 @@ vxge_open(struct net_device *dev)
         int ret = 0;
         int i;
         u64 val64, function_mode;
+
         vxge_debug_entryexit(VXGE_TRACE,
                 "%s: %s:%d", dev->name, __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
-        hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev);
+        vdev = netdev_priv(dev);
+        hldev = pci_get_drvdata(vdev->pdev);
         function_mode = vdev->config.device_hw_info.function_mode;
 
         /* make sure you have link off by default every time Nic is
@@ -2598,6 +2630,8 @@ vxge_open(struct net_device *dev)
                         goto out2;
                 }
         }
+        printk(KERN_INFO "%s: Receive Hashing Offload %s\n", dev->name,
+               hldev->config.rth_en ? "enabled" : "disabled");
 
         for (i = 0; i < vdev->no_of_vpath; i++) {
                 vpath = &vdev->vpaths[i];
@@ -2683,9 +2717,10 @@ vxge_open(struct net_device *dev)
                 vxge_os_timer(vdev->vp_reset_timer,
                         vxge_poll_vp_reset, vdev, (HZ/2));
 
-        if (vdev->vp_lockup_timer.function == NULL)
-                vxge_os_timer(vdev->vp_lockup_timer,
-                        vxge_poll_vp_lockup, vdev, (HZ/2));
+        /* There is no need to check for RxD leak and RxD lookup on Titan1A */
+        if (vdev->titan1 && vdev->vp_lockup_timer.function == NULL)
+                vxge_os_timer(vdev->vp_lockup_timer, vxge_poll_vp_lockup, vdev,
+                              HZ / 2);
 
         set_bit(__VXGE_STATE_CARD_UP, &vdev->state);
 
@@ -2767,8 +2802,8 @@ static int do_vxge_close(struct net_device *dev, int do_io)
         vxge_debug_entryexit(VXGE_TRACE, "%s: %s:%d",
                 dev->name, __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
-        hldev = (struct __vxge_hw_device *) pci_get_drvdata(vdev->pdev);
+        vdev = netdev_priv(dev);
+        hldev = pci_get_drvdata(vdev->pdev);
 
         if (unlikely(!is_vxge_card_up(vdev)))
                 return 0;
@@ -2778,7 +2813,6 @@ static int do_vxge_close(struct net_device *dev, int do_io)
         while (test_and_set_bit(__VXGE_STATE_RESET_CARD, &vdev->state))
                 msleep(50);
 
-        clear_bit(__VXGE_STATE_CARD_UP, &vdev->state);
         if (do_io) {
                 /* Put the vpath back in normal mode */
                 vpath_vector = vxge_mBIT(vdev->vpaths[0].device_id);
@@ -2789,7 +2823,6 @@ static int do_vxge_close(struct net_device *dev, int do_io)
                                         struct vxge_hw_mrpcim_reg,
                                         rts_mgr_cbasin_cfg),
                                 &val64);
-
                 if (status == VXGE_HW_OK) {
                         val64 &= ~vpath_vector;
                         status = vxge_hw_mgmt_reg_write(vdev->devh,
@@ -2818,10 +2851,17 @@ static int do_vxge_close(struct net_device *dev, int do_io)
 
                 smp_wmb();
         }
-        del_timer_sync(&vdev->vp_lockup_timer);
+
+        if (vdev->titan1)
+                del_timer_sync(&vdev->vp_lockup_timer);
 
         del_timer_sync(&vdev->vp_reset_timer);
 
+        if (do_io)
+                vxge_hw_device_wait_receive_idle(hldev);
+
+        clear_bit(__VXGE_STATE_CARD_UP, &vdev->state);
+
         /* Disable napi */
         if (vdev->config.intr_type != MSI_X)
                 napi_disable(&vdev->napi);
@@ -2838,8 +2878,6 @@ static int do_vxge_close(struct net_device *dev, int do_io)
         if (do_io)
                 vxge_hw_device_intr_disable(vdev->devh);
 
-        mdelay(1000);
-
         vxge_rem_isr(vdev);
 
         vxge_napi_del_all(vdev);
@@ -2868,8 +2906,7 @@ static int do_vxge_close(struct net_device *dev, int do_io)
  * Return value: '0' on success and an appropriate (-)ve integer as
  * defined in errno.h file on failure.
  */
-static int
-vxge_close(struct net_device *dev)
+static int vxge_close(struct net_device *dev)
 {
         do_vxge_close(dev, 1);
         return 0;
@@ -2943,9 +2980,7 @@ vxge_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
                 net_stats->rx_bytes += vdev->vpaths[k].ring.stats.rx_bytes;
                 net_stats->rx_errors += vdev->vpaths[k].ring.stats.rx_errors;
                 net_stats->multicast += vdev->vpaths[k].ring.stats.rx_mcast;
-                net_stats->rx_dropped +=
-                        vdev->vpaths[k].ring.stats.rx_dropped;
-
+                net_stats->rx_dropped += vdev->vpaths[k].ring.stats.rx_dropped;
                 net_stats->tx_packets += vdev->vpaths[k].fifo.stats.tx_frms;
                 net_stats->tx_bytes += vdev->vpaths[k].fifo.stats.tx_bytes;
                 net_stats->tx_errors += vdev->vpaths[k].fifo.stats.tx_errors;
@@ -2954,6 +2989,101 @@ vxge_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
         return net_stats;
 }
 
+static enum vxge_hw_status vxge_timestamp_config(struct vxgedev *vdev,
+                                                 int enable)
+{
+        enum vxge_hw_status status;
+        u64 val64;
+
+        /* Timestamp is passed to the driver via the FCS, therefore we
+         * must disable the FCS stripping by the adapter.  Since this is
+         * required for the driver to load (due to a hardware bug),
+         * there is no need to do anything special here.
+         */
+        if (enable)
+                val64 = VXGE_HW_XMAC_TIMESTAMP_EN |
+                        VXGE_HW_XMAC_TIMESTAMP_USE_LINK_ID(0) |
+                        VXGE_HW_XMAC_TIMESTAMP_INTERVAL(0);
+        else
+                val64 = 0;
+
+        status = vxge_hw_mgmt_reg_write(vdev->devh,
+                                        vxge_hw_mgmt_reg_type_mrpcim,
+                                        0,
+                                        offsetof(struct vxge_hw_mrpcim_reg,
+                                                 xmac_timestamp),
+                                        val64);
+        vxge_hw_device_flush_io(vdev->devh);
+        return status;
+}
+
+static int vxge_hwtstamp_ioctl(struct vxgedev *vdev, void __user *data)
+{
+        struct hwtstamp_config config;
+        enum vxge_hw_status status;
+        int i;
+
+        if (copy_from_user(&config, data, sizeof(config)))
+                return -EFAULT;
+
+        /* reserved for future extensions */
+        if (config.flags)
+                return -EINVAL;
+
+        /* Transmit HW Timestamp not supported */
+        switch (config.tx_type) {
+        case HWTSTAMP_TX_OFF:
+                break;
+        case HWTSTAMP_TX_ON:
+        default:
+                return -ERANGE;
+        }
+
+        switch (config.rx_filter) {
+        case HWTSTAMP_FILTER_NONE:
+                status = vxge_timestamp_config(vdev, 0);
+                if (status != VXGE_HW_OK)
+                        return -EFAULT;
+
+                vdev->rx_hwts = 0;
+                config.rx_filter = HWTSTAMP_FILTER_NONE;
+                break;
+
+        case HWTSTAMP_FILTER_ALL:
+        case HWTSTAMP_FILTER_SOME:
+        case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+        case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+        case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+        case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+        case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+        case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+        case HWTSTAMP_FILTER_PTP_V2_EVENT:
+        case HWTSTAMP_FILTER_PTP_V2_SYNC:
+        case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+                status = vxge_timestamp_config(vdev, 1);
+                if (status != VXGE_HW_OK)
+                        return -EFAULT;
+
+                vdev->rx_hwts = 1;
+                config.rx_filter = HWTSTAMP_FILTER_ALL;
+                break;
+
+        default:
+                 return -ERANGE;
+        }
+
+        for (i = 0; i < vdev->no_of_vpath; i++)
+                vdev->vpaths[i].ring.rx_hwts = vdev->rx_hwts;
+
+        if (copy_to_user(data, &config, sizeof(config)))
+                return -EFAULT;
+
+        return 0;
+}
+
 /**
  * vxge_ioctl
  * @dev: Device pointer.
@@ -2966,7 +3096,20 @@ vxge_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
  */
 static int vxge_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
-        return -EOPNOTSUPP;
+        struct vxgedev *vdev = netdev_priv(dev);
+        int ret;
+
+        switch (cmd) {
+        case SIOCSHWTSTAMP:
+                ret = vxge_hwtstamp_ioctl(vdev, rq->ifr_data);
+                if (ret)
+                        return ret;
+                break;
+        default:
+                return -EOPNOTSUPP;
+        }
+
+        return 0;
 }
 
 /**
@@ -2977,18 +3120,17 @@ static int vxge_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  * This function is triggered if the Tx Queue is stopped
  * for a pre-defined amount of time when the Interface is still up.
  */
-static void
-vxge_tx_watchdog(struct net_device *dev)
+static void vxge_tx_watchdog(struct net_device *dev)
 {
         struct vxgedev *vdev;
 
         vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
 
         vdev->cric_err_event = VXGE_HW_EVENT_RESET_START;
 
-        vxge_reset(vdev);
+        schedule_work(&vdev->reset_task);
         vxge_debug_entryexit(VXGE_TRACE,
                 "%s:%d  Exiting...", __func__, __LINE__);
 }
@@ -3012,7 +3154,7 @@ vxge_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 
         vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
 
         vpath = &vdev->vpaths[0];
         if ((NULL == grp) && (vpath->is_open)) {
@@ -3061,7 +3203,7 @@ vxge_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
         struct vxge_vpath *vpath;
         int vp_id;
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
 
         /* Add these vlan to the vid table */
         for (vp_id = 0; vp_id < vdev->no_of_vpath; vp_id++) {
@@ -3088,7 +3230,7 @@ vxge_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 
         vxge_debug_entryexit(VXGE_TRACE, "%s:%d", __func__, __LINE__);
 
-        vdev = (struct vxgedev *)netdev_priv(dev);
+        vdev = netdev_priv(dev);
 
         vlan_group_set_device(vdev->vlgrp, vid, NULL);
 
@@ -3110,21 +3252,31 @@ static const struct net_device_ops vxge_netdev_ops = {
         .ndo_start_xmit         = vxge_xmit,
         .ndo_validate_addr      = eth_validate_addr,
         .ndo_set_multicast_list = vxge_set_multicast,
-
         .ndo_do_ioctl           = vxge_ioctl,
-
         .ndo_set_mac_address    = vxge_set_mac_addr,
         .ndo_change_mtu         = vxge_change_mtu,
         .ndo_vlan_rx_register   = vxge_vlan_rx_register,
         .ndo_vlan_rx_kill_vid   = vxge_vlan_rx_kill_vid,
         .ndo_vlan_rx_add_vid    = vxge_vlan_rx_add_vid,
-
         .ndo_tx_timeout         = vxge_tx_watchdog,
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller    = vxge_netpoll,
 #endif
 };
 
+static int __devinit vxge_device_revision(struct vxgedev *vdev)
+{
+        int ret;
+        u8 revision;
+
+        ret = pci_read_config_byte(vdev->pdev, PCI_REVISION_ID, &revision);
+        if (ret)
+                return -EIO;
+
+        vdev->titan1 = (revision == VXGE_HW_TITAN1_PCI_REVISION);
+        return 0;
+}
+
 static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
                                           struct vxge_config *config,
                                           int high_dma, int no_of_vpath,
@@ -3163,6 +3315,11 @@ static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
         vdev->pdev = hldev->pdev;
         memcpy(&vdev->config, config, sizeof(struct vxge_config));
         vdev->rx_csum = 1;      /* Enable Rx CSUM by default. */
+        vdev->rx_hwts = 0;
+
+        ret = vxge_device_revision(vdev);
+        if (ret < 0)
+                goto _out1;
 
         SET_NETDEV_DEV(ndev, &vdev->pdev->dev);
 
@@ -3175,9 +3332,15 @@ static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
         ndev->netdev_ops = &vxge_netdev_ops;
 
         ndev->watchdog_timeo = VXGE_LL_WATCH_DOG_TIMEOUT;
+        INIT_WORK(&vdev->reset_task, vxge_reset);
 
         vxge_initialize_ethtool_ops(ndev);
 
+        if (vdev->config.rth_steering != NO_STEERING) {
+                ndev->features |= NETIF_F_RXHASH;
+                hldev->config.rth_en = VXGE_HW_RTH_ENABLE;
+        }
+
         /* Allocate memory for vpath */
         vdev->vpaths = kzalloc((sizeof(struct vxge_vpath)) *
                                 no_of_vpath, GFP_KERNEL);
@@ -3191,7 +3354,7 @@ static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
 
         ndev->features |= NETIF_F_SG;
 
-        ndev->features |= NETIF_F_HW_CSUM;
+        ndev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
         vxge_debug_init(vxge_hw_device_trace_level_get(hldev),
                 "%s : checksuming enabled", __func__);
 
@@ -3227,6 +3390,7 @@ static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
                 "%s: Ethernet device registered",
                 ndev->name);
 
+        hldev->ndev = ndev;
         *vdev_out = vdev;
 
         /* Resetting the Device stats */
@@ -3261,36 +3425,29 @@ _out0:
  *
  * This function will unregister and free network device
  */
-static void
-vxge_device_unregister(struct __vxge_hw_device *hldev)
+static void vxge_device_unregister(struct __vxge_hw_device *hldev)
 {
         struct vxgedev *vdev;
         struct net_device *dev;
         char buf[IFNAMSIZ];
-#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \
-        (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK))
-        u32 level_trace;
-#endif
 
         dev = hldev->ndev;
         vdev = netdev_priv(dev);
-#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \
-        (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK))
-        level_trace = vdev->level_trace;
-#endif
-        vxge_debug_entryexit(level_trace,
-                "%s: %s:%d", vdev->ndev->name, __func__, __LINE__);
 
-        memcpy(buf, vdev->ndev->name, IFNAMSIZ);
+        vxge_debug_entryexit(vdev->level_trace, "%s: %s:%d", vdev->ndev->name,
+                             __func__, __LINE__);
+
+        strncpy(buf, dev->name, IFNAMSIZ);
+
+        flush_work_sync(&vdev->reset_task);
 
         /* in 2.6 will call stop() if device is up */
         unregister_netdev(dev);
 
-        flush_scheduled_work();
-
-        vxge_debug_init(level_trace, "%s: ethernet device unregistered", buf);
-        vxge_debug_entryexit(level_trace,
-                "%s: %s:%d  Exiting...", buf, __func__, __LINE__);
+        vxge_debug_init(vdev->level_trace, "%s: ethernet device unregistered",
+                        buf);
+        vxge_debug_entryexit(vdev->level_trace, "%s: %s:%d  Exiting...", buf,
+                             __func__, __LINE__);
 }
 
 /*
@@ -3304,7 +3461,7 @@ vxge_callback_crit_err(struct __vxge_hw_device *hldev,
                         enum vxge_hw_event type, u64 vp_id)
 {
         struct net_device *dev = hldev->ndev;
-        struct vxgedev *vdev = (struct vxgedev *)netdev_priv(dev);
+        struct vxgedev *vdev = netdev_priv(dev);
         struct vxge_vpath *vpath = NULL;
         int vpath_idx;
 
@@ -3527,9 +3684,9 @@ static int __devinit vxge_config_vpaths(
                 device_config->vp_config[i].tti.timer_ac_en =
                                 VXGE_HW_TIM_TIMER_AC_ENABLE;
 
-                /* For msi-x with napi (each vector
-                has a handler of its own) -
-                Set CI to OFF for all vpaths */
+                /* For msi-x with napi (each vector has a handler of its own) -
+                 * Set CI to OFF for all vpaths
+                 */
                 device_config->vp_config[i].tti.timer_ci_en =
                         VXGE_HW_TIM_TIMER_CI_DISABLE;
 
@@ -3559,10 +3716,13 @@ static int __devinit vxge_config_vpaths(
 
                 device_config->vp_config[i].ring.ring_blocks  =
                                                 VXGE_HW_DEF_RING_BLOCKS;
+
                 device_config->vp_config[i].ring.buffer_mode =
                         VXGE_HW_RING_RXD_BUFFER_MODE_1;
+
                 device_config->vp_config[i].ring.rxds_limit  =
                                 VXGE_HW_DEF_RING_RXDS_LIMIT;
+
                 device_config->vp_config[i].ring.scatter_mode =
                                         VXGE_HW_RING_SCATTER_MODE_A;
 
@@ -3642,6 +3802,7 @@ static void __devinit vxge_device_config_init(
                 device_config->intr_mode = VXGE_HW_INTR_MODE_MSIX;
                 break;
         }
+
         /* Timer period between device poll */
         device_config->device_poll_millis = VXGE_TIMER_DELAY;
 
@@ -3653,16 +3814,10 @@ static void __devinit vxge_device_config_init(
 
         vxge_debug_ll_config(VXGE_TRACE, "%s : Device Config Params ",
                         __func__);
-        vxge_debug_ll_config(VXGE_TRACE, "dma_blockpool_initial : %d",
-                        device_config->dma_blockpool_initial);
-        vxge_debug_ll_config(VXGE_TRACE, "dma_blockpool_max : %d",
-                        device_config->dma_blockpool_max);
         vxge_debug_ll_config(VXGE_TRACE, "intr_mode : %d",
                         device_config->intr_mode);
         vxge_debug_ll_config(VXGE_TRACE, "device_poll_millis : %d",
                         device_config->device_poll_millis);
-        vxge_debug_ll_config(VXGE_TRACE, "rts_mac_en : %d",
-                        device_config->rts_mac_en);
         vxge_debug_ll_config(VXGE_TRACE, "rth_en : %d",
                         device_config->rth_en);
         vxge_debug_ll_config(VXGE_TRACE, "rth_it_type : %d",
@@ -3751,9 +3906,6 @@ static void __devinit vxge_print_parm(struct vxgedev *vdev, u64 vpath_mask)
                 vxge_debug_init(VXGE_TRACE,
                         "%s: MAC Address learning enabled", vdev->ndev->name);
 
-        vxge_debug_init(VXGE_TRACE,
-                "%s: Rx doorbell mode enabled", vdev->ndev->name);
-
         for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
                 if (!vxge_bVALn(vpath_mask, i, 1))
                         continue;
@@ -3766,14 +3918,6 @@ static void __devinit vxge_print_parm(struct vxgedev *vdev, u64 vpath_mask)
                         ((struct __vxge_hw_device  *)(vdev->devh))->
                                 config.vp_config[i].rpa_strip_vlan_tag
                         ? "Enabled" : "Disabled");
-                vxge_debug_init(VXGE_TRACE,
-                        "%s: Ring blocks : %d", vdev->ndev->name,
-                        ((struct __vxge_hw_device  *)(vdev->devh))->
-                                config.vp_config[i].ring.ring_blocks);
-                vxge_debug_init(VXGE_TRACE,
-                        "%s: Fifo blocks : %d", vdev->ndev->name,
-                        ((struct __vxge_hw_device  *)(vdev->devh))->
-                                config.vp_config[i].fifo.fifo_blocks);
                 vxge_debug_ll_config(VXGE_TRACE,
                         "%s: Max frags : %d", vdev->ndev->name,
                         ((struct __vxge_hw_device  *)(vdev->devh))->
@@ -3813,8 +3957,7 @@ static int vxge_pm_resume(struct pci_dev *pdev)
 static pci_ers_result_t vxge_io_error_detected(struct pci_dev *pdev,
                                                 pci_channel_state_t state)
 {
-        struct __vxge_hw_device  *hldev =
-                (struct __vxge_hw_device  *) pci_get_drvdata(pdev);
+        struct __vxge_hw_device *hldev = pci_get_drvdata(pdev);
         struct net_device *netdev = hldev->ndev;
 
         netif_device_detach(netdev);
@@ -3843,8 +3986,7 @@ static pci_ers_result_t vxge_io_error_detected(struct pci_dev *pdev,
  */
 static pci_ers_result_t vxge_io_slot_reset(struct pci_dev *pdev)
 {
-        struct __vxge_hw_device  *hldev =
-                (struct __vxge_hw_device  *) pci_get_drvdata(pdev);
+        struct __vxge_hw_device *hldev = pci_get_drvdata(pdev);
         struct net_device *netdev = hldev->ndev;
 
         struct vxgedev *vdev = netdev_priv(netdev);
@@ -3855,7 +3997,7 @@ static pci_ers_result_t vxge_io_slot_reset(struct pci_dev *pdev)
         }
 
         pci_set_master(pdev);
-        vxge_reset(vdev);
+        do_vxge_reset(vdev, VXGE_LL_FULL_RESET);
 
         return PCI_ERS_RESULT_RECOVERED;
 }
@@ -3869,8 +4011,7 @@ static pci_ers_result_t vxge_io_slot_reset(struct pci_dev *pdev)
  */
 static void vxge_io_resume(struct pci_dev *pdev)
 {
-        struct __vxge_hw_device  *hldev =
-                (struct __vxge_hw_device  *) pci_get_drvdata(pdev);
+        struct __vxge_hw_device *hldev = pci_get_drvdata(pdev);
         struct net_device *netdev = hldev->ndev;
 
         if (netif_running(netdev)) {
@@ -3914,6 +4055,156 @@ static inline u32 vxge_get_num_vfs(u64 function_mode)
         return num_functions;
 }
 
+int vxge_fw_upgrade(struct vxgedev *vdev, char *fw_name, int override)
+{
+        struct __vxge_hw_device *hldev = vdev->devh;
+        u32 maj, min, bld, cmaj, cmin, cbld;
+        enum vxge_hw_status status;
+        const struct firmware *fw;
+        int ret;
+
+        ret = request_firmware(&fw, fw_name, &vdev->pdev->dev);
+        if (ret) {
+                vxge_debug_init(VXGE_ERR, "%s: Firmware file '%s' not found",
+                                VXGE_DRIVER_NAME, fw_name);
+                goto out;
+        }
+
+        /* Load the new firmware onto the adapter */
+        status = vxge_update_fw_image(hldev, fw->data, fw->size);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR,
+                                "%s: FW image download to adapter failed '%s'.",
+                                VXGE_DRIVER_NAME, fw_name);
+                ret = -EIO;
+                goto out;
+        }
+
+        /* Read the version of the new firmware */
+        status = vxge_hw_upgrade_read_version(hldev, &maj, &min, &bld);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR,
+                                "%s: Upgrade read version failed '%s'.",
+                                VXGE_DRIVER_NAME, fw_name);
+                ret = -EIO;
+                goto out;
+        }
+
+        cmaj = vdev->config.device_hw_info.fw_version.major;
+        cmin = vdev->config.device_hw_info.fw_version.minor;
+        cbld = vdev->config.device_hw_info.fw_version.build;
+        /* It's possible the version in /lib/firmware is not the latest version.
+         * If so, we could get into a loop of trying to upgrade to the latest
+         * and flashing the older version.
+         */
+        if (VXGE_FW_VER(maj, min, bld) == VXGE_FW_VER(cmaj, cmin, cbld) &&
+            !override) {
+                ret = -EINVAL;
+                goto out;
+        }
+
+        printk(KERN_NOTICE "Upgrade to firmware version %d.%d.%d commencing\n",
+               maj, min, bld);
+
+        /* Flash the adapter with the new firmware */
+        status = vxge_hw_flash_fw(hldev);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR, "%s: Upgrade commit failed '%s'.",
+                                VXGE_DRIVER_NAME, fw_name);
+                ret = -EIO;
+                goto out;
+        }
+
+        printk(KERN_NOTICE "Upgrade of firmware successful!  Adapter must be "
+               "hard reset before using, thus requiring a system reboot or a "
+               "hotplug event.\n");
+
+out:
+        return ret;
+}
+
+static int vxge_probe_fw_update(struct vxgedev *vdev)
+{
+        u32 maj, min, bld;
+        int ret, gpxe = 0;
+        char *fw_name;
+
+        maj = vdev->config.device_hw_info.fw_version.major;
+        min = vdev->config.device_hw_info.fw_version.minor;
+        bld = vdev->config.device_hw_info.fw_version.build;
+
+        if (VXGE_FW_VER(maj, min, bld) == VXGE_CERT_FW_VER)
+                return 0;
+
+        /* Ignore the build number when determining if the current firmware is
+         * "too new" to load the driver
+         */
+        if (VXGE_FW_VER(maj, min, 0) > VXGE_CERT_FW_VER) {
+                vxge_debug_init(VXGE_ERR, "%s: Firmware newer than last known "
+                                "version, unable to load driver\n",
+                                VXGE_DRIVER_NAME);
+                return -EINVAL;
+        }
+
+        /* Firmware 1.4.4 and older cannot be upgraded, and is too ancient to
+         * work with this driver.
+         */
+        if (VXGE_FW_VER(maj, min, bld) <= VXGE_FW_DEAD_VER) {
+                vxge_debug_init(VXGE_ERR, "%s: Firmware %d.%d.%d cannot be "
+                                "upgraded\n", VXGE_DRIVER_NAME, maj, min, bld);
+                return -EINVAL;
+        }
+
+        /* If file not specified, determine gPXE or not */
+        if (VXGE_FW_VER(maj, min, bld) >= VXGE_EPROM_FW_VER) {
+                int i;
+                for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++)
+                        if (vdev->devh->eprom_versions[i]) {
+                                gpxe = 1;
+                                break;
+                        }
+        }
+        if (gpxe)
+                fw_name = "vxge/X3fw-pxe.ncf";
+        else
+                fw_name = "vxge/X3fw.ncf";
+
+        ret = vxge_fw_upgrade(vdev, fw_name, 0);
+        /* -EINVAL and -ENOENT are not fatal errors for flashing firmware on
+         * probe, so ignore them
+         */
+        if (ret != -EINVAL && ret != -ENOENT)
+                return -EIO;
+        else
+                ret = 0;
+
+        if (VXGE_FW_VER(VXGE_CERT_FW_VER_MAJOR, VXGE_CERT_FW_VER_MINOR, 0) >
+            VXGE_FW_VER(maj, min, 0)) {
+                vxge_debug_init(VXGE_ERR, "%s: Firmware %d.%d.%d is too old to"
+                                " be used with this driver.\n"
+                                "Please get the latest version from "
+                                "ftp://ftp.s2io.com/pub/X3100-Drivers/FIRMWARE",
+                                VXGE_DRIVER_NAME, maj, min, bld);
+                return -EINVAL;
+        }
+
+        return ret;
+}
+
+static int __devinit is_sriov_initialized(struct pci_dev *pdev)
+{
+        int pos;
+        u16 ctrl;
+
+        pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
+        if (pos) {
+                pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
+                if (ctrl & PCI_SRIOV_CTRL_VFE)
+                        return 1;
+        }
+        return 0;
+}
+
 /**
  * vxge_probe
  * @pdev : structure containing the PCI related information of the device.
@@ -3928,7 +4219,7 @@ static inline u32 vxge_get_num_vfs(u64 function_mode)
 static int __devinit
 vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
 {
-        struct __vxge_hw_device  *hldev;
+        struct __vxge_hw_device *hldev;
         enum vxge_hw_status status;
         int ret;
         int high_dma = 0;
@@ -3951,9 +4242,10 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
         attr.pdev = pdev;
 
         /* In SRIOV-17 mode, functions of the same adapter
-         * can be deployed on different buses */
-        if ((!pdev->is_virtfn) && ((bus != pdev->bus->number) ||
-                (device != PCI_SLOT(pdev->devfn))))
+         * can be deployed on different buses
+         */
+        if (((bus != pdev->bus->number) || (device != PCI_SLOT(pdev->devfn))) &&
+            !pdev->is_virtfn)
                 new_device = 1;
 
         bus = pdev->bus->number;
@@ -3971,6 +4263,7 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
                 driver_config->config_dev_cnt = 0;
                 driver_config->total_dev_cnt = 0;
         }
+
         /* Now making the CPU based no of vpath calculation
          * applicable for individual functions as well.
          */
@@ -3993,11 +4286,11 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
                 goto _exit0;
         }
 
-        ll_config = kzalloc(sizeof(*ll_config), GFP_KERNEL);
+        ll_config = kzalloc(sizeof(struct vxge_config), GFP_KERNEL);
         if (!ll_config) {
                 ret = -ENOMEM;
                 vxge_debug_init(VXGE_ERR,
-                        "ll_config : malloc failed %s %d",
+                        "device_config : malloc failed %s %d",
                         __FILE__, __LINE__);
                 goto _exit0;
         }
@@ -4041,7 +4334,7 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
                 goto _exit1;
         }
 
-        if (pci_request_regions(pdev, VXGE_DRIVER_NAME)) {
+        if (pci_request_region(pdev, 0, VXGE_DRIVER_NAME)) {
                 vxge_debug_init(VXGE_ERR,
                         "%s : request regions failed", __func__);
                 ret = -ENODEV;
@@ -4072,16 +4365,6 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
                 goto _exit3;
         }
 
-        if (ll_config->device_hw_info.fw_version.major !=
-                VXGE_DRIVER_FW_VERSION_MAJOR) {
-                vxge_debug_init(VXGE_ERR,
-                        "%s: Incorrect firmware version."
-                        "Please upgrade the firmware to version 1.x.x",
-                        VXGE_DRIVER_NAME);
-                ret = -EINVAL;
-                goto _exit3;
-        }
-
         vpath_mask = ll_config->device_hw_info.vpath_mask;
         if (vpath_mask == 0) {
                 vxge_debug_ll_config(VXGE_TRACE,
@@ -4110,14 +4393,13 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
                 num_vfs = vxge_get_num_vfs(function_mode) - 1;
 
         /* Enable SRIOV mode, if firmware has SRIOV support and if it is a PF */
-        if (is_sriov(function_mode) && (max_config_dev > 1) &&
-                (ll_config->intr_type != INTA) &&
-                (is_privileged == VXGE_HW_OK)) {
-                ret = pci_enable_sriov(pdev, ((max_config_dev - 1) < num_vfs)
-                        ? (max_config_dev - 1) : num_vfs);
+        if (is_sriov(function_mode) && !is_sriov_initialized(pdev) &&
+           (ll_config->intr_type != INTA)) {
+                ret = pci_enable_sriov(pdev, num_vfs);
                 if (ret)
                         vxge_debug_ll_config(VXGE_ERR,
                                 "Failed in enabling SRIOV mode: %d\n", ret);
+                        /* No need to fail out, as an error here is non-fatal */
         }
 
         /*
@@ -4145,11 +4427,37 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
                         goto _exit3;
         }
 
+        if (VXGE_FW_VER(ll_config->device_hw_info.fw_version.major,
+                        ll_config->device_hw_info.fw_version.minor,
+                        ll_config->device_hw_info.fw_version.build) >=
+            VXGE_EPROM_FW_VER) {
+                struct eprom_image img[VXGE_HW_MAX_ROM_IMAGES];
+
+                status = vxge_hw_vpath_eprom_img_ver_get(hldev, img);
+                if (status != VXGE_HW_OK) {
+                        vxge_debug_init(VXGE_ERR, "%s: Reading of EPROM failed",
+                                        VXGE_DRIVER_NAME);
+                        /* This is a non-fatal error, continue */
+                }
+
+                for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
+                        hldev->eprom_versions[i] = img[i].version;
+                        if (!img[i].is_valid)
+                                break;
+                        vxge_debug_init(VXGE_TRACE, "%s: EPROM %d, version "
+                                        "%d.%d.%d.%d\n", VXGE_DRIVER_NAME, i,
+                                        VXGE_EPROM_IMG_MAJOR(img[i].version),
+                                        VXGE_EPROM_IMG_MINOR(img[i].version),
+                                        VXGE_EPROM_IMG_FIX(img[i].version),
+                                        VXGE_EPROM_IMG_BUILD(img[i].version));
+                }
+        }
+
         /* if FCS stripping is not disabled in MAC fail driver load */
-        if (vxge_hw_vpath_strip_fcs_check(hldev, vpath_mask) != VXGE_HW_OK) {
-                vxge_debug_init(VXGE_ERR,
-                        "%s: FCS stripping is not disabled in MAC"
-                        " failing driver load", VXGE_DRIVER_NAME);
+        status = vxge_hw_vpath_strip_fcs_check(hldev, vpath_mask);
+        if (status != VXGE_HW_OK) {
+                vxge_debug_init(VXGE_ERR, "%s: FCS stripping is enabled in MAC"
+                                " failing driver load", VXGE_DRIVER_NAME);
                 ret = -EINVAL;
                 goto _exit4;
         }
@@ -4163,28 +4471,32 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
         ll_config->fifo_indicate_max_pkts = VXGE_FIFO_INDICATE_MAX_PKTS;
         ll_config->addr_learn_en = addr_learn_en;
         ll_config->rth_algorithm = RTH_ALG_JENKINS;
-        ll_config->rth_hash_type_tcpipv4 = VXGE_HW_RING_HASH_TYPE_TCP_IPV4;
-        ll_config->rth_hash_type_ipv4 = VXGE_HW_RING_HASH_TYPE_NONE;
-        ll_config->rth_hash_type_tcpipv6 = VXGE_HW_RING_HASH_TYPE_NONE;
-        ll_config->rth_hash_type_ipv6 = VXGE_HW_RING_HASH_TYPE_NONE;
-        ll_config->rth_hash_type_tcpipv6ex = VXGE_HW_RING_HASH_TYPE_NONE;
-        ll_config->rth_hash_type_ipv6ex = VXGE_HW_RING_HASH_TYPE_NONE;
+        ll_config->rth_hash_type_tcpipv4 = 1;
+        ll_config->rth_hash_type_ipv4 = 0;
+        ll_config->rth_hash_type_tcpipv6 = 0;
+        ll_config->rth_hash_type_ipv6 = 0;
+        ll_config->rth_hash_type_tcpipv6ex = 0;
+        ll_config->rth_hash_type_ipv6ex = 0;
         ll_config->rth_bkt_sz = RTH_BUCKET_SIZE;
         ll_config->tx_pause_enable = VXGE_PAUSE_CTRL_ENABLE;
         ll_config->rx_pause_enable = VXGE_PAUSE_CTRL_ENABLE;
 
-        if (vxge_device_register(hldev, ll_config, high_dma, no_of_vpath,
-                &vdev)) {
+        ret = vxge_device_register(hldev, ll_config, high_dma, no_of_vpath,
+                                   &vdev);
+        if (ret) {
                 ret = -EINVAL;
                 goto _exit4;
         }
 
+        ret = vxge_probe_fw_update(vdev);
+        if (ret)
+                goto _exit5;
+
         vxge_hw_device_debug_set(hldev, VXGE_TRACE, VXGE_COMPONENT_LL);
         VXGE_COPY_DEBUG_INFO_TO_LL(vdev, vxge_hw_device_error_level_get(hldev),
                 vxge_hw_device_trace_level_get(hldev));
 
         /* set private HW device info */
-        hldev->ndev = vdev->ndev;
         vdev->mtu = VXGE_HW_DEFAULT_MTU;
         vdev->bar0 = attr.bar0;
         vdev->max_vpath_supported = max_vpath_supported;
@@ -4278,15 +4590,13 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
 
         /* Copy the station mac address to the list */
         for (i = 0; i < vdev->no_of_vpath; i++) {
-                entry = (struct vxge_mac_addrs *)
-                                kzalloc(sizeof(struct vxge_mac_addrs),
-                                        GFP_KERNEL);
+                entry = kzalloc(sizeof(struct vxge_mac_addrs), GFP_KERNEL);
                 if (NULL == entry) {
                         vxge_debug_init(VXGE_ERR,
                                 "%s: mac_addr_list : memory allocation failed",
                                 vdev->ndev->name);
                         ret = -EPERM;
-                        goto _exit5;
+                        goto _exit6;
                 }
                 macaddr = (u8 *)&entry->macaddr;
                 memcpy(macaddr, vdev->ndev->dev_addr, ETH_ALEN);
@@ -4326,10 +4636,10 @@ vxge_probe(struct pci_dev *pdev, const struct pci_device_id *pre)
         kfree(ll_config);
         return 0;
 
-_exit5:
+_exit6:
         for (i = 0; i < vdev->no_of_vpath; i++)
                 vxge_free_mac_add_list(&vdev->vpaths[i]);
-
+_exit5:
         vxge_device_unregister(hldev);
 _exit4:
         pci_disable_sriov(pdev);
@@ -4337,7 +4647,7 @@ _exit4:
 _exit3:
         iounmap(attr.bar0);
 _exit2:
-        pci_release_regions(pdev);
+        pci_release_region(pdev, 0);
 _exit1:
         pci_disable_device(pdev);
 _exit0:
@@ -4354,34 +4664,25 @@ _exit0:
  * Description: This function is called by the Pci subsystem to release a
  * PCI device and free up all resource held up by the device.
  */
-static void __devexit
-vxge_remove(struct pci_dev *pdev)
+static void __devexit vxge_remove(struct pci_dev *pdev)
 {
-        struct __vxge_hw_device  *hldev;
+        struct __vxge_hw_device *hldev;
         struct vxgedev *vdev = NULL;
         struct net_device *dev;
         int i = 0;
-#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \
-        (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK))
-        u32 level_trace;
-#endif
 
-        hldev = (struct __vxge_hw_device  *) pci_get_drvdata(pdev);
+        hldev = pci_get_drvdata(pdev);
 
         if (hldev == NULL)
                 return;
+
         dev = hldev->ndev;
         vdev = netdev_priv(dev);
 
-#if ((VXGE_DEBUG_INIT & VXGE_DEBUG_MASK) || \
-        (VXGE_DEBUG_ENTRYEXIT & VXGE_DEBUG_MASK))
-        level_trace = vdev->level_trace;
-#endif
-        vxge_debug_entryexit(level_trace,
-                "%s:%d", __func__, __LINE__);
+        vxge_debug_entryexit(vdev->level_trace, "%s:%d", __func__, __LINE__);
 
-        vxge_debug_init(level_trace,
-                "%s : removing PCI device...", __func__);
+        vxge_debug_init(vdev->level_trace, "%s : removing PCI device...",
+                        __func__);
         vxge_device_unregister(hldev);
 
         for (i = 0; i < vdev->no_of_vpath; i++) {
@@ -4394,21 +4695,19 @@ vxge_remove(struct pci_dev *pdev)
 
         iounmap(vdev->bar0);
 
-        pci_disable_sriov(pdev);
-
         /* we are safe to free it now */
         free_netdev(dev);
 
-        vxge_debug_init(level_trace,
-                "%s:%d  Device unregistered", __func__, __LINE__);
+        vxge_debug_init(vdev->level_trace, "%s:%d Device unregistered",
+                        __func__, __LINE__);
 
         vxge_hw_device_terminate(hldev);
 
         pci_disable_device(pdev);
-        pci_release_regions(pdev);
+        pci_release_region(pdev, 0);
         pci_set_drvdata(pdev, NULL);
-        vxge_debug_entryexit(level_trace,
-                "%s:%d  Exiting...", __func__, __LINE__);
+        vxge_debug_entryexit(vdev->level_trace, "%s:%d  Exiting...", __func__,
+                             __LINE__);
 }
 
 static struct pci_error_handlers vxge_err_handler = {
@@ -4444,6 +4743,10 @@ vxge_starter(void)
                 return -ENOMEM;
 
         ret = pci_register_driver(&vxge_driver);
+        if (ret) {
+                kfree(driver_config);
+                goto err;
+        }
 
         if (driver_config->config_dev_cnt &&
            (driver_config->config_dev_cnt != driver_config->total_dev_cnt))
@@ -4451,10 +4754,7 @@ vxge_starter(void)
                         "%s: Configured %d of %d devices",
                         VXGE_DRIVER_NAME, driver_config->config_dev_cnt,
                         driver_config->total_dev_cnt);
-
-        if (ret)
-                kfree(driver_config);
-
+err:
         return ret;
 }
 
diff --git a/drivers/net/vxge/vxge-main.h b/drivers/net/vxge/vxge-main.h
index de64536cb7d0..5746fedc356f 100644
--- a/drivers/net/vxge/vxge-main.h
+++ b/drivers/net/vxge/vxge-main.h
@@ -29,6 +29,9 @@
 
 #define PCI_DEVICE_ID_TITAN_WIN         0x5733
 #define PCI_DEVICE_ID_TITAN_UNI         0x5833
+#define VXGE_HW_TITAN1_PCI_REVISION     1
+#define VXGE_HW_TITAN1A_PCI_REVISION    2
+
 #define VXGE_USE_DEFAULT                0xffffffff
 #define VXGE_HW_VPATH_MSIX_ACTIVE       4
 #define VXGE_ALARM_MSIX_ID              2
@@ -53,11 +56,13 @@
 
 #define VXGE_TTI_BTIMER_VAL 250000
 
-#define VXGE_TTI_LTIMER_VAL 1000
-#define VXGE_TTI_RTIMER_VAL 0
-#define VXGE_RTI_BTIMER_VAL 250
-#define VXGE_RTI_LTIMER_VAL 100
-#define VXGE_RTI_RTIMER_VAL 0
+#define VXGE_TTI_LTIMER_VAL     1000
+#define VXGE_T1A_TTI_LTIMER_VAL 80
+#define VXGE_TTI_RTIMER_VAL     0
+#define VXGE_T1A_TTI_RTIMER_VAL 400
+#define VXGE_RTI_BTIMER_VAL     250
+#define VXGE_RTI_LTIMER_VAL     100
+#define VXGE_RTI_RTIMER_VAL     0
 #define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH
 #define VXGE_ISR_POLLING_CNT    8
 #define VXGE_MAX_CONFIG_DEV     0xFF
@@ -76,14 +81,32 @@
 #define TTI_TX_UFC_B    40
 #define TTI_TX_UFC_C    60
 #define TTI_TX_UFC_D    100
+#define TTI_T1A_TX_UFC_A        30
+#define TTI_T1A_TX_UFC_B        80
+/* Slope - (max_mtu - min_mtu)/(max_mtu_ufc - min_mtu_ufc) */
+/* Slope - 93 */
+/* 60 - 9k Mtu, 140 - 1.5k mtu */
+#define TTI_T1A_TX_UFC_C(mtu)   (60 + ((VXGE_HW_MAX_MTU - mtu) / 93))
+
+/* Slope - 37 */
+/* 100 - 9k Mtu, 300 - 1.5k mtu */
+#define TTI_T1A_TX_UFC_D(mtu)   (100 + ((VXGE_HW_MAX_MTU - mtu) / 37))
+
+
+#define RTI_RX_URANGE_A         5
+#define RTI_RX_URANGE_B         15
+#define RTI_RX_URANGE_C         40
+#define RTI_T1A_RX_URANGE_A     1
+#define RTI_T1A_RX_URANGE_B     20
+#define RTI_T1A_RX_URANGE_C     50
+#define RTI_RX_UFC_A            1
+#define RTI_RX_UFC_B            5
+#define RTI_RX_UFC_C            10
+#define RTI_RX_UFC_D            15
+#define RTI_T1A_RX_UFC_B        20
+#define RTI_T1A_RX_UFC_C        50
+#define RTI_T1A_RX_UFC_D        60
 
-#define RTI_RX_URANGE_A 5
-#define RTI_RX_URANGE_B 15
-#define RTI_RX_URANGE_C 40
-#define RTI_RX_UFC_A    1
-#define RTI_RX_UFC_B    5
-#define RTI_RX_UFC_C    10
-#define RTI_RX_UFC_D    15
 
 /* Milli secs timer period */
 #define VXGE_TIMER_DELAY                10000
@@ -145,15 +168,15 @@ struct vxge_config {
 
         int             addr_learn_en;
 
-        int             rth_steering;
-        int             rth_algorithm;
-        int             rth_hash_type_tcpipv4;
-        int             rth_hash_type_ipv4;
-        int             rth_hash_type_tcpipv6;
-        int             rth_hash_type_ipv6;
-        int             rth_hash_type_tcpipv6ex;
-        int             rth_hash_type_ipv6ex;
-        int             rth_bkt_sz;
+        u32             rth_steering:2,
+                        rth_algorithm:2,
+                        rth_hash_type_tcpipv4:1,
+                        rth_hash_type_ipv4:1,
+                        rth_hash_type_tcpipv6:1,
+                        rth_hash_type_ipv6:1,
+                        rth_hash_type_tcpipv6ex:1,
+                        rth_hash_type_ipv6ex:1,
+                        rth_bkt_sz:8;
         int             rth_jhash_golden_ratio;
         int             tx_steering_type;
         int     fifo_indicate_max_pkts;
@@ -248,8 +271,9 @@ struct vxge_ring {
          */
         int driver_id;
 
-         /* copy of the flag indicating whether rx_csum is to be used */
-        u32 rx_csum;
+        /* copy of the flag indicating whether rx_csum is to be used */
+        u32 rx_csum:1,
+            rx_hwts:1;
 
         int pkts_processed;
         int budget;
@@ -281,8 +305,8 @@ struct vxge_vpath {
         int is_configured;
         int is_open;
         struct vxgedev *vdev;
-        u8 (macaddr)[ETH_ALEN];
-        u8 (macmask)[ETH_ALEN];
+        u8 macaddr[ETH_ALEN];
+        u8 macmask[ETH_ALEN];
 
 #define VXGE_MAX_LEARN_MAC_ADDR_CNT     2048
         /* mac addresses currently programmed into NIC */
@@ -327,7 +351,9 @@ struct vxgedev {
         u16             all_multi_flg;
 
          /* A flag indicating whether rx_csum is to be used or not. */
-        u32     rx_csum;
+        u32     rx_csum:1,
+                rx_hwts:1,
+                titan1:1;
 
         struct vxge_msix_entry *vxge_entries;
         struct msix_entry *entries;
@@ -369,6 +395,7 @@ struct vxgedev {
         u32             level_err;
         u32             level_trace;
         char            fw_version[VXGE_HW_FW_STRLEN];
+        struct work_struct reset_task;
 };
 
 struct vxge_rx_priv {
@@ -387,8 +414,6 @@ struct vxge_tx_priv {
         static int p = val; \
         module_param(p, int, 0)
 
-#define vxge_os_bug(fmt...)             { printk(fmt); BUG(); }
-
 #define vxge_os_timer(timer, handle, arg, exp) do { \
                 init_timer(&timer); \
                 timer.function = handle; \
@@ -396,7 +421,10 @@ struct vxge_tx_priv {
                 mod_timer(&timer, (jiffies + exp)); \
         } while (0);
 
-extern void vxge_initialize_ethtool_ops(struct net_device *ndev);
+void vxge_initialize_ethtool_ops(struct net_device *ndev);
+enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev);
+int vxge_fw_upgrade(struct vxgedev *vdev, char *fw_name, int override);
+
 /**
  * #define VXGE_DEBUG_INIT: debug for initialization functions
  * #define VXGE_DEBUG_TX         : debug transmit related functions
diff --git a/drivers/net/vxge/vxge-reg.h b/drivers/net/vxge/vxge-reg.h
index 3dd5c9615ef9..3e658b175947 100644
--- a/drivers/net/vxge/vxge-reg.h
+++ b/drivers/net/vxge/vxge-reg.h
@@ -49,6 +49,33 @@
 #define VXGE_HW_TITAN_VPMGMT_REG_SPACES                 17
 #define VXGE_HW_TITAN_VPATH_REG_SPACES                  17
 
+#define VXGE_HW_FW_API_GET_EPROM_REV                    31
+
+#define VXGE_EPROM_IMG_MAJOR(val)               (u32) vxge_bVALn(val, 48, 4)
+#define VXGE_EPROM_IMG_MINOR(val)               (u32) vxge_bVALn(val, 52, 4)
+#define VXGE_EPROM_IMG_FIX(val)                 (u32) vxge_bVALn(val, 56, 4)
+#define VXGE_EPROM_IMG_BUILD(val)               (u32) vxge_bVALn(val, 60, 4)
+
+#define VXGE_HW_GET_EPROM_IMAGE_INDEX(val)              vxge_bVALn(val, 16, 8)
+#define VXGE_HW_GET_EPROM_IMAGE_VALID(val)              vxge_bVALn(val, 31, 1)
+#define VXGE_HW_GET_EPROM_IMAGE_TYPE(val)               vxge_bVALn(val, 40, 8)
+#define VXGE_HW_GET_EPROM_IMAGE_REV(val)                vxge_bVALn(val, 48, 16)
+#define VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(val)   vxge_vBIT(val, 16, 8)
+
+#define VXGE_HW_FW_API_GET_FUNC_MODE                    29
+#define VXGE_HW_GET_FUNC_MODE_VAL(val)                  (val & 0xFF)
+
+#define VXGE_HW_FW_UPGRADE_MEMO                         13
+#define VXGE_HW_FW_UPGRADE_ACTION                       16
+#define VXGE_HW_FW_UPGRADE_OFFSET_START                 2
+#define VXGE_HW_FW_UPGRADE_OFFSET_SEND                  3
+#define VXGE_HW_FW_UPGRADE_OFFSET_COMMIT                4
+#define VXGE_HW_FW_UPGRADE_OFFSET_READ                  5
+
+#define VXGE_HW_FW_UPGRADE_BLK_SIZE                     16
+#define VXGE_HW_UPGRADE_GET_RET_ERR_CODE(val)           (val & 0xff)
+#define VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(val)           ((val >> 8) & 0xff)
+
 #define VXGE_HW_ASIC_MODE_RESERVED                              0
 #define VXGE_HW_ASIC_MODE_NO_IOV                                1
 #define VXGE_HW_ASIC_MODE_SR_IOV                                2
@@ -165,13 +192,13 @@
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_ETYPE             2
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_PN                3
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG       5
-#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT  6
+#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT          6
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_JHASH_CFG     7
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK          8
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY           9
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_QOS               10
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DS                11
-#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT 12
+#define VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT         12
 #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO           13
 
 #define VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(bits) \
@@ -437,6 +464,7 @@
 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(bits) \
                                                         vxge_bVALn(bits, 48, 16)
 #define VXGE_HW_RTS_ACCESS_STEER_DATA1_FLASH_VER_BUILD vxge_vBIT(val, 48, 16)
+#define VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(bits) vxge_bVALn(bits, 0, 8)
 
 #define VXGE_HW_SRPCIM_TO_VPATH_ALARM_REG_GET_PPIF_SRPCIM_TO_VPATH_ALARM(bits)\
                                                         vxge_bVALn(bits, 0, 18)
@@ -3998,6 +4026,7 @@ struct vxge_hw_vpath_reg {
 #define VXGE_HW_PRC_CFG6_L4_CPC_TRSFR_CODE_EN   vxge_mBIT(9)
 #define VXGE_HW_PRC_CFG6_RXD_CRXDT(val) vxge_vBIT(val, 23, 9)
 #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) vxge_vBIT(val, 36, 9)
+#define VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val)      vxge_bVALn(val, 36, 9)
 /*0x00a78*/     u64     prc_cfg7;
 #define VXGE_HW_PRC_CFG7_SCATTER_MODE(val) vxge_vBIT(val, 6, 2)
 #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN  vxge_mBIT(11)
diff --git a/drivers/net/vxge/vxge-traffic.c b/drivers/net/vxge/vxge-traffic.c
index 4bdb611a6842..4c10d6c4075f 100644
--- a/drivers/net/vxge/vxge-traffic.c
+++ b/drivers/net/vxge/vxge-traffic.c
@@ -17,13 +17,6 @@
 #include "vxge-config.h"
 #include "vxge-main.h"
 
-static enum vxge_hw_status
-__vxge_hw_device_handle_error(struct __vxge_hw_device *hldev,
-                              u32 vp_id, enum vxge_hw_event type);
-static enum vxge_hw_status
-__vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath,
-                              u32 skip_alarms);
-
 /*
  * vxge_hw_vpath_intr_enable - Enable vpath interrupts.
  * @vp: Virtual Path handle.
@@ -419,6 +412,384 @@ void vxge_hw_device_flush_io(struct __vxge_hw_device *hldev)
 }
 
 /**
+ * __vxge_hw_device_handle_error - Handle error
+ * @hldev: HW device
+ * @vp_id: Vpath Id
+ * @type: Error type. Please see enum vxge_hw_event{}
+ *
+ * Handle error.
+ */
+static enum vxge_hw_status
+__vxge_hw_device_handle_error(struct __vxge_hw_device *hldev, u32 vp_id,
+                              enum vxge_hw_event type)
+{
+        switch (type) {
+        case VXGE_HW_EVENT_UNKNOWN:
+                break;
+        case VXGE_HW_EVENT_RESET_START:
+        case VXGE_HW_EVENT_RESET_COMPLETE:
+        case VXGE_HW_EVENT_LINK_DOWN:
+        case VXGE_HW_EVENT_LINK_UP:
+                goto out;
+        case VXGE_HW_EVENT_ALARM_CLEARED:
+                goto out;
+        case VXGE_HW_EVENT_ECCERR:
+        case VXGE_HW_EVENT_MRPCIM_ECCERR:
+                goto out;
+        case VXGE_HW_EVENT_FIFO_ERR:
+        case VXGE_HW_EVENT_VPATH_ERR:
+        case VXGE_HW_EVENT_CRITICAL_ERR:
+        case VXGE_HW_EVENT_SERR:
+                break;
+        case VXGE_HW_EVENT_SRPCIM_SERR:
+        case VXGE_HW_EVENT_MRPCIM_SERR:
+                goto out;
+        case VXGE_HW_EVENT_SLOT_FREEZE:
+                break;
+        default:
+                vxge_assert(0);
+                goto out;
+        }
+
+        /* notify driver */
+        if (hldev->uld_callbacks.crit_err)
+                hldev->uld_callbacks.crit_err(
+                        (struct __vxge_hw_device *)hldev,
+                        type, vp_id);
+out:
+
+        return VXGE_HW_OK;
+}
+
+/*
+ * __vxge_hw_device_handle_link_down_ind
+ * @hldev: HW device handle.
+ *
+ * Link down indication handler. The function is invoked by HW when
+ * Titan indicates that the link is down.
+ */
+static enum vxge_hw_status
+__vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev)
+{
+        /*
+         * If the previous link state is not down, return.
+         */
+        if (hldev->link_state == VXGE_HW_LINK_DOWN)
+                goto exit;
+
+        hldev->link_state = VXGE_HW_LINK_DOWN;
+
+        /* notify driver */
+        if (hldev->uld_callbacks.link_down)
+                hldev->uld_callbacks.link_down(hldev);
+exit:
+        return VXGE_HW_OK;
+}
+
+/*
+ * __vxge_hw_device_handle_link_up_ind
+ * @hldev: HW device handle.
+ *
+ * Link up indication handler. The function is invoked by HW when
+ * Titan indicates that the link is up for programmable amount of time.
+ */
+static enum vxge_hw_status
+__vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev)
+{
+        /*
+         * If the previous link state is not down, return.
+         */
+        if (hldev->link_state == VXGE_HW_LINK_UP)
+                goto exit;
+
+        hldev->link_state = VXGE_HW_LINK_UP;
+
+        /* notify driver */
+        if (hldev->uld_callbacks.link_up)
+                hldev->uld_callbacks.link_up(hldev);
+exit:
+        return VXGE_HW_OK;
+}
+
+/*
+ * __vxge_hw_vpath_alarm_process - Process Alarms.
+ * @vpath: Virtual Path.
+ * @skip_alarms: Do not clear the alarms
+ *
+ * Process vpath alarms.
+ *
+ */
+static enum vxge_hw_status
+__vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath,
+                              u32 skip_alarms)
+{
+        u64 val64;
+        u64 alarm_status;
+        u64 pic_status;
+        struct __vxge_hw_device *hldev = NULL;
+        enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN;
+        u64 mask64;
+        struct vxge_hw_vpath_stats_sw_info *sw_stats;
+        struct vxge_hw_vpath_reg __iomem *vp_reg;
+
+        if (vpath == NULL) {
+                alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
+                        alarm_event);
+                goto out2;
+        }
+
+        hldev = vpath->hldev;
+        vp_reg = vpath->vp_reg;
+        alarm_status = readq(&vp_reg->vpath_general_int_status);
+
+        if (alarm_status == VXGE_HW_ALL_FOXES) {
+                alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE,
+                        alarm_event);
+                goto out;
+        }
+
+        sw_stats = vpath->sw_stats;
+
+        if (alarm_status & ~(
+                VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
+                VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
+                VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
+                VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
+                sw_stats->error_stats.unknown_alarms++;
+
+                alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
+                        alarm_event);
+                goto out;
+        }
+
+        if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
+
+                val64 = readq(&vp_reg->xgmac_vp_int_status);
+
+                if (val64 &
+                VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
+
+                        val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
+
+                        if (((val64 &
+                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
+                             (!(val64 &
+                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
+                            ((val64 &
+                             VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) &&
+                             (!(val64 &
+                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
+                                     ))) {
+                                sw_stats->error_stats.network_sustained_fault++;
+
+                                writeq(
+                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
+                                        &vp_reg->asic_ntwk_vp_err_mask);
+
+                                __vxge_hw_device_handle_link_down_ind(hldev);
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_LINK_DOWN, alarm_event);
+                        }
+
+                        if (((val64 &
+                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
+                             (!(val64 &
+                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
+                            ((val64 &
+                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) &&
+                             (!(val64 &
+                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
+                                     ))) {
+
+                                sw_stats->error_stats.network_sustained_ok++;
+
+                                writeq(
+                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
+                                        &vp_reg->asic_ntwk_vp_err_mask);
+
+                                __vxge_hw_device_handle_link_up_ind(hldev);
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_LINK_UP, alarm_event);
+                        }
+
+                        writeq(VXGE_HW_INTR_MASK_ALL,
+                                &vp_reg->asic_ntwk_vp_err_reg);
+
+                        alarm_event = VXGE_HW_SET_LEVEL(
+                                VXGE_HW_EVENT_ALARM_CLEARED, alarm_event);
+
+                        if (skip_alarms)
+                                return VXGE_HW_OK;
+                }
+        }
+
+        if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) {
+
+                pic_status = readq(&vp_reg->vpath_ppif_int_status);
+
+                if (pic_status &
+                    VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) {
+
+                        val64 = readq(&vp_reg->general_errors_reg);
+                        mask64 = readq(&vp_reg->general_errors_mask);
+
+                        if ((val64 &
+                                VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) &
+                                ~mask64) {
+                                sw_stats->error_stats.ini_serr_det++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_SERR, alarm_event);
+                        }
+
+                        if ((val64 &
+                            VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) &
+                                ~mask64) {
+                                sw_stats->error_stats.dblgen_fifo0_overflow++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_FIFO_ERR, alarm_event);
+                        }
+
+                        if ((val64 &
+                            VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) &
+                                ~mask64)
+                                sw_stats->error_stats.statsb_pif_chain_error++;
+
+                        if ((val64 &
+                           VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) &
+                                ~mask64)
+                                sw_stats->error_stats.statsb_drop_timeout++;
+
+                        if ((val64 &
+                                VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) &
+                                ~mask64)
+                                sw_stats->error_stats.target_illegal_access++;
+
+                        if (!skip_alarms) {
+                                writeq(VXGE_HW_INTR_MASK_ALL,
+                                        &vp_reg->general_errors_reg);
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_ALARM_CLEARED,
+                                        alarm_event);
+                        }
+                }
+
+                if (pic_status &
+                    VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) {
+
+                        val64 = readq(&vp_reg->kdfcctl_errors_reg);
+                        mask64 = readq(&vp_reg->kdfcctl_errors_mask);
+
+                        if ((val64 &
+                            VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) &
+                                ~mask64) {
+                                sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_FIFO_ERR,
+                                        alarm_event);
+                        }
+
+                        if ((val64 &
+                            VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) &
+                                ~mask64) {
+                                sw_stats->error_stats.kdfcctl_fifo0_poison++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_FIFO_ERR,
+                                        alarm_event);
+                        }
+
+                        if ((val64 &
+                            VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) &
+                                ~mask64) {
+                                sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_FIFO_ERR,
+                                        alarm_event);
+                        }
+
+                        if (!skip_alarms) {
+                                writeq(VXGE_HW_INTR_MASK_ALL,
+                                        &vp_reg->kdfcctl_errors_reg);
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_ALARM_CLEARED,
+                                        alarm_event);
+                        }
+                }
+
+        }
+
+        if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
+
+                val64 = readq(&vp_reg->wrdma_alarm_status);
+
+                if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
+
+                        val64 = readq(&vp_reg->prc_alarm_reg);
+                        mask64 = readq(&vp_reg->prc_alarm_mask);
+
+                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)&
+                                ~mask64)
+                                sw_stats->error_stats.prc_ring_bumps++;
+
+                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) &
+                                ~mask64) {
+                                sw_stats->error_stats.prc_rxdcm_sc_err++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_VPATH_ERR,
+                                        alarm_event);
+                        }
+
+                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT)
+                                & ~mask64) {
+                                sw_stats->error_stats.prc_rxdcm_sc_abort++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                                VXGE_HW_EVENT_VPATH_ERR,
+                                                alarm_event);
+                        }
+
+                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR)
+                                 & ~mask64) {
+                                sw_stats->error_stats.prc_quanta_size_err++;
+
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                        VXGE_HW_EVENT_VPATH_ERR,
+                                        alarm_event);
+                        }
+
+                        if (!skip_alarms) {
+                                writeq(VXGE_HW_INTR_MASK_ALL,
+                                        &vp_reg->prc_alarm_reg);
+                                alarm_event = VXGE_HW_SET_LEVEL(
+                                                VXGE_HW_EVENT_ALARM_CLEARED,
+                                                alarm_event);
+                        }
+                }
+        }
+out:
+        hldev->stats.sw_dev_err_stats.vpath_alarms++;
+out2:
+        if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) ||
+                (alarm_event == VXGE_HW_EVENT_UNKNOWN))
+                return VXGE_HW_OK;
+
+        __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event);
+
+        if (alarm_event == VXGE_HW_EVENT_SERR)
+                return VXGE_HW_ERR_CRITICAL;
+
+        return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ?
+                VXGE_HW_ERR_SLOT_FREEZE :
+                (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO :
+                VXGE_HW_ERR_VPATH;
+}
+
+/**
  * vxge_hw_device_begin_irq - Begin IRQ processing.
  * @hldev: HW device handle.
  * @skip_alarms: Do not clear the alarms
@@ -513,108 +884,6 @@ exit:
         return ret;
 }
 
-/*
- * __vxge_hw_device_handle_link_up_ind
- * @hldev: HW device handle.
- *
- * Link up indication handler. The function is invoked by HW when
- * Titan indicates that the link is up for programmable amount of time.
- */
-static enum vxge_hw_status
-__vxge_hw_device_handle_link_up_ind(struct __vxge_hw_device *hldev)
-{
-        /*
-         * If the previous link state is not down, return.
-         */
-        if (hldev->link_state == VXGE_HW_LINK_UP)
-                goto exit;
-
-        hldev->link_state = VXGE_HW_LINK_UP;
-
-        /* notify driver */
-        if (hldev->uld_callbacks.link_up)
-                hldev->uld_callbacks.link_up(hldev);
-exit:
-        return VXGE_HW_OK;
-}
-
-/*
- * __vxge_hw_device_handle_link_down_ind
- * @hldev: HW device handle.
- *
- * Link down indication handler. The function is invoked by HW when
- * Titan indicates that the link is down.
- */
-static enum vxge_hw_status
-__vxge_hw_device_handle_link_down_ind(struct __vxge_hw_device *hldev)
-{
-        /*
-         * If the previous link state is not down, return.
-         */
-        if (hldev->link_state == VXGE_HW_LINK_DOWN)
-                goto exit;
-
-        hldev->link_state = VXGE_HW_LINK_DOWN;
-
-        /* notify driver */
-        if (hldev->uld_callbacks.link_down)
-                hldev->uld_callbacks.link_down(hldev);
-exit:
-        return VXGE_HW_OK;
-}
-
-/**
- * __vxge_hw_device_handle_error - Handle error
- * @hldev: HW device
- * @vp_id: Vpath Id
- * @type: Error type. Please see enum vxge_hw_event{}
- *
- * Handle error.
- */
-static enum vxge_hw_status
-__vxge_hw_device_handle_error(
-                struct __vxge_hw_device *hldev,
-                u32 vp_id,
-                enum vxge_hw_event type)
-{
-        switch (type) {
-        case VXGE_HW_EVENT_UNKNOWN:
-                break;
-        case VXGE_HW_EVENT_RESET_START:
-        case VXGE_HW_EVENT_RESET_COMPLETE:
-        case VXGE_HW_EVENT_LINK_DOWN:
-        case VXGE_HW_EVENT_LINK_UP:
-                goto out;
-        case VXGE_HW_EVENT_ALARM_CLEARED:
-                goto out;
-        case VXGE_HW_EVENT_ECCERR:
-        case VXGE_HW_EVENT_MRPCIM_ECCERR:
-                goto out;
-        case VXGE_HW_EVENT_FIFO_ERR:
-        case VXGE_HW_EVENT_VPATH_ERR:
-        case VXGE_HW_EVENT_CRITICAL_ERR:
-        case VXGE_HW_EVENT_SERR:
-                break;
-        case VXGE_HW_EVENT_SRPCIM_SERR:
-        case VXGE_HW_EVENT_MRPCIM_SERR:
-                goto out;
-        case VXGE_HW_EVENT_SLOT_FREEZE:
-                break;
-        default:
-                vxge_assert(0);
-                goto out;
-        }
-
-        /* notify driver */
-        if (hldev->uld_callbacks.crit_err)
-                hldev->uld_callbacks.crit_err(
-                        (struct __vxge_hw_device *)hldev,
-                        type, vp_id);
-out:
-
-        return VXGE_HW_OK;
-}
-
 /**
  * vxge_hw_device_clear_tx_rx - Acknowledge (that is, clear) the
  * condition that has caused the Tx and RX interrupt.
@@ -699,8 +968,8 @@ _alloc_after_swap:
  * Posts a dtr to work array.
  *
  */
-static void vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel,
-                                     void *dtrh)
+static void
+vxge_hw_channel_dtr_post(struct __vxge_hw_channel *channel, void *dtrh)
 {
         vxge_assert(channel->work_arr[channel->post_index] == NULL);
 
@@ -911,10 +1180,6 @@ void vxge_hw_ring_rxd_post(struct __vxge_hw_ring *ring, void *rxdh)
  */
 void vxge_hw_ring_rxd_post_post_wmb(struct __vxge_hw_ring *ring, void *rxdh)
 {
-        struct __vxge_hw_channel *channel;
-
-        channel = &ring->channel;
-
         wmb();
         vxge_hw_ring_rxd_post_post(ring, rxdh);
 }
@@ -975,7 +1240,7 @@ enum vxge_hw_status vxge_hw_ring_rxd_next_completed(
         *t_code = (u8)VXGE_HW_RING_RXD_T_CODE_GET(control_0);
 
         /* check whether it is not the end */
-        if (!own || ((*t_code == VXGE_HW_RING_T_CODE_FRM_DROP) && own)) {
+        if (!own || *t_code == VXGE_HW_RING_T_CODE_FRM_DROP) {
 
                 vxge_assert(((struct vxge_hw_ring_rxd_1 *)rxdp)->host_control !=
                                 0);
@@ -1868,284 +2133,6 @@ exit:
 }
 
 /*
- * __vxge_hw_vpath_alarm_process - Process Alarms.
- * @vpath: Virtual Path.
- * @skip_alarms: Do not clear the alarms
- *
- * Process vpath alarms.
- *
- */
-static enum vxge_hw_status
-__vxge_hw_vpath_alarm_process(struct __vxge_hw_virtualpath *vpath,
-                              u32 skip_alarms)
-{
-        u64 val64;
-        u64 alarm_status;
-        u64 pic_status;
-        struct __vxge_hw_device *hldev = NULL;
-        enum vxge_hw_event alarm_event = VXGE_HW_EVENT_UNKNOWN;
-        u64 mask64;
-        struct vxge_hw_vpath_stats_sw_info *sw_stats;
-        struct vxge_hw_vpath_reg __iomem *vp_reg;
-
-        if (vpath == NULL) {
-                alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
-                        alarm_event);
-                goto out2;
-        }
-
-        hldev = vpath->hldev;
-        vp_reg = vpath->vp_reg;
-        alarm_status = readq(&vp_reg->vpath_general_int_status);
-
-        if (alarm_status == VXGE_HW_ALL_FOXES) {
-                alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_SLOT_FREEZE,
-                        alarm_event);
-                goto out;
-        }
-
-        sw_stats = vpath->sw_stats;
-
-        if (alarm_status & ~(
-                VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT |
-                VXGE_HW_VPATH_GENERAL_INT_STATUS_PCI_INT |
-                VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT |
-                VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT)) {
-                sw_stats->error_stats.unknown_alarms++;
-
-                alarm_event = VXGE_HW_SET_LEVEL(VXGE_HW_EVENT_UNKNOWN,
-                        alarm_event);
-                goto out;
-        }
-
-        if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_XMAC_INT) {
-
-                val64 = readq(&vp_reg->xgmac_vp_int_status);
-
-                if (val64 &
-                VXGE_HW_XGMAC_VP_INT_STATUS_ASIC_NTWK_VP_ERR_ASIC_NTWK_VP_INT) {
-
-                        val64 = readq(&vp_reg->asic_ntwk_vp_err_reg);
-
-                        if (((val64 &
-                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT) &&
-                             (!(val64 &
-                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK))) ||
-                            ((val64 &
-                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR) &&
-                             (!(val64 &
-                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR)
-                                     ))) {
-                                sw_stats->error_stats.network_sustained_fault++;
-
-                                writeq(
-                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT,
-                                        &vp_reg->asic_ntwk_vp_err_mask);
-
-                                __vxge_hw_device_handle_link_down_ind(hldev);
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_LINK_DOWN, alarm_event);
-                        }
-
-                        if (((val64 &
-                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK) &&
-                             (!(val64 &
-                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT))) ||
-                            ((val64 &
-                              VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK_OCCURR) &&
-                             (!(val64 &
-                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_FLT_OCCURR)
-                                     ))) {
-
-                                sw_stats->error_stats.network_sustained_ok++;
-
-                                writeq(
-                                VXGE_HW_ASIC_NW_VP_ERR_REG_XMACJ_STN_OK,
-                                        &vp_reg->asic_ntwk_vp_err_mask);
-
-                                __vxge_hw_device_handle_link_up_ind(hldev);
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_LINK_UP, alarm_event);
-                        }
-
-                        writeq(VXGE_HW_INTR_MASK_ALL,
-                                &vp_reg->asic_ntwk_vp_err_reg);
-
-                        alarm_event = VXGE_HW_SET_LEVEL(
-                                VXGE_HW_EVENT_ALARM_CLEARED, alarm_event);
-
-                        if (skip_alarms)
-                                return VXGE_HW_OK;
-                }
-        }
-
-        if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_PIC_INT) {
-
-                pic_status = readq(&vp_reg->vpath_ppif_int_status);
-
-                if (pic_status &
-                    VXGE_HW_VPATH_PPIF_INT_STATUS_GENERAL_ERRORS_GENERAL_INT) {
-
-                        val64 = readq(&vp_reg->general_errors_reg);
-                        mask64 = readq(&vp_reg->general_errors_mask);
-
-                        if ((val64 &
-                                VXGE_HW_GENERAL_ERRORS_REG_INI_SERR_DET) &
-                                ~mask64) {
-                                sw_stats->error_stats.ini_serr_det++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_SERR, alarm_event);
-                        }
-
-                        if ((val64 &
-                            VXGE_HW_GENERAL_ERRORS_REG_DBLGEN_FIFO0_OVRFLOW) &
-                                ~mask64) {
-                                sw_stats->error_stats.dblgen_fifo0_overflow++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_FIFO_ERR, alarm_event);
-                        }
-
-                        if ((val64 &
-                            VXGE_HW_GENERAL_ERRORS_REG_STATSB_PIF_CHAIN_ERR) &
-                                ~mask64)
-                                sw_stats->error_stats.statsb_pif_chain_error++;
-
-                        if ((val64 &
-                           VXGE_HW_GENERAL_ERRORS_REG_STATSB_DROP_TIMEOUT_REQ) &
-                                ~mask64)
-                                sw_stats->error_stats.statsb_drop_timeout++;
-
-                        if ((val64 &
-                                VXGE_HW_GENERAL_ERRORS_REG_TGT_ILLEGAL_ACCESS) &
-                                ~mask64)
-                                sw_stats->error_stats.target_illegal_access++;
-
-                        if (!skip_alarms) {
-                                writeq(VXGE_HW_INTR_MASK_ALL,
-                                        &vp_reg->general_errors_reg);
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_ALARM_CLEARED,
-                                        alarm_event);
-                        }
-                }
-
-                if (pic_status &
-                    VXGE_HW_VPATH_PPIF_INT_STATUS_KDFCCTL_ERRORS_KDFCCTL_INT) {
-
-                        val64 = readq(&vp_reg->kdfcctl_errors_reg);
-                        mask64 = readq(&vp_reg->kdfcctl_errors_mask);
-
-                        if ((val64 &
-                            VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_OVRWR) &
-                                ~mask64) {
-                                sw_stats->error_stats.kdfcctl_fifo0_overwrite++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_FIFO_ERR,
-                                        alarm_event);
-                        }
-
-                        if ((val64 &
-                            VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_POISON) &
-                                ~mask64) {
-                                sw_stats->error_stats.kdfcctl_fifo0_poison++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_FIFO_ERR,
-                                        alarm_event);
-                        }
-
-                        if ((val64 &
-                            VXGE_HW_KDFCCTL_ERRORS_REG_KDFCCTL_FIFO0_DMA_ERR) &
-                                ~mask64) {
-                                sw_stats->error_stats.kdfcctl_fifo0_dma_error++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_FIFO_ERR,
-                                        alarm_event);
-                        }
-
-                        if (!skip_alarms) {
-                                writeq(VXGE_HW_INTR_MASK_ALL,
-                                        &vp_reg->kdfcctl_errors_reg);
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_ALARM_CLEARED,
-                                        alarm_event);
-                        }
-                }
-
-        }
-
-        if (alarm_status & VXGE_HW_VPATH_GENERAL_INT_STATUS_WRDMA_INT) {
-
-                val64 = readq(&vp_reg->wrdma_alarm_status);
-
-                if (val64 & VXGE_HW_WRDMA_ALARM_STATUS_PRC_ALARM_PRC_INT) {
-
-                        val64 = readq(&vp_reg->prc_alarm_reg);
-                        mask64 = readq(&vp_reg->prc_alarm_mask);
-
-                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RING_BUMP)&
-                                ~mask64)
-                                sw_stats->error_stats.prc_ring_bumps++;
-
-                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ERR) &
-                                ~mask64) {
-                                sw_stats->error_stats.prc_rxdcm_sc_err++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_VPATH_ERR,
-                                        alarm_event);
-                        }
-
-                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_RXDCM_SC_ABORT)
-                                & ~mask64) {
-                                sw_stats->error_stats.prc_rxdcm_sc_abort++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                                VXGE_HW_EVENT_VPATH_ERR,
-                                                alarm_event);
-                        }
-
-                        if ((val64 & VXGE_HW_PRC_ALARM_REG_PRC_QUANTA_SIZE_ERR)
-                                 & ~mask64) {
-                                sw_stats->error_stats.prc_quanta_size_err++;
-
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                        VXGE_HW_EVENT_VPATH_ERR,
-                                        alarm_event);
-                        }
-
-                        if (!skip_alarms) {
-                                writeq(VXGE_HW_INTR_MASK_ALL,
-                                        &vp_reg->prc_alarm_reg);
-                                alarm_event = VXGE_HW_SET_LEVEL(
-                                                VXGE_HW_EVENT_ALARM_CLEARED,
-                                                alarm_event);
-                        }
-                }
-        }
-out:
-        hldev->stats.sw_dev_err_stats.vpath_alarms++;
-out2:
-        if ((alarm_event == VXGE_HW_EVENT_ALARM_CLEARED) ||
-                (alarm_event == VXGE_HW_EVENT_UNKNOWN))
-                return VXGE_HW_OK;
-
-        __vxge_hw_device_handle_error(hldev, vpath->vp_id, alarm_event);
-
-        if (alarm_event == VXGE_HW_EVENT_SERR)
-                return VXGE_HW_ERR_CRITICAL;
-
-        return (alarm_event == VXGE_HW_EVENT_SLOT_FREEZE) ?
-                VXGE_HW_ERR_SLOT_FREEZE :
-                (alarm_event == VXGE_HW_EVENT_FIFO_ERR) ? VXGE_HW_ERR_FIFO :
-                VXGE_HW_ERR_VPATH;
-}
-
-/*
  * vxge_hw_vpath_alarm_process - Process Alarms.
  * @vpath: Virtual Path.
  * @skip_alarms: Do not clear the alarms
diff --git a/drivers/net/vxge/vxge-traffic.h b/drivers/net/vxge/vxge-traffic.h
index 654295816a39..d48486d6afa1 100644
--- a/drivers/net/vxge/vxge-traffic.h
+++ b/drivers/net/vxge/vxge-traffic.h
@@ -1904,34 +1904,6 @@ enum vxge_hw_ring_tcode {
         VXGE_HW_RING_T_CODE_MULTI_ERR                   = 0xF
 };
 
-/**
- * enum enum vxge_hw_ring_hash_type - RTH hash types
- * @VXGE_HW_RING_HASH_TYPE_NONE: No Hash
- * @VXGE_HW_RING_HASH_TYPE_TCP_IPV4: TCP IPv4
- * @VXGE_HW_RING_HASH_TYPE_UDP_IPV4: UDP IPv4
- * @VXGE_HW_RING_HASH_TYPE_IPV4: IPv4
- * @VXGE_HW_RING_HASH_TYPE_TCP_IPV6: TCP IPv6
- * @VXGE_HW_RING_HASH_TYPE_UDP_IPV6: UDP IPv6
- * @VXGE_HW_RING_HASH_TYPE_IPV6: IPv6
- * @VXGE_HW_RING_HASH_TYPE_TCP_IPV6_EX: TCP IPv6 extension
- * @VXGE_HW_RING_HASH_TYPE_UDP_IPV6_EX: UDP IPv6 extension
- * @VXGE_HW_RING_HASH_TYPE_IPV6_EX: IPv6 extension
- *
- * RTH hash types
- */
-enum vxge_hw_ring_hash_type {
-        VXGE_HW_RING_HASH_TYPE_NONE                     = 0x0,
-        VXGE_HW_RING_HASH_TYPE_TCP_IPV4         = 0x1,
-        VXGE_HW_RING_HASH_TYPE_UDP_IPV4         = 0x2,
-        VXGE_HW_RING_HASH_TYPE_IPV4                     = 0x3,
-        VXGE_HW_RING_HASH_TYPE_TCP_IPV6         = 0x4,
-        VXGE_HW_RING_HASH_TYPE_UDP_IPV6         = 0x5,
-        VXGE_HW_RING_HASH_TYPE_IPV6                     = 0x6,
-        VXGE_HW_RING_HASH_TYPE_TCP_IPV6_EX      = 0x7,
-        VXGE_HW_RING_HASH_TYPE_UDP_IPV6_EX      = 0x8,
-        VXGE_HW_RING_HASH_TYPE_IPV6_EX          = 0x9
-};
-
 enum vxge_hw_status vxge_hw_ring_rxd_reserve(
         struct __vxge_hw_ring *ring_handle,
         void **rxdh);
@@ -2109,10 +2081,6 @@ struct __vxge_hw_ring_rxd_priv {
 #endif
 };
 
-/* ========================= FIFO PRIVATE API ============================= */
-
-struct vxge_hw_fifo_attr;
-
 struct vxge_hw_mempool_cbs {
         void (*item_func_alloc)(
                         struct vxge_hw_mempool *mempoolh,
@@ -2186,27 +2154,27 @@ enum vxge_hw_vpath_mac_addr_add_mode {
 enum vxge_hw_status
 vxge_hw_vpath_mac_addr_add(
         struct __vxge_hw_vpath_handle *vpath_handle,
-        u8 (macaddr)[ETH_ALEN],
-        u8 (macaddr_mask)[ETH_ALEN],
+        u8 *macaddr,
+        u8 *macaddr_mask,
         enum vxge_hw_vpath_mac_addr_add_mode duplicate_mode);
 
 enum vxge_hw_status
 vxge_hw_vpath_mac_addr_get(
         struct __vxge_hw_vpath_handle *vpath_handle,
-        u8 (macaddr)[ETH_ALEN],
-        u8 (macaddr_mask)[ETH_ALEN]);
+        u8 *macaddr,
+        u8 *macaddr_mask);
 
 enum vxge_hw_status
 vxge_hw_vpath_mac_addr_get_next(
         struct __vxge_hw_vpath_handle *vpath_handle,
-        u8 (macaddr)[ETH_ALEN],
-        u8 (macaddr_mask)[ETH_ALEN]);
+        u8 *macaddr,
+        u8 *macaddr_mask);
 
 enum vxge_hw_status
 vxge_hw_vpath_mac_addr_delete(
         struct __vxge_hw_vpath_handle *vpath_handle,
-        u8 (macaddr)[ETH_ALEN],
-        u8 (macaddr_mask)[ETH_ALEN]);
+        u8 *macaddr,
+        u8 *macaddr_mask);
 
 enum vxge_hw_status
 vxge_hw_vpath_vid_add(
@@ -2313,6 +2281,7 @@ vxge_hw_channel_dtr_free(struct __vxge_hw_channel *channel, void *dtrh);
 
 int
 vxge_hw_channel_dtr_count(struct __vxge_hw_channel *channel);
+
 void
 vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id);
 
diff --git a/drivers/net/vxge/vxge-version.h b/drivers/net/vxge/vxge-version.h
index 53fefe137368..ad2f99b9bcf3 100644
--- a/drivers/net/vxge/vxge-version.h
+++ b/drivers/net/vxge/vxge-version.h
@@ -15,8 +15,35 @@
 #define VXGE_VERSION_H
 
 #define VXGE_VERSION_MAJOR      "2"
-#define VXGE_VERSION_MINOR      "0"
-#define VXGE_VERSION_FIX        "9"
-#define VXGE_VERSION_BUILD      "20840"
+#define VXGE_VERSION_MINOR      "5"
+#define VXGE_VERSION_FIX        "1"
+#define VXGE_VERSION_BUILD      "22082"
 #define VXGE_VERSION_FOR        "k"
+
+#define VXGE_FW_VER(maj, min, bld) (((maj) << 16) + ((min) << 8) + (bld))
+
+#define VXGE_DEAD_FW_VER_MAJOR  1
+#define VXGE_DEAD_FW_VER_MINOR  4
+#define VXGE_DEAD_FW_VER_BUILD  4
+
+#define VXGE_FW_DEAD_VER VXGE_FW_VER(VXGE_DEAD_FW_VER_MAJOR, \
+                                     VXGE_DEAD_FW_VER_MINOR, \
+                                     VXGE_DEAD_FW_VER_BUILD)
+
+#define VXGE_EPROM_FW_VER_MAJOR 1
+#define VXGE_EPROM_FW_VER_MINOR 6
+#define VXGE_EPROM_FW_VER_BUILD 1
+
+#define VXGE_EPROM_FW_VER VXGE_FW_VER(VXGE_EPROM_FW_VER_MAJOR, \
+                                      VXGE_EPROM_FW_VER_MINOR, \
+                                      VXGE_EPROM_FW_VER_BUILD)
+
+#define VXGE_CERT_FW_VER_MAJOR  1
+#define VXGE_CERT_FW_VER_MINOR  8
+#define VXGE_CERT_FW_VER_BUILD  1
+
+#define VXGE_CERT_FW_VER VXGE_FW_VER(VXGE_CERT_FW_VER_MAJOR, \
+                                     VXGE_CERT_FW_VER_MINOR, \
+                                     VXGE_CERT_FW_VER_BUILD)
+
 #endif
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c
index 94ff9b02e28e..4578e5b4b411 100644
--- a/drivers/net/wan/dscc4.c
+++ b/drivers/net/wan/dscc4.c
@@ -1358,7 +1358,7 @@ static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
         return ret;
 }
 
-static int dscc4_match(struct thingie *p, int value)
+static int dscc4_match(const struct thingie *p, int value)
 {
         int i;
 
@@ -1403,7 +1403,7 @@ done:
 static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
                                   struct net_device *dev)
 {
-        struct thingie encoding[] = {
+        static const struct thingie encoding[] = {
                 { ENCODING_NRZ,         0x00000000 },
                 { ENCODING_NRZI,        0x00200000 },
                 { ENCODING_FM_MARK,     0x00400000 },
@@ -1442,7 +1442,7 @@ static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
 static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
                              struct net_device *dev)
 {
-        struct thingie crc[] = {
+        static const struct thingie crc[] = {
                 { PARITY_CRC16_PR0_CCITT,       0x00000010 },
                 { PARITY_CRC16_PR1_CCITT,       0x00000000 },
                 { PARITY_CRC32_PR0_CCITT,       0x00000011 },
diff --git a/drivers/net/wd.c b/drivers/net/wd.c
index f1549fff0edc..8831a3393ecf 100644
--- a/drivers/net/wd.c
+++ b/drivers/net/wd.c
@@ -275,7 +275,7 @@ static int __init wd_probe1(struct net_device *dev, int ioaddr)
         dev->base_addr = ioaddr+WD_NIC_OFFSET;
 
         if (dev->irq < 2) {
-                int irqmap[] = {9,3,5,7,10,11,15,4};
+                static const int irqmap[] = {9, 3, 5, 7, 10, 11, 15, 4};
                 int reg1 = inb(ioaddr+1);
                 int reg4 = inb(ioaddr+4);
                 if (ancient || reg1 == 0xff) {  /* Ack!! No way to read the IRQ! */
diff --git a/drivers/net/wimax/i2400m/driver.c b/drivers/net/wimax/i2400m/driver.c
index bcb483fdc4d9..65bc334ed57b 100644
--- a/drivers/net/wimax/i2400m/driver.c
+++ b/drivers/net/wimax/i2400m/driver.c
@@ -92,54 +92,6 @@ MODULE_PARM_DESC(barkers,
                  "signal; values are appended to a list--setting one value "
                  "as zero cleans the existing list and starts a new one.");
 
-static
-struct i2400m_work *__i2400m_work_setup(
-        struct i2400m *i2400m, void (*fn)(struct work_struct *),
-        gfp_t gfp_flags, const void *pl, size_t pl_size)
-{
-        struct i2400m_work *iw;
-
-        iw = kzalloc(sizeof(*iw) + pl_size, gfp_flags);
-        if (iw == NULL)
-                return NULL;
-        iw->i2400m = i2400m_get(i2400m);
-        iw->pl_size = pl_size;
-        memcpy(iw->pl, pl, pl_size);
-        INIT_WORK(&iw->ws, fn);
-        return iw;
-}
-
-
-/*
- * Schedule i2400m's specific work on the system's queue.
- *
- * Used for a few cases where we really need it; otherwise, identical
- * to i2400m_queue_work().
- *
- * Returns < 0 errno code on error, 1 if ok.
- *
- * If it returns zero, something really bad happened, as it means the
- * works struct was already queued, but we have just allocated it, so
- * it should not happen.
- */
-static int i2400m_schedule_work(struct i2400m *i2400m,
-                         void (*fn)(struct work_struct *), gfp_t gfp_flags,
-                         const void *pl, size_t pl_size)
-{
-        int result;
-        struct i2400m_work *iw;
-
-        result = -ENOMEM;
-        iw = __i2400m_work_setup(i2400m, fn, gfp_flags, pl, pl_size);
-        if (iw != NULL) {
-                result = schedule_work(&iw->ws);
-                if (WARN_ON(result == 0))
-                        result = -ENXIO;
-        }
-        return result;
-}
-
-
 /*
  * WiMAX stack operation: relay a message from user space
  *
@@ -648,17 +600,11 @@ EXPORT_SYMBOL_GPL(i2400m_post_reset);
 static
 void __i2400m_dev_reset_handle(struct work_struct *ws)
 {
-        int result;
-        struct i2400m_work *iw = container_of(ws, struct i2400m_work, ws);
-        const char *reason;
-        struct i2400m *i2400m = iw->i2400m;
+        struct i2400m *i2400m = container_of(ws, struct i2400m, reset_ws);
+        const char *reason = i2400m->reset_reason;
         struct device *dev = i2400m_dev(i2400m);
         struct i2400m_reset_ctx *ctx = i2400m->reset_ctx;
-
-        if (WARN_ON(iw->pl_size != sizeof(reason)))
-                reason = "SW BUG: reason n/a";
-        else
-                memcpy(&reason, iw->pl, sizeof(reason));
+        int result;
 
         d_fnstart(3, dev, "(ws %p i2400m %p reason %s)\n", ws, i2400m, reason);
 
@@ -733,8 +679,6 @@ void __i2400m_dev_reset_handle(struct work_struct *ws)
                 }
         }
 out:
-        i2400m_put(i2400m);
-        kfree(iw);
         d_fnend(3, dev, "(ws %p i2400m %p reason %s) = void\n",
                 ws, i2400m, reason);
 }
@@ -754,8 +698,8 @@ out:
  */
 int i2400m_dev_reset_handle(struct i2400m *i2400m, const char *reason)
 {
-        return i2400m_schedule_work(i2400m, __i2400m_dev_reset_handle,
-                                    GFP_ATOMIC, &reason, sizeof(reason));
+        i2400m->reset_reason = reason;
+        return schedule_work(&i2400m->reset_ws);
 }
 EXPORT_SYMBOL_GPL(i2400m_dev_reset_handle);
 
@@ -768,14 +712,9 @@ EXPORT_SYMBOL_GPL(i2400m_dev_reset_handle);
 static
 void __i2400m_error_recovery(struct work_struct *ws)
 {
-        struct i2400m_work *iw = container_of(ws, struct i2400m_work, ws);
-        struct i2400m *i2400m = iw->i2400m;
+        struct i2400m *i2400m = container_of(ws, struct i2400m, recovery_ws);
 
         i2400m_reset(i2400m, I2400M_RT_BUS);
-
-        i2400m_put(i2400m);
-        kfree(iw);
-        return;
 }
 
 /*
@@ -805,18 +744,10 @@ void __i2400m_error_recovery(struct work_struct *ws)
  */
 void i2400m_error_recovery(struct i2400m *i2400m)
 {
-        struct device *dev = i2400m_dev(i2400m);
-
-        if (atomic_add_return(1, &i2400m->error_recovery) == 1) {
-                if (i2400m_schedule_work(i2400m, __i2400m_error_recovery,
-                        GFP_ATOMIC, NULL, 0) < 0) {
-                        dev_err(dev, "run out of memory for "
-                                "scheduling an error recovery ?\n");
-                        atomic_dec(&i2400m->error_recovery);
-                }
-        } else
+        if (atomic_add_return(1, &i2400m->error_recovery) == 1)
+                schedule_work(&i2400m->recovery_ws);
+        else
                 atomic_dec(&i2400m->error_recovery);
-        return;
 }
 EXPORT_SYMBOL_GPL(i2400m_error_recovery);
 
@@ -886,6 +817,10 @@ void i2400m_init(struct i2400m *i2400m)
 
         mutex_init(&i2400m->init_mutex);
         /* wake_tx_ws is initialized in i2400m_tx_setup() */
+
+        INIT_WORK(&i2400m->reset_ws, __i2400m_dev_reset_handle);
+        INIT_WORK(&i2400m->recovery_ws, __i2400m_error_recovery);
+
         atomic_set(&i2400m->bus_reset_retries, 0);
 
         i2400m->alive = 0;
@@ -1040,6 +975,9 @@ void i2400m_release(struct i2400m *i2400m)
 
         i2400m_dev_stop(i2400m);
 
+        cancel_work_sync(&i2400m->reset_ws);
+        cancel_work_sync(&i2400m->recovery_ws);
+
         i2400m_debugfs_rm(i2400m);
         sysfs_remove_group(&i2400m->wimax_dev.net_dev->dev.kobj,
                            &i2400m_dev_attr_group);
@@ -1083,8 +1021,6 @@ module_init(i2400m_driver_init);
 static
 void __exit i2400m_driver_exit(void)
 {
-        /* for scheds i2400m_dev_reset_handle() */
-        flush_scheduled_work();
         i2400m_barker_db_exit();
 }
 module_exit(i2400m_driver_exit);
diff --git a/drivers/net/wimax/i2400m/i2400m.h b/drivers/net/wimax/i2400m/i2400m.h
index a2dbc94f6232..030cbfd31704 100644
--- a/drivers/net/wimax/i2400m/i2400m.h
+++ b/drivers/net/wimax/i2400m/i2400m.h
@@ -632,6 +632,11 @@ struct i2400m {
         struct work_struct wake_tx_ws;
         struct sk_buff *wake_tx_skb;
 
+        struct work_struct reset_ws;
+        const char *reset_reason;
+
+        struct work_struct recovery_ws;
+
         struct dentry *debugfs_dentry;
         const char *fw_name;            /* name of the current firmware image */
         unsigned long fw_version;       /* version of the firmware interface */
@@ -896,20 +901,6 @@ struct device *i2400m_dev(struct i2400m *i2400m)
         return i2400m->wimax_dev.net_dev->dev.parent;
 }
 
-/*
- * Helper for scheduling simple work functions
- *
- * This struct can get any kind of payload attached (normally in the
- * form of a struct where you pack the stuff you want to pass to the
- * _work function).
- */
-struct i2400m_work {
-        struct work_struct ws;
-        struct i2400m *i2400m;
-        size_t pl_size;
-        u8 pl[0];
-};
-
 extern int i2400m_msg_check_status(const struct i2400m_l3l4_hdr *,
                                    char *, size_t);
 extern int i2400m_msg_size_check(struct i2400m *,
diff --git a/drivers/net/wimax/i2400m/sdio.c b/drivers/net/wimax/i2400m/sdio.c
index 9bfc26e1bc6b..be428cae28d8 100644
--- a/drivers/net/wimax/i2400m/sdio.c
+++ b/drivers/net/wimax/i2400m/sdio.c
@@ -590,7 +590,6 @@ module_init(i2400ms_driver_init);
 static
 void __exit i2400ms_driver_exit(void)
 {
-        flush_scheduled_work(); /* for the stuff we schedule */
         sdio_unregister_driver(&i2400m_sdio_driver);
 }
 module_exit(i2400ms_driver_exit);
diff --git a/drivers/net/wimax/i2400m/usb.c b/drivers/net/wimax/i2400m/usb.c
index d3365ac85dde..298f2b0b6311 100644
--- a/drivers/net/wimax/i2400m/usb.c
+++ b/drivers/net/wimax/i2400m/usb.c
@@ -514,7 +514,7 @@ int i2400mu_probe(struct usb_interface *iface,
 #ifdef CONFIG_PM
         iface->needs_remote_wakeup = 1;         /* autosuspend (15s delay) */
         device_init_wakeup(dev, 1);
-        usb_dev->autosuspend_delay = 15 * HZ;
+        pm_runtime_set_autosuspend_delay(&usb_dev->dev, 15000);
         usb_enable_autosuspend(usb_dev);
 #endif
 
@@ -780,7 +780,6 @@ module_init(i2400mu_driver_init);
 static
 void __exit i2400mu_driver_exit(void)
 {
-        flush_scheduled_work(); /* for the stuff we schedule from sysfs.c */
         usb_deregister(&i2400mu_driver);
 }
 module_exit(i2400mu_driver_exit);
diff --git a/drivers/net/wireless/Kconfig b/drivers/net/wireless/Kconfig
index 4de4410cd38e..b4338f389394 100644
--- a/drivers/net/wireless/Kconfig
+++ b/drivers/net/wireless/Kconfig
@@ -279,6 +279,7 @@ source "drivers/net/wireless/libertas/Kconfig"
 source "drivers/net/wireless/orinoco/Kconfig"
 source "drivers/net/wireless/p54/Kconfig"
 source "drivers/net/wireless/rt2x00/Kconfig"
+source "drivers/net/wireless/rtlwifi/Kconfig"
 source "drivers/net/wireless/wl1251/Kconfig"
 source "drivers/net/wireless/wl12xx/Kconfig"
 source "drivers/net/wireless/zd1211rw/Kconfig"
diff --git a/drivers/net/wireless/Makefile b/drivers/net/wireless/Makefile
index 06f8ca26c5c1..9760561a27a5 100644
--- a/drivers/net/wireless/Makefile
+++ b/drivers/net/wireless/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_B43LEGACY)		+= b43legacy/
 obj-$(CONFIG_ZD1211RW)          += zd1211rw/
 obj-$(CONFIG_RTL8180)           += rtl818x/
 obj-$(CONFIG_RTL8187)           += rtl818x/
+obj-$(CONFIG_RTL8192CE)         += rtlwifi/
 
 # 16-bit wireless PCMCIA client drivers
 obj-$(CONFIG_PCMCIA_RAYCS)      += ray_cs.o
diff --git a/drivers/net/wireless/airo.c b/drivers/net/wireless/airo.c
index a36e7870b03e..57a79b0475f6 100644
--- a/drivers/net/wireless/airo.c
+++ b/drivers/net/wireless/airo.c
@@ -4652,24 +4652,18 @@ static ssize_t proc_write( struct file *file,
                            size_t len,
                            loff_t *offset )
 {
-        loff_t pos = *offset;
+        ssize_t ret;
         struct proc_data *priv = file->private_data;
 
         if (!priv->wbuffer)
                 return -EINVAL;
 
-        if (pos < 0)
-                return -EINVAL;
-        if (pos >= priv->maxwritelen)
-                return 0;
-        if (len > priv->maxwritelen - pos)
-                len = priv->maxwritelen - pos;
-        if (copy_from_user(priv->wbuffer + pos, buffer, len))
-                return -EFAULT;
-        if ( pos + len > priv->writelen )
-                priv->writelen = len + file->f_pos;
-        *offset = pos + len;
-        return len;
+        ret = simple_write_to_buffer(priv->wbuffer, priv->maxwritelen, offset,
+                                        buffer, len);
+        if (ret > 0)
+                priv->writelen = max_t(int, priv->writelen, *offset);
+
+        return ret;
 }
 
 static int proc_status_open(struct inode *inode, struct file *file)
diff --git a/drivers/net/wireless/ath/ar9170/cmd.c b/drivers/net/wireless/ath/ar9170/cmd.c
index 4604de09a8b2..6452c5055a63 100644
--- a/drivers/net/wireless/ath/ar9170/cmd.c
+++ b/drivers/net/wireless/ath/ar9170/cmd.c
@@ -54,7 +54,7 @@ int ar9170_write_mem(struct ar9170 *ar, const __le32 *data, size_t len)
 
 int ar9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
 {
-        __le32 buf[2] = {
+        const __le32 buf[2] = {
                 cpu_to_le32(reg),
                 cpu_to_le32(val),
         };
diff --git a/drivers/net/wireless/ath/ar9170/usb.c b/drivers/net/wireless/ath/ar9170/usb.c
index 5dbb5361fd51..d3be6f9816b5 100644
--- a/drivers/net/wireless/ath/ar9170/usb.c
+++ b/drivers/net/wireless/ath/ar9170/usb.c
@@ -161,8 +161,7 @@ static void ar9170_usb_submit_urb(struct ar9170_usb *aru)
 static void ar9170_usb_tx_urb_complete_frame(struct urb *urb)
 {
         struct sk_buff *skb = urb->context;
-        struct ar9170_usb *aru = (struct ar9170_usb *)
-              usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
+        struct ar9170_usb *aru = usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
 
         if (unlikely(!aru)) {
                 dev_kfree_skb_irq(skb);
@@ -219,8 +218,7 @@ free:
 static void ar9170_usb_rx_completed(struct urb *urb)
 {
         struct sk_buff *skb = urb->context;
-        struct ar9170_usb *aru = (struct ar9170_usb *)
-                usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
+        struct ar9170_usb *aru = usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int err;
 
         if (!aru)
diff --git a/drivers/net/wireless/ath/ath.h b/drivers/net/wireless/ath/ath.h
index 501050c0296f..e43210c8585c 100644
--- a/drivers/net/wireless/ath/ath.h
+++ b/drivers/net/wireless/ath/ath.h
@@ -126,6 +126,7 @@ struct ath_bus_ops {
         void (*read_cachesize)(struct ath_common *common, int *csz);
         bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
         void (*bt_coex_prep)(struct ath_common *common);
+        void (*extn_synch_en)(struct ath_common *common);
 };
 
 struct ath_common {
@@ -162,6 +163,8 @@ struct ath_common {
         struct ath_regulatory regulatory;
         const struct ath_ops *ops;
         const struct ath_bus_ops *bus_ops;
+
+        bool btcoex_enabled;
 };
 
 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
@@ -178,4 +181,112 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry);
 void ath_hw_cycle_counters_update(struct ath_common *common);
 int32_t ath_hw_get_listen_time(struct ath_common *common);
 
+extern __attribute__ ((format (printf, 3, 4))) int
+ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
+
+#define ath_emerg(common, fmt, ...)                             \
+        ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
+#define ath_alert(common, fmt, ...)                             \
+        ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
+#define ath_crit(common, fmt, ...)                              \
+        ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
+#define ath_err(common, fmt, ...)                               \
+        ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
+#define ath_warn(common, fmt, ...)                              \
+        ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
+#define ath_notice(common, fmt, ...)                            \
+        ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
+#define ath_info(common, fmt, ...)                              \
+        ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
+
+/**
+ * enum ath_debug_level - atheros wireless debug level
+ *
+ * @ATH_DBG_RESET: reset processing
+ * @ATH_DBG_QUEUE: hardware queue management
+ * @ATH_DBG_EEPROM: eeprom processing
+ * @ATH_DBG_CALIBRATE: periodic calibration
+ * @ATH_DBG_INTERRUPT: interrupt processing
+ * @ATH_DBG_REGULATORY: regulatory processing
+ * @ATH_DBG_ANI: adaptive noise immunitive processing
+ * @ATH_DBG_XMIT: basic xmit operation
+ * @ATH_DBG_BEACON: beacon handling
+ * @ATH_DBG_CONFIG: configuration of the hardware
+ * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
+ * @ATH_DBG_PS: power save processing
+ * @ATH_DBG_HWTIMER: hardware timer handling
+ * @ATH_DBG_BTCOEX: bluetooth coexistance
+ * @ATH_DBG_BSTUCK: stuck beacons
+ * @ATH_DBG_ANY: enable all debugging
+ *
+ * The debug level is used to control the amount and type of debugging output
+ * we want to see. Each driver has its own method for enabling debugging and
+ * modifying debug level states -- but this is typically done through a
+ * module parameter 'debug' along with a respective 'debug' debugfs file
+ * entry.
+ */
+enum ATH_DEBUG {
+        ATH_DBG_RESET           = 0x00000001,
+        ATH_DBG_QUEUE           = 0x00000002,
+        ATH_DBG_EEPROM          = 0x00000004,
+        ATH_DBG_CALIBRATE       = 0x00000008,
+        ATH_DBG_INTERRUPT       = 0x00000010,
+        ATH_DBG_REGULATORY      = 0x00000020,
+        ATH_DBG_ANI             = 0x00000040,
+        ATH_DBG_XMIT            = 0x00000080,
+        ATH_DBG_BEACON          = 0x00000100,
+        ATH_DBG_CONFIG          = 0x00000200,
+        ATH_DBG_FATAL           = 0x00000400,
+        ATH_DBG_PS              = 0x00000800,
+        ATH_DBG_HWTIMER         = 0x00001000,
+        ATH_DBG_BTCOEX          = 0x00002000,
+        ATH_DBG_WMI             = 0x00004000,
+        ATH_DBG_BSTUCK          = 0x00008000,
+        ATH_DBG_ANY             = 0xffffffff
+};
+
+#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
+
+#ifdef CONFIG_ATH_DEBUG
+
+#define ath_dbg(common, dbg_mask, fmt, ...)                     \
+({                                                              \
+        int rtn;                                                \
+        if ((common)->debug_mask & dbg_mask)                    \
+                rtn = ath_printk(KERN_DEBUG, common, fmt,       \
+                                 ##__VA_ARGS__);                \
+        else                                                    \
+                rtn = 0;                                        \
+                                                                \
+        rtn;                                                    \
+})
+#define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
+#define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
+
+#else
+
+static inline  __attribute__ ((format (printf, 3, 4))) int
+ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
+        const char *fmt, ...)
+{
+        return 0;
+}
+#define ATH_DBG_WARN(foo, arg...) do {} while (0)
+#define ATH_DBG_WARN_ON_ONCE(foo) ({                            \
+        int __ret_warn_once = !!(foo);                          \
+        unlikely(__ret_warn_once);                              \
+})
+
+#endif /* CONFIG_ATH_DEBUG */
+
+/** Returns string describing opmode, or NULL if unknown mode. */
+#ifdef CONFIG_ATH_DEBUG
+const char *ath_opmode_to_string(enum nl80211_iftype opmode);
+#else
+static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
+{
+        return "UNKNOWN";
+}
+#endif
+
 #endif /* ATH_H */
diff --git a/drivers/net/wireless/ath/ath5k/Kconfig b/drivers/net/wireless/ath/ath5k/Kconfig
index eb83b7b4d0e3..e0793319389d 100644
--- a/drivers/net/wireless/ath/ath5k/Kconfig
+++ b/drivers/net/wireless/ath/ath5k/Kconfig
@@ -1,9 +1,12 @@
 config ATH5K
         tristate "Atheros 5xxx wireless cards support"
-        depends on PCI && MAC80211
+        depends on (PCI || ATHEROS_AR231X) && MAC80211
         select MAC80211_LEDS
         select LEDS_CLASS
         select NEW_LEDS
+        select AVERAGE
+        select ATH5K_AHB if (ATHEROS_AR231X && !PCI)
+        select ATH5K_PCI if (!ATHEROS_AR231X && PCI)
         ---help---
           This module adds support for wireless adapters based on
           Atheros 5xxx chipset.
@@ -37,3 +40,16 @@ config ATH5K_DEBUG
 
           modprobe ath5k debug=0x00000400
 
+config ATH5K_AHB
+        bool "Atheros 5xxx AHB bus support"
+        depends on (ATHEROS_AR231X && !PCI)
+        ---help---
+          This adds support for WiSoC type chipsets of the 5xxx Atheros
+          family.
+
+config ATH5K_PCI
+        bool "Atheros 5xxx PCI bus support"
+        depends on (!ATHEROS_AR231X && PCI)
+        ---help---
+          This adds support for PCI type chipsets of the 5xxx Atheros
+          family.
diff --git a/drivers/net/wireless/ath/ath5k/Makefile b/drivers/net/wireless/ath/ath5k/Makefile
index 2242a140e4fe..f60b3899afc4 100644
--- a/drivers/net/wireless/ath/ath5k/Makefile
+++ b/drivers/net/wireless/ath/ath5k/Makefile
@@ -14,5 +14,8 @@ ath5k-y				+= led.o
 ath5k-y                         += rfkill.o
 ath5k-y                         += ani.o
 ath5k-y                         += sysfs.o
+ath5k-y                         += mac80211-ops.o
 ath5k-$(CONFIG_ATH5K_DEBUG)     += debug.o
+ath5k-$(CONFIG_ATH5K_AHB)       += ahb.o
+ath5k-$(CONFIG_ATH5K_PCI)       += pci.o
 obj-$(CONFIG_ATH5K)             += ath5k.o
diff --git a/drivers/net/wireless/ath/ath5k/ahb.c b/drivers/net/wireless/ath/ath5k/ahb.c
new file mode 100644
index 000000000000..707cde149248
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/ahb.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ * Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/platform_device.h>
+#include <ar231x_platform.h>
+#include "ath5k.h"
+#include "debug.h"
+#include "base.h"
+#include "reg.h"
+#include "debug.h"
+
+/* return bus cachesize in 4B word units */
+static void ath5k_ahb_read_cachesize(struct ath_common *common, int *csz)
+{
+        *csz = L1_CACHE_BYTES >> 2;
+}
+
+bool ath5k_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
+{
+        struct ath5k_softc *sc = common->priv;
+        struct platform_device *pdev = to_platform_device(sc->dev);
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        u16 *eeprom, *eeprom_end;
+
+
+
+        bcfg = pdev->dev.platform_data;
+        eeprom = (u16 *) bcfg->radio;
+        eeprom_end = ((void *) bcfg->config) + BOARD_CONFIG_BUFSZ;
+
+        eeprom += off;
+        if (eeprom > eeprom_end)
+                return -EINVAL;
+
+        *data = *eeprom;
+        return 0;
+}
+
+int ath5k_hw_read_srev(struct ath5k_hw *ah)
+{
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct platform_device *pdev = to_platform_device(sc->dev);
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        ah->ah_mac_srev = bcfg->devid;
+        return 0;
+}
+
+static const struct ath_bus_ops ath_ahb_bus_ops = {
+        .ath_bus_type = ATH_AHB,
+        .read_cachesize = ath5k_ahb_read_cachesize,
+        .eeprom_read = ath5k_ahb_eeprom_read,
+};
+
+/*Initialization*/
+static int ath_ahb_probe(struct platform_device *pdev)
+{
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        struct ath5k_softc *sc;
+        struct ieee80211_hw *hw;
+        struct resource *res;
+        void __iomem *mem;
+        int irq;
+        int ret = 0;
+        u32 reg;
+
+        if (!pdev->dev.platform_data) {
+                dev_err(&pdev->dev, "no platform data specified\n");
+                ret = -EINVAL;
+                goto err_out;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no memory resource found\n");
+                ret = -ENXIO;
+                goto err_out;
+        }
+
+        mem = ioremap_nocache(res->start, res->end - res->start + 1);
+        if (mem == NULL) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err_out;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "no IRQ resource found\n");
+                ret = -ENXIO;
+                goto err_out;
+        }
+
+        irq = res->start;
+
+        hw = ieee80211_alloc_hw(sizeof(struct ath5k_softc), &ath5k_hw_ops);
+        if (hw == NULL) {
+                dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
+                ret = -ENOMEM;
+                goto err_out;
+        }
+
+        sc = hw->priv;
+        sc->hw = hw;
+        sc->dev = &pdev->dev;
+        sc->iobase = mem;
+        sc->irq = irq;
+        sc->devid = bcfg->devid;
+
+        if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
+                /* Enable WMAC AHB arbitration */
+                reg = __raw_readl((void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+                reg |= AR5K_AR2315_AHB_ARB_CTL_WLAN;
+                __raw_writel(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+
+                /* Enable global WMAC swapping */
+                reg = __raw_readl((void __iomem *) AR5K_AR2315_BYTESWAP);
+                reg |= AR5K_AR2315_BYTESWAP_WMAC;
+                __raw_writel(reg, (void __iomem *) AR5K_AR2315_BYTESWAP);
+        } else {
+                /* Enable WMAC DMA access (assuming 5312 or 231x*/
+                /* TODO: check other platforms */
+                reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
+                if (to_platform_device(sc->dev)->id == 0)
+                        reg |= AR5K_AR5312_ENABLE_WLAN0;
+                else
+                        reg |= AR5K_AR5312_ENABLE_WLAN1;
+                __raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE);
+        }
+
+        ret = ath5k_init_softc(sc, &ath_ahb_bus_ops);
+        if (ret != 0) {
+                dev_err(&pdev->dev, "failed to attach device, err=%d\n", ret);
+                ret = -ENODEV;
+                goto err_free_hw;
+        }
+
+        platform_set_drvdata(pdev, hw);
+
+        return 0;
+
+ err_free_hw:
+        ieee80211_free_hw(hw);
+        platform_set_drvdata(pdev, NULL);
+ err_out:
+        return ret;
+}
+
+static int ath_ahb_remove(struct platform_device *pdev)
+{
+        struct ar231x_board_config *bcfg = pdev->dev.platform_data;
+        struct ieee80211_hw *hw = platform_get_drvdata(pdev);
+        struct ath5k_softc *sc;
+        u32 reg;
+
+        if (!hw)
+                return 0;
+
+        sc = hw->priv;
+
+        if (bcfg->devid >= AR5K_SREV_AR2315_R6) {
+                /* Disable WMAC AHB arbitration */
+                reg = __raw_readl((void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+                reg &= ~AR5K_AR2315_AHB_ARB_CTL_WLAN;
+                __raw_writel(reg, (void __iomem *) AR5K_AR2315_AHB_ARB_CTL);
+        } else {
+                /*Stop DMA access */
+                reg = __raw_readl((void __iomem *) AR5K_AR5312_ENABLE);
+                if (to_platform_device(sc->dev)->id == 0)
+                        reg &= ~AR5K_AR5312_ENABLE_WLAN0;
+                else
+                        reg &= ~AR5K_AR5312_ENABLE_WLAN1;
+                __raw_writel(reg, (void __iomem *) AR5K_AR5312_ENABLE);
+        }
+
+        ath5k_deinit_softc(sc);
+        platform_set_drvdata(pdev, NULL);
+
+        return 0;
+}
+
+static struct platform_driver ath_ahb_driver = {
+        .probe      = ath_ahb_probe,
+        .remove     = ath_ahb_remove,
+        .driver         = {
+                .name   = "ar231x-wmac",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init
+ath5k_ahb_init(void)
+{
+        return platform_driver_register(&ath_ahb_driver);
+}
+
+static void __exit
+ath5k_ahb_exit(void)
+{
+        platform_driver_unregister(&ath_ahb_driver);
+}
+
+module_init(ath5k_ahb_init);
+module_exit(ath5k_ahb_exit);
diff --git a/drivers/net/wireless/ath/ath5k/ani.c b/drivers/net/wireless/ath/ath5k/ani.c
index f1419198a479..f915f404302d 100644
--- a/drivers/net/wireless/ath/ath5k/ani.c
+++ b/drivers/net/wireless/ath/ath5k/ani.c
@@ -58,20 +58,20 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
 {
         /* TODO:
          * ANI documents suggest the following five levels to use, but the HAL
-         * and ath9k use only use the last two levels, making this
+         * and ath9k use only the last two levels, making this
          * essentially an on/off option. There *may* be a reason for this (???),
          * so i stick with the HAL version for now...
          */
 #if 0
-        const s8 hi[] = { -18, -18, -16, -14, -12 };
-        const s8 lo[] = { -52, -56, -60, -64, -70 };
-        const s8 sz[] = { -34, -41, -48, -55, -62 };
-        const s8 fr[] = { -70, -72, -75, -78, -80 };
+        static const s8 lo[] = { -52, -56, -60, -64, -70 };
+        static const s8 hi[] = { -18, -18, -16, -14, -12 };
+        static const s8 sz[] = { -34, -41, -48, -55, -62 };
+        static const s8 fr[] = { -70, -72, -75, -78, -80 };
 #else
-        const s8 sz[] = { -55, -62 };
-        const s8 lo[] = { -64, -70 };
-        const s8 hi[] = { -14, -12 };
-        const s8 fr[] = { -78, -80 };
+        static const s8 lo[] = { -64, -70 };
+        static const s8 hi[] = { -14, -12 };
+        static const s8 sz[] = { -55, -62 };
+        static const s8 fr[] = { -78, -80 };
 #endif
         if (level < 0 || level >= ARRAY_SIZE(sz)) {
                 ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range",
@@ -102,7 +102,7 @@ ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level)
 void
 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
 {
-        const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
+        static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
 
         if (level < 0 || level >= ARRAY_SIZE(val) ||
             level > ah->ah_sc->ani_state.max_spur_level) {
@@ -127,7 +127,7 @@ ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level)
 void
 ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
 {
-        const int val[] = { 0, 4, 8 };
+        static const int val[] = { 0, 4, 8 };
 
         if (level < 0 || level >= ARRAY_SIZE(val)) {
                 ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level);
@@ -151,12 +151,12 @@ ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level)
 void
 ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
 {
-        const int m1l[] = { 127, 50 };
-        const int m2l[] = { 127, 40 };
-        const int m1[] = { 127, 0x4d };
-        const int m2[] = { 127, 0x40 };
-        const int m2cnt[] = { 31, 16 };
-        const int m2lcnt[] = { 63, 48 };
+        static const int m1l[] = { 127, 50 };
+        static const int m2l[] = { 127, 40 };
+        static const int m1[] = { 127, 0x4d };
+        static const int m2[] = { 127, 0x40 };
+        static const int m2cnt[] = { 31, 16 };
+        static const int m2lcnt[] = { 63, 48 };
 
         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR,
                                 AR5K_PHY_WEAK_OFDM_LOW_THR_M1, m1l[on]);
@@ -192,7 +192,7 @@ ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on)
 void
 ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on)
 {
-        const int val[] = { 8, 6 };
+        static const int val[] = { 8, 6 };
         AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR,
                                 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]);
         ah->ah_sc->ani_state.cck_weak_sig = on;
@@ -216,7 +216,7 @@ static void
 ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
                          bool ofdm_trigger)
 {
-        int rssi = ah->ah_beacon_rssi_avg.avg;
+        int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
 
         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)",
                 ofdm_trigger ? "ODFM" : "CCK");
@@ -301,7 +301,7 @@ ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as,
 static void
 ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as)
 {
-        int rssi = ah->ah_beacon_rssi_avg.avg;
+        int rssi = ewma_read(&ah->ah_beacon_rssi_avg);
 
         ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity");
 
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index 308b79e1ff08..407e39c2b10b 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -25,6 +25,7 @@
 
 #include <linux/io.h>
 #include <linux/types.h>
+#include <linux/average.h>
 #include <net/mac80211.h>
 
 /* RX/TX descriptor hw structs
@@ -153,19 +154,6 @@
                 udelay(1);                                              \
 } while (0)
 
-/* Register dumps are done per operation mode */
-#define AR5K_INI_RFGAIN_5GHZ            0
-#define AR5K_INI_RFGAIN_2GHZ            1
-
-/* TODO: Clean this up */
-#define AR5K_INI_VAL_11A                0
-#define AR5K_INI_VAL_11A_TURBO          1
-#define AR5K_INI_VAL_11B                2
-#define AR5K_INI_VAL_11G                3
-#define AR5K_INI_VAL_11G_TURBO          4
-#define AR5K_INI_VAL_XR                 0
-#define AR5K_INI_VAL_MAX                5
-
 /*
  * Some tuneable values (these should be changeable by the user)
  * TODO: Make use of them and add more options OR use debug/configfs
@@ -221,42 +209,66 @@
 
 /* Initial values */
 #define AR5K_INIT_CYCRSSI_THR1                  2
-#define AR5K_INIT_TX_LATENCY                    502
-#define AR5K_INIT_USEC                          39
-#define AR5K_INIT_USEC_TURBO                    79
-#define AR5K_INIT_USEC_32                       31
-#define AR5K_INIT_SLOT_TIME                     396
-#define AR5K_INIT_SLOT_TIME_TURBO               480
-#define AR5K_INIT_ACK_CTS_TIMEOUT               1024
-#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO         0x08000800
-#define AR5K_INIT_PROG_IFS                      920
-#define AR5K_INIT_PROG_IFS_TURBO                960
-#define AR5K_INIT_EIFS                          3440
-#define AR5K_INIT_EIFS_TURBO                    6880
-#define AR5K_INIT_SIFS                          560
-#define AR5K_INIT_SIFS_TURBO                    480
+
+/* Tx retry limits */
 #define AR5K_INIT_SH_RETRY                      10
 #define AR5K_INIT_LG_RETRY                      AR5K_INIT_SH_RETRY
+/* For station mode */
 #define AR5K_INIT_SSH_RETRY                     32
 #define AR5K_INIT_SLG_RETRY                     AR5K_INIT_SSH_RETRY
 #define AR5K_INIT_TX_RETRY                      10
 
-#define AR5K_INIT_TRANSMIT_LATENCY              (                       \
-        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
-        (AR5K_INIT_USEC)                                                \
-)
-#define AR5K_INIT_TRANSMIT_LATENCY_TURBO        (                       \
-        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
-        (AR5K_INIT_USEC_TURBO)                                          \
-)
-#define AR5K_INIT_PROTO_TIME_CNTRL              (                       \
-        (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) |      \
-        (AR5K_INIT_PROG_IFS)                                            \
-)
-#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO        (                       \
-        (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
-        (AR5K_INIT_PROG_IFS_TURBO)                                      \
-)
+
+/* Slot time */
+#define AR5K_INIT_SLOT_TIME_TURBO               6
+#define AR5K_INIT_SLOT_TIME_DEFAULT             9
+#define AR5K_INIT_SLOT_TIME_HALF_RATE           13
+#define AR5K_INIT_SLOT_TIME_QUARTER_RATE        21
+#define AR5K_INIT_SLOT_TIME_B                   20
+#define AR5K_SLOT_TIME_MAX                      0xffff
+
+/* SIFS */
+#define AR5K_INIT_SIFS_TURBO                    6
+/* XXX: 8 from initvals 10 from standard */
+#define AR5K_INIT_SIFS_DEFAULT_BG               8
+#define AR5K_INIT_SIFS_DEFAULT_A                16
+#define AR5K_INIT_SIFS_HALF_RATE                32
+#define AR5K_INIT_SIFS_QUARTER_RATE             64
+
+/* Used to calculate tx time for non 5/10/40MHz
+ * operation */
+/* It's preamble time + signal time (16 + 4) */
+#define AR5K_INIT_OFDM_PREAMPLE_TIME            20
+/* Preamble time for 40MHz (turbo) operation (min ?) */
+#define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN        14
+#define AR5K_INIT_OFDM_SYMBOL_TIME              4
+#define AR5K_INIT_OFDM_PLCP_BITS                22
+
+/* Rx latency for 5 and 10MHz operation (max ?) */
+#define AR5K_INIT_RX_LAT_MAX                    63
+/* Tx latencies from initvals (5212 only but no problem
+ * because we only tweak them on 5212) */
+#define AR5K_INIT_TX_LAT_A                      54
+#define AR5K_INIT_TX_LAT_BG                     384
+/* Tx latency for 40MHz (turbo) operation (min ?) */
+#define AR5K_INIT_TX_LAT_MIN                    32
+/* Default Tx/Rx latencies (same for 5211)*/
+#define AR5K_INIT_TX_LATENCY_5210               54
+#define AR5K_INIT_RX_LATENCY_5210               29
+
+/* Tx frame to Tx data start delay */
+#define AR5K_INIT_TXF2TXD_START_DEFAULT         14
+#define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ     12
+#define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ      13
+
+/* We need to increase PHY switch and agc settling time
+ * on turbo mode */
+#define AR5K_SWITCH_SETTLING                    5760
+#define AR5K_SWITCH_SETTLING_TURBO              7168
+
+#define AR5K_AGC_SETTLING                       28
+/* 38 on 5210 but shouldn't matter */
+#define AR5K_AGC_SETTLING_TURBO                 37
 
 
 /* GENERIC CHIPSET DEFINITIONS */
@@ -303,12 +315,19 @@ struct ath5k_srev_name {
 #define AR5K_SREV_AR5311B       0x30 /* Spirit */
 #define AR5K_SREV_AR5211        0x40 /* Oahu */
 #define AR5K_SREV_AR5212        0x50 /* Venice */
+#define AR5K_SREV_AR5312_R2     0x52 /* AP31 */
 #define AR5K_SREV_AR5212_V4     0x54 /* ??? */
 #define AR5K_SREV_AR5213        0x55 /* ??? */
+#define AR5K_SREV_AR5312_R7     0x57 /* AP30 */
+#define AR5K_SREV_AR2313_R8     0x58 /* AP43 */
 #define AR5K_SREV_AR5213A       0x59 /* Hainan */
 #define AR5K_SREV_AR2413        0x78 /* Griffin lite */
 #define AR5K_SREV_AR2414        0x70 /* Griffin */
+#define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
+#define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
 #define AR5K_SREV_AR5424        0x90 /* Condor */
+#define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
+#define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
 #define AR5K_SREV_AR5413        0xa4 /* Eagle lite */
 #define AR5K_SREV_AR5414        0xa0 /* Eagle */
 #define AR5K_SREV_AR2415        0xb0 /* Talon */
@@ -404,12 +423,10 @@ struct ath5k_srev_name {
 
 enum ath5k_driver_mode {
         AR5K_MODE_11A           =       0,
-        AR5K_MODE_11A_TURBO     =       1,
-        AR5K_MODE_11B           =       2,
-        AR5K_MODE_11G           =       3,
-        AR5K_MODE_11G_TURBO     =       4,
+        AR5K_MODE_11B           =       1,
+        AR5K_MODE_11G           =       2,
         AR5K_MODE_XR            =       0,
-        AR5K_MODE_MAX           =       5
+        AR5K_MODE_MAX           =       3
 };
 
 enum ath5k_ant_mode {
@@ -423,6 +440,12 @@ enum ath5k_ant_mode {
         AR5K_ANTMODE_MAX,
 };
 
+enum ath5k_bw_mode {
+        AR5K_BWMODE_DEFAULT     = 0,    /* 20MHz, default operation */
+        AR5K_BWMODE_5MHZ        = 1,    /* Quarter rate */
+        AR5K_BWMODE_10MHZ       = 2,    /* Half rate */
+        AR5K_BWMODE_40MHZ       = 3     /* Turbo */
+};
 
 /****************\
   TX DEFINITIONS
@@ -655,7 +678,6 @@ struct ath5k_gain {
 
 /* channel_flags */
 #define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
-#define CHANNEL_TURBO   0x0010  /* Turbo Channel */
 #define CHANNEL_CCK     0x0020  /* CCK channel */
 #define CHANNEL_OFDM    0x0040  /* OFDM channel */
 #define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
@@ -667,16 +689,10 @@ struct ath5k_gain {
 #define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
 #define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
 #define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
-#define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
-#define CHANNEL_108A    CHANNEL_T
-#define CHANNEL_108G    CHANNEL_TG
 #define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
 
-#define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
-                CHANNEL_TURBO)
+#define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ)
 
-#define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
 #define CHANNEL_MODES           CHANNEL_ALL
 
 /*
@@ -1025,7 +1041,6 @@ struct ath5k_hw {
         enum ath5k_int          ah_imr;
 
         struct ieee80211_channel *ah_current_channel;
-        bool                    ah_turbo;
         bool                    ah_calibration;
         bool                    ah_single_chip;
 
@@ -1034,6 +1049,7 @@ struct ath5k_hw {
         u32                     ah_phy;
         u32                     ah_mac_srev;
         u16                     ah_mac_version;
+        u16                     ah_mac_revision;
         u16                     ah_phy_revision;
         u16                     ah_radio_5ghz_revision;
         u16                     ah_radio_2ghz_revision;
@@ -1043,6 +1059,8 @@ struct ath5k_hw {
 
         u32                     ah_limit_tx_retries;
         u8                      ah_coverage_class;
+        bool                    ah_ack_bitrate_high;
+        u8                      ah_bwmode;
 
         /* Antenna Control */
         u32                     ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
@@ -1085,12 +1103,14 @@ struct ath5k_hw {
                 /* Values in 0.25dB units */
                 s16             txp_min_pwr;
                 s16             txp_max_pwr;
+                s16             txp_cur_pwr;
                 /* Values in 0.5dB units */
                 s16             txp_offset;
                 s16             txp_ofdm;
                 s16             txp_cck_ofdm_gainf_delta;
                 /* Value in dB units */
                 s16             txp_cck_ofdm_pwr_delta;
+                bool            txp_setup;
         } ah_txpower;
 
         struct {
@@ -1102,7 +1122,7 @@ struct ath5k_hw {
         struct ath5k_nfcal_hist ah_nfcal_hist;
 
         /* average beacon RSSI in our BSS (used by ANI) */
-        struct ath5k_avg_val    ah_beacon_rssi_avg;
+        struct ewma             ah_beacon_rssi_avg;
 
         /* noise floor from last periodic calibration */
         s32                     ah_noise_floor;
@@ -1131,36 +1151,50 @@ struct ath5k_hw {
 /*
  * Prototypes
  */
+extern const struct ieee80211_ops ath5k_hw_ops;
 
-/* Attach/Detach Functions */
-int ath5k_hw_attach(struct ath5k_softc *sc);
-void ath5k_hw_detach(struct ath5k_hw *ah);
+/* Initialization and detach functions */
+int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops);
+void ath5k_deinit_softc(struct ath5k_softc *sc);
+int ath5k_hw_init(struct ath5k_softc *sc);
+void ath5k_hw_deinit(struct ath5k_hw *ah);
 
 int ath5k_sysfs_register(struct ath5k_softc *sc);
 void ath5k_sysfs_unregister(struct ath5k_softc *sc);
 
+/*Chip id helper functions */
+const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val);
+int ath5k_hw_read_srev(struct ath5k_hw *ah);
+
 /* LED functions */
 int ath5k_init_leds(struct ath5k_softc *sc);
 void ath5k_led_enable(struct ath5k_softc *sc);
 void ath5k_led_off(struct ath5k_softc *sc);
 void ath5k_unregister_leds(struct ath5k_softc *sc);
 
+
 /* Reset Functions */
 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
 int ath5k_hw_on_hold(struct ath5k_hw *ah);
 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
-                   struct ieee80211_channel *channel, bool change_channel);
+           struct ieee80211_channel *channel, bool fast, bool skip_pcu);
 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
                               bool is_set);
 /* Power management functions */
 
+
+/* Clock rate related functions */
+unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
+unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
+void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
+
+
 /* DMA Related Functions */
 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
-int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
-void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
+int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
-int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
+int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
                                 u32 phys_addr);
@@ -1170,38 +1204,43 @@ bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
+/* Init/Stop functions */
+void ath5k_hw_dma_init(struct ath5k_hw *ah);
+int ath5k_hw_dma_stop(struct ath5k_hw *ah);
 
 /* EEPROM access functions */
 int ath5k_eeprom_init(struct ath5k_hw *ah);
 void ath5k_eeprom_detach(struct ath5k_hw *ah);
 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
 
+
 /* Protocol Control Unit Functions */
+/* Helpers */
+int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
+                int len, struct ieee80211_rate *rate);
+unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
+unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
-/* BSSID Functions */
+/* RX filter control*/
 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
 void ath5k_hw_set_bssid(struct ath5k_hw *ah);
 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
-/* Receive start/stop functions */
-void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
-void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
-/* RX Filter functions */
 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
+/* Receive (DRU) start/stop functions */
+void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
+void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
 /* Beacon control functions */
 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
-/* ACK bit rate */
-void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
-/* Clock rate related functions */
-unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
-unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
-void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
+/* Init function */
+void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
+                                                                u8 mode);
 
 /* Queue Control Unit, DFS Control Unit Functions */
 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
@@ -1214,7 +1253,9 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
-int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
+int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
+/* Init function */
+int ath5k_hw_init_queues(struct ath5k_hw *ah);
 
 /* Hardware Descriptor Functions */
 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
@@ -1224,6 +1265,7 @@ int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
         u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
 
+
 /* GPIO Functions */
 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
@@ -1233,11 +1275,13 @@ int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
                             u32 interrupt_level);
 
-/* rfkill Functions */
+
+/* RFkill Functions */
 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
 
-/* Misc functions */
+
+/* Misc functions TODO: Cleanup */
 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
 int ath5k_hw_get_capability(struct ath5k_hw *ah,
                             enum ath5k_capability_type cap_type, u32 capability,
@@ -1245,19 +1289,20 @@ int ath5k_hw_get_capability(struct ath5k_hw *ah,
 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
 
+
 /* Initial register settings functions */
 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
 
-/* Initialize RF */
-int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
-                         struct ieee80211_channel *channel,
-                         unsigned int mode);
-int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
+
+/* PHY functions */
+/* Misc PHY functions */
+u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
+int ath5k_hw_phy_disable(struct ath5k_hw *ah);
+/* Gain_F optimization */
 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
 /* PHY/RF channel functions */
 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
-int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
 /* PHY calibration */
 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
@@ -1266,18 +1311,14 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
 /* Spur mitigation */
 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
                                   struct ieee80211_channel *channel);
-void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
-                                         struct ieee80211_channel *channel);
-/* Misc PHY functions */
-u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
-int ath5k_hw_phy_disable(struct ath5k_hw *ah);
 /* Antenna control */
 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
 /* TX power setup */
-int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
-                     u8 ee_mode, u8 txpower);
 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
+/* Init function */
+int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
+                                u8 mode, bool fast);
 
 /*
  * Functions used internaly
@@ -1293,6 +1334,32 @@ static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
         return &(ath5k_hw_common(ah)->regulatory);
 }
 
+#ifdef CONFIG_ATHEROS_AR231X
+#define AR5K_AR2315_PCI_BASE    ((void __iomem *)0xb0100000)
+
+static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
+{
+        /* On AR2315 and AR2317 the PCI clock domain registers
+         * are outside of the WMAC register space */
+        if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
+                (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
+                return AR5K_AR2315_PCI_BASE + reg;
+
+        return ah->ah_iobase + reg;
+}
+
+static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
+{
+        return __raw_readl(ath5k_ahb_reg(ah, reg));
+}
+
+static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
+{
+        __raw_writel(val, ath5k_ahb_reg(ah, reg));
+}
+
+#else
+
 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
 {
         return ioread32(ah->ah_iobase + reg);
@@ -1303,6 +1370,24 @@ static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
         iowrite32(val, ah->ah_iobase + reg);
 }
 
+#endif
+
+static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
+{
+        return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
+}
+
+static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
+{
+        common->bus_ops->read_cachesize(common, csz);
+}
+
+static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        return common->bus_ops->eeprom_read(common, off, data);
+}
+
 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
 {
         u32 retval = 0, bit, i;
@@ -1315,27 +1400,4 @@ static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
         return retval;
 }
 
-#define AVG_SAMPLES     8
-#define AVG_FACTOR      1000
-
-/**
- * ath5k_moving_average -  Exponentially weighted moving average
- * @avg: average structure
- * @val: current value
- *
- * This implementation make use of a struct ath5k_avg_val to prevent rounding
- * errors.
- */
-static inline struct ath5k_avg_val
-ath5k_moving_average(const struct ath5k_avg_val avg, const int val)
-{
-        struct ath5k_avg_val new;
-        new.avg_weight = avg.avg_weight  ?
-                (((avg.avg_weight * ((AVG_SAMPLES) - 1)) +
-                        (val * (AVG_FACTOR))) / (AVG_SAMPLES)) :
-                (val * (AVG_FACTOR));
-        new.avg = new.avg_weight / (AVG_FACTOR);
-        return new;
-}
-
 #endif
diff --git a/drivers/net/wireless/ath/ath5k/attach.c b/drivers/net/wireless/ath/ath5k/attach.c
index fbe8aca975d8..cdac5cff0177 100644
--- a/drivers/net/wireless/ath/ath5k/attach.c
+++ b/drivers/net/wireless/ath/ath5k/attach.c
@@ -93,16 +93,16 @@ static int ath5k_hw_post(struct ath5k_hw *ah)
 }
 
 /**
- * ath5k_hw_attach - Check if hw is supported and init the needed structs
+ * ath5k_hw_init - Check if hw is supported and init the needed structs
  *
- * @sc: The &struct ath5k_softc we got from the driver's attach function
+ * @sc: The &struct ath5k_softc we got from the driver's init_softc function
  *
  * Check if the device is supported, perform a POST and initialize the needed
  * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  * -ENODEV if the device is not supported or prints an error msg if something
  * else went wrong.
  */
-int ath5k_hw_attach(struct ath5k_softc *sc)
+int ath5k_hw_init(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
         struct ath_common *common = ath5k_hw_common(ah);
@@ -115,7 +115,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
          * HW information
          */
         ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
-        ah->ah_turbo = false;
+        ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
         ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
         ah->ah_imr = 0;
         ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
@@ -128,7 +128,8 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         /*
          * Find the mac version
          */
-        srev = ath5k_hw_reg_read(ah, AR5K_SREV);
+        ath5k_hw_read_srev(ah);
+        srev = ah->ah_mac_srev;
         if (srev < AR5K_SREV_AR5311)
                 ah->ah_version = AR5K_AR5210;
         else if (srev < AR5K_SREV_AR5212)
@@ -136,6 +137,10 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         else
                 ah->ah_version = AR5K_AR5212;
 
+        /* Get the MAC revision */
+        ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+        ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
+
         /* Fill the ath5k_hw struct with the needed functions */
         ret = ath5k_hw_init_desc_functions(ah);
         if (ret)
@@ -146,9 +151,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         if (ret)
                 goto err;
 
-        /* Get MAC, PHY and RADIO revisions */
-        ah->ah_mac_srev = srev;
-        ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+        /* Get PHY and RADIO revisions */
         ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
                         0xffffffff;
         ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
@@ -273,7 +276,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         /*
          * Write PCI-E power save settings
          */
-        if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
+        if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
                 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
                 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
 
@@ -305,8 +308,7 @@ int ath5k_hw_attach(struct ath5k_softc *sc)
         /* Get misc capabilities */
         ret = ath5k_hw_set_capabilities(ah);
         if (ret) {
-                ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
-                        sc->pdev->device);
+                ATH5K_ERR(sc, "unable to get device capabilities\n");
                 goto err;
         }
 
@@ -346,11 +348,11 @@ err:
 }
 
 /**
- * ath5k_hw_detach - Free the ath5k_hw struct
+ * ath5k_hw_deinit - Free the ath5k_hw struct
  *
  * @ah: The &struct ath5k_hw
  */
-void ath5k_hw_detach(struct ath5k_hw *ah)
+void ath5k_hw_deinit(struct ath5k_hw *ah)
 {
         __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
 
diff --git a/drivers/net/wireless/ath/ath5k/base.c b/drivers/net/wireless/ath/ath5k/base.c
index 42ed923cdb1a..019a74d533a6 100644
--- a/drivers/net/wireless/ath/ath5k/base.c
+++ b/drivers/net/wireless/ath/ath5k/base.c
@@ -47,8 +47,6 @@
 #include <linux/io.h>
 #include <linux/netdevice.h>
 #include <linux/cache.h>
-#include <linux/pci.h>
-#include <linux/pci-aspm.h>
 #include <linux/ethtool.h>
 #include <linux/uaccess.h>
 #include <linux/slab.h>
@@ -62,10 +60,9 @@
 #include "reg.h"
 #include "debug.h"
 #include "ani.h"
-#include "../debug.h"
 
-static int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
+int ath5k_modparam_nohwcrypt;
+module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
 
 static int modparam_all_channels;
@@ -78,39 +75,24 @@ MODULE_AUTHOR("Nick Kossifidis");
 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
 MODULE_LICENSE("Dual BSD/GPL");
-MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
-
-static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
-static int ath5k_beacon_update(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif);
-static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
-
-/* Known PCI ids */
-static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
-        { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
-        { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
-        { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
-        { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
-        { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
-        { PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
-        { PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
-        { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
-        { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
-        { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
-        { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
-        { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
-        { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
-        { 0 }
-};
-MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
+
+static int ath5k_init(struct ieee80211_hw *hw);
+static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
+                                                                bool skip_pcu);
+int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
+void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 
 /* Known SREVs */
 static const struct ath5k_srev_name srev_names[] = {
+#ifdef CONFIG_ATHEROS_AR231X
+        { "5312",       AR5K_VERSION_MAC,       AR5K_SREV_AR5312_R2 },
+        { "5312",       AR5K_VERSION_MAC,       AR5K_SREV_AR5312_R7 },
+        { "2313",       AR5K_VERSION_MAC,       AR5K_SREV_AR2313_R8 },
+        { "2315",       AR5K_VERSION_MAC,       AR5K_SREV_AR2315_R6 },
+        { "2315",       AR5K_VERSION_MAC,       AR5K_SREV_AR2315_R7 },
+        { "2317",       AR5K_VERSION_MAC,       AR5K_SREV_AR2317_R1 },
+        { "2317",       AR5K_VERSION_MAC,       AR5K_SREV_AR2317_R2 },
+#else
         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
@@ -129,6 +111,7 @@ static const struct ath5k_srev_name srev_names[] = {
         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
+#endif
         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
@@ -142,10 +125,12 @@ static const struct ath5k_srev_name srev_names[] = {
         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
-        { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
-        { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
+#ifdef CONFIG_ATHEROS_AR231X
+        { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
+        { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
+#endif
         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 };
 
@@ -191,38 +176,6 @@ static const struct ieee80211_rate ath5k_rates[] = {
         /* XR missing */
 };
 
-static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
-                                struct ath5k_buf *bf)
-{
-        BUG_ON(!bf);
-        if (!bf->skb)
-                return;
-        pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
-                        PCI_DMA_TODEVICE);
-        dev_kfree_skb_any(bf->skb);
-        bf->skb = NULL;
-        bf->skbaddr = 0;
-        bf->desc->ds_data = 0;
-}
-
-static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
-                                struct ath5k_buf *bf)
-{
-        struct ath5k_hw *ah = sc->ah;
-        struct ath_common *common = ath5k_hw_common(ah);
-
-        BUG_ON(!bf);
-        if (!bf->skb)
-                return;
-        pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
-                        PCI_DMA_FROMDEVICE);
-        dev_kfree_skb_any(bf->skb);
-        bf->skb = NULL;
-        bf->skbaddr = 0;
-        bf->desc->ds_data = 0;
-}
-
-
 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 {
         u64 tsf = ath5k_hw_get_tsf64(ah);
@@ -233,7 +186,7 @@ static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
         return (tsf & ~0x7fff) | rstamp;
 }
 
-static const char *
+const char *
 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 {
         const char *name = "xxxxx";
@@ -327,14 +280,12 @@ ath5k_copy_channels(struct ath5k_hw *ah,
 
         switch (mode) {
         case AR5K_MODE_11A:
-        case AR5K_MODE_11A_TURBO:
                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
                 size = 220 ;
                 chfreq = CHANNEL_5GHZ;
                 break;
         case AR5K_MODE_11B:
         case AR5K_MODE_11G:
-        case AR5K_MODE_11G_TURBO:
                 size = 26;
                 chfreq = CHANNEL_2GHZ;
                 break;
@@ -363,11 +314,6 @@ ath5k_copy_channels(struct ath5k_hw *ah,
                 case AR5K_MODE_11G:
                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
                         break;
-                case AR5K_MODE_11A_TURBO:
-                case AR5K_MODE_11G_TURBO:
-                        channels[count].hw_value = chfreq |
-                                CHANNEL_OFDM | CHANNEL_TURBO;
-                        break;
                 case AR5K_MODE_11B:
                         channels[count].hw_value = CHANNEL_B;
                 }
@@ -483,7 +429,7 @@ ath5k_setup_bands(struct ieee80211_hw *hw)
  *
  * Called with sc->lock.
  */
-static int
+int
 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
 {
         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
@@ -496,7 +442,7 @@ ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
          * hardware at the new frequency, and then re-enable
          * the relevant bits of the h/w.
          */
-        return ath5k_reset(sc, chan);
+        return ath5k_reset(sc, chan, true);
 }
 
 static void
@@ -549,7 +495,7 @@ static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
         /* Calculate combined mode - when APs are active, operate in AP mode.
          * Otherwise use the mode of the new interface. This can currently
          * only deal with combinations of APs and STAs. Only one ad-hoc
-         * interfaces is allowed above.
+         * interfaces is allowed.
          */
         if (avf->opmode == NL80211_IFTYPE_AP)
                 iter_data->opmode = NL80211_IFTYPE_AP;
@@ -558,16 +504,9 @@ static void ath_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
                         iter_data->opmode = avf->opmode;
 }
 
-static void ath_do_set_opmode(struct ath5k_softc *sc)
-{
-        struct ath5k_hw *ah = sc->ah;
-        ath5k_hw_set_opmode(ah, sc->opmode);
-        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
-                  sc->opmode, ath_opmode_to_string(sc->opmode));
-}
-
-void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
-                                        struct ieee80211_vif *vif)
+void
+ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
+                                   struct ieee80211_vif *vif)
 {
         struct ath_common *common = ath5k_hw_common(sc->ah);
         struct ath_vif_iter_data iter_data;
@@ -595,7 +534,9 @@ void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
                 /* Nothing active, default to station mode */
                 sc->opmode = NL80211_IFTYPE_STATION;
 
-        ath_do_set_opmode(sc);
+        ath5k_hw_set_opmode(sc->ah, sc->opmode);
+        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
+                  sc->opmode, ath_opmode_to_string(sc->opmode));
 
         if (iter_data.need_set_hw_addr && iter_data.found_active)
                 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
@@ -604,7 +545,7 @@ void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
                 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 }
 
-static void
+void
 ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif)
 {
         struct ath5k_hw *ah = sc->ah;
@@ -659,10 +600,11 @@ struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
                 return NULL;
         }
 
-        *skb_addr = pci_map_single(sc->pdev,
+        *skb_addr = dma_map_single(sc->dev,
                                    skb->data, common->rx_bufsize,
-                                   PCI_DMA_FROMDEVICE);
-        if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
+                                   DMA_FROM_DEVICE);
+
+        if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
                 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
                 dev_kfree_skb(skb);
                 return NULL;
@@ -758,8 +700,8 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
 
         /* XXX endianness */
-        bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
-                        PCI_DMA_TODEVICE);
+        bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
+                        DMA_TO_DEVICE);
 
         rate = ieee80211_get_tx_rate(sc->hw, info);
         if (!rate) {
@@ -839,7 +781,7 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
 
         return 0;
 err_unmap:
-        pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
+        dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
         return ret;
 }
 
@@ -848,7 +790,7 @@ err_unmap:
 \*******************/
 
 static int
-ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
+ath5k_desc_alloc(struct ath5k_softc *sc)
 {
         struct ath5k_desc *ds;
         struct ath5k_buf *bf;
@@ -859,7 +801,9 @@ ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
         /* allocate descriptors */
         sc->desc_len = sizeof(struct ath5k_desc) *
                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
-        sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
+
+        sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
+                                &sc->desc_daddr, GFP_KERNEL);
         if (sc->desc == NULL) {
                 ATH5K_ERR(sc, "can't allocate descriptors\n");
                 ret = -ENOMEM;
@@ -905,14 +849,45 @@ ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
 
         return 0;
 err_free:
-        pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
+        dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
 err:
         sc->desc = NULL;
         return ret;
 }
 
+void
+ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
+{
+        BUG_ON(!bf);
+        if (!bf->skb)
+                return;
+        dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
+                        DMA_TO_DEVICE);
+        dev_kfree_skb_any(bf->skb);
+        bf->skb = NULL;
+        bf->skbaddr = 0;
+        bf->desc->ds_data = 0;
+}
+
+void
+ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
+{
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+
+        BUG_ON(!bf);
+        if (!bf->skb)
+                return;
+        dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
+                        DMA_FROM_DEVICE);
+        dev_kfree_skb_any(bf->skb);
+        bf->skb = NULL;
+        bf->skbaddr = 0;
+        bf->desc->ds_data = 0;
+}
+
 static void
-ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
+ath5k_desc_free(struct ath5k_softc *sc)
 {
         struct ath5k_buf *bf;
 
@@ -924,7 +899,7 @@ ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
                 ath5k_txbuf_free_skb(sc, bf);
 
         /* Free memory associated with all descriptors */
-        pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
+        dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
         sc->desc = NULL;
         sc->desc_daddr = 0;
 
@@ -1069,62 +1044,44 @@ err:
         return ret;
 }
 
+/**
+ * ath5k_drain_tx_buffs - Empty tx buffers
+ *
+ * @sc The &struct ath5k_softc
+ *
+ * Empty tx buffers from all queues in preparation
+ * of a reset or during shutdown.
+ *
+ * NB:  this assumes output has been stopped and
+ *      we do not need to block ath5k_tx_tasklet
+ */
 static void
-ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
+ath5k_drain_tx_buffs(struct ath5k_softc *sc)
 {
+        struct ath5k_txq *txq;
         struct ath5k_buf *bf, *bf0;
+        int i;
 
-        /*
-         * NB: this assumes output has been stopped and
-         *     we do not need to block ath5k_tx_tasklet
-         */
-        spin_lock_bh(&txq->lock);
-        list_for_each_entry_safe(bf, bf0, &txq->q, list) {
-                ath5k_debug_printtxbuf(sc, bf);
-
-                ath5k_txbuf_free_skb(sc, bf);
-
-                spin_lock_bh(&sc->txbuflock);
-                list_move_tail(&bf->list, &sc->txbuf);
-                sc->txbuf_len++;
-                txq->txq_len--;
-                spin_unlock_bh(&sc->txbuflock);
-        }
-        txq->link = NULL;
-        txq->txq_poll_mark = false;
-        spin_unlock_bh(&txq->lock);
-}
+        for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
+                if (sc->txqs[i].setup) {
+                        txq = &sc->txqs[i];
+                        spin_lock_bh(&txq->lock);
+                        list_for_each_entry_safe(bf, bf0, &txq->q, list) {
+                                ath5k_debug_printtxbuf(sc, bf);
 
-/*
- * Drain the transmit queues and reclaim resources.
- */
-static void
-ath5k_txq_cleanup(struct ath5k_softc *sc)
-{
-        struct ath5k_hw *ah = sc->ah;
-        unsigned int i;
+                                ath5k_txbuf_free_skb(sc, bf);
 
-        /* XXX return value */
-        if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
-                /* don't touch the hardware if marked invalid */
-                ath5k_hw_stop_tx_dma(ah, sc->bhalq);
-                ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
-                        ath5k_hw_get_txdp(ah, sc->bhalq));
-                for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
-                        if (sc->txqs[i].setup) {
-                                ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
-                                ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
-                                        "link %p\n",
-                                        sc->txqs[i].qnum,
-                                        ath5k_hw_get_txdp(ah,
-                                                        sc->txqs[i].qnum),
-                                        sc->txqs[i].link);
+                                spin_lock_bh(&sc->txbuflock);
+                                list_move_tail(&bf->list, &sc->txbuf);
+                                sc->txbuf_len++;
+                                txq->txq_len--;
+                                spin_unlock_bh(&sc->txbuflock);
                         }
+                        txq->link = NULL;
+                        txq->txq_poll_mark = false;
+                        spin_unlock_bh(&txq->lock);
+                }
         }
-
-        for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
-                if (sc->txqs[i].setup)
-                        ath5k_txq_drainq(sc, &sc->txqs[i]);
 }
 
 static void
@@ -1184,16 +1141,19 @@ err:
 }
 
 /*
- * Disable the receive h/w in preparation for a reset.
+ * Disable the receive logic on PCU (DRU)
+ * In preparation for a shutdown.
+ *
+ * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
+ * does.
  */
 static void
 ath5k_rx_stop(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
 
-        ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
-        ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
+        ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
 
         ath5k_debug_printrxbuffs(sc, ah);
 }
@@ -1307,8 +1267,7 @@ ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
             memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
                 return;
 
-        ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
-                                                      rssi);
+        ewma_add(&ah->ah_beacon_rssi_avg, rssi);
 
         /* in IBSS mode we should keep RSSI statistics per neighbour */
         /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
@@ -1551,9 +1510,9 @@ ath5k_tasklet_rx(unsigned long data)
                         if (!next_skb)
                                 goto next;
 
-                        pci_unmap_single(sc->pdev, bf->skbaddr,
+                        dma_unmap_single(sc->dev, bf->skbaddr,
                                          common->rx_bufsize,
-                                         PCI_DMA_FROMDEVICE);
+                                         DMA_FROM_DEVICE);
 
                         skb_put(skb, rs.rs_datalen);
 
@@ -1574,8 +1533,9 @@ unlock:
 * TX Handling *
 \*************/
 
-static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
-                          struct ath5k_txq *txq)
+int
+ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
+               struct ath5k_txq *txq)
 {
         struct ath5k_softc *sc = hw->priv;
         struct ath5k_buf *bf;
@@ -1716,8 +1676,9 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
 
                         skb = bf->skb;
                         bf->skb = NULL;
-                        pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
-                                        PCI_DMA_TODEVICE);
+
+                        dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
+                                        DMA_TO_DEVICE);
                         ath5k_tx_frame_completed(sc, skb, &ts);
                 }
 
@@ -1771,12 +1732,13 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
         u32 flags;
         const int padsize = 0;
 
-        bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
-                        PCI_DMA_TODEVICE);
+        bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
+                        DMA_TO_DEVICE);
         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
                         "skbaddr %llx\n", skb, skb->data, skb->len,
                         (unsigned long long)bf->skbaddr);
-        if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
+
+        if (dma_mapping_error(sc->dev, bf->skbaddr)) {
                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
                 return -EIO;
         }
@@ -1828,7 +1790,7 @@ ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
 
         return 0;
 err_unmap:
-        pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
+        dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
         return ret;
 }
 
@@ -1839,7 +1801,7 @@ err_unmap:
  *
  * Called with the beacon lock.
  */
-static int
+int
 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
 {
         int ret;
@@ -1945,7 +1907,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
          * This should never fail since we check above that no frames
          * are still pending on the queue.
          */
-        if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
+        if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
                 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
                 /* NB: hw still stops DMA, so proceed */
         }
@@ -1985,7 +1947,7 @@ ath5k_beacon_send(struct ath5k_softc *sc)
  * when we otherwise know we have to update the timers, but we keep it in this
  * function to have it all together in one place.
  */
-static void
+void
 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
 {
         struct ath5k_hw *ah = sc->ah;
@@ -2087,7 +2049,7 @@ ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
  * interrupts to detect TSF updates only.
  */
-static void
+void
 ath5k_beacon_config(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
@@ -2115,7 +2077,7 @@ ath5k_beacon_config(struct ath5k_softc *sc)
                 } else
                         ath5k_beacon_update_timers(sc, -1);
         } else {
-                ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
+                ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
         }
 
         ath5k_hw_set_imr(ah, sc->imask);
@@ -2177,7 +2139,7 @@ ath5k_intr_calibration_poll(struct ath5k_hw *ah)
          * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
 }
 
-static irqreturn_t
+irqreturn_t
 ath5k_intr(int irq, void *dev_id)
 {
         struct ath5k_softc *sc = dev_id;
@@ -2186,7 +2148,8 @@ ath5k_intr(int irq, void *dev_id)
         unsigned int counter = 1000;
 
         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
-                                !ath5k_hw_is_intr_pending(ah)))
+                ((ath5k_get_bus_type(ah) != ATH_AHB) &&
+                                !ath5k_hw_is_intr_pending(ah))))
                 return IRQ_NONE;
 
         do {
@@ -2252,6 +2215,10 @@ ath5k_intr(int irq, void *dev_id)
                                 tasklet_schedule(&sc->rf_kill.toggleq);
 
                 }
+
+                if (ath5k_get_bus_type(ah) == ATH_AHB)
+                        break;
+
         } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
 
         if (unlikely(!counter))
@@ -2351,7 +2318,7 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
         if (needreset) {
                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
                           "TX queues stuck, resetting\n");
-                ath5k_reset(sc, sc->curchan);
+                ath5k_reset(sc, NULL, true);
         }
 
         ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
@@ -2363,6 +2330,163 @@ ath5k_tx_complete_poll_work(struct work_struct *work)
 * Initialization routines *
 \*************************/
 
+int
+ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
+{
+        struct ieee80211_hw *hw = sc->hw;
+        struct ath_common *common;
+        int ret;
+        int csz;
+
+        /* Initialize driver private data */
+        SET_IEEE80211_DEV(hw, sc->dev);
+        hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
+                        IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
+                        IEEE80211_HW_SIGNAL_DBM |
+                        IEEE80211_HW_REPORTS_TX_ACK_STATUS;
+
+        hw->wiphy->interface_modes =
+                BIT(NL80211_IFTYPE_AP) |
+                BIT(NL80211_IFTYPE_STATION) |
+                BIT(NL80211_IFTYPE_ADHOC) |
+                BIT(NL80211_IFTYPE_MESH_POINT);
+
+        /* both antennas can be configured as RX or TX */
+        hw->wiphy->available_antennas_tx = 0x3;
+        hw->wiphy->available_antennas_rx = 0x3;
+
+        hw->extra_tx_headroom = 2;
+        hw->channel_change_time = 5000;
+
+        /*
+         * Mark the device as detached to avoid processing
+         * interrupts until setup is complete.
+         */
+        __set_bit(ATH_STAT_INVALID, sc->status);
+
+        sc->opmode = NL80211_IFTYPE_STATION;
+        sc->bintval = 1000;
+        mutex_init(&sc->lock);
+        spin_lock_init(&sc->rxbuflock);
+        spin_lock_init(&sc->txbuflock);
+        spin_lock_init(&sc->block);
+
+
+        /* Setup interrupt handler */
+        ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
+        if (ret) {
+                ATH5K_ERR(sc, "request_irq failed\n");
+                goto err;
+        }
+
+        /* If we passed the test, malloc an ath5k_hw struct */
+        sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
+        if (!sc->ah) {
+                ret = -ENOMEM;
+                ATH5K_ERR(sc, "out of memory\n");
+                goto err_irq;
+        }
+
+        sc->ah->ah_sc = sc;
+        sc->ah->ah_iobase = sc->iobase;
+        common = ath5k_hw_common(sc->ah);
+        common->ops = &ath5k_common_ops;
+        common->bus_ops = bus_ops;
+        common->ah = sc->ah;
+        common->hw = hw;
+        common->priv = sc;
+
+        /*
+         * Cache line size is used to size and align various
+         * structures used to communicate with the hardware.
+         */
+        ath5k_read_cachesize(common, &csz);
+        common->cachelsz = csz << 2; /* convert to bytes */
+
+        spin_lock_init(&common->cc_lock);
+
+        /* Initialize device */
+        ret = ath5k_hw_init(sc);
+        if (ret)
+                goto err_free_ah;
+
+        /* set up multi-rate retry capabilities */
+        if (sc->ah->ah_version == AR5K_AR5212) {
+                hw->max_rates = 4;
+                hw->max_rate_tries = 11;
+        }
+
+        hw->vif_data_size = sizeof(struct ath5k_vif);
+
+        /* Finish private driver data initialization */
+        ret = ath5k_init(hw);
+        if (ret)
+                goto err_ah;
+
+        ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
+                        ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
+                                        sc->ah->ah_mac_srev,
+                                        sc->ah->ah_phy_revision);
+
+        if (!sc->ah->ah_single_chip) {
+                /* Single chip radio (!RF5111) */
+                if (sc->ah->ah_radio_5ghz_revision &&
+                        !sc->ah->ah_radio_2ghz_revision) {
+                        /* No 5GHz support -> report 2GHz radio */
+                        if (!test_bit(AR5K_MODE_11A,
+                                sc->ah->ah_capabilities.cap_mode)) {
+                                ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
+                                        ath5k_chip_name(AR5K_VERSION_RAD,
+                                                sc->ah->ah_radio_5ghz_revision),
+                                                sc->ah->ah_radio_5ghz_revision);
+                        /* No 2GHz support (5110 and some
+                         * 5Ghz only cards) -> report 5Ghz radio */
+                        } else if (!test_bit(AR5K_MODE_11B,
+                                sc->ah->ah_capabilities.cap_mode)) {
+                                ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
+                                        ath5k_chip_name(AR5K_VERSION_RAD,
+                                                sc->ah->ah_radio_5ghz_revision),
+                                                sc->ah->ah_radio_5ghz_revision);
+                        /* Multiband radio */
+                        } else {
+                                ATH5K_INFO(sc, "RF%s multiband radio found"
+                                        " (0x%x)\n",
+                                        ath5k_chip_name(AR5K_VERSION_RAD,
+                                                sc->ah->ah_radio_5ghz_revision),
+                                                sc->ah->ah_radio_5ghz_revision);
+                        }
+                }
+                /* Multi chip radio (RF5111 - RF2111) ->
+                 * report both 2GHz/5GHz radios */
+                else if (sc->ah->ah_radio_5ghz_revision &&
+                                sc->ah->ah_radio_2ghz_revision){
+                        ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
+                                ath5k_chip_name(AR5K_VERSION_RAD,
+                                        sc->ah->ah_radio_5ghz_revision),
+                                        sc->ah->ah_radio_5ghz_revision);
+                        ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
+                                ath5k_chip_name(AR5K_VERSION_RAD,
+                                        sc->ah->ah_radio_2ghz_revision),
+                                        sc->ah->ah_radio_2ghz_revision);
+                }
+        }
+
+        ath5k_debug_init_device(sc);
+
+        /* ready to process interrupts */
+        __clear_bit(ATH_STAT_INVALID, sc->status);
+
+        return 0;
+err_ah:
+        ath5k_hw_deinit(sc->ah);
+err_free_ah:
+        kfree(sc->ah);
+err_irq:
+        free_irq(sc->irq, sc);
+err:
+        return ret;
+}
+
 static int
 ath5k_stop_locked(struct ath5k_softc *sc)
 {
@@ -2391,19 +2515,18 @@ ath5k_stop_locked(struct ath5k_softc *sc)
         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
                 ath5k_led_off(sc);
                 ath5k_hw_set_imr(ah, 0);
-                synchronize_irq(sc->pdev->irq);
-        }
-        ath5k_txq_cleanup(sc);
-        if (!test_bit(ATH_STAT_INVALID, sc->status)) {
+                synchronize_irq(sc->irq);
                 ath5k_rx_stop(sc);
+                ath5k_hw_dma_stop(ah);
+                ath5k_drain_tx_buffs(sc);
                 ath5k_hw_phy_disable(ah);
         }
 
         return 0;
 }
 
-static int
-ath5k_init(struct ath5k_softc *sc)
+int
+ath5k_init_hw(struct ath5k_softc *sc)
 {
         struct ath5k_hw *ah = sc->ah;
         struct ath_common *common = ath5k_hw_common(ah);
@@ -2432,7 +2555,7 @@ ath5k_init(struct ath5k_softc *sc)
                 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
                 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
 
-        ret = ath5k_reset(sc, NULL);
+        ret = ath5k_reset(sc, NULL, false);
         if (ret)
                 goto done;
 
@@ -2445,7 +2568,9 @@ ath5k_init(struct ath5k_softc *sc)
         for (i = 0; i < common->keymax; i++)
                 ath_hw_keyreset(common, (u16) i);
 
-        ath5k_hw_set_ack_bitrate_high(ah, true);
+        /* Use higher rates for acks instead of base
+         * rate */
+        ah->ah_ack_bitrate_high = true;
 
         for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
                 sc->bslot[i] = NULL;
@@ -2476,7 +2601,7 @@ static void stop_tasklets(struct ath5k_softc *sc)
  * if another thread does a system call and the thread doing the
  * stop is preempted).
  */
-static int
+int
 ath5k_stop_hw(struct ath5k_softc *sc)
 {
         int ret;
@@ -2529,25 +2654,35 @@ ath5k_stop_hw(struct ath5k_softc *sc)
  * This should be called with sc->lock.
  */
 static int
-ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
+ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
+                                                        bool skip_pcu)
 {
         struct ath5k_hw *ah = sc->ah;
-        int ret;
+        struct ath_common *common = ath5k_hw_common(ah);
+        int ret, ani_mode;
 
         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
 
         ath5k_hw_set_imr(ah, 0);
-        synchronize_irq(sc->pdev->irq);
+        synchronize_irq(sc->irq);
         stop_tasklets(sc);
 
-        if (chan) {
-                ath5k_txq_cleanup(sc);
-                ath5k_rx_stop(sc);
+        /* Save ani mode and disable ANI durring
+         * reset. If we don't we might get false
+         * PHY error interrupts. */
+        ani_mode = ah->ah_sc->ani_state.ani_mode;
+        ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
 
+        /* We are going to empty hw queues
+         * so we should also free any remaining
+         * tx buffers */
+        ath5k_drain_tx_buffs(sc);
+        if (chan) {
                 sc->curchan = chan;
                 sc->curband = &sc->sbands[chan->band];
         }
-        ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
+        ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
+                                                                skip_pcu);
         if (ret) {
                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
                 goto err;
@@ -2559,11 +2694,20 @@ ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
                 goto err;
         }
 
-        ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
+        ath5k_ani_init(ah, ani_mode);
 
         ah->ah_cal_next_full = jiffies;
         ah->ah_cal_next_ani = jiffies;
         ah->ah_cal_next_nf = jiffies;
+        ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
+
+        /* clear survey data and cycle counters */
+        memset(&sc->survey, 0, sizeof(sc->survey));
+        spin_lock_bh(&common->cc_lock);
+        ath_hw_cycle_counters_update(common);
+        memset(&common->cc_survey, 0, sizeof(common->cc_survey));
+        memset(&common->cc_ani, 0, sizeof(common->cc_ani));
+        spin_unlock_bh(&common->cc_lock);
 
         /*
          * Change channels and update the h/w rate map if we're switching;
@@ -2592,13 +2736,14 @@ static void ath5k_reset_work(struct work_struct *work)
                 reset_work);
 
         mutex_lock(&sc->lock);
-        ath5k_reset(sc, sc->curchan);
+        ath5k_reset(sc, NULL, true);
         mutex_unlock(&sc->lock);
 }
 
 static int
-ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
+ath5k_init(struct ieee80211_hw *hw)
 {
+
         struct ath5k_softc *sc = hw->priv;
         struct ath5k_hw *ah = sc->ah;
         struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
@@ -2606,7 +2751,6 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
         u8 mac[ETH_ALEN] = {};
         int ret;
 
-        ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 
         /*
          * Check if the MAC has multi-rate retry support.
@@ -2643,7 +2787,7 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
         /*
          * Allocate tx+rx descriptors and populate the lists.
          */
-        ret = ath5k_desc_alloc(sc, pdev);
+        ret = ath5k_desc_alloc(sc);
         if (ret) {
                 ATH5K_ERR(sc, "can't allocate descriptors\n");
                 goto err;
@@ -2668,33 +2812,46 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
                 goto err_bhal;
         }
 
-        /* This order matches mac80211's queue priority, so we can
-         * directly use the mac80211 queue number without any mapping */
-        txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
-        if (IS_ERR(txq)) {
-                ATH5K_ERR(sc, "can't setup xmit queue\n");
-                ret = PTR_ERR(txq);
-                goto err_queues;
-        }
-        txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
-        if (IS_ERR(txq)) {
-                ATH5K_ERR(sc, "can't setup xmit queue\n");
-                ret = PTR_ERR(txq);
-                goto err_queues;
-        }
-        txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
-        if (IS_ERR(txq)) {
-                ATH5K_ERR(sc, "can't setup xmit queue\n");
-                ret = PTR_ERR(txq);
-                goto err_queues;
-        }
-        txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
-        if (IS_ERR(txq)) {
-                ATH5K_ERR(sc, "can't setup xmit queue\n");
-                ret = PTR_ERR(txq);
-                goto err_queues;
+        /* 5211 and 5212 usually support 10 queues but we better rely on the
+         * capability information */
+        if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
+                /* This order matches mac80211's queue priority, so we can
+                * directly use the mac80211 queue number without any mapping */
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                hw->queues = 4;
+        } else {
+                /* older hardware (5210) can only support one data queue */
+                txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
+                if (IS_ERR(txq)) {
+                        ATH5K_ERR(sc, "can't setup xmit queue\n");
+                        ret = PTR_ERR(txq);
+                        goto err_queues;
+                }
+                hw->queues = 1;
         }
-        hw->queues = 4;
 
         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
@@ -2707,8 +2864,7 @@ ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 
         ret = ath5k_eeprom_read_mac(ah, mac);
         if (ret) {
-                ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
-                        sc->pdev->device);
+                ATH5K_ERR(sc, "unable to read address from EEPROM\n");
                 goto err_queues;
         }
 
@@ -2743,15 +2899,15 @@ err_queues:
 err_bhal:
         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 err_desc:
-        ath5k_desc_free(sc, pdev);
+        ath5k_desc_free(sc);
 err:
         return ret;
 }
 
-static void
-ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
+void
+ath5k_deinit_softc(struct ath5k_softc *sc)
 {
-        struct ath5k_softc *sc = hw->priv;
+        struct ieee80211_hw *hw = sc->hw;
 
         /*
          * NB: the order of these is important:
@@ -2766,8 +2922,9 @@ ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
          * XXX: ??? detach ath5k_hw ???
          * Other than that, it's straightforward...
          */
+        ath5k_debug_finish_device(sc);
         ieee80211_unregister_hw(hw);
-        ath5k_desc_free(sc, pdev);
+        ath5k_desc_free(sc);
         ath5k_txq_release(sc);
         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
         ath5k_unregister_leds(sc);
@@ -2778,232 +2935,12 @@ ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
          * returns because we'll get called back to reclaim node
          * state and potentially want to use them.
          */
+        ath5k_hw_deinit(sc->ah);
+        free_irq(sc->irq, sc);
 }
 
-/********************\
-* Mac80211 functions *
-\********************/
-
-static int
-ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
-        struct ath5k_softc *sc = hw->priv;
-        u16 qnum = skb_get_queue_mapping(skb);
-
-        if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
-                dev_kfree_skb_any(skb);
-                return 0;
-        }
-
-        return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
-}
-
-static int ath5k_start(struct ieee80211_hw *hw)
-{
-        return ath5k_init(hw->priv);
-}
-
-static void ath5k_stop(struct ieee80211_hw *hw)
-{
-        ath5k_stop_hw(hw->priv);
-}
-
-static int ath5k_add_interface(struct ieee80211_hw *hw,
-                struct ieee80211_vif *vif)
-{
-        struct ath5k_softc *sc = hw->priv;
-        int ret;
-        struct ath5k_vif *avf = (void *)vif->drv_priv;
-
-        mutex_lock(&sc->lock);
-
-        if ((vif->type == NL80211_IFTYPE_AP ||
-             vif->type == NL80211_IFTYPE_ADHOC)
-            && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
-                ret = -ELNRNG;
-                goto end;
-        }
-
-        /* Don't allow other interfaces if one ad-hoc is configured.
-         * TODO: Fix the problems with ad-hoc and multiple other interfaces.
-         * We would need to operate the HW in ad-hoc mode to allow TSF updates
-         * for the IBSS, but this breaks with additional AP or STA interfaces
-         * at the moment. */
-        if (sc->num_adhoc_vifs ||
-            (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
-                ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
-                ret = -ELNRNG;
-                goto end;
-        }
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_AP:
-        case NL80211_IFTYPE_STATION:
-        case NL80211_IFTYPE_ADHOC:
-        case NL80211_IFTYPE_MESH_POINT:
-                avf->opmode = vif->type;
-                break;
-        default:
-                ret = -EOPNOTSUPP;
-                goto end;
-        }
-
-        sc->nvifs++;
-        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
-
-        /* Assign the vap/adhoc to a beacon xmit slot. */
-        if ((avf->opmode == NL80211_IFTYPE_AP) ||
-            (avf->opmode == NL80211_IFTYPE_ADHOC) ||
-            (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
-                int slot;
-
-                WARN_ON(list_empty(&sc->bcbuf));
-                avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
-                                             list);
-                list_del(&avf->bbuf->list);
-
-                avf->bslot = 0;
-                for (slot = 0; slot < ATH_BCBUF; slot++) {
-                        if (!sc->bslot[slot]) {
-                                avf->bslot = slot;
-                                break;
-                        }
-                }
-                BUG_ON(sc->bslot[avf->bslot] != NULL);
-                sc->bslot[avf->bslot] = vif;
-                if (avf->opmode == NL80211_IFTYPE_AP)
-                        sc->num_ap_vifs++;
-                else if (avf->opmode == NL80211_IFTYPE_ADHOC)
-                        sc->num_adhoc_vifs++;
-        }
-
-        /* Any MAC address is fine, all others are included through the
-         * filter.
-         */
-        memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
-        ath5k_hw_set_lladdr(sc->ah, vif->addr);
-
-        memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
-
-        ath5k_mode_setup(sc, vif);
-
-        ret = 0;
-end:
-        mutex_unlock(&sc->lock);
-        return ret;
-}
-
-static void
-ath5k_remove_interface(struct ieee80211_hw *hw,
-                        struct ieee80211_vif *vif)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_vif *avf = (void *)vif->drv_priv;
-        unsigned int i;
-
-        mutex_lock(&sc->lock);
-        sc->nvifs--;
-
-        if (avf->bbuf) {
-                ath5k_txbuf_free_skb(sc, avf->bbuf);
-                list_add_tail(&avf->bbuf->list, &sc->bcbuf);
-                for (i = 0; i < ATH_BCBUF; i++) {
-                        if (sc->bslot[i] == vif) {
-                                sc->bslot[i] = NULL;
-                                break;
-                        }
-                }
-                avf->bbuf = NULL;
-        }
-        if (avf->opmode == NL80211_IFTYPE_AP)
-                sc->num_ap_vifs--;
-        else if (avf->opmode == NL80211_IFTYPE_ADHOC)
-                sc->num_adhoc_vifs--;
-
-        ath5k_update_bssid_mask_and_opmode(sc, NULL);
-        mutex_unlock(&sc->lock);
-}
-
-/*
- * TODO: Phy disable/diversity etc
- */
-static int
-ath5k_config(struct ieee80211_hw *hw, u32 changed)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ieee80211_conf *conf = &hw->conf;
-        int ret = 0;
-
-        mutex_lock(&sc->lock);
-
-        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
-                ret = ath5k_chan_set(sc, conf->channel);
-                if (ret < 0)
-                        goto unlock;
-        }
-
-        if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
-        (sc->power_level != conf->power_level)) {
-                sc->power_level = conf->power_level;
-
-                /* Half dB steps */
-                ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
-        }
-
-        /* TODO:
-         * 1) Move this on config_interface and handle each case
-         * separately eg. when we have only one STA vif, use
-         * AR5K_ANTMODE_SINGLE_AP
-         *
-         * 2) Allow the user to change antenna mode eg. when only
-         * one antenna is present
-         *
-         * 3) Allow the user to set default/tx antenna when possible
-         *
-         * 4) Default mode should handle 90% of the cases, together
-         * with fixed a/b and single AP modes we should be able to
-         * handle 99%. Sectored modes are extreme cases and i still
-         * haven't found a usage for them. If we decide to support them,
-         * then we must allow the user to set how many tx antennas we
-         * have available
-         */
-        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
-
-unlock:
-        mutex_unlock(&sc->lock);
-        return ret;
-}
-
-static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
-                                   struct netdev_hw_addr_list *mc_list)
-{
-        u32 mfilt[2], val;
-        u8 pos;
-        struct netdev_hw_addr *ha;
-
-        mfilt[0] = 0;
-        mfilt[1] = 1;
-
-        netdev_hw_addr_list_for_each(ha, mc_list) {
-                /* calculate XOR of eight 6-bit values */
-                val = get_unaligned_le32(ha->addr + 0);
-                pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
-                val = get_unaligned_le32(ha->addr + 3);
-                pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
-                pos &= 0x3f;
-                mfilt[pos / 32] |= (1 << (pos % 32));
-                /* XXX: we might be able to just do this instead,
-                * but not sure, needs testing, if we do use this we'd
-                * neet to inform below to not reset the mcast */
-                /* ath5k_hw_set_mcast_filterindex(ah,
-                 *      ha->addr[5]); */
-        }
-
-        return ((u64)(mfilt[1]) << 32) | mfilt[0];
-}
-
-static bool ath_any_vif_assoc(struct ath5k_softc *sc)
+bool
+ath_any_vif_assoc(struct ath5k_softc *sc)
 {
         struct ath_vif_iter_data iter_data;
         iter_data.hw_macaddr = NULL;
@@ -3016,242 +2953,7 @@ static bool ath_any_vif_assoc(struct ath5k_softc *sc)
         return iter_data.any_assoc;
 }
 
-#define SUPPORTED_FIF_FLAGS \
-        FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
-        FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
-        FIF_BCN_PRBRESP_PROMISC
-/*
- * o always accept unicast, broadcast, and multicast traffic
- * o multicast traffic for all BSSIDs will be enabled if mac80211
- *   says it should be
- * o maintain current state of phy ofdm or phy cck error reception.
- *   If the hardware detects any of these type of errors then
- *   ath5k_hw_get_rx_filter() will pass to us the respective
- *   hardware filters to be able to receive these type of frames.
- * o probe request frames are accepted only when operating in
- *   hostap, adhoc, or monitor modes
- * o enable promiscuous mode according to the interface state
- * o accept beacons:
- *   - when operating in adhoc mode so the 802.11 layer creates
- *     node table entries for peers,
- *   - when operating in station mode for collecting rssi data when
- *     the station is otherwise quiet, or
- *   - when scanning
- */
-static void ath5k_configure_filter(struct ieee80211_hw *hw,
-                unsigned int changed_flags,
-                unsigned int *new_flags,
-                u64 multicast)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        u32 mfilt[2], rfilt;
-
-        mutex_lock(&sc->lock);
-
-        mfilt[0] = multicast;
-        mfilt[1] = multicast >> 32;
-
-        /* Only deal with supported flags */
-        changed_flags &= SUPPORTED_FIF_FLAGS;
-        *new_flags &= SUPPORTED_FIF_FLAGS;
-
-        /* If HW detects any phy or radar errors, leave those filters on.
-         * Also, always enable Unicast, Broadcasts and Multicast
-         * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
-        rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
-                (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
-                AR5K_RX_FILTER_MCAST);
-
-        if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
-                if (*new_flags & FIF_PROMISC_IN_BSS) {
-                        __set_bit(ATH_STAT_PROMISC, sc->status);
-                } else {
-                        __clear_bit(ATH_STAT_PROMISC, sc->status);
-                }
-        }
-
-        if (test_bit(ATH_STAT_PROMISC, sc->status))
-                rfilt |= AR5K_RX_FILTER_PROM;
-
-        /* Note, AR5K_RX_FILTER_MCAST is already enabled */
-        if (*new_flags & FIF_ALLMULTI) {
-                mfilt[0] =  ~0;
-                mfilt[1] =  ~0;
-        }
-
-        /* This is the best we can do */
-        if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
-                rfilt |= AR5K_RX_FILTER_PHYERR;
-
-        /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
-        * and probes for any BSSID */
-        if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
-                rfilt |= AR5K_RX_FILTER_BEACON;
-
-        /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
-         * set we should only pass on control frames for this
-         * station. This needs testing. I believe right now this
-         * enables *all* control frames, which is OK.. but
-         * but we should see if we can improve on granularity */
-        if (*new_flags & FIF_CONTROL)
-                rfilt |= AR5K_RX_FILTER_CONTROL;
-
-        /* Additional settings per mode -- this is per ath5k */
-
-        /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
-
-        switch (sc->opmode) {
-        case NL80211_IFTYPE_MESH_POINT:
-                rfilt |= AR5K_RX_FILTER_CONTROL |
-                         AR5K_RX_FILTER_BEACON |
-                         AR5K_RX_FILTER_PROBEREQ |
-                         AR5K_RX_FILTER_PROM;
-                break;
-        case NL80211_IFTYPE_AP:
-        case NL80211_IFTYPE_ADHOC:
-                rfilt |= AR5K_RX_FILTER_PROBEREQ |
-                         AR5K_RX_FILTER_BEACON;
-                break;
-        case NL80211_IFTYPE_STATION:
-                if (sc->assoc)
-                        rfilt |= AR5K_RX_FILTER_BEACON;
-        default:
-                break;
-        }
-
-        /* Set filters */
-        ath5k_hw_set_rx_filter(ah, rfilt);
-
-        /* Set multicast bits */
-        ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
-        /* Set the cached hw filter flags, this will later actually
-         * be set in HW */
-        sc->filter_flags = rfilt;
-
-        mutex_unlock(&sc->lock);
-}
-
-static int
-ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
-              struct ieee80211_vif *vif, struct ieee80211_sta *sta,
-              struct ieee80211_key_conf *key)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ath_common *common = ath5k_hw_common(ah);
-        int ret = 0;
-
-        if (modparam_nohwcrypt)
-                return -EOPNOTSUPP;
-
-        switch (key->cipher) {
-        case WLAN_CIPHER_SUITE_WEP40:
-        case WLAN_CIPHER_SUITE_WEP104:
-        case WLAN_CIPHER_SUITE_TKIP:
-                break;
-        case WLAN_CIPHER_SUITE_CCMP:
-                if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
-                        break;
-                return -EOPNOTSUPP;
-        default:
-                WARN_ON(1);
-                return -EINVAL;
-        }
-
-        mutex_lock(&sc->lock);
-
-        switch (cmd) {
-        case SET_KEY:
-                ret = ath_key_config(common, vif, sta, key);
-                if (ret >= 0) {
-                        key->hw_key_idx = ret;
-                        /* push IV and Michael MIC generation to stack */
-                        key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
-                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
-                                key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
-                        if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
-                                key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
-                        ret = 0;
-                }
-                break;
-        case DISABLE_KEY:
-                ath_key_delete(common, key);
-                break;
-        default:
-                ret = -EINVAL;
-        }
-
-        mmiowb();
-        mutex_unlock(&sc->lock);
-        return ret;
-}
-
-static int
-ath5k_get_stats(struct ieee80211_hw *hw,
-                struct ieee80211_low_level_stats *stats)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        /* Force update */
-        ath5k_hw_update_mib_counters(sc->ah);
-
-        stats->dot11ACKFailureCount = sc->stats.ack_fail;
-        stats->dot11RTSFailureCount = sc->stats.rts_fail;
-        stats->dot11RTSSuccessCount = sc->stats.rts_ok;
-        stats->dot11FCSErrorCount = sc->stats.fcs_error;
-
-        return 0;
-}
-
-static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
-                struct survey_info *survey)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ieee80211_conf *conf = &hw->conf;
-
-         if (idx != 0)
-                return -ENOENT;
-
-        survey->channel = conf->channel;
-        survey->filled = SURVEY_INFO_NOISE_DBM;
-        survey->noise = sc->ah->ah_noise_floor;
-
-        return 0;
-}
-
-static u64
-ath5k_get_tsf(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        return ath5k_hw_get_tsf64(sc->ah);
-}
-
-static void
-ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        ath5k_hw_set_tsf64(sc->ah, tsf);
-}
-
-static void
-ath5k_reset_tsf(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        /*
-         * in IBSS mode we need to update the beacon timers too.
-         * this will also reset the TSF if we call it with 0
-         */
-        if (sc->opmode == NL80211_IFTYPE_ADHOC)
-                ath5k_beacon_update_timers(sc, 0);
-        else
-                ath5k_hw_reset_tsf(sc->ah);
-}
-
-static void
+void
 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
 {
         struct ath5k_softc *sc = hw->priv;
@@ -3265,494 +2967,3 @@ set_beacon_filter(struct ieee80211_hw *hw, bool enable)
         ath5k_hw_set_rx_filter(ah, rfilt);
         sc->filter_flags = rfilt;
 }
-
-static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
-                                    struct ieee80211_vif *vif,
-                                    struct ieee80211_bss_conf *bss_conf,
-                                    u32 changes)
-{
-        struct ath5k_vif *avf = (void *)vif->drv_priv;
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ath_common *common = ath5k_hw_common(ah);
-        unsigned long flags;
-
-        mutex_lock(&sc->lock);
-
-        if (changes & BSS_CHANGED_BSSID) {
-                /* Cache for later use during resets */
-                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
-                common->curaid = 0;
-                ath5k_hw_set_bssid(ah);
-                mmiowb();
-        }
-
-        if (changes & BSS_CHANGED_BEACON_INT)
-                sc->bintval = bss_conf->beacon_int;
-
-        if (changes & BSS_CHANGED_ASSOC) {
-                avf->assoc = bss_conf->assoc;
-                if (bss_conf->assoc)
-                        sc->assoc = bss_conf->assoc;
-                else
-                        sc->assoc = ath_any_vif_assoc(sc);
-
-                if (sc->opmode == NL80211_IFTYPE_STATION)
-                        set_beacon_filter(hw, sc->assoc);
-                ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
-                        AR5K_LED_ASSOC : AR5K_LED_INIT);
-                if (bss_conf->assoc) {
-                        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
-                                  "Bss Info ASSOC %d, bssid: %pM\n",
-                                  bss_conf->aid, common->curbssid);
-                        common->curaid = bss_conf->aid;
-                        ath5k_hw_set_bssid(ah);
-                        /* Once ANI is available you would start it here */
-                }
-        }
-
-        if (changes & BSS_CHANGED_BEACON) {
-                spin_lock_irqsave(&sc->block, flags);
-                ath5k_beacon_update(hw, vif);
-                spin_unlock_irqrestore(&sc->block, flags);
-        }
-
-        if (changes & BSS_CHANGED_BEACON_ENABLED)
-                sc->enable_beacon = bss_conf->enable_beacon;
-
-        if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
-                       BSS_CHANGED_BEACON_INT))
-                ath5k_beacon_config(sc);
-
-        mutex_unlock(&sc->lock);
-}
-
-static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-        if (!sc->assoc)
-                ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
-}
-
-static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
-{
-        struct ath5k_softc *sc = hw->priv;
-        ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
-                AR5K_LED_ASSOC : AR5K_LED_INIT);
-}
-
-/**
- * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
- *
- * @hw: struct ieee80211_hw pointer
- * @coverage_class: IEEE 802.11 coverage class number
- *
- * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
- * coverage class. The values are persistent, they are restored after device
- * reset.
- */
-static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
-{
-        struct ath5k_softc *sc = hw->priv;
-
-        mutex_lock(&sc->lock);
-        ath5k_hw_set_coverage_class(sc->ah, coverage_class);
-        mutex_unlock(&sc->lock);
-}
-
-static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
-                         const struct ieee80211_tx_queue_params *params)
-{
-        struct ath5k_softc *sc = hw->priv;
-        struct ath5k_hw *ah = sc->ah;
-        struct ath5k_txq_info qi;
-        int ret = 0;
-
-        if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
-                return 0;
-
-        mutex_lock(&sc->lock);
-
-        ath5k_hw_get_tx_queueprops(ah, queue, &qi);
-
-        qi.tqi_aifs = params->aifs;
-        qi.tqi_cw_min = params->cw_min;
-        qi.tqi_cw_max = params->cw_max;
-        qi.tqi_burst_time = params->txop;
-
-        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
-                  "Configure tx [queue %d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
-
-        if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
-                ATH5K_ERR(sc,
-                          "Unable to update hardware queue %u!\n", queue);
-                ret = -EIO;
-        } else
-                ath5k_hw_reset_tx_queue(ah, queue);
-
-        mutex_unlock(&sc->lock);
-
-        return ret;
-}
-
-static const struct ieee80211_ops ath5k_hw_ops = {
-        .tx             = ath5k_tx,
-        .start          = ath5k_start,
-        .stop           = ath5k_stop,
-        .add_interface  = ath5k_add_interface,
-        .remove_interface = ath5k_remove_interface,
-        .config         = ath5k_config,
-        .prepare_multicast = ath5k_prepare_multicast,
-        .configure_filter = ath5k_configure_filter,
-        .set_key        = ath5k_set_key,
-        .get_stats      = ath5k_get_stats,
-        .get_survey     = ath5k_get_survey,
-        .conf_tx        = ath5k_conf_tx,
-        .get_tsf        = ath5k_get_tsf,
-        .set_tsf        = ath5k_set_tsf,
-        .reset_tsf      = ath5k_reset_tsf,
-        .bss_info_changed = ath5k_bss_info_changed,
-        .sw_scan_start  = ath5k_sw_scan_start,
-        .sw_scan_complete = ath5k_sw_scan_complete,
-        .set_coverage_class = ath5k_set_coverage_class,
-};
-
-/********************\
-* PCI Initialization *
-\********************/
-
-static int __devinit
-ath5k_pci_probe(struct pci_dev *pdev,
-                const struct pci_device_id *id)
-{
-        void __iomem *mem;
-        struct ath5k_softc *sc;
-        struct ath_common *common;
-        struct ieee80211_hw *hw;
-        int ret;
-        u8 csz;
-
-        /*
-         * L0s needs to be disabled on all ath5k cards.
-         *
-         * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
-         * by default in the future in 2.6.36) this will also mean both L1 and
-         * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
-         * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
-         * though but cannot currently undue the effect of a blacklist, for
-         * details you can read pcie_aspm_sanity_check() and see how it adjusts
-         * the device link capability.
-         *
-         * It may be possible in the future to implement some PCI API to allow
-         * drivers to override blacklists for pre 1.1 PCIe but for now it is
-         * best to accept that both L0s and L1 will be disabled completely for
-         * distributions shipping with CONFIG_PCIEASPM rather than having this
-         * issue present. Motivation for adding this new API will be to help
-         * with power consumption for some of these devices.
-         */
-        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
-
-        ret = pci_enable_device(pdev);
-        if (ret) {
-                dev_err(&pdev->dev, "can't enable device\n");
-                goto err;
-        }
-
-        /* XXX 32-bit addressing only */
-        ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
-        if (ret) {
-                dev_err(&pdev->dev, "32-bit DMA not available\n");
-                goto err_dis;
-        }
-
-        /*
-         * Cache line size is used to size and align various
-         * structures used to communicate with the hardware.
-         */
-        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
-        if (csz == 0) {
-                /*
-                 * Linux 2.4.18 (at least) writes the cache line size
-                 * register as a 16-bit wide register which is wrong.
-                 * We must have this setup properly for rx buffer
-                 * DMA to work so force a reasonable value here if it
-                 * comes up zero.
-                 */
-                csz = L1_CACHE_BYTES >> 2;
-                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
-        }
-        /*
-         * The default setting of latency timer yields poor results,
-         * set it to the value used by other systems.  It may be worth
-         * tweaking this setting more.
-         */
-        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
-
-        /* Enable bus mastering */
-        pci_set_master(pdev);
-
-        /*
-         * Disable the RETRY_TIMEOUT register (0x41) to keep
-         * PCI Tx retries from interfering with C3 CPU state.
-         */
-        pci_write_config_byte(pdev, 0x41, 0);
-
-        ret = pci_request_region(pdev, 0, "ath5k");
-        if (ret) {
-                dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
-                goto err_dis;
-        }
-
-        mem = pci_iomap(pdev, 0, 0);
-        if (!mem) {
-                dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
-                ret = -EIO;
-                goto err_reg;
-        }
-
-        /*
-         * Allocate hw (mac80211 main struct)
-         * and hw->priv (driver private data)
-         */
-        hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
-        if (hw == NULL) {
-                dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
-                ret = -ENOMEM;
-                goto err_map;
-        }
-
-        dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
-
-        /* Initialize driver private data */
-        SET_IEEE80211_DEV(hw, &pdev->dev);
-        hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
-                    IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
-                    IEEE80211_HW_SIGNAL_DBM;
-
-        hw->wiphy->interface_modes =
-                BIT(NL80211_IFTYPE_AP) |
-                BIT(NL80211_IFTYPE_STATION) |
-                BIT(NL80211_IFTYPE_ADHOC) |
-                BIT(NL80211_IFTYPE_MESH_POINT);
-
-        hw->extra_tx_headroom = 2;
-        hw->channel_change_time = 5000;
-        sc = hw->priv;
-        sc->hw = hw;
-        sc->pdev = pdev;
-
-        /*
-         * Mark the device as detached to avoid processing
-         * interrupts until setup is complete.
-         */
-        __set_bit(ATH_STAT_INVALID, sc->status);
-
-        sc->iobase = mem; /* So we can unmap it on detach */
-        sc->opmode = NL80211_IFTYPE_STATION;
-        sc->bintval = 1000;
-        mutex_init(&sc->lock);
-        spin_lock_init(&sc->rxbuflock);
-        spin_lock_init(&sc->txbuflock);
-        spin_lock_init(&sc->block);
-
-        /* Set private data */
-        pci_set_drvdata(pdev, sc);
-
-        /* Setup interrupt handler */
-        ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
-        if (ret) {
-                ATH5K_ERR(sc, "request_irq failed\n");
-                goto err_free;
-        }
-
-        /* If we passed the test, malloc an ath5k_hw struct */
-        sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
-        if (!sc->ah) {
-                ret = -ENOMEM;
-                ATH5K_ERR(sc, "out of memory\n");
-                goto err_irq;
-        }
-
-        sc->ah->ah_sc = sc;
-        sc->ah->ah_iobase = sc->iobase;
-        common = ath5k_hw_common(sc->ah);
-        common->ops = &ath5k_common_ops;
-        common->ah = sc->ah;
-        common->hw = hw;
-        common->cachelsz = csz << 2; /* convert to bytes */
-        spin_lock_init(&common->cc_lock);
-
-        /* Initialize device */
-        ret = ath5k_hw_attach(sc);
-        if (ret) {
-                goto err_free_ah;
-        }
-
-        /* set up multi-rate retry capabilities */
-        if (sc->ah->ah_version == AR5K_AR5212) {
-                hw->max_rates = 4;
-                hw->max_rate_tries = 11;
-        }
-
-        hw->vif_data_size = sizeof(struct ath5k_vif);
-
-        /* Finish private driver data initialization */
-        ret = ath5k_attach(pdev, hw);
-        if (ret)
-                goto err_ah;
-
-        ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
-                        ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
-                                        sc->ah->ah_mac_srev,
-                                        sc->ah->ah_phy_revision);
-
-        if (!sc->ah->ah_single_chip) {
-                /* Single chip radio (!RF5111) */
-                if (sc->ah->ah_radio_5ghz_revision &&
-                        !sc->ah->ah_radio_2ghz_revision) {
-                        /* No 5GHz support -> report 2GHz radio */
-                        if (!test_bit(AR5K_MODE_11A,
-                                sc->ah->ah_capabilities.cap_mode)) {
-                                ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
-                                        ath5k_chip_name(AR5K_VERSION_RAD,
-                                                sc->ah->ah_radio_5ghz_revision),
-                                                sc->ah->ah_radio_5ghz_revision);
-                        /* No 2GHz support (5110 and some
-                         * 5Ghz only cards) -> report 5Ghz radio */
-                        } else if (!test_bit(AR5K_MODE_11B,
-                                sc->ah->ah_capabilities.cap_mode)) {
-                                ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
-                                        ath5k_chip_name(AR5K_VERSION_RAD,
-                                                sc->ah->ah_radio_5ghz_revision),
-                                                sc->ah->ah_radio_5ghz_revision);
-                        /* Multiband radio */
-                        } else {
-                                ATH5K_INFO(sc, "RF%s multiband radio found"
-                                        " (0x%x)\n",
-                                        ath5k_chip_name(AR5K_VERSION_RAD,
-                                                sc->ah->ah_radio_5ghz_revision),
-                                                sc->ah->ah_radio_5ghz_revision);
-                        }
-                }
-                /* Multi chip radio (RF5111 - RF2111) ->
-                 * report both 2GHz/5GHz radios */
-                else if (sc->ah->ah_radio_5ghz_revision &&
-                                sc->ah->ah_radio_2ghz_revision){
-                        ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
-                                ath5k_chip_name(AR5K_VERSION_RAD,
-                                        sc->ah->ah_radio_5ghz_revision),
-                                        sc->ah->ah_radio_5ghz_revision);
-                        ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
-                                ath5k_chip_name(AR5K_VERSION_RAD,
-                                        sc->ah->ah_radio_2ghz_revision),
-                                        sc->ah->ah_radio_2ghz_revision);
-                }
-        }
-
-        ath5k_debug_init_device(sc);
-
-        /* ready to process interrupts */
-        __clear_bit(ATH_STAT_INVALID, sc->status);
-
-        return 0;
-err_ah:
-        ath5k_hw_detach(sc->ah);
-err_free_ah:
-        kfree(sc->ah);
-err_irq:
-        free_irq(pdev->irq, sc);
-err_free:
-        ieee80211_free_hw(hw);
-err_map:
-        pci_iounmap(pdev, mem);
-err_reg:
-        pci_release_region(pdev, 0);
-err_dis:
-        pci_disable_device(pdev);
-err:
-        return ret;
-}
-
-static void __devexit
-ath5k_pci_remove(struct pci_dev *pdev)
-{
-        struct ath5k_softc *sc = pci_get_drvdata(pdev);
-
-        ath5k_debug_finish_device(sc);
-        ath5k_detach(pdev, sc->hw);
-        ath5k_hw_detach(sc->ah);
-        kfree(sc->ah);
-        free_irq(pdev->irq, sc);
-        pci_iounmap(pdev, sc->iobase);
-        pci_release_region(pdev, 0);
-        pci_disable_device(pdev);
-        ieee80211_free_hw(sc->hw);
-}
-
-#ifdef CONFIG_PM_SLEEP
-static int ath5k_pci_suspend(struct device *dev)
-{
-        struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
-
-        ath5k_led_off(sc);
-        return 0;
-}
-
-static int ath5k_pci_resume(struct device *dev)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        struct ath5k_softc *sc = pci_get_drvdata(pdev);
-
-        /*
-         * Suspend/Resume resets the PCI configuration space, so we have to
-         * re-disable the RETRY_TIMEOUT register (0x41) to keep
-         * PCI Tx retries from interfering with C3 CPU state
-         */
-        pci_write_config_byte(pdev, 0x41, 0);
-
-        ath5k_led_enable(sc);
-        return 0;
-}
-
-static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
-#define ATH5K_PM_OPS    (&ath5k_pm_ops)
-#else
-#define ATH5K_PM_OPS    NULL
-#endif /* CONFIG_PM_SLEEP */
-
-static struct pci_driver ath5k_pci_driver = {
-        .name           = KBUILD_MODNAME,
-        .id_table       = ath5k_pci_id_table,
-        .probe          = ath5k_pci_probe,
-        .remove         = __devexit_p(ath5k_pci_remove),
-        .driver.pm      = ATH5K_PM_OPS,
-};
-
-/*
- * Module init/exit functions
- */
-static int __init
-init_ath5k_pci(void)
-{
-        int ret;
-
-        ret = pci_register_driver(&ath5k_pci_driver);
-        if (ret) {
-                printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
-                return ret;
-        }
-
-        return 0;
-}
-
-static void __exit
-exit_ath5k_pci(void)
-{
-        pci_unregister_driver(&ath5k_pci_driver);
-}
-
-module_init(init_ath5k_pci);
-module_exit(exit_ath5k_pci);
diff --git a/drivers/net/wireless/ath/ath5k/base.h b/drivers/net/wireless/ath/ath5k/base.h
index 9a79773cdc2a..6d511476e4d2 100644
--- a/drivers/net/wireless/ath/ath5k/base.h
+++ b/drivers/net/wireless/ath/ath5k/base.h
@@ -169,7 +169,10 @@ struct ath5k_vif {
 /* Software Carrier, keeps track of the driver state
  * associated with an instance of a device */
 struct ath5k_softc {
-        struct pci_dev          *pdev;          /* for dma mapping */
+        struct pci_dev          *pdev;
+        struct device           *dev;           /* for dma mapping */
+        int irq;
+        u16 devid;
         void __iomem            *iobase;        /* address of the device */
         struct mutex            lock;           /* dev-level lock */
         struct ieee80211_hw     *hw;            /* IEEE 802.11 common */
@@ -255,6 +258,8 @@ struct ath5k_softc {
         struct tasklet_struct   ani_tasklet;    /* ANI calibration */
 
         struct delayed_work     tx_complete_work;
+
+        struct survey_info      survey;         /* collected survey info */
 };
 
 #define ath5k_hw_hasbssidmask(_ah) \
diff --git a/drivers/net/wireless/ath/ath5k/caps.c b/drivers/net/wireless/ath/ath5k/caps.c
index beae519aa735..31cad80e9b01 100644
--- a/drivers/net/wireless/ath/ath5k/caps.c
+++ b/drivers/net/wireless/ath/ath5k/caps.c
@@ -49,7 +49,6 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
 
                 /* Set supported modes */
                 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
-                __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
         } else {
                 /*
                  * XXX The tranceiver supports frequencies from 4920 to 6100GHz
@@ -74,11 +73,6 @@ int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
                         /* Set supported modes */
                         __set_bit(AR5K_MODE_11A,
                                         ah->ah_capabilities.cap_mode);
-                        __set_bit(AR5K_MODE_11A_TURBO,
-                                        ah->ah_capabilities.cap_mode);
-                        if (ah->ah_version == AR5K_AR5212)
-                                __set_bit(AR5K_MODE_11G_TURBO,
-                                                ah->ah_capabilities.cap_mode);
                 }
 
                 /* Enable  802.11b if a 2GHz capable radio (2111/5112) is
diff --git a/drivers/net/wireless/ath/ath5k/debug.c b/drivers/net/wireless/ath/ath5k/debug.c
index acda56ee521b..d2f84d76bb07 100644
--- a/drivers/net/wireless/ath/ath5k/debug.c
+++ b/drivers/net/wireless/ath/ath5k/debug.c
@@ -60,7 +60,6 @@
 
 #include "base.h"
 #include "debug.h"
-#include "../debug.h"
 
 static unsigned int ath5k_debug;
 module_param_named(debug, ath5k_debug, uint, 0);
@@ -312,6 +311,7 @@ static const struct {
         { ATH5K_DEBUG_DUMP_RX,  "dumprx",       "print received skb content" },
         { ATH5K_DEBUG_DUMP_TX,  "dumptx",       "print transmit skb content" },
         { ATH5K_DEBUG_DUMPBANDS, "dumpbands",   "dump bands" },
+        { ATH5K_DEBUG_DMA,      "dma",          "dma start/stop" },
         { ATH5K_DEBUG_ANI,      "ani",          "adaptive noise immunity" },
         { ATH5K_DEBUG_DESC,     "desc",         "descriptor chains" },
         { ATH5K_DEBUG_ANY,      "all",          "show all debug levels" },
@@ -554,63 +554,63 @@ static ssize_t read_file_frameerrors(struct file *file, char __user *user_buf,
 
         len += snprintf(buf+len, sizeof(buf)-len,
                         "RX\n---------------------\n");
-        len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "CRC\t%u\t(%u%%)\n",
                         st->rxerr_crc,
                         st->rx_all_count > 0 ?
                                 st->rxerr_crc*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "PHY\t%u\t(%u%%)\n",
                         st->rxerr_phy,
                         st->rx_all_count > 0 ?
                                 st->rxerr_phy*100/st->rx_all_count : 0);
         for (i = 0; i < 32; i++) {
                 if (st->rxerr_phy_code[i])
                         len += snprintf(buf+len, sizeof(buf)-len,
-                                " phy_err[%d]\t%d\n",
+                                " phy_err[%u]\t%u\n",
                                 i, st->rxerr_phy_code[i]);
         }
 
-        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n",
                         st->rxerr_fifo,
                         st->rx_all_count > 0 ?
                                 st->rxerr_fifo*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "decrypt\t%u\t(%u%%)\n",
                         st->rxerr_decrypt,
                         st->rx_all_count > 0 ?
                                 st->rxerr_decrypt*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "MIC\t%u\t(%u%%)\n",
                         st->rxerr_mic,
                         st->rx_all_count > 0 ?
                                 st->rxerr_mic*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "process\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "process\t%u\t(%u%%)\n",
                         st->rxerr_proc,
                         st->rx_all_count > 0 ?
                                 st->rxerr_proc*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "jumbo\t%u\t(%u%%)\n",
                         st->rxerr_jumbo,
                         st->rx_all_count > 0 ?
                                 st->rxerr_jumbo*100/st->rx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%d]\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "[RX all\t%u]\n",
                         st->rx_all_count);
-        len += snprintf(buf+len, sizeof(buf)-len, "RX-all-bytes\t%d\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "RX-all-bytes\t%u\n",
                         st->rx_bytes_count);
 
         len += snprintf(buf+len, sizeof(buf)-len,
                         "\nTX\n---------------------\n");
-        len += snprintf(buf+len, sizeof(buf)-len, "retry\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "retry\t%u\t(%u%%)\n",
                         st->txerr_retry,
                         st->tx_all_count > 0 ?
                                 st->txerr_retry*100/st->tx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "FIFO\t%u\t(%u%%)\n",
                         st->txerr_fifo,
                         st->tx_all_count > 0 ?
                                 st->txerr_fifo*100/st->tx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "filter\t%d\t(%d%%)\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "filter\t%u\t(%u%%)\n",
                         st->txerr_filt,
                         st->tx_all_count > 0 ?
                                 st->txerr_filt*100/st->tx_all_count : 0);
-        len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%d]\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "[TX all\t%u]\n",
                         st->tx_all_count);
-        len += snprintf(buf+len, sizeof(buf)-len, "TX-all-bytes\t%d\n",
+        len += snprintf(buf+len, sizeof(buf)-len, "TX-all-bytes\t%u\n",
                         st->tx_bytes_count);
 
         if (len > sizeof(buf))
@@ -719,7 +719,7 @@ static ssize_t read_file_ani(struct file *file, char __user *user_buf,
                         st->mib_intr);
         len += snprintf(buf+len, sizeof(buf)-len,
                         "beacon RSSI average:\t%d\n",
-                        sc->ah->ah_beacon_rssi_avg.avg);
+                        (int)ewma_read(&sc->ah->ah_beacon_rssi_avg));
 
 #define CC_PRINT(_struct, _field) \
         _struct._field, \
diff --git a/drivers/net/wireless/ath/ath5k/debug.h b/drivers/net/wireless/ath/ath5k/debug.h
index 236edbd2507d..3e34428d5126 100644
--- a/drivers/net/wireless/ath/ath5k/debug.h
+++ b/drivers/net/wireless/ath/ath5k/debug.h
@@ -95,6 +95,7 @@ struct ath5k_dbg_info {
  * @ATH5K_DEBUG_DUMP_RX: print received skb content
  * @ATH5K_DEBUG_DUMP_TX: print transmit skb content
  * @ATH5K_DEBUG_DUMPBANDS: dump bands
+ * @ATH5K_DEBUG_DMA: debug dma start/stop
  * @ATH5K_DEBUG_TRACE: trace function calls
  * @ATH5K_DEBUG_DESC: descriptor setup
  * @ATH5K_DEBUG_ANY: show at any debug level
@@ -118,6 +119,7 @@ enum ath5k_debug_level {
         ATH5K_DEBUG_DUMP_RX     = 0x00000100,
         ATH5K_DEBUG_DUMP_TX     = 0x00000200,
         ATH5K_DEBUG_DUMPBANDS   = 0x00000400,
+        ATH5K_DEBUG_DMA         = 0x00000800,
         ATH5K_DEBUG_ANI         = 0x00002000,
         ATH5K_DEBUG_DESC        = 0x00004000,
         ATH5K_DEBUG_ANY         = 0xffffffff
diff --git a/drivers/net/wireless/ath/ath5k/desc.c b/drivers/net/wireless/ath/ath5k/desc.c
index 43244382f213..16b44ff7dd3e 100644
--- a/drivers/net/wireless/ath/ath5k/desc.c
+++ b/drivers/net/wireless/ath/ath5k/desc.c
@@ -26,9 +26,10 @@
 #include "debug.h"
 #include "base.h"
 
-/*
- * TX Descriptors
- */
+
+/************************\
+* TX Control descriptors *
+\************************/
 
 /*
  * Initialize the 2-word tx control descriptor on 5210/5211
@@ -335,6 +336,11 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
         return 0;
 }
 
+
+/***********************\
+* TX Status descriptors *
+\***********************/
+
 /*
  * Proccess the tx status descriptor on 5210/5211
  */
@@ -476,9 +482,10 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
         return 0;
 }
 
-/*
- * RX Descriptors
- */
+
+/****************\
+* RX Descriptors *
+\****************/
 
 /*
  * Initialize an rx control descriptor
@@ -666,6 +673,11 @@ static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
         return 0;
 }
 
+
+/********\
+* Attach *
+\********/
+
 /*
  * Init function pointers inside ath5k_hw struct
  */
diff --git a/drivers/net/wireless/ath/ath5k/desc.h b/drivers/net/wireless/ath/ath5k/desc.h
index b2adb2a281c2..2509d0bf037d 100644
--- a/drivers/net/wireless/ath/ath5k/desc.h
+++ b/drivers/net/wireless/ath/ath5k/desc.h
@@ -26,7 +26,7 @@
 struct ath5k_hw_rx_ctl {
         u32     rx_control_0; /* RX control word 0 */
         u32     rx_control_1; /* RX control word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* RX control word 1 fields/flags */
 #define AR5K_DESC_RX_CTL1_BUF_LEN               0x00000fff /* data buffer length */
@@ -39,7 +39,7 @@ struct ath5k_hw_rx_ctl {
 struct ath5k_hw_rx_status {
         u32     rx_status_0; /* RX status word 0 */
         u32     rx_status_1; /* RX status word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* 5210/5211 */
 /* RX status word 0 fields/flags */
@@ -129,7 +129,7 @@ enum ath5k_phy_error_code {
 struct ath5k_hw_2w_tx_ctl {
         u32     tx_control_0; /* TX control word 0 */
         u32     tx_control_1; /* TX control word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* TX control word 0 fields/flags */
 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN          0x00000fff /* frame length */
@@ -185,7 +185,7 @@ struct ath5k_hw_4w_tx_ctl {
         u32     tx_control_1; /* TX control word 1 */
         u32     tx_control_2; /* TX control word 2 */
         u32     tx_control_3; /* TX control word 3 */
-} __packed;
+} __packed __aligned(4);
 
 /* TX control word 0 fields/flags */
 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN          0x00000fff /* frame length */
@@ -244,7 +244,7 @@ struct ath5k_hw_4w_tx_ctl {
 struct ath5k_hw_tx_status {
         u32     tx_status_0; /* TX status word 0 */
         u32     tx_status_1; /* TX status word 1 */
-} __packed;
+} __packed __aligned(4);
 
 /* TX status word 0 fields/flags */
 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK      0x00000001 /* TX success */
@@ -282,7 +282,7 @@ struct ath5k_hw_tx_status {
 struct ath5k_hw_5210_tx_desc {
         struct ath5k_hw_2w_tx_ctl       tx_ctl;
         struct ath5k_hw_tx_status       tx_stat;
-} __packed;
+} __packed __aligned(4);
 
 /*
  * 5212 hardware TX descriptor
@@ -290,7 +290,7 @@ struct ath5k_hw_5210_tx_desc {
 struct ath5k_hw_5212_tx_desc {
         struct ath5k_hw_4w_tx_ctl       tx_ctl;
         struct ath5k_hw_tx_status       tx_stat;
-} __packed;
+} __packed __aligned(4);
 
 /*
  * Common hardware RX descriptor
@@ -298,7 +298,7 @@ struct ath5k_hw_5212_tx_desc {
 struct ath5k_hw_all_rx_desc {
         struct ath5k_hw_rx_ctl          rx_ctl;
         struct ath5k_hw_rx_status       rx_stat;
-} __packed;
+} __packed __aligned(4);
 
 /*
  * Atheros hardware DMA descriptor
@@ -313,7 +313,7 @@ struct ath5k_desc {
                 struct ath5k_hw_5212_tx_desc    ds_tx5212;
                 struct ath5k_hw_all_rx_desc     ds_rx;
         } ud;
-} __packed;
+} __packed __aligned(4);
 
 #define AR5K_RXDESC_INTREQ      0x0020
 
diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index 923c9ca5c4f0..0064be7ce5c9 100644
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -37,6 +37,7 @@
 #include "debug.h"
 #include "base.h"
 
+
 /*********\
 * Receive *
 \*********/
@@ -57,7 +58,7 @@ void ath5k_hw_start_rx_dma(struct ath5k_hw *ah)
  *
  * @ah: The &struct ath5k_hw
  */
-int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
+static int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
 {
         unsigned int i;
 
@@ -69,7 +70,11 @@ int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
         for (i = 1000; i > 0 &&
                         (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
                         i--)
-                udelay(10);
+                udelay(100);
+
+        if (!i)
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "failed to stop RX DMA !\n");
 
         return i ? 0 : -EBUSY;
 }
@@ -90,11 +95,18 @@ u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah)
  * @ah: The &struct ath5k_hw
  * @phys_addr: RX descriptor address
  *
- * XXX: Should we check if rx is enabled before setting rxdp ?
+ * Returns -EIO if rx is active
  */
-void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
+int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr)
 {
+        if (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) {
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "tried to set RXDP while rx was active !\n");
+                return -EIO;
+        }
+
         ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
+        return 0;
 }
 
 
@@ -125,7 +137,7 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 
         /* Return if queue is declared inactive */
         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return -EIO;
+                return -EINVAL;
 
         if (ah->ah_version == AR5K_AR5210) {
                 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
@@ -173,10 +185,10 @@ int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)
  *
  * Stop DMA transmit on a specific hw queue and drain queue so we don't
  * have any pending frames. Returns -EBUSY if we still have pending frames,
- * -EINVAL if queue number is out of range.
+ * -EINVAL if queue number is out of range or inactive.
  *
  */
-int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
+static int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 {
         unsigned int i = 40;
         u32 tx_queue, pending;
@@ -185,7 +197,7 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 
         /* Return if queue is declared inactive */
         if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return -EIO;
+                return -EINVAL;
 
         if (ah->ah_version == AR5K_AR5210) {
                 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
@@ -211,12 +223,31 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
                 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
                 ath5k_hw_reg_read(ah, AR5K_CR);
         } else {
+
+                /*
+                 * Enable DCU early termination to quickly
+                 * flush any pending frames from QCU
+                 */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_DCU_EARLY);
+
                 /*
                  * Schedule TX disable and wait until queue is empty
                  */
                 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
 
-                /*Check for pending frames*/
+                /* Wait for queue to stop */
+                for (i = 1000; i > 0 &&
+                (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);
+                i--)
+                        udelay(100);
+
+                if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "queue %i didn't stop !\n", queue);
+
+                /* Check for pending frames */
+                i = 1000;
                 do {
                         pending = ath5k_hw_reg_read(ah,
                                 AR5K_QUEUE_STATUS(queue)) &
@@ -247,12 +278,12 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
                                         AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
 
                         /* Wait a while and disable mechanism */
-                        udelay(200);
+                        udelay(400);
                         AR5K_REG_DISABLE_BITS(ah, AR5K_QUIET_CTL1,
                                                 AR5K_QUIET_CTL1_QT_EN);
 
                         /* Re-check for pending frames */
-                        i = 40;
+                        i = 100;
                         do {
                                 pending = ath5k_hw_reg_read(ah,
                                         AR5K_QUEUE_STATUS(queue)) &
@@ -262,12 +293,27 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 
                         AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5211,
                                         AR5K_DIAG_SW_CHANNEL_IDLE_HIGH);
+
+                        if (pending)
+                                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                        "quiet mechanism didn't work q:%i !\n",
+                                        queue);
                 }
 
+                /*
+                 * Disable DCU early termination
+                 */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_DCU_EARLY);
+
                 /* Clear register */
                 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
-                if (pending)
+                if (pending) {
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                        "tx dma didn't stop (q:%i, frm:%i) !\n",
+                                        queue, pending);
                         return -EBUSY;
+                }
         }
 
         /* TODO: Check for success on 5210 else return error */
@@ -275,6 +321,26 @@ int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
 }
 
 /**
+ * ath5k_hw_stop_beacon_queue - Stop beacon queue
+ *
+ * @ah The &struct ath5k_hw
+ * @queue The queue number
+ *
+ * Returns -EIO if queue didn't stop
+ */
+int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)
+{
+        int ret;
+        ret = ath5k_hw_stop_tx_dma(ah, queue);
+        if (ret) {
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_DMA,
+                                "beacon queue didn't stop !\n");
+                return -EIO;
+        }
+        return 0;
+}
+
+/**
  * ath5k_hw_get_txdp - Get TX Descriptor's address for a specific queue
  *
  * @ah: The &struct ath5k_hw
@@ -427,6 +493,7 @@ done:
         return ret;
 }
 
+
 /*******************\
 * Interrupt masking *
 \*******************/
@@ -688,3 +755,92 @@ enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask)
         return old_mask;
 }
 
+
+/********************\
+ Init/Stop functions
+\********************/
+
+/**
+ * ath5k_hw_dma_init - Initialize DMA unit
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Set DMA size and pre-enable interrupts
+ * (driver handles tx/rx buffer setup and
+ * dma start/stop)
+ *
+ * XXX: Save/restore RXDP/TXDP registers ?
+ */
+void ath5k_hw_dma_init(struct ath5k_hw *ah)
+{
+        /*
+         * Set Rx/Tx DMA Configuration
+         *
+         * Set standard DMA size (128). Note that
+         * a DMA size of 512 causes rx overruns and tx errors
+         * on pci-e cards (tested on 5424 but since rx overruns
+         * also occur on 5416/5418 with madwifi we set 128
+         * for all PCI-E cards to be safe).
+         *
+         * XXX: need to check 5210 for this
+         * TODO: Check out tx triger level, it's always 64 on dumps but I
+         * guess we can tweak it and see how it goes ;-)
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
+                        AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
+                AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
+                        AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
+        }
+
+        /* Pre-enable interrupts on 5211/5212*/
+        if (ah->ah_version != AR5K_AR5210)
+                ath5k_hw_set_imr(ah, ah->ah_imr);
+
+}
+
+/**
+ * ath5k_hw_dma_stop - stop DMA unit
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Stop tx/rx DMA and interrupts. Returns
+ * -EBUSY if tx or rx dma failed to stop.
+ *
+ * XXX: Sometimes DMA unit hangs and we have
+ * stuck frames on tx queues, only a reset
+ * can fix that.
+ */
+int ath5k_hw_dma_stop(struct ath5k_hw *ah)
+{
+        int i, qmax, err;
+        err = 0;
+
+        /* Disable interrupts */
+        ath5k_hw_set_imr(ah, 0);
+
+        /* Stop rx dma */
+        err = ath5k_hw_stop_rx_dma(ah);
+        if (err)
+                return err;
+
+        /* Clear any pending interrupts
+         * and disable tx dma */
+        if (ah->ah_version != AR5K_AR5210) {
+                ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
+                qmax = AR5K_NUM_TX_QUEUES;
+        } else {
+                /* PISR/SISR Not available on 5210 */
+                ath5k_hw_reg_read(ah, AR5K_ISR);
+                qmax = AR5K_NUM_TX_QUEUES_NOQCU;
+        }
+
+        for (i = 0; i < qmax; i++) {
+                err = ath5k_hw_stop_tx_dma(ah, i);
+                /* -EINVAL -> queue inactive */
+                if (err != -EINVAL)
+                        return err;
+        }
+
+        return err;
+}
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c
index 39722dd73e43..80e625608bac 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.c
+++ b/drivers/net/wireless/ath/ath5k/eeprom.c
@@ -28,45 +28,16 @@
 #include "debug.h"
 #include "base.h"
 
-/*
- * Read from eeprom
- */
-static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
-{
-        u32 status, timeout;
-
-        /*
-         * Initialize EEPROM access
-         */
-        if (ah->ah_version == AR5K_AR5210) {
-                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
-                (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
-        } else {
-                ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
-                AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
-                                AR5K_EEPROM_CMD_READ);
-        }
-
-        for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
-                status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
-                if (status & AR5K_EEPROM_STAT_RDDONE) {
-                        if (status & AR5K_EEPROM_STAT_RDERR)
-                                return -EIO;
-                        *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
-                                        0xffff);
-                        return 0;
-                }
-                udelay(15);
-        }
 
-        return -ETIMEDOUT;
-}
+/******************\
+* Helper functions *
+\******************/
 
 /*
  * Translate binary channel representation in EEPROM to frequency
  */
 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
-                                 unsigned int mode)
+                                                        unsigned int mode)
 {
         u16 val;
 
@@ -89,6 +60,11 @@ static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
         return val;
 }
 
+
+/*********\
+* Parsers *
+\*********/
+
 /*
  * Initialize eeprom & capabilities structs
  */
@@ -198,7 +174,7 @@ ath5k_eeprom_init_header(struct ath5k_hw *ah)
          *
          * XXX: Serdes values seem to be fixed so
          * no need to read them here, we write them
-         * during ath5k_hw_attach */
+         * during ath5k_hw_init */
         AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
         ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
                                                         true : false;
@@ -647,6 +623,7 @@ ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
         return 0;
 }
 
+
 /*
  * Read power calibration for RF5111 chips
  *
@@ -1514,6 +1491,7 @@ ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
         return 0;
 }
 
+
 /*
  * Read per channel calibration info from EEPROM
  *
@@ -1607,15 +1585,6 @@ ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
         return 0;
 }
 
-void
-ath5k_eeprom_detach(struct ath5k_hw *ah)
-{
-        u8 mode;
-
-        for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
-                ath5k_eeprom_free_pcal_info(ah, mode);
-}
-
 /* Read conformance test limits used for regulatory control */
 static int
 ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
@@ -1757,6 +1726,44 @@ ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
 }
 
 /*
+ * Read the MAC address from eeprom
+ */
+int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
+{
+        u8 mac_d[ETH_ALEN] = {};
+        u32 total, offset;
+        u16 data;
+        int octet, ret;
+
+        ret = ath5k_hw_nvram_read(ah, 0x20, &data);
+        if (ret)
+                return ret;
+
+        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
+                ret = ath5k_hw_nvram_read(ah, offset, &data);
+                if (ret)
+                        return ret;
+
+                total += data;
+                mac_d[octet + 1] = data & 0xff;
+                mac_d[octet] = data >> 8;
+                octet += 2;
+        }
+
+        if (!total || total == 3 * 0xffff)
+                return -EINVAL;
+
+        memcpy(mac, mac_d, ETH_ALEN);
+
+        return 0;
+}
+
+
+/***********************\
+* Init/Detach functions *
+\***********************/
+
+/*
  * Initialize eeprom data structure
  */
 int
@@ -1787,35 +1794,27 @@ ath5k_eeprom_init(struct ath5k_hw *ah)
         return 0;
 }
 
-/*
- * Read the MAC address from eeprom
- */
-int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
+void
+ath5k_eeprom_detach(struct ath5k_hw *ah)
 {
-        u8 mac_d[ETH_ALEN] = {};
-        u32 total, offset;
-        u16 data;
-        int octet, ret;
-
-        ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
-        if (ret)
-                return ret;
+        u8 mode;
 
-        for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
-                ret = ath5k_hw_eeprom_read(ah, offset, &data);
-                if (ret)
-                        return ret;
+        for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
+                ath5k_eeprom_free_pcal_info(ah, mode);
+}
 
-                total += data;
-                mac_d[octet + 1] = data & 0xff;
-                mac_d[octet] = data >> 8;
-                octet += 2;
+int
+ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel)
+{
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+        case CHANNEL_XR:
+                return AR5K_EEPROM_MODE_11A;
+        case CHANNEL_G:
+                return AR5K_EEPROM_MODE_11G;
+        case CHANNEL_B:
+                return AR5K_EEPROM_MODE_11B;
+        default:
+                return -1;
         }
-
-        if (!total || total == 3 * 0xffff)
-                return -EINVAL;
-
-        memcpy(mac, mac_d, ETH_ALEN);
-
-        return 0;
 }
diff --git a/drivers/net/wireless/ath/ath5k/eeprom.h b/drivers/net/wireless/ath/ath5k/eeprom.h
index c4a6d5f26af4..7c09e150dbdc 100644
--- a/drivers/net/wireless/ath/ath5k/eeprom.h
+++ b/drivers/net/wireless/ath/ath5k/eeprom.h
@@ -241,7 +241,7 @@ enum ath5k_eeprom_freq_bands{
 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz      6250
 
 #define AR5K_EEPROM_READ(_o, _v) do {                   \
-        ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
+        ret = ath5k_hw_nvram_read(ah, (_o), &(_v));     \
         if (ret)                                        \
                 return ret;                             \
 } while (0)
@@ -517,3 +517,5 @@ struct ath5k_eeprom_info {
         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 };
 
+int
+ath5k_eeprom_mode_from_channel(struct ieee80211_channel *channel);
diff --git a/drivers/net/wireless/ath/ath5k/initvals.c b/drivers/net/wireless/ath/ath5k/initvals.c
index 8fa439308828..e49340d18df4 100644
--- a/drivers/net/wireless/ath/ath5k/initvals.c
+++ b/drivers/net/wireless/ath/ath5k/initvals.c
@@ -44,7 +44,7 @@ struct ath5k_ini {
 
 struct ath5k_ini_mode {
         u16     mode_register;
-        u32     mode_value[5];
+        u32     mode_value[3];
 };
 
 /* Initial register settings for AR5210 */
@@ -391,76 +391,74 @@ static const struct ath5k_ini ar5211_ini[] = {
  */
 static const struct ath5k_ini_mode ar5211_ini_mode[] = {
         { AR5K_TXCFG,
-        /*        a         aTurbo        b       g (OFDM)    */
-           { 0x00000015, 0x00000015, 0x0000001d, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x0000001d, 0x00000015 } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_DCU_GBL_IFS_SLOT,
-           { 0x00000168, 0x000001e0, 0x000001b8, 0x00000168 } },
+           { 0x00000168, 0x000001b8, 0x00000168 } },
         { AR5K_DCU_GBL_IFS_SIFS,
-           { 0x00000230, 0x000001e0, 0x000000b0, 0x00000230 } },
+           { 0x00000230, 0x000000b0, 0x00000230 } },
         { AR5K_DCU_GBL_IFS_EIFS,
-           { 0x00000d98, 0x00001180, 0x00001f48, 0x00000d98 } },
+           { 0x00000d98, 0x00001f48, 0x00000d98 } },
         { AR5K_DCU_GBL_IFS_MISC,
-           { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000a0e0 } },
+           { 0x0000a0e0, 0x00005880, 0x0000a0e0 } },
         { AR5K_TIME_OUT,
-           { 0x04000400, 0x08000800, 0x20003000, 0x04000400 } },
+           { 0x04000400, 0x20003000, 0x04000400 } },
         { AR5K_USEC_5211,
-           { 0x0e8d8fa7, 0x0e8d8fcf, 0x01608f95, 0x0e8d8fa7 } },
-        { AR5K_PHY_TURBO,
-           { 0x00000000, 0x00000003, 0x00000000, 0x00000000 } },
+           { 0x0e8d8fa7, 0x01608f95, 0x0e8d8fa7 } },
         { AR5K_PHY(8),
-           { 0x02020200, 0x02020200, 0x02010200, 0x02020200 } },
-        { AR5K_PHY(9),
-           { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e } },
-        { AR5K_PHY(10),
-           { 0x0a020001, 0x0a020001, 0x05010000, 0x0a020001 } },
-        { AR5K_PHY(13),
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
-        { AR5K_PHY(14),
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b } },
-        { AR5K_PHY(17),
-           { 0x1372169c, 0x137216a5, 0x137216a8, 0x1372169c } },
-        { AR5K_PHY(18),
-           { 0x0018ba67, 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
-        { AR5K_PHY(20),
-           { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
+           { 0x02020200, 0x02010200, 0x02020200 } },
+        { AR5K_PHY_RF_CTL2,
+           { 0x00000e0e, 0x00000707, 0x00000e0e } },
+        { AR5K_PHY_RF_CTL3,
+           { 0x0a020001, 0x05010000, 0x0a020001 } },
+        { AR5K_PHY_RF_CTL4,
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+        { AR5K_PHY_PA_CTL,
+           { 0x00000007, 0x0000000b, 0x0000000b } },
+        { AR5K_PHY_SETTLING,
+           { 0x1372169c, 0x137216a8, 0x1372169c } },
+        { AR5K_PHY_GAIN,
+           { 0x0018ba67, 0x0018ba69, 0x0018ba69 } },
+        { AR5K_PHY_DESIRED_SIZE,
+           { 0x0c28b4e0, 0x0c28b4e0, 0x0c28b4e0 } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ec00d2e, 0x7e800d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x31375d5e, 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
+           { 0x31375d5e, 0x313a5d5e, 0x31375d5e } },
         { AR5K_PHY_AGCCTL,
-           { 0x0000bd10, 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
+           { 0x0000bd10, 0x0000bd38, 0x0000bd10 } },
         { AR5K_PHY_NF,
-           { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
+           { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x00002710, 0x00002710, 0x0000157c, 0x00002710 } },
+           { 0x00002710, 0x0000157c, 0x00002710 } },
         { AR5K_PHY(70),
-           { 0x00000190, 0x00000190, 0x00000084, 0x00000190 } },
+           { 0x00000190, 0x00000084, 0x00000190 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0x6fe01020, 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
+           { 0x6fe01020, 0x6fe00920, 0x6fe01020 } },
         { AR5K_PHY_PCDAC_TXPOWER_BASE,
-           { 0x05ff14ff, 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
+           { 0x05ff14ff, 0x05ff14ff, 0x05ff19ff } },
         { AR5K_RF_BUFFER_CONTROL_4,
-           { 0x00000010, 0x00000014, 0x00000010, 0x00000010 } },
+           { 0x00000010, 0x00000010, 0x00000010 } },
 };
 
 /* Initial register settings for AR5212 */
@@ -677,89 +675,87 @@ static const struct ath5k_ini ar5212_ini_common_start[] = {
 /* Initial mode-specific settings for AR5212 (Written before ar5212_ini) */
 static const struct ath5k_ini_mode ar5212_ini_mode_start[] = {
         { AR5K_QUEUE_DFS_LOCAL_IFS(0),
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+        /*      A/XR          B           G       */
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(1),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(2),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(3),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(4),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(5),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(6),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(7),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(8),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_QUEUE_DFS_LOCAL_IFS(9),
-           { 0x002ffc0f, 0x002ffc0f, 0x002ffc1f, 0x002ffc0f, 0x002ffc0f } },
+           { 0x002ffc0f, 0x002ffc1f, 0x002ffc0f } },
         { AR5K_DCU_GBL_IFS_SIFS,
-           { 0x00000230, 0x000001e0, 0x000000b0, 0x00000160, 0x000001e0 } },
+           { 0x00000230, 0x000000b0, 0x00000160 } },
         { AR5K_DCU_GBL_IFS_SLOT,
-           { 0x00000168, 0x000001e0, 0x000001b8, 0x0000018c, 0x000001e0 } },
+           { 0x00000168, 0x000001b8, 0x0000018c } },
         { AR5K_DCU_GBL_IFS_EIFS,
-           { 0x00000e60, 0x00001180, 0x00001f1c, 0x00003e38, 0x00001180 } },
+           { 0x00000e60, 0x00001f1c, 0x00003e38 } },
         { AR5K_DCU_GBL_IFS_MISC,
-           { 0x0000a0e0, 0x00014068, 0x00005880, 0x0000b0e0, 0x00014068 } },
+           { 0x0000a0e0, 0x00005880, 0x0000b0e0 } },
         { AR5K_TIME_OUT,
-           { 0x03e803e8, 0x06e006e0, 0x04200420, 0x08400840, 0x06e006e0 } },
-        { AR5K_PHY_TURBO,
-           { 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000003 } },
+           { 0x03e803e8, 0x04200420, 0x08400840 } },
         { AR5K_PHY(8),
-           { 0x02020200, 0x02020200, 0x02010200, 0x02020200, 0x02020200 } },
+           { 0x02020200, 0x02010200, 0x02020200 } },
         { AR5K_PHY_RF_CTL2,
-           { 0x00000e0e, 0x00000e0e, 0x00000707, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000707, 0x00000e0e } },
         { AR5K_PHY_SETTLING,
-           { 0x1372161c, 0x13721c25, 0x13721722, 0x137216a2, 0x13721c25 } },
+           { 0x1372161c, 0x13721722, 0x137216a2 } },
         { AR5K_PHY_AGCCTL,
-           { 0x00009d10, 0x00009d10, 0x00009d18, 0x00009d18, 0x00009d10 } },
+           { 0x00009d10, 0x00009d18, 0x00009d18 } },
         { AR5K_PHY_NF,
-           { 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
+           { 0x0001ce00, 0x0001ce00, 0x0001ce00 } },
         { AR5K_PHY_WEAK_OFDM_HIGH_THR,
-           { 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190 } },
+           { 0x409a4190, 0x409a4190, 0x409a4190 } },
         { AR5K_PHY(70),
-           { 0x000001b8, 0x000001b8, 0x00000084, 0x00000108, 0x000001b8 } },
+           { 0x000001b8, 0x00000084, 0x00000108 } },
         { AR5K_PHY_OFDM_SELFCORR,
-           { 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05, 0x10058a05 } },
+           { 0x10058a05, 0x10058a05, 0x10058a05 } },
         { 0xa230,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000108, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000108 } },
 };
 
 /* Initial mode-specific settings for AR5212 + RF5111 (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5111_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
+        /*      A/XR          B           G       */
+           { 0x00008015, 0x00008015, 0x00008015 } },
         { AR5K_USEC_5211,
-           { 0x128d8fa7, 0x09880fcf, 0x04e00f95, 0x12e00fab, 0x09880fcf } },
+           { 0x128d8fa7, 0x04e00f95, 0x12e00fab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05010100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05010100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000007, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_GAIN,
-           { 0x0018da5a, 0x0018da5a, 0x0018ca69, 0x0018ca69, 0x0018ca69 } },
+           { 0x0018da5a, 0x0018ca69, 0x0018ca69 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
+           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ee84d2e, 0x7ee84d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137615e } },
+           { 0x3137665e, 0x3137665e, 0x3137665e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb080, 0x050cb080 } },
+           { 0x050cb081, 0x050cb081, 0x050cb080 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x00002710, 0x00002710, 0x0000157c, 0x00002af8, 0x00002710 } },
+           { 0x00002710, 0x0000157c, 0x00002af8 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81020, 0xf7b81020, 0xf7b80d20, 0xf7b81020, 0xf7b81020 } },
+           { 0xf7b81020, 0xf7b80d20, 0xf7b81020 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x642c416a, 0x642c416a, 0x6440416a, 0x6440416a, 0x6440416a } },
+           { 0x642c416a, 0x6440416a, 0x6440416a } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1873800a, 0x1883800a } },
 };
 
 static const struct ath5k_ini rf5111_ini_common_end[] = {
@@ -782,38 +778,38 @@ static const struct ath5k_ini rf5111_ini_common_end[] = {
 /* Initial mode-specific settings for AR5212 + RF5112 (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5112_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00008015, 0x00008015, 0x00008015, 0x00008015, 0x00008015 } },
+        /*      A/XR          B           G       */
+           { 0x00008015, 0x00008015, 0x00008015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000007, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_GAIN,
-           { 0x0018da6d, 0x0018da6d, 0x0018ca75, 0x0018ca75, 0x0018ca75 } },
+           { 0x0018da6d, 0x0018ca75, 0x0018ca75 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
+           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b4e0 } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ee80d2e, 0x7ee80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e, 0x3137665e } },
+           { 0x3137665e, 0x3137665e, 0x3137665e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81020, 0xf7b81020, 0xf7b80d10, 0xf7b81010, 0xf7b81010 } },
+           { 0xf7b81020, 0xf7b80d10, 0xf7b81010 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000008, 0x00000008, 0x00000008 } },
+           { 0x00000000, 0x00000008, 0x00000008 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x642c0140, 0x642c0140, 0x6442c160, 0x6442c160, 0x6442c160 } },
+           { 0x642c0140, 0x6442c160, 0x6442c160 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1873800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1873800a, 0x1883800a } },
 };
 
 static const struct ath5k_ini rf5112_ini_common_end[] = {
@@ -833,66 +829,66 @@ static const struct ath5k_ini rf5112_ini_common_end[] = {
 /* Initial mode-specific settings for RF5413/5414 (Written after ar5212_ini) */
 static const struct ath5k_ini_mode rf5413_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x00000015, 0x00000015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000007, 0x00000007, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000007, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_GAIN,
-           { 0x0018fa61, 0x0018fa61, 0x001a1a63, 0x001a1a63, 0x001a1a63 } },
+           { 0x0018fa61, 0x001a1a63, 0x001a1a63 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
+           { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
         { AR5K_PHY_SIG,
-           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
+           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
+           { 0x3139605e, 0x3139605e, 0x3139605e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+           { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000000 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x002ec1e0, 0x002ec1e0, 0x002ac120, 0x002ac120, 0x002ac120 } },
+           { 0x002ec1e0, 0x002ac120, 0x002ac120 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1863800a, 0x1883800a } },
         { 0xa300,
-           { 0x18010000, 0x18010000, 0x18010000, 0x18010000, 0x18010000 } },
+           { 0x18010000, 0x18010000, 0x18010000 } },
         { 0xa304,
-           { 0x30032602, 0x30032602, 0x30032602, 0x30032602, 0x30032602 } },
+           { 0x30032602, 0x30032602, 0x30032602 } },
         { 0xa308,
-           { 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06, 0x48073e06 } },
+           { 0x48073e06, 0x48073e06, 0x48073e06 } },
         { 0xa30c,
-           { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
+           { 0x560b4c0a, 0x560b4c0a, 0x560b4c0a } },
         { 0xa310,
-           { 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f, 0x641a600f } },
+           { 0x641a600f, 0x641a600f, 0x641a600f } },
         { 0xa314,
-           { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
+           { 0x784f6e1b, 0x784f6e1b, 0x784f6e1b } },
         { 0xa318,
-           { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
+           { 0x868f7c5a, 0x868f7c5a, 0x868f7c5a } },
         { 0xa31c,
-           { 0x90cf865b, 0x90cf865b, 0x8ecf865b, 0x8ecf865b, 0x8ecf865b } },
+           { 0x90cf865b, 0x8ecf865b, 0x8ecf865b } },
         { 0xa320,
-           { 0x9d4f970f, 0x9d4f970f, 0x9b4f970f, 0x9b4f970f, 0x9b4f970f } },
+           { 0x9d4f970f, 0x9b4f970f, 0x9b4f970f } },
         { 0xa324,
-           { 0xa7cfa38f, 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f, 0xa3cf9f8f } },
+           { 0xa7cfa38f, 0xa3cf9f8f, 0xa3cf9f8f } },
         { 0xa328,
-           { 0xb55faf1f, 0xb55faf1f, 0xb35faf1f, 0xb35faf1f, 0xb35faf1f } },
+           { 0xb55faf1f, 0xb35faf1f, 0xb35faf1f } },
         { 0xa32c,
-           { 0xbddfb99f, 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f, 0xbbdfb99f } },
+           { 0xbddfb99f, 0xbbdfb99f, 0xbbdfb99f } },
         { 0xa330,
-           { 0xcb7fc53f, 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f, 0xcb7fc73f } },
+           { 0xcb7fc53f, 0xcb7fc73f, 0xcb7fc73f } },
         { 0xa334,
-           { 0xd5ffd1bf, 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
+           { 0xd5ffd1bf, 0xd3ffd1bf, 0xd3ffd1bf } },
 };
 
 static const struct ath5k_ini rf5413_ini_common_end[] = {
@@ -972,38 +968,38 @@ static const struct ath5k_ini rf5413_ini_common_end[] = {
 /* XXX: a mode ? */
 static const struct ath5k_ini_mode rf2413_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x00000015, 0x00000015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020000, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020000, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00, 0x00000e00 } },
+           { 0x00000e00, 0x00000e00, 0x00000e00 } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000002, 0x00000002, 0x0000000a, 0x0000000a, 0x0000000a } },
+           { 0x00000002, 0x0000000a, 0x0000000a } },
         { AR5K_PHY_GAIN,
-           { 0x0018da6d, 0x0018da6d, 0x001a6a64, 0x001a6a64, 0x001a6a64 } },
+           { 0x0018da6d, 0x001a6a64, 0x001a6a64 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0de8b4e0, 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da, 0x0de8b0da } },
+           { 0x0de8b4e0, 0x0de8b0da, 0x0c98b0da } },
         { AR5K_PHY_SIG,
-           { 0x7e800d2e, 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e, 0x7e800d2e } },
+           { 0x7e800d2e, 0x7ee80d2e, 0x7ec80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3137665e, 0x3137665e, 0x3137665e, 0x3139605e, 0x3137665e } },
+           { 0x3137665e, 0x3137665e, 0x3139605e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+           { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000000 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x002c0140, 0x002c0140, 0x0042c140, 0x0042c140, 0x0042c140 } },
+           { 0x002c0140, 0x0042c140, 0x0042c140 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1863800a, 0x1883800a } },
 };
 
 static const struct ath5k_ini rf2413_ini_common_end[] = {
@@ -1094,52 +1090,50 @@ static const struct ath5k_ini rf2413_ini_common_end[] = {
 /* XXX: a mode ? */
 static const struct ath5k_ini_mode rf2425_ini_mode_end[] = {
         { AR5K_TXCFG,
-        /*      a/XR       aTurbo         b        g (DYN)     gTurbo     */
-           { 0x00000015, 0x00000015, 0x00000015, 0x00000015, 0x00000015 } },
+        /*      A/XR          B           G       */
+           { 0x00000015, 0x00000015, 0x00000015 } },
         { AR5K_USEC_5211,
-           { 0x128d93a7, 0x098813cf, 0x04e01395, 0x12e013ab, 0x098813cf } },
-        { AR5K_PHY_TURBO,
-           { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000001 } },
+           { 0x128d93a7, 0x04e01395, 0x12e013ab } },
         { AR5K_PHY_RF_CTL3,
-           { 0x0a020001, 0x0a020001, 0x05020100, 0x0a020001, 0x0a020001 } },
+           { 0x0a020001, 0x05020100, 0x0a020001 } },
         { AR5K_PHY_RF_CTL4,
-           { 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e } },
+           { 0x00000e0e, 0x00000e0e, 0x00000e0e } },
         { AR5K_PHY_PA_CTL,
-           { 0x00000003, 0x00000003, 0x0000000b, 0x0000000b, 0x0000000b } },
+           { 0x00000003, 0x0000000b, 0x0000000b } },
         { AR5K_PHY_SETTLING,
-           { 0x1372161c, 0x13721c25, 0x13721722, 0x13721422, 0x13721c25 } },
+           { 0x1372161c, 0x13721722, 0x13721422 } },
         { AR5K_PHY_GAIN,
-           { 0x0018fa61, 0x0018fa61, 0x00199a65, 0x00199a65, 0x00199a65 } },
+           { 0x0018fa61, 0x00199a65, 0x00199a65 } },
         { AR5K_PHY_DESIRED_SIZE,
-           { 0x0c98b4e0, 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da, 0x0c98b0da } },
+           { 0x0c98b4e0, 0x0c98b0da, 0x0c98b0da } },
         { AR5K_PHY_SIG,
-           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
+           { 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e } },
         { AR5K_PHY_AGCCOARSE,
-           { 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e, 0x3139605e } },
+           { 0x3139605e, 0x3139605e, 0x3139605e } },
         { AR5K_PHY_WEAK_OFDM_LOW_THR,
-           { 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081 } },
+           { 0x050cb081, 0x050cb081, 0x050cb081 } },
         { AR5K_PHY_RX_DELAY,
-           { 0x000007d0, 0x000007d0, 0x0000044c, 0x00000898, 0x000007d0 } },
+           { 0x000007d0, 0x0000044c, 0x00000898 } },
         { AR5K_PHY_FRAME_CTL_5211,
-           { 0xf7b81000, 0xf7b81000, 0xf7b80d00, 0xf7b81000, 0xf7b81000 } },
+           { 0xf7b81000, 0xf7b80d00, 0xf7b81000 } },
         { AR5K_PHY_CCKTXCTL,
-           { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
+           { 0x00000000, 0x00000000, 0x00000000 } },
         { AR5K_PHY_CCK_CROSSCORR,
-           { 0xd6be6788, 0xd6be6788, 0xd03e6788, 0xd03e6788, 0xd03e6788 } },
+           { 0xd6be6788, 0xd03e6788, 0xd03e6788 } },
         { AR5K_PHY_GAIN_2GHZ,
-           { 0x00000140, 0x00000140, 0x0052c140, 0x0052c140, 0x0052c140 } },
+           { 0x00000140, 0x0052c140, 0x0052c140 } },
         { AR5K_PHY_CCK_RX_CTL_4,
-           { 0x1883800a, 0x1883800a, 0x1863800a, 0x1883800a, 0x1883800a } },
+           { 0x1883800a, 0x1863800a, 0x1883800a } },
         { 0xa324,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa328,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa32c,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa330,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
         { 0xa334,
-           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
+           { 0xa7cfa7cf, 0xa7cfa7cf, 0xa7cfa7cf } },
 };
 
 static const struct ath5k_ini rf2425_ini_common_end[] = {
@@ -1368,15 +1362,15 @@ static const struct ath5k_ini rf5112_ini_bbgain[] = {
  * Write initial register dump
  */
 static void ath5k_hw_ini_registers(struct ath5k_hw *ah, unsigned int size,
-                const struct ath5k_ini *ini_regs, bool change_channel)
+                const struct ath5k_ini *ini_regs, bool skip_pcu)
 {
         unsigned int i;
 
         /* Write initial registers */
         for (i = 0; i < size; i++) {
-                /* On channel change there is
-                 * no need to mess with PCU */
-                if (change_channel &&
+                /* Skip PCU registers if
+                 * requested */
+                if (skip_pcu &&
                                 ini_regs[i].ini_register >= AR5K_PCU_MIN &&
                                 ini_regs[i].ini_register <= AR5K_PCU_MAX)
                         continue;
@@ -1409,7 +1403,7 @@ static void ath5k_hw_ini_mode_registers(struct ath5k_hw *ah,
 
 }
 
-int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
+int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool skip_pcu)
 {
         /*
          * Write initial register settings
@@ -1427,7 +1421,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
                  * Write initial settings common for all modes
                  */
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5212_ini_common_start),
-                                ar5212_ini_common_start, change_channel);
+                                ar5212_ini_common_start, skip_pcu);
 
                 /* Second set of mode-specific settings */
                 switch (ah->ah_radio) {
@@ -1439,12 +1433,12 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5111_ini_common_end),
-                                        rf5111_ini_common_end, change_channel);
+                                        rf5111_ini_common_end, skip_pcu);
 
                         /* Baseband gain table */
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5111_ini_bbgain),
-                                        rf5111_ini_bbgain, change_channel);
+                                        rf5111_ini_bbgain, skip_pcu);
 
                         break;
                 case AR5K_RF5112:
@@ -1455,11 +1449,11 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_common_end),
-                                        rf5112_ini_common_end, change_channel);
+                                        rf5112_ini_common_end, skip_pcu);
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
 
                         break;
                 case AR5K_RF5413:
@@ -1470,11 +1464,11 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5413_ini_common_end),
-                                        rf5413_ini_common_end, change_channel);
+                                        rf5413_ini_common_end, skip_pcu);
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
 
                         break;
                 case AR5K_RF2316:
@@ -1486,7 +1480,7 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf2413_ini_common_end),
-                                        rf2413_ini_common_end, change_channel);
+                                        rf2413_ini_common_end, skip_pcu);
 
                         /* Override settings from rf2413_ini_common_end */
                         if (ah->ah_radio == AR5K_RF2316) {
@@ -1498,9 +1492,32 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
                         break;
                 case AR5K_RF2317:
+
+                        ath5k_hw_ini_mode_registers(ah,
+                                        ARRAY_SIZE(rf2413_ini_mode_end),
+                                        rf2413_ini_mode_end, mode);
+
+                        ath5k_hw_ini_registers(ah,
+                                        ARRAY_SIZE(rf2425_ini_common_end),
+                                        rf2425_ini_common_end, skip_pcu);
+
+                        /* Override settings from rf2413_ini_mode_end */
+                        ath5k_hw_reg_write(ah, 0x00180a65, AR5K_PHY_GAIN);
+
+                        /* Override settings from rf2413_ini_common_end */
+                        ath5k_hw_reg_write(ah, 0x00004000, AR5K_PHY_AGC);
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TPC_RG5,
+                                AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP, 0xa);
+                        ath5k_hw_reg_write(ah, 0x800000a8, 0x8140);
+                        ath5k_hw_reg_write(ah, 0x000000ff, 0x9958);
+
+                        ath5k_hw_ini_registers(ah,
+                                        ARRAY_SIZE(rf5112_ini_bbgain),
+                                        rf5112_ini_bbgain, skip_pcu);
+                        break;
                 case AR5K_RF2425:
 
                         ath5k_hw_ini_mode_registers(ah,
@@ -1509,11 +1526,11 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf2425_ini_common_end),
-                                        rf2425_ini_common_end, change_channel);
+                                        rf2425_ini_common_end, skip_pcu);
 
                         ath5k_hw_ini_registers(ah,
                                         ARRAY_SIZE(rf5112_ini_bbgain),
-                                        rf5112_ini_bbgain, change_channel);
+                                        rf5112_ini_bbgain, skip_pcu);
                         break;
                 default:
                         return -EINVAL;
@@ -1538,17 +1555,17 @@ int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel)
                  * Write initial settings common for all modes
                  */
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5211_ini),
-                                ar5211_ini, change_channel);
+                                ar5211_ini, skip_pcu);
 
                 /* AR5211 only comes with 5111 */
 
                 /* Baseband gain table */
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(rf5111_ini_bbgain),
-                                rf5111_ini_bbgain, change_channel);
+                                rf5111_ini_bbgain, skip_pcu);
         /* For AR5210 (for mode settings check out ath5k_hw_reset_tx_queue) */
         } else if (ah->ah_version == AR5K_AR5210) {
                 ath5k_hw_ini_registers(ah, ARRAY_SIZE(ar5210_ini),
-                                ar5210_ini, change_channel);
+                                ar5210_ini, skip_pcu);
         }
 
         return 0;
diff --git a/drivers/net/wireless/ath/ath5k/led.c b/drivers/net/wireless/ath/ath5k/led.c
index 67aa52e9bf94..576edf2965dc 100644
--- a/drivers/net/wireless/ath/ath5k/led.c
+++ b/drivers/net/wireless/ath/ath5k/led.c
@@ -133,7 +133,7 @@ ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
         led->led_dev.default_trigger = trigger;
         led->led_dev.brightness_set = ath5k_led_brightness_set;
 
-        err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
+        err = led_classdev_register(sc->dev, &led->led_dev);
         if (err) {
                 ATH5K_WARN(sc, "could not register LED %s\n", name);
                 led->sc = NULL;
@@ -161,11 +161,20 @@ int ath5k_init_leds(struct ath5k_softc *sc)
 {
         int ret = 0;
         struct ieee80211_hw *hw = sc->hw;
+#ifndef CONFIG_ATHEROS_AR231X
         struct pci_dev *pdev = sc->pdev;
+#endif
         char name[ATH5K_LED_MAX_NAME_LEN + 1];
         const struct pci_device_id *match;
 
+        if (!sc->pdev)
+                return 0;
+
+#ifdef CONFIG_ATHEROS_AR231X
+        match = NULL;
+#else
         match = pci_match_id(&ath5k_led_devices[0], pdev);
+#endif
         if (match) {
                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
                 sc->led_pin = ATH_PIN(match->driver_data);
diff --git a/drivers/net/wireless/ath/ath5k/mac80211-ops.c b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
new file mode 100644
index 000000000000..d76d68c99f72
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
@@ -0,0 +1,774 @@
+/*-
+ * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
+ * Copyright (c) 2004-2005 Atheros Communications, Inc.
+ * Copyright (c) 2006 Devicescape Software, Inc.
+ * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
+ * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
+ * Copyright (c) 2010 Bruno Randolf <br1@einfach.org>
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer,
+ *    without modification.
+ * 2. Redistributions in binary form must reproduce at minimum a disclaimer
+ *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
+ *    redistribution must be conditioned upon including a substantially
+ *    similar Disclaimer requirement for further binary redistribution.
+ * 3. Neither the names of the above-listed copyright holders nor the names
+ *    of any contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ *
+ * NO WARRANTY
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
+ * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+ * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGES.
+ *
+ */
+
+#include <asm/unaligned.h>
+
+#include "base.h"
+#include "reg.h"
+
+extern int ath5k_modparam_nohwcrypt;
+
+/* functions used from base.c */
+void set_beacon_filter(struct ieee80211_hw *hw, bool enable);
+bool ath_any_vif_assoc(struct ath5k_softc *sc);
+int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
+                   struct ath5k_txq *txq);
+int ath5k_init_hw(struct ath5k_softc *sc);
+int ath5k_stop_hw(struct ath5k_softc *sc);
+void ath5k_mode_setup(struct ath5k_softc *sc, struct ieee80211_vif *vif);
+void ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
+                                        struct ieee80211_vif *vif);
+int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan);
+void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
+int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
+void ath5k_beacon_config(struct ath5k_softc *sc);
+void ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
+void ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf);
+
+/********************\
+* Mac80211 functions *
+\********************/
+
+static int
+ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct ath5k_softc *sc = hw->priv;
+        u16 qnum = skb_get_queue_mapping(skb);
+
+        if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
+                dev_kfree_skb_any(skb);
+                return 0;
+        }
+
+        return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
+}
+
+
+static int
+ath5k_start(struct ieee80211_hw *hw)
+{
+        return ath5k_init_hw(hw->priv);
+}
+
+
+static void
+ath5k_stop(struct ieee80211_hw *hw)
+{
+        ath5k_stop_hw(hw->priv);
+}
+
+
+static int
+ath5k_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
+{
+        struct ath5k_softc *sc = hw->priv;
+        int ret;
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+
+        mutex_lock(&sc->lock);
+
+        if ((vif->type == NL80211_IFTYPE_AP ||
+             vif->type == NL80211_IFTYPE_ADHOC)
+            && (sc->num_ap_vifs + sc->num_adhoc_vifs) >= ATH_BCBUF) {
+                ret = -ELNRNG;
+                goto end;
+        }
+
+        /* Don't allow other interfaces if one ad-hoc is configured.
+         * TODO: Fix the problems with ad-hoc and multiple other interfaces.
+         * We would need to operate the HW in ad-hoc mode to allow TSF updates
+         * for the IBSS, but this breaks with additional AP or STA interfaces
+         * at the moment. */
+        if (sc->num_adhoc_vifs ||
+            (sc->nvifs && vif->type == NL80211_IFTYPE_ADHOC)) {
+                ATH5K_ERR(sc, "Only one single ad-hoc interface is allowed.\n");
+                ret = -ELNRNG;
+                goto end;
+        }
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_STATION:
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_MESH_POINT:
+                avf->opmode = vif->type;
+                break;
+        default:
+                ret = -EOPNOTSUPP;
+                goto end;
+        }
+
+        sc->nvifs++;
+        ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", avf->opmode);
+
+        /* Assign the vap/adhoc to a beacon xmit slot. */
+        if ((avf->opmode == NL80211_IFTYPE_AP) ||
+            (avf->opmode == NL80211_IFTYPE_ADHOC) ||
+            (avf->opmode == NL80211_IFTYPE_MESH_POINT)) {
+                int slot;
+
+                WARN_ON(list_empty(&sc->bcbuf));
+                avf->bbuf = list_first_entry(&sc->bcbuf, struct ath5k_buf,
+                                             list);
+                list_del(&avf->bbuf->list);
+
+                avf->bslot = 0;
+                for (slot = 0; slot < ATH_BCBUF; slot++) {
+                        if (!sc->bslot[slot]) {
+                                avf->bslot = slot;
+                                break;
+                        }
+                }
+                BUG_ON(sc->bslot[avf->bslot] != NULL);
+                sc->bslot[avf->bslot] = vif;
+                if (avf->opmode == NL80211_IFTYPE_AP)
+                        sc->num_ap_vifs++;
+                else if (avf->opmode == NL80211_IFTYPE_ADHOC)
+                        sc->num_adhoc_vifs++;
+        }
+
+        /* Any MAC address is fine, all others are included through the
+         * filter.
+         */
+        memcpy(&sc->lladdr, vif->addr, ETH_ALEN);
+        ath5k_hw_set_lladdr(sc->ah, vif->addr);
+
+        memcpy(&avf->lladdr, vif->addr, ETH_ALEN);
+
+        ath5k_mode_setup(sc, vif);
+
+        ret = 0;
+end:
+        mutex_unlock(&sc->lock);
+        return ret;
+}
+
+
+static void
+ath5k_remove_interface(struct ieee80211_hw *hw,
+                       struct ieee80211_vif *vif)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+        unsigned int i;
+
+        mutex_lock(&sc->lock);
+        sc->nvifs--;
+
+        if (avf->bbuf) {
+                ath5k_txbuf_free_skb(sc, avf->bbuf);
+                list_add_tail(&avf->bbuf->list, &sc->bcbuf);
+                for (i = 0; i < ATH_BCBUF; i++) {
+                        if (sc->bslot[i] == vif) {
+                                sc->bslot[i] = NULL;
+                                break;
+                        }
+                }
+                avf->bbuf = NULL;
+        }
+        if (avf->opmode == NL80211_IFTYPE_AP)
+                sc->num_ap_vifs--;
+        else if (avf->opmode == NL80211_IFTYPE_ADHOC)
+                sc->num_adhoc_vifs--;
+
+        ath5k_update_bssid_mask_and_opmode(sc, NULL);
+        mutex_unlock(&sc->lock);
+}
+
+
+/*
+ * TODO: Phy disable/diversity etc
+ */
+static int
+ath5k_config(struct ieee80211_hw *hw, u32 changed)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ieee80211_conf *conf = &hw->conf;
+        int ret = 0;
+
+        mutex_lock(&sc->lock);
+
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+                ret = ath5k_chan_set(sc, conf->channel);
+                if (ret < 0)
+                        goto unlock;
+        }
+
+        if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
+        (sc->power_level != conf->power_level)) {
+                sc->power_level = conf->power_level;
+
+                /* Half dB steps */
+                ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
+        }
+
+        /* TODO:
+         * 1) Move this on config_interface and handle each case
+         * separately eg. when we have only one STA vif, use
+         * AR5K_ANTMODE_SINGLE_AP
+         *
+         * 2) Allow the user to change antenna mode eg. when only
+         * one antenna is present
+         *
+         * 3) Allow the user to set default/tx antenna when possible
+         *
+         * 4) Default mode should handle 90% of the cases, together
+         * with fixed a/b and single AP modes we should be able to
+         * handle 99%. Sectored modes are extreme cases and i still
+         * haven't found a usage for them. If we decide to support them,
+         * then we must allow the user to set how many tx antennas we
+         * have available
+         */
+        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
+
+unlock:
+        mutex_unlock(&sc->lock);
+        return ret;
+}
+
+
+static void
+ath5k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+                       struct ieee80211_bss_conf *bss_conf, u32 changes)
+{
+        struct ath5k_vif *avf = (void *)vif->drv_priv;
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+        unsigned long flags;
+
+        mutex_lock(&sc->lock);
+
+        if (changes & BSS_CHANGED_BSSID) {
+                /* Cache for later use during resets */
+                memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
+                common->curaid = 0;
+                ath5k_hw_set_bssid(ah);
+                mmiowb();
+        }
+
+        if (changes & BSS_CHANGED_BEACON_INT)
+                sc->bintval = bss_conf->beacon_int;
+
+        if (changes & BSS_CHANGED_ASSOC) {
+                avf->assoc = bss_conf->assoc;
+                if (bss_conf->assoc)
+                        sc->assoc = bss_conf->assoc;
+                else
+                        sc->assoc = ath_any_vif_assoc(sc);
+
+                if (sc->opmode == NL80211_IFTYPE_STATION)
+                        set_beacon_filter(hw, sc->assoc);
+                ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
+                        AR5K_LED_ASSOC : AR5K_LED_INIT);
+                if (bss_conf->assoc) {
+                        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
+                                  "Bss Info ASSOC %d, bssid: %pM\n",
+                                  bss_conf->aid, common->curbssid);
+                        common->curaid = bss_conf->aid;
+                        ath5k_hw_set_bssid(ah);
+                        /* Once ANI is available you would start it here */
+                }
+        }
+
+        if (changes & BSS_CHANGED_BEACON) {
+                spin_lock_irqsave(&sc->block, flags);
+                ath5k_beacon_update(hw, vif);
+                spin_unlock_irqrestore(&sc->block, flags);
+        }
+
+        if (changes & BSS_CHANGED_BEACON_ENABLED)
+                sc->enable_beacon = bss_conf->enable_beacon;
+
+        if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
+                       BSS_CHANGED_BEACON_INT))
+                ath5k_beacon_config(sc);
+
+        mutex_unlock(&sc->lock);
+}
+
+
+static u64
+ath5k_prepare_multicast(struct ieee80211_hw *hw,
+                        struct netdev_hw_addr_list *mc_list)
+{
+        u32 mfilt[2], val;
+        u8 pos;
+        struct netdev_hw_addr *ha;
+
+        mfilt[0] = 0;
+        mfilt[1] = 1;
+
+        netdev_hw_addr_list_for_each(ha, mc_list) {
+                /* calculate XOR of eight 6-bit values */
+                val = get_unaligned_le32(ha->addr + 0);
+                pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+                val = get_unaligned_le32(ha->addr + 3);
+                pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
+                pos &= 0x3f;
+                mfilt[pos / 32] |= (1 << (pos % 32));
+                /* XXX: we might be able to just do this instead,
+                * but not sure, needs testing, if we do use this we'd
+                * neet to inform below to not reset the mcast */
+                /* ath5k_hw_set_mcast_filterindex(ah,
+                 *      ha->addr[5]); */
+        }
+
+        return ((u64)(mfilt[1]) << 32) | mfilt[0];
+}
+
+
+/*
+ * o always accept unicast, broadcast, and multicast traffic
+ * o multicast traffic for all BSSIDs will be enabled if mac80211
+ *   says it should be
+ * o maintain current state of phy ofdm or phy cck error reception.
+ *   If the hardware detects any of these type of errors then
+ *   ath5k_hw_get_rx_filter() will pass to us the respective
+ *   hardware filters to be able to receive these type of frames.
+ * o probe request frames are accepted only when operating in
+ *   hostap, adhoc, or monitor modes
+ * o enable promiscuous mode according to the interface state
+ * o accept beacons:
+ *   - when operating in adhoc mode so the 802.11 layer creates
+ *     node table entries for peers,
+ *   - when operating in station mode for collecting rssi data when
+ *     the station is otherwise quiet, or
+ *   - when scanning
+ */
+static void
+ath5k_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags,
+                       unsigned int *new_flags, u64 multicast)
+{
+#define SUPPORTED_FIF_FLAGS \
+        (FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
+        FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
+        FIF_BCN_PRBRESP_PROMISC)
+
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        u32 mfilt[2], rfilt;
+
+        mutex_lock(&sc->lock);
+
+        mfilt[0] = multicast;
+        mfilt[1] = multicast >> 32;
+
+        /* Only deal with supported flags */
+        changed_flags &= SUPPORTED_FIF_FLAGS;
+        *new_flags &= SUPPORTED_FIF_FLAGS;
+
+        /* If HW detects any phy or radar errors, leave those filters on.
+         * Also, always enable Unicast, Broadcasts and Multicast
+         * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
+        rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
+                (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
+                AR5K_RX_FILTER_MCAST);
+
+        if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
+                if (*new_flags & FIF_PROMISC_IN_BSS)
+                        __set_bit(ATH_STAT_PROMISC, sc->status);
+                else
+                        __clear_bit(ATH_STAT_PROMISC, sc->status);
+        }
+
+        if (test_bit(ATH_STAT_PROMISC, sc->status))
+                rfilt |= AR5K_RX_FILTER_PROM;
+
+        /* Note, AR5K_RX_FILTER_MCAST is already enabled */
+        if (*new_flags & FIF_ALLMULTI) {
+                mfilt[0] =  ~0;
+                mfilt[1] =  ~0;
+        }
+
+        /* This is the best we can do */
+        if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
+                rfilt |= AR5K_RX_FILTER_PHYERR;
+
+        /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
+        * and probes for any BSSID */
+        if ((*new_flags & FIF_BCN_PRBRESP_PROMISC) || (sc->nvifs > 1))
+                rfilt |= AR5K_RX_FILTER_BEACON;
+
+        /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
+         * set we should only pass on control frames for this
+         * station. This needs testing. I believe right now this
+         * enables *all* control frames, which is OK.. but
+         * but we should see if we can improve on granularity */
+        if (*new_flags & FIF_CONTROL)
+                rfilt |= AR5K_RX_FILTER_CONTROL;
+
+        /* Additional settings per mode -- this is per ath5k */
+
+        /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
+
+        switch (sc->opmode) {
+        case NL80211_IFTYPE_MESH_POINT:
+                rfilt |= AR5K_RX_FILTER_CONTROL |
+                         AR5K_RX_FILTER_BEACON |
+                         AR5K_RX_FILTER_PROBEREQ |
+                         AR5K_RX_FILTER_PROM;
+                break;
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_ADHOC:
+                rfilt |= AR5K_RX_FILTER_PROBEREQ |
+                         AR5K_RX_FILTER_BEACON;
+                break;
+        case NL80211_IFTYPE_STATION:
+                if (sc->assoc)
+                        rfilt |= AR5K_RX_FILTER_BEACON;
+        default:
+                break;
+        }
+
+        /* Set filters */
+        ath5k_hw_set_rx_filter(ah, rfilt);
+
+        /* Set multicast bits */
+        ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
+        /* Set the cached hw filter flags, this will later actually
+         * be set in HW */
+        sc->filter_flags = rfilt;
+
+        mutex_unlock(&sc->lock);
+}
+
+
+static int
+ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+              struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+              struct ieee80211_key_conf *key)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath_common *common = ath5k_hw_common(ah);
+        int ret = 0;
+
+        if (ath5k_modparam_nohwcrypt)
+                return -EOPNOTSUPP;
+
+        switch (key->cipher) {
+        case WLAN_CIPHER_SUITE_WEP40:
+        case WLAN_CIPHER_SUITE_WEP104:
+        case WLAN_CIPHER_SUITE_TKIP:
+                break;
+        case WLAN_CIPHER_SUITE_CCMP:
+                if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
+                        break;
+                return -EOPNOTSUPP;
+        default:
+                WARN_ON(1);
+                return -EINVAL;
+        }
+
+        mutex_lock(&sc->lock);
+
+        switch (cmd) {
+        case SET_KEY:
+                ret = ath_key_config(common, vif, sta, key);
+                if (ret >= 0) {
+                        key->hw_key_idx = ret;
+                        /* push IV and Michael MIC generation to stack */
+                        key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
+                        if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
+                                key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+                        if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
+                                key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
+                        ret = 0;
+                }
+                break;
+        case DISABLE_KEY:
+                ath_key_delete(common, key);
+                break;
+        default:
+                ret = -EINVAL;
+        }
+
+        mmiowb();
+        mutex_unlock(&sc->lock);
+        return ret;
+}
+
+
+static void
+ath5k_sw_scan_start(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+        if (!sc->assoc)
+                ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
+}
+
+
+static void
+ath5k_sw_scan_complete(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+        ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
+                AR5K_LED_ASSOC : AR5K_LED_INIT);
+}
+
+
+static int
+ath5k_get_stats(struct ieee80211_hw *hw,
+                struct ieee80211_low_level_stats *stats)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        /* Force update */
+        ath5k_hw_update_mib_counters(sc->ah);
+
+        stats->dot11ACKFailureCount = sc->stats.ack_fail;
+        stats->dot11RTSFailureCount = sc->stats.rts_fail;
+        stats->dot11RTSSuccessCount = sc->stats.rts_ok;
+        stats->dot11FCSErrorCount = sc->stats.fcs_error;
+
+        return 0;
+}
+
+
+static int
+ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
+              const struct ieee80211_tx_queue_params *params)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ath5k_hw *ah = sc->ah;
+        struct ath5k_txq_info qi;
+        int ret = 0;
+
+        if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
+                return 0;
+
+        mutex_lock(&sc->lock);
+
+        ath5k_hw_get_tx_queueprops(ah, queue, &qi);
+
+        qi.tqi_aifs = params->aifs;
+        qi.tqi_cw_min = params->cw_min;
+        qi.tqi_cw_max = params->cw_max;
+        qi.tqi_burst_time = params->txop;
+
+        ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
+                  "Configure tx [queue %d],  "
+                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                  queue, params->aifs, params->cw_min,
+                  params->cw_max, params->txop);
+
+        if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
+                ATH5K_ERR(sc,
+                          "Unable to update hardware queue %u!\n", queue);
+                ret = -EIO;
+        } else
+                ath5k_hw_reset_tx_queue(ah, queue);
+
+        mutex_unlock(&sc->lock);
+
+        return ret;
+}
+
+
+static u64
+ath5k_get_tsf(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        return ath5k_hw_get_tsf64(sc->ah);
+}
+
+
+static void
+ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        ath5k_hw_set_tsf64(sc->ah, tsf);
+}
+
+
+static void
+ath5k_reset_tsf(struct ieee80211_hw *hw)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        /*
+         * in IBSS mode we need to update the beacon timers too.
+         * this will also reset the TSF if we call it with 0
+         */
+        if (sc->opmode == NL80211_IFTYPE_ADHOC)
+                ath5k_beacon_update_timers(sc, 0);
+        else
+                ath5k_hw_reset_tsf(sc->ah);
+}
+
+
+static int
+ath5k_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey)
+{
+        struct ath5k_softc *sc = hw->priv;
+        struct ieee80211_conf *conf = &hw->conf;
+        struct ath_common *common = ath5k_hw_common(sc->ah);
+        struct ath_cycle_counters *cc = &common->cc_survey;
+        unsigned int div = common->clockrate * 1000;
+
+        if (idx != 0)
+                return -ENOENT;
+
+        spin_lock_bh(&common->cc_lock);
+        ath_hw_cycle_counters_update(common);
+        if (cc->cycles > 0) {
+                sc->survey.channel_time += cc->cycles / div;
+                sc->survey.channel_time_busy += cc->rx_busy / div;
+                sc->survey.channel_time_rx += cc->rx_frame / div;
+                sc->survey.channel_time_tx += cc->tx_frame / div;
+        }
+        memset(cc, 0, sizeof(*cc));
+        spin_unlock_bh(&common->cc_lock);
+
+        memcpy(survey, &sc->survey, sizeof(*survey));
+
+        survey->channel = conf->channel;
+        survey->noise = sc->ah->ah_noise_floor;
+        survey->filled = SURVEY_INFO_NOISE_DBM |
+                        SURVEY_INFO_CHANNEL_TIME |
+                        SURVEY_INFO_CHANNEL_TIME_BUSY |
+                        SURVEY_INFO_CHANNEL_TIME_RX |
+                        SURVEY_INFO_CHANNEL_TIME_TX;
+
+        return 0;
+}
+
+
+/**
+ * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
+ *
+ * @hw: struct ieee80211_hw pointer
+ * @coverage_class: IEEE 802.11 coverage class number
+ *
+ * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
+ * coverage class. The values are persistent, they are restored after device
+ * reset.
+ */
+static void
+ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        mutex_lock(&sc->lock);
+        ath5k_hw_set_coverage_class(sc->ah, coverage_class);
+        mutex_unlock(&sc->lock);
+}
+
+
+static int
+ath5k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        if (tx_ant == 1 && rx_ant == 1)
+                ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_A);
+        else if (tx_ant == 2 && rx_ant == 2)
+                ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_FIXED_B);
+        else if ((tx_ant & 3) == 3 && (rx_ant & 3) == 3)
+                ath5k_hw_set_antenna_mode(sc->ah, AR5K_ANTMODE_DEFAULT);
+        else
+                return -EINVAL;
+        return 0;
+}
+
+
+static int
+ath5k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
+{
+        struct ath5k_softc *sc = hw->priv;
+
+        switch (sc->ah->ah_ant_mode) {
+        case AR5K_ANTMODE_FIXED_A:
+                *tx_ant = 1; *rx_ant = 1; break;
+        case AR5K_ANTMODE_FIXED_B:
+                *tx_ant = 2; *rx_ant = 2; break;
+        case AR5K_ANTMODE_DEFAULT:
+                *tx_ant = 3; *rx_ant = 3; break;
+        }
+        return 0;
+}
+
+
+const struct ieee80211_ops ath5k_hw_ops = {
+        .tx                     = ath5k_tx,
+        .start                  = ath5k_start,
+        .stop                   = ath5k_stop,
+        .add_interface          = ath5k_add_interface,
+        /* .change_interface    = not implemented */
+        .remove_interface       = ath5k_remove_interface,
+        .config                 = ath5k_config,
+        .bss_info_changed       = ath5k_bss_info_changed,
+        .prepare_multicast      = ath5k_prepare_multicast,
+        .configure_filter       = ath5k_configure_filter,
+        /* .set_tim             = not implemented */
+        .set_key                = ath5k_set_key,
+        /* .update_tkip_key     = not implemented */
+        /* .hw_scan             = not implemented */
+        .sw_scan_start          = ath5k_sw_scan_start,
+        .sw_scan_complete       = ath5k_sw_scan_complete,
+        .get_stats              = ath5k_get_stats,
+        /* .get_tkip_seq        = not implemented */
+        /* .set_frag_threshold  = not implemented */
+        /* .set_rts_threshold   = not implemented */
+        /* .sta_add             = not implemented */
+        /* .sta_remove          = not implemented */
+        /* .sta_notify          = not implemented */
+        .conf_tx                = ath5k_conf_tx,
+        .get_tsf                = ath5k_get_tsf,
+        .set_tsf                = ath5k_set_tsf,
+        .reset_tsf              = ath5k_reset_tsf,
+        /* .tx_last_beacon      = not implemented */
+        /* .ampdu_action        = not needed */
+        .get_survey             = ath5k_get_survey,
+        .set_coverage_class     = ath5k_set_coverage_class,
+        /* .rfkill_poll         = not implemented */
+        /* .flush               = not implemented */
+        /* .channel_switch      = not implemented */
+        /* .napi_poll           = not implemented */
+        .set_antenna            = ath5k_set_antenna,
+        .get_antenna            = ath5k_get_antenna,
+};
diff --git a/drivers/net/wireless/ath/ath5k/pci.c b/drivers/net/wireless/ath/ath5k/pci.c
new file mode 100644
index 000000000000..7f8c5b0e9d2a
--- /dev/null
+++ b/drivers/net/wireless/ath/ath5k/pci.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2008-2009 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/nl80211.h>
+#include <linux/pci.h>
+#include <linux/pci-aspm.h>
+#include "../ath.h"
+#include "ath5k.h"
+#include "debug.h"
+#include "base.h"
+#include "reg.h"
+
+/* Known PCI ids */
+static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
+        { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
+        { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
+        { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
+        { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
+        { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
+        { PCI_VDEVICE(3COM_2,  0x0013) }, /* 3com 5212 */
+        { PCI_VDEVICE(3COM,    0x0013) }, /* 3com 3CRDAG675 5212 */
+        { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
+        { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
+        { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
+        { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
+        { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
+        { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
+        { 0 }
+};
+MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
+
+/* return bus cachesize in 4B word units */
+static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz)
+{
+        struct ath5k_softc *sc = (struct ath5k_softc *) common->priv;
+        u8 u8tmp;
+
+        pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp);
+        *csz = (int)u8tmp;
+
+        /*
+         * This check was put in to avoid "unplesant" consequences if
+         * the bootrom has not fully initialized all PCI devices.
+         * Sometimes the cache line size register is not set
+         */
+
+        if (*csz == 0)
+                *csz = L1_CACHE_BYTES >> 2;   /* Use the default size */
+}
+
+/*
+ * Read from eeprom
+ */
+bool ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data)
+{
+        struct ath5k_hw *ah = (struct ath5k_hw *) common->ah;
+        u32 status, timeout;
+
+        /*
+         * Initialize EEPROM access
+         */
+        if (ah->ah_version == AR5K_AR5210) {
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
+                (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
+        } else {
+                ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
+                AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
+                                AR5K_EEPROM_CMD_READ);
+        }
+
+        for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
+                status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
+                if (status & AR5K_EEPROM_STAT_RDDONE) {
+                        if (status & AR5K_EEPROM_STAT_RDERR)
+                                return -EIO;
+                        *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
+                                        0xffff);
+                        return 0;
+                }
+                udelay(15);
+        }
+
+        return -ETIMEDOUT;
+}
+
+int ath5k_hw_read_srev(struct ath5k_hw *ah)
+{
+        ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV);
+        return 0;
+}
+
+/* Common ath_bus_opts structure */
+static const struct ath_bus_ops ath_pci_bus_ops = {
+        .ath_bus_type = ATH_PCI,
+        .read_cachesize = ath5k_pci_read_cachesize,
+        .eeprom_read = ath5k_pci_eeprom_read,
+};
+
+/********************\
+* PCI Initialization *
+\********************/
+
+static int __devinit
+ath5k_pci_probe(struct pci_dev *pdev,
+                const struct pci_device_id *id)
+{
+        void __iomem *mem;
+        struct ath5k_softc *sc;
+        struct ieee80211_hw *hw;
+        int ret;
+        u8 csz;
+
+        /*
+         * L0s needs to be disabled on all ath5k cards.
+         *
+         * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
+         * by default in the future in 2.6.36) this will also mean both L1 and
+         * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
+         * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
+         * though but cannot currently undue the effect of a blacklist, for
+         * details you can read pcie_aspm_sanity_check() and see how it adjusts
+         * the device link capability.
+         *
+         * It may be possible in the future to implement some PCI API to allow
+         * drivers to override blacklists for pre 1.1 PCIe but for now it is
+         * best to accept that both L0s and L1 will be disabled completely for
+         * distributions shipping with CONFIG_PCIEASPM rather than having this
+         * issue present. Motivation for adding this new API will be to help
+         * with power consumption for some of these devices.
+         */
+        pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
+
+        ret = pci_enable_device(pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "can't enable device\n");
+                goto err;
+        }
+
+        /* XXX 32-bit addressing only */
+        ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+        if (ret) {
+                dev_err(&pdev->dev, "32-bit DMA not available\n");
+                goto err_dis;
+        }
+
+        /*
+         * Cache line size is used to size and align various
+         * structures used to communicate with the hardware.
+         */
+        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
+        if (csz == 0) {
+                /*
+                 * Linux 2.4.18 (at least) writes the cache line size
+                 * register as a 16-bit wide register which is wrong.
+                 * We must have this setup properly for rx buffer
+                 * DMA to work so force a reasonable value here if it
+                 * comes up zero.
+                 */
+                csz = L1_CACHE_BYTES >> 2;
+                pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
+        }
+        /*
+         * The default setting of latency timer yields poor results,
+         * set it to the value used by other systems.  It may be worth
+         * tweaking this setting more.
+         */
+        pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
+
+        /* Enable bus mastering */
+        pci_set_master(pdev);
+
+        /*
+         * Disable the RETRY_TIMEOUT register (0x41) to keep
+         * PCI Tx retries from interfering with C3 CPU state.
+         */
+        pci_write_config_byte(pdev, 0x41, 0);
+
+        ret = pci_request_region(pdev, 0, "ath5k");
+        if (ret) {
+                dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
+                goto err_dis;
+        }
+
+        mem = pci_iomap(pdev, 0, 0);
+        if (!mem) {
+                dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
+                ret = -EIO;
+                goto err_reg;
+        }
+
+        /*
+         * Allocate hw (mac80211 main struct)
+         * and hw->priv (driver private data)
+         */
+        hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
+        if (hw == NULL) {
+                dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
+                ret = -ENOMEM;
+                goto err_map;
+        }
+
+        dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
+
+        sc = hw->priv;
+        sc->hw = hw;
+        sc->pdev = pdev;
+        sc->dev = &pdev->dev;
+        sc->irq = pdev->irq;
+        sc->devid = id->device;
+        sc->iobase = mem; /* So we can unmap it on detach */
+
+        /* Initialize */
+        ret = ath5k_init_softc(sc, &ath_pci_bus_ops);
+        if (ret)
+                goto err_free;
+
+        /* Set private data */
+        pci_set_drvdata(pdev, hw);
+
+        return 0;
+err_free:
+        ieee80211_free_hw(hw);
+err_map:
+        pci_iounmap(pdev, mem);
+err_reg:
+        pci_release_region(pdev, 0);
+err_dis:
+        pci_disable_device(pdev);
+err:
+        return ret;
+}
+
+static void __devexit
+ath5k_pci_remove(struct pci_dev *pdev)
+{
+        struct ieee80211_hw *hw = pci_get_drvdata(pdev);
+        struct ath5k_softc *sc = hw->priv;
+
+        ath5k_deinit_softc(sc);
+        pci_iounmap(pdev, sc->iobase);
+        pci_release_region(pdev, 0);
+        pci_disable_device(pdev);
+        ieee80211_free_hw(hw);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int ath5k_pci_suspend(struct device *dev)
+{
+        struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
+
+        ath5k_led_off(sc);
+        return 0;
+}
+
+static int ath5k_pci_resume(struct device *dev)
+{
+        struct pci_dev *pdev = to_pci_dev(dev);
+        struct ath5k_softc *sc = pci_get_drvdata(pdev);
+
+        /*
+         * Suspend/Resume resets the PCI configuration space, so we have to
+         * re-disable the RETRY_TIMEOUT register (0x41) to keep
+         * PCI Tx retries from interfering with C3 CPU state
+         */
+        pci_write_config_byte(pdev, 0x41, 0);
+
+        ath5k_led_enable(sc);
+        return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
+#define ATH5K_PM_OPS    (&ath5k_pm_ops)
+#else
+#define ATH5K_PM_OPS    NULL
+#endif /* CONFIG_PM_SLEEP */
+
+static struct pci_driver ath5k_pci_driver = {
+        .name           = KBUILD_MODNAME,
+        .id_table       = ath5k_pci_id_table,
+        .probe          = ath5k_pci_probe,
+        .remove         = __devexit_p(ath5k_pci_remove),
+        .driver.pm      = ATH5K_PM_OPS,
+};
+
+/*
+ * Module init/exit functions
+ */
+static int __init
+init_ath5k_pci(void)
+{
+        int ret;
+
+        ret = pci_register_driver(&ath5k_pci_driver);
+        if (ret) {
+                printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static void __exit
+exit_ath5k_pci(void)
+{
+        pci_unregister_driver(&ath5k_pci_driver);
+}
+
+module_init(init_ath5k_pci);
+module_exit(exit_ath5k_pci);
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index 074b4c644399..e5f2b96a4c63 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -31,87 +31,163 @@
 #include "debug.h"
 #include "base.h"
 
+/*
+ * AR5212+ can use higher rates for ack transmition
+ * based on current tx rate instead of the base rate.
+ * It does this to better utilize channel usage.
+ * This is a mapping between G rates (that cover both
+ * CCK and OFDM) and ack rates that we use when setting
+ * rate -> duration table. This mapping is hw-based so
+ * don't change anything.
+ *
+ * To enable this functionality we must set
+ * ah->ah_ack_bitrate_high to true else base rate is
+ * used (1Mb for CCK, 6Mb for OFDM).
+ */
+static const unsigned int ack_rates_high[] =
+/* Tx   -> ACK  */
+/* 1Mb  -> 1Mb  */      { 0,
+/* 2MB  -> 2Mb  */      1,
+/* 5.5Mb -> 2Mb */      1,
+/* 11Mb -> 2Mb  */      1,
+/* 6Mb  -> 6Mb  */      4,
+/* 9Mb  -> 6Mb  */      4,
+/* 12Mb -> 12Mb */      6,
+/* 18Mb -> 12Mb */      6,
+/* 24Mb -> 24Mb */      8,
+/* 36Mb -> 24Mb */      8,
+/* 48Mb -> 24Mb */      8,
+/* 54Mb -> 24Mb */      8 };
+
 /*******************\
-* Generic functions *
+* Helper functions *
 \*******************/
 
 /**
- * ath5k_hw_set_opmode - Set PCU operating mode
+ * ath5k_hw_get_frame_duration - Get tx time of a frame
  *
  * @ah: The &struct ath5k_hw
- * @op_mode: &enum nl80211_iftype operating mode
+ * @len: Frame's length in bytes
+ * @rate: The @struct ieee80211_rate
  *
- * Initialize PCU for the various operating modes (AP/STA etc)
+ * Calculate tx duration of a frame given it's rate and length
+ * It extends ieee80211_generic_frame_duration for non standard
+ * bwmodes.
  */
-int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
+int ath5k_hw_get_frame_duration(struct ath5k_hw *ah,
+                int len, struct ieee80211_rate *rate)
 {
-        struct ath_common *common = ath5k_hw_common(ah);
-        u32 pcu_reg, beacon_reg, low_id, high_id;
+        struct ath5k_softc *sc = ah->ah_sc;
+        int sifs, preamble, plcp_bits, sym_time;
+        int bitrate, bits, symbols, symbol_bits;
+        int dur;
+
+        /* Fallback */
+        if (!ah->ah_bwmode) {
+                dur = ieee80211_generic_frame_duration(sc->hw,
+                                                NULL, len, rate);
+                return dur;
+        }
 
-        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
+        bitrate = rate->bitrate;
+        preamble = AR5K_INIT_OFDM_PREAMPLE_TIME;
+        plcp_bits = AR5K_INIT_OFDM_PLCP_BITS;
+        sym_time = AR5K_INIT_OFDM_SYMBOL_TIME;
 
-        /* Preserve rest settings */
-        pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
-        pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
-                        | AR5K_STA_ID1_KEYSRCH_MODE
-                        | (ah->ah_version == AR5K_AR5210 ?
-                        (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                sifs = AR5K_INIT_SIFS_TURBO;
+                preamble = AR5K_INIT_OFDM_PREAMBLE_TIME_MIN;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                sifs = AR5K_INIT_SIFS_HALF_RATE;
+                preamble *= 2;
+                sym_time *= 2;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                sifs = AR5K_INIT_SIFS_QUARTER_RATE;
+                preamble *= 4;
+                sym_time *= 4;
+                break;
+        default:
+                sifs = AR5K_INIT_SIFS_DEFAULT_BG;
+                break;
+        }
 
-        beacon_reg = 0;
+        bits = plcp_bits + (len << 3);
+        /* Bit rate is in 100Kbits */
+        symbol_bits = bitrate * sym_time;
+        symbols = DIV_ROUND_UP(bits * 10, symbol_bits);
 
-        switch (op_mode) {
-        case NL80211_IFTYPE_ADHOC:
-                pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
-                beacon_reg |= AR5K_BCR_ADHOC;
-                if (ah->ah_version == AR5K_AR5210)
-                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
-                else
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
-                break;
+        dur = sifs + preamble + (sym_time * symbols);
 
-        case NL80211_IFTYPE_AP:
-        case NL80211_IFTYPE_MESH_POINT:
-                pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
-                beacon_reg |= AR5K_BCR_AP;
-                if (ah->ah_version == AR5K_AR5210)
-                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
-                else
-                        AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
-                break;
+        return dur;
+}
 
-        case NL80211_IFTYPE_STATION:
-                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
-                        | (ah->ah_version == AR5K_AR5210 ?
-                                AR5K_STA_ID1_PWR_SV : 0);
-        case NL80211_IFTYPE_MONITOR:
-                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
-                        | (ah->ah_version == AR5K_AR5210 ?
-                                AR5K_STA_ID1_NO_PSPOLL : 0);
-                break;
+/**
+ * ath5k_hw_get_default_slottime - Get the default slot time for current mode
+ *
+ * @ah: The &struct ath5k_hw
+ */
+unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
+{
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        unsigned int slot_time;
 
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                slot_time = AR5K_INIT_SLOT_TIME_TURBO;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                slot_time = AR5K_INIT_SLOT_TIME_HALF_RATE;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                slot_time = AR5K_INIT_SLOT_TIME_QUARTER_RATE;
+                break;
+        case AR5K_BWMODE_DEFAULT:
+                slot_time = AR5K_INIT_SLOT_TIME_DEFAULT;
         default:
-                return -EINVAL;
+                if (channel->hw_value & CHANNEL_CCK)
+                        slot_time = AR5K_INIT_SLOT_TIME_B;
+                break;
         }
 
-        /*
-         * Set PCU registers
-         */
-        low_id = get_unaligned_le32(common->macaddr);
-        high_id = get_unaligned_le16(common->macaddr + 4);
-        ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
-        ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
+        return slot_time;
+}
 
-        /*
-         * Set Beacon Control Register on 5210
-         */
-        if (ah->ah_version == AR5K_AR5210)
-                ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
+/**
+ * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
+ *
+ * @ah: The &struct ath5k_hw
+ */
+unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
+{
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        unsigned int sifs;
 
-        return 0;
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                sifs = AR5K_INIT_SIFS_TURBO;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                sifs = AR5K_INIT_SIFS_HALF_RATE;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                sifs = AR5K_INIT_SIFS_QUARTER_RATE;
+                break;
+        case AR5K_BWMODE_DEFAULT:
+                sifs = AR5K_INIT_SIFS_DEFAULT_BG;
+        default:
+                if (channel->hw_value & CHANNEL_5GHZ)
+                        sifs = AR5K_INIT_SIFS_DEFAULT_A;
+                break;
+        }
+
+        return sifs;
 }
 
 /**
- * ath5k_hw_update - Update MIB counters (mac layer statistics)
+ * ath5k_hw_update_mib_counters - Update MIB counters (mac layer statistics)
  *
  * @ah: The &struct ath5k_hw
  *
@@ -133,36 +209,88 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
         stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
 }
 
+
+/******************\
+* ACK/CTS Timeouts *
+\******************/
+
 /**
- * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
+ * ath5k_hw_write_rate_duration - fill rate code to duration table
  *
- * @ah: The &struct ath5k_hw
- * @high: Flag to determine if we want to use high transmission rate
- * for ACKs or not
+ * @ah: the &struct ath5k_hw
+ * @mode: one of enum ath5k_driver_mode
+ *
+ * Write the rate code to duration table upon hw reset. This is a helper for
+ * ath5k_hw_pcu_init(). It seems all this is doing is setting an ACK timeout on
+ * the hardware, based on current mode, for each rate. The rates which are
+ * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
+ * different rate code so we write their value twice (one for long preamble
+ * and one for short).
+ *
+ * Note: Band doesn't matter here, if we set the values for OFDM it works
+ * on both a and g modes. So all we have to do is set values for all g rates
+ * that include all OFDM and CCK rates.
  *
- * If high flag is set, we tell hw to use a set of control rates based on
- * the current transmission rate (check out control_rates array inside reset.c).
- * If not hw just uses the lowest rate available for the current modulation
- * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
  */
-void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
+static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah)
 {
-        if (ah->ah_version != AR5K_AR5212)
-                return;
-        else {
-                u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
-                if (high)
-                        AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct ieee80211_rate *rate;
+        unsigned int i;
+        /* 802.11g covers both OFDM and CCK */
+        u8 band = IEEE80211_BAND_2GHZ;
+
+        /* Write rate duration table */
+        for (i = 0; i < sc->sbands[band].n_bitrates; i++) {
+                u32 reg;
+                u16 tx_time;
+
+                if (ah->ah_ack_bitrate_high)
+                        rate = &sc->sbands[band].bitrates[ack_rates_high[i]];
+                /* CCK -> 1Mb */
+                else if (i < 4)
+                        rate = &sc->sbands[band].bitrates[0];
+                /* OFDM -> 6Mb */
                 else
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
+                        rate = &sc->sbands[band].bitrates[4];
+
+                /* Set ACK timeout */
+                reg = AR5K_RATE_DUR(rate->hw_value);
+
+                /* An ACK frame consists of 10 bytes. If you add the FCS,
+                 * which ieee80211_generic_frame_duration() adds,
+                 * its 14 bytes. Note we use the control rate and not the
+                 * actual rate for this rate. See mac80211 tx.c
+                 * ieee80211_duration() for a brief description of
+                 * what rate we should choose to TX ACKs. */
+                tx_time = ath5k_hw_get_frame_duration(ah, 10, rate);
+
+                tx_time = le16_to_cpu(tx_time);
+
+                ath5k_hw_reg_write(ah, tx_time, reg);
+
+                if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
+                        continue;
+
+                /*
+                 * We're not distinguishing short preamble here,
+                 * This is true, all we'll get is a longer value here
+                 * which is not necessarilly bad. We could use
+                 * export ieee80211_frame_duration() but that needs to be
+                 * fixed first to be properly used by mac802111 drivers:
+                 *
+                 *  - remove erp stuff and let the routine figure ofdm
+                 *    erp rates
+                 *  - remove passing argument ieee80211_local as
+                 *    drivers don't have access to it
+                 *  - move drivers using ieee80211_generic_frame_duration()
+                 *    to this
+                 */
+                ath5k_hw_reg_write(ah, tx_time,
+                        reg + (AR5K_SET_SHORT_PREAMBLE << 2));
         }
 }
 
-
-/******************\
-* ACK/CTS Timeouts *
-\******************/
-
 /**
  * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
  *
@@ -199,88 +327,10 @@ static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
         return 0;
 }
 
-/**
- * ath5k_hw_htoclock - Translate usec to hw clock units
- *
- * @ah: The &struct ath5k_hw
- * @usec: value in microseconds
- */
-unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
-{
-        struct ath_common *common = ath5k_hw_common(ah);
-        return usec * common->clockrate;
-}
-
-/**
- * ath5k_hw_clocktoh - Translate hw clock units to usec
- * @clock: value in hw clock units
- */
-unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
-{
-        struct ath_common *common = ath5k_hw_common(ah);
-        return clock / common->clockrate;
-}
-
-/**
- * ath5k_hw_set_clockrate - Set common->clockrate for the current channel
- *
- * @ah: The &struct ath5k_hw
- */
-void ath5k_hw_set_clockrate(struct ath5k_hw *ah)
-{
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-        struct ath_common *common = ath5k_hw_common(ah);
-        int clock;
-
-        if (channel->hw_value & CHANNEL_5GHZ)
-                clock = 40; /* 802.11a */
-        else if (channel->hw_value & CHANNEL_CCK)
-                clock = 22; /* 802.11b */
-        else
-                clock = 44; /* 802.11g */
-
-        /* Clock rate in turbo modes is twice the normal rate */
-        if (channel->hw_value & CHANNEL_TURBO)
-                clock *= 2;
-
-        common->clockrate = clock;
-}
-
-/**
- * ath5k_hw_get_default_slottime - Get the default slot time for current mode
- *
- * @ah: The &struct ath5k_hw
- */
-static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
-{
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-
-        if (channel->hw_value & CHANNEL_TURBO)
-                return 6; /* both turbo modes */
-
-        if (channel->hw_value & CHANNEL_CCK)
-                return 20; /* 802.11b */
-
-        return 9; /* 802.11 a/g */
-}
-
-/**
- * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
- *
- * @ah: The &struct ath5k_hw
- */
-static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
-{
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-
-        if (channel->hw_value & CHANNEL_TURBO)
-                return 8; /* both turbo modes */
 
-        if (channel->hw_value & CHANNEL_5GHZ)
-                return 16; /* 802.11a */
-
-        return 10; /* 802.11 b/g */
-}
+/*******************\
+* RX filter Control *
+\*******************/
 
 /**
  * ath5k_hw_set_lladdr - Set station id
@@ -362,39 +412,6 @@ void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
                 ath_hw_setbssidmask(common);
 }
 
-/************\
-* RX Control *
-\************/
-
-/**
- * ath5k_hw_start_rx_pcu - Start RX engine
- *
- * @ah: The &struct ath5k_hw
- *
- * Starts RX engine on PCU so that hw can process RXed frames
- * (ACK etc).
- *
- * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
- */
-void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
-{
-        AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
-}
-
-/**
- * at5k_hw_stop_rx_pcu - Stop RX engine
- *
- * @ah: The &struct ath5k_hw
- *
- * Stops RX engine on PCU
- *
- * TODO: Detach ANI here
- */
-void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
-{
-        AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
-}
-
 /*
  * Set multicast filter
  */
@@ -746,7 +763,7 @@ ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
  * @ah: The &struct ath5k_hw
  * @coverage_class: IEEE 802.11 coverage class number
  *
- * Sets slot time, ACK timeout and CTS timeout for given coverage class.
+ * Sets IFS intervals and ACK/CTS timeouts for given coverage class.
  */
 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
 {
@@ -755,9 +772,175 @@ void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
         int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
         int cts_timeout = ack_timeout;
 
-        ath5k_hw_set_slot_time(ah, slot_time);
+        ath5k_hw_set_ifs_intervals(ah, slot_time);
         ath5k_hw_set_ack_timeout(ah, ack_timeout);
         ath5k_hw_set_cts_timeout(ah, cts_timeout);
 
         ah->ah_coverage_class = coverage_class;
 }
+
+/***************************\
+* Init/Start/Stop functions *
+\***************************/
+
+/**
+ * ath5k_hw_start_rx_pcu - Start RX engine
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Starts RX engine on PCU so that hw can process RXed frames
+ * (ACK etc).
+ *
+ * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
+ */
+void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
+{
+        AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
+}
+
+/**
+ * at5k_hw_stop_rx_pcu - Stop RX engine
+ *
+ * @ah: The &struct ath5k_hw
+ *
+ * Stops RX engine on PCU
+ */
+void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
+{
+        AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
+}
+
+/**
+ * ath5k_hw_set_opmode - Set PCU operating mode
+ *
+ * @ah: The &struct ath5k_hw
+ * @op_mode: &enum nl80211_iftype operating mode
+ *
+ * Configure PCU for the various operating modes (AP/STA etc)
+ */
+int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        u32 pcu_reg, beacon_reg, low_id, high_id;
+
+        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
+
+        /* Preserve rest settings */
+        pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
+        pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
+                        | AR5K_STA_ID1_KEYSRCH_MODE
+                        | (ah->ah_version == AR5K_AR5210 ?
+                        (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
+
+        beacon_reg = 0;
+
+        switch (op_mode) {
+        case NL80211_IFTYPE_ADHOC:
+                pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
+                beacon_reg |= AR5K_BCR_ADHOC;
+                if (ah->ah_version == AR5K_AR5210)
+                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
+                else
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
+                break;
+
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_MESH_POINT:
+                pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
+                beacon_reg |= AR5K_BCR_AP;
+                if (ah->ah_version == AR5K_AR5210)
+                        pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
+                else
+                        AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
+                break;
+
+        case NL80211_IFTYPE_STATION:
+                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
+                        | (ah->ah_version == AR5K_AR5210 ?
+                                AR5K_STA_ID1_PWR_SV : 0);
+        case NL80211_IFTYPE_MONITOR:
+                pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
+                        | (ah->ah_version == AR5K_AR5210 ?
+                                AR5K_STA_ID1_NO_PSPOLL : 0);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        /*
+         * Set PCU registers
+         */
+        low_id = get_unaligned_le32(common->macaddr);
+        high_id = get_unaligned_le16(common->macaddr + 4);
+        ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
+        ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
+
+        /*
+         * Set Beacon Control Register on 5210
+         */
+        if (ah->ah_version == AR5K_AR5210)
+                ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
+
+        return 0;
+}
+
+void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
+                                                                u8 mode)
+{
+        /* Set bssid and bssid mask */
+        ath5k_hw_set_bssid(ah);
+
+        /* Set PCU config */
+        ath5k_hw_set_opmode(ah, op_mode);
+
+        /* Write rate duration table only on AR5212 and if
+         * virtual interface has already been brought up
+         * XXX: rethink this after new mode changes to
+         * mac80211 are integrated */
+        if (ah->ah_version == AR5K_AR5212 &&
+                ah->ah_sc->nvifs)
+                ath5k_hw_write_rate_duration(ah);
+
+        /* Set RSSI/BRSSI thresholds
+         *
+         * Note: If we decide to set this value
+         * dynamicaly, have in mind that when AR5K_RSSI_THR
+         * register is read it might return 0x40 if we haven't
+         * wrote anything to it plus BMISS RSSI threshold is zeroed.
+         * So doing a save/restore procedure here isn't the right
+         * choice. Instead store it on ath5k_hw */
+        ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
+                                AR5K_TUNE_BMISS_THRES <<
+                                AR5K_RSSI_THR_BMISS_S),
+                                AR5K_RSSI_THR);
+
+        /* MIC QoS support */
+        if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
+                ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
+                ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
+        }
+
+        /* QoS NOACK Policy */
+        if (ah->ah_version == AR5K_AR5212) {
+                ath5k_hw_reg_write(ah,
+                        AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
+                        AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
+                        AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
+                        AR5K_QOS_NOACK);
+        }
+
+        /* Restore slot time and ACK timeouts */
+        if (ah->ah_coverage_class > 0)
+                ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
+
+        /* Set ACK bitrate mode (see ack_rates_high) */
+        if (ah->ah_version == AR5K_AR5212) {
+                u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
+                if (ah->ah_ack_bitrate_high)
+                        AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
+                else
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
+        }
+        return;
+}
diff --git a/drivers/net/wireless/ath/ath5k/phy.c b/drivers/net/wireless/ath/ath5k/phy.c
index 219367884e64..78c26fdccad1 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -29,6 +29,95 @@
 #include "rfbuffer.h"
 #include "rfgain.h"
 
+
+/******************\
+* Helper functions *
+\******************/
+
+/*
+ * Get the PHY Chip revision
+ */
+u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
+{
+        unsigned int i;
+        u32 srev;
+        u16 ret;
+
+        /*
+         * Set the radio chip access register
+         */
+        switch (chan) {
+        case CHANNEL_2GHZ:
+                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
+                break;
+        case CHANNEL_5GHZ:
+                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+                break;
+        default:
+                return 0;
+        }
+
+        mdelay(2);
+
+        /* ...wait until PHY is ready and read the selected radio revision */
+        ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
+
+        for (i = 0; i < 8; i++)
+                ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
+
+        if (ah->ah_version == AR5K_AR5210) {
+                srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
+                ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
+        } else {
+                srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
+                ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
+                                ((srev & 0x0f) << 4), 8);
+        }
+
+        /* Reset to the 5GHz mode */
+        ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+
+        return ret;
+}
+
+/*
+ * Check if a channel is supported
+ */
+bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
+{
+        /* Check if the channel is in our supported range */
+        if (flags & CHANNEL_2GHZ) {
+                if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
+                    (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
+                        return true;
+        } else if (flags & CHANNEL_5GHZ)
+                if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
+                    (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
+                        return true;
+
+        return false;
+}
+
+bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
+                                struct ieee80211_channel *channel)
+{
+        u8 refclk_freq;
+
+        if ((ah->ah_radio == AR5K_RF5112) ||
+        (ah->ah_radio == AR5K_RF5413) ||
+        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                refclk_freq = 40;
+        else
+                refclk_freq = 32;
+
+        if ((channel->center_freq % refclk_freq != 0) &&
+        ((channel->center_freq % refclk_freq < 10) ||
+        (channel->center_freq % refclk_freq > 22)))
+                return true;
+        else
+                return false;
+}
+
 /*
  * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
  */
@@ -110,6 +199,90 @@ static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
         return data;
 }
 
+/**
+ * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
+ *
+ * @ah: the &struct ath5k_hw
+ * @channel: the currently set channel upon reset
+ *
+ * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
+ * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
+ *
+ * Since delta slope is floating point we split it on its exponent and
+ * mantissa and provide these values on hw.
+ *
+ * For more infos i think this patent is related
+ * http://www.freepatentsonline.com/7184495.html
+ */
+static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
+        struct ieee80211_channel *channel)
+{
+        /* Get exponent and mantissa and set it */
+        u32 coef_scaled, coef_exp, coef_man,
+                ds_coef_exp, ds_coef_man, clock;
+
+        BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
+                !(channel->hw_value & CHANNEL_OFDM));
+
+        /* Get coefficient
+         * ALGO: coef = (5 * clock / carrier_freq) / 2
+         * we scale coef by shifting clock value by 24 for
+         * better precision since we use integers */
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                clock = 40 * 2;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                clock = 40 / 2;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                clock = 40 / 4;
+                break;
+        default:
+                clock = 40;
+                break;
+        }
+        coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
+
+        /* Get exponent
+         * ALGO: coef_exp = 14 - highest set bit position */
+        coef_exp = ilog2(coef_scaled);
+
+        /* Doesn't make sense if it's zero*/
+        if (!coef_scaled || !coef_exp)
+                return -EINVAL;
+
+        /* Note: we've shifted coef_scaled by 24 */
+        coef_exp = 14 - (coef_exp - 24);
+
+
+        /* Get mantissa (significant digits)
+         * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
+        coef_man = coef_scaled +
+                (1 << (24 - coef_exp - 1));
+
+        /* Calculate delta slope coefficient exponent
+         * and mantissa (remove scaling) and set them on hw */
+        ds_coef_man = coef_man >> (24 - coef_exp);
+        ds_coef_exp = coef_exp - 16;
+
+        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
+                AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
+        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
+                AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
+
+        return 0;
+}
+
+int ath5k_hw_phy_disable(struct ath5k_hw *ah)
+{
+        /*Just a try M.F.*/
+        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+
+        return 0;
+}
+
+
 /**********************\
 * RF Gain optimization *
 \**********************/
@@ -436,10 +609,10 @@ done:
 /* Write initial RF gain table to set the RF sensitivity
  * this one works on all RF chips and has nothing to do
  * with gain_F calibration */
-int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
+static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
 {
         const struct ath5k_ini_rfgain *ath5k_rfg;
-        unsigned int i, size;
+        unsigned int i, size, index;
 
         switch (ah->ah_radio) {
         case AR5K_RF5111:
@@ -471,17 +644,11 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
                 return -EINVAL;
         }
 
-        switch (freq) {
-        case AR5K_INI_RFGAIN_2GHZ:
-        case AR5K_INI_RFGAIN_5GHZ:
-                break;
-        default:
-                return -EINVAL;
-        }
+        index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
 
         for (i = 0; i < size; i++) {
                 AR5K_REG_WAIT(i);
-                ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
+                ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
                         (u32)ath5k_rfg[i].rfg_register);
         }
 
@@ -494,12 +661,11 @@ int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
 * RF Registers setup *
 \********************/
 
-
 /*
  * Setup RF registers by writing RF buffer on hw
  */
-int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
-                unsigned int mode)
+static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
+        struct ieee80211_channel *channel, unsigned int mode)
 {
         const struct ath5k_rf_reg *rf_regs;
         const struct ath5k_ini_rfbuffer *ini_rfb;
@@ -652,6 +818,11 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 
         g_step = &go->go_step[ah->ah_gain.g_step_idx];
 
+        /* Set turbo mode (N/A on RF5413) */
+        if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
+        (ah->ah_radio != AR5K_RF5413))
+                ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
+
         /* Bank Modifications (chip-specific) */
         if (ah->ah_radio == AR5K_RF5111) {
 
@@ -691,7 +862,23 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
                                                 AR5K_RF_PLO_SEL, true);
 
-                /* TODO: Half/quarter channel support */
+                /* Tweak power detectors for half/quarter rate support */
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
+                ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
+                        u8 wait_i;
+
+                        ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
+                                                AR5K_RF_WAIT_S, true);
+
+                        wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
+                                                        0x1f : 0x10;
+
+                        ath5k_hw_rfb_op(ah, rf_regs, wait_i,
+                                                AR5K_RF_WAIT_I, true);
+                        ath5k_hw_rfb_op(ah, rf_regs, 3,
+                                                AR5K_RF_MAX_TIME, true);
+
+                }
         }
 
         if (ah->ah_radio == AR5K_RF5112) {
@@ -789,8 +976,20 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
                                                 AR5K_RF_GAIN_I, true);
 
-                /* TODO: Half/quarter channel support */
+                /* Tweak power detector for half/quarter rates */
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
+                ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
+                        u8 pd_delay;
 
+                        pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
+                                                        0xf : 0x8;
+
+                        ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
+                                                AR5K_RF_PD_PERIOD_A, true);
+                        ath5k_hw_rfb_op(ah, rf_regs, 0xf,
+                                                AR5K_RF_PD_DELAY_A, true);
+
+                }
         }
 
         if (ah->ah_radio == AR5K_RF5413 &&
@@ -822,24 +1021,6 @@ int ath5k_hw_rfregs_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 \**************************/
 
 /*
- * Check if a channel is supported
- */
-bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
-{
-        /* Check if the channel is in our supported range */
-        if (flags & CHANNEL_2GHZ) {
-                if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
-                    (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
-                        return true;
-        } else if (flags & CHANNEL_5GHZ)
-                if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
-                    (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
-                        return true;
-
-        return false;
-}
-
-/*
  * Convertion needed for RF5110
  */
 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
@@ -1045,7 +1226,8 @@ static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
 /*
  * Set a channel on the radio chip
  */
-int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
+static int ath5k_hw_channel(struct ath5k_hw *ah,
+                struct ieee80211_channel *channel)
 {
         int ret;
         /*
@@ -1092,8 +1274,6 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
         }
 
         ah->ah_current_channel = channel;
-        ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
-        ath5k_hw_set_clockrate(ah);
 
         return 0;
 }
@@ -1102,18 +1282,12 @@ int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
   PHY calibration
 \*****************/
 
-static int sign_extend(int val, const int nbits)
-{
-        int order = BIT(nbits-1);
-        return (val ^ order) - order;
-}
-
 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
 {
         s32 val;
 
         val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
-        return sign_extend(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 9);
+        return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
 }
 
 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
@@ -1181,22 +1355,7 @@ void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
                 return;
         }
 
-        switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
-        case CHANNEL_A:
-        case CHANNEL_T:
-        case CHANNEL_XR:
-                ee_mode = AR5K_EEPROM_MODE_11A;
-                break;
-        case CHANNEL_G:
-        case CHANNEL_TG:
-                ee_mode = AR5K_EEPROM_MODE_11G;
-                break;
-        default:
-        case CHANNEL_B:
-                ee_mode = AR5K_EEPROM_MODE_11B;
-                break;
-        }
-
+        ee_mode = ath5k_eeprom_mode_from_channel(ah->ah_current_channel);
 
         /* completed NF calibration, test threshold */
         nf = ath5k_hw_read_measured_noise_floor(ah);
@@ -1425,31 +1584,12 @@ int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
         return ret;
 }
 
+
 /***************************\
 * Spur mitigation functions *
 \***************************/
 
-bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
-                                struct ieee80211_channel *channel)
-{
-        u8 refclk_freq;
-
-        if ((ah->ah_radio == AR5K_RF5112) ||
-        (ah->ah_radio == AR5K_RF5413) ||
-        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                refclk_freq = 40;
-        else
-                refclk_freq = 32;
-
-        if ((channel->center_freq % refclk_freq != 0) &&
-        ((channel->center_freq % refclk_freq < 10) ||
-        (channel->center_freq % refclk_freq > 22)))
-                return true;
-        else
-                return false;
-}
-
-void
+static void
 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
                                 struct ieee80211_channel *channel)
 {
@@ -1478,7 +1618,7 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
         spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
         spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
         /* XXX: Half/Quarter channels ?*/
-        if (channel->hw_value & CHANNEL_TURBO)
+        if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
                 spur_detection_window *= 2;
 
         for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
@@ -1507,32 +1647,43 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
                  * Calculate deltas:
                  * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
                  * spur_delta_phase -> spur_offset / chip_freq << 11
-                 * Note: Both values have 100KHz resolution
+                 * Note: Both values have 100Hz resolution
                  */
-                /* XXX: Half/Quarter rate channels ? */
-                switch (channel->hw_value) {
-                case CHANNEL_A:
-                        /* Both sample_freq and chip_freq are 40MHz */
-                        spur_delta_phase = (spur_offset << 17) / 25;
-                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
-                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
-                        break;
-                case CHANNEL_G:
-                        /* sample_freq -> 40MHz chip_freq -> 44MHz
-                         * (for b compatibility) */
-                        spur_freq_sigma_delta = (spur_offset << 8) / 55;
-                        spur_delta_phase = (spur_offset << 17) / 25;
-                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
-                        break;
-                case CHANNEL_T:
-                case CHANNEL_TG:
+                switch (ah->ah_bwmode) {
+                case AR5K_BWMODE_40MHZ:
                         /* Both sample_freq and chip_freq are 80MHz */
                         spur_delta_phase = (spur_offset << 16) / 25;
                         spur_freq_sigma_delta = (spur_delta_phase >> 10);
-                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz;
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
                         break;
+                case AR5K_BWMODE_10MHZ:
+                        /* Both sample_freq and chip_freq are 20MHz (?) */
+                        spur_delta_phase = (spur_offset << 18) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
+                case AR5K_BWMODE_5MHZ:
+                        /* Both sample_freq and chip_freq are 10MHz (?) */
+                        spur_delta_phase = (spur_offset << 19) / 25;
+                        spur_freq_sigma_delta = (spur_delta_phase >> 10);
+                        symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
                 default:
-                        return;
+                        if (channel->hw_value == CHANNEL_A) {
+                                /* Both sample_freq and chip_freq are 40MHz */
+                                spur_delta_phase = (spur_offset << 17) / 25;
+                                spur_freq_sigma_delta =
+                                                (spur_delta_phase >> 10);
+                                symbol_width =
+                                        AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        } else {
+                                /* sample_freq -> 40MHz chip_freq -> 44MHz
+                                 * (for b compatibility) */
+                                spur_delta_phase = (spur_offset << 17) / 25;
+                                spur_freq_sigma_delta =
+                                                (spur_offset << 8) / 55;
+                                symbol_width =
+                                        AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
+                        }
+                        break;
                 }
 
                 /* Calculate pilot and magnitude masks */
@@ -1672,63 +1823,6 @@ ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
         }
 }
 
-/********************\
-  Misc PHY functions
-\********************/
-
-int ath5k_hw_phy_disable(struct ath5k_hw *ah)
-{
-        /*Just a try M.F.*/
-        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
-
-        return 0;
-}
-
-/*
- * Get the PHY Chip revision
- */
-u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
-{
-        unsigned int i;
-        u32 srev;
-        u16 ret;
-
-        /*
-         * Set the radio chip access register
-         */
-        switch (chan) {
-        case CHANNEL_2GHZ:
-                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
-                break;
-        case CHANNEL_5GHZ:
-                ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
-                break;
-        default:
-                return 0;
-        }
-
-        mdelay(2);
-
-        /* ...wait until PHY is ready and read the selected radio revision */
-        ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
-
-        for (i = 0; i < 8; i++)
-                ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
-
-        if (ah->ah_version == AR5K_AR5210) {
-                srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
-                ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
-        } else {
-                srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
-                ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
-                                ((srev & 0x0f) << 4), 8);
-        }
-
-        /* Reset to the 5GHz mode */
-        ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
-
-        return ret;
-}
 
 /*****************\
 * Antenna control *
@@ -1822,7 +1916,8 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
         struct ieee80211_channel *channel = ah->ah_current_channel;
         bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
         bool use_def_for_sg;
-        u8 def_ant, tx_ant, ee_mode;
+        int ee_mode;
+        u8 def_ant, tx_ant;
         u32 sta_id1 = 0;
 
         /* if channel is not initialized yet we can't set the antennas
@@ -1834,20 +1929,8 @@ ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
 
         def_ant = ah->ah_def_ant;
 
-        switch (channel->hw_value & CHANNEL_MODES) {
-        case CHANNEL_A:
-        case CHANNEL_T:
-        case CHANNEL_XR:
-                ee_mode = AR5K_EEPROM_MODE_11A;
-                break;
-        case CHANNEL_G:
-        case CHANNEL_TG:
-                ee_mode = AR5K_EEPROM_MODE_11G;
-                break;
-        case CHANNEL_B:
-                ee_mode = AR5K_EEPROM_MODE_11B;
-                break;
-        default:
+        ee_mode = ath5k_eeprom_mode_from_channel(channel);
+        if (ee_mode < 0) {
                 ATH5K_ERR(ah->ah_sc,
                         "invalid channel: %d\n", channel->center_freq);
                 return;
@@ -2275,20 +2358,20 @@ ath5k_get_max_ctl_power(struct ath5k_hw *ah,
 
         switch (channel->hw_value & CHANNEL_MODES) {
         case CHANNEL_A:
-                ctl_mode |= AR5K_CTL_11A;
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
+                        ctl_mode |= AR5K_CTL_TURBO;
+                else
+                        ctl_mode |= AR5K_CTL_11A;
                 break;
         case CHANNEL_G:
-                ctl_mode |= AR5K_CTL_11G;
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
+                        ctl_mode |= AR5K_CTL_TURBOG;
+                else
+                        ctl_mode |= AR5K_CTL_11G;
                 break;
         case CHANNEL_B:
                 ctl_mode |= AR5K_CTL_11B;
                 break;
-        case CHANNEL_T:
-                ctl_mode |= AR5K_CTL_TURBO;
-                break;
-        case CHANNEL_TG:
-                ctl_mode |= AR5K_CTL_TURBOG;
-                break;
         case CHANNEL_XR:
                 /* Fall through */
         default:
@@ -2482,7 +2565,7 @@ ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
 
 /* Write PCDAC values on hw */
 static void
-ath5k_setup_pcdac_table(struct ath5k_hw *ah)
+ath5k_write_pcdac_table(struct ath5k_hw *ah)
 {
         u8      *pcdac_out = ah->ah_txpower.txp_pd_table;
         int     i;
@@ -2631,10 +2714,12 @@ ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
 
 /* Write PDADC values on hw */
 static void
-ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
-                        u8 pdcurves, u8 *pdg_to_idx)
+ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
 {
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
+        u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
+        u8 pdcurves = ee->ee_pd_gains[ee_mode];
         u32 reg;
         u8 i;
 
@@ -2844,8 +2929,7 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                                         (s16) pcinfo_R->freq,
                                         pcinfo_L->max_pwr, pcinfo_R->max_pwr);
 
-        /* We are ready to go, fill PCDAC/PDADC
-         * table and write settings on hardware */
+        /* Fill PCDAC/PDADC table */
         switch (type) {
         case AR5K_PWRTABLE_LINEAR_PCDAC:
                 /* For RF5112 we can have one or two curves
@@ -2858,9 +2942,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                  * match max power value with max
                  * table index */
                 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
-
-                /* Write settings on hw */
-                ath5k_setup_pcdac_table(ah);
                 break;
         case AR5K_PWRTABLE_PWR_TO_PCDAC:
                 /* We are done for RF5111 since it has only
@@ -2870,9 +2951,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 /* No rate powertable adjustment for RF5111 */
                 ah->ah_txpower.txp_min_idx = 0;
                 ah->ah_txpower.txp_offset = 0;
-
-                /* Write settings on hw */
-                ath5k_setup_pcdac_table(ah);
                 break;
         case AR5K_PWRTABLE_PWR_TO_PDADC:
                 /* Set PDADC boundaries and fill
@@ -2880,9 +2958,6 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
                                                 ee->ee_pd_gains[ee_mode]);
 
-                /* Write settings on hw */
-                ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
-
                 /* Set txp.offset, note that table_min
                  * can be negative */
                 ah->ah_txpower.txp_offset = table_min[0];
@@ -2891,9 +2966,20 @@ ath5k_setup_channel_powertable(struct ath5k_hw *ah,
                 return -EINVAL;
         }
 
+        ah->ah_txpower.txp_setup = true;
+
         return 0;
 }
 
+/* Write power table for current channel to hw */
+static void
+ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
+{
+        if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
+                ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
+        else
+                ath5k_write_pcdac_table(ah);
+}
 
 /*
  * Per-rate tx power setting
@@ -2982,7 +3068,7 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
 
         /* Min/max in 0.25dB units */
         ah->ah_txpower.txp_min_pwr = 2 * rates[7];
-        ah->ah_txpower.txp_max_pwr = 2 * rates[0];
+        ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
         ah->ah_txpower.txp_ofdm = rates[7];
 }
 
@@ -2990,11 +3076,13 @@ ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
 /*
  * Set transmission power
  */
-int
+static int
 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
-                u8 ee_mode, u8 txpower)
+                 u8 txpower)
 {
         struct ath5k_rate_pcal_info rate_info;
+        struct ieee80211_channel *curr_channel = ah->ah_current_channel;
+        int ee_mode;
         u8 type;
         int ret;
 
@@ -3003,14 +3091,18 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 return -EINVAL;
         }
 
-        /* Reset TX power values */
-        memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
-        ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
-        ah->ah_txpower.txp_min_pwr = 0;
-        ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
+        ee_mode = ath5k_eeprom_mode_from_channel(channel);
+        if (ee_mode < 0) {
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return -EINVAL;
+        }
 
         /* Initialize TX power table */
         switch (ah->ah_radio) {
+        case AR5K_RF5110:
+                /* TODO */
+                return 0;
         case AR5K_RF5111:
                 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
                 break;
@@ -3028,10 +3120,26 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
                 return -EINVAL;
         }
 
-        /* FIXME: Only on channel/mode change */
-        ret = ath5k_setup_channel_powertable(ah, channel, ee_mode, type);
-        if (ret)
-                return ret;
+        /*
+         * If we don't change channel/mode skip tx powertable calculation
+         * and use the cached one.
+         */
+        if (!ah->ah_txpower.txp_setup ||
+            (channel->hw_value != curr_channel->hw_value) ||
+            (channel->center_freq != curr_channel->center_freq)) {
+                /* Reset TX power values */
+                memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
+                ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
+
+                /* Calculate the powertable */
+                ret = ath5k_setup_channel_powertable(ah, channel,
+                                                        ee_mode, type);
+                if (ret)
+                        return ret;
+        }
+
+        /* Write table on hw */
+        ath5k_write_channel_powertable(ah, ee_mode, type);
 
         /* Limit max power if we have a CTL available */
         ath5k_get_max_ctl_power(ah, channel);
@@ -3086,31 +3194,219 @@ ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
 
 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
 {
-        /*Just a try M.F.*/
-        struct ieee80211_channel *channel = ah->ah_current_channel;
-        u8 ee_mode;
+        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
+                "changing txpower to %d\n", txpower);
 
-        switch (channel->hw_value & CHANNEL_MODES) {
-        case CHANNEL_A:
-        case CHANNEL_T:
-        case CHANNEL_XR:
-                ee_mode = AR5K_EEPROM_MODE_11A;
-                break;
-        case CHANNEL_G:
-        case CHANNEL_TG:
-                ee_mode = AR5K_EEPROM_MODE_11G;
-                break;
-        case CHANNEL_B:
-                ee_mode = AR5K_EEPROM_MODE_11B;
-                break;
-        default:
-                ATH5K_ERR(ah->ah_sc,
-                        "invalid channel: %d\n", channel->center_freq);
+        return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
+}
+
+/*************\
+ Init function
+\*************/
+
+int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
+                      u8 mode, bool fast)
+{
+        struct ieee80211_channel *curr_channel;
+        int ret, i;
+        u32 phy_tst1;
+        ret = 0;
+
+        /*
+         * Sanity check for fast flag
+         * Don't try fast channel change when changing modulation
+         * mode/band. We check for chip compatibility on
+         * ath5k_hw_reset.
+         */
+        curr_channel = ah->ah_current_channel;
+        if (fast && (channel->hw_value != curr_channel->hw_value))
                 return -EINVAL;
+
+        /*
+         * On fast channel change we only set the synth parameters
+         * while PHY is running, enable calibration and skip the rest.
+         */
+        if (fast) {
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
+                                    AR5K_PHY_RFBUS_REQ_REQUEST);
+                for (i = 0; i < 100; i++) {
+                        if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
+                                break;
+                        udelay(5);
+                }
+                /* Failed */
+                if (i >= 100)
+                        return -EIO;
         }
 
-        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
-                "changing txpower to %d\n", txpower);
+        /*
+         * Set TX power
+         *
+         * Note: We need to do that before we set
+         * RF buffer settings on 5211/5212+ so that we
+         * properly set curve indices.
+         */
+        ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_cur_pwr ?
+                        ah->ah_txpower.txp_cur_pwr / 2 : AR5K_TUNE_MAX_TXPOWER);
+        if (ret)
+                return ret;
+
+        /*
+         * For 5210 we do all initialization using
+         * initvals, so we don't have to modify
+         * any settings (5210 also only supports
+         * a/aturbo modes)
+         */
+        if ((ah->ah_version != AR5K_AR5210) && !fast) {
+
+                /*
+                 * Write initial RF gain settings
+                 * This should work for both 5111/5112
+                 */
+                ret = ath5k_hw_rfgain_init(ah, channel->band);
+                if (ret)
+                        return ret;
+
+                mdelay(1);
+
+                /*
+                 * Write RF buffer
+                 */
+                ret = ath5k_hw_rfregs_init(ah, channel, mode);
+                if (ret)
+                        return ret;
+
+                /* Write OFDM timings on 5212*/
+                if (ah->ah_version == AR5K_AR5212 &&
+                        channel->hw_value & CHANNEL_OFDM) {
+
+                        ret = ath5k_hw_write_ofdm_timings(ah, channel);
+                        if (ret)
+                                return ret;
+
+                        /* Spur info is available only from EEPROM versions
+                         * greater than 5.3, but the EEPROM routines will use
+                         * static values for older versions */
+                        if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
+                                ath5k_hw_set_spur_mitigation_filter(ah,
+                                                                    channel);
+                }
+
+                /*Enable/disable 802.11b mode on 5111
+                (enable 2111 frequency converter + CCK)*/
+                if (ah->ah_radio == AR5K_RF5111) {
+                        if (mode == AR5K_MODE_11B)
+                                AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
+                                    AR5K_TXCFG_B_MODE);
+                        else
+                                AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
+                                    AR5K_TXCFG_B_MODE);
+                }
+
+        } else if (ah->ah_version == AR5K_AR5210) {
+                mdelay(1);
+                /* Disable phy and wait */
+                ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+                mdelay(1);
+        }
+
+        /* Set channel on PHY */
+        ret = ath5k_hw_channel(ah, channel);
+        if (ret)
+                return ret;
+
+        /*
+         * Enable the PHY and wait until completion
+         * This includes BaseBand and Synthesizer
+         * activation.
+         */
+        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
+
+        /*
+         * On 5211+ read activation -> rx delay
+         * and use it.
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                u32 delay;
+                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
+                        AR5K_PHY_RX_DELAY_M;
+                delay = (channel->hw_value & CHANNEL_CCK) ?
+                        ((delay << 2) / 22) : (delay / 10);
+                if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
+                        delay = delay << 1;
+                if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
+                        delay = delay << 2;
+                /* XXX: /2 on turbo ? Let's be safe
+                 * for now */
+                udelay(100 + delay);
+        } else {
+                mdelay(1);
+        }
+
+        if (fast)
+                /*
+                 * Release RF Bus grant
+                 */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
+                                    AR5K_PHY_RFBUS_REQ_REQUEST);
+        else {
+                /*
+                 * Perform ADC test to see if baseband is ready
+                 * Set tx hold and check adc test register
+                 */
+                phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
+                ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
+                for (i = 0; i <= 20; i++) {
+                        if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
+                                break;
+                        udelay(200);
+                }
+                ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
+        }
+
+        /*
+         * Start automatic gain control calibration
+         *
+         * During AGC calibration RX path is re-routed to
+         * a power detector so we don't receive anything.
+         *
+         * This method is used to calibrate some static offsets
+         * used together with on-the fly I/Q calibration (the
+         * one performed via ath5k_hw_phy_calibrate), which doesn't
+         * interrupt rx path.
+         *
+         * While rx path is re-routed to the power detector we also
+         * start a noise floor calibration to measure the
+         * card's noise floor (the noise we measure when we are not
+         * transmitting or receiving anything).
+         *
+         * If we are in a noisy environment, AGC calibration may time
+         * out and/or noise floor calibration might timeout.
+         */
+        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
+                                AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
+
+        /* At the same time start I/Q calibration for QAM constellation
+         * -no need for CCK- */
+        ah->ah_calibration = false;
+        if (!(mode == AR5K_MODE_11B)) {
+                ah->ah_calibration = true;
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
+                                AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
+                                AR5K_PHY_IQ_RUN);
+        }
+
+        /* Wait for gain calibration to finish (we check for I/Q calibration
+         * during ath5k_phy_calibrate) */
+        if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
+                        AR5K_PHY_AGCCTL_CAL, 0, false)) {
+                ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
+                        channel->center_freq);
+        }
+
+        /* Restore antenna mode */
+        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
 
-        return ath5k_hw_txpower(ah, channel, ee_mode, txpower);
+        return ret;
 }
diff --git a/drivers/net/wireless/ath/ath5k/qcu.c b/drivers/net/wireless/ath/ath5k/qcu.c
index 84c717ded1c5..2c9c9e793d4e 100644
--- a/drivers/net/wireless/ath/ath5k/qcu.c
+++ b/drivers/net/wireless/ath/ath5k/qcu.c
@@ -25,14 +25,52 @@ Queue Control Unit, DFS Control Unit Functions
 #include "debug.h"
 #include "base.h"
 
+
+/******************\
+* Helper functions *
+\******************/
+
 /*
- * Get properties for a transmit queue
+ * Get number of pending frames
+ * for a specific queue [5211+]
  */
-int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
-                struct ath5k_txq_info *queue_info)
+u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
 {
-        memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
-        return 0;
+        u32 pending;
+        AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
+
+        /* Return if queue is declared inactive */
+        if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
+                return false;
+
+        /* XXX: How about AR5K_CFG_TXCNT ? */
+        if (ah->ah_version == AR5K_AR5210)
+                return false;
+
+        pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
+        pending &= AR5K_QCU_STS_FRMPENDCNT;
+
+        /* It's possible to have no frames pending even if TXE
+         * is set. To indicate that q has not stopped return
+         * true */
+        if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
+                return true;
+
+        return pending;
+}
+
+/*
+ * Set a transmit queue inactive
+ */
+void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+{
+        if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
+                return;
+
+        /* This queue will be skipped in further operations */
+        ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
+        /*For SIMR setup*/
+        AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
 }
 
 /*
@@ -50,6 +88,16 @@ static u16 ath5k_cw_validate(u16 cw_req)
 }
 
 /*
+ * Get properties for a transmit queue
+ */
+int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
+                struct ath5k_txq_info *queue_info)
+{
+        memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
+        return 0;
+}
+
+/*
  * Set properties for a transmit queue
  */
 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
@@ -104,8 +152,8 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
         /*
          * Get queue by type
          */
-        /*5210 only has 2 queues*/
-        if (ah->ah_version == AR5K_AR5210) {
+        /* 5210 only has 2 queues */
+        if (ah->ah_capabilities.cap_queues.q_tx_num == 2) {
                 switch (queue_type) {
                 case AR5K_TX_QUEUE_DATA:
                         queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
@@ -172,113 +220,18 @@ int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
         return queue;
 }
 
-/*
- * Get number of pending frames
- * for a specific queue [5211+]
- */
-u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)
-{
-        u32 pending;
-        AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
-
-        /* Return if queue is declared inactive */
-        if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return false;
-
-        /* XXX: How about AR5K_CFG_TXCNT ? */
-        if (ah->ah_version == AR5K_AR5210)
-                return false;
-
-        pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));
-        pending &= AR5K_QCU_STS_FRMPENDCNT;
-
-        /* It's possible to have no frames pending even if TXE
-         * is set. To indicate that q has not stopped return
-         * true */
-        if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
-                return true;
-
-        return pending;
-}
-
-/*
- * Set a transmit queue inactive
- */
-void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
-{
-        if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
-                return;
 
-        /* This queue will be skipped in further operations */
-        ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
-        /*For SIMR setup*/
-        AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
-}
+/*******************************\
+* Single QCU/DCU initialization *
+\*******************************/
 
 /*
- * Set DFS properties for a transmit queue on DCU
+ * Set tx retry limits on DCU
  */
-int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+static void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
+                                        unsigned int queue)
 {
         u32 retry_lg, retry_sh;
-        struct ath5k_txq_info *tq = &ah->ah_txq[queue];
-
-        AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
-
-        tq = &ah->ah_txq[queue];
-
-        if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
-                return 0;
-
-        if (ah->ah_version == AR5K_AR5210) {
-                /* Only handle data queues, others will be ignored */
-                if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
-                        return 0;
-
-                /* Set Slot time */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
-                        AR5K_SLOT_TIME);
-                /* Set ACK_CTS timeout */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
-                        AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
-                /* Set Transmit Latency */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_TRANSMIT_LATENCY_TURBO :
-                        AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
-
-                /* Set IFS0 */
-                if (ah->ah_turbo) {
-                         ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
-                                tq->tqi_aifs * AR5K_INIT_SLOT_TIME_TURBO) <<
-                                AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
-                                AR5K_IFS0);
-                } else {
-                        ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
-                                tq->tqi_aifs * AR5K_INIT_SLOT_TIME) <<
-                                AR5K_IFS0_DIFS_S) |
-                                AR5K_INIT_SIFS, AR5K_IFS0);
-                }
-
-                /* Set IFS1 */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
-                        AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
-                /* Set AR5K_PHY_SETTLING */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
-                        | 0x38 :
-                        (ath5k_hw_reg_read(ah, AR5K_PHY_SETTLING) & ~0x7F)
-                        | 0x1C,
-                        AR5K_PHY_SETTLING);
-                /* Set Frame Control Register */
-                ath5k_hw_reg_write(ah, ah->ah_turbo ?
-                        (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
-                        AR5K_PHY_TURBO_SHORT | 0x2020) :
-                        (AR5K_PHY_FRAME_CTL_INI | 0x1020),
-                        AR5K_PHY_FRAME_CTL_5210);
-        }
 
         /*
          * Calculate and set retry limits
@@ -293,8 +246,13 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
                 retry_sh = AR5K_INIT_SH_RETRY;
         }
 
-        /*No QCU/DCU [5210]*/
+        /* Single data queue on AR5210 */
         if (ah->ah_version == AR5K_AR5210) {
+                struct ath5k_txq_info *tq = &ah->ah_txq[queue];
+
+                if (queue > 0)
+                        return;
+
                 ath5k_hw_reg_write(ah,
                         (tq->tqi_cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
                         | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
@@ -304,8 +262,8 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
                         | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
                         | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
                         AR5K_NODCU_RETRY_LMT);
+        /* DCU on AR5211+ */
         } else {
-                /*QCU/DCU [5211+]*/
                 ath5k_hw_reg_write(ah,
                         AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
                                 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
@@ -314,219 +272,393 @@ int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
                         AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
                         AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
                         AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
+        }
+        return;
+}
 
-        /*===Rest is also for QCU/DCU only [5211+]===*/
+/**
+ * ath5k_hw_reset_tx_queue - Initialize a single hw queue
+ *
+ * @ah The &struct ath5k_hw
+ * @queue The hw queue number
+ *
+ * Set DFS properties for the given transmit queue on DCU
+ * and configures all queue-specific parameters.
+ */
+int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
+{
+        struct ath5k_txq_info *tq = &ah->ah_txq[queue];
 
-                /*
-                 * Set contention window (cw_min/cw_max)
-                 * and arbitrated interframe space (aifs)...
-                 */
-                ath5k_hw_reg_write(ah,
-                        AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
-                        AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
-                        AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),
-                        AR5K_QUEUE_DFS_LOCAL_IFS(queue));
-
-                /*
-                 * Set misc registers
-                 */
-                /* Enable DCU early termination for this queue */
-                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                        AR5K_QCU_MISC_DCU_EARLY);
+        AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
+
+        tq = &ah->ah_txq[queue];
+
+        /* Skip if queue inactive or if we are on AR5210
+         * that doesn't have QCU/DCU */
+        if ((ah->ah_version == AR5K_AR5210) ||
+        (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE))
+                return 0;
+
+        /*
+         * Set contention window (cw_min/cw_max)
+         * and arbitrated interframe space (aifs)...
+         */
+        ath5k_hw_reg_write(ah,
+                AR5K_REG_SM(tq->tqi_cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
+                AR5K_REG_SM(tq->tqi_cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
+                AR5K_REG_SM(tq->tqi_aifs, AR5K_DCU_LCL_IFS_AIFS),
+                AR5K_QUEUE_DFS_LOCAL_IFS(queue));
+
+        /*
+         * Set tx retry limits for this queue
+         */
+        ath5k_hw_set_tx_retry_limits(ah, queue);
+
+
+        /*
+         * Set misc registers
+         */
+
+        /* Enable DCU to wait for next fragment from QCU */
+        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                                AR5K_DCU_MISC_FRAG_WAIT);
 
-                /* Enable DCU to wait for next fragment from QCU */
+        /* On Maui and Spirit use the global seqnum on DCU */
+        if (ah->ah_mac_version < AR5K_SREV_AR5211)
                 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
-                                        AR5K_DCU_MISC_FRAG_WAIT);
-
-                /* On Maui and Spirit use the global seqnum on DCU */
-                if (ah->ah_mac_version < AR5K_SREV_AR5211)
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
-                                                AR5K_DCU_MISC_SEQNUM_CTL);
-
-                if (tq->tqi_cbr_period) {
-                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
-                                AR5K_QCU_CBRCFG_INTVAL) |
-                                AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
-                                AR5K_QCU_CBRCFG_ORN_THRES),
-                                AR5K_QUEUE_CBRCFG(queue));
+                                        AR5K_DCU_MISC_SEQNUM_CTL);
+
+        /* Constant bit rate period */
+        if (tq->tqi_cbr_period) {
+                ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
+                                        AR5K_QCU_CBRCFG_INTVAL) |
+                                        AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
+                                        AR5K_QCU_CBRCFG_ORN_THRES),
+                                        AR5K_QUEUE_CBRCFG(queue));
+
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_FRSHED_CBR);
+
+                if (tq->tqi_cbr_overflow_limit)
                         AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_FRSHED_CBR);
-                        if (tq->tqi_cbr_overflow_limit)
-                                AR5K_REG_ENABLE_BITS(ah,
-                                        AR5K_QUEUE_MISC(queue),
                                         AR5K_QCU_MISC_CBR_THRES_ENABLE);
-                }
+        }
 
-                if (tq->tqi_ready_time &&
-                (tq->tqi_type != AR5K_TX_QUEUE_CAB))
-                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
-                                AR5K_QCU_RDYTIMECFG_INTVAL) |
-                                AR5K_QCU_RDYTIMECFG_ENABLE,
-                                AR5K_QUEUE_RDYTIMECFG(queue));
-
-                if (tq->tqi_burst_time) {
-                        ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
-                                AR5K_DCU_CHAN_TIME_DUR) |
-                                AR5K_DCU_CHAN_TIME_ENABLE,
-                                AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
-
-                        if (tq->tqi_flags
-                        & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
-                                AR5K_REG_ENABLE_BITS(ah,
-                                        AR5K_QUEUE_MISC(queue),
+        /* Ready time interval */
+        if (tq->tqi_ready_time && (tq->tqi_type != AR5K_TX_QUEUE_CAB))
+                ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
+                                        AR5K_QCU_RDYTIMECFG_INTVAL) |
+                                        AR5K_QCU_RDYTIMECFG_ENABLE,
+                                        AR5K_QUEUE_RDYTIMECFG(queue));
+
+        if (tq->tqi_burst_time) {
+                ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
+                                        AR5K_DCU_CHAN_TIME_DUR) |
+                                        AR5K_DCU_CHAN_TIME_ENABLE,
+                                        AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
+
+                if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
+                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                         AR5K_QCU_MISC_RDY_VEOL_POLICY);
-                }
+        }
 
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
-                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
-                                AR5K_QUEUE_DFS_MISC(queue));
+        /* Enable/disable Post frame backoff */
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
+                ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
+                                        AR5K_QUEUE_DFS_MISC(queue));
 
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
-                        ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
-                                AR5K_QUEUE_DFS_MISC(queue));
+        /* Enable/disable fragmentation burst backoff */
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
+                ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
+                                        AR5K_QUEUE_DFS_MISC(queue));
 
-                /*
-                 * Set registers by queue type
-                 */
-                switch (tq->tqi_type) {
-                case AR5K_TX_QUEUE_BEACON:
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+        /*
+         * Set registers by queue type
+         */
+        switch (tq->tqi_type) {
+        case AR5K_TX_QUEUE_BEACON:
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
                                 AR5K_QCU_MISC_FRSHED_DBA_GT |
                                 AR5K_QCU_MISC_CBREXP_BCN_DIS |
                                 AR5K_QCU_MISC_BCN_ENABLE);
 
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
                                 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
                                 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
                                 AR5K_DCU_MISC_ARBLOCK_IGNORE |
                                 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
                                 AR5K_DCU_MISC_BCN_ENABLE);
-                        break;
+                break;
 
-                case AR5K_TX_QUEUE_CAB:
-                        /* XXX: use BCN_SENT_GT, if we can figure out how */
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_FRSHED_DBA_GT |
-                                AR5K_QCU_MISC_CBREXP_DIS |
-                                AR5K_QCU_MISC_CBREXP_BCN_DIS);
+        case AR5K_TX_QUEUE_CAB:
+                /* XXX: use BCN_SENT_GT, if we can figure out how */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_FRSHED_DBA_GT |
+                                        AR5K_QCU_MISC_CBREXP_DIS |
+                                        AR5K_QCU_MISC_CBREXP_BCN_DIS);
 
-                        ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -
-                                (AR5K_TUNE_SW_BEACON_RESP -
-                                AR5K_TUNE_DMA_BEACON_RESP) -
+                ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -
+                                        (AR5K_TUNE_SW_BEACON_RESP -
+                                        AR5K_TUNE_DMA_BEACON_RESP) -
                                 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
-                                AR5K_QCU_RDYTIMECFG_ENABLE,
-                                AR5K_QUEUE_RDYTIMECFG(queue));
+                                        AR5K_QCU_RDYTIMECFG_ENABLE,
+                                        AR5K_QUEUE_RDYTIMECFG(queue));
 
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
-                                (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
-                                AR5K_DCU_MISC_ARBLOCK_CTL_S));
-                        break;
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
+                                        (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
+                                        AR5K_DCU_MISC_ARBLOCK_CTL_S));
+                break;
 
-                case AR5K_TX_QUEUE_UAPSD:
-                        AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
-                                AR5K_QCU_MISC_CBREXP_DIS);
-                        break;
+        case AR5K_TX_QUEUE_UAPSD:
+                AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
+                                        AR5K_QCU_MISC_CBREXP_DIS);
+                break;
 
-                case AR5K_TX_QUEUE_DATA:
-                default:
+        case AR5K_TX_QUEUE_DATA:
+        default:
                         break;
-                }
-
-                /* TODO: Handle frame compression */
-
-                /*
-                 * Enable interrupts for this tx queue
-                 * in the secondary interrupt mask registers
-                 */
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
-
-                if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
-                        AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
-
-                /* Update secondary interrupt mask registers */
-
-                /* Filter out inactive queues */
-                ah->ah_txq_imr_txok &= ah->ah_txq_status;
-                ah->ah_txq_imr_txerr &= ah->ah_txq_status;
-                ah->ah_txq_imr_txurn &= ah->ah_txq_status;
-                ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
-                ah->ah_txq_imr_txeol &= ah->ah_txq_status;
-                ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
-                ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
-                ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
-                ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
-
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
-                        AR5K_SIMR0_QCU_TXOK) |
-                        AR5K_REG_SM(ah->ah_txq_imr_txdesc,
-                        AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
-                        AR5K_SIMR1_QCU_TXERR) |
-                        AR5K_REG_SM(ah->ah_txq_imr_txeol,
-                        AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
-                /* Update simr2 but don't overwrite rest simr2 settings */
-                AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
-                AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
-                        AR5K_REG_SM(ah->ah_txq_imr_txurn,
-                        AR5K_SIMR2_QCU_TXURN));
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
-                        AR5K_SIMR3_QCBRORN) |
-                        AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
-                        AR5K_SIMR3_QCBRURN), AR5K_SIMR3);
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
-                        AR5K_SIMR4_QTRIG), AR5K_SIMR4);
-                /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
-                ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
-                        AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
-                /* No queue has TXNOFRM enabled, disable the interrupt
-                 * by setting AR5K_TXNOFRM to zero */
-                if (ah->ah_txq_imr_nofrm == 0)
-                        ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
-
-                /* Set QCU mask for this DCU to save power */
-                AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
         }
 
+        /* TODO: Handle frame compression */
+
+        /*
+         * Enable interrupts for this tx queue
+         * in the secondary interrupt mask registers
+         */
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRORNINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_CBRURNINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_QTRIGINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);
+
+        if (tq->tqi_flags & AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE)
+                AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);
+
+        /* Update secondary interrupt mask registers */
+
+        /* Filter out inactive queues */
+        ah->ah_txq_imr_txok &= ah->ah_txq_status;
+        ah->ah_txq_imr_txerr &= ah->ah_txq_status;
+        ah->ah_txq_imr_txurn &= ah->ah_txq_status;
+        ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
+        ah->ah_txq_imr_txeol &= ah->ah_txq_status;
+        ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;
+        ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;
+        ah->ah_txq_imr_qtrig &= ah->ah_txq_status;
+        ah->ah_txq_imr_nofrm &= ah->ah_txq_status;
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
+                                        AR5K_SIMR0_QCU_TXOK) |
+                                        AR5K_REG_SM(ah->ah_txq_imr_txdesc,
+                                        AR5K_SIMR0_QCU_TXDESC),
+                                        AR5K_SIMR0);
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
+                                        AR5K_SIMR1_QCU_TXERR) |
+                                        AR5K_REG_SM(ah->ah_txq_imr_txeol,
+                                        AR5K_SIMR1_QCU_TXEOL),
+                                        AR5K_SIMR1);
+
+        /* Update SIMR2 but don't overwrite rest simr2 settings */
+        AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);
+        AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,
+                                AR5K_REG_SM(ah->ah_txq_imr_txurn,
+                                AR5K_SIMR2_QCU_TXURN));
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,
+                                AR5K_SIMR3_QCBRORN) |
+                                AR5K_REG_SM(ah->ah_txq_imr_cbrurn,
+                                AR5K_SIMR3_QCBRURN),
+                                AR5K_SIMR3);
+
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,
+                                AR5K_SIMR4_QTRIG), AR5K_SIMR4);
+
+        /* Set TXNOFRM_QCU for the queues with TXNOFRM enabled */
+        ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,
+                                AR5K_TXNOFRM_QCU), AR5K_TXNOFRM);
+
+        /* No queue has TXNOFRM enabled, disable the interrupt
+         * by setting AR5K_TXNOFRM to zero */
+        if (ah->ah_txq_imr_nofrm == 0)
+                ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);
+
+        /* Set QCU mask for this DCU to save power */
+        AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);
+
         return 0;
 }
 
-/*
- * Set slot time on DCU
+
+/**************************\
+* Global QCU/DCU functions *
+\**************************/
+
+/**
+ * ath5k_hw_set_ifs_intervals  - Set global inter-frame spaces on DCU
+ *
+ * @ah The &struct ath5k_hw
+ * @slot_time Slot time in us
+ *
+ * Sets the global IFS intervals on DCU (also works on AR5210) for
+ * the given slot time and the current bwmode.
  */
-int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
+int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)
 {
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        struct ath5k_softc *sc = ah->ah_sc;
+        struct ieee80211_rate *rate;
+        u32 ack_tx_time, eifs, eifs_clock, sifs, sifs_clock;
         u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);
 
         if (slot_time < 6 || slot_time_clock > AR5K_SLOT_TIME_MAX)
                 return -EINVAL;
 
-        if (ah->ah_version == AR5K_AR5210)
-                ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);
+        sifs = ath5k_hw_get_default_sifs(ah);
+        sifs_clock = ath5k_hw_htoclock(ah, sifs);
+
+        /* EIFS
+         * Txtime of ack at lowest rate + SIFS + DIFS
+         * (DIFS = SIFS + 2 * Slot time)
+         *
+         * Note: HAL has some predefined values for EIFS
+         * Turbo:   (37 + 2 * 6)
+         * Default: (74 + 2 * 9)
+         * Half:    (149 + 2 * 13)
+         * Quarter: (298 + 2 * 21)
+         *
+         * (74 + 2 * 6) for AR5210 default and turbo !
+         *
+         * According to the formula we have
+         * ack_tx_time = 25 for turbo and
+         * ack_tx_time = 42.5 * clock multiplier
+         * for default/half/quarter.
+         *
+         * This can't be right, 42 is what we would get
+         * from ath5k_hw_get_frame_dur_for_bwmode or
+         * ieee80211_generic_frame_duration for zero frame
+         * length and without SIFS !
+         *
+         * Also we have different lowest rate for 802.11a
+         */
+        if (channel->hw_value & CHANNEL_5GHZ)
+                rate = &sc->sbands[IEEE80211_BAND_5GHZ].bitrates[0];
         else
-                ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);
+                rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[0];
+
+        ack_tx_time = ath5k_hw_get_frame_duration(ah, 10, rate);
+
+        /* ack_tx_time includes an SIFS already */
+        eifs = ack_tx_time + sifs + 2 * slot_time;
+        eifs_clock = ath5k_hw_htoclock(ah, eifs);
+
+        /* Set IFS settings on AR5210 */
+        if (ah->ah_version == AR5K_AR5210) {
+                u32 pifs, pifs_clock, difs, difs_clock;
+
+                /* Set slot time */
+                ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);
+
+                /* Set EIFS */
+                eifs_clock = AR5K_REG_SM(eifs_clock, AR5K_IFS1_EIFS);
+
+                /* PIFS = Slot time + SIFS */
+                pifs = slot_time + sifs;
+                pifs_clock = ath5k_hw_htoclock(ah, pifs);
+                pifs_clock = AR5K_REG_SM(pifs_clock, AR5K_IFS1_PIFS);
+
+                /* DIFS = SIFS + 2 * Slot time */
+                difs = sifs + 2 * slot_time;
+                difs_clock = ath5k_hw_htoclock(ah, difs);
+
+                /* Set SIFS/DIFS */
+                ath5k_hw_reg_write(ah, (difs_clock <<
+                                AR5K_IFS0_DIFS_S) | sifs_clock,
+                                AR5K_IFS0);
+
+                /* Set PIFS/EIFS and preserve AR5K_INIT_CARR_SENSE_EN */
+                ath5k_hw_reg_write(ah, pifs_clock | eifs_clock |
+                                (AR5K_INIT_CARR_SENSE_EN << AR5K_IFS1_CS_EN_S),
+                                AR5K_IFS1);
+
+                return 0;
+        }
+
+        /* Set IFS slot time */
+        ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);
+
+        /* Set EIFS interval */
+        ath5k_hw_reg_write(ah, eifs_clock, AR5K_DCU_GBL_IFS_EIFS);
+
+        /* Set SIFS interval in usecs */
+        AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
+                                AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC,
+                                sifs);
+
+        /* Set SIFS interval in clock cycles */
+        ath5k_hw_reg_write(ah, sifs_clock, AR5K_DCU_GBL_IFS_SIFS);
 
         return 0;
 }
 
+
+int ath5k_hw_init_queues(struct ath5k_hw *ah)
+{
+        int i, ret;
+
+        /* TODO: HW Compression support for data queues */
+        /* TODO: Burst prefetch for data queues */
+
+        /*
+         * Reset queues and start beacon timers at the end of the reset routine
+         * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
+         * Note: If we want we can assign multiple qcus on one dcu.
+         */
+        if (ah->ah_version != AR5K_AR5210)
+                for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
+                        ret = ath5k_hw_reset_tx_queue(ah, i);
+                        if (ret) {
+                                ATH5K_ERR(ah->ah_sc,
+                                        "failed to reset TX queue #%d\n", i);
+                                return ret;
+                        }
+                }
+        else
+                /* No QCU/DCU on AR5210, just set tx
+                 * retry limits. We set IFS parameters
+                 * on ath5k_hw_set_ifs_intervals */
+                ath5k_hw_set_tx_retry_limits(ah, 0);
+
+        /* Set the turbo flag when operating on 40MHz */
+        if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
+                AR5K_REG_ENABLE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
+                                AR5K_DCU_GBL_IFS_MISC_TURBO_MODE);
+
+        /* If we didn't set IFS timings through
+         * ath5k_hw_set_coverage_class make sure
+         * we set them here */
+        if (!ah->ah_coverage_class) {
+                unsigned int slot_time = ath5k_hw_get_default_slottime(ah);
+                ath5k_hw_set_ifs_intervals(ah, slot_time);
+        }
+
+        return 0;
+}
diff --git a/drivers/net/wireless/ath/ath5k/reg.h b/drivers/net/wireless/ath/ath5k/reg.h
index 2a246d13b520..fd14b9103951 100644
--- a/drivers/net/wireless/ath/ath5k/reg.h
+++ b/drivers/net/wireless/ath/ath5k/reg.h
@@ -787,6 +787,7 @@
 #define AR5K_DCU_GBL_IFS_MISC_LFSR_SLICE        0x00000007      /* LFSR Slice Select */
 #define AR5K_DCU_GBL_IFS_MISC_TURBO_MODE        0x00000008      /* Turbo mode */
 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC     0x000003f0      /* SIFS Duration mask */
+#define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC_S   4
 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR          0x000ffc00      /* USEC Duration mask */
 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR_S        10
 #define AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DELAY     0x00300000      /* DCU Arbiter delay mask */
@@ -1311,7 +1312,7 @@
 #define AR5K_IFS1_EIFS          0x03fff000
 #define AR5K_IFS1_EIFS_S        12
 #define AR5K_IFS1_CS_EN         0x04000000
-
+#define AR5K_IFS1_CS_EN_S       26
 
 /*
  * CFP duration register
@@ -2058,6 +2059,7 @@
 
 #define AR5K_PHY_SCAL                   0x9878
 #define AR5K_PHY_SCAL_32MHZ             0x0000000e
+#define AR5K_PHY_SCAL_32MHZ_5311        0x00000008
 #define AR5K_PHY_SCAL_32MHZ_2417        0x0000000a
 #define AR5K_PHY_SCAL_32MHZ_HB63        0x00000032
 
@@ -2244,6 +2246,8 @@
 #define AR5K_PHY_FRAME_CTL              (ah->ah_version == AR5K_AR5210 ? \
                                         AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211)
 /*---[5111+]---*/
+#define AR5K_PHY_FRAME_CTL_WIN_LEN      0x00000003      /* Force window length (?) */
+#define AR5K_PHY_FRAME_CTL_WIN_LEN_S    0
 #define AR5K_PHY_FRAME_CTL_TX_CLIP      0x00000038      /* Mask for tx clip (?) */
 #define AR5K_PHY_FRAME_CTL_TX_CLIP_S    3
 #define AR5K_PHY_FRAME_CTL_PREP_CHINFO  0x00010000      /* Prepend chan info */
@@ -2558,3 +2562,28 @@
  */
 #define AR5K_PHY_PDADC_TXPOWER_BASE     0xa280
 #define AR5K_PHY_PDADC_TXPOWER(_n)      (AR5K_PHY_PDADC_TXPOWER_BASE + ((_n) << 2))
+
+/*
+ * Platform registers for WiSoC
+ */
+#define AR5K_AR5312_RESET               0xbc003020
+#define AR5K_AR5312_RESET_BB0_COLD      0x00000004
+#define AR5K_AR5312_RESET_BB1_COLD      0x00000200
+#define AR5K_AR5312_RESET_WMAC0         0x00002000
+#define AR5K_AR5312_RESET_BB0_WARM      0x00004000
+#define AR5K_AR5312_RESET_WMAC1         0x00020000
+#define AR5K_AR5312_RESET_BB1_WARM      0x00040000
+
+#define AR5K_AR5312_ENABLE              0xbc003080
+#define AR5K_AR5312_ENABLE_WLAN0    0x00000001
+#define AR5K_AR5312_ENABLE_WLAN1    0x00000008
+
+#define AR5K_AR2315_RESET               0xb1000004
+#define AR5K_AR2315_RESET_WMAC          0x00000001
+#define AR5K_AR2315_RESET_BB_WARM       0x00000002
+
+#define AR5K_AR2315_AHB_ARB_CTL         0xb1000008
+#define AR5K_AR2315_AHB_ARB_CTL_WLAN    0x00000002
+
+#define AR5K_AR2315_BYTESWAP    0xb100000c
+#define AR5K_AR2315_BYTESWAP_WMAC       0x00000002
diff --git a/drivers/net/wireless/ath/ath5k/reset.c b/drivers/net/wireless/ath/ath5k/reset.c
index 5b179d01f97d..84206898f77d 100644
--- a/drivers/net/wireless/ath/ath5k/reset.c
+++ b/drivers/net/wireless/ath/ath5k/reset.c
@@ -27,11 +27,17 @@
 
 #include <linux/pci.h>          /* To determine if a card is pci-e */
 #include <linux/log2.h>
+#include <linux/platform_device.h>
 #include "ath5k.h"
 #include "reg.h"
 #include "base.h"
 #include "debug.h"
 
+
+/******************\
+* Helper functions *
+\******************/
+
 /*
  * Check if a register write has been completed
  */
@@ -53,146 +59,267 @@ int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
         return (i <= 0) ? -EAGAIN : 0;
 }
 
+
+/*************************\
+* Clock related functions *
+\*************************/
+
 /**
- * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
+ * ath5k_hw_htoclock - Translate usec to hw clock units
  *
- * @ah: the &struct ath5k_hw
- * @channel: the currently set channel upon reset
- *
- * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
- * operation on the AR5212 upon reset. This is a helper for ath5k_hw_reset().
+ * @ah: The &struct ath5k_hw
+ * @usec: value in microseconds
+ */
+unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        return usec * common->clockrate;
+}
+
+/**
+ * ath5k_hw_clocktoh - Translate hw clock units to usec
+ * @clock: value in hw clock units
+ */
+unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
+{
+        struct ath_common *common = ath5k_hw_common(ah);
+        return clock / common->clockrate;
+}
+
+/**
+ * ath5k_hw_init_core_clock - Initialize core clock
  *
- * Since delta slope is floating point we split it on its exponent and
- * mantissa and provide these values on hw.
+ * @ah The &struct ath5k_hw
  *
- * For more infos i think this patent is related
- * http://www.freepatentsonline.com/7184495.html
+ * Initialize core clock parameters (usec, usec32, latencies etc).
  */
-static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
-        struct ieee80211_channel *channel)
+static void ath5k_hw_init_core_clock(struct ath5k_hw *ah)
 {
-        /* Get exponent and mantissa and set it */
-        u32 coef_scaled, coef_exp, coef_man,
-                ds_coef_exp, ds_coef_man, clock;
-
-        BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
-                !(channel->hw_value & CHANNEL_OFDM));
-
-        /* Get coefficient
-         * ALGO: coef = (5 * clock / carrier_freq) / 2
-         * we scale coef by shifting clock value by 24 for
-         * better precision since we use integers */
-        /* TODO: Half/quarter rate */
-        clock =  (channel->hw_value & CHANNEL_TURBO) ? 80 : 40;
-        coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
-
-        /* Get exponent
-         * ALGO: coef_exp = 14 - highest set bit position */
-        coef_exp = ilog2(coef_scaled);
-
-        /* Doesn't make sense if it's zero*/
-        if (!coef_scaled || !coef_exp)
-                return -EINVAL;
+        struct ieee80211_channel *channel = ah->ah_current_channel;
+        struct ath_common *common = ath5k_hw_common(ah);
+        u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs;
+
+        /*
+         * Set core clock frequency
+         */
+        if (channel->hw_value & CHANNEL_5GHZ)
+                clock = 40; /* 802.11a */
+        else if (channel->hw_value & CHANNEL_CCK)
+                clock = 22; /* 802.11b */
+        else
+                clock = 44; /* 802.11g */
+
+        /* Use clock multiplier for non-default
+         * bwmode */
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_40MHZ:
+                clock *= 2;
+                break;
+        case AR5K_BWMODE_10MHZ:
+                clock /= 2;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                clock /= 4;
+                break;
+        default:
+                break;
+        }
 
-        /* Note: we've shifted coef_scaled by 24 */
-        coef_exp = 14 - (coef_exp - 24);
+        common->clockrate = clock;
 
+        /*
+         * Set USEC parameters
+         */
+        /* Set USEC counter on PCU*/
+        usec = clock - 1;
+        usec = AR5K_REG_SM(usec, AR5K_USEC_1);
 
-        /* Get mantissa (significant digits)
-         * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
-        coef_man = coef_scaled +
-                (1 << (24 - coef_exp - 1));
+        /* Set usec duration on DCU */
+        if (ah->ah_version != AR5K_AR5210)
+                AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,
+                                        AR5K_DCU_GBL_IFS_MISC_USEC_DUR,
+                                        clock);
 
-        /* Calculate delta slope coefficient exponent
-         * and mantissa (remove scaling) and set them on hw */
-        ds_coef_man = coef_man >> (24 - coef_exp);
-        ds_coef_exp = coef_exp - 16;
+        /* Set 32MHz USEC counter */
+        if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_radio == AR5K_RF2316) ||
+                (ah->ah_radio == AR5K_RF2317))
+        /* Remain on 40MHz clock ? */
+                sclock = 40 - 1;
+        else
+                sclock = 32 - 1;
+        sclock = AR5K_REG_SM(sclock, AR5K_USEC_32);
 
-        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
-                AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
-        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
-                AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
+        /*
+         * Set tx/rx latencies
+         */
+        usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
+        txlat = AR5K_REG_MS(usec_reg, AR5K_USEC_TX_LATENCY_5211);
+        rxlat = AR5K_REG_MS(usec_reg, AR5K_USEC_RX_LATENCY_5211);
 
-        return 0;
-}
+        /*
+         * 5210 initvals don't include usec settings
+         * so we need to use magic values here for
+         * tx/rx latencies
+         */
+        if (ah->ah_version == AR5K_AR5210) {
+                /* same for turbo */
+                txlat = AR5K_INIT_TX_LATENCY_5210;
+                rxlat = AR5K_INIT_RX_LATENCY_5210;
+        }
 
+        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
+                /* 5311 has different tx/rx latency masks
+                 * from 5211, since we deal 5311 the same
+                 * as 5211 when setting initvals, shift
+                 * values here to their proper locations
+                 *
+                 * Note: Initvals indicate tx/rx/ latencies
+                 * are the same for turbo mode */
+                txlat = AR5K_REG_SM(txlat, AR5K_USEC_TX_LATENCY_5210);
+                rxlat = AR5K_REG_SM(rxlat, AR5K_USEC_RX_LATENCY_5210);
+        } else
+        switch (ah->ah_bwmode) {
+        case AR5K_BWMODE_10MHZ:
+                txlat = AR5K_REG_SM(txlat * 2,
+                                AR5K_USEC_TX_LATENCY_5211);
+                rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
+                                AR5K_USEC_RX_LATENCY_5211);
+                txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_10MHZ;
+                break;
+        case AR5K_BWMODE_5MHZ:
+                txlat = AR5K_REG_SM(txlat * 4,
+                                AR5K_USEC_TX_LATENCY_5211);
+                rxlat = AR5K_REG_SM(AR5K_INIT_RX_LAT_MAX,
+                                AR5K_USEC_RX_LATENCY_5211);
+                txf2txs = AR5K_INIT_TXF2TXD_START_DELAY_5MHZ;
+                break;
+        case AR5K_BWMODE_40MHZ:
+                txlat = AR5K_INIT_TX_LAT_MIN;
+                rxlat = AR5K_REG_SM(rxlat / 2,
+                                AR5K_USEC_RX_LATENCY_5211);
+                txf2txs = AR5K_INIT_TXF2TXD_START_DEFAULT;
+                break;
+        default:
+                break;
+        }
 
-/*
- * index into rates for control rates, we can set it up like this because
- * this is only used for AR5212 and we know it supports G mode
- */
-static const unsigned int control_rates[] =
-        { 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
+        usec_reg = (usec | sclock | txlat | rxlat);
+        ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);
 
-/**
- * ath5k_hw_write_rate_duration - fill rate code to duration table
- *
- * @ah: the &struct ath5k_hw
- * @mode: one of enum ath5k_driver_mode
- *
- * Write the rate code to duration table upon hw reset. This is a helper for
- * ath5k_hw_reset(). It seems all this is doing is setting an ACK timeout on
- * the hardware, based on current mode, for each rate. The rates which are
- * capable of short preamble (802.11b rates 2Mbps, 5.5Mbps, and 11Mbps) have
- * different rate code so we write their value twice (one for long preample
- * and one for short).
+        /* On 5112 set tx frane to tx data start delay */
+        if (ah->ah_radio == AR5K_RF5112) {
+                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,
+                                        AR5K_PHY_RF_CTL2_TXF2TXD_START,
+                                        txf2txs);
+        }
+}
+
+/*
+ * If there is an external 32KHz crystal available, use it
+ * as ref. clock instead of 32/40MHz clock and baseband clocks
+ * to save power during sleep or restore normal 32/40MHz
+ * operation.
  *
- * Note: Band doesn't matter here, if we set the values for OFDM it works
- * on both a and g modes. So all we have to do is set values for all g rates
- * that include all OFDM and CCK rates. If we operate in turbo or xr/half/
- * quarter rate mode, we need to use another set of bitrates (that's why we
- * need the mode parameter) but we don't handle these proprietary modes yet.
+ * XXX: When operating on 32KHz certain PHY registers (27 - 31,
+ *      123 - 127) require delay on access.
  */
-static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
-       unsigned int mode)
+static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
 {
-        struct ath5k_softc *sc = ah->ah_sc;
-        struct ieee80211_rate *rate;
-        unsigned int i;
+        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+        u32 scal, spending;
+
+        /* Only set 32KHz settings if we have an external
+         * 32KHz crystal present */
+        if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
+        AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
+        enable) {
 
-        /* Write rate duration table */
-        for (i = 0; i < sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates; i++) {
-                u32 reg;
-                u16 tx_time;
+                /* 1 usec/cycle */
+                AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
+                /* Set up tsf increment on each cycle */
+                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
 
-                rate = &sc->sbands[IEEE80211_BAND_2GHZ].bitrates[control_rates[i]];
+                /* Set baseband sleep control registers
+                 * and sleep control rate */
+                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
+
+                if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_radio == AR5K_RF2316) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                        spending = 0x14;
+                else
+                        spending = 0x18;
+                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
 
-                /* Set ACK timeout */
-                reg = AR5K_RATE_DUR(rate->hw_value);
+                if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
+                        ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
+                        ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
+                        ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
+                        ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
+                } else {
+                        ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
+                        ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
+                        ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
+                        ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
+                }
 
-                /* An ACK frame consists of 10 bytes. If you add the FCS,
-                 * which ieee80211_generic_frame_duration() adds,
-                 * its 14 bytes. Note we use the control rate and not the
-                 * actual rate for this rate. See mac80211 tx.c
-                 * ieee80211_duration() for a brief description of
-                 * what rate we should choose to TX ACKs. */
-                tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
-                                                        NULL, 10, rate));
+                /* Enable sleep clock operation */
+                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_EN);
 
-                ath5k_hw_reg_write(ah, tx_time, reg);
+        } else {
 
-                if (!(rate->flags & IEEE80211_RATE_SHORT_PREAMBLE))
-                        continue;
+                /* Disable sleep clock operation and
+                 * restore default parameters */
+                AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_EN);
 
-                /*
-                 * We're not distinguishing short preamble here,
-                 * This is true, all we'll get is a longer value here
-                 * which is not necessarilly bad. We could use
-                 * export ieee80211_frame_duration() but that needs to be
-                 * fixed first to be properly used by mac802111 drivers:
-                 *
-                 *  - remove erp stuff and let the routine figure ofdm
-                 *    erp rates
-                 *  - remove passing argument ieee80211_local as
-                 *    drivers don't have access to it
-                 *  - move drivers using ieee80211_generic_frame_duration()
-                 *    to this
-                 */
-                ath5k_hw_reg_write(ah, tx_time,
-                        reg + (AR5K_SET_SHORT_PREAMBLE << 2));
+                AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
+                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
+
+                /* Set DAC/ADC delays */
+                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
+                ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
+
+                if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
+                        scal = AR5K_PHY_SCAL_32MHZ_2417;
+                else if (ee->ee_is_hb63)
+                        scal = AR5K_PHY_SCAL_32MHZ_HB63;
+                else
+                        scal = AR5K_PHY_SCAL_32MHZ;
+                ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
+
+                ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
+                ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
+
+                if ((ah->ah_radio == AR5K_RF5112) ||
+                (ah->ah_radio == AR5K_RF5413) ||
+                (ah->ah_radio == AR5K_RF2316) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
+                        spending = 0x14;
+                else
+                        spending = 0x18;
+                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
+
+                /* Set up tsf increment on each cycle */
+                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
         }
 }
 
+
+/*********************\
+* Reset/Sleep control *
+\*********************/
+
 /*
  * Reset chipset
  */
@@ -236,6 +363,64 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
 }
 
 /*
+ * Reset AHB chipset
+ * AR5K_RESET_CTL_PCU flag resets WMAC
+ * AR5K_RESET_CTL_BASEBAND flag resets WBB
+ */
+static int ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)
+{
+        u32 mask = flags ? flags : ~0U;
+        volatile u32 *reg;
+        u32 regval;
+        u32 val = 0;
+
+        /* ah->ah_mac_srev is not available at this point yet */
+        if (ah->ah_sc->devid >= AR5K_SREV_AR2315_R6) {
+                reg = (u32 *) AR5K_AR2315_RESET;
+                if (mask & AR5K_RESET_CTL_PCU)
+                        val |= AR5K_AR2315_RESET_WMAC;
+                if (mask & AR5K_RESET_CTL_BASEBAND)
+                        val |= AR5K_AR2315_RESET_BB_WARM;
+        } else {
+                reg = (u32 *) AR5K_AR5312_RESET;
+                if (to_platform_device(ah->ah_sc->dev)->id == 0) {
+                        if (mask & AR5K_RESET_CTL_PCU)
+                                val |= AR5K_AR5312_RESET_WMAC0;
+                        if (mask & AR5K_RESET_CTL_BASEBAND)
+                                val |= AR5K_AR5312_RESET_BB0_COLD |
+                                       AR5K_AR5312_RESET_BB0_WARM;
+                } else {
+                        if (mask & AR5K_RESET_CTL_PCU)
+                                val |= AR5K_AR5312_RESET_WMAC1;
+                        if (mask & AR5K_RESET_CTL_BASEBAND)
+                                val |= AR5K_AR5312_RESET_BB1_COLD |
+                                       AR5K_AR5312_RESET_BB1_WARM;
+                }
+        }
+
+        /* Put BB/MAC into reset */
+        regval = __raw_readl(reg);
+        __raw_writel(regval | val, reg);
+        regval = __raw_readl(reg);
+        udelay(100);
+
+        /* Bring BB/MAC out of reset */
+        __raw_writel(regval & ~val, reg);
+        regval = __raw_readl(reg);
+
+        /*
+         * Reset configuration register (for hw byte-swap). Note that this
+         * is only set for big endian. We do the necessary magic in
+         * AR5K_INIT_CFG.
+         */
+        if ((flags & AR5K_RESET_CTL_PCU) == 0)
+                ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
+
+        return 0;
+}
+
+
+/*
  * Sleep control
  */
 static int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
@@ -334,6 +519,9 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
         u32 bus_flags;
         int ret;
 
+        if (ath5k_get_bus_type(ah) == ATH_AHB)
+                return 0;
+
         /* Make sure device is awake */
         ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
         if (ret) {
@@ -349,7 +537,7 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
          * we ingore that flag for PCI-E cards. On PCI cards
          * this flag gets cleared after 64 PCI clocks.
          */
-        bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
+        bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 
         if (ah->ah_version == AR5K_AR5210) {
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
@@ -378,7 +566,6 @@ int ath5k_hw_on_hold(struct ath5k_hw *ah)
 
 /*
  * Bring up MAC + PHY Chips and program PLL
- * TODO: Half/Quarter rate support
  */
 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
 {
@@ -390,11 +577,13 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
         mode = 0;
         clock = 0;
 
-        /* Wakeup the device */
-        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
-        if (ret) {
-                ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
-                return ret;
+        if ((ath5k_get_bus_type(ah) != ATH_AHB) || !initial) {
+                /* Wakeup the device */
+                ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
+                if (ret) {
+                        ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
+                        return ret;
+                }
         }
 
         /*
@@ -405,7 +594,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
          * we ingore that flag for PCI-E cards. On PCI cards
          * this flag gets cleared after 64 PCI clocks.
          */
-        bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
+        bus_flags = (pdev && pci_is_pcie(pdev)) ? 0 : AR5K_RESET_CTL_PCI;
 
         if (ah->ah_version == AR5K_AR5210) {
                 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
@@ -413,8 +602,12 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                         AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
                         mdelay(2);
         } else {
-                ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
-                        AR5K_RESET_CTL_BASEBAND | bus_flags);
+                if (ath5k_get_bus_type(ah) == ATH_AHB)
+                        ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |
+                                AR5K_RESET_CTL_BASEBAND);
+                else
+                        ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+                                AR5K_RESET_CTL_BASEBAND | bus_flags);
         }
 
         if (ret) {
@@ -429,9 +622,15 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                 return ret;
         }
 
-        /* ...clear reset control register and pull device out of
-         * warm reset */
-        if (ath5k_hw_nic_reset(ah, 0)) {
+        /* ...reset configuration regiter on Wisoc ...
+         * ...clear reset control register and pull device out of
+         * warm reset on others */
+        if (ath5k_get_bus_type(ah) == ATH_AHB)
+                ret = ath5k_hw_wisoc_reset(ah, 0);
+        else
+                ret = ath5k_hw_nic_reset(ah, 0);
+
+        if (ret) {
                 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
                 return -EIO;
         }
@@ -466,7 +665,8 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                                  * CCK headers) operation. We need to test
                                  * this, 5211 might support ofdm-only g after
                                  * all, there are also initial register values
-                                 * in the code for g mode (see initvals.c). */
+                                 * in the code for g mode (see initvals.c).
+                                 */
                                 if (ah->ah_version == AR5K_AR5211)
                                         mode |= AR5K_PHY_MODE_MOD_OFDM;
                                 else
@@ -479,6 +679,7 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                 } else if (flags & CHANNEL_5GHZ) {
                         mode |= AR5K_PHY_MODE_FREQ_5GHZ;
 
+                        /* Different PLL setting for 5413 */
                         if (ah->ah_radio == AR5K_RF5413)
                                 clock = AR5K_PHY_PLL_40MHZ_5413;
                         else
@@ -496,12 +697,29 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
                         return -EINVAL;
                 }
 
-                if (flags & CHANNEL_TURBO)
-                        turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
+                /*XXX: Can bwmode be used with dynamic mode ?
+                 * (I don't think it supports 44MHz) */
+                /* On 2425 initvals TURBO_SHORT is not pressent */
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
+                        turbo = AR5K_PHY_TURBO_MODE |
+                                (ah->ah_radio == AR5K_RF2425) ? 0 :
+                                AR5K_PHY_TURBO_SHORT;
+                } else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {
+                        if (ah->ah_radio == AR5K_RF5413) {
+                                mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
+                                        AR5K_PHY_MODE_HALF_RATE :
+                                        AR5K_PHY_MODE_QUARTER_RATE;
+                        } else if (ah->ah_version == AR5K_AR5212) {
+                                clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?
+                                        AR5K_PHY_PLL_HALF_RATE :
+                                        AR5K_PHY_PLL_QUARTER_RATE;
+                        }
+                }
+
         } else { /* Reset the device */
 
                 /* ...enable Atheros turbo mode if requested */
-                if (flags & CHANNEL_TURBO)
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
                         ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
                                         AR5K_PHY_TURBO);
         }
@@ -522,107 +740,10 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
         return 0;
 }
 
-/*
- * If there is an external 32KHz crystal available, use it
- * as ref. clock instead of 32/40MHz clock and baseband clocks
- * to save power during sleep or restore normal 32/40MHz
- * operation.
- *
- * XXX: When operating on 32KHz certain PHY registers (27 - 31,
- *      123 - 127) require delay on access.
- */
-static void ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)
-{
-        struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-        u32 scal, spending, usec32;
 
-        /* Only set 32KHz settings if we have an external
-         * 32KHz crystal present */
-        if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||
-        AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&
-        enable) {
-
-                /* 1 usec/cycle */
-                AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);
-                /* Set up tsf increment on each cycle */
-                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);
-
-                /* Set baseband sleep control registers
-                 * and sleep control rate */
-                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413) ||
-                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                        spending = 0x14;
-                else
-                        spending = 0x18;
-                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413) ||
-                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
-                        ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);
-                        ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);
-                        ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);
-                        ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);
-                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x02);
-                } else {
-                        ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);
-                        ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);
-                        ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);
-                        ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);
-                        AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0x03);
-                }
-
-                /* Enable sleep clock operation */
-                AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_EN);
-
-        } else {
-
-                /* Disable sleep clock operation and
-                 * restore default parameters */
-                AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_EN);
-
-                AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,
-                                AR5K_PCICFG_SLEEP_CLOCK_RATE, 0);
-
-                ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);
-                ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
-
-                if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
-                        scal = AR5K_PHY_SCAL_32MHZ_2417;
-                else if (ee->ee_is_hb63)
-                        scal = AR5K_PHY_SCAL_32MHZ_HB63;
-                else
-                        scal = AR5K_PHY_SCAL_32MHZ;
-                ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
-
-                ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
-                ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413) ||
-                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
-                        spending = 0x14;
-                else
-                        spending = 0x18;
-                ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);
-
-                if ((ah->ah_radio == AR5K_RF5112) ||
-                (ah->ah_radio == AR5K_RF5413))
-                        usec32 = 39;
-                else
-                        usec32 = 31;
-                AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, usec32);
-
-                AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);
-        }
-}
+/**************************************\
+* Post-initvals register modifications *
+\**************************************/
 
 /* TODO: Half/Quarter rate */
 static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
@@ -663,22 +784,10 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
                 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
                                 AR5K_TXCFG_DCU_DBL_BUF_DIS);
 
-        /* Set DAC/ADC delays */
-        if (ah->ah_version == AR5K_AR5212) {
-                u32 scal;
-                struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
-                if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))
-                        scal = AR5K_PHY_SCAL_32MHZ_2417;
-                else if (ee->ee_is_hb63)
-                        scal = AR5K_PHY_SCAL_32MHZ_HB63;
-                else
-                        scal = AR5K_PHY_SCAL_32MHZ;
-                ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);
-        }
-
         /* Set fast ADC */
         if ((ah->ah_radio == AR5K_RF5413) ||
-        (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
+                (ah->ah_radio == AR5K_RF2317) ||
+                (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {
                 u32 fast_adc = true;
 
                 if (channel->center_freq == 2462 ||
@@ -706,33 +815,68 @@ static void ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,
         }
 
         if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
-                u32 usec_reg;
-                /* 5311 has different tx/rx latency masks
-                 * from 5211, since we deal 5311 the same
-                 * as 5211 when setting initvals, shift
-                 * values here to their proper locations */
-                usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);
-                ath5k_hw_reg_write(ah, usec_reg & (AR5K_USEC_1 |
-                                AR5K_USEC_32 |
-                                AR5K_USEC_TX_LATENCY_5211 |
-                                AR5K_REG_SM(29,
-                                AR5K_USEC_RX_LATENCY_5210)),
-                                AR5K_USEC_5211);
                 /* Clear QCU/DCU clock gating register */
                 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);
                 /* Set DAC/ADC delays */
-                ath5k_hw_reg_write(ah, 0x08, AR5K_PHY_SCAL);
+                ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,
+                                                AR5K_PHY_SCAL);
                 /* Enable PCU FIFO corruption ECO */
                 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,
                                         AR5K_DIAG_SW_ECO_ENABLE);
         }
+
+        if (ah->ah_bwmode) {
+                /* Increase PHY switch and AGC settling time
+                 * on turbo mode (ath5k_hw_commit_eeprom_settings
+                 * will override settling time if available) */
+                if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {
+
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
+                                                AR5K_PHY_SETTLING_AGC,
+                                                AR5K_AGC_SETTLING_TURBO);
+
+                        /* XXX: Initvals indicate we only increase
+                         * switch time on AR5212, 5211 and 5210
+                         * only change agc time (bug?) */
+                        if (ah->ah_version == AR5K_AR5212)
+                                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
+                                                AR5K_PHY_SETTLING_SWITCH,
+                                                AR5K_SWITCH_SETTLING_TURBO);
+
+                        if (ah->ah_version == AR5K_AR5210) {
+                                /* Set Frame Control Register */
+                                ath5k_hw_reg_write(ah,
+                                        (AR5K_PHY_FRAME_CTL_INI |
+                                        AR5K_PHY_TURBO_MODE |
+                                        AR5K_PHY_TURBO_SHORT | 0x2020),
+                                        AR5K_PHY_FRAME_CTL_5210);
+                        }
+                /* On 5413 PHY force window length for half/quarter rate*/
+                } else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&
+                (ah->ah_mac_srev <= AR5K_SREV_AR5414)) {
+                        AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,
+                                                AR5K_PHY_FRAME_CTL_WIN_LEN,
+                                                3);
+                }
+        } else if (ah->ah_version == AR5K_AR5210) {
+                /* Set Frame Control Register for normal operation */
+                ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),
+                                                AR5K_PHY_FRAME_CTL_5210);
+        }
 }
 
 static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
-                struct ieee80211_channel *channel, u8 ee_mode)
+                struct ieee80211_channel *channel)
 {
         struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
         s16 cck_ofdm_pwr_delta;
+        u8 ee_mode;
+
+        /* TODO: Add support for AR5210 EEPROM */
+        if (ah->ah_version == AR5K_AR5210)
+                return;
+
+        ee_mode = ath5k_eeprom_mode_from_channel(channel);
 
         /* Adjust power delta for channel 14 */
         if (channel->center_freq == 2484)
@@ -772,7 +916,7 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
                 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
                 AR5K_PHY_NFTHRES);
 
-        if ((channel->hw_value & CHANNEL_TURBO) &&
+        if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
         (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {
                 /* Switch settling time (Turbo) */
                 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,
@@ -870,143 +1014,172 @@ static void ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,
                 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);
 }
 
-/*
- * Main reset function
- */
+
+/*********************\
+* Main reset function *
+\*********************/
+
 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
-        struct ieee80211_channel *channel, bool change_channel)
+                struct ieee80211_channel *channel, bool fast, bool skip_pcu)
 {
-        struct ath_common *common = ath5k_hw_common(ah);
-        u32 s_seq[10], s_led[3], staid1_flags, tsf_up, tsf_lo;
-        u32 phy_tst1;
-        u8 mode, freq, ee_mode;
+        u32 s_seq[10], s_led[3], tsf_up, tsf_lo;
+        u8 mode;
         int i, ret;
 
-        ee_mode = 0;
-        staid1_flags = 0;
         tsf_up = 0;
         tsf_lo = 0;
-        freq = 0;
         mode = 0;
 
         /*
-         * Save some registers before a reset
+         * Sanity check for fast flag
+         * Fast channel change only available
+         * on AR2413/AR5413.
          */
-        /*DCU/Antenna selection not available on 5210*/
-        if (ah->ah_version != AR5K_AR5210) {
+        if (fast && (ah->ah_radio != AR5K_RF2413) &&
+        (ah->ah_radio != AR5K_RF5413))
+                fast = 0;
 
-                switch (channel->hw_value & CHANNEL_MODES) {
-                case CHANNEL_A:
-                        mode = AR5K_MODE_11A;
-                        freq = AR5K_INI_RFGAIN_5GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11A;
-                        break;
-                case CHANNEL_G:
-                        mode = AR5K_MODE_11G;
-                        freq = AR5K_INI_RFGAIN_2GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11G;
-                        break;
-                case CHANNEL_B:
-                        mode = AR5K_MODE_11B;
-                        freq = AR5K_INI_RFGAIN_2GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11B;
-                        break;
-                case CHANNEL_T:
-                        mode = AR5K_MODE_11A_TURBO;
-                        freq = AR5K_INI_RFGAIN_5GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11A;
-                        break;
-                case CHANNEL_TG:
-                        if (ah->ah_version == AR5K_AR5211) {
-                                ATH5K_ERR(ah->ah_sc,
-                                        "TurboG mode not available on 5211");
-                                return -EINVAL;
-                        }
-                        mode = AR5K_MODE_11G_TURBO;
-                        freq = AR5K_INI_RFGAIN_2GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11G;
-                        break;
-                case CHANNEL_XR:
-                        if (ah->ah_version == AR5K_AR5211) {
-                                ATH5K_ERR(ah->ah_sc,
-                                        "XR mode not available on 5211");
-                                return -EINVAL;
-                        }
-                        mode = AR5K_MODE_XR;
-                        freq = AR5K_INI_RFGAIN_5GHZ;
-                        ee_mode = AR5K_EEPROM_MODE_11A;
-                        break;
-                default:
+        /* Disable sleep clock operation
+         * to avoid register access delay on certain
+         * PHY registers */
+        if (ah->ah_version == AR5K_AR5212)
+                ath5k_hw_set_sleep_clock(ah, false);
+
+        /*
+         * Stop PCU
+         */
+        ath5k_hw_stop_rx_pcu(ah);
+
+        /*
+         * Stop DMA
+         *
+         * Note: If DMA didn't stop continue
+         * since only a reset will fix it.
+         */
+        ret = ath5k_hw_dma_stop(ah);
+
+        /* RF Bus grant won't work if we have pending
+         * frames */
+        if (ret && fast) {
+                ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
+                        "DMA didn't stop, falling back to normal reset\n");
+                fast = 0;
+                /* Non fatal, just continue with
+                 * normal reset */
+                ret = 0;
+        }
+
+        switch (channel->hw_value & CHANNEL_MODES) {
+        case CHANNEL_A:
+                mode = AR5K_MODE_11A;
+                break;
+        case CHANNEL_G:
+
+                if (ah->ah_version <= AR5K_AR5211) {
                         ATH5K_ERR(ah->ah_sc,
-                                "invalid channel: %d\n", channel->center_freq);
+                                "G mode not available on 5210/5211");
                         return -EINVAL;
                 }
 
-                if (change_channel) {
-                        /*
-                         * Save frame sequence count
-                         * For revs. after Oahu, only save
-                         * seq num for DCU 0 (Global seq num)
-                         */
-                        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
-
-                                for (i = 0; i < 10; i++)
-                                        s_seq[i] = ath5k_hw_reg_read(ah,
-                                                AR5K_QUEUE_DCU_SEQNUM(i));
+                mode = AR5K_MODE_11G;
+                break;
+        case CHANNEL_B:
 
-                        } else {
-                                s_seq[0] = ath5k_hw_reg_read(ah,
-                                                AR5K_QUEUE_DCU_SEQNUM(0));
-                        }
+                if (ah->ah_version < AR5K_AR5211) {
+                        ATH5K_ERR(ah->ah_sc,
+                                "B mode not available on 5210");
+                        return -EINVAL;
+                }
 
-                        /* TSF accelerates on AR5211 during reset
-                         * As a workaround save it here and restore
-                         * it later so that it's back in time after
-                         * reset. This way it'll get re-synced on the
-                         * next beacon without breaking ad-hoc.
-                         *
-                         * On AR5212 TSF is almost preserved across a
-                         * reset so it stays back in time anyway and
-                         * we don't have to save/restore it.
-                         *
-                         * XXX: Since this breaks power saving we have
-                         * to disable power saving until we receive the
-                         * next beacon, so we can resync beacon timers */
-                        if (ah->ah_version == AR5K_AR5211) {
-                                tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
-                                tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
-                        }
+                mode = AR5K_MODE_11B;
+                break;
+        case CHANNEL_XR:
+                if (ah->ah_version == AR5K_AR5211) {
+                        ATH5K_ERR(ah->ah_sc,
+                                "XR mode not available on 5211");
+                        return -EINVAL;
                 }
+                mode = AR5K_MODE_XR;
+                break;
+        default:
+                ATH5K_ERR(ah->ah_sc,
+                        "invalid channel: %d\n", channel->center_freq);
+                return -EINVAL;
+        }
 
-                if (ah->ah_version == AR5K_AR5212) {
-                        /* Restore normal 32/40MHz clock operation
-                         * to avoid register access delay on certain
-                         * PHY registers */
-                        ath5k_hw_set_sleep_clock(ah, false);
+        /*
+         * If driver requested fast channel change and DMA has stopped
+         * go on. If it fails continue with a normal reset.
+         */
+        if (fast) {
+                ret = ath5k_hw_phy_init(ah, channel, mode, true);
+                if (ret) {
+                        ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_RESET,
+                                "fast chan change failed, falling back to normal reset\n");
+                        /* Non fatal, can happen eg.
+                         * on mode change */
+                        ret = 0;
+                } else
+                        return 0;
+        }
 
-                        /* Since we are going to write rf buffer
-                         * check if we have any pending gain_F
-                         * optimization settings */
-                        if (change_channel && ah->ah_rf_banks != NULL)
-                                ath5k_hw_gainf_calibrate(ah);
+        /*
+         * Save some registers before a reset
+         */
+        if (ah->ah_version != AR5K_AR5210) {
+                /*
+                 * Save frame sequence count
+                 * For revs. after Oahu, only save
+                 * seq num for DCU 0 (Global seq num)
+                 */
+                if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
+
+                        for (i = 0; i < 10; i++)
+                                s_seq[i] = ath5k_hw_reg_read(ah,
+                                        AR5K_QUEUE_DCU_SEQNUM(i));
+
+                } else {
+                        s_seq[0] = ath5k_hw_reg_read(ah,
+                                        AR5K_QUEUE_DCU_SEQNUM(0));
+                }
+
+                /* TSF accelerates on AR5211 during reset
+                 * As a workaround save it here and restore
+                 * it later so that it's back in time after
+                 * reset. This way it'll get re-synced on the
+                 * next beacon without breaking ad-hoc.
+                 *
+                 * On AR5212 TSF is almost preserved across a
+                 * reset so it stays back in time anyway and
+                 * we don't have to save/restore it.
+                 *
+                 * XXX: Since this breaks power saving we have
+                 * to disable power saving until we receive the
+                 * next beacon, so we can resync beacon timers */
+                if (ah->ah_version == AR5K_AR5211) {
+                        tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
+                        tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
                 }
         }
 
+
         /*GPIOs*/
         s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &
                                         AR5K_PCICFG_LEDSTATE;
         s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
         s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
 
-        /* AR5K_STA_ID1 flags, only preserve antenna
-         * settings and ack/cts rate mode */
-        staid1_flags = ath5k_hw_reg_read(ah, AR5K_STA_ID1) &
-                        (AR5K_STA_ID1_DEFAULT_ANTENNA |
-                        AR5K_STA_ID1_DESC_ANTENNA |
-                        AR5K_STA_ID1_RTS_DEF_ANTENNA |
-                        AR5K_STA_ID1_ACKCTS_6MB |
-                        AR5K_STA_ID1_BASE_RATE_11B |
-                        AR5K_STA_ID1_SELFGEN_DEF_ANT);
+
+        /*
+         * Since we are going to write rf buffer
+         * check if we have any pending gain_F
+         * optimization settings
+         */
+        if (ah->ah_version == AR5K_AR5212 &&
+        (ah->ah_radio <= AR5K_RF5112)) {
+                if (!fast && ah->ah_rf_banks != NULL)
+                                ath5k_hw_gainf_calibrate(ah);
+        }
 
         /* Wakeup the device */
         ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
@@ -1021,121 +1194,42 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                                                         AR5K_PHY(0));
 
         /* Write initial settings */
-        ret = ath5k_hw_write_initvals(ah, mode, change_channel);
+        ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);
         if (ret)
                 return ret;
 
+        /* Initialize core clock settings */
+        ath5k_hw_init_core_clock(ah);
+
         /*
-         * 5211/5212 Specific
+         * Tweak initval settings for revised
+         * chipsets and add some more config
+         * bits
          */
-        if (ah->ah_version != AR5K_AR5210) {
-
-                /*
-                 * Write initial RF gain settings
-                 * This should work for both 5111/5112
-                 */
-                ret = ath5k_hw_rfgain_init(ah, freq);
-                if (ret)
-                        return ret;
-
-                mdelay(1);
-
-                /*
-                 * Tweak initval settings for revised
-                 * chipsets and add some more config
-                 * bits
-                 */
-                ath5k_hw_tweak_initval_settings(ah, channel);
-
-                /*
-                 * Set TX power
-                 */
-                ret = ath5k_hw_txpower(ah, channel, ee_mode,
-                                        ah->ah_txpower.txp_max_pwr / 2);
-                if (ret)
-                        return ret;
+        ath5k_hw_tweak_initval_settings(ah, channel);
 
-                /* Write rate duration table only on AR5212 and if
-                 * virtual interface has already been brought up
-                 * XXX: rethink this after new mode changes to
-                 * mac80211 are integrated */
-                if (ah->ah_version == AR5K_AR5212 &&
-                        ah->ah_sc->nvifs)
-                        ath5k_hw_write_rate_duration(ah, mode);
+        /* Commit values from EEPROM */
+        ath5k_hw_commit_eeprom_settings(ah, channel);
 
-                /*
-                 * Write RF buffer
-                 */
-                ret = ath5k_hw_rfregs_init(ah, channel, mode);
-                if (ret)
-                        return ret;
-
-
-                /* Write OFDM timings on 5212*/
-                if (ah->ah_version == AR5K_AR5212 &&
-                        channel->hw_value & CHANNEL_OFDM) {
-
-                        ret = ath5k_hw_write_ofdm_timings(ah, channel);
-                        if (ret)
-                                return ret;
-
-                        /* Spur info is available only from EEPROM versions
-                         * greater than 5.3, but the EEPROM routines will use
-                         * static values for older versions */
-                        if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
-                                ath5k_hw_set_spur_mitigation_filter(ah,
-                                                                    channel);
-                }
-
-                /*Enable/disable 802.11b mode on 5111
-                (enable 2111 frequency converter + CCK)*/
-                if (ah->ah_radio == AR5K_RF5111) {
-                        if (mode == AR5K_MODE_11B)
-                                AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
-                                    AR5K_TXCFG_B_MODE);
-                        else
-                                AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
-                                    AR5K_TXCFG_B_MODE);
-                }
-
-                /* Commit values from EEPROM */
-                ath5k_hw_commit_eeprom_settings(ah, channel, ee_mode);
-
-        } else {
-                /*
-                 * For 5210 we do all initialization using
-                 * initvals, so we don't have to modify
-                 * any settings (5210 also only supports
-                 * a/aturbo modes)
-                 */
-                mdelay(1);
-                /* Disable phy and wait */
-                ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
-                mdelay(1);
-        }
 
         /*
          * Restore saved values
          */
 
-        /*DCU/Antenna selection not available on 5210*/
+        /* Seqnum, TSF */
         if (ah->ah_version != AR5K_AR5210) {
+                if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
+                        for (i = 0; i < 10; i++)
+                                ath5k_hw_reg_write(ah, s_seq[i],
+                                        AR5K_QUEUE_DCU_SEQNUM(i));
+                } else {
+                        ath5k_hw_reg_write(ah, s_seq[0],
+                                AR5K_QUEUE_DCU_SEQNUM(0));
+                }
 
-                if (change_channel) {
-                        if (ah->ah_mac_srev < AR5K_SREV_AR5211) {
-                                for (i = 0; i < 10; i++)
-                                        ath5k_hw_reg_write(ah, s_seq[i],
-                                                AR5K_QUEUE_DCU_SEQNUM(i));
-                        } else {
-                                ath5k_hw_reg_write(ah, s_seq[0],
-                                        AR5K_QUEUE_DCU_SEQNUM(0));
-                        }
-
-
-                        if (ah->ah_version == AR5K_AR5211) {
-                                ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
-                                ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
-                        }
+                if (ah->ah_version == AR5K_AR5211) {
+                        ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);
+                        ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);
                 }
         }
 
@@ -1146,203 +1240,34 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
         ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
         ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
 
-        /* Restore sta_id flags and preserve our mac address*/
-        ath5k_hw_reg_write(ah,
-                           get_unaligned_le32(common->macaddr),
-                           AR5K_STA_ID0);
-        ath5k_hw_reg_write(ah,
-                           staid1_flags | get_unaligned_le16(common->macaddr + 4),
-                           AR5K_STA_ID1);
-
-
         /*
-         * Configure PCU
+         * Initialize PCU
          */
-
-        /* Restore bssid and bssid mask */
-        ath5k_hw_set_bssid(ah);
-
-        /* Set PCU config */
-        ath5k_hw_set_opmode(ah, op_mode);
-
-        /* Clear any pending interrupts
-         * PISR/SISR Not available on 5210 */
-        if (ah->ah_version != AR5K_AR5210)
-                ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
-
-        /* Set RSSI/BRSSI thresholds
-         *
-         * Note: If we decide to set this value
-         * dynamically, keep in mind that when AR5K_RSSI_THR
-         * register is read, it might return 0x40 if we haven't
-         * written anything to it.  Also, BMISS RSSI threshold is zeroed.
-         * So doing a save/restore procedure here isn't the right
-         * choice. Instead, store it in ath5k_hw */
-        ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |
-                                AR5K_TUNE_BMISS_THRES <<
-                                AR5K_RSSI_THR_BMISS_S),
-                                AR5K_RSSI_THR);
-
-        /* MIC QoS support */
-        if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {
-                ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);
-                ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);
-        }
-
-        /* QoS NOACK Policy */
-        if (ah->ah_version == AR5K_AR5212) {
-                ath5k_hw_reg_write(ah,
-                        AR5K_REG_SM(2, AR5K_QOS_NOACK_2BIT_VALUES) |
-                        AR5K_REG_SM(5, AR5K_QOS_NOACK_BIT_OFFSET)  |
-                        AR5K_REG_SM(0, AR5K_QOS_NOACK_BYTE_OFFSET),
-                        AR5K_QOS_NOACK);
-        }
-
+        ath5k_hw_pcu_init(ah, op_mode, mode);
 
         /*
-         * Configure PHY
+         * Initialize PHY
          */
-
-        /* Set channel on PHY */
-        ret = ath5k_hw_channel(ah, channel);
-        if (ret)
+        ret = ath5k_hw_phy_init(ah, channel, mode, false);
+        if (ret) {
+                ATH5K_ERR(ah->ah_sc,
+                        "failed to initialize PHY (%i) !\n", ret);
                 return ret;
-
-        /*
-         * Enable the PHY and wait until completion
-         * This includes BaseBand and Synthesizer
-         * activation.
-         */
-        ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
-
-        /*
-         * On 5211+ read activation -> rx delay
-         * and use it.
-         *
-         * TODO: Half/quarter rate support
-         */
-        if (ah->ah_version != AR5K_AR5210) {
-                u32 delay;
-                delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
-                        AR5K_PHY_RX_DELAY_M;
-                delay = (channel->hw_value & CHANNEL_CCK) ?
-                        ((delay << 2) / 22) : (delay / 10);
-
-                udelay(100 + (2 * delay));
-        } else {
-                mdelay(1);
         }
 
         /*
-         * Perform ADC test to see if baseband is ready
-         * Set TX hold and check ADC test register
-         */
-        phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
-        ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
-        for (i = 0; i <= 20; i++) {
-                if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
-                        break;
-                udelay(200);
-        }
-        ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
-
-        /*
-         * Start automatic gain control calibration
-         *
-         * During AGC calibration RX path is re-routed to
-         * a power detector so we don't receive anything.
-         *
-         * This method is used to calibrate some static offsets
-         * used together with on-the fly I/Q calibration (the
-         * one performed via ath5k_hw_phy_calibrate), which doesn't
-         * interrupt rx path.
-         *
-         * While rx path is re-routed to the power detector we also
-         * start a noise floor calibration to measure the
-         * card's noise floor (the noise we measure when we are not
-         * transmitting or receiving anything).
-         *
-         * If we are in a noisy environment, AGC calibration may time
-         * out and/or noise floor calibration might timeout.
-         */
-        AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
-                                AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
-
-        /* At the same time start I/Q calibration for QAM constellation
-         * -no need for CCK- */
-        ah->ah_calibration = false;
-        if (!(mode == AR5K_MODE_11B)) {
-                ah->ah_calibration = true;
-                AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
-                                AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
-                AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
-                                AR5K_PHY_IQ_RUN);
-        }
-
-        /* Wait for gain calibration to finish (we check for I/Q calibration
-         * during ath5k_phy_calibrate) */
-        if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
-                        AR5K_PHY_AGCCTL_CAL, 0, false)) {
-                ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
-                        channel->center_freq);
-        }
-
-        /* Restore antenna mode */
-        ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
-
-        /* Restore slot time and ACK timeouts */
-        if (ah->ah_coverage_class > 0)
-                ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);
-
-        /*
          * Configure QCUs/DCUs
          */
+        ret = ath5k_hw_init_queues(ah);
+        if (ret)
+                return ret;
 
-        /* TODO: HW Compression support for data queues */
-        /* TODO: Burst prefetch for data queues */
-
-        /*
-         * Reset queues and start beacon timers at the end of the reset routine
-         * This also sets QCU mask on each DCU for 1:1 qcu to dcu mapping
-         * Note: If we want we can assign multiple qcus on one dcu.
-         */
-        for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
-                ret = ath5k_hw_reset_tx_queue(ah, i);
-                if (ret) {
-                        ATH5K_ERR(ah->ah_sc,
-                                "failed to reset TX queue #%d\n", i);
-                        return ret;
-                }
-        }
-
-
-        /*
-         * Configure DMA/Interrupts
-         */
 
         /*
-         * Set Rx/Tx DMA Configuration
-         *
-         * Set standard DMA size (128). Note that
-         * a DMA size of 512 causes rx overruns and tx errors
-         * on pci-e cards (tested on 5424 but since rx overruns
-         * also occur on 5416/5418 with madwifi we set 128
-         * for all PCI-E cards to be safe).
-         *
-         * XXX: need to check 5210 for this
-         * TODO: Check out tx triger level, it's always 64 on dumps but I
-         * guess we can tweak it and see how it goes ;-)
+         * Initialize DMA/Interrupts
          */
-        if (ah->ah_version != AR5K_AR5210) {
-                AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
-                        AR5K_TXCFG_SDMAMR, AR5K_DMASIZE_128B);
-                AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
-                        AR5K_RXCFG_SDMAMW, AR5K_DMASIZE_128B);
-        }
+        ath5k_hw_dma_init(ah);
 
-        /* Pre-enable interrupts on 5211/5212*/
-        if (ah->ah_version != AR5K_AR5210)
-                ath5k_hw_set_imr(ah, ah->ah_imr);
 
         /* Enable 32KHz clock function for AR5212+ chips
          * Set clocks to 32KHz operation and use an
diff --git a/drivers/net/wireless/ath/ath5k/rfbuffer.h b/drivers/net/wireless/ath/ath5k/rfbuffer.h
index 3ac4cff4239d..16b67e84906d 100644
--- a/drivers/net/wireless/ath/ath5k/rfbuffer.h
+++ b/drivers/net/wireless/ath/ath5k/rfbuffer.h
@@ -51,7 +51,7 @@
 struct ath5k_ini_rfbuffer {
         u8      rfb_bank;               /* RF Bank number */
         u16     rfb_ctrl_register;      /* RF Buffer control register */
-        u32     rfb_mode_data[5];       /* RF Buffer data for each mode */
+        u32     rfb_mode_data[3];       /* RF Buffer data for each mode */
 };
 
 /*
@@ -79,8 +79,10 @@ struct ath5k_rf_reg {
  * life easier by using an index for each register
  * instead of a full rfb_field */
 enum ath5k_rf_regs_idx {
+        /* BANK 2 */
+        AR5K_RF_TURBO = 0,
         /* BANK 6 */
-        AR5K_RF_OB_2GHZ = 0,
+        AR5K_RF_OB_2GHZ,
         AR5K_RF_OB_5GHZ,
         AR5K_RF_DB_2GHZ,
         AR5K_RF_DB_5GHZ,
@@ -134,6 +136,9 @@ enum ath5k_rf_regs_idx {
 * RF5111 (Sombrero) *
 \*******************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF5111_RF_TURBO            { 1, 3,   0 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF5111_OB_2GHZ             { 3, 119, 0 }
 #define AR5K_RF5111_DB_2GHZ             { 3, 122, 0 }
@@ -158,6 +163,7 @@ enum ath5k_rf_regs_idx {
 #define AR5K_RF5111_MAX_TIME            { 2, 49,  0 }
 
 static const struct ath5k_rf_reg rf_regs_5111[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF5111_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5111_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5111_DB_2GHZ},
         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5111_OB_5GHZ},
@@ -177,97 +183,52 @@ static const struct ath5k_rf_reg rf_regs_5111[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5111[] = {
-        { 0, 0x989c,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 0, 0x989c,
-            { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
-        { 0, 0x989c,
-            { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
-        { 0, 0x98d4,
-            { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
-        { 1, 0x98d4,
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d4,
-            { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
-        { 3, 0x98d8,
-            { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
-        { 6, 0x989c,
-            { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
-        { 6, 0x989c,
-            { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
-        { 6, 0x989c,
-            { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
-        { 6, 0x989c,
-            { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
-        { 6, 0x98d4,
-            { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
-        { 7, 0x989c,
-            { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
-        { 7, 0x989c,
-            { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
-        { 7, 0x989c,
-            { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
-        { 7, 0x989c,
-            { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
-        { 7, 0x989c,
-            { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
-        { 7, 0x989c,
-            { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
-        { 7, 0x989c,
-            { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00380000, 0x00380000, 0x00380000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 0, 0x989c, { 0x00000000, 0x000000c0, 0x00000080 } },
+        { 0, 0x989c, { 0x000400f9, 0x000400ff, 0x000400fd } },
+        { 0, 0x98d4, { 0x00000000, 0x00000004, 0x00000004 } },
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d4, { 0x00000010, 0x00000010, 0x00000010 } },
+        { 3, 0x98d8, { 0x00601068, 0x00601068, 0x00601068 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x04000000, 0x04000000, 0x04000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x0a000000, 0x00000000 } },
+        { 6, 0x989c, { 0x003800c0, 0x023800c0, 0x003800c0 } },
+        { 6, 0x989c, { 0x00020006, 0x00000006, 0x00020006 } },
+        { 6, 0x989c, { 0x00000089, 0x00000089, 0x00000089 } },
+        { 6, 0x989c, { 0x000000a0, 0x000000a0, 0x000000a0 } },
+        { 6, 0x989c, { 0x00040007, 0x00040007, 0x00040007 } },
+        { 6, 0x98d4, { 0x0000001a, 0x0000001a, 0x0000001a } },
+        { 7, 0x989c, { 0x00000040, 0x00000040, 0x00000040 } },
+        { 7, 0x989c, { 0x00000010, 0x00000010, 0x00000010 } },
+        { 7, 0x989c, { 0x00000008, 0x00000008, 0x00000008 } },
+        { 7, 0x989c, { 0x0000004f, 0x0000004f, 0x0000004f } },
+        { 7, 0x989c, { 0x000000f1, 0x00000061, 0x000000f1 } },
+        { 7, 0x989c, { 0x0000904f, 0x0000904c, 0x0000904f } },
+        { 7, 0x989c, { 0x0000125a, 0x0000129a, 0x0000125a } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000f, 0x0000000e } },
 };
 
 
@@ -276,6 +237,9 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = {
 * RF5112/RF2112 (Derby) *
 \***********************/
 
+/* BANK 2 (Common)                      len  pos col */
+#define AR5K_RF5112X_RF_TURBO           { 1, 1,   2 }
+
 /* BANK 7 (Common)                      len  pos col */
 #define AR5K_RF5112X_GAIN_I             { 6, 14,  0 }
 #define AR5K_RF5112X_MIXVGA_OVR         { 1, 36,  0 }
@@ -307,6 +271,7 @@ static const struct ath5k_ini_rfbuffer rfb_5111[] = {
 #define AR5K_RF5112_PWD(_n)             { 1, (302 - _n), 3 }
 
 static const struct ath5k_rf_reg rf_regs_5112[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF5112X_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5112_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5112_DB_2GHZ},
         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5112_OB_5GHZ},
@@ -335,115 +300,61 @@ static const struct ath5k_rf_reg rf_regs_5112[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5112[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
-        { 3, 0x98dc,
-            { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
-        { 6, 0x989c,
-            { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
-        { 6, 0x989c,
-            { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
-        { 6, 0x989c,
-            { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
-        { 6, 0x989c,
-            { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
-        { 6, 0x989c,
-            { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
-        { 6, 0x989c,
-            { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
-        { 6, 0x989c,
-            { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
-        { 6, 0x989c,
-            { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
-        { 6, 0x989c,
-            { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
-        { 6, 0x989c,
-            { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
-        { 6, 0x989c,
-            { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
-        { 6, 0x989c,
-            { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
-        { 6, 0x989c,
-            { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
-        { 6, 0x989c,
-            { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
-        { 6, 0x989c,
-            { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
-        { 6, 0x989c,
-            { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
-        { 6, 0x989c,
-            { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
-        { 6, 0x989c,
-            { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
-        { 6, 0x989c,
-            { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
-        { 6, 0x989c,
-            { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
-        { 6, 0x989c,
-            { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
-        { 6, 0x989c,
-            { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
-        { 6, 0x989c,
-            { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
-        { 6, 0x989c,
-            { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
-        { 6, 0x989c,
-            { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
-        { 6, 0x989c,
-            { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
-        { 6, 0x989c,
-            { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
-        { 6, 0x989c,
-            { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
-        { 6, 0x98d0,
-            { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
-        { 7, 0x989c,
-            { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
-        { 7, 0x989c,
-            { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
-        { 7, 0x989c,
-            { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
-        { 7, 0x989c,
-            { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
-        { 7, 0x989c,
-            { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
-        { 7, 0x989c,
-            { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
-        { 7, 0x989c,
-            { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
-        { 7, 0x989c,
-            { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
-        { 7, 0x989c,
-            { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
-        { 7, 0x989c,
-            { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
-        { 7, 0x989c,
-            { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
-        { 7, 0x989c,
-            { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
-        { 7, 0x98c4,
-            { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
+        { 3, 0x98dc, { 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
+        { 6, 0x989c, { 0x00a00000, 0x00a00000, 0x00a00000 } },
+        { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00660000, 0x00660000, 0x00660000 } },
+        { 6, 0x989c, { 0x00db0000, 0x00db0000, 0x00db0000 } },
+        { 6, 0x989c, { 0x00f10000, 0x00f10000, 0x00f10000 } },
+        { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
+        { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x008b0000, 0x008b0000, 0x008b0000 } },
+        { 6, 0x989c, { 0x00600000, 0x00600000, 0x00600000 } },
+        { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
+        { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
+        { 6, 0x989c, { 0x00640000, 0x00640000, 0x00640000 } },
+        { 6, 0x989c, { 0x00200000, 0x00200000, 0x00200000 } },
+        { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
+        { 6, 0x989c, { 0x00250000, 0x00250000, 0x00250000 } },
+        { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
+        { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
+        { 6, 0x989c, { 0x00510000, 0x00510000, 0x00510000 } },
+        { 6, 0x989c, { 0x1c040000, 0x1c040000, 0x1c040000 } },
+        { 6, 0x989c, { 0x000a0000, 0x000a0000, 0x000a0000 } },
+        { 6, 0x989c, { 0x00a10000, 0x00a10000, 0x00a10000 } },
+        { 6, 0x989c, { 0x00400000, 0x00400000, 0x00400000 } },
+        { 6, 0x989c, { 0x03090000, 0x03090000, 0x03090000 } },
+        { 6, 0x989c, { 0x06000000, 0x06000000, 0x06000000 } },
+        { 6, 0x989c, { 0x000000b0, 0x000000a8, 0x000000a8 } },
+        { 6, 0x989c, { 0x0000002e, 0x0000002e, 0x0000002e } },
+        { 6, 0x989c, { 0x006c4a41, 0x006c4af1, 0x006c4a61 } },
+        { 6, 0x989c, { 0x0050892a, 0x0050892b, 0x0050892b } },
+        { 6, 0x989c, { 0x00842400, 0x00842400, 0x00842400 } },
+        { 6, 0x989c, { 0x00c69200, 0x00c69200, 0x00c69200 } },
+        { 6, 0x98d0, { 0x0002000c, 0x0002000c, 0x0002000c } },
+        { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
+        { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
+        { 7, 0x989c, { 0x0000000a, 0x00000012, 0x00000012 } },
+        { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
+        { 7, 0x989c, { 0x000000c1, 0x000000c1, 0x000000c1 } },
+        { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
+        { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
+        { 7, 0x989c, { 0x00000022, 0x00000022, 0x00000022 } },
+        { 7, 0x989c, { 0x00000092, 0x00000092, 0x00000092 } },
+        { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
+        { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
+        { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
+        { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
 };
 
 /* RFX112A (Derby 2) */
@@ -477,6 +388,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112[] = {
 #define AR5K_RF5112A_XB5_LVL            { 2, 3,   3 }
 
 static const struct ath5k_rf_reg rf_regs_5112a[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF5112X_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF5112A_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF5112A_DB_2GHZ},
         {6, AR5K_RF_OB_5GHZ,            AR5K_RF5112A_OB_5GHZ},
@@ -515,119 +427,63 @@ static const struct ath5k_rf_reg rf_regs_5112a[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
-        { 6, 0x989c,
-            { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
-        { 6, 0x989c,
-            { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
-        { 6, 0x989c,
-            { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
-        { 6, 0x989c,
-            { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
-        { 6, 0x989c,
-            { 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000, 0x004c0000 } },
-        { 6, 0x989c,
-            { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
-        { 6, 0x989c,
-            { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
-        { 6, 0x989c,
-            { 0x02190000, 0x02190000, 0x02190000, 0x02190000, 0x02190000 } },
-        { 6, 0x989c,
-            { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
-        { 6, 0x989c,
-            { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
-        { 6, 0x989c,
-            { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
-        { 6, 0x989c,
-            { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
-        { 6, 0x989c,
-            { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
-        { 6, 0x989c,
-            { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
-        { 6, 0x989c,
-            { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
-        { 6, 0x989c,
-            { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
-        { 6, 0x989c,
-            { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
-        { 6, 0x989c,
-            { 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080, 0x00f20080 } },
-        { 6, 0x989c,
-            { 0x00270019, 0x00270019, 0x00270019, 0x00270019, 0x00270019 } },
-        { 6, 0x989c,
-            { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
-        { 6, 0x989c,
-            { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
-        { 6, 0x989c,
-            { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
-        { 6, 0x989c,
-            { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
-        { 6, 0x989c,
-            { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
-        { 6, 0x98d8,
-            { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
-        { 7, 0x989c,
-            { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
-        { 7, 0x989c,
-            { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
-        { 7, 0x989c,
-            { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
-        { 7, 0x989c,
-            { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
-        { 7, 0x989c,
-            { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
-        { 7, 0x989c,
-            { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
-        { 7, 0x989c,
-            { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
-        { 7, 0x989c,
-            { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
-        { 7, 0x989c,
-            { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
-        { 7, 0x989c,
-            { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
-        { 7, 0x989c,
-            { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
-        { 7, 0x989c,
-            { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
-        { 7, 0x98c4,
-            { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x03060408, 0x03060408, 0x03060408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00800000, 0x00800000, 0x00800000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00010000, 0x00010000, 0x00010000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00180000, 0x00180000, 0x00180000 } },
+        { 6, 0x989c, { 0x00600000, 0x006e0000, 0x006e0000 } },
+        { 6, 0x989c, { 0x00c70000, 0x00c70000, 0x00c70000 } },
+        { 6, 0x989c, { 0x004b0000, 0x004b0000, 0x004b0000 } },
+        { 6, 0x989c, { 0x04480000, 0x04480000, 0x04480000 } },
+        { 6, 0x989c, { 0x004c0000, 0x004c0000, 0x004c0000 } },
+        { 6, 0x989c, { 0x00e40000, 0x00e40000, 0x00e40000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x043f0000, 0x043f0000, 0x043f0000 } },
+        { 6, 0x989c, { 0x000c0000, 0x000c0000, 0x000c0000 } },
+        { 6, 0x989c, { 0x02190000, 0x02190000, 0x02190000 } },
+        { 6, 0x989c, { 0x00240000, 0x00240000, 0x00240000 } },
+        { 6, 0x989c, { 0x00b40000, 0x00b40000, 0x00b40000 } },
+        { 6, 0x989c, { 0x00990000, 0x00990000, 0x00990000 } },
+        { 6, 0x989c, { 0x00500000, 0x00500000, 0x00500000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00120000, 0x00120000, 0x00120000 } },
+        { 6, 0x989c, { 0xc0320000, 0xc0320000, 0xc0320000 } },
+        { 6, 0x989c, { 0x01740000, 0x01740000, 0x01740000 } },
+        { 6, 0x989c, { 0x00110000, 0x00110000, 0x00110000 } },
+        { 6, 0x989c, { 0x86280000, 0x86280000, 0x86280000 } },
+        { 6, 0x989c, { 0x31840000, 0x31840000, 0x31840000 } },
+        { 6, 0x989c, { 0x00f20080, 0x00f20080, 0x00f20080 } },
+        { 6, 0x989c, { 0x00270019, 0x00270019, 0x00270019 } },
+        { 6, 0x989c, { 0x00000003, 0x00000003, 0x00000003 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x000000b2, 0x000000b2, 0x000000b2 } },
+        { 6, 0x989c, { 0x00b02084, 0x00b02084, 0x00b02084 } },
+        { 6, 0x989c, { 0x004125a4, 0x004125a4, 0x004125a4 } },
+        { 6, 0x989c, { 0x00119220, 0x00119220, 0x00119220 } },
+        { 6, 0x989c, { 0x001a4800, 0x001a4800, 0x001a4800 } },
+        { 6, 0x98d8, { 0x000b0230, 0x000b0230, 0x000b0230 } },
+        { 7, 0x989c, { 0x00000094, 0x00000094, 0x00000094 } },
+        { 7, 0x989c, { 0x00000091, 0x00000091, 0x00000091 } },
+        { 7, 0x989c, { 0x00000012, 0x00000012, 0x00000012 } },
+        { 7, 0x989c, { 0x00000080, 0x00000080, 0x00000080 } },
+        { 7, 0x989c, { 0x000000d9, 0x000000d9, 0x000000d9 } },
+        { 7, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
+        { 7, 0x989c, { 0x000000f0, 0x000000f0, 0x000000f0 } },
+        { 7, 0x989c, { 0x000000a2, 0x000000a2, 0x000000a2 } },
+        { 7, 0x989c, { 0x00000052, 0x00000052, 0x00000052 } },
+        { 7, 0x989c, { 0x000000d4, 0x000000d4, 0x000000d4 } },
+        { 7, 0x989c, { 0x000014cc, 0x000014cc, 0x000014cc } },
+        { 7, 0x989c, { 0x0000048c, 0x0000048c, 0x0000048c } },
+        { 7, 0x98c4, { 0x00000003, 0x00000003, 0x00000003 } },
 };
 
 
@@ -636,11 +492,15 @@ static const struct ath5k_ini_rfbuffer rfb_5112a[] = {
 * RF2413 (Griffin) *
 \******************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF2413_RF_TURBO            { 1, 1,   2 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF2413_OB_2GHZ             { 3, 168, 0 }
 #define AR5K_RF2413_DB_2GHZ             { 3, 165, 0 }
 
 static const struct ath5k_rf_reg rf_regs_2413[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF2413_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2413_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2413_DB_2GHZ},
 };
@@ -649,73 +509,40 @@ static const struct ath5k_rf_reg rf_regs_2413[] = {
  * XXX: a/aTurbo ???
  */
 static const struct ath5k_ini_rfbuffer rfb_2413[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000, 0xf0000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x03000000, 0x03000000, 0x03000000, 0x03000000, 0x03000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x40400000, 0x40400000, 0x40400000, 0x40400000, 0x40400000 } },
-        { 6, 0x989c,
-            { 0x65050000, 0x65050000, 0x65050000, 0x65050000, 0x65050000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00420000, 0x00420000, 0x00420000, 0x00420000, 0x00420000 } },
-        { 6, 0x989c,
-            { 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000, 0x00b50000 } },
-        { 6, 0x989c,
-            { 0x00030000, 0x00030000, 0x00030000, 0x00030000, 0x00030000 } },
-        { 6, 0x989c,
-            { 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000, 0x00f70000 } },
-        { 6, 0x989c,
-            { 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000, 0x009d0000 } },
-        { 6, 0x989c,
-            { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
-        { 6, 0x989c,
-            { 0x04220000, 0x04220000, 0x04220000, 0x04220000, 0x04220000 } },
-        { 6, 0x989c,
-            { 0x00230018, 0x00230018, 0x00230018, 0x00230018, 0x00230018 } },
-        { 6, 0x989c,
-            { 0x00280000, 0x00280000, 0x00280060, 0x00280060, 0x00280060 } },
-        { 6, 0x989c,
-            { 0x005000c0, 0x005000c0, 0x005000c3, 0x005000c3, 0x005000c3 } },
-        { 6, 0x989c,
-            { 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f, 0x0004007f } },
-        { 6, 0x989c,
-            { 0x00000458, 0x00000458, 0x00000458, 0x00000458, 0x00000458 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000, 0x0000c000 } },
-        { 6, 0x98d8,
-            { 0x00400230, 0x00400230, 0x00400230, 0x00400230, 0x00400230 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0xf0000000, 0xf0000000, 0xf0000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x03000000, 0x03000000, 0x03000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x40400000, 0x40400000, 0x40400000 } },
+        { 6, 0x989c, { 0x65050000, 0x65050000, 0x65050000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00420000, 0x00420000, 0x00420000 } },
+        { 6, 0x989c, { 0x00b50000, 0x00b50000, 0x00b50000 } },
+        { 6, 0x989c, { 0x00030000, 0x00030000, 0x00030000 } },
+        { 6, 0x989c, { 0x00f70000, 0x00f70000, 0x00f70000 } },
+        { 6, 0x989c, { 0x009d0000, 0x009d0000, 0x009d0000 } },
+        { 6, 0x989c, { 0x00220000, 0x00220000, 0x00220000 } },
+        { 6, 0x989c, { 0x04220000, 0x04220000, 0x04220000 } },
+        { 6, 0x989c, { 0x00230018, 0x00230018, 0x00230018 } },
+        { 6, 0x989c, { 0x00280000, 0x00280060, 0x00280060 } },
+        { 6, 0x989c, { 0x005000c0, 0x005000c3, 0x005000c3 } },
+        { 6, 0x989c, { 0x0004007f, 0x0004007f, 0x0004007f } },
+        { 6, 0x989c, { 0x00000458, 0x00000458, 0x00000458 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x0000c000, 0x0000c000, 0x0000c000 } },
+        { 6, 0x98d8, { 0x00400230, 0x00400230, 0x00400230 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 
@@ -724,88 +551,57 @@ static const struct ath5k_ini_rfbuffer rfb_2413[] = {
 * RF2315/RF2316 (Cobra SoC) *
 \***************************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF2316_RF_TURBO            { 1, 1,   2 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF2316_OB_2GHZ             { 3, 178, 0 }
 #define AR5K_RF2316_DB_2GHZ             { 3, 175, 0 }
 
 static const struct ath5k_rf_reg rf_regs_2316[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF2316_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2316_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2316_DB_2GHZ},
 };
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_2316[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000, 0xc0000000 } },
-        { 6, 0x989c,
-            { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
-        { 6, 0x989c,
-            { 0x02000000, 0x02000000, 0x02000000, 0x02000000, 0x02000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000, 0xf8000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x95150000, 0x95150000, 0x95150000, 0x95150000, 0x95150000 } },
-        { 6, 0x989c,
-            { 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000, 0xc1000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00080000, 0x00080000, 0x00080000, 0x00080000, 0x00080000 } },
-        { 6, 0x989c,
-            { 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000, 0x00d50000 } },
-        { 6, 0x989c,
-            { 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000, 0x000e0000 } },
-        { 6, 0x989c,
-            { 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
-        { 6, 0x989c,
-            { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
-        { 6, 0x989c,
-            { 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000, 0x008a0000 } },
-        { 6, 0x989c,
-            { 0x10880000, 0x10880000, 0x10880000, 0x10880000, 0x10880000 } },
-        { 6, 0x989c,
-            { 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060, 0x008c0060 } },
-        { 6, 0x989c,
-            { 0x00a00000, 0x00a00000, 0x00a00080, 0x00a00080, 0x00a00080 } },
-        { 6, 0x989c,
-            { 0x00400000, 0x00400000, 0x0040000d, 0x0040000d, 0x0040000d } },
-        { 6, 0x989c,
-            { 0x00110400, 0x00110400, 0x00110400, 0x00110400, 0x00110400 } },
-        { 6, 0x989c,
-            { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
-        { 6, 0x989c,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 6, 0x989c,
-            { 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00, 0x00000b00 } },
-        { 6, 0x989c,
-            { 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8, 0x00000be8 } },
-        { 6, 0x98c0,
-            { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0xc0000000, 0xc0000000, 0xc0000000 } },
+        { 6, 0x989c, { 0x0f000000, 0x0f000000, 0x0f000000 } },
+        { 6, 0x989c, { 0x02000000, 0x02000000, 0x02000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0xf8000000, 0xf8000000, 0xf8000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x95150000, 0x95150000, 0x95150000 } },
+        { 6, 0x989c, { 0xc1000000, 0xc1000000, 0xc1000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00080000, 0x00080000, 0x00080000 } },
+        { 6, 0x989c, { 0x00d50000, 0x00d50000, 0x00d50000 } },
+        { 6, 0x989c, { 0x000e0000, 0x000e0000, 0x000e0000 } },
+        { 6, 0x989c, { 0x00dc0000, 0x00dc0000, 0x00dc0000 } },
+        { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
+        { 6, 0x989c, { 0x008a0000, 0x008a0000, 0x008a0000 } },
+        { 6, 0x989c, { 0x10880000, 0x10880000, 0x10880000 } },
+        { 6, 0x989c, { 0x008c0060, 0x008c0060, 0x008c0060 } },
+        { 6, 0x989c, { 0x00a00000, 0x00a00080, 0x00a00080 } },
+        { 6, 0x989c, { 0x00400000, 0x0040000d, 0x0040000d } },
+        { 6, 0x989c, { 0x00110400, 0x00110400, 0x00110400 } },
+        { 6, 0x989c, { 0x00000060, 0x00000060, 0x00000060 } },
+        { 6, 0x989c, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 6, 0x989c, { 0x00000b00, 0x00000b00, 0x00000b00 } },
+        { 6, 0x989c, { 0x00000be8, 0x00000be8, 0x00000be8 } },
+        { 6, 0x98c0, { 0x00010000, 0x00010000, 0x00010000 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 
@@ -835,93 +631,50 @@ static const struct ath5k_rf_reg rf_regs_5413[] = {
 
 /* Default mode specific settings */
 static const struct ath5k_ini_rfbuffer rfb_5413[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
-        { 3, 0x98dc,
-            { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } },
-        { 6, 0x989c,
-            { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } },
-        { 6, 0x989c,
-            { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } },
-        { 6, 0x989c,
-            { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } },
-        { 6, 0x989c,
-            { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
-        { 6, 0x989c,
-            { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
-        { 6, 0x989c,
-            { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
-        { 6, 0x989c,
-            { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } },
-        { 6, 0x989c,
-            { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } },
-        { 6, 0x989c,
-            { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
-        { 6, 0x989c,
-            { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } },
-        { 6, 0x989c,
-            { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } },
-        { 6, 0x989c,
-            { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } },
-        { 6, 0x989c,
-            { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } },
-        { 6, 0x989c,
-            { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } },
-        { 6, 0x989c,
-            { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } },
-        { 6, 0x989c,
-            { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } },
-        { 6, 0x989c,
-            { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } },
-        { 6, 0x989c,
-            { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } },
-        { 6, 0x989c,
-            { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } },
-        { 6, 0x989c,
-            { 0x00510040, 0x00510040, 0x00510040, 0x00510040, 0x00510040 } },
-        { 6, 0x989c,
-            { 0x005000da, 0x005000da, 0x005000da, 0x005000da, 0x005000da } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } },
-        { 6, 0x989c,
-            { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00002c00 } },
-        { 6, 0x98c8,
-            { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x00000008, 0x00000008, 0x00000008 } },
+        { 3, 0x98dc, { 0x00a000c0, 0x00e000c0, 0x00e000c0 } },
+        { 6, 0x989c, { 0x33000000, 0x33000000, 0x33000000 } },
+        { 6, 0x989c, { 0x01000000, 0x01000000, 0x01000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x1f000000, 0x1f000000, 0x1f000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00b80000, 0x00b80000, 0x00b80000 } },
+        { 6, 0x989c, { 0x00b70000, 0x00b70000, 0x00b70000 } },
+        { 6, 0x989c, { 0x00840000, 0x00840000, 0x00840000 } },
+        { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
+        { 6, 0x989c, { 0x00c00000, 0x00c00000, 0x00c00000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
+        { 6, 0x989c, { 0x00d70000, 0x00d70000, 0x00d70000 } },
+        { 6, 0x989c, { 0x00610000, 0x00610000, 0x00610000 } },
+        { 6, 0x989c, { 0x00fe0000, 0x00fe0000, 0x00fe0000 } },
+        { 6, 0x989c, { 0x00de0000, 0x00de0000, 0x00de0000 } },
+        { 6, 0x989c, { 0x007f0000, 0x007f0000, 0x007f0000 } },
+        { 6, 0x989c, { 0x043d0000, 0x043d0000, 0x043d0000 } },
+        { 6, 0x989c, { 0x00770000, 0x00770000, 0x00770000 } },
+        { 6, 0x989c, { 0x00440000, 0x00440000, 0x00440000 } },
+        { 6, 0x989c, { 0x00980000, 0x00980000, 0x00980000 } },
+        { 6, 0x989c, { 0x00100080, 0x00100080, 0x00100080 } },
+        { 6, 0x989c, { 0x0005c034, 0x0005c034, 0x0005c034 } },
+        { 6, 0x989c, { 0x003100f0, 0x003100f0, 0x003100f0 } },
+        { 6, 0x989c, { 0x000c011f, 0x000c011f, 0x000c011f } },
+        { 6, 0x989c, { 0x00510040, 0x00510040, 0x00510040 } },
+        { 6, 0x989c, { 0x005000da, 0x005000da, 0x005000da } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00004044, 0x00004044, 0x00004044 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x000060c0, 0x000060c0, 0x000060c0 } },
+        { 6, 0x989c, { 0x00002c00, 0x00003600, 0x00003600 } },
+        { 6, 0x98c8, { 0x00000403, 0x00040403, 0x00040403 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 
@@ -931,92 +684,59 @@ static const struct ath5k_ini_rfbuffer rfb_5413[] = {
 * AR2317 (Spider SoC)       *
 \***************************/
 
+/* BANK 2                               len  pos col */
+#define AR5K_RF2425_RF_TURBO            { 1, 1,   2 }
+
 /* BANK 6                               len  pos col */
 #define AR5K_RF2425_OB_2GHZ             { 3, 193, 0 }
 #define AR5K_RF2425_DB_2GHZ             { 3, 190, 0 }
 
 static const struct ath5k_rf_reg rf_regs_2425[] = {
+        {2, AR5K_RF_TURBO,              AR5K_RF2425_RF_TURBO},
         {6, AR5K_RF_OB_2GHZ,            AR5K_RF2425_OB_2GHZ},
         {6, AR5K_RF_DB_2GHZ,            AR5K_RF2425_DB_2GHZ},
 };
 
 /* Default mode specific settings
- * XXX: a/aTurbo ?
  */
 static const struct ath5k_ini_rfbuffer rfb_2425[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
-        { 6, 0x989c,
-            { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
-        { 6, 0x989c,
-            { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
-        { 6, 0x989c,
-            { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
-        { 6, 0x989c,
-            { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
-        { 6, 0x989c,
-            { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
-        { 6, 0x989c,
-            { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
-        { 6, 0x989c,
-            { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
-        { 6, 0x989c,
-            { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
-        { 6, 0x989c,
-            { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
-        { 6, 0x98c4,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
+        { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
+        { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
+        { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
+        { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
+        { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
+        { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
+        { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
+        { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
+        { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
+        { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 /*
@@ -1024,158 +744,85 @@ static const struct ath5k_ini_rfbuffer rfb_2425[] = {
  * bank modification and get rid of this
  */
 static const struct ath5k_ini_rfbuffer rfb_2317[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02011408, 0x02001408, 0x02001408, 0x02011408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
-        { 6, 0x989c,
-            { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
-        { 6, 0x989c,
-            { 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000, 0x00e70000 } },
-        { 6, 0x989c,
-            { 0x00140100, 0x00140100, 0x00140100, 0x00140100, 0x00140100 } },
-        { 6, 0x989c,
-            { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
-        { 6, 0x989c,
-            { 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a, 0x0007001a } },
-        { 6, 0x989c,
-            { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
-        { 6, 0x989c,
-            { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
-        { 6, 0x989c,
-            { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
-        { 6, 0x989c,
-            { 0x00009688, 0x00009688, 0x00009688, 0x00009688, 0x00009688 } },
-        { 6, 0x98c4,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
+        { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
+        { 6, 0x989c, { 0x00e70000, 0x00e70000, 0x00e70000 } },
+        { 6, 0x989c, { 0x00140100, 0x00140100, 0x00140100 } },
+        { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
+        { 6, 0x989c, { 0x0007001a, 0x0007001a, 0x0007001a } },
+        { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
+        { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
+        { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
+        { 6, 0x989c, { 0x00009688, 0x00009688, 0x00009688 } },
+        { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
 
 /*
  * TODO: Handle the few differences with swan during
  * bank modification and get rid of this
- * XXX: a/aTurbo ?
  */
 static const struct ath5k_ini_rfbuffer rfb_2417[] = {
-        { 1, 0x98d4,
-        /*     mode a/XR  mode aTurbo    mode b     mode g    mode gTurbo */
-            { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
-        { 2, 0x98d0,
-            { 0x02001408, 0x02001408, 0x02001408, 0x02001408, 0x02001408 } },
-        { 3, 0x98dc,
-            { 0x00a020c0, 0x00a020c0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } },
-        { 6, 0x989c,
-            { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00100000, 0x00100000, 0x00100000, 0x00100000, 0x00100000 } },
-        { 6, 0x989c,
-            { 0x00020000, 0x00020000, 0x00020000, 0x00020000, 0x00020000 } },
-        { 6, 0x989c,
-            { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
-        { 6, 0x989c,
-            { 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000, 0x00f80000 } },
-        { 6, 0x989c,
-            { 0x00e70000, 0x00e70000, 0x80e70000, 0x80e70000, 0x00e70000 } },
-        { 6, 0x989c,
-            { 0x00140000, 0x00140000, 0x00140000, 0x00140000, 0x00140000 } },
-        { 6, 0x989c,
-            { 0x00910040, 0x00910040, 0x00910040, 0x00910040, 0x00910040 } },
-        { 6, 0x989c,
-            { 0x0007001a, 0x0007001a, 0x0207001a, 0x0207001a, 0x0007001a } },
-        { 6, 0x989c,
-            { 0x00410000, 0x00410000, 0x00410000, 0x00410000, 0x00410000 } },
-        { 6, 0x989c,
-            { 0x00810000, 0x00810000, 0x00810060, 0x00810060, 0x00810060 } },
-        { 6, 0x989c,
-            { 0x00020800, 0x00020800, 0x00020803, 0x00020803, 0x00020803 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
-        { 6, 0x989c,
-            { 0x00001660, 0x00001660, 0x00001660, 0x00001660, 0x00001660 } },
-        { 6, 0x989c,
-            { 0x00001688, 0x00001688, 0x00001688, 0x00001688, 0x00001688 } },
-        { 6, 0x98c4,
-            { 0x00000001, 0x00000001, 0x00000001, 0x00000001, 0x00000001 } },
-        { 7, 0x989c,
-            { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } },
-        { 7, 0x989c,
-            { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } },
-        { 7, 0x98cc,
-            { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } },
+        /* BANK / C.R.     A/XR         B           G      */
+        { 1, 0x98d4, { 0x00000020, 0x00000020, 0x00000020 } },
+        { 2, 0x98d0, { 0x02001408, 0x02001408, 0x02001408 } },
+        { 3, 0x98dc, { 0x00a020c0, 0x00e020c0, 0x00e020c0 } },
+        { 6, 0x989c, { 0x10000000, 0x10000000, 0x10000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x002a0000, 0x002a0000, 0x002a0000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00100000, 0x00100000, 0x00100000 } },
+        { 6, 0x989c, { 0x00020000, 0x00020000, 0x00020000 } },
+        { 6, 0x989c, { 0x00730000, 0x00730000, 0x00730000 } },
+        { 6, 0x989c, { 0x00f80000, 0x00f80000, 0x00f80000 } },
+        { 6, 0x989c, { 0x00e70000, 0x80e70000, 0x80e70000 } },
+        { 6, 0x989c, { 0x00140000, 0x00140000, 0x00140000 } },
+        { 6, 0x989c, { 0x00910040, 0x00910040, 0x00910040 } },
+        { 6, 0x989c, { 0x0007001a, 0x0207001a, 0x0207001a } },
+        { 6, 0x989c, { 0x00410000, 0x00410000, 0x00410000 } },
+        { 6, 0x989c, { 0x00810000, 0x00810060, 0x00810060 } },
+        { 6, 0x989c, { 0x00020800, 0x00020803, 0x00020803 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00000000, 0x00000000, 0x00000000 } },
+        { 6, 0x989c, { 0x00001660, 0x00001660, 0x00001660 } },
+        { 6, 0x989c, { 0x00001688, 0x00001688, 0x00001688 } },
+        { 6, 0x98c4, { 0x00000001, 0x00000001, 0x00000001 } },
+        { 7, 0x989c, { 0x00006400, 0x00006400, 0x00006400 } },
+        { 7, 0x989c, { 0x00000800, 0x00000800, 0x00000800 } },
+        { 7, 0x98cc, { 0x0000000e, 0x0000000e, 0x0000000e } },
 };
diff --git a/drivers/net/wireless/ath/ath5k/sysfs.c b/drivers/net/wireless/ath/ath5k/sysfs.c
index 90757de7bf59..929c68cdf8ab 100644
--- a/drivers/net/wireless/ath/ath5k/sysfs.c
+++ b/drivers/net/wireless/ath/ath5k/sysfs.c
@@ -95,7 +95,7 @@ static struct attribute_group ath5k_attribute_group_ani = {
 int
 ath5k_sysfs_register(struct ath5k_softc *sc)
 {
-        struct device *dev = &sc->pdev->dev;
+        struct device *dev = sc->dev;
         int err;
 
         err = sysfs_create_group(&dev->kobj, &ath5k_attribute_group_ani);
@@ -110,7 +110,7 @@ ath5k_sysfs_register(struct ath5k_softc *sc)
 void
 ath5k_sysfs_unregister(struct ath5k_softc *sc)
 {
-        struct device *dev = &sc->pdev->dev;
+        struct device *dev = sc->dev;
 
         sysfs_remove_group(&dev->kobj, &ath5k_attribute_group_ani);
 }
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 1a984b02e9e5..25a6e4417cdb 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -35,10 +35,9 @@ static bool ath_ahb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 
         pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
         if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "%s: flash read failed, offset %08x "
-                          "is out of range\n",
-                          __func__, off);
+                ath_err(common,
+                        "%s: flash read failed, offset %08x is out of range\n",
+                        __func__, off);
                 return false;
         }
 
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 63ccb39cdcd4..2e31c775351f 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -135,8 +135,8 @@ static void ath9k_ani_restart(struct ath_hw *ah)
                 cck_base = AR_PHY_COUNTMAX - ah->config.cck_trig_high;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Writing ofdmbase=%u   cckbase=%u\n", ofdm_base, cck_base);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Writing ofdmbase=%u   cckbase=%u\n", ofdm_base, cck_base);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -267,11 +267,11 @@ static void ath9k_hw_set_ofdm_nil(struct ath_hw *ah, u8 immunityLevel)
 
         aniState->noiseFloor = BEACON_RSSI(ah);
 
-        ath_print(common, ATH_DBG_ANI,
-                  "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
-                  aniState->ofdmNoiseImmunityLevel,
-                  immunityLevel, aniState->noiseFloor,
-                  aniState->rssiThrLow, aniState->rssiThrHigh);
+        ath_dbg(common, ATH_DBG_ANI,
+                "**** ofdmlevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
+                aniState->ofdmNoiseImmunityLevel,
+                immunityLevel, aniState->noiseFloor,
+                aniState->rssiThrLow, aniState->rssiThrHigh);
 
         aniState->ofdmNoiseImmunityLevel = immunityLevel;
 
@@ -334,11 +334,11 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
         const struct ani_cck_level_entry *entry_cck;
 
         aniState->noiseFloor = BEACON_RSSI(ah);
-        ath_print(common, ATH_DBG_ANI,
-                  "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
-                  aniState->cckNoiseImmunityLevel, immunityLevel,
-                  aniState->noiseFloor, aniState->rssiThrLow,
-                  aniState->rssiThrHigh);
+        ath_dbg(common, ATH_DBG_ANI,
+                "**** ccklevel %d=>%d, rssi=%d[lo=%d hi=%d]\n",
+                aniState->cckNoiseImmunityLevel, immunityLevel,
+                aniState->noiseFloor, aniState->rssiThrLow,
+                aniState->rssiThrHigh);
 
         if ((ah->opmode == NL80211_IFTYPE_STATION ||
              ah->opmode == NL80211_IFTYPE_ADHOC) &&
@@ -358,7 +358,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel)
                                      entry_cck->fir_step_level);
 
         /* Skip MRC CCK for pre AR9003 families */
-        if (!AR_SREV_9300_20_OR_LATER(ah))
+        if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah))
                 return;
 
         if (aniState->mrcCCKOff == entry_cck->mrc_cck_on)
@@ -478,8 +478,8 @@ static void ath9k_ani_reset_old(struct ath_hw *ah, bool is_scanning)
 
         if (ah->opmode != NL80211_IFTYPE_STATION
             && ah->opmode != NL80211_IFTYPE_ADHOC) {
-                ath_print(common, ATH_DBG_ANI,
-                          "Reset ANI state opmode %u\n", ah->opmode);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Reset ANI state opmode %u\n", ah->opmode);
                 ah->stats.ast_ani_reset++;
 
                 if (ah->opmode == NL80211_IFTYPE_AP) {
@@ -584,16 +584,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
                     ATH9K_ANI_OFDM_DEF_LEVEL ||
                     aniState->cckNoiseImmunityLevel !=
                     ATH9K_ANI_CCK_DEF_LEVEL) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "Restore defaults: opmode %u "
-                                  "chan %d Mhz/0x%x is_scanning=%d "
-                                  "ofdm:%d cck:%d\n",
-                                  ah->opmode,
-                                  chan->channel,
-                                  chan->channelFlags,
-                                  is_scanning,
-                                  aniState->ofdmNoiseImmunityLevel,
-                                  aniState->cckNoiseImmunityLevel);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "Restore defaults: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
+                                ah->opmode,
+                                chan->channel,
+                                chan->channelFlags,
+                                is_scanning,
+                                aniState->ofdmNoiseImmunityLevel,
+                                aniState->cckNoiseImmunityLevel);
 
                         ath9k_hw_set_ofdm_nil(ah, ATH9K_ANI_OFDM_DEF_LEVEL);
                         ath9k_hw_set_cck_nil(ah, ATH9K_ANI_CCK_DEF_LEVEL);
@@ -602,16 +600,14 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
                 /*
                  * restore historical levels for this channel
                  */
-                ath_print(common, ATH_DBG_ANI,
-                          "Restore history: opmode %u "
-                          "chan %d Mhz/0x%x is_scanning=%d "
-                          "ofdm:%d cck:%d\n",
-                          ah->opmode,
-                          chan->channel,
-                          chan->channelFlags,
-                          is_scanning,
-                          aniState->ofdmNoiseImmunityLevel,
-                          aniState->cckNoiseImmunityLevel);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Restore history: opmode %u chan %d Mhz/0x%x is_scanning=%d ofdm:%d cck:%d\n",
+                        ah->opmode,
+                        chan->channel,
+                        chan->channelFlags,
+                        is_scanning,
+                        aniState->ofdmNoiseImmunityLevel,
+                        aniState->cckNoiseImmunityLevel);
 
                         ath9k_hw_set_ofdm_nil(ah,
                                               aniState->ofdmNoiseImmunityLevel);
@@ -666,19 +662,17 @@ static bool ath9k_hw_ani_read_counters(struct ath_hw *ah)
 
         if (!use_new_ani(ah) && (phyCnt1 < ofdm_base || phyCnt2 < cck_base)) {
                 if (phyCnt1 < ofdm_base) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt1 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt1, ofdm_base);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "phyCnt1 0x%x, resetting counter value to 0x%x\n",
+                                phyCnt1, ofdm_base);
                         REG_WRITE(ah, AR_PHY_ERR_1, ofdm_base);
                         REG_WRITE(ah, AR_PHY_ERR_MASK_1,
                                   AR_PHY_ERR_OFDM_TIMING);
                 }
                 if (phyCnt2 < cck_base) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "phyCnt2 0x%x, resetting "
-                                  "counter value to 0x%x\n",
-                                  phyCnt2, cck_base);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "phyCnt2 0x%x, resetting counter value to 0x%x\n",
+                                phyCnt2, cck_base);
                         REG_WRITE(ah, AR_PHY_ERR_2, cck_base);
                         REG_WRITE(ah, AR_PHY_ERR_MASK_2,
                                   AR_PHY_ERR_CCK_TIMING);
@@ -719,13 +713,12 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan)
         cckPhyErrRate =  aniState->cckPhyErrCount * 1000 /
                          aniState->listenTime;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "listenTime=%d OFDM:%d errs=%d/s CCK:%d "
-                  "errs=%d/s ofdm_turn=%d\n",
-                  aniState->listenTime,
-                  aniState->ofdmNoiseImmunityLevel,
-                  ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
-                  cckPhyErrRate, aniState->ofdmsTurn);
+        ath_dbg(common, ATH_DBG_ANI,
+                "listenTime=%d OFDM:%d errs=%d/s CCK:%d errs=%d/s ofdm_turn=%d\n",
+                aniState->listenTime,
+                aniState->ofdmNoiseImmunityLevel,
+                ofdmPhyErrRate, aniState->cckNoiseImmunityLevel,
+                cckPhyErrRate, aniState->ofdmsTurn);
 
         if (aniState->listenTime > 5 * ah->aniperiod) {
                 if (ofdmPhyErrRate <= ah->config.ofdm_trig_low &&
@@ -755,7 +748,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_ANI, "Enable MIB counters\n");
+        ath_dbg(common, ATH_DBG_ANI, "Enable MIB counters\n");
 
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
 
@@ -777,7 +770,7 @@ void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_ANI, "Disable MIB counters\n");
+        ath_dbg(common, ATH_DBG_ANI, "Disable MIB counters\n");
 
         REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
         ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
@@ -834,10 +827,10 @@ void ath9k_hw_ani_setup(struct ath_hw *ah)
 {
         int i;
 
-        const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
-        const int coarseHigh[] = { -14, -14, -14, -14, -12 };
-        const int coarseLow[] = { -64, -64, -64, -64, -70 };
-        const int firpwr[] = { -78, -78, -78, -78, -80 };
+        static const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
+        static const int coarseHigh[] = { -14, -14, -14, -14, -12 };
+        static const int coarseLow[] = { -64, -64, -64, -64, -70 };
+        static const int firpwr[] = { -78, -78, -78, -78, -80 };
 
         for (i = 0; i < 5; i++) {
                 ah->totalSizeDesired[i] = totalSizeDesired[i];
@@ -852,7 +845,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         int i;
 
-        ath_print(common, ATH_DBG_ANI, "Initialize ANI\n");
+        ath_dbg(common, ATH_DBG_ANI, "Initialize ANI\n");
 
         if (use_new_ani(ah)) {
                 ah->config.ofdm_trig_high = ATH9K_ANI_OFDM_TRIG_HIGH_NEW;
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index ea9f4497f58c..ffcf44a4058b 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -130,9 +130,8 @@ static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
         /* pre-reverse this field */
         tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Force rf_pwd_icsyndiv to %1d on %4d\n",
-                  new_bias, synth_freq);
+        ath_dbg(common, ATH_DBG_CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
+                new_bias, synth_freq);
 
         /* swizzle rf_pwd_icsyndiv */
         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
@@ -173,8 +172,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                         channelSel = ((freq - 704) * 2 - 3040) / 10;
                         bModeSynth = 1;
                 } else {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Invalid channel %u MHz\n", freq);
+                        ath_err(common, "Invalid channel %u MHz\n", freq);
                         return -EINVAL;
                 }
 
@@ -206,8 +204,7 @@ static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
         } else {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Invalid channel %u MHz\n", freq);
+                ath_err(common, "Invalid channel %u MHz\n", freq);
                 return -EINVAL;
         }
 
@@ -244,13 +241,15 @@ static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
         int upper, lower, cur_vit_mask;
         int tmp, new;
         int i;
-        int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                          AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+        static int pilot_mask_reg[4] = {
+                AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
         };
-        int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                         AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+        static int chan_mask_reg[4] = {
+                AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
         };
-        int inc[4] = { 0, 100, 0, 0 };
+        static int inc[4] = { 0, 100, 0, 0 };
 
         int8_t mask_m[123];
         int8_t mask_p[123];
@@ -446,8 +445,7 @@ static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 #define ATH_ALLOC_BANK(bank, size) do { \
                 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
                 if (!bank) { \
-                        ath_print(common, ATH_DBG_FATAL, \
-                                  "Cannot allocate RF banks\n"); \
+                        ath_err(common, "Cannot allocate RF banks\n"); \
                         return -ENOMEM; \
                 } \
         } while (0);
@@ -873,12 +871,11 @@ static int ar5008_hw_process_ini(struct ath_hw *ah,
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), false);
 
         /* Write analog registers */
         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "ar5416SetRfRegs failed\n");
+                ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
                 return -EIO;
         }
 
@@ -964,18 +961,6 @@ static void ar5008_hw_rfbus_done(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
-{
-        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-
-        REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                    AR_GPIO_INPUT_MUX2_RFSILENT);
-
-        ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-        REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar5008_restore_chainmask(struct ath_hw *ah)
 {
         int rx_chainmask = ah->rxchainmask;
@@ -1056,10 +1041,9 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(ah->totalSizeDesired));
                         return false;
                 }
 
@@ -1084,12 +1068,12 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
-                const int m1ThreshLow[] = { 127, 50 };
-                const int m2ThreshLow[] = { 127, 40 };
-                const int m1Thresh[] = { 127, 0x4d };
-                const int m2Thresh[] = { 127, 0x40 };
-                const int m2CountThr[] = { 31, 16 };
-                const int m2CountThrLow[] = { 63, 48 };
+                static const int m1ThreshLow[] = { 127, 50 };
+                static const int m2ThreshLow[] = { 127, 40 };
+                static const int m1Thresh[] = { 127, 0x4d };
+                static const int m2Thresh[] = { 127, 0x40 };
+                static const int m2CountThr[] = { 31, 16 };
+                static const int m2CountThrLow[] = { 63, 48 };
                 u32 on = param ? 1 : 0;
 
                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
@@ -1141,7 +1125,7 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
-                const int weakSigThrCck[] = { 8, 6 };
+                static const int weakSigThrCck[] = { 8, 6 };
                 u32 high = param ? 1 : 0;
 
                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
@@ -1157,14 +1141,13 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_FIRSTEP_LEVEL:{
-                const int firstep[] = { 0, 4, 8 };
+                static const int firstep[] = { 0, 4, 8 };
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep));
                         return false;
                 }
                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
@@ -1178,14 +1161,13 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
                 break;
         }
         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
-                const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
+                static const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "level out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1));
                         return false;
                 }
                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
@@ -1201,25 +1183,22 @@ static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
-        ath_print(common, ATH_DBG_ANI,
-                  "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
-                  "ofdmWeakSigDetectOff=%d\n",
-                  aniState->noiseImmunityLevel,
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff);
-        ath_print(common, ATH_DBG_ANI,
-                  "cckWeakSigThreshold=%d, "
-                  "firstepLevel=%d, listenTime=%d\n",
-                  aniState->cckWeakSigThreshold,
-                  aniState->firstepLevel,
-                  aniState->listenTime);
-        ath_print(common, ATH_DBG_ANI,
+        ath_dbg(common, ATH_DBG_ANI, "ANI parameters:\n");
+        ath_dbg(common, ATH_DBG_ANI,
+                "noiseImmunityLevel=%d, spurImmunityLevel=%d, ofdmWeakSigDetectOff=%d\n",
+                aniState->noiseImmunityLevel,
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff);
+        ath_dbg(common, ATH_DBG_ANI,
+                "cckWeakSigThreshold=%d, firstepLevel=%d, listenTime=%d\n",
+                aniState->cckWeakSigThreshold,
+                aniState->firstepLevel,
+                aniState->listenTime);
+        ath_dbg(common, ATH_DBG_ANI,
                 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
                 aniState->ofdmPhyErrCount,
                 aniState->cckPhyErrCount);
@@ -1304,12 +1283,12 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                 if (!on != aniState->ofdmWeakSigDetectOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: ofdm weak signal: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->ofdmWeakSigDetectOff ?
-                                        "on" : "off",
-                                  on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: ofdm weak signal: %s=>%s\n",
+                                chan->channel,
+                                !aniState->ofdmWeakSigDetectOff ?
+                                "on" : "off",
+                                on ? "on" : "off");
                         if (on)
                                 ah->stats.ast_ani_ofdmon++;
                         else
@@ -1322,11 +1301,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_FIRSTEP_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep_table));
                         return false;
                 }
 
@@ -1361,24 +1338,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                               AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
 
                 if (level != aniState->firstepLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.firstep);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep_low[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.firstepLow);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value,
+                                aniState->iniDef.firstep);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value2,
+                                aniState->iniDef.firstepLow);
                         if (level > aniState->firstepLevel)
                                 ah->stats.ast_ani_stepup++;
                         else if (level < aniState->firstepLevel)
@@ -1391,11 +1366,9 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1_table));
                         return false;
                 }
                 /*
@@ -1429,24 +1402,22 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
                               AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
 
                 if (level != aniState->spurImmunityLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.cycpwrThr1);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1Ext[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.cycpwrThr1Ext);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value,
+                                aniState->iniDef.cycpwrThr1);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value2,
+                                aniState->iniDef.cycpwrThr1Ext);
                         if (level > aniState->spurImmunityLevel)
                                 ah->stats.ast_ani_spurup++;
                         else if (level < aniState->spurImmunityLevel)
@@ -1465,22 +1436,19 @@ static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                  "MRCcck=%s listenTime=%d "
-                  "ofdmErrs=%d cckErrs=%d\n",
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
-                  aniState->firstepLevel,
-                  !aniState->mrcCCKOff ? "on" : "off",
-                  aniState->listenTime,
-                  aniState->ofdmPhyErrCount,
-                  aniState->cckPhyErrCount);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+                aniState->firstepLevel,
+                !aniState->mrcCCKOff ? "on" : "off",
+                aniState->listenTime,
+                aniState->ofdmPhyErrCount,
+                aniState->cckPhyErrCount);
         return true;
 }
 
@@ -1490,25 +1458,25 @@ static void ar5008_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
-        nfarray[2] = sign_extend(nf, 9);
+        nfarray[2] = sign_extend32(nf, 8);
 
         if (!IS_CHAN_HT40(ah->curchan))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-        nfarray[3] = sign_extend(nf, 9);
+        nfarray[3] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
-        nfarray[4] = sign_extend(nf, 9);
+        nfarray[4] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
-        nfarray[5] = sign_extend(nf, 9);
+        nfarray[5] = sign_extend32(nf, 8);
 }
 
 /*
@@ -1526,13 +1494,12 @@ static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
 
         iniDef = &aniState->iniDef;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
-                  ah->hw_version.macVersion,
-                  ah->hw_version.macRev,
-                  ah->opmode,
-                  chan->channel,
-                  chan->channelFlags);
+        ath_dbg(common, ATH_DBG_ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+                ah->hw_version.macVersion,
+                ah->hw_version.macRev,
+                ah->opmode,
+                chan->channel,
+                chan->channelFlags);
 
         val = REG_READ(ah, AR_PHY_SFCORR);
         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1579,10 +1546,55 @@ static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
 }
 
+static void ar5008_hw_set_radar_params(struct ath_hw *ah,
+                                       struct ath_hw_radar_conf *conf)
+{
+        u32 radar_0 = 0, radar_1 = 0;
+
+        if (!conf) {
+                REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+                return;
+        }
+
+        radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+        radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+        radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+        radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+        radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+        radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+        radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+        radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+        radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+        radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+        radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+        REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+        REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+        if (conf->ext_channel)
+                REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+        else
+                REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
+{
+        struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+        conf->fir_power = -33;
+        conf->radar_rssi = 20;
+        conf->pulse_height = 10;
+        conf->pulse_rssi = 24;
+        conf->pulse_inband = 15;
+        conf->pulse_maxlen = 255;
+        conf->pulse_inband_step = 12;
+        conf->radar_inband = 8;
+}
+
 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        const u32 ar5416_cca_regs[6] = {
+        static const u32 ar5416_cca_regs[6] = {
                 AR_PHY_CCA,
                 AR_PHY_CH1_CCA,
                 AR_PHY_CH2_CCA,
@@ -1605,10 +1617,10 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
         priv_ops->rfbus_req = ar5008_hw_rfbus_req;
         priv_ops->rfbus_done = ar5008_hw_rfbus_done;
-        priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
         priv_ops->restore_chainmask = ar5008_restore_chainmask;
         priv_ops->set_diversity = ar5008_set_diversity;
         priv_ops->do_getnf = ar5008_hw_do_getnf;
+        priv_ops->set_radar_params = ar5008_hw_set_radar_params;
 
         if (modparam_force_new_ani) {
                 priv_ops->ani_control = ar5008_hw_ani_control_new;
@@ -1624,5 +1636,6 @@ void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
                 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
 
         ar5008_hw_set_nf_limits(ah);
+        ar5008_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
index 15f62cd0cc38..01880aa13e36 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c
@@ -39,18 +39,18 @@ static void ar9002_hw_setup_calibration(struct ath_hw *ah,
         switch (currCal->calData->calType) {
         case IQ_MISMATCH_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting IQ Mismatch Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting IQ Mismatch Calibration\n");
                 break;
         case ADC_GAIN_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting ADC Gain Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting ADC Gain Calibration\n");
                 break;
         case ADC_DC_CAL:
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting ADC DC Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting ADC DC Calibration\n");
                 break;
         }
 
@@ -107,11 +107,11 @@ static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
                 ah->totalIqCorrMeas[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
-                          ah->cal_samples, i, ah->totalPowerMeasI[i],
-                          ah->totalPowerMeasQ[i],
-                          ah->totalIqCorrMeas[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+                        ah->cal_samples, i, ah->totalPowerMeasI[i],
+                        ah->totalPowerMeasQ[i],
+                        ah->totalIqCorrMeas[i]);
         }
 }
 
@@ -129,14 +129,13 @@ static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
                 ah->totalAdcQEvenPhase[i] +=
                         REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
-                          "oddq=0x%08x; evenq=0x%08x;\n",
-                          ah->cal_samples, i,
-                          ah->totalAdcIOddPhase[i],
-                          ah->totalAdcIEvenPhase[i],
-                          ah->totalAdcQOddPhase[i],
-                          ah->totalAdcQEvenPhase[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+                        ah->cal_samples, i,
+                        ah->totalAdcIOddPhase[i],
+                        ah->totalAdcIEvenPhase[i],
+                        ah->totalAdcQOddPhase[i],
+                        ah->totalAdcQEvenPhase[i]);
         }
 }
 
@@ -154,14 +153,13 @@ static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
                 ah->totalAdcDcOffsetQEvenPhase[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
 
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
-                          "oddq=0x%08x; evenq=0x%08x;\n",
-                          ah->cal_samples, i,
-                          ah->totalAdcDcOffsetIOddPhase[i],
-                          ah->totalAdcDcOffsetIEvenPhase[i],
-                          ah->totalAdcDcOffsetQOddPhase[i],
-                          ah->totalAdcDcOffsetQEvenPhase[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
+                        ah->cal_samples, i,
+                        ah->totalAdcDcOffsetIOddPhase[i],
+                        ah->totalAdcDcOffsetIEvenPhase[i],
+                        ah->totalAdcDcOffsetQOddPhase[i],
+                        ah->totalAdcDcOffsetQEvenPhase[i]);
         }
 }
 
@@ -178,13 +176,13 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 powerMeasQ = ah->totalPowerMeasQ[i];
                 iqCorrMeas = ah->totalIqCorrMeas[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting IQ Cal and Correction for Chain %d\n",
-                          i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting IQ Cal and Correction for Chain %d\n",
+                        i);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
-                          i, ah->totalIqCorrMeas[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
 
@@ -193,12 +191,12 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iqCorrNeg = 1;
                 }
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-                ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
-                          iqCorrNeg);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
+                ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+                        iqCorrNeg);
 
                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
                 qCoffDenom = powerMeasQ / 64;
@@ -207,14 +205,14 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                     (qCoffDenom != 0)) {
                         iCoff = iqCorrMeas / iCoffDenom;
                         qCoff = powerMeasI / qCoffDenom - 64;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                         iCoff = iCoff & 0x3f;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
                         if (iqCorrNeg == 0x0)
                                 iCoff = 0x40 - iCoff;
 
@@ -223,9 +221,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         else if (qCoff <= -16)
                                 qCoff = -16;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                  i, iCoff, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
+                                i, iCoff, qCoff);
 
                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
@@ -233,9 +231,9 @@ static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
                                       AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
                                       qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ Cal and Correction done for Chain %d\n",
-                                  i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "IQ Cal and Correction done for Chain %d\n",
+                                i);
                 }
         }
 
@@ -255,21 +253,21 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                 qOddMeasOffset = ah->totalAdcQOddPhase[i];
                 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting ADC Gain Cal for Chain %d\n", i);
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
-                          iOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_i = 0x%08x\n", i,
-                          iEvenMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
-                          qOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_q = 0x%08x\n", i,
-                          qEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting ADC Gain Cal for Chain %d\n", i);
+
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
+                        iOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_i = 0x%08x\n", i,
+                        iEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
+                        qOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_q = 0x%08x\n", i,
+                        qEvenMeasOffset);
 
                 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
                         iGainMismatch =
@@ -279,20 +277,20 @@ static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
                                 ((qOddMeasOffset * 32) /
                                  qEvenMeasOffset) & 0x3f;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d gain_mismatch_i = 0x%08x\n", i,
-                                  iGainMismatch);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d gain_mismatch_q = 0x%08x\n", i,
-                                  qGainMismatch);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d gain_mismatch_i = 0x%08x\n", i,
+                                iGainMismatch);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d gain_mismatch_q = 0x%08x\n", i,
+                                qGainMismatch);
 
                         val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
                         val &= 0xfffff000;
                         val |= (qGainMismatch) | (iGainMismatch << 6);
                         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "ADC Gain Cal done for Chain %d\n", i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "ADC Gain Cal done for Chain %d\n", i);
                 }
         }
 
@@ -317,41 +315,41 @@ static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
                 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
                 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                           "Starting ADC DC Offset Cal for Chain %d\n", i);
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_i = %d\n", i,
-                          iOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_i = %d\n", i,
-                          iEvenMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_odd_q = %d\n", i,
-                          qOddMeasOffset);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_even_q = %d\n", i,
-                          qEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting ADC DC Offset Cal for Chain %d\n", i);
+
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_i = %d\n", i,
+                        iOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_i = %d\n", i,
+                        iEvenMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_odd_q = %d\n", i,
+                        qOddMeasOffset);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_even_q = %d\n", i,
+                        qEvenMeasOffset);
 
                 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
                                numSamples) & 0x1ff;
                 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
                                numSamples) & 0x1ff;
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
-                          iDcMismatch);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
-                          qDcMismatch);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
+                        iDcMismatch);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
+                        qDcMismatch);
 
                 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
                 val &= 0xc0000fff;
                 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
                 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "ADC DC Offset Cal done for Chain %d\n", i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "ADC DC Offset Cal done for Chain %d\n", i);
         }
 
         REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
@@ -540,7 +538,7 @@ static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
                 { 0x7838, 0 },
         };
 
-        ath_print(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
 
         /* PA CAL is not needed for high power solution */
         if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -721,9 +719,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                   AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
-                        ath_print(common, ATH_DBG_CALIBRATE, "offset "
-                                  "calibration failed to complete in "
-                                  "1ms; noisy ??\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "offset calibration failed to complete in 1ms; noisy environment?\n");
                         return false;
                 }
                 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
@@ -736,8 +733,8 @@ static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                           0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE, "offset calibration "
-                          "failed to complete in 1ms; noisy ??\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "offset calibration failed to complete in 1ms; noisy environment?\n");
                 return false;
         }
 
@@ -829,9 +826,8 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
                 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
                                    AR_PHY_AGC_CONTROL_CAL,
                                    0, AH_WAIT_TIMEOUT)) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "offset calibration failed to "
-                                  "complete in 1ms; noisy environment?\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "offset calibration failed to complete in 1ms; noisy environment?\n");
                         return false;
                 }
 
@@ -866,19 +862,19 @@ static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
 
                         INIT_CAL(&ah->adcgain_caldata);
                         INSERT_CAL(ah, &ah->adcgain_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling ADC Gain Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "enabling ADC Gain Calibration.\n");
 
                         INIT_CAL(&ah->adcdc_caldata);
                         INSERT_CAL(ah, &ah->adcdc_caldata);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "enabling ADC DC Calibration.\n");
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "enabling ADC DC Calibration.\n");
                 }
 
                 INIT_CAL(&ah->iq_caldata);
                 INSERT_CAL(ah, &ah->iq_caldata);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling IQ Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling IQ Calibration.\n");
 
                 ah->cal_list_curr = ah->cal_list;
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_hw.c b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
index 48261b7252d0..f8a7771faee2 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
@@ -22,28 +22,10 @@
 
 int modparam_force_new_ani;
 module_param_named(force_new_ani, modparam_force_new_ani, int, 0444);
-MODULE_PARM_DESC(nohwcrypt, "Force new ANI for AR5008, AR9001, AR9002");
+MODULE_PARM_DESC(force_new_ani, "Force new ANI for AR5008, AR9001, AR9002");
 
 /* General hardware code for the A5008/AR9001/AR9002 hadware families */
 
-static bool ar9002_hw_macversion_supported(u32 macversion)
-{
-        switch (macversion) {
-        case AR_SREV_VERSION_5416_PCI:
-        case AR_SREV_VERSION_5416_PCIE:
-        case AR_SREV_VERSION_9160:
-        case AR_SREV_VERSION_9100:
-        case AR_SREV_VERSION_9280:
-        case AR_SREV_VERSION_9285:
-        case AR_SREV_VERSION_9287:
-        case AR_SREV_VERSION_9271:
-                return true;
-        default:
-                break;
-        }
-        return false;
-}
-
 static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
 {
         if (AR_SREV_9271(ah)) {
@@ -494,9 +476,9 @@ int ar9002_hw_rf_claim(struct ath_hw *ah)
         case AR_RAD2122_SREV_MAJOR:
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Radio Chip Rev 0x%02X not supported\n",
-                          val & AR_RADIO_SREV_MAJOR);
+                ath_err(ath9k_hw_common(ah),
+                        "Radio Chip Rev 0x%02X not supported\n",
+                        val & AR_RADIO_SREV_MAJOR);
                 return -EOPNOTSUPP;
         }
 
@@ -565,7 +547,6 @@ void ar9002_hw_attach_ops(struct ath_hw *ah)
 
         priv_ops->init_mode_regs = ar9002_hw_init_mode_regs;
         priv_ops->init_mode_gain_regs = ar9002_hw_init_mode_gain_regs;
-        priv_ops->macversion_supported = ar9002_hw_macversion_supported;
 
         ops->config_pci_powersave = ar9002_hw_configpcipowersave;
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_mac.c b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
index 50dda394f8be..399ab3bb299b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_mac.c
@@ -90,13 +90,10 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 
                 *masked = isr & ATH9K_INT_COMMON;
 
-                if (ah->config.rx_intr_mitigation) {
-                        if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
-                                *masked |= ATH9K_INT_RX;
-                }
-
-                if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+                if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM |
+                           AR_ISR_RXOK | AR_ISR_RXERR))
                         *masked |= ATH9K_INT_RX;
+
                 if (isr &
                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
                      AR_ISR_TXEOL)) {
@@ -114,16 +111,8 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 }
 
                 if (isr & AR_ISR_RXORN) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "receive FIFO overrun interrupt\n");
-                }
-
-                if (!AR_SREV_9100(ah)) {
-                        if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
-                                u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
-                                if (isr5 & AR_ISR_S5_TIM_TIMER)
-                                        *masked |= ATH9K_INT_TIM_TIMER;
-                        }
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "receive FIFO overrun interrupt\n");
                 }
 
                 *masked |= mask2;
@@ -136,17 +125,18 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 u32 s5_s;
 
                 s5_s = REG_READ(ah, AR_ISR_S5_S);
-                if (isr & AR_ISR_GENTMR) {
-                        ah->intr_gen_timer_trigger =
+                ah->intr_gen_timer_trigger =
                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
 
-                        ah->intr_gen_timer_thresh =
-                                MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
+                ah->intr_gen_timer_thresh =
+                        MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
 
-                        if (ah->intr_gen_timer_trigger)
-                                *masked |= ATH9K_INT_GENTIMER;
+                if (ah->intr_gen_timer_trigger)
+                        *masked |= ATH9K_INT_GENTIMER;
 
-                }
+                if ((s5_s & AR_ISR_S5_TIM_TIMER) &&
+                    !(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+                        *masked |= ATH9K_INT_TIM_TIMER;
         }
 
         if (sync_cause) {
@@ -157,25 +147,25 @@ static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
 
                 if (fatal_int) {
                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
-                                ath_print(common, ATH_DBG_ANY,
-                                          "received PCI FATAL interrupt\n");
+                                ath_dbg(common, ATH_DBG_ANY,
+                                        "received PCI FATAL interrupt\n");
                         }
                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
-                                ath_print(common, ATH_DBG_ANY,
-                                          "received PCI PERR interrupt\n");
+                                ath_dbg(common, ATH_DBG_ANY,
+                                        "received PCI PERR interrupt\n");
                         }
                         *masked |= ATH9K_INT_FATAL;
                 }
                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
                         REG_WRITE(ah, AR_RC, 0);
                         *masked |= ATH9K_INT_FATAL;
                 }
                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
                 }
 
                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
@@ -218,77 +208,70 @@ static int ar9002_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                  struct ath_tx_status *ts)
 {
         struct ar5416_desc *ads = AR5416DESC(ds);
+        u32 status;
 
-        if ((ads->ds_txstatus9 & AR_TxDone) == 0)
+        status = ACCESS_ONCE(ads->ds_txstatus9);
+        if ((status & AR_TxDone) == 0)
                 return -EINPROGRESS;
 
-        ts->ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
         ts->ts_tstamp = ads->AR_SendTimestamp;
         ts->ts_status = 0;
         ts->ts_flags = 0;
 
-        if (ads->ds_txstatus1 & AR_FrmXmitOK)
+        if (status & AR_TxOpExceeded)
+                ts->ts_status |= ATH9K_TXERR_XTXOP;
+        ts->tid = MS(status, AR_TxTid);
+        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
+        ts->ts_seqnum = MS(status, AR_SeqNum);
+
+        status = ACCESS_ONCE(ads->ds_txstatus0);
+        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
+        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
+        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
+        if (status & AR_TxBaStatus) {
+                ts->ts_flags |= ATH9K_TX_BA;
+                ts->ba_low = ads->AR_BaBitmapLow;
+                ts->ba_high = ads->AR_BaBitmapHigh;
+        }
+
+        status = ACCESS_ONCE(ads->ds_txstatus1);
+        if (status & AR_FrmXmitOK)
                 ts->ts_status |= ATH9K_TX_ACKED;
-        if (ads->ds_txstatus1 & AR_ExcessiveRetries)
-                ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->ds_txstatus1 & AR_Filtered)
-                ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->ds_txstatus1 & AR_FIFOUnderrun) {
-                ts->ts_status |= ATH9K_TXERR_FIFO;
-                ath9k_hw_updatetxtriglevel(ah, true);
+        else {
+                if (status & AR_ExcessiveRetries)
+                        ts->ts_status |= ATH9K_TXERR_XRETRY;
+                if (status & AR_Filtered)
+                        ts->ts_status |= ATH9K_TXERR_FILT;
+                if (status & AR_FIFOUnderrun) {
+                        ts->ts_status |= ATH9K_TXERR_FIFO;
+                        ath9k_hw_updatetxtriglevel(ah, true);
+                }
         }
-        if (ads->ds_txstatus9 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->ds_txstatus1 & AR_TxTimerExpired)
+        if (status & AR_TxTimerExpired)
                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->ds_txstatus1 & AR_DescCfgErr)
+        if (status & AR_DescCfgErr)
                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
+        if (status & AR_TxDataUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
+        if (status & AR_TxDelimUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->ds_txstatus0 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->AR_BaBitmapLow;
-                ts->ba_high = ads->AR_BaBitmapHigh;
-        }
+        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
+        ts->ts_longretry = MS(status, AR_DataFailCnt);
+        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
-        ts->ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
-        switch (ts->ts_rateindex) {
-        case 0:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
-                break;
-        case 1:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
-                break;
-        case 2:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
-                break;
-        case 3:
-                ts->ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
-                break;
-        }
+        status = ACCESS_ONCE(ads->ds_txstatus5);
+        ts->ts_rssi = MS(status, AR_TxRSSICombined);
+        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
+        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
+        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
-        ts->ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
         ts->evm0 = ads->AR_TxEVM0;
         ts->evm1 = ads->AR_TxEVM1;
         ts->evm2 = ads->AR_TxEVM2;
-        ts->ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
-        ts->tid = MS(ads->ds_txstatus9, AR_TxTid);
-        ts->ts_antenna = 0;
 
         return 0;
 }
@@ -300,7 +283,6 @@ static void ar9002_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
 {
         struct ar5416_desc *ads = AR5416DESC(ds);
 
-        txPower += ah->txpower_indexoffset;
         if (txPower > 63)
                 txPower = 63;
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
index c00cdc67b55b..7d68d61e406b 100644
--- a/drivers/net/wireless/ath/ath9k/ar9002_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -175,13 +175,15 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         int upper, lower, cur_vit_mask;
         int tmp, newVal;
         int i;
-        int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
-                          AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
+        static const int pilot_mask_reg[4] = {
+                AR_PHY_TIMING7, AR_PHY_TIMING8,
+                AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
         };
-        int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
-                         AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
+        static const int chan_mask_reg[4] = {
+                AR_PHY_TIMING9, AR_PHY_TIMING10,
+                AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
         };
-        int inc[4] = { 0, 100, 0, 0 };
+        static const int inc[4] = { 0, 100, 0, 0 };
         struct chan_centers centers;
 
         int8_t mask_m[123];
@@ -201,13 +203,14 @@ static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
 
+                if (AR_NO_SPUR == cur_bb_spur)
+                        break;
+
                 if (is2GHz)
                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
                 else
                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
 
-                if (AR_NO_SPUR == cur_bb_spur)
-                        break;
                 cur_bb_spur = cur_bb_spur - freq;
 
                 if (IS_CHAN_HT40(chan)) {
@@ -473,21 +476,21 @@ static void ar9002_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
         if (IS_CHAN_HT40(ah->curchan))
-                nfarray[3] = sign_extend(nf, 9);
+                nfarray[3] = sign_extend32(nf, 8);
 
         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
         if (IS_CHAN_HT40(ah->curchan))
-                nfarray[4] = sign_extend(nf, 9);
+                nfarray[4] = sign_extend32(nf, 8);
 }
 
 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index a14a5e43cf56..81f9cf294dec 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -34,9 +34,9 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
 
 static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         /* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
-        {0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x00637800, 0x00637800},
-        {0x0000a2e0, 0x0000f800, 0x0000f800, 0x03838000, 0x03838000},
-        {0x0000a2e4, 0x03ff0000, 0x03ff0000, 0x03fc0000, 0x03fc0000},
+        {0x0000a2dc, 0x00033800, 0x00033800, 0x00637800, 0x00637800},
+        {0x0000a2e0, 0x0003c000, 0x0003c000, 0x03838000, 0x03838000},
+        {0x0000a2e4, 0x03fc0000, 0x03fc0000, 0x03fc0000, 0x03fc0000},
         {0x0000a2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
         {0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -56,21 +56,21 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a538, 0x4702244a, 0x4702244a, 0x34000e24, 0x34000e24},
         {0x0000a53c, 0x4b02244c, 0x4b02244c, 0x38001640, 0x38001640},
         {0x0000a540, 0x4e02246c, 0x4e02246c, 0x3c001660, 0x3c001660},
-        {0x0000a544, 0x5302266c, 0x5302266c, 0x3f001861, 0x3f001861},
-        {0x0000a548, 0x5702286c, 0x5702286c, 0x43001a81, 0x43001a81},
-        {0x0000a54c, 0x5c02486b, 0x5c02486b, 0x47001a83, 0x47001a83},
-        {0x0000a550, 0x61024a6c, 0x61024a6c, 0x4a001c84, 0x4a001c84},
-        {0x0000a554, 0x66026a6c, 0x66026a6c, 0x4e001ce3, 0x4e001ce3},
-        {0x0000a558, 0x6b026e6c, 0x6b026e6c, 0x52001ce5, 0x52001ce5},
-        {0x0000a55c, 0x7002708c, 0x7002708c, 0x56001ce9, 0x56001ce9},
-        {0x0000a560, 0x7302b08a, 0x7302b08a, 0x5a001ceb, 0x5a001ceb},
-        {0x0000a564, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a568, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a56c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a570, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a574, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a578, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
-        {0x0000a57c, 0x7702b08c, 0x7702b08c, 0x5d001eec, 0x5d001eec},
+        {0x0000a544, 0x52022470, 0x52022470, 0x3f001861, 0x3f001861},
+        {0x0000a548, 0x55022490, 0x55022490, 0x43001a81, 0x43001a81},
+        {0x0000a54c, 0x59022492, 0x59022492, 0x47001a83, 0x47001a83},
+        {0x0000a550, 0x5d022692, 0x5d022692, 0x4a001c84, 0x4a001c84},
+        {0x0000a554, 0x61022892, 0x61022892, 0x4e001ce3, 0x4e001ce3},
+        {0x0000a558, 0x65024890, 0x65024890, 0x52001ce5, 0x52001ce5},
+        {0x0000a55c, 0x69024892, 0x69024892, 0x56001ce9, 0x56001ce9},
+        {0x0000a560, 0x6e024c92, 0x6e024c92, 0x5a001ceb, 0x5a001ceb},
+        {0x0000a564, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a568, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a56c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a570, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a574, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a578, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
+        {0x0000a57c, 0x74026e92, 0x74026e92, 0x5d001eec, 0x5d001eec},
         {0x0000a580, 0x00800000, 0x00800000, 0x00800000, 0x00800000},
         {0x0000a584, 0x06800003, 0x06800003, 0x04800002, 0x04800002},
         {0x0000a588, 0x0a800020, 0x0a800020, 0x08800004, 0x08800004},
@@ -88,44 +88,44 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
         {0x0000a5b8, 0x4782244a, 0x4782244a, 0x34800e24, 0x34800e24},
         {0x0000a5bc, 0x4b82244c, 0x4b82244c, 0x38801640, 0x38801640},
         {0x0000a5c0, 0x4e82246c, 0x4e82246c, 0x3c801660, 0x3c801660},
-        {0x0000a5c4, 0x5382266c, 0x5382266c, 0x3f801861, 0x3f801861},
-        {0x0000a5c8, 0x5782286c, 0x5782286c, 0x43801a81, 0x43801a81},
-        {0x0000a5cc, 0x5c82486b, 0x5c82486b, 0x47801a83, 0x47801a83},
-        {0x0000a5d0, 0x61824a6c, 0x61824a6c, 0x4a801c84, 0x4a801c84},
-        {0x0000a5d4, 0x66826a6c, 0x66826a6c, 0x4e801ce3, 0x4e801ce3},
-        {0x0000a5d8, 0x6b826e6c, 0x6b826e6c, 0x52801ce5, 0x52801ce5},
-        {0x0000a5dc, 0x7082708c, 0x7082708c, 0x56801ce9, 0x56801ce9},
-        {0x0000a5e0, 0x7382b08a, 0x7382b08a, 0x5a801ceb, 0x5a801ceb},
-        {0x0000a5e4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5e8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5ec, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f0, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f4, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5f8, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
-        {0x0000a5fc, 0x7782b08c, 0x7782b08c, 0x5d801eec, 0x5d801eec},
+        {0x0000a5c4, 0x52822470, 0x52822470, 0x3f801861, 0x3f801861},
+        {0x0000a5c8, 0x55822490, 0x55822490, 0x43801a81, 0x43801a81},
+        {0x0000a5cc, 0x59822492, 0x59822492, 0x47801a83, 0x47801a83},
+        {0x0000a5d0, 0x5d822692, 0x5d822692, 0x4a801c84, 0x4a801c84},
+        {0x0000a5d4, 0x61822892, 0x61822892, 0x4e801ce3, 0x4e801ce3},
+        {0x0000a5d8, 0x65824890, 0x65824890, 0x52801ce5, 0x52801ce5},
+        {0x0000a5dc, 0x69824892, 0x69824892, 0x56801ce9, 0x56801ce9},
+        {0x0000a5e0, 0x6e824c92, 0x6e824c92, 0x5a801ceb, 0x5a801ceb},
+        {0x0000a5e4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5e8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5ec, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f0, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f4, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5f8, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
+        {0x0000a5fc, 0x74826e92, 0x74826e92, 0x5d801eec, 0x5d801eec},
         {0x0000a600, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a604, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a608, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a60c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x0000a610, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x0000a614, 0x01404000, 0x01404000, 0x01404000, 0x01404000},
-        {0x0000a618, 0x01404501, 0x01404501, 0x01404501, 0x01404501},
-        {0x0000a61c, 0x02008802, 0x02008802, 0x02008501, 0x02008501},
-        {0x0000a620, 0x0300cc03, 0x0300cc03, 0x0280ca03, 0x0280ca03},
-        {0x0000a624, 0x0300cc03, 0x0300cc03, 0x03010c04, 0x03010c04},
-        {0x0000a628, 0x0300cc03, 0x0300cc03, 0x04014c04, 0x04014c04},
-        {0x0000a62c, 0x03810c03, 0x03810c03, 0x04015005, 0x04015005},
-        {0x0000a630, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
-        {0x0000a634, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
-        {0x0000a638, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
-        {0x0000a63c, 0x03810e04, 0x03810e04, 0x04015005, 0x04015005},
-        {0x0000b2dc, 0x0380c7fc, 0x0380c7fc, 0x00637800, 0x00637800},
-        {0x0000b2e0, 0x0000f800, 0x0000f800, 0x03838000, 0x03838000},
-        {0x0000b2e4, 0x03ff0000, 0x03ff0000, 0x03fc0000, 0x03fc0000},
+        {0x0000a614, 0x02004000, 0x02004000, 0x01404000, 0x01404000},
+        {0x0000a618, 0x02004801, 0x02004801, 0x01404501, 0x01404501},
+        {0x0000a61c, 0x02808a02, 0x02808a02, 0x02008501, 0x02008501},
+        {0x0000a620, 0x0380ce03, 0x0380ce03, 0x0280ca03, 0x0280ca03},
+        {0x0000a624, 0x04411104, 0x04411104, 0x03010c04, 0x03010c04},
+        {0x0000a628, 0x04411104, 0x04411104, 0x04014c04, 0x04014c04},
+        {0x0000a62c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a630, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a634, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a638, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000a63c, 0x04411104, 0x04411104, 0x04015005, 0x04015005},
+        {0x0000b2dc, 0x00033800, 0x00033800, 0x00637800, 0x00637800},
+        {0x0000b2e0, 0x0003c000, 0x0003c000, 0x03838000, 0x03838000},
+        {0x0000b2e4, 0x03fc0000, 0x03fc0000, 0x03fc0000, 0x03fc0000},
         {0x0000b2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
-        {0x0000c2dc, 0x0380c7fc, 0x0380c7fc, 0x00637800, 0x00637800},
-        {0x0000c2e0, 0x0000f800, 0x0000f800, 0x03838000, 0x03838000},
-        {0x0000c2e4, 0x03ff0000, 0x03ff0000, 0x03fc0000, 0x03fc0000},
+        {0x0000c2dc, 0x00033800, 0x00033800, 0x00637800, 0x00637800},
+        {0x0000c2e0, 0x0003c000, 0x0003c000, 0x03838000, 0x03838000},
+        {0x0000c2e4, 0x03fc0000, 0x03fc0000, 0x03fc0000, 0x03fc0000},
         {0x0000c2e8, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
         {0x00016044, 0x012492d4, 0x012492d4, 0x012492d4, 0x012492d4},
         {0x00016048, 0x62480001, 0x62480001, 0x62480001, 0x62480001},
@@ -638,6 +638,7 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
         {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
         {0x0000a204, 0x000037c0, 0x000037c4, 0x000037c4, 0x000037c0},
         {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+        {0x0000a22c, 0x01026a2f, 0x01026a2f, 0x01026a2f, 0x01026a2f},
         {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
         {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
         {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
@@ -680,7 +681,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000981c, 0x00020028},
         {0x00009834, 0x6400a290},
         {0x00009838, 0x0108ecff},
-        {0x0000983c, 0x14750600},
+        {0x0000983c, 0x0d000600},
         {0x00009880, 0x201fff00},
         {0x00009884, 0x00001042},
         {0x000098a4, 0x00200400},
@@ -722,7 +723,6 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
         {0x0000a220, 0x00000000},
         {0x0000a224, 0x00000000},
         {0x0000a228, 0x10002310},
-        {0x0000a22c, 0x01036a27},
         {0x0000a23c, 0x00000000},
         {0x0000a244, 0x0c000000},
         {0x0000a2a0, 0x00000001},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
index 9e6edffe0bd1..4a4cd88429c0 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c
@@ -18,6 +18,16 @@
 #include "hw-ops.h"
 #include "ar9003_phy.h"
 
+#define MPASS   3
+#define MAX_MEASUREMENT 8
+#define MAX_DIFFERENCE  10
+
+struct coeff {
+        int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
+        int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT][MPASS];
+        int iqc_coeff[2];
+};
+
 enum ar9003_cal_types {
         IQ_MISMATCH_CAL = BIT(0),
         TEMP_COMP_CAL = BIT(1),
@@ -40,8 +50,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                 currCal->calData->calCountMax);
                 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting IQ Mismatch Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting IQ Mismatch Calibration\n");
 
                 /* Kick-off cal */
                 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
@@ -52,8 +62,8 @@ static void ar9003_hw_setup_calibration(struct ath_hw *ah,
                 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
                               AR_PHY_65NM_CH0_THERM_START, 1);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "starting Temperature Compensation Calibration\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "starting Temperature Compensation Calibration\n");
                 break;
         }
 }
@@ -181,11 +191,11 @@ static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
                         REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
                 ah->totalIqCorrMeas[i] +=
                         (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
-                ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                          "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
-                          ah->cal_samples, i, ah->totalPowerMeasI[i],
-                          ah->totalPowerMeasQ[i],
-                          ah->totalIqCorrMeas[i]);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
+                        "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
+                        ah->cal_samples, i, ah->totalPowerMeasI[i],
+                        ah->totalPowerMeasQ[i],
+                        ah->totalIqCorrMeas[i]);
         }
 }
 
@@ -196,7 +206,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
         u32 qCoffDenom, iCoffDenom;
         int32_t qCoff, iCoff;
         int iqCorrNeg, i;
-        const u_int32_t offset_array[3] = {
+        static const u_int32_t offset_array[3] = {
                 AR_PHY_RX_IQCAL_CORR_B0,
                 AR_PHY_RX_IQCAL_CORR_B1,
                 AR_PHY_RX_IQCAL_CORR_B2,
@@ -207,13 +217,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 powerMeasQ = ah->totalPowerMeasQ[i];
                 iqCorrMeas = ah->totalIqCorrMeas[i];
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Starting IQ Cal and Correction for Chain %d\n",
-                          i);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Starting IQ Cal and Correction for Chain %d\n",
+                        i);
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Orignal: Chn %diq_corr_meas = 0x%08x\n",
-                          i, ah->totalIqCorrMeas[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Orignal: Chn %diq_corr_meas = 0x%08x\n",
+                        i, ah->totalIqCorrMeas[i]);
 
                 iqCorrNeg = 0;
 
@@ -222,12 +232,12 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iqCorrNeg = 1;
                 }
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
-                ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
-                          iqCorrNeg);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
+                ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
+                        iqCorrNeg);
 
                 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
                 qCoffDenom = powerMeasQ / 64;
@@ -235,10 +245,10 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
                         iCoff = iqCorrMeas / iCoffDenom;
                         qCoff = powerMeasI / qCoffDenom - 64;
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d iCoff = 0x%08x\n", i, iCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d qCoff = 0x%08x\n", i, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d iCoff = 0x%08x\n", i, iCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d qCoff = 0x%08x\n", i, qCoff);
 
                         /* Force bounds on iCoff */
                         if (iCoff >= 63)
@@ -259,14 +269,13 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         iCoff = iCoff & 0x7f;
                         qCoff = qCoff & 0x7f;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
-                                  i, iCoff, qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) "
-                                  "before update = 0x%x\n",
-                                  offset_array[i],
-                                  REG_READ(ah, offset_array[i]));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Chn %d : iCoff = 0x%x  qCoff = 0x%x\n",
+                                i, iCoff, qCoff);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) before update = 0x%x\n",
+                                offset_array[i],
+                                REG_READ(ah, offset_array[i]));
 
                         REG_RMW_FIELD(ah, offset_array[i],
                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
@@ -274,33 +283,29 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
                         REG_RMW_FIELD(ah, offset_array[i],
                                       AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
                                       qCoff);
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) QI COFF "
-                                  "(bitfields 0x%08x) after update = 0x%x\n",
-                                  offset_array[i],
-                                  AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
-                                  REG_READ(ah, offset_array[i]));
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Register offset (0x%04x) QQ COFF "
-                                  "(bitfields 0x%08x) after update = 0x%x\n",
-                                  offset_array[i],
-                                  AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
-                                  REG_READ(ah, offset_array[i]));
-
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ Cal and Correction done for Chain %d\n",
-                                  i);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
+                                offset_array[i],
+                                AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
+                                REG_READ(ah, offset_array[i]));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
+                                offset_array[i],
+                                AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
+                                REG_READ(ah, offset_array[i]));
+
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "IQ Cal and Correction done for Chain %d\n", i);
                 }
         }
 
         REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
                     AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "IQ Cal and Correction (offset 0x%04x) enabled "
-                  "(bit position 0x%08x). New Value 0x%08x\n",
-                  (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
-                  AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
-                  REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
+                (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
+                AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
+                REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
 }
 
 static const struct ath9k_percal_data iq_cal_single_sample = {
@@ -340,7 +345,7 @@ static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
         f2 = (f1 * f1 + f3 * f3) / result_shift;
 
         if (!f2) {
-                ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
                 return false;
         }
 
@@ -461,11 +466,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
             (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0:\na0_d0=%d\n"
-                          "a0_d1=%d\na2_d0=%d\na1_d1=%d\n",
-                          i2_p_q2_a0_d0, i2_p_q2_a0_d1,
-                          i2_p_q2_a1_d0, i2_p_q2_a1_d1);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0:\n"
+                        "a0_d0=%d\n"
+                        "a0_d1=%d\n"
+                        "a2_d0=%d\n"
+                        "a1_d1=%d\n",
+                        i2_p_q2_a0_d0, i2_p_q2_a0_d1,
+                        i2_p_q2_a1_d0, i2_p_q2_a1_d1);
                 return false;
         }
 
@@ -498,9 +506,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
 
         if ((mag1 == 0) || (mag2 == 0)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag1=%d, mag2=%d\n",
-                          mag1, mag2);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag1=%d, mag2=%d\n",
+                        mag1, mag2);
                 return false;
         }
 
@@ -517,8 +525,8 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
                              mag_a0_d0, phs_a0_d0,
                              mag_a1_d0,
                              phs_a1_d0, solved_eq)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Call to ar9003_hw_solve_iq_cal() failed.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Call to ar9003_hw_solve_iq_cal() failed.\n");
                 return false;
         }
 
@@ -527,14 +535,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         mag_rx = solved_eq[2];
         phs_rx = solved_eq[3];
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "chain %d: mag mismatch=%d phase mismatch=%d\n",
-                  chain_idx, mag_tx/res_scale, phs_tx/res_scale);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "chain %d: mag mismatch=%d phase mismatch=%d\n",
+                chain_idx, mag_tx/res_scale, phs_tx/res_scale);
 
         if (res_scale == mag_tx) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag_tx=%d, res_scale=%d\n",
-                          mag_tx, res_scale);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag_tx=%d, res_scale=%d\n",
+                        mag_tx, res_scale);
                 return false;
         }
 
@@ -545,9 +553,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         q_q_coff = (mag_corr_tx * 128 / res_scale);
         q_i_coff = (phs_corr_tx * 256 / res_scale);
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "tx chain %d: mag corr=%d  phase corr=%d\n",
-                  chain_idx, q_q_coff, q_i_coff);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "tx chain %d: mag corr=%d  phase corr=%d\n",
+                chain_idx, q_q_coff, q_i_coff);
 
         if (q_i_coff < -63)
                 q_i_coff = -63;
@@ -560,14 +568,14 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "tx chain %d: iq corr coeff=%x\n",
-                  chain_idx, iqc_coeff[0]);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "tx chain %d: iq corr coeff=%x\n",
+                chain_idx, iqc_coeff[0]);
 
         if (-mag_rx == res_scale) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Divide by 0: mag_rx=%d, res_scale=%d\n",
-                          mag_rx, res_scale);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Divide by 0: mag_rx=%d, res_scale=%d\n",
+                        mag_rx, res_scale);
                 return false;
         }
 
@@ -578,9 +586,9 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
         q_q_coff = (mag_corr_rx * 128 / res_scale);
         q_i_coff = (phs_corr_rx * 256 / res_scale);
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "rx chain %d: mag corr=%d  phase corr=%d\n",
-                  chain_idx, q_q_coff, q_i_coff);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "rx chain %d: mag corr=%d  phase corr=%d\n",
+                chain_idx, q_q_coff, q_i_coff);
 
         if (q_i_coff < -63)
                 q_i_coff = -63;
@@ -593,140 +601,367 @@ static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
 
         iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "rx chain %d: iq corr coeff=%x\n",
-                  chain_idx, iqc_coeff[1]);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "rx chain %d: iq corr coeff=%x\n",
+                chain_idx, iqc_coeff[1]);
+
+        return true;
+}
+
+static bool ar9003_hw_compute_closest_pass_and_avg(int *mp_coeff, int *mp_avg)
+{
+        int diff[MPASS];
+
+        diff[0] = abs(mp_coeff[0] - mp_coeff[1]);
+        diff[1] = abs(mp_coeff[1] - mp_coeff[2]);
+        diff[2] = abs(mp_coeff[2] - mp_coeff[0]);
+
+        if (diff[0] > MAX_DIFFERENCE &&
+            diff[1] > MAX_DIFFERENCE &&
+            diff[2] > MAX_DIFFERENCE)
+                return false;
+
+        if (diff[0] <= diff[1] && diff[0] <= diff[2])
+                *mp_avg = (mp_coeff[0] + mp_coeff[1]) / 2;
+        else if (diff[1] <= diff[2])
+                *mp_avg = (mp_coeff[1] + mp_coeff[2]) / 2;
+        else
+                *mp_avg = (mp_coeff[2] + mp_coeff[0]) / 2;
 
         return true;
 }
 
+static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
+                                                 u8 num_chains,
+                                                 struct coeff *coeff)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        int i, im, nmeasurement;
+        int magnitude, phase;
+        u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
+
+        memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
+        for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
+                tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
+                if (!AR_SREV_9485(ah)) {
+                        tx_corr_coeff[i * 2][1] =
+                        tx_corr_coeff[(i * 2) + 1][1] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
+
+                        tx_corr_coeff[i * 2][2] =
+                        tx_corr_coeff[(i * 2) + 1][2] =
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
+                }
+        }
+
+        /* Load the average of 2 passes */
+        for (i = 0; i < num_chains; i++) {
+                if (AR_SREV_9485(ah))
+                        nmeasurement = REG_READ_FIELD(ah,
+                                        AR_PHY_TX_IQCAL_STATUS_B0_9485,
+                                        AR_PHY_CALIBRATED_GAINS_0);
+                else
+                        nmeasurement = REG_READ_FIELD(ah,
+                                        AR_PHY_TX_IQCAL_STATUS_B0,
+                                        AR_PHY_CALIBRATED_GAINS_0);
+
+                if (nmeasurement > MAX_MEASUREMENT)
+                        nmeasurement = MAX_MEASUREMENT;
+
+                for (im = 0; im < nmeasurement; im++) {
+                        /*
+                         * Determine which 2 passes are closest and compute avg
+                         * magnitude
+                         */
+                        if (!ar9003_hw_compute_closest_pass_and_avg(coeff->mag_coeff[i][im],
+                                                                    &magnitude))
+                                goto disable_txiqcal;
+
+                        /*
+                         * Determine which 2 passes are closest and compute avg
+                         * phase
+                         */
+                        if (!ar9003_hw_compute_closest_pass_and_avg(coeff->phs_coeff[i][im],
+                                                                    &phase))
+                                goto disable_txiqcal;
+
+                        coeff->iqc_coeff[0] = (magnitude & 0x7f) |
+                                              ((phase & 0x7f) << 7);
+
+                        if ((im % 2) == 0)
+                                REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
+                                        coeff->iqc_coeff[0]);
+                        else
+                                REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
+                                        AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
+                                        coeff->iqc_coeff[0]);
+                }
+        }
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
+                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
+        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
+                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
+
+        return;
+
+disable_txiqcal:
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
+                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x0);
+        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
+                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x0);
+
+        ath_dbg(common, ATH_DBG_CALIBRATE, "TX IQ Cal disabled\n");
+}
+
 static void ar9003_hw_tx_iq_cal(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
-        const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
+        static const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
                 AR_PHY_TX_IQCAL_STATUS_B0,
                 AR_PHY_TX_IQCAL_STATUS_B1,
                 AR_PHY_TX_IQCAL_STATUS_B2,
         };
-        const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = {
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B0,
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B1,
-                AR_PHY_TX_IQCAL_CORR_COEFF_01_B2,
-        };
-        const u32 rx_corr[AR9300_MAX_CHAINS] = {
-                AR_PHY_RX_IQCAL_CORR_B0,
-                AR_PHY_RX_IQCAL_CORR_B1,
-                AR_PHY_RX_IQCAL_CORR_B2,
-        };
-        const u_int32_t chan_info_tab[] = {
+        static const u32 chan_info_tab[] = {
                 AR_PHY_CHAN_INFO_TAB_0,
                 AR_PHY_CHAN_INFO_TAB_1,
                 AR_PHY_CHAN_INFO_TAB_2,
         };
+        struct coeff coeff;
         s32 iq_res[6];
-        s32 iqc_coeff[2];
-        s32 i, j;
-        u32 num_chains = 0;
+        s32 i, j, ip, im, nmeasurement;
+        u8 nchains = get_streams(common->tx_chainmask);
+
+        for (ip = 0; ip < MPASS; ip++) {
+                REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
+                              AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
+                              DELPT);
+                REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
+                              AR_PHY_TX_IQCAL_START_DO_CAL,
+                              AR_PHY_TX_IQCAL_START_DO_CAL);
+
+                if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
+                                   AR_PHY_TX_IQCAL_START_DO_CAL,
+                                   0, AH_WAIT_TIMEOUT)) {
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Tx IQ Cal not complete.\n");
+                        goto TX_IQ_CAL_FAILED;
+                }
 
-        for (i = 0; i < AR9300_MAX_CHAINS; i++) {
-                if (ah->txchainmask & (1 << i))
-                        num_chains++;
-        }
+                nmeasurement = REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_STATUS_B0,
+                                              AR_PHY_CALIBRATED_GAINS_0);
+                        if (nmeasurement > MAX_MEASUREMENT)
+                                nmeasurement = MAX_MEASUREMENT;
+
+                for (i = 0; i < nchains; i++) {
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "Doing Tx IQ Cal for chain %d.\n", i);
+                        for (im = 0; im < nmeasurement; im++) {
+                                if (REG_READ(ah, txiqcal_status[i]) &
+                                             AR_PHY_TX_IQCAL_STATUS_FAILED) {
+                                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                                "Tx IQ Cal failed for chain %d.\n", i);
+                                        goto TX_IQ_CAL_FAILED;
+                                }
 
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
-                      AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
-                      DELPT);
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
-                      AR_PHY_TX_IQCAL_START_DO_CAL,
-                      AR_PHY_TX_IQCAL_START_DO_CAL);
+                                for (j = 0; j < 3; j++) {
+                                        u8 idx = 2 * j,
+                                           offset = 4 * (3 * im + j);
 
-        if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
-                           AR_PHY_TX_IQCAL_START_DO_CAL,
-                           0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Tx IQ Cal not complete.\n");
-                goto TX_IQ_CAL_FAILED;
-        }
+                                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
+                                                      AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                      0);
 
-        for (i = 0; i < num_chains; i++) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Doing Tx IQ Cal for chain %d.\n", i);
+                                        /* 32 bits */
+                                        iq_res[idx] = REG_READ(ah,
+                                                        chan_info_tab[i] +
+                                                        offset);
 
-                if (REG_READ(ah, txiqcal_status[i]) &
-                             AR_PHY_TX_IQCAL_STATUS_FAILED) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Tx IQ Cal failed for chain %d.\n", i);
-                        goto TX_IQ_CAL_FAILED;
-                }
+                                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
+                                                      AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                      1);
 
-                for (j = 0; j < 3; j++) {
-                        u_int8_t idx = 2 * j,
-                        offset = 4 * j;
+                                        /* 16 bits */
+                                        iq_res[idx+1] = 0xffff & REG_READ(ah,
+                                                                chan_info_tab[i] +
+                                                                offset);
 
-                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
-                                      AR_PHY_CHAN_INFO_TAB_S2_READ, 0);
-
-                        /* 32 bits */
-                        iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset);
+                                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                                "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
+                                                idx, iq_res[idx], idx+1, iq_res[idx+1]);
+                                }
 
-                        REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
-                                      AR_PHY_CHAN_INFO_TAB_S2_READ, 1);
+                                if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
+                                                            coeff.iqc_coeff)) {
+                                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                                "Failed in calculation of IQ correction.\n");
+                                        goto TX_IQ_CAL_FAILED;
+                                }
+                                coeff.mag_coeff[i][im][ip] =
+                                                coeff.iqc_coeff[0] & 0x7f;
+                                coeff.phs_coeff[i][im][ip] =
+                                                (coeff.iqc_coeff[0] >> 7) & 0x7f;
 
-                        /* 16 bits */
-                        iq_res[idx+1] = 0xffff & REG_READ(ah,
-                                                          chan_info_tab[i] +
-                                                          offset);
+                                if (coeff.mag_coeff[i][im][ip] > 63)
+                                        coeff.mag_coeff[i][im][ip] -= 128;
+                                if (coeff.phs_coeff[i][im][ip] > 63)
+                                        coeff.phs_coeff[i][im][ip] -= 128;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n",
-                                  idx, iq_res[idx], idx+1, iq_res[idx+1]);
-                }
-
-                if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "Failed in calculation of IQ correction.\n");
-                        goto TX_IQ_CAL_FAILED;
+                        }
                 }
-
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n",
-                          iqc_coeff[0], iqc_coeff[1]);
-
-                REG_RMW_FIELD(ah, tx_corr_coeff[i],
-                              AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
-                              iqc_coeff[0]);
-                REG_RMW_FIELD(ah, rx_corr[i],
-                              AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF,
-                              iqc_coeff[1] >> 7);
-                REG_RMW_FIELD(ah, rx_corr[i],
-                              AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF,
-                              iqc_coeff[1]);
         }
 
-        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
-                      AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
-        REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
-                      AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
+        ar9003_hw_tx_iqcal_load_avg_2_passes(ah, nchains, &coeff);
 
         return;
 
 TX_IQ_CAL_FAILED:
-        ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+}
+
+static void ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
+{
+        u8 tx_gain_forced;
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1_9485,
+                      AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, DELPT);
+        tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
+                                        AR_PHY_TXGAIN_FORCE);
+        if (tx_gain_forced)
+                REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
+                              AR_PHY_TXGAIN_FORCE, 0);
+
+        REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START_9485,
+                      AR_PHY_TX_IQCAL_START_DO_CAL_9485, 1);
 }
 
+static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
+                AR_PHY_TX_IQCAL_STATUS_B0_9485,
+                AR_PHY_TX_IQCAL_STATUS_B1,
+                AR_PHY_TX_IQCAL_STATUS_B2,
+        };
+        const u_int32_t chan_info_tab[] = {
+                AR_PHY_CHAN_INFO_TAB_0,
+                AR_PHY_CHAN_INFO_TAB_1,
+                AR_PHY_CHAN_INFO_TAB_2,
+        };
+        struct coeff coeff;
+        s32 iq_res[6];
+        u8 num_chains = 0;
+        int i, ip, im, j;
+        int nmeasurement;
+
+        for (i = 0; i < AR9300_MAX_CHAINS; i++) {
+                if (ah->txchainmask & (1 << i))
+                        num_chains++;
+        }
+
+        for (ip = 0; ip < MPASS; ip++) {
+                for (i = 0; i < num_chains; i++) {
+                        nmeasurement = REG_READ_FIELD(ah,
+                                        AR_PHY_TX_IQCAL_STATUS_B0_9485,
+                                        AR_PHY_CALIBRATED_GAINS_0);
+                        if (nmeasurement > MAX_MEASUREMENT)
+                                nmeasurement = MAX_MEASUREMENT;
+
+                        for (im = 0; im < nmeasurement; im++) {
+                                ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "Doing Tx IQ Cal for chain %d.\n", i);
+
+                                if (REG_READ(ah, txiqcal_status[i]) &
+                                    AR_PHY_TX_IQCAL_STATUS_FAILED) {
+                                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                        "Tx IQ Cal failed for chain %d.\n", i);
+                                        goto tx_iqcal_fail;
+                                }
+
+                                for (j = 0; j < 3; j++) {
+                                        u32 idx = 2 * j, offset = 4 * (3 * im + j);
+
+                                        REG_RMW_FIELD(ah,
+                                                AR_PHY_CHAN_INFO_MEMORY,
+                                                AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                0);
+
+                                        /* 32 bits */
+                                        iq_res[idx] = REG_READ(ah,
+                                                        chan_info_tab[i] +
+                                                        offset);
+
+                                        REG_RMW_FIELD(ah,
+                                                AR_PHY_CHAN_INFO_MEMORY,
+                                                AR_PHY_CHAN_INFO_TAB_S2_READ,
+                                                1);
+
+                                        /* 16 bits */
+                                        iq_res[idx + 1] = 0xffff & REG_READ(ah,
+                                                          chan_info_tab[i] + offset);
+
+                                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                                "IQ RES[%d]=0x%x"
+                                                "IQ_RES[%d]=0x%x\n",
+                                                idx, iq_res[idx], idx + 1,
+                                                iq_res[idx + 1]);
+                                }
+
+                                if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
+                                                            coeff.iqc_coeff)) {
+                                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                         "Failed in calculation of IQ correction.\n");
+                                        goto tx_iqcal_fail;
+                                }
+
+                                coeff.mag_coeff[i][im][ip] =
+                                                coeff.iqc_coeff[0] & 0x7f;
+                                coeff.phs_coeff[i][im][ip] =
+                                                (coeff.iqc_coeff[0] >> 7) & 0x7f;
+
+                                if (coeff.mag_coeff[i][im][ip] > 63)
+                                        coeff.mag_coeff[i][im][ip] -= 128;
+                                if (coeff.phs_coeff[i][im][ip] > 63)
+                                        coeff.phs_coeff[i][im][ip] -= 128;
+                        }
+                }
+        }
+        ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
+
+        return;
+
+tx_iqcal_fail:
+        ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
+        return;
+}
 static bool ar9003_hw_init_cal(struct ath_hw *ah,
                                struct ath9k_channel *chan)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        int val;
 
-        /*
-         * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before
-         * running AGC/TxIQ cals
-         */
-        ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
+        val = REG_READ(ah, AR_ENT_OTP);
+        ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
+
+        if (AR_SREV_9485(ah))
+                ar9003_hw_set_chain_masks(ah, 0x1, 0x1);
+        else if (val & AR_ENT_OTP_CHAIN2_DISABLE)
+                ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
+        else
+                /*
+                 * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain
+                 * mode before running AGC/TxIQ cals
+                 */
+                ar9003_hw_set_chain_masks(ah, 0x7, 0x7);
 
         /* Do Tx IQ Calibration */
-        ar9003_hw_tx_iq_cal(ah);
+        if (AR_SREV_9485(ah))
+                ar9003_hw_tx_iq_cal_run(ah);
+        else
+                ar9003_hw_tx_iq_cal(ah);
+
         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
         udelay(5);
         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
@@ -739,12 +974,14 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
         /* Poll for offset calibration complete */
         if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
                            0, AH_WAIT_TIMEOUT)) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "offset calibration failed to "
-                          "complete in 1ms; noisy environment?\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "offset calibration failed to complete in 1ms; noisy environment?\n");
                 return false;
         }
 
+        if (AR_SREV_9485(ah))
+                ar9003_hw_tx_iq_cal_post_proc(ah);
+
         /* Revert chainmasks to their original values before NF cal */
         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 
@@ -757,15 +994,15 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah,
         if (ah->supp_cals & IQ_MISMATCH_CAL) {
                 INIT_CAL(&ah->iq_caldata);
                 INSERT_CAL(ah, &ah->iq_caldata);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling IQ Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling IQ Calibration.\n");
         }
 
         if (ah->supp_cals & TEMP_COMP_CAL) {
                 INIT_CAL(&ah->tempCompCalData);
                 INSERT_CAL(ah, &ah->tempCompCalData);
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "enabling Temperature Compensation Calibration.\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "enabling Temperature Compensation Calibration.\n");
         }
 
         /* Initialize current pointer to first element in list */
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
index a7b82f0085d2..4819747fa4c3 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
@@ -22,12 +22,14 @@
 #define COMP_CKSUM_LEN 2
 
 #define AR_CH0_TOP (0x00016288)
-#define AR_CH0_TOP_XPABIASLVL (0x3)
+#define AR_CH0_TOP_XPABIASLVL (0x300)
 #define AR_CH0_TOP_XPABIASLVL_S (8)
 
 #define AR_CH0_THERM (0x00016290)
-#define AR_CH0_THERM_SPARE (0x3f)
-#define AR_CH0_THERM_SPARE_S (0)
+#define AR_CH0_THERM_XPABIASLVL_MSB 0x3
+#define AR_CH0_THERM_XPABIASLVL_MSB_S 0
+#define AR_CH0_THERM_XPASHORT2GND 0x4
+#define AR_CH0_THERM_XPASHORT2GND_S 2
 
 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
 #define AR_SWITCH_TABLE_COM_ALL_S (0)
@@ -57,6 +59,12 @@
 
 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
 
+#define EEPROM_DATA_LEN_9485    1088
+
+static int ar9003_hw_power_interpolate(int32_t x,
+                                       int32_t *px, int32_t *py, u_int16_t np);
+
+
 static const struct ar9300_eeprom ar9300_default = {
         .eepromVersion = 2,
         .templateVersion = 2,
@@ -67,7 +75,7 @@ static const struct ar9300_eeprom ar9300_default = {
                 .regDmn = { LE16(0), LE16(0x1f) },
                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
                 .opCapFlags = {
-                        .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
                         .eepMisc = 0,
                 },
                 .rfSilent = 0,
@@ -146,13 +154,16 @@ static const struct ar9300_eeprom ar9300_default = {
                 .txEndToRxOn = 0x2,
                 .txFrameToXpaOn = 0xe,
                 .thresh62 = 28,
-                .papdRateMaskHt20 = LE32(0x80c080),
-                .papdRateMaskHt40 = LE32(0x80c080),
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
                 .futureModal = {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                 },
          },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
         .calFreqPier2G = {
                 FREQ2FBIN(2412, 1),
                 FREQ2FBIN(2437, 1),
@@ -287,8 +298,7 @@ static const struct ar9300_eeprom ar9300_default = {
                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
-                        /* Data[11].ctlEdges[3].bChannel */
-                        FREQ2FBIN(2462, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
                 }
          },
         .ctlPowerData_2G = {
@@ -346,13 +356,20 @@ static const struct ar9300_eeprom ar9300_default = {
                 .txEndToRxOn = 0x2,
                 .txFrameToXpaOn = 0xe,
                 .thresh62 = 28,
-                .papdRateMaskHt20 = LE32(0xf0e0e0),
-                .papdRateMaskHt40 = LE32(0xf0e0e0),
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
                 .futureModal = {
-                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-                        0, 0, 0, 0, 0, 0, 0, 0
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                 },
          },
+        .base_ext2 = {
+                .tempSlopeLow = 0,
+                .tempSlopeHigh = 0,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+        },
         .calFreqPier5G = {
                 FREQ2FBIN(5180, 0),
                 FREQ2FBIN(5220, 0),
@@ -626,9 +643,2341 @@ static const struct ar9300_eeprom ar9300_default = {
          }
 };
 
+static const struct ar9300_eeprom ar9300_x113 = {
+        .eepromVersion = 2,
+        .templateVersion = 6,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"x113-023-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                 /*
+                  * bit0 - enable tx temp comp - disabled
+                  * bit1 - enable tx volt comp - disabled
+                  * bit2 - enable fastClock - enabled
+                  * bit3 - enable doubling - enabled
+                  * bit4 - enable internal regulator - disabled
+                  * bit5 - enable pa predistortion - disabled
+                  */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x21,
+                .swreg = 0,
+         },
+        .modalHeader2G = {
+        /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+         .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+         },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+         },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTargetPowerCck = {
+                 /* 1L-5L,5S,11L,11S */
+                 { {34, 34, 34, 34} },
+                 { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                 /* 6-24,36,48,54 */
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+         },
+        .ctlPowerData_2G = {
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+         },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x11111),
+                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 68,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+        .base_ext2 = {
+                .tempSlopeLow = 72,
+                .tempSlopeHigh = 105,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+         },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5190, 0),
+                FREQ2FBIN(5230, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5410, 0),
+                FREQ2FBIN(5510, 0),
+                FREQ2FBIN(5670, 0),
+                FREQ2FBIN(5755, 0),
+                FREQ2FBIN(5825, 0)
+         },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+                { {42, 40, 40, 34} },
+         },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
+                { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
+                { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
+         },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
+                { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
+                { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
+         },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+         },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+         }
+};
+
+
+static const struct ar9300_eeprom ar9300_h112 = {
+        .eepromVersion = 2,
+        .templateVersion = 3,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"h112-241-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                /*
+                 * bit0 - enable tx temp comp - disabled
+                 * bit1 - enable tx volt comp - disabled
+                 * bit2 - enable fastClock - enabled
+                 * bit3 - enable doubling - enabled
+                 * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
+                 */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x10,
+                .swreg = 0,
+        },
+        .modalHeader2G = {
+                /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x80c080),
+                .papdRateMaskHt40 = LE32(0x80c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+        },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2484, 1),
+        },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTargetPowerCck = {
+                /* 1L-5L,5S,11L,11S */
+                { {34, 34, 34, 34} },
+                { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                /* 6-24,36,48,54 */
+                { {34, 34, 32, 32} },
+                { {34, 34, 32, 32} },
+                { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+        },
+        .ctlPowerData_2G = {
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+        },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+                /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0, 0, 0},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0, 0, 0},
+                .tempSlope = 45,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext2 = {
+                .tempSlopeLow = 40,
+                .tempSlopeHigh = 50,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+        },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calPierData5G = {
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+        },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
+        },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
+        },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+        },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+        }
+};
+
+
+static const struct ar9300_eeprom ar9300_x112 = {
+        .eepromVersion = 2,
+        .templateVersion = 5,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"x112-041-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                /*
+                 * bit0 - enable tx temp comp - disabled
+                 * bit1 - enable tx volt comp - disabled
+                 * bit2 - enable fastclock - enabled
+                 * bit3 - enable doubling - enabled
+                 * bit4 - enable internal regulator - disabled
+                 * bit5 - enable pa predistortion - disabled
+                 */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x0,
+                .swreg = 0,
+        },
+        .modalHeader2G = {
+                /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x22222),
+
+                /*
+                 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+                /*
+                 * xatten1DB[AR9300_max_chains];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0x1b, 0x1b, 0x1b},
+
+                /*
+                 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x15, 0x15, 0x15},
+                .tempSlope = 50,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80c080),
+                .papdRateMaskHt40 = LE32(0x0080c080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+        },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+        },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+        },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+        },
+        .calTargetPowerCck = {
+                /* 1L-5L,5S,11L,11s */
+                { {38, 38, 38, 38} },
+                { {38, 38, 38, 38} },
+        },
+        .calTargetPower2G = {
+                /* 6-24,36,48,54 */
+                { {38, 38, 36, 34} },
+                { {38, 38, 36, 34} },
+                { {38, 38, 34, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
+                { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
+                { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
+        },
+        .calTargetPower2GHT40 = {
+                { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
+                { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
+                { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
+                }
+        },
+        .ctlPowerData_2G = {
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+        },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x22222),
+                /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x0), LE16(0x0), LE16(0x0),
+                },
+                /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0x13, 0x19, 0x17},
+
+                /*
+                 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x19, 0x19, 0x19},
+                .tempSlope = 70,
+                .voltSlope = 15,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshch check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+        },
+        .base_ext2 = {
+                .tempSlopeLow = 72,
+                .tempSlopeHigh = 105,
+                .xatten1DBLow = {0x10, 0x14, 0x10},
+                .xatten1MarginLow = {0x19, 0x19 , 0x19},
+                .xatten1DBHigh = {0x1d, 0x20, 0x24},
+                .xatten1MarginHigh = {0x10, 0x10, 0x10}
+        },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+                {
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                        {0, 0, 0, 0, 0},
+                },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5725, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {32, 32, 28, 26} },
+                { {32, 32, 28, 26} },
+                { {32, 32, 28, 26} },
+                { {32, 32, 26, 24} },
+                { {32, 32, 26, 24} },
+                { {32, 32, 24, 22} },
+                { {30, 30, 24, 22} },
+                { {30, 30, 24, 22} },
+        },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
+                { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
+                { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
+        },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
+                { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
+                { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
+                { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+                { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
+        },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctledges[6].bchannel */ 0xFF,
+                        /* Data[3].ctledges[7].bchannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctledges[4].bchannel */ 0xFF,
+                        /* Data[4].ctledges[5].bchannel */ 0xFF,
+                        /* Data[4].ctledges[6].bchannel */ 0xFF,
+                        /* Data[4].ctledges[7].bchannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctledges[6].bchannel */ 0xFF,
+                        /* Data[5].ctledges[7].bchannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
+                }
+        },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+        }
+};
+
+static const struct ar9300_eeprom ar9300_h116 = {
+        .eepromVersion = 2,
+        .templateVersion = 4,
+        .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
+        .custData = {"h116-041-f0000"},
+        .baseEepHeader = {
+                .regDmn = { LE16(0), LE16(0x1f) },
+                .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
+                .opCapFlags = {
+                        .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
+                        .eepMisc = 0,
+                },
+                .rfSilent = 0,
+                .blueToothOptions = 0,
+                .deviceCap = 0,
+                .deviceType = 5, /* takes lower byte in eeprom location */
+                .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
+                .params_for_tuning_caps = {0, 0},
+                .featureEnable = 0x0d,
+                 /*
+                  * bit0 - enable tx temp comp - disabled
+                  * bit1 - enable tx volt comp - disabled
+                  * bit2 - enable fastClock - enabled
+                  * bit3 - enable doubling - enabled
+                  * bit4 - enable internal regulator - disabled
+                  * bit5 - enable pa predistortion - disabled
+                  */
+                .miscConfiguration = 0, /* bit0 - turn down drivestrength */
+                .eepromWriteEnableGpio = 6,
+                .wlanDisableGpio = 0,
+                .wlanLedGpio = 8,
+                .rxBandSelectGpio = 0xff,
+                .txrxgain = 0x10,
+                .swreg = 0,
+         },
+        .modalHeader2G = {
+        /* ar9300_modal_eep_header  2g */
+                /* 4 idle,t1,t2,b(4 bits per setting) */
+                .antCtrlCommon = LE32(0x110),
+                /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+
+                /*
+                 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
+                 * rx1, rx12, b (2 bits each)
+                 */
+                .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
+
+                /*
+                 * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
+                 * for ar9280 (0xa20c/b20c 5:0)
+                 */
+                .xatten1DB = {0x1f, 0x1f, 0x1f},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for ar9280 (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x12, 0x12, 0x12},
+                .tempSlope = 25,
+                .voltSlope = 0,
+
+                /*
+                 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
+                 * channels in usual fbin coding format
+                 */
+                .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
+
+                /*
+                 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
+                 * if the register is per chain
+                 */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {1, 1, 1},/* 3 chain */
+                .db_stage2 = {1, 1, 1}, /* 3 chain  */
+                .db_stage3 = {0, 0, 0},
+                .db_stage4 = {0, 0, 0},
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2c,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0c80C080),
+                .papdRateMaskHt40 = LE32(0x0080C080),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+         .base_ext1 = {
+                .ant_div_control = 0,
+                .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
+         },
+        .calFreqPier2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        /* ar9300_cal_data_per_freq_op_loop 2g */
+        .calPierData2G = {
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+                { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
+         },
+        .calTarget_freqbin_Cck = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2472, 1),
+         },
+        .calTarget_freqbin_2G = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT20 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTarget_freqbin_2GHT40 = {
+                FREQ2FBIN(2412, 1),
+                FREQ2FBIN(2437, 1),
+                FREQ2FBIN(2472, 1)
+         },
+        .calTargetPowerCck = {
+                 /* 1L-5L,5S,11L,11S */
+                 { {34, 34, 34, 34} },
+                 { {34, 34, 34, 34} },
+        },
+        .calTargetPower2G = {
+                 /* 6-24,36,48,54 */
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+                 { {34, 34, 32, 32} },
+        },
+        .calTargetPower2GHT20 = {
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+                { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
+        },
+        .calTargetPower2GHT40 = {
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+                { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
+        },
+        .ctlIndex_2G =  {
+                0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
+                0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
+        },
+        .ctl_freqbin_2G = {
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2457, 1),
+                        FREQ2FBIN(2462, 1)
+                },
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+
+                {
+                        FREQ2FBIN(2412, 1),
+                        FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2462, 1),
+                        0xFF,
+                },
+                {
+                        FREQ2FBIN(2422, 1),
+                        FREQ2FBIN(2427, 1),
+                        FREQ2FBIN(2447, 1),
+                        FREQ2FBIN(2452, 1)
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        FREQ2FBIN(2472, 1),
+                        0,
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                },
+
+                {
+                        /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
+                        /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
+                        /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
+                        0
+                },
+
+                {
+                        /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
+                        /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
+                        /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
+                        /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
+                }
+         },
+        .ctlPowerData_2G = {
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
+
+                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
+         },
+        .modalHeader5G = {
+                /* 4 idle,t1,t2,b (4 bits per setting) */
+                .antCtrlCommon = LE32(0x220),
+                /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
+                .antCtrlCommon2 = LE32(0x44444),
+                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
+                .antCtrlChain = {
+                        LE16(0x150), LE16(0x150), LE16(0x150),
+                },
+                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
+                .xatten1DB = {0x19, 0x19, 0x19},
+
+                /*
+                 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
+                 * for merlin (0xa20c/b20c 16:12
+                 */
+                .xatten1Margin = {0x14, 0x14, 0x14},
+                .tempSlope = 70,
+                .voltSlope = 0,
+                /* spurChans spur channels in usual fbin coding format */
+                .spurChans = {0, 0, 0, 0, 0},
+                /* noiseFloorThreshCh Check if the register is per chain */
+                .noiseFloorThreshCh = {-1, 0, 0},
+                .ob = {3, 3, 3}, /* 3 chain */
+                .db_stage2 = {3, 3, 3}, /* 3 chain */
+                .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
+                .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
+                .xpaBiasLvl = 0,
+                .txFrameToDataStart = 0x0e,
+                .txFrameToPaOn = 0x0e,
+                .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
+                .antennaGain = 0,
+                .switchSettling = 0x2d,
+                .adcDesiredSize = -30,
+                .txEndToXpaOff = 0,
+                .txEndToRxOn = 0x2,
+                .txFrameToXpaOn = 0xe,
+                .thresh62 = 28,
+                .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+                .papdRateMaskHt40 = LE32(0x6cf0e0e0),
+                .futureModal = {
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                },
+         },
+        .base_ext2 = {
+                .tempSlopeLow = 35,
+                .tempSlopeHigh = 50,
+                .xatten1DBLow = {0, 0, 0},
+                .xatten1MarginLow = {0, 0, 0},
+                .xatten1DBHigh = {0, 0, 0},
+                .xatten1MarginHigh = {0, 0, 0}
+         },
+        .calFreqPier5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5220, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5785, 0)
+        },
+        .calPierData5G = {
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+                        {
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                                {0, 0, 0, 0, 0},
+                        },
+
+        },
+        .calTarget_freqbin_5G = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5600, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT20 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+        },
+        .calTarget_freqbin_5GHT40 = {
+                FREQ2FBIN(5180, 0),
+                FREQ2FBIN(5240, 0),
+                FREQ2FBIN(5320, 0),
+                FREQ2FBIN(5400, 0),
+                FREQ2FBIN(5500, 0),
+                FREQ2FBIN(5700, 0),
+                FREQ2FBIN(5745, 0),
+                FREQ2FBIN(5825, 0)
+         },
+        .calTargetPower5G = {
+                /* 6-24,36,48,54 */
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+                { {30, 30, 28, 24} },
+         },
+        .calTargetPower5GHT20 = {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
+                { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
+                { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
+                { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+                { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
+         },
+        .calTargetPower5GHT40 =  {
+                /*
+                 * 0_8_16,1-3_9-11_17-19,
+                 * 4,5,6,7,12,13,14,15,20,21,22,23
+                 */
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
+                { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
+                { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
+                { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+                { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
+         },
+        .ctlIndex_5G =  {
+                0x10, 0x16, 0x18, 0x40, 0x46,
+                0x48, 0x30, 0x36, 0x38
+        },
+        .ctl_freqbin_5G =  {
+                {
+                        /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+                {
+                        /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
+                        /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
+                        /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
+                },
+
+                {
+                        /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[3].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[3].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[4].ctlEdges[4].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[5].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[4].ctlEdges[7].bChannel */ 0xFF,
+                },
+
+                {
+                        /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
+                        /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
+                        /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[5].ctlEdges[6].bChannel */ 0xFF,
+                        /* Data[5].ctlEdges[7].bChannel */ 0xFF
+                },
+
+                {
+                        /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
+                        /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
+                        /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
+                        /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
+                },
+
+                {
+                        /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
+                        /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
+                        /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
+                        /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
+                        /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
+                        /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
+                        /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
+                        /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
+                },
+
+                {
+                        /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
+                        /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
+                        /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
+                        /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
+                        /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
+                        /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
+                        /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
+                        /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
+                }
+         },
+        .ctlPowerData_5G = {
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                                CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
+                        }
+                },
+                {
+                        {
+                                CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
+                                CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
+                        }
+                },
+         }
+};
+
+
+static const struct ar9300_eeprom *ar9300_eep_templates[] = {
+        &ar9300_default,
+        &ar9300_x112,
+        &ar9300_h116,
+        &ar9300_h112,
+        &ar9300_x113,
+};
+
+static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
+{
+#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
+        int it;
+
+        for (it = 0; it < N_LOOP; it++)
+                if (ar9300_eep_templates[it]->templateVersion == id)
+                        return ar9300_eep_templates[it];
+        return NULL;
+#undef N_LOOP
+}
+
+
 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
 {
-        if (fbin == AR9300_BCHAN_UNUSED)
+        if (fbin == AR5416_BCHAN_UNUSED)
                 return fbin;
 
         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
@@ -639,6 +2988,16 @@ static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
         return 0;
 }
 
+static int interpolate(int x, int xa, int xb, int ya, int yb)
+{
+        int bf, factor, plus;
+
+        bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
+        factor = bf / 2;
+        plus = bf % 2;
+        return ya + factor + plus;
+}
+
 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                                       enum eeprom_param param)
 {
@@ -676,6 +3035,10 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
                 return le32_to_cpu(pBase->swreg);
         case EEP_PAPRD:
                 return !!(pBase->featureEnable & BIT(5));
+        case EEP_CHAIN_MASK_REDUCE:
+                return (pBase->miscConfiguration >> 0x3) & 0x1;
+        case EEP_ANT_DIV_CTL1:
+                return le32_to_cpu(eep->base_ext1.ant_div_control);
         default:
                 return 0;
         }
@@ -714,8 +3077,8 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
         int i;
 
         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "eeprom address not in range\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "eeprom address not in range\n");
                 return false;
         }
 
@@ -746,11 +3109,41 @@ static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
         return true;
 
 error:
-        ath_print(common, ATH_DBG_EEPROM,
-                  "unable to read eeprom region at offset %d\n", address);
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "unable to read eeprom region at offset %d\n", address);
         return false;
 }
 
+static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
+{
+        REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
+
+        if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
+                           AR9300_OTP_STATUS_VALID, 1000))
+                return false;
+
+        *data = REG_READ(ah, AR9300_OTP_READ_DATA);
+        return true;
+}
+
+static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
+                            int count)
+{
+        u32 data;
+        int i;
+
+        for (i = 0; i < count; i++) {
+                int offset = 8 * ((address - i) % 4);
+                if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
+                        return false;
+
+                buffer[i] = (data >> offset) & 0xff;
+        }
+
+        return true;
+}
+
+
 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
                                    int *length, int *major, int *minor)
 {
@@ -801,17 +3194,15 @@ static bool ar9300_uncompress_block(struct ath_hw *ah,
                 length &= 0xff;
 
                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Restore at %d: spot=%d "
-                                  "offset=%d length=%d\n",
-                                   it, spot, offset, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Restore at %d: spot=%d offset=%d length=%d\n",
+                                it, spot, offset, length);
                         memcpy(&mptr[spot], &block[it+2], length);
                         spot += length;
                 } else if (length > 0) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Bad restore at %d: spot=%d "
-                                  "offset=%d length=%d\n",
-                                  it, spot, offset, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Bad restore at %d: spot=%d offset=%d length=%d\n",
+                                it, spot, offset, length);
                         return false;
                 }
         }
@@ -827,45 +3218,80 @@ static int ar9300_compress_decision(struct ath_hw *ah,
 {
         struct ath_common *common = ath9k_hw_common(ah);
         u8 *dptr;
+        const struct ar9300_eeprom *eep = NULL;
 
         switch (code) {
         case _CompressNone:
                 if (length != mdata_size) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "EEPROM structure size mismatch"
-                                  "memory=%d eeprom=%d\n", mdata_size, length);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "EEPROM structure size mismatch memory=%d eeprom=%d\n",
+                                mdata_size, length);
                         return -1;
                 }
                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
-                ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
-                          " uncompressed, length %d\n", it, length);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "restored eeprom %d: uncompressed, length %d\n",
+                        it, length);
                 break;
         case _CompressBlock:
                 if (reference == 0) {
                         dptr = mptr;
                 } else {
-                        if (reference != 2) {
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "cant find reference eeprom"
-                                          "struct %d\n", reference);
+                        eep = ar9003_eeprom_struct_find_by_id(reference);
+                        if (eep == NULL) {
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "cant find reference eeprom struct %d\n",
+                                        reference);
                                 return -1;
                         }
-                        memcpy(mptr, &ar9300_default, mdata_size);
+                        memcpy(mptr, eep, mdata_size);
                 }
-                ath_print(common, ATH_DBG_EEPROM,
-                          "restore eeprom %d: block, reference %d,"
-                          " length %d\n", it, reference, length);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "restore eeprom %d: block, reference %d, length %d\n",
+                        it, reference, length);
                 ar9300_uncompress_block(ah, mptr, mdata_size,
                                         (u8 *) (word + COMP_HDR_LEN), length);
                 break;
         default:
-                ath_print(common, ATH_DBG_EEPROM, "unknown compression"
-                          " code %d\n", code);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "unknown compression code %d\n", code);
                 return -1;
         }
         return 0;
 }
 
+typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
+                               int count);
+
+static bool ar9300_check_header(void *data)
+{
+        u32 *word = data;
+        return !(*word == 0 || *word == ~0);
+}
+
+static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
+                                       int base_addr)
+{
+        u8 header[4];
+
+        if (!read(ah, base_addr, header, 4))
+                return false;
+
+        return ar9300_check_header(header);
+}
+
+static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
+                                       int mdata_size)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        u16 *data = (u16 *) mptr;
+        int i;
+
+        for (i = 0; i < mdata_size / 2; i++, data++)
+                ath9k_hw_nvram_read(common, i, data);
+
+        return 0;
+}
 /*
  * Read the configuration data from the eeprom.
  * The data can be put in any specified memory buffer.
@@ -886,6 +3312,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
         int it;
         u16 checksum, mchecksum;
         struct ath_common *common = ath9k_hw_common(ah);
+        eeprom_read_op read;
+
+        if (ath9k_hw_use_flash(ah))
+                return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
 
         word = kzalloc(2048, GFP_KERNEL);
         if (!word)
@@ -893,43 +3323,73 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
 
         memcpy(mptr, &ar9300_default, mdata_size);
 
+        read = ar9300_read_eeprom;
+        if (AR_SREV_9485(ah))
+                cptr = AR9300_BASE_ADDR_4K;
+        else
+                cptr = AR9300_BASE_ADDR;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying EEPROM accesss at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        cptr = AR9300_BASE_ADDR_512;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying EEPROM accesss at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        read = ar9300_read_otp;
         cptr = AR9300_BASE_ADDR;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying OTP accesss at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        cptr = AR9300_BASE_ADDR_512;
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "Trying OTP accesss at Address 0x%04x\n", cptr);
+        if (ar9300_check_eeprom_header(ah, read, cptr))
+                goto found;
+
+        goto fail;
+
+found:
+        ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
+
         for (it = 0; it < MSTATE; it++) {
-                if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
+                if (!read(ah, cptr, word, COMP_HDR_LEN))
                         goto fail;
 
-                if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
-                     word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
-                                       && word[2] == 0xff && word[3] == 0xff))
+                if (!ar9300_check_header(word))
                         break;
 
                 ar9300_comp_hdr_unpack(word, &code, &reference,
                                        &length, &major, &minor);
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Found block at %x: code=%d ref=%d"
-                          "length=%d major=%d minor=%d\n", cptr, code,
-                          reference, length, major, minor);
-                if (length >= 1024) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Skipping bad header\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
+                        cptr, code, reference, length, major, minor);
+                if ((!AR_SREV_9485(ah) && length >= 1024) ||
+                    (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Skipping bad header\n");
                         cptr -= COMP_HDR_LEN;
                         continue;
                 }
 
                 osize = length;
-                ar9300_read_eeprom(ah, cptr, word,
-                                   COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
+                read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
                 mchecksum = word[COMP_HDR_LEN + osize] |
                     (word[COMP_HDR_LEN + osize + 1] << 8);
-                ath_print(common, ATH_DBG_EEPROM,
-                          "checksum %x %x\n", checksum, mchecksum);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "checksum %x %x\n", checksum, mchecksum);
                 if (checksum == mchecksum) {
                         ar9300_compress_decision(ah, it, code, reference, mptr,
                                                  word, length, mdata_size);
                 } else {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "skipping block with bad checksum\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "skipping block with bad checksum\n");
                 }
                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
         }
@@ -970,18 +3430,6 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
         return 0;
 }
 
-static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
-                                             enum ath9k_hal_freq_band freq_band)
-{
-        return 1;
-}
-
-static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                                  struct ath9k_channel *chan)
-{
-        return -EINVAL;
-}
-
 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 {
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
@@ -995,9 +3443,15 @@ static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
 {
         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
-        REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, (bias & 0x3));
-        REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_SPARE,
-                      ((bias >> 2) & 0x3));
+
+        if (AR_SREV_9485(ah))
+                REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+        else {
+                REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
+                REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
+                              bias >> 2);
+                REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
+        }
 }
 
 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
@@ -1052,11 +3506,25 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
         value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
         REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
+        if (!AR_SREV_9485(ah)) {
+                value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
+                REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
+                              value);
 
-        value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
-        REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
+                value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
+                REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
+                              value);
+        }
+
+        if (AR_SREV_9485(ah)) {
+                value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
+                REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
+                              value);
+                REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
+                              value >> 6);
+                REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
+                              value >> 7);
+        }
 }
 
 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
@@ -1100,28 +3568,177 @@ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
 }
 
+static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
+                                     struct ath9k_channel *chan)
+{
+        int f[3], t[3];
+        u16 value;
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (chain >= 0 && chain < 3) {
+                if (IS_CHAN_2GHZ(chan))
+                        return eep->modalHeader2G.xatten1DB[chain];
+                else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
+                        t[0] = eep->base_ext2.xatten1DBLow[chain];
+                        f[0] = 5180;
+                        t[1] = eep->modalHeader5G.xatten1DB[chain];
+                        f[1] = 5500;
+                        t[2] = eep->base_ext2.xatten1DBHigh[chain];
+                        f[2] = 5785;
+                        value = ar9003_hw_power_interpolate((s32) chan->channel,
+                                                            f, t, 3);
+                        return value;
+                } else
+                        return eep->modalHeader5G.xatten1DB[chain];
+        }
+
+        return 0;
+}
+
+
+static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
+                                            struct ath9k_channel *chan)
+{
+        int f[3], t[3];
+        u16 value;
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (chain >= 0 && chain < 3) {
+                if (IS_CHAN_2GHZ(chan))
+                        return eep->modalHeader2G.xatten1Margin[chain];
+                else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
+                        t[0] = eep->base_ext2.xatten1MarginLow[chain];
+                        f[0] = 5180;
+                        t[1] = eep->modalHeader5G.xatten1Margin[chain];
+                        f[1] = 5500;
+                        t[2] = eep->base_ext2.xatten1MarginHigh[chain];
+                        f[2] = 5785;
+                        value = ar9003_hw_power_interpolate((s32) chan->channel,
+                                                            f, t, 3);
+                        return value;
+                } else
+                        return eep->modalHeader5G.xatten1Margin[chain];
+        }
+
+        return 0;
+}
+
+static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
+{
+        int i;
+        u16 value;
+        unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
+                                          AR_PHY_EXT_ATTEN_CTL_1,
+                                          AR_PHY_EXT_ATTEN_CTL_2,
+                                         };
+
+        /* Test value. if 0 then attenuation is unused. Don't load anything. */
+        for (i = 0; i < 3; i++) {
+                value = ar9003_hw_atten_chain_get(ah, i, chan);
+                REG_RMW_FIELD(ah, ext_atten_reg[i],
+                              AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
+
+                value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
+                REG_RMW_FIELD(ah, ext_atten_reg[i],
+                              AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
+        }
+}
+
+static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
+{
+        int timeout = 100;
+
+        while (pmu_set != REG_READ(ah, pmu_reg)) {
+                if (timeout-- == 0)
+                        return false;
+                REG_WRITE(ah, pmu_reg, pmu_set);
+                udelay(10);
+        }
+
+        return true;
+}
+
 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
 {
         int internal_regulator =
                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
 
         if (internal_regulator) {
-                /* Internal regulator is ON. Write swreg register. */
-                int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
-                REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                REG_READ(ah, AR_RTC_REG_CONTROL1) &
-                         (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
-                REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
-                /* Set REG_CONTROL1.SWREG_PROGRAM */
-                REG_WRITE(ah, AR_RTC_REG_CONTROL1,
-                          REG_READ(ah,
-                                   AR_RTC_REG_CONTROL1) |
-                                   AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+                if (AR_SREV_9485(ah)) {
+                        int reg_pmu_set;
+
+                        reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
+                                      (7 << 14) | (6 << 17) | (1 << 20) |
+                                      (3 << 24) | (1 << 28);
+
+                        REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
+                                        | (4 << 26);
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+
+                        reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
+                                        | (1 << 21);
+                        REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
+                        if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+                                return;
+                } else {
+                        /* Internal regulator is ON. Write swreg register. */
+                        int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                  REG_READ(ah, AR_RTC_REG_CONTROL1) &
+                                  (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
+                        /* Set REG_CONTROL1.SWREG_PROGRAM */
+                        REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+                                  REG_READ(ah,
+                                           AR_RTC_REG_CONTROL1) |
+                                           AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
+                }
         } else {
-                REG_WRITE(ah, AR_RTC_SLEEP_CLK,
-                          (REG_READ(ah,
-                                    AR_RTC_SLEEP_CLK) |
-                                    AR_RTC_FORCE_SWREG_PRD));
+                if (AR_SREV_9485(ah)) {
+                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
+                        while (REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                              AR_PHY_PMU2_PGM))
+                                udelay(10);
+
+                        REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
+                        while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
+                                               AR_PHY_PMU1_PWD))
+                                udelay(10);
+                        REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
+                        while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
+                                              AR_PHY_PMU2_PGM))
+                                udelay(10);
+                } else
+                        REG_WRITE(ah, AR_RTC_SLEEP_CLK,
+                                  (REG_READ(ah,
+                                   AR_RTC_SLEEP_CLK) |
+                                   AR_RTC_FORCE_SWREG_PRD));
+        }
+
+}
+
+static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+
+        if (eep->baseEepHeader.featureEnable & 0x40) {
+                tuning_caps_param &= 0x7f;
+                REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
+                              tuning_caps_param);
+                REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
+                              tuning_caps_param);
         }
 }
 
@@ -1131,7 +3748,10 @@ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
         ar9003_hw_drive_strength_apply(ah);
+        ar9003_hw_atten_apply(ah, chan);
         ar9003_hw_internal_regulator_apply(ah);
+        if (AR_SREV_9485(ah))
+                ar9003_hw_apply_tuning_caps(ah);
 }
 
 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
@@ -1192,7 +3812,7 @@ static int ar9003_hw_power_interpolate(int32_t x,
                         if (hx == lx)
                                 y = ly;
                         else    /* interpolate  */
-                                y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
+                                y = interpolate(x, lx, hx, ly, hy);
                 } else          /* only low is good, use it */
                         y = ly;
         } else if (hhave)       /* only high is good, use it */
@@ -1561,22 +4181,9 @@ static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
                                               is2GHz) + ht40PowerIncForPdadc;
 
-        while (i < ar9300RateSize) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
-                i++;
+        for (i = 0; i < ar9300RateSize; i++) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
         }
 }
 
@@ -1595,18 +4202,17 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
         struct ath_common *common = ath9k_hw_common(ah);
 
         if (ichain >= AR9300_MAX_CHAINS) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Invalid chain index, must be less than %d\n",
-                          AR9300_MAX_CHAINS);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Invalid chain index, must be less than %d\n",
+                        AR9300_MAX_CHAINS);
                 return -1;
         }
 
         if (mode) {             /* 5GHz */
                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Invalid 5GHz cal pier index, must "
-                                  "be less than %d\n",
-                                  AR9300_NUM_5G_CAL_PIERS);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Invalid 5GHz cal pier index, must be less than %d\n",
+                                AR9300_NUM_5G_CAL_PIERS);
                         return -1;
                 }
                 pCalPier = &(eep->calFreqPier5G[ipier]);
@@ -1614,9 +4220,9 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
                 is2GHz = 0;
         } else {
                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Invalid 2GHz cal pier index, must "
-                                  "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Invalid 2GHz cal pier index, must be less than %d\n",
+                                AR9300_NUM_2G_CAL_PIERS);
                         return -1;
                 }
 
@@ -1640,27 +4246,32 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
 {
         int tempSlope = 0;
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        int f[3], t[3];
 
         REG_RMW(ah, AR_PHY_TPC_11_B0,
                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
                 AR_PHY_TPC_OLPC_GAIN_DELTA);
-        REG_RMW(ah, AR_PHY_TPC_11_B1,
-                (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-                AR_PHY_TPC_OLPC_GAIN_DELTA);
-        REG_RMW(ah, AR_PHY_TPC_11_B2,
-                (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
-                AR_PHY_TPC_OLPC_GAIN_DELTA);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW(ah, AR_PHY_TPC_11_B1,
+                        (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                        AR_PHY_TPC_OLPC_GAIN_DELTA);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW(ah, AR_PHY_TPC_11_B2,
+                        (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
+                        AR_PHY_TPC_OLPC_GAIN_DELTA);
 
         /* enable open loop power control on chip */
         REG_RMW(ah, AR_PHY_TPC_6_B0,
                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
                 AR_PHY_TPC_6_ERROR_EST_MODE);
-        REG_RMW(ah, AR_PHY_TPC_6_B1,
-                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-                AR_PHY_TPC_6_ERROR_EST_MODE);
-        REG_RMW(ah, AR_PHY_TPC_6_B2,
-                (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
-                AR_PHY_TPC_6_ERROR_EST_MODE);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW(ah, AR_PHY_TPC_6_B1,
+                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                        AR_PHY_TPC_6_ERROR_EST_MODE);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW(ah, AR_PHY_TPC_6_B2,
+                        (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
+                        AR_PHY_TPC_6_ERROR_EST_MODE);
 
         /*
          * enable temperature compensation
@@ -1668,7 +4279,16 @@ static int ar9003_hw_power_control_override(struct ath_hw *ah,
          */
         if (frequency < 4000)
                 tempSlope = eep->modalHeader2G.tempSlope;
-        else
+        else if (eep->base_ext2.tempSlopeLow != 0) {
+                t[0] = eep->base_ext2.tempSlopeLow;
+                f[0] = 5180;
+                t[1] = eep->modalHeader5G.tempSlope;
+                f[1] = 5500;
+                t[2] = eep->base_ext2.tempSlopeHigh;
+                f[2] = 5785;
+                tempSlope = ar9003_hw_power_interpolate((s32) frequency,
+                                                        f, t, 3);
+        } else
                 tempSlope = eep->modalHeader5G.tempSlope;
 
         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
@@ -1756,11 +4376,11 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
 
         /* interpolate  */
         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "ch=%d f=%d low=%d %d h=%d %d\n",
-                          ichain, frequency, lfrequency[ichain],
-                          lcorrection[ichain], hfrequency[ichain],
-                          hcorrection[ichain]);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "ch=%d f=%d low=%d %d h=%d %d\n",
+                        ichain, frequency, lfrequency[ichain],
+                        lcorrection[ichain], hfrequency[ichain],
+                        hcorrection[ichain]);
                 /* they're the same, so just pick one */
                 if (hfrequency[ichain] == lfrequency[ichain]) {
                         correction[ichain] = lcorrection[ichain];
@@ -1772,25 +4392,23 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
                         /* so is the high frequency, interpolate */
                         if (hfrequency[ichain] - frequency < 1000) {
 
-                                correction[ichain] = lcorrection[ichain] +
-                                    (((frequency - lfrequency[ichain]) *
-                                      (hcorrection[ichain] -
-                                       lcorrection[ichain])) /
-                                     (hfrequency[ichain] - lfrequency[ichain]));
-
-                                temperature[ichain] = ltemperature[ichain] +
-                                    (((frequency - lfrequency[ichain]) *
-                                      (htemperature[ichain] -
-                                       ltemperature[ichain])) /
-                                     (hfrequency[ichain] - lfrequency[ichain]));
-
-                                voltage[ichain] =
-                                    lvoltage[ichain] +
-                                    (((frequency -
-                                       lfrequency[ichain]) * (hvoltage[ichain] -
-                                                              lvoltage[ichain]))
-                                     / (hfrequency[ichain] -
-                                        lfrequency[ichain]));
+                                correction[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                lcorrection[ichain],
+                                                hcorrection[ichain]);
+
+                                temperature[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                ltemperature[ichain],
+                                                htemperature[ichain]);
+
+                                voltage[ichain] = interpolate(frequency,
+                                                lfrequency[ichain],
+                                                hfrequency[ichain],
+                                                lvoltage[ichain],
+                                                hvoltage[ichain]);
                         }
                         /* only low is good, use it */
                         else {
@@ -1814,9 +4432,9 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
                                          temperature);
 
-        ath_print(common, ATH_DBG_EEPROM,
-                  "for frequency=%d, calibration correction = %d %d %d\n",
-                  frequency, correction[0], correction[1], correction[2]);
+        ath_dbg(common, ATH_DBG_EEPROM,
+                "for frequency=%d, calibration correction = %d %d %d\n",
+                frequency, correction[0], correction[1], correction[2]);
 
         return 0;
 }
@@ -1858,7 +4476,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
         }
 
-        return AR9300_MAX_RATE_POWER;
+        return MAX_RATE_POWER;
 }
 
 /*
@@ -1867,7 +4485,7 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
                                         u16 freq, int idx, bool is2GHz)
 {
-        u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         u8 *ctl_freqbin = is2GHz ?
                 &eep->ctl_freqbin_2G[idx][0] :
                 &eep->ctl_freqbin_5G[idx][0];
@@ -1877,7 +4495,7 @@ static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
 
         /* Get the edge power */
         for (edge = 0;
-             (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
+             (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
              edge++) {
                 /*
                  * If there's an exact channel match or an inband flag set
@@ -1915,21 +4533,23 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
-        u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] = {
-                0, 3, 6, 9, AR9300_MAX_RATE_POWER
+                0, 3, 6, 9, MAX_RATE_POWER
         };
         int i;
         int16_t  twiceLargestAntenna;
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11a[] = {
+        static const u16 ctlModesFor11a[] = {
                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
         };
-        u16 ctlModesFor11g[] = {
+        static const u16 ctlModesFor11g[] = {
                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
                 CTL_11G_EXT, CTL_2GHT40
         };
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         u8 *ctlIndex;
         u8 ctlNum;
@@ -2019,11 +4639,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                 else
                         freq = centers.ctl_center;
 
-                ath_print(common, ATH_DBG_REGULATORY,
-                          "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
-                          "EXT_ADDITIVE %d\n",
-                          ctlMode, numCtlModes, isHt40CtlMode,
-                          (pCtlMode[ctlMode] & EXT_ADDITIVE));
+                ath_dbg(common, ATH_DBG_REGULATORY,
+                        "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
+                        ctlMode, numCtlModes, isHt40CtlMode,
+                        (pCtlMode[ctlMode] & EXT_ADDITIVE));
 
                 /* walk through each CTL index stored in EEPROM */
                 if (is2ghz) {
@@ -2035,12 +4654,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
                 }
 
                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
-                        ath_print(common, ATH_DBG_REGULATORY,
-                                  "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
-                                  "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
-                                  "chan %dn",
-                                  i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
-                                  chan->channel);
+                        ath_dbg(common, ATH_DBG_REGULATORY,
+                                "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
+                                i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
+                                chan->channel);
 
                                 /*
                                  * compare test group from regulatory
@@ -2079,11 +4696,10 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
 
                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 
-                        ath_print(common, ATH_DBG_REGULATORY,
-                                  "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
-                                  "sP %d minCtlPwr %d\n",
-                                  ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
-                                  scaledPower, minCtlPower);
+                        ath_dbg(common, ATH_DBG_REGULATORY,
+                                "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
+                                ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
+                                scaledPower, minCtlPower);
 
                         /* Apply ctl mode to correct target power set */
                         switch (pCtlMode[ctlMode]) {
@@ -2130,40 +4746,101 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
         } /* end ctl mode checking */
 }
 
+static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
+{
+        u8 mod_idx = mcs_idx % 8;
+
+        if (mod_idx <= 3)
+                return mod_idx ? (base_pwridx + 1) : base_pwridx;
+        else
+                return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
+}
+
 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
                                         struct ath9k_channel *chan, u16 cfgCtl,
                                         u8 twiceAntennaReduction,
                                         u8 twiceMaxRegulatoryPower,
-                                        u8 powerLimit)
+                                        u8 powerLimit, bool test)
 {
+        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath_common *common = ath9k_hw_common(ah);
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        struct ar9300_modal_eep_header *modal_hdr;
         u8 targetPowerValT2[ar9300RateSize];
-        unsigned int i = 0;
+        u8 target_power_val_t2_eep[ar9300RateSize];
+        unsigned int i = 0, paprd_scale_factor = 0;
+        u8 pwr_idx, min_pwridx = 0;
 
         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
+
+        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
+                if (IS_CHAN_2GHZ(chan))
+                        modal_hdr = &eep->modalHeader2G;
+                else
+                        modal_hdr = &eep->modalHeader5G;
+
+                ah->paprd_ratemask =
+                        le32_to_cpu(modal_hdr->papdRateMaskHt20) &
+                        AR9300_PAPRD_RATE_MASK;
+
+                ah->paprd_ratemask_ht40 =
+                        le32_to_cpu(modal_hdr->papdRateMaskHt40) &
+                        AR9300_PAPRD_RATE_MASK;
+
+                paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
+                min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
+                                                  ALL_TARGET_HT20_0_8_16;
+
+                if (!ah->paprd_table_write_done) {
+                        memcpy(target_power_val_t2_eep, targetPowerValT2,
+                               sizeof(targetPowerValT2));
+                        for (i = 0; i < 24; i++) {
+                                pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
+                                if (ah->paprd_ratemask & (1 << i)) {
+                                        if (targetPowerValT2[pwr_idx] &&
+                                            targetPowerValT2[pwr_idx] ==
+                                            target_power_val_t2_eep[pwr_idx])
+                                                targetPowerValT2[pwr_idx] -=
+                                                        paprd_scale_factor;
+                                }
+                        }
+                }
+                memcpy(target_power_val_t2_eep, targetPowerValT2,
+                       sizeof(targetPowerValT2));
+        }
+
         ar9003_hw_set_power_per_rate_table(ah, chan,
                                            targetPowerValT2, cfgCtl,
                                            twiceAntennaReduction,
                                            twiceMaxRegulatoryPower,
                                            powerLimit);
 
-        while (i < ar9300RateSize) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
-                i++;
-                ath_print(common, ATH_DBG_EEPROM,
-                          "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
-                i++;
+        if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
+                for (i = 0; i < ar9300RateSize; i++) {
+                        if ((ah->paprd_ratemask & (1 << i)) &&
+                            (abs(targetPowerValT2[i] -
+                                target_power_val_t2_eep[i]) >
+                            paprd_scale_factor)) {
+                                ah->paprd_ratemask &= ~(1 << i);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "paprd disabled for mcs %d\n", i);
+                        }
+                }
         }
 
-        /* Write target power array to registers */
-        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
+        regulatory->max_power_level = 0;
+        for (i = 0; i < ar9300RateSize; i++) {
+                if (targetPowerValT2[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = targetPowerValT2[i];
+        }
+
+        if (test)
+                return;
+
+        for (i = 0; i < ar9300RateSize; i++) {
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
+        }
 
         /*
          * This is the TX power we send back to driver core,
@@ -2183,8 +4860,24 @@ static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
                 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
 
         ah->txpower_limit = targetPowerValT2[i];
+        regulatory->max_power_level = targetPowerValT2[i];
 
+        /* Write target power array to registers */
+        ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
         ar9003_hw_calibration_apply(ah, chan->channel);
+
+        if (IS_CHAN_2GHZ(chan)) {
+                if (IS_CHAN_HT40(chan))
+                        i = ALL_TARGET_HT40_0_8_16;
+                else
+                        i = ALL_TARGET_HT20_0_8_16;
+        } else {
+                if (IS_CHAN_HT40(chan))
+                        i = ALL_TARGET_HT40_7;
+                else
+                        i = ALL_TARGET_HT20_7;
+        }
+        ah->paprd_target_power = targetPowerValT2[i];
 }
 
 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
@@ -2207,14 +4900,43 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
 }
 
+u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (is_2ghz)
+                return eep->modalHeader2G.spurChans;
+        else
+                return eep->modalHeader5G.spurChans;
+}
+
+unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+                                           struct ath9k_channel *chan)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+        if (IS_CHAN_2GHZ(chan))
+                return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
+                          AR9300_PAPRD_SCALE_1);
+        else {
+                if (chan->channel >= 5700)
+                return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
+                          AR9300_PAPRD_SCALE_1);
+                else if (chan->channel >= 5400)
+                        return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
+                                   AR9300_PAPRD_SCALE_2);
+                else
+                        return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
+                                  AR9300_PAPRD_SCALE_1);
+        }
+}
+
 const struct eeprom_ops eep_ar9300_ops = {
         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
-        .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
         .set_board_values = ath9k_hw_ar9300_set_board_values,
         .set_addac = ath9k_hw_ar9300_set_addac,
         .set_txpower = ath9k_hw_ar9300_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 655b3033396c..afb0b5ee1865 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -20,47 +20,22 @@
 /* #define AR9300_NUM_CTLS              21 */
 #define AR9300_NUM_CTLS_5G           9
 #define AR9300_NUM_CTLS_2G           12
-#define AR9300_CTL_MODE_M            0xF
 #define AR9300_NUM_BAND_EDGES_5G     8
 #define AR9300_NUM_BAND_EDGES_2G     4
-#define AR9300_NUM_PD_GAINS          4
-#define AR9300_PD_GAINS_IN_MASK      4
-#define AR9300_PD_GAIN_ICEPTS        5
-#define AR9300_EEPROM_MODAL_SPURS    5
-#define AR9300_MAX_RATE_POWER        63
-#define AR9300_NUM_PDADC_VALUES      128
-#define AR9300_NUM_RATES             16
-#define AR9300_BCHAN_UNUSED          0xFF
-#define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
-#define AR9300_OPFLAGS_11A           0x01
-#define AR9300_OPFLAGS_11G           0x02
-#define AR9300_OPFLAGS_5G_HT40       0x04
-#define AR9300_OPFLAGS_2G_HT40       0x08
-#define AR9300_OPFLAGS_5G_HT20       0x10
-#define AR9300_OPFLAGS_2G_HT20       0x20
 #define AR9300_EEPMISC_BIG_ENDIAN    0x01
 #define AR9300_EEPMISC_WOW           0x02
 #define AR9300_CUSTOMER_DATA_SIZE    20
 
-#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
 #define AR9300_MAX_CHAINS            3
 #define AR9300_ANT_16S               25
 #define AR9300_FUTURE_MODAL_SZ       6
 
-#define AR9300_NUM_ANT_CHAIN_FIELDS     7
-#define AR9300_NUM_ANT_COMMON_FIELDS    4
-#define AR9300_SIZE_ANT_CHAIN_FIELD     3
-#define AR9300_SIZE_ANT_COMMON_FIELD    4
-#define AR9300_ANT_CHAIN_MASK           0x7
-#define AR9300_ANT_COMMON_MASK          0xf
-#define AR9300_CHAIN_0_IDX              0
-#define AR9300_CHAIN_1_IDX              1
-#define AR9300_CHAIN_2_IDX              2
-
-#define AR928X_NUM_ANT_CHAIN_FIELDS     6
-#define AR928X_SIZE_ANT_CHAIN_FIELD     2
-#define AR928X_ANT_CHAIN_MASK           0x3
+#define AR9300_PAPRD_RATE_MASK          0x01ffffff
+#define AR9300_PAPRD_SCALE_1            0x0e000000
+#define AR9300_PAPRD_SCALE_1_S          25
+#define AR9300_PAPRD_SCALE_2            0x70000000
+#define AR9300_PAPRD_SCALE_2_S          28
 
 /* Delta from which to start power to pdadc table */
 /* This offset is used in both open loop and closed loop power control
@@ -71,14 +46,20 @@
  */
 #define AR9300_PWR_TABLE_OFFSET  0
 
-/* enable flags for voltage and temp compensation */
-#define ENABLE_TEMP_COMPENSATION 0x01
-#define ENABLE_VOLT_COMPENSATION 0x02
 /* byte addressable */
 #define AR9300_EEPROM_SIZE (16*1024)
-#define FIXED_CCA_THRESHOLD 15
 
+#define AR9300_BASE_ADDR_4K 0xfff
 #define AR9300_BASE_ADDR 0x3ff
+#define AR9300_BASE_ADDR_512 0x1ff
+
+#define AR9300_OTP_BASE                 0x14000
+#define AR9300_OTP_STATUS               0x15f18
+#define AR9300_OTP_STATUS_TYPE          0x7
+#define AR9300_OTP_STATUS_VALID         0x4
+#define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
+#define AR9300_OTP_STATUS_SM_BUSY       0x1
+#define AR9300_OTP_READ_DATA            0x15f1c
 
 enum targetPowerHTRates {
         HT_TARGET_RATE_0_8_16,
@@ -216,7 +197,7 @@ struct ar9300_modal_eep_header {
         int8_t tempSlope;
         int8_t voltSlope;
         /* spur channels in usual fbin coding format */
-        u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
+        u8 spurChans[AR_EEPROM_MODAL_SPURS];
         /* 3  Check if the register is per chain */
         int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
         u8 ob[AR9300_MAX_CHAINS];
@@ -236,7 +217,7 @@ struct ar9300_modal_eep_header {
         u8 thresh62;
         __le32 papdRateMaskHt20;
         __le32 papdRateMaskHt40;
-        u8 futureModal[24];
+        u8 futureModal[10];
 } __packed;
 
 struct ar9300_cal_data_per_freq_op_loop {
@@ -269,6 +250,20 @@ struct cal_ctl_data_5g {
         u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G];
 } __packed;
 
+struct ar9300_BaseExtension_1 {
+        u8 ant_div_control;
+        u8 future[13];
+} __packed;
+
+struct ar9300_BaseExtension_2 {
+        int8_t    tempSlopeLow;
+        int8_t    tempSlopeHigh;
+        u8   xatten1DBLow[AR9300_MAX_CHAINS];
+        u8   xatten1MarginLow[AR9300_MAX_CHAINS];
+        u8   xatten1DBHigh[AR9300_MAX_CHAINS];
+        u8   xatten1MarginHigh[AR9300_MAX_CHAINS];
+} __packed;
+
 struct ar9300_eeprom {
         u8 eepromVersion;
         u8 templateVersion;
@@ -278,6 +273,7 @@ struct ar9300_eeprom {
         struct ar9300_base_eep_hdr baseEepHeader;
 
         struct ar9300_modal_eep_header modalHeader2G;
+        struct ar9300_BaseExtension_1 base_ext1;
         u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
         struct ar9300_cal_data_per_freq_op_loop
          calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
@@ -297,6 +293,7 @@ struct ar9300_eeprom {
         u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
         struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
         struct ar9300_modal_eep_header modalHeader5G;
+        struct ar9300_BaseExtension_2 base_ext2;
         u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
         struct ar9300_cal_data_per_freq_op_loop
          calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
@@ -317,4 +314,8 @@ struct ar9300_eeprom {
 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);
 
+u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz);
+
+unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+                                           struct ath9k_channel *chan);
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index c2a057156bfa..6137634e46ca 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -17,20 +17,10 @@
 #include "hw.h"
 #include "ar9003_mac.h"
 #include "ar9003_2p2_initvals.h"
+#include "ar9485_initvals.h"
 
 /* General hardware code for the AR9003 hadware family */
 
-static bool ar9003_hw_macversion_supported(u32 macversion)
-{
-        switch (macversion) {
-        case AR_SREV_VERSION_9300:
-                return true;
-        default:
-                break;
-        }
-        return false;
-}
-
 /*
  * The AR9003 family uses a new INI format (pre, core, post
  * arrays per subsystem). This provides support for the
@@ -38,72 +28,134 @@ static bool ar9003_hw_macversion_supported(u32 macversion)
  */
 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 {
-        /* mac */
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
-                       ar9300_2p2_mac_core,
-                       ARRAY_SIZE(ar9300_2p2_mac_core), 2);
-        INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
-                       ar9300_2p2_mac_postamble,
-                       ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
-
-        /* bb */
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
-                       ar9300_2p2_baseband_core,
-                       ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
-        INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
-                       ar9300_2p2_baseband_postamble,
-                       ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
-
-        /* radio */
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
-                       ar9300_2p2_radio_core,
-                       ARRAY_SIZE(ar9300_2p2_radio_core), 2);
-        INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
-                       ar9300_2p2_radio_postamble,
-                       ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
-
-        /* soc */
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
-                       ar9300_2p2_soc_preamble,
-                       ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
-        INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
-                       ar9300_2p2_soc_postamble,
-                       ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
-
-        /* rx/tx gain */
-        INIT_INI_ARRAY(&ah->iniModesRxGain,
-                       ar9300Common_rx_gain_table_2p2,
-                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
-        INIT_INI_ARRAY(&ah->iniModesTxGain,
-                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
-                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
-                       5);
-
-        /* Load PCIE SERDES settings from INI */
-
-        /* Awake Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdes,
-                       ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
-                       ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
-                       2);
-
-        /* Sleep Setting */
-
-        INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-                       ar9300PciePhy_clkreq_enable_L1_2p2,
-                       ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
-                       2);
-
-        /* Fast clock modal settings */
-        INIT_INI_ARRAY(&ah->iniModesAdditional,
-                       ar9300Modes_fast_clock_2p2,
-                       ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
-                       3);
+        if (AR_SREV_9485(ah)) {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9485_1_0_mac_core,
+                                ARRAY_SIZE(ar9485_1_0_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9485_1_0_mac_postamble,
+                                ARRAY_SIZE(ar9485_1_0_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_0,
+                                ARRAY_SIZE(ar9485_1_0), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9485_1_0_baseband_core,
+                                ARRAY_SIZE(ar9485_1_0_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9485_1_0_baseband_postamble,
+                                ARRAY_SIZE(ar9485_1_0_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9485_1_0_radio_core,
+                                ARRAY_SIZE(ar9485_1_0_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9485_1_0_radio_postamble,
+                                ARRAY_SIZE(ar9485_1_0_radio_postamble), 2);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9485_1_0_soc_preamble,
+                                ARRAY_SIZE(ar9485_1_0_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9485Common_rx_gain_1_0,
+                                ARRAY_SIZE(ar9485Common_rx_gain_1_0), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9485Modes_lowest_ob_db_tx_gain_1_0,
+                                ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+                                5);
+
+                /* Load PCIE SERDES settings from INI */
+
+                /* Awake Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1,
+                                ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1),
+                                2);
+
+                /* Sleep Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1,
+                                ARRAY_SIZE(ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1),
+                                2);
+        } else {
+                /* mac */
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+                                ar9300_2p2_mac_core,
+                                ARRAY_SIZE(ar9300_2p2_mac_core), 2);
+                INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+                                ar9300_2p2_mac_postamble,
+                                ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
+
+                /* bb */
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+                                ar9300_2p2_baseband_core,
+                                ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
+                INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+                                ar9300_2p2_baseband_postamble,
+                                ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
+
+                /* radio */
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+                                ar9300_2p2_radio_core,
+                                ARRAY_SIZE(ar9300_2p2_radio_core), 2);
+                INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+                                ar9300_2p2_radio_postamble,
+                                ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
+
+                /* soc */
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+                                ar9300_2p2_soc_preamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+                INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+                                ar9300_2p2_soc_postamble,
+                                ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
+
+                /* rx/tx gain */
+                INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                ar9300Common_rx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
+                INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+                                ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+                                5);
+
+                /* Load PCIE SERDES settings from INI */
+
+                /* Awake Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdes,
+                                ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+                                2);
+
+                /* Sleep Setting */
+
+                INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+                                ar9300PciePhy_clkreq_enable_L1_2p2,
+                                ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
+                                2);
+
+                /* Fast clock modal settings */
+                INIT_INI_ARRAY(&ah->iniModesAdditional,
+                                ar9300Modes_fast_clock_2p2,
+                                ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+                                3);
+        }
 }
 
 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
@@ -111,22 +163,52 @@ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
         switch (ar9003_hw_get_tx_gain_idx(ah)) {
         case 0:
         default:
-                INIT_INI_ARRAY(&ah->iniModesTxGain,
-                               ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
-                               ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
-                               5);
+                if (AR_SREV_9485(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9485Modes_lowest_ob_db_tx_gain_1_0,
+                                       ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+                                       5);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+                                       5);
                 break;
         case 1:
-                INIT_INI_ARRAY(&ah->iniModesTxGain,
-                               ar9300Modes_high_ob_db_tx_gain_table_2p2,
-                               ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
-                               5);
+                if (AR_SREV_9485(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9485Modes_high_ob_db_tx_gain_1_0,
+                                       ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+                                       5);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9300Modes_high_ob_db_tx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
+                                       5);
                 break;
         case 2:
-                INIT_INI_ARRAY(&ah->iniModesTxGain,
-                               ar9300Modes_low_ob_db_tx_gain_table_2p2,
-                               ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
-                               5);
+                if (AR_SREV_9485(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9485Modes_low_ob_db_tx_gain_1_0,
+                                       ARRAY_SIZE(ar9485Modes_lowest_ob_db_tx_gain_1_0),
+                                       5);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9300Modes_low_ob_db_tx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
+                                       5);
+                break;
+        case 3:
+                if (AR_SREV_9485(ah))
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9485Modes_high_power_tx_gain_1_0,
+                                       ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_0),
+                                       5);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesTxGain,
+                                       ar9300Modes_high_power_tx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
+                                       5);
                 break;
         }
 }
@@ -136,16 +218,28 @@ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
         switch (ar9003_hw_get_rx_gain_idx(ah)) {
         case 0:
         default:
-                INIT_INI_ARRAY(&ah->iniModesRxGain,
-                               ar9300Common_rx_gain_table_2p2,
-                               ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
-                               2);
+                if (AR_SREV_9485(ah))
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9485Common_rx_gain_1_0,
+                                       ARRAY_SIZE(ar9485Common_rx_gain_1_0),
+                                       2);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9300Common_rx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
+                                       2);
                 break;
         case 1:
-                INIT_INI_ARRAY(&ah->iniModesRxGain,
-                               ar9300Common_wo_xlna_rx_gain_table_2p2,
-                               ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
-                               2);
+                if (AR_SREV_9485(ah))
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9485Common_wo_xlna_rx_gain_1_0,
+                                       ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_0),
+                                       2);
+                else
+                        INIT_INI_ARRAY(&ah->iniModesRxGain,
+                                       ar9300Common_wo_xlna_rx_gain_table_2p2,
+                                       ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
+                                       2);
                 break;
         }
 }
@@ -216,7 +310,6 @@ void ar9003_hw_attach_ops(struct ath_hw *ah)
 
         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
-        priv_ops->macversion_supported = ar9003_hw_macversion_supported;
 
         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index 3b424ca1ba84..4ceddbbdfcee 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -182,8 +182,8 @@ static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
                 }
 
                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT)
-                        ath_print(common, ATH_DBG_INTERRUPT,
-                                  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+                        ath_dbg(common, ATH_DBG_INTERRUPT,
+                                "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
 
                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
@@ -237,73 +237,76 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds,
                                  struct ath_tx_status *ts)
 {
         struct ar9003_txs *ads;
+        u32 status;
 
         ads = &ah->ts_ring[ah->ts_tail];
 
-        if ((ads->status8 & AR_TxDone) == 0)
+        status = ACCESS_ONCE(ads->status8);
+        if ((status & AR_TxDone) == 0)
                 return -EINPROGRESS;
 
         ah->ts_tail = (ah->ts_tail + 1) % ah->ts_size;
 
         if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) ||
             (MS(ads->ds_info, AR_TxRxDesc) != 1)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                          "Tx Descriptor error %x\n", ads->ds_info);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                        "Tx Descriptor error %x\n", ads->ds_info);
                 memset(ads, 0, sizeof(*ads));
                 return -EIO;
         }
 
+        if (status & AR_TxOpExceeded)
+                ts->ts_status |= ATH9K_TXERR_XTXOP;
+        ts->ts_rateindex = MS(status, AR_FinalTxIdx);
+        ts->ts_seqnum = MS(status, AR_SeqNum);
+        ts->tid = MS(status, AR_TxTid);
+
         ts->qid = MS(ads->ds_info, AR_TxQcuNum);
         ts->desc_id = MS(ads->status1, AR_TxDescId);
-        ts->ts_seqnum = MS(ads->status8, AR_SeqNum);
         ts->ts_tstamp = ads->status4;
         ts->ts_status = 0;
         ts->ts_flags  = 0;
 
-        if (ads->status3 & AR_ExcessiveRetries)
+        status = ACCESS_ONCE(ads->status2);
+        ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00);
+        ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01);
+        ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02);
+        if (status & AR_TxBaStatus) {
+                ts->ts_flags |= ATH9K_TX_BA;
+                ts->ba_low = ads->status5;
+                ts->ba_high = ads->status6;
+        }
+
+        status = ACCESS_ONCE(ads->status3);
+        if (status & AR_ExcessiveRetries)
                 ts->ts_status |= ATH9K_TXERR_XRETRY;
-        if (ads->status3 & AR_Filtered)
+        if (status & AR_Filtered)
                 ts->ts_status |= ATH9K_TXERR_FILT;
-        if (ads->status3 & AR_FIFOUnderrun) {
+        if (status & AR_FIFOUnderrun) {
                 ts->ts_status |= ATH9K_TXERR_FIFO;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status8 & AR_TxOpExceeded)
-                ts->ts_status |= ATH9K_TXERR_XTXOP;
-        if (ads->status3 & AR_TxTimerExpired)
+        if (status & AR_TxTimerExpired)
                 ts->ts_status |= ATH9K_TXERR_TIMER_EXPIRED;
-
-        if (ads->status3 & AR_DescCfgErr)
+        if (status & AR_DescCfgErr)
                 ts->ts_flags |= ATH9K_TX_DESC_CFG_ERR;
-        if (ads->status3 & AR_TxDataUnderrun) {
+        if (status & AR_TxDataUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DATA_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status3 & AR_TxDelimUnderrun) {
+        if (status & AR_TxDelimUnderrun) {
                 ts->ts_flags |= ATH9K_TX_DELIM_UNDERRUN;
                 ath9k_hw_updatetxtriglevel(ah, true);
         }
-        if (ads->status2 & AR_TxBaStatus) {
-                ts->ts_flags |= ATH9K_TX_BA;
-                ts->ba_low = ads->status5;
-                ts->ba_high = ads->status6;
-        }
+        ts->ts_shortretry = MS(status, AR_RTSFailCnt);
+        ts->ts_longretry = MS(status, AR_DataFailCnt);
+        ts->ts_virtcol = MS(status, AR_VirtRetryCnt);
 
-        ts->ts_rateindex = MS(ads->status8, AR_FinalTxIdx);
-
-        ts->ts_rssi = MS(ads->status7, AR_TxRSSICombined);
-        ts->ts_rssi_ctl0 = MS(ads->status2, AR_TxRSSIAnt00);
-        ts->ts_rssi_ctl1 = MS(ads->status2, AR_TxRSSIAnt01);
-        ts->ts_rssi_ctl2 = MS(ads->status2, AR_TxRSSIAnt02);
-        ts->ts_rssi_ext0 = MS(ads->status7, AR_TxRSSIAnt10);
-        ts->ts_rssi_ext1 = MS(ads->status7, AR_TxRSSIAnt11);
-        ts->ts_rssi_ext2 = MS(ads->status7, AR_TxRSSIAnt12);
-        ts->ts_shortretry = MS(ads->status3, AR_RTSFailCnt);
-        ts->ts_longretry = MS(ads->status3, AR_DataFailCnt);
-        ts->ts_virtcol = MS(ads->status3, AR_VirtRetryCnt);
-        ts->ts_antenna = 0;
-
-        ts->tid = MS(ads->status8, AR_TxTid);
+        status = ACCESS_ONCE(ads->status7);
+        ts->ts_rssi = MS(status, AR_TxRSSICombined);
+        ts->ts_rssi_ext0 = MS(status, AR_TxRSSIAnt10);
+        ts->ts_rssi_ext1 = MS(status, AR_TxRSSIAnt11);
+        ts->ts_rssi_ext2 = MS(status, AR_TxRSSIAnt12);
 
         memset(ads, 0, sizeof(*ads));
 
@@ -319,7 +322,6 @@ static void ar9003_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
         if (txpower > ah->txpower_limit)
                 txpower = ah->txpower_limit;
 
-        txpower += ah->txpower_indexoffset;
         if (txpower > 63)
                 txpower = 63;
 
@@ -407,12 +409,36 @@ static void ar9003_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
 static void ar9003_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
                                         u32 aggrLen)
 {
+#define FIRST_DESC_NDELIMS 60
         struct ar9003_txc *ads = (struct ar9003_txc *) ds;
 
         ads->ctl12 |= (AR_IsAggr | AR_MoreAggr);
 
-        ads->ctl17 &= ~AR_AggrLen;
-        ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+        if (ah->ent_mode & AR_ENT_OTP_MPSD) {
+                u32 ctl17, ndelim;
+                /*
+                 * Add delimiter when using RTS/CTS with aggregation
+                 * and non enterprise AR9003 card
+                 */
+                ctl17 = ads->ctl17;
+                ndelim = MS(ctl17, AR_PadDelim);
+
+                if (ndelim < FIRST_DESC_NDELIMS) {
+                        aggrLen += (FIRST_DESC_NDELIMS - ndelim) * 4;
+                        ndelim = FIRST_DESC_NDELIMS;
+                }
+
+                ctl17 &= ~AR_AggrLen;
+                ctl17 |= SM(aggrLen, AR_AggrLen);
+
+                ctl17 &= ~AR_PadDelim;
+                ctl17 |= SM(ndelim, AR_PadDelim);
+
+                ads->ctl17 = ctl17;
+        } else {
+                ads->ctl17 &= ~AR_AggrLen;
+                ads->ctl17 |= SM(aggrLen, AR_AggrLen);
+        }
 }
 
 static void ar9003_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
@@ -587,9 +613,9 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
                  * possibly be reviewing the last subframe. AR_CRCErr
                  * is the CRC of the actual data.
                  */
-                if (rxsp->status11 & AR_CRCErr) {
+                if (rxsp->status11 & AR_CRCErr)
                         rxs->rs_status |= ATH9K_RXERR_CRC;
-                } else if (rxsp->status11 & AR_PHYErr) {
+                if (rxsp->status11 & AR_PHYErr) {
                         phyerr = MS(rxsp->status11, AR_PHYErrCode);
                         /*
                          * If we reach a point here where AR_PostDelimCRCErr is
@@ -612,11 +638,12 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs,
                                 rxs->rs_phyerr = phyerr;
                         }
 
-                } else if (rxsp->status11 & AR_DecryptCRCErr) {
+                }
+                if (rxsp->status11 & AR_DecryptCRCErr)
                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
-                } else if (rxsp->status11 & AR_MichaelErr) {
+                if (rxsp->status11 & AR_MichaelErr)
                         rxs->rs_status |= ATH9K_RXERR_MIC;
-                } else if (rxsp->status11 & AR_KeyMiss)
+                if (rxsp->status11 & AR_KeyMiss)
                         rxs->rs_status |= ATH9K_RXERR_DECRYPT;
         }
 
@@ -631,10 +658,10 @@ void ath9k_hw_reset_txstatus_ring(struct ath_hw *ah)
         memset((void *) ah->ts_ring, 0,
                 ah->ts_size * sizeof(struct ar9003_txs));
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                  "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
-                   ah->ts_paddr_start, ah->ts_paddr_end,
-                   ah->ts_ring, ah->ts_size);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                "TS Start 0x%x End 0x%x Virt %p, Size %d\n",
+                ah->ts_paddr_start, ah->ts_paddr_end,
+                ah->ts_ring, ah->ts_size);
 
         REG_WRITE(ah, AR_Q_STATUS_RING_START, ah->ts_paddr_start);
         REG_WRITE(ah, AR_Q_STATUS_RING_END, ah->ts_paddr_end);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
index 9f2cea70a840..45cc7e80436c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h
@@ -65,7 +65,7 @@ struct ar9003_rxs {
         u32 status9;
         u32 status10;
         u32 status11;
-} __packed;
+} __packed __aligned(4);
 
 /* Transmit Control Descriptor */
 struct ar9003_txc {
@@ -93,7 +93,7 @@ struct ar9003_txc {
         u32 ctl21;  /* DMA control 21 */
         u32 ctl22;  /* DMA control 22 */
         u32 pad[9]; /* pad to cache line (128 bytes/32 dwords) */
-} __packed;
+} __packed __aligned(4);
 
 struct ar9003_txs {
         u32 ds_info;
@@ -105,7 +105,7 @@ struct ar9003_txs {
         u32 status6;
         u32 status7;
         u32 status8;
-} __packed;
+} __packed __aligned(4);
 
 void ar9003_hw_attach_mac_ops(struct ath_hw *hw);
 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
index 716db414c258..356d2fd78822 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c
@@ -19,45 +19,124 @@
 
 void ar9003_paprd_enable(struct ath_hw *ah, bool val)
 {
+        struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
+        struct ath9k_channel *chan = ah->curchan;
+
+        if (val) {
+                ah->paprd_table_write_done = true;
+
+                ah->eep_ops->set_txpower(ah, chan,
+                                ath9k_regd_get_ctl(regulatory, chan),
+                                chan->chan->max_antenna_gain * 2,
+                                chan->chan->max_power * 2,
+                                min((u32) MAX_RATE_POWER,
+                                (u32) regulatory->power_limit), false);
+        }
+
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B0,
                       AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
-                      AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
-                      AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B1,
+                              AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL0_B2,
+                              AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE, !!val);
 }
 EXPORT_SYMBOL(ar9003_paprd_enable);
 
-static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
+static int ar9003_get_training_power_2g(struct ath_hw *ah)
+{
+        struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+        struct ar9300_modal_eep_header *hdr = &eep->modalHeader2G;
+        unsigned int power, scale, delta;
+
+        scale = MS(le32_to_cpu(hdr->papdRateMaskHt20), AR9300_PAPRD_SCALE_1);
+        power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
+                               AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
+
+        delta = abs((int) ah->paprd_target_power - (int) power);
+        if (delta > scale)
+                return -1;
+
+        if (delta < 4)
+                power -= 4 - delta;
+
+        return power;
+}
+
+static int ar9003_get_training_power_5g(struct ath_hw *ah)
 {
+        struct ath_common *common = ath9k_hw_common(ah);
         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
-        struct ar9300_modal_eep_header *hdr;
-        const u32 ctrl0[3] = {
+        struct ar9300_modal_eep_header *hdr = &eep->modalHeader5G;
+        struct ath9k_channel *chan = ah->curchan;
+        unsigned int power, scale, delta;
+
+        if (chan->channel >= 5700)
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt20),
+                           AR9300_PAPRD_SCALE_1);
+        else if (chan->channel >= 5400)
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
+                           AR9300_PAPRD_SCALE_2);
+        else
+                scale = MS(le32_to_cpu(hdr->papdRateMaskHt40),
+                           AR9300_PAPRD_SCALE_1);
+
+        if (IS_CHAN_HT40(chan))
+                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE8,
+                        AR_PHY_POWERTX_RATE8_POWERTXHT40_5);
+        else
+                power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE6,
+                        AR_PHY_POWERTX_RATE6_POWERTXHT20_5);
+
+        power += scale;
+        delta = abs((int) ah->paprd_target_power - (int) power);
+        if (delta > scale)
+                return -1;
+
+        power += 2 * get_streams(common->tx_chainmask);
+        return power;
+}
+
+static int ar9003_paprd_setup_single_table(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+        static const u32 ctrl0[3] = {
                 AR_PHY_PAPRD_CTRL0_B0,
                 AR_PHY_PAPRD_CTRL0_B1,
                 AR_PHY_PAPRD_CTRL0_B2
         };
-        const u32 ctrl1[3] = {
+        static const u32 ctrl1[3] = {
                 AR_PHY_PAPRD_CTRL1_B0,
                 AR_PHY_PAPRD_CTRL1_B1,
                 AR_PHY_PAPRD_CTRL1_B2
         };
-        u32 am_mask, ht40_mask;
+        int training_power;
         int i;
 
-        if (ah->curchan && IS_CHAN_5GHZ(ah->curchan))
-                hdr = &eep->modalHeader5G;
+        if (IS_CHAN_2GHZ(ah->curchan))
+                training_power = ar9003_get_training_power_2g(ah);
         else
-                hdr = &eep->modalHeader2G;
-
-        am_mask = le32_to_cpu(hdr->papdRateMaskHt20);
-        ht40_mask = le32_to_cpu(hdr->papdRateMaskHt40);
+                training_power = ar9003_get_training_power_5g(ah);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK, am_mask);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK, am_mask);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK, ht40_mask);
-
-        for (i = 0; i < 3; i++) {
+        if (training_power < 0) {
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "PAPRD target power delta out of range");
+                return -ERANGE;
+        }
+        ah->paprd_training_power = training_power;
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "Training power: %d, Target power: %d\n",
+                ah->paprd_training_power, ah->paprd_target_power);
+
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
+                      ah->paprd_ratemask);
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
+                      ah->paprd_ratemask);
+        REG_RMW_FIELD(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
+                      ah->paprd_ratemask_ht40);
+
+        for (i = 0; i < ah->caps.max_txchains; i++) {
                 REG_RMW_FIELD(ah, ctrl0[i],
                               AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK, 1);
                 REG_RMW_FIELD(ah, ctrl1[i],
@@ -102,8 +181,14 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES, 7);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL, 1);
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
-                      AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP, -6);
+        if (AR_SREV_9485(ah))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+                              AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+                              -3);
+        else
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
+                              AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP,
+                              -6);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
                       AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE,
                       -15);
@@ -132,6 +217,7 @@ static void ar9003_paprd_setup_single_table(struct ath_hw *ah)
                       AR_PHY_PAPRD_PRE_POST_SCALING, 185706);
         REG_RMW_FIELD(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
                       AR_PHY_PAPRD_PRE_POST_SCALING, 175487);
+        return 0;
 }
 
 static void ar9003_paprd_get_gain_table(struct ath_hw *ah)
@@ -586,15 +672,10 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
 {
         u32 *paprd_table_val = caldata->pa_table[chain];
         u32 small_signal_gain = caldata->small_signal_gain[chain];
-        u32 training_power;
+        u32 training_power = ah->paprd_training_power;
         u32 reg = 0;
         int i;
 
-        training_power =
-            REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
-                           AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
-        training_power -= 4;
-
         if (chain == 0)
                 reg = AR_PHY_PAPRD_MEM_TAB_B0;
         else if (chain == 1)
@@ -620,26 +701,22 @@ void ar9003_paprd_populate_single_table(struct ath_hw *ah,
                       AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
                       training_power);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
-                      AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
-                      training_power);
+        if (ah->caps.tx_chainmask & BIT(1))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B1,
+                              AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
+                              training_power);
 
-        REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
-                      AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
-                      training_power);
+        if (ah->caps.tx_chainmask & BIT(2))
+                REG_RMW_FIELD(ah, AR_PHY_PAPRD_CTRL1_B2,
+                              AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL,
+                              training_power);
 }
 EXPORT_SYMBOL(ar9003_paprd_populate_single_table);
 
 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain)
 {
-
         unsigned int i, desired_gain, gain_index;
-        unsigned int train_power;
-
-        train_power = REG_READ_FIELD(ah, AR_PHY_POWERTX_RATE5,
-                                     AR_PHY_POWERTX_RATE5_POWERTXHT20_0);
-
-        train_power = train_power - 4;
+        unsigned int train_power = ah->paprd_training_power;
 
         desired_gain = ar9003_get_desired_gain(ah, chain, train_power);
 
@@ -705,7 +782,12 @@ EXPORT_SYMBOL(ar9003_paprd_create_curve);
 
 int ar9003_paprd_init_table(struct ath_hw *ah)
 {
-        ar9003_paprd_setup_single_table(ah);
+        int ret;
+
+        ret = ar9003_paprd_setup_single_table(ah);
+        if (ret < 0)
+            return ret;
+
         ar9003_paprd_get_gain_table(ah);
         return 0;
 }
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 669b777729b3..8d60f4f09acc 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -75,7 +75,10 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
         freq = centers.synth_center;
 
         if (freq < 4800) {     /* 2 GHz, fractional mode */
-                channelSel = CHANSEL_2G(freq);
+                if (AR_SREV_9485(ah))
+                        channelSel = CHANSEL_2G_9485(freq);
+                else
+                        channelSel = CHANSEL_2G(freq);
                 /* Set to 2G mode */
                 bMode = 1;
         } else {
@@ -128,24 +131,53 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
                                             struct ath9k_channel *chan)
 {
-        u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
+        static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
         int cur_bb_spur, negative = 0, cck_spur_freq;
         int i;
+        int range, max_spur_cnts, synth_freq;
+        u8 *spur_fbin_ptr = NULL;
 
         /*
          * Need to verify range +/- 10 MHz in control channel, otherwise spur
          * is out-of-band and can be ignored.
          */
 
-        for (i = 0; i < 4; i++) {
+        if (AR_SREV_9485(ah)) {
+                spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah,
+                                                         IS_CHAN_2GHZ(chan));
+                if (spur_fbin_ptr[0] == 0) /* No spur */
+                        return;
+                max_spur_cnts = 5;
+                if (IS_CHAN_HT40(chan)) {
+                        range = 19;
+                        if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
+                                           AR_PHY_GC_DYN2040_PRI_CH) == 0)
+                                synth_freq = chan->channel + 10;
+                        else
+                                synth_freq = chan->channel - 10;
+                } else {
+                        range = 10;
+                        synth_freq = chan->channel;
+                }
+        } else {
+                range = 10;
+                max_spur_cnts = 4;
+                synth_freq = chan->channel;
+        }
+
+        for (i = 0; i < max_spur_cnts; i++) {
                 negative = 0;
-                cur_bb_spur = spur_freq[i] - chan->channel;
+                if (AR_SREV_9485(ah))
+                        cur_bb_spur = FBIN2FREQ(spur_fbin_ptr[i],
+                                        IS_CHAN_2GHZ(chan)) - synth_freq;
+                else
+                        cur_bb_spur = spur_freq[i] - synth_freq;
 
                 if (cur_bb_spur < 0) {
                         negative = 1;
                         cur_bb_spur = -cur_bb_spur;
                 }
-                if (cur_bb_spur < 10) {
+                if (cur_bb_spur < range) {
                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 
                         if (negative == 1)
@@ -487,7 +519,11 @@ void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
                 break;
         }
 
-        REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+        if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
+                REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
+        else
+                REG_WRITE(ah, AR_SELFGEN_MASK, tx);
+
         if (tx == 0x5) {
                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
                             AR_PHY_SWAP_ALT_CHAIN);
@@ -542,10 +578,7 @@ static void ar9003_hw_prog_ini(struct ath_hw *ah,
                 u32 reg = INI_RA(iniArr, i, 0);
                 u32 val = INI_RA(iniArr, i, column);
 
-                if (reg >= 0x16000 && reg < 0x17000)
-                        ath9k_hw_analog_shift_regwrite(ah, reg, val);
-                else
-                        REG_WRITE(ah, reg, val);
+                REG_WRITE(ah, reg, val);
 
                 DO_DELAY(regWrites);
         }
@@ -614,7 +647,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), false);
 
         return 0;
 }
@@ -712,28 +745,6 @@ static void ar9003_hw_rfbus_done(struct ath_hw *ah)
         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 }
 
-/*
- * Set the interrupt and GPIO values so the ISR can disable RF
- * on a switch signal.  Assumes GPIO port and interrupt polarity
- * are set prior to call.
- */
-static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
-{
-        /* Connect rfsilent_bb_l to baseband */
-        REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
-                    AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
-        /* Set input mux for rfsilent_bb_l to GPIO #0 */
-        REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
-                    AR_GPIO_INPUT_MUX2_RFSILENT);
-
-        /*
-         * Configure the desired GPIO port for input and
-         * enable baseband rf silence.
-         */
-        ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
-        REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
-}
-
 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 {
         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
@@ -820,12 +831,12 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 
                 if (!on != aniState->ofdmWeakSigDetectOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: ofdm weak signal: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->ofdmWeakSigDetectOff ?
-                                        "on" : "off",
-                                  on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: ofdm weak signal: %s=>%s\n",
+                                chan->channel,
+                                !aniState->ofdmWeakSigDetectOff ?
+                                "on" : "off",
+                                on ? "on" : "off");
                         if (on)
                                 ah->stats.ast_ani_ofdmon++;
                         else
@@ -838,11 +849,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(firstep_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_FIRSTEP_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(firstep_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(firstep_table));
                         return false;
                 }
 
@@ -877,24 +886,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                               AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
 
                 if (level != aniState->firstepLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.firstep);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "firstep_low[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->firstepLevel,
-                                  level,
-                                  ATH9K_ANI_FIRSTEP_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.firstepLow);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value,
+                                aniState->iniDef.firstep);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->firstepLevel,
+                                level,
+                                ATH9K_ANI_FIRSTEP_LVL_NEW,
+                                value2,
+                                aniState->iniDef.firstepLow);
                         if (level > aniState->firstepLevel)
                                 ah->stats.ast_ani_stepup++;
                         else if (level < aniState->firstepLevel)
@@ -907,11 +914,9 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 u32 level = param;
 
                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
-                                  "out of range (%u > %u)\n",
-                                  level,
-                                  (unsigned) ARRAY_SIZE(cycpwrThr1_table));
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
+                                level, ARRAY_SIZE(cycpwrThr1_table));
                         return false;
                 }
                 /*
@@ -945,24 +950,22 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                               AR_PHY_EXT_CYCPWR_THR1, value2);
 
                 if (level != aniState->spurImmunityLevel) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value,
-                                  aniState->iniDef.cycpwrThr1);
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: level %d=>%d[def:%d] "
-                                  "cycpwrThr1Ext[level]=%d ini=%d\n",
-                                  chan->channel,
-                                  aniState->spurImmunityLevel,
-                                  level,
-                                  ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
-                                  value2,
-                                  aniState->iniDef.cycpwrThr1Ext);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value,
+                                aniState->iniDef.cycpwrThr1);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
+                                chan->channel,
+                                aniState->spurImmunityLevel,
+                                level,
+                                ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
+                                value2,
+                                aniState->iniDef.cycpwrThr1Ext);
                         if (level > aniState->spurImmunityLevel)
                                 ah->stats.ast_ani_spurup++;
                         else if (level < aniState->spurImmunityLevel)
@@ -982,11 +985,11 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
                 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
                               AR_PHY_MRC_CCK_MUX_REG, is_on);
                 if (!is_on != aniState->mrcCCKOff) {
-                        ath_print(common, ATH_DBG_ANI,
-                                  "** ch %d: MRC CCK: %s=>%s\n",
-                                  chan->channel,
-                                  !aniState->mrcCCKOff ? "on" : "off",
-                                  is_on ? "on" : "off");
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "** ch %d: MRC CCK: %s=>%s\n",
+                                chan->channel,
+                                !aniState->mrcCCKOff ? "on" : "off",
+                                is_on ? "on" : "off");
                 if (is_on)
                         ah->stats.ast_ani_ccklow++;
                 else
@@ -998,22 +1001,19 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
         case ATH9K_ANI_PRESENT:
                 break;
         default:
-                ath_print(common, ATH_DBG_ANI,
-                          "invalid cmd %u\n", cmd);
+                ath_dbg(common, ATH_DBG_ANI, "invalid cmd %u\n", cmd);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                  "MRCcck=%s listenTime=%d "
-                  "ofdmErrs=%d cckErrs=%d\n",
-                  aniState->spurImmunityLevel,
-                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
-                  aniState->firstepLevel,
-                  !aniState->mrcCCKOff ? "on" : "off",
-                  aniState->listenTime,
-                  aniState->ofdmPhyErrCount,
-                  aniState->cckPhyErrCount);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
+                aniState->spurImmunityLevel,
+                !aniState->ofdmWeakSigDetectOff ? "on" : "off",
+                aniState->firstepLevel,
+                !aniState->mrcCCKOff ? "on" : "off",
+                aniState->listenTime,
+                aniState->ofdmPhyErrCount,
+                aniState->cckPhyErrCount);
         return true;
 }
 
@@ -1023,25 +1023,25 @@ static void ar9003_hw_do_getnf(struct ath_hw *ah,
         int16_t nf;
 
         nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
-        nfarray[0] = sign_extend(nf, 9);
+        nfarray[0] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
-        nfarray[1] = sign_extend(nf, 9);
+        nfarray[1] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
-        nfarray[2] = sign_extend(nf, 9);
+        nfarray[2] = sign_extend32(nf, 8);
 
         if (!IS_CHAN_HT40(ah->curchan))
                 return;
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-        nfarray[3] = sign_extend(nf, 9);
+        nfarray[3] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
-        nfarray[4] = sign_extend(nf, 9);
+        nfarray[4] = sign_extend32(nf, 8);
 
         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
-        nfarray[5] = sign_extend(nf, 9);
+        nfarray[5] = sign_extend32(nf, 8);
 }
 
 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
@@ -1070,13 +1070,13 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
         aniState = &ah->curchan->ani;
         iniDef = &aniState->iniDef;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
-                  ah->hw_version.macVersion,
-                  ah->hw_version.macRev,
-                  ah->opmode,
-                  chan->channel,
-                  chan->channelFlags);
+        ath_dbg(common, ATH_DBG_ANI,
+                "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
+                ah->hw_version.macVersion,
+                ah->hw_version.macRev,
+                ah->opmode,
+                chan->channel,
+                chan->channelFlags);
 
         val = REG_READ(ah, AR_PHY_SFCORR);
         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
@@ -1113,10 +1113,55 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
         aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
 }
 
+static void ar9003_hw_set_radar_params(struct ath_hw *ah,
+                                       struct ath_hw_radar_conf *conf)
+{
+        u32 radar_0 = 0, radar_1 = 0;
+
+        if (!conf) {
+                REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+                return;
+        }
+
+        radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+        radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+        radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+        radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+        radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+        radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+        radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+        radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+        radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+        radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+        radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+        REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+        REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+        if (conf->ext_channel)
+                REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+        else
+                REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
+{
+        struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+        conf->fir_power = -28;
+        conf->radar_rssi = 0;
+        conf->pulse_height = 10;
+        conf->pulse_rssi = 24;
+        conf->pulse_inband = 8;
+        conf->pulse_maxlen = 255;
+        conf->pulse_inband_step = 12;
+        conf->radar_inband = 8;
+}
+
 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 {
         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-        const u32 ar9300_cca_regs[6] = {
+        static const u32 ar9300_cca_regs[6] = {
                 AR_PHY_CCA_0,
                 AR_PHY_CCA_1,
                 AR_PHY_CCA_2,
@@ -1136,13 +1181,14 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
-        priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
         priv_ops->set_diversity = ar9003_hw_set_diversity;
         priv_ops->ani_control = ar9003_hw_ani_control;
         priv_ops->do_getnf = ar9003_hw_do_getnf;
         priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
+        priv_ops->set_radar_params = ar9003_hw_set_radar_params;
 
         ar9003_hw_set_nf_limits(ah);
+        ar9003_hw_set_radar_conf(ah);
         memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
 }
 
@@ -1165,7 +1211,7 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
                           ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
                             AR_PHY_WATCHDOG_IDLE_ENABLE));
 
-                ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
+                ath_dbg(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
                 return;
         }
 
@@ -1201,9 +1247,9 @@ void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
                   AR_PHY_WATCHDOG_IDLE_MASK |
                   (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
 
-        ath_print(common, ATH_DBG_RESET,
-                  "Enabled BB Watchdog timeout (%u ms)\n",
-                  idle_tmo_ms);
+        ath_dbg(common, ATH_DBG_RESET,
+                "Enabled BB Watchdog timeout (%u ms)\n",
+                idle_tmo_ms);
 }
 
 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
@@ -1231,37 +1277,35 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
                 return;
 
         status = ah->bb_watchdog_last_status;
-        ath_print(common, ATH_DBG_RESET,
-                  "\n==== BB update: BB status=0x%08x ====\n", status);
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
-                  "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
-                  MS(status, AR_PHY_WATCHDOG_INFO),
-                  MS(status, AR_PHY_WATCHDOG_DET_HANG),
-                  MS(status, AR_PHY_WATCHDOG_RADAR_SM),
-                  MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
-                  MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
-                  MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
-                  MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
-                  MS(status, AR_PHY_WATCHDOG_AGC_SM),
-                  MS(status,AR_PHY_WATCHDOG_SRCH_SM));
-
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
-                  REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
-                  REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
-        ath_print(common, ATH_DBG_RESET,
-                  "** BB mode: BB_gen_controls=0x%08x **\n",
-                  REG_READ(ah, AR_PHY_GEN_CTRL));
+        ath_dbg(common, ATH_DBG_RESET,
+                "\n==== BB update: BB status=0x%08x ====\n", status);
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
+                MS(status, AR_PHY_WATCHDOG_INFO),
+                MS(status, AR_PHY_WATCHDOG_DET_HANG),
+                MS(status, AR_PHY_WATCHDOG_RADAR_SM),
+                MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
+                MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
+                MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
+                MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
+                MS(status, AR_PHY_WATCHDOG_AGC_SM),
+                MS(status, AR_PHY_WATCHDOG_SRCH_SM));
+
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
+                REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
+                REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
+        ath_dbg(common, ATH_DBG_RESET,
+                "** BB mode: BB_gen_controls=0x%08x **\n",
+                REG_READ(ah, AR_PHY_GEN_CTRL));
 
 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
         if (common->cc_survey.cycles)
-                ath_print(common, ATH_DBG_RESET,
-                          "** BB busy times: rx_clear=%d%%, "
-                          "rx_frame=%d%%, tx_frame=%d%% **\n",
-                          PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
+                ath_dbg(common, ATH_DBG_RESET,
+                        "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
+                        PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
 
-        ath_print(common, ATH_DBG_RESET,
-                  "==== BB update: done ====\n\n");
+        ath_dbg(common, ATH_DBG_RESET,
+                "==== BB update: done ====\n\n");
 }
 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
index 3394dfe52b42..59bab6bd8a74 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
@@ -260,7 +260,13 @@
 #define AR_PHY_CCA_0            (AR_AGC_BASE + 0x1c)
 #define AR_PHY_EXT_CCA0         (AR_AGC_BASE + 0x20)
 #define AR_PHY_RESTART          (AR_AGC_BASE + 0x24)
+
 #define AR_PHY_MC_GAIN_CTRL     (AR_AGC_BASE + 0x28)
+#define AR_ANT_DIV_CTRL_ALL     0x7e000000
+#define AR_ANT_DIV_CTRL_ALL_S   25
+#define AR_ANT_DIV_ENABLE       0x1000000
+#define AR_ANT_DIV_ENABLE_S     24
+
 #define AR_PHY_EXTCHN_PWRTHR1   (AR_AGC_BASE + 0x2c)
 #define AR_PHY_EXT_CHN_WIN      (AR_AGC_BASE + 0x30)
 #define AR_PHY_20_40_DET_THR    (AR_AGC_BASE + 0x34)
@@ -271,7 +277,11 @@
 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
 #define AR_PHY_RSSI_0           (AR_AGC_BASE + 0x180)
 #define AR_PHY_SPUR_CCK_REP0    (AR_AGC_BASE + 0x184)
+
 #define AR_PHY_CCK_DETECT       (AR_AGC_BASE + 0x1c0)
+#define AR_FAST_DIV_ENABLE      0x2000
+#define AR_FAST_DIV_ENABLE_S    13
+
 #define AR_PHY_DAG_CTRLCCK      (AR_AGC_BASE + 0x1c4)
 #define AR_PHY_IQCORR_CTRL_CCK  (AR_AGC_BASE + 0x1c8)
 
@@ -536,10 +546,18 @@
 
 #define AR_PHY_TXGAIN_TABLE      (AR_SM_BASE + 0x300)
 
+#define AR_PHY_TX_IQCAL_START_9485              (AR_SM_BASE + 0x3c4)
+#define AR_PHY_TX_IQCAL_START_DO_CAL_9485       0x80000000
+#define AR_PHY_TX_IQCAL_START_DO_CAL_9485_S     31
+#define AR_PHY_TX_IQCAL_CONTROL_1_9485          (AR_SM_BASE + 0x3c8)
+#define AR_PHY_TX_IQCAL_STATUS_B0_9485          (AR_SM_BASE + 0x3f0)
+
 #define AR_PHY_TX_IQCAL_CONTROL_1   (AR_SM_BASE + 0x448)
 #define AR_PHY_TX_IQCAL_START       (AR_SM_BASE + 0x440)
 #define AR_PHY_TX_IQCAL_STATUS_B0   (AR_SM_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B0    (AR_SM_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B0(_i)    (AR_SM_BASE + \
+                                             (AR_SREV_9485(ah) ? \
+                                              0x3d0 : 0x450) + ((_i) << 2))
 
 #define AR_PHY_WATCHDOG_STATUS      (AR_SM_BASE + 0x5c0)
 #define AR_PHY_WATCHDOG_CTL_1       (AR_SM_BASE + 0x5c4)
@@ -568,7 +586,7 @@
 #define AR_PHY_65NM_CH0_BIAS2       0x160c4
 #define AR_PHY_65NM_CH0_BIAS4       0x160cc
 #define AR_PHY_65NM_CH0_RXTX4       0x1610c
-#define AR_PHY_65NM_CH0_THERM       0x16290
+#define AR_PHY_65NM_CH0_THERM       (AR_SREV_9485(ah) ? 0x1628c : 0x16290)
 
 #define AR_PHY_65NM_CH0_THERM_LOCAL   0x80000000
 #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31
@@ -584,6 +602,24 @@
 #define AR_PHY_65NM_CH2_RXTX1       0x16900
 #define AR_PHY_65NM_CH2_RXTX2       0x16904
 
+#define AR_CH0_TOP2 (AR_SREV_9485(ah) ? 0x00016284 : 0x0001628c)
+#define AR_CH0_TOP2_XPABIASLVL          0xf000
+#define AR_CH0_TOP2_XPABIASLVL_S        12
+
+#define AR_CH0_XTAL             (AR_SREV_9485(ah) ? 0x16290 : 0x16294)
+#define AR_CH0_XTAL_CAPINDAC    0x7f000000
+#define AR_CH0_XTAL_CAPINDAC_S  24
+#define AR_CH0_XTAL_CAPOUTDAC   0x00fe0000
+#define AR_CH0_XTAL_CAPOUTDAC_S 17
+
+#define AR_PHY_PMU1             0x16c40
+#define AR_PHY_PMU1_PWD         0x1
+#define AR_PHY_PMU1_PWD_S       0
+
+#define AR_PHY_PMU2             0x16c44
+#define AR_PHY_PMU2_PGM         0x00200000
+#define AR_PHY_PMU2_PGM_S       21
+
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT          0x00380000
 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT_S        19
 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT          0x00c00000
@@ -683,6 +719,7 @@
 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN_S 1
 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN    0x00000001
 #define AR_PHY_TXGAIN_FORCE               0x00000001
+#define AR_PHY_TXGAIN_FORCE_S             0
 #define AR_PHY_TXGAIN_FORCED_PADVGNRA     0x00003c00
 #define AR_PHY_TXGAIN_FORCED_PADVGNRA_S   10
 #define AR_PHY_TXGAIN_FORCED_PADVGNRB     0x0003c000
@@ -725,8 +762,13 @@
 #define AR_PHY_TX_IQCAL_START_DO_CAL_S      0
 
 #define AR_PHY_TX_IQCAL_STATUS_FAILED    0x00000001
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x00003fff
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    0
+#define AR_PHY_CALIBRATED_GAINS_0        0x3e
+#define AR_PHY_CALIBRATED_GAINS_0_S      1
+
+#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE      0x00003fff
+#define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S    0
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE      0x0fffc000
+#define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE_S    14
 
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON          0x10000000
 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S        28
@@ -785,7 +827,7 @@
 #define AR_PHY_TPC_11_B1         (AR_SM1_BASE + 0x220)
 #define AR_PHY_PDADC_TAB_1       (AR_SM1_BASE + 0x240)
 #define AR_PHY_TX_IQCAL_STATUS_B1   (AR_SM1_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B1    (AR_SM1_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i)    (AR_SM_BASE + 0x450 + ((_i) << 2))
 
 /*
  * Channel 2 Register Map
@@ -838,7 +880,7 @@
 #define AR_PHY_TPC_11_B2         (AR_SM2_BASE + 0x220)
 #define AR_PHY_PDADC_TAB_2       (AR_SM2_BASE + 0x240)
 #define AR_PHY_TX_IQCAL_STATUS_B2   (AR_SM2_BASE + 0x48c)
-#define AR_PHY_TX_IQCAL_CORR_COEFF_01_B2    (AR_SM2_BASE + 0x450)
+#define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i)    (AR_SM2_BASE + 0x450 + ((_i) << 2))
 
 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED    0x00000001
 
@@ -945,7 +987,9 @@
 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT         0x0ffe0000
 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT_S       17
 
-#define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + 0x490)
+#define AR_PHY_PAPRD_TRAINER_CNTL1                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x580 : 0x490))
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE     0x00000001
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S   0
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING       0x0000007e
@@ -961,11 +1005,15 @@
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP             0x0003f000
 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_S           12
 
-#define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + 0x494)
+#define AR_PHY_PAPRD_TRAINER_CNTL2                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x584 : 0x494))
 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN     0xFFFFFFFF
 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S   0
 
-#define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + 0x498)
+#define AR_PHY_PAPRD_TRAINER_CNTL3                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x588 : 0x498))
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE    0x0000003f
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S  0
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP          0x00000fc0
@@ -981,7 +1029,9 @@
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE     0x20000000
 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_S   29
 
-#define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + 0x49c)
+#define AR_PHY_PAPRD_TRAINER_CNTL4                              (AR_SM_BASE + \
+                                                                 (AR_SREV_9485(ah) ? \
+                                                                  0x58c : 0x49c))
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES   0x03ff0000
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_S 16
 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA        0x0000f000
@@ -1040,6 +1090,14 @@
 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0      0x3F
 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S    0
 
+#define AR_PHY_POWERTX_RATE6                    (AR_SM_BASE + 0x1d4)
+#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5      0x3F00
+#define AR_PHY_POWERTX_RATE6_POWERTXHT20_5_S    8
+
+#define AR_PHY_POWERTX_RATE8                    (AR_SM_BASE + 0x1dc)
+#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5      0x3F00
+#define AR_PHY_POWERTX_RATE8_POWERTXHT40_5_S    8
+
 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
 
 #endif  /* AR9003_PHY_H */
diff --git a/drivers/net/wireless/ath/ath9k/ar9485_initvals.h b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
new file mode 100644
index 000000000000..70de3d89a7b5
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9485_initvals.h
@@ -0,0 +1,943 @@
+/*
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef INITVALS_9485_H
+#define INITVALS_9485_H
+
+static const u32 ar9485Common_1_0[][2] = {
+        /*   Addr     allmodes */
+        {0x00007010, 0x00000022},
+        {0x00007020, 0x00000000},
+        {0x00007034, 0x00000002},
+        {0x00007038, 0x000004c2},
+};
+
+static const u32 ar9485_1_0_mac_postamble[][5] = {
+        /* Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20    */
+        {0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
+        {0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
+        {0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38},
+        {0x00008014, 0x03e803e8, 0x07d007d0, 0x10801600, 0x08400b00},
+        {0x0000801c, 0x128d8027, 0x128d804f, 0x12e00057, 0x12e0002b},
+        {0x00008120, 0x08f04800, 0x08f04800, 0x08f04810, 0x08f04810},
+        {0x000081d0, 0x00003210, 0x00003210, 0x0000320a, 0x0000320a},
+        {0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
+};
+
+static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
+        /*   Addr     allmodes */
+        {0x00018c00, 0x10212e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000580c},
+};
+
+static const u32 ar9485Common_wo_xlna_rx_gain_1_0[][2] = {
+        /*   Addr     allmodes */
+        {0x0000a000, 0x00010000},
+        {0x0000a004, 0x00030002},
+        {0x0000a008, 0x00050004},
+        {0x0000a00c, 0x00810080},
+        {0x0000a010, 0x01800082},
+        {0x0000a014, 0x01820181},
+        {0x0000a018, 0x01840183},
+        {0x0000a01c, 0x01880185},
+        {0x0000a020, 0x018a0189},
+        {0x0000a024, 0x02850284},
+        {0x0000a028, 0x02890288},
+        {0x0000a02c, 0x03850384},
+        {0x0000a030, 0x03890388},
+        {0x0000a034, 0x038b038a},
+        {0x0000a038, 0x038d038c},
+        {0x0000a03c, 0x03910390},
+        {0x0000a040, 0x03930392},
+        {0x0000a044, 0x03950394},
+        {0x0000a048, 0x00000396},
+        {0x0000a04c, 0x00000000},
+        {0x0000a050, 0x00000000},
+        {0x0000a054, 0x00000000},
+        {0x0000a058, 0x00000000},
+        {0x0000a05c, 0x00000000},
+        {0x0000a060, 0x00000000},
+        {0x0000a064, 0x00000000},
+        {0x0000a068, 0x00000000},
+        {0x0000a06c, 0x00000000},
+        {0x0000a070, 0x00000000},
+        {0x0000a074, 0x00000000},
+        {0x0000a078, 0x00000000},
+        {0x0000a07c, 0x00000000},
+        {0x0000a080, 0x28282828},
+        {0x0000a084, 0x28282828},
+        {0x0000a088, 0x28282828},
+        {0x0000a08c, 0x28282828},
+        {0x0000a090, 0x28282828},
+        {0x0000a094, 0x21212128},
+        {0x0000a098, 0x171c1c1c},
+        {0x0000a09c, 0x02020212},
+        {0x0000a0a0, 0x00000202},
+        {0x0000a0a4, 0x00000000},
+        {0x0000a0a8, 0x00000000},
+        {0x0000a0ac, 0x00000000},
+        {0x0000a0b0, 0x00000000},
+        {0x0000a0b4, 0x00000000},
+        {0x0000a0b8, 0x00000000},
+        {0x0000a0bc, 0x00000000},
+        {0x0000a0c0, 0x001f0000},
+        {0x0000a0c4, 0x111f1100},
+        {0x0000a0c8, 0x111d111e},
+        {0x0000a0cc, 0x111b111c},
+        {0x0000a0d0, 0x22032204},
+        {0x0000a0d4, 0x22012202},
+        {0x0000a0d8, 0x221f2200},
+        {0x0000a0dc, 0x221d221e},
+        {0x0000a0e0, 0x33013302},
+        {0x0000a0e4, 0x331f3300},
+        {0x0000a0e8, 0x4402331e},
+        {0x0000a0ec, 0x44004401},
+        {0x0000a0f0, 0x441e441f},
+        {0x0000a0f4, 0x55015502},
+        {0x0000a0f8, 0x551f5500},
+        {0x0000a0fc, 0x6602551e},
+        {0x0000a100, 0x66006601},
+        {0x0000a104, 0x661e661f},
+        {0x0000a108, 0x7703661d},
+        {0x0000a10c, 0x77017702},
+        {0x0000a110, 0x00007700},
+        {0x0000a114, 0x00000000},
+        {0x0000a118, 0x00000000},
+        {0x0000a11c, 0x00000000},
+        {0x0000a120, 0x00000000},
+        {0x0000a124, 0x00000000},
+        {0x0000a128, 0x00000000},
+        {0x0000a12c, 0x00000000},
+        {0x0000a130, 0x00000000},
+        {0x0000a134, 0x00000000},
+        {0x0000a138, 0x00000000},
+        {0x0000a13c, 0x00000000},
+        {0x0000a140, 0x001f0000},
+        {0x0000a144, 0x111f1100},
+        {0x0000a148, 0x111d111e},
+        {0x0000a14c, 0x111b111c},
+        {0x0000a150, 0x22032204},
+        {0x0000a154, 0x22012202},
+        {0x0000a158, 0x221f2200},
+        {0x0000a15c, 0x221d221e},
+        {0x0000a160, 0x33013302},
+        {0x0000a164, 0x331f3300},
+        {0x0000a168, 0x4402331e},
+        {0x0000a16c, 0x44004401},
+        {0x0000a170, 0x441e441f},
+        {0x0000a174, 0x55015502},
+        {0x0000a178, 0x551f5500},
+        {0x0000a17c, 0x6602551e},
+        {0x0000a180, 0x66006601},
+        {0x0000a184, 0x661e661f},
+        {0x0000a188, 0x7703661d},
+        {0x0000a18c, 0x77017702},
+        {0x0000a190, 0x00007700},
+        {0x0000a194, 0x00000000},
+        {0x0000a198, 0x00000000},
+        {0x0000a19c, 0x00000000},
+        {0x0000a1a0, 0x00000000},
+        {0x0000a1a4, 0x00000000},
+        {0x0000a1a8, 0x00000000},
+        {0x0000a1ac, 0x00000000},
+        {0x0000a1b0, 0x00000000},
+        {0x0000a1b4, 0x00000000},
+        {0x0000a1b8, 0x00000000},
+        {0x0000a1bc, 0x00000000},
+        {0x0000a1c0, 0x00000000},
+        {0x0000a1c4, 0x00000000},
+        {0x0000a1c8, 0x00000000},
+        {0x0000a1cc, 0x00000000},
+        {0x0000a1d0, 0x00000000},
+        {0x0000a1d4, 0x00000000},
+        {0x0000a1d8, 0x00000000},
+        {0x0000a1dc, 0x00000000},
+        {0x0000a1e0, 0x00000000},
+        {0x0000a1e4, 0x00000000},
+        {0x0000a1e8, 0x00000000},
+        {0x0000a1ec, 0x00000000},
+        {0x0000a1f0, 0x00000396},
+        {0x0000a1f4, 0x00000396},
+        {0x0000a1f8, 0x00000396},
+        {0x0000a1fc, 0x00000296},
+};
+
+static const u32 ar9485Modes_high_power_tx_gain_1_0[][5] = {
+        /*   Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20 */
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+};
+
+static const u32 ar9485_1_0[][2] = {
+        /*  Addr      allmodes */
+        {0x0000a580, 0x00000000},
+        {0x0000a584, 0x00000000},
+        {0x0000a588, 0x00000000},
+        {0x0000a58c, 0x00000000},
+        {0x0000a590, 0x00000000},
+        {0x0000a594, 0x00000000},
+        {0x0000a598, 0x00000000},
+        {0x0000a59c, 0x00000000},
+        {0x0000a5a0, 0x00000000},
+        {0x0000a5a4, 0x00000000},
+        {0x0000a5a8, 0x00000000},
+        {0x0000a5ac, 0x00000000},
+        {0x0000a5b0, 0x00000000},
+        {0x0000a5b4, 0x00000000},
+        {0x0000a5b8, 0x00000000},
+        {0x0000a5bc, 0x00000000},
+};
+
+static const u32 ar9485_1_0_radio_core[][2] = {
+        /*   Addr     allmodes */
+        {0x00016000, 0x36db6db6},
+        {0x00016004, 0x6db6db40},
+        {0x00016008, 0x73800000},
+        {0x0001600c, 0x00000000},
+        {0x00016040, 0x7f80fff8},
+        {0x00016048, 0x6c92426e},
+        {0x0001604c, 0x000f0278},
+        {0x00016050, 0x6db6db6c},
+        {0x00016054, 0x6db60000},
+        {0x00016080, 0x00080000},
+        {0x00016084, 0x0e48048c},
+        {0x00016088, 0x14214514},
+        {0x0001608c, 0x119f081e},
+        {0x00016090, 0x24926490},
+        {0x00016098, 0xd28b3330},
+        {0x000160a0, 0xc2108ffe},
+        {0x000160a4, 0x812fc370},
+        {0x000160a8, 0x423c8000},
+        {0x000160b4, 0x92480040},
+        {0x000160c0, 0x006db6db},
+        {0x000160c4, 0x0186db60},
+        {0x000160c8, 0x6db6db6c},
+        {0x000160cc, 0x6de6fbe0},
+        {0x000160d0, 0xf7dfcf3c},
+        {0x00016100, 0x04cb0001},
+        {0x00016104, 0xfff80015},
+        {0x00016108, 0x00080010},
+        {0x00016144, 0x01884080},
+        {0x00016148, 0x00008040},
+        {0x00016180, 0x08453333},
+        {0x00016184, 0x18e82f01},
+        {0x00016188, 0x00000000},
+        {0x0001618c, 0x00000000},
+        {0x00016240, 0x08400000},
+        {0x00016244, 0x1bf90f00},
+        {0x00016248, 0x00000000},
+        {0x0001624c, 0x00000000},
+        {0x00016280, 0x01000015},
+        {0x00016284, 0x00d30000},
+        {0x00016288, 0x00318000},
+        {0x0001628c, 0x50000000},
+        {0x00016290, 0x4b96210f},
+        {0x00016380, 0x00000000},
+        {0x00016384, 0x00000000},
+        {0x00016388, 0x00800700},
+        {0x0001638c, 0x00800700},
+        {0x00016390, 0x00800700},
+        {0x00016394, 0x00000000},
+        {0x00016398, 0x00000000},
+        {0x0001639c, 0x00000000},
+        {0x000163a0, 0x00000001},
+        {0x000163a4, 0x00000001},
+        {0x000163a8, 0x00000000},
+        {0x000163ac, 0x00000000},
+        {0x000163b0, 0x00000000},
+        {0x000163b4, 0x00000000},
+        {0x000163b8, 0x00000000},
+        {0x000163bc, 0x00000000},
+        {0x000163c0, 0x000000a0},
+        {0x000163c4, 0x000c0000},
+        {0x000163c8, 0x14021402},
+        {0x000163cc, 0x00001402},
+        {0x000163d0, 0x00000000},
+        {0x000163d4, 0x00000000},
+        {0x00016c40, 0x1319c178},
+        {0x00016c44, 0x10000000},
+};
+
+static const u32 ar9485Modes_lowest_ob_db_tx_gain_1_0[][5] = {
+        /*  Addr       5G_HT20     5G_HT40     2G_HT40     2G_HT20 */
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+};
+
+static const u32 ar9485_1_0_baseband_core[][2] = {
+        /* Addr      allmodes  */
+        {0x00009800, 0xafe68e30},
+        {0x00009804, 0xfd14e000},
+        {0x00009808, 0x9c0a8f6b},
+        {0x0000980c, 0x04800000},
+        {0x00009814, 0x9280c00a},
+        {0x00009818, 0x00000000},
+        {0x0000981c, 0x00020028},
+        {0x00009834, 0x5f3ca3de},
+        {0x00009838, 0x0108ecff},
+        {0x0000983c, 0x14750600},
+        {0x00009880, 0x201fff00},
+        {0x00009884, 0x00001042},
+        {0x000098a4, 0x00200400},
+        {0x000098b0, 0x52440bbe},
+        {0x000098bc, 0x00000002},
+        {0x000098d0, 0x004b6a8e},
+        {0x000098d4, 0x00000820},
+        {0x000098dc, 0x00000000},
+        {0x000098f0, 0x00000000},
+        {0x000098f4, 0x00000000},
+        {0x00009c04, 0x00000000},
+        {0x00009c08, 0x03200000},
+        {0x00009c0c, 0x00000000},
+        {0x00009c10, 0x00000000},
+        {0x00009c14, 0x00046384},
+        {0x00009c18, 0x05b6b440},
+        {0x00009c1c, 0x00b6b440},
+        {0x00009d00, 0xc080a333},
+        {0x00009d04, 0x40206c10},
+        {0x00009d08, 0x009c4060},
+        {0x00009d0c, 0x1883800a},
+        {0x00009d10, 0x01834061},
+        {0x00009d14, 0x00c00400},
+        {0x00009d18, 0x00000000},
+        {0x00009d1c, 0x00000000},
+        {0x00009e08, 0x0038233c},
+        {0x00009e24, 0x990bb515},
+        {0x00009e28, 0x0a6f0000},
+        {0x00009e30, 0x06336f77},
+        {0x00009e34, 0x6af6532f},
+        {0x00009e38, 0x0cc80c00},
+        {0x00009e40, 0x0d261820},
+        {0x00009e4c, 0x00001004},
+        {0x00009e50, 0x00ff03f1},
+        {0x00009fc0, 0x80be4788},
+        {0x00009fc4, 0x0001efb5},
+        {0x00009fcc, 0x40000014},
+        {0x0000a20c, 0x00000000},
+        {0x0000a210, 0x00000000},
+        {0x0000a220, 0x00000000},
+        {0x0000a224, 0x00000000},
+        {0x0000a228, 0x10002310},
+        {0x0000a23c, 0x00000000},
+        {0x0000a244, 0x0c000000},
+        {0x0000a2a0, 0x00000001},
+        {0x0000a2c0, 0x00000001},
+        {0x0000a2c8, 0x00000000},
+        {0x0000a2cc, 0x18c43433},
+        {0x0000a2d4, 0x00000000},
+        {0x0000a2dc, 0x00000000},
+        {0x0000a2e0, 0x00000000},
+        {0x0000a2e4, 0x00000000},
+        {0x0000a2e8, 0x00000000},
+        {0x0000a2ec, 0x00000000},
+        {0x0000a2f0, 0x00000000},
+        {0x0000a2f4, 0x00000000},
+        {0x0000a2f8, 0x00000000},
+        {0x0000a344, 0x00000000},
+        {0x0000a34c, 0x00000000},
+        {0x0000a350, 0x0000a000},
+        {0x0000a364, 0x00000000},
+        {0x0000a370, 0x00000000},
+        {0x0000a390, 0x00000001},
+        {0x0000a394, 0x00000444},
+        {0x0000a398, 0x001f0e0f},
+        {0x0000a39c, 0x0075393f},
+        {0x0000a3a0, 0xb79f6427},
+        {0x0000a3a4, 0x00000000},
+        {0x0000a3a8, 0xaaaaaaaa},
+        {0x0000a3ac, 0x3c466478},
+        {0x0000a3c0, 0x20202020},
+        {0x0000a3c4, 0x22222220},
+        {0x0000a3c8, 0x20200020},
+        {0x0000a3cc, 0x20202020},
+        {0x0000a3d0, 0x20202020},
+        {0x0000a3d4, 0x20202020},
+        {0x0000a3d8, 0x20202020},
+        {0x0000a3dc, 0x20202020},
+        {0x0000a3e0, 0x20202020},
+        {0x0000a3e4, 0x20202020},
+        {0x0000a3e8, 0x20202020},
+        {0x0000a3ec, 0x20202020},
+        {0x0000a3f0, 0x00000000},
+        {0x0000a3f4, 0x00000006},
+        {0x0000a3f8, 0x0cdbd380},
+        {0x0000a3fc, 0x000f0f01},
+        {0x0000a400, 0x8fa91f01},
+        {0x0000a404, 0x00000000},
+        {0x0000a408, 0x0e79e5c6},
+        {0x0000a40c, 0x00820820},
+        {0x0000a414, 0x1ce739ce},
+        {0x0000a418, 0x2d0011ce},
+        {0x0000a41c, 0x1ce739ce},
+        {0x0000a420, 0x000001ce},
+        {0x0000a424, 0x1ce739ce},
+        {0x0000a428, 0x000001ce},
+        {0x0000a42c, 0x1ce739ce},
+        {0x0000a430, 0x1ce739ce},
+        {0x0000a434, 0x00000000},
+        {0x0000a438, 0x00001801},
+        {0x0000a43c, 0x00000000},
+        {0x0000a440, 0x00000000},
+        {0x0000a444, 0x00000000},
+        {0x0000a448, 0x04000000},
+        {0x0000a44c, 0x00000001},
+        {0x0000a450, 0x00010000},
+        {0x0000a458, 0x00000000},
+        {0x0000a5c4, 0x3fad9d74},
+        {0x0000a5c8, 0x0048060a},
+        {0x0000a5cc, 0x00000637},
+        {0x0000a760, 0x03020100},
+        {0x0000a764, 0x09080504},
+        {0x0000a768, 0x0d0c0b0a},
+        {0x0000a76c, 0x13121110},
+        {0x0000a770, 0x31301514},
+        {0x0000a774, 0x35343332},
+        {0x0000a778, 0x00000036},
+        {0x0000a780, 0x00000838},
+        {0x0000a7c0, 0x00000000},
+        {0x0000a7c4, 0xfffffffc},
+        {0x0000a7c8, 0x00000000},
+        {0x0000a7cc, 0x00000000},
+        {0x0000a7d0, 0x00000000},
+        {0x0000a7d4, 0x00000004},
+        {0x0000a7dc, 0x00000001},
+};
+
+static const u32 ar9485Modes_high_ob_db_tx_gain_1_0[][5] = {
+        /* Addr        5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+};
+
+static const u32 ar9485Common_rx_gain_1_0[][2] = {
+        /* Addr      allmodes  */
+        {0x0000a000, 0x00010000},
+        {0x0000a004, 0x00030002},
+        {0x0000a008, 0x00050004},
+        {0x0000a00c, 0x00810080},
+        {0x0000a010, 0x01800082},
+        {0x0000a014, 0x01820181},
+        {0x0000a018, 0x01840183},
+        {0x0000a01c, 0x01880185},
+        {0x0000a020, 0x018a0189},
+        {0x0000a024, 0x02850284},
+        {0x0000a028, 0x02890288},
+        {0x0000a02c, 0x03850384},
+        {0x0000a030, 0x03890388},
+        {0x0000a034, 0x038b038a},
+        {0x0000a038, 0x038d038c},
+        {0x0000a03c, 0x03910390},
+        {0x0000a040, 0x03930392},
+        {0x0000a044, 0x03950394},
+        {0x0000a048, 0x00000396},
+        {0x0000a04c, 0x00000000},
+        {0x0000a050, 0x00000000},
+        {0x0000a054, 0x00000000},
+        {0x0000a058, 0x00000000},
+        {0x0000a05c, 0x00000000},
+        {0x0000a060, 0x00000000},
+        {0x0000a064, 0x00000000},
+        {0x0000a068, 0x00000000},
+        {0x0000a06c, 0x00000000},
+        {0x0000a070, 0x00000000},
+        {0x0000a074, 0x00000000},
+        {0x0000a078, 0x00000000},
+        {0x0000a07c, 0x00000000},
+        {0x0000a080, 0x28282828},
+        {0x0000a084, 0x28282828},
+        {0x0000a088, 0x28282828},
+        {0x0000a08c, 0x28282828},
+        {0x0000a090, 0x28282828},
+        {0x0000a094, 0x21212128},
+        {0x0000a098, 0x171c1c1c},
+        {0x0000a09c, 0x02020212},
+        {0x0000a0a0, 0x00000202},
+        {0x0000a0a4, 0x00000000},
+        {0x0000a0a8, 0x00000000},
+        {0x0000a0ac, 0x00000000},
+        {0x0000a0b0, 0x00000000},
+        {0x0000a0b4, 0x00000000},
+        {0x0000a0b8, 0x00000000},
+        {0x0000a0bc, 0x00000000},
+        {0x0000a0c0, 0x001f0000},
+        {0x0000a0c4, 0x111f1100},
+        {0x0000a0c8, 0x111d111e},
+        {0x0000a0cc, 0x111b111c},
+        {0x0000a0d0, 0x22032204},
+        {0x0000a0d4, 0x22012202},
+        {0x0000a0d8, 0x221f2200},
+        {0x0000a0dc, 0x221d221e},
+        {0x0000a0e0, 0x33013302},
+        {0x0000a0e4, 0x331f3300},
+        {0x0000a0e8, 0x4402331e},
+        {0x0000a0ec, 0x44004401},
+        {0x0000a0f0, 0x441e441f},
+        {0x0000a0f4, 0x55015502},
+        {0x0000a0f8, 0x551f5500},
+        {0x0000a0fc, 0x6602551e},
+        {0x0000a100, 0x66006601},
+        {0x0000a104, 0x661e661f},
+        {0x0000a108, 0x7703661d},
+        {0x0000a10c, 0x77017702},
+        {0x0000a110, 0x00007700},
+        {0x0000a114, 0x00000000},
+        {0x0000a118, 0x00000000},
+        {0x0000a11c, 0x00000000},
+        {0x0000a120, 0x00000000},
+        {0x0000a124, 0x00000000},
+        {0x0000a128, 0x00000000},
+        {0x0000a12c, 0x00000000},
+        {0x0000a130, 0x00000000},
+        {0x0000a134, 0x00000000},
+        {0x0000a138, 0x00000000},
+        {0x0000a13c, 0x00000000},
+        {0x0000a140, 0x001f0000},
+        {0x0000a144, 0x111f1100},
+        {0x0000a148, 0x111d111e},
+        {0x0000a14c, 0x111b111c},
+        {0x0000a150, 0x22032204},
+        {0x0000a154, 0x22012202},
+        {0x0000a158, 0x221f2200},
+        {0x0000a15c, 0x221d221e},
+        {0x0000a160, 0x33013302},
+        {0x0000a164, 0x331f3300},
+        {0x0000a168, 0x4402331e},
+        {0x0000a16c, 0x44004401},
+        {0x0000a170, 0x441e441f},
+        {0x0000a174, 0x55015502},
+        {0x0000a178, 0x551f5500},
+        {0x0000a17c, 0x6602551e},
+        {0x0000a180, 0x66006601},
+        {0x0000a184, 0x661e661f},
+        {0x0000a188, 0x7703661d},
+        {0x0000a18c, 0x77017702},
+        {0x0000a190, 0x00007700},
+        {0x0000a194, 0x00000000},
+        {0x0000a198, 0x00000000},
+        {0x0000a19c, 0x00000000},
+        {0x0000a1a0, 0x00000000},
+        {0x0000a1a4, 0x00000000},
+        {0x0000a1a8, 0x00000000},
+        {0x0000a1ac, 0x00000000},
+        {0x0000a1b0, 0x00000000},
+        {0x0000a1b4, 0x00000000},
+        {0x0000a1b8, 0x00000000},
+        {0x0000a1bc, 0x00000000},
+        {0x0000a1c0, 0x00000000},
+        {0x0000a1c4, 0x00000000},
+        {0x0000a1c8, 0x00000000},
+        {0x0000a1cc, 0x00000000},
+        {0x0000a1d0, 0x00000000},
+        {0x0000a1d4, 0x00000000},
+        {0x0000a1d8, 0x00000000},
+        {0x0000a1dc, 0x00000000},
+        {0x0000a1e0, 0x00000000},
+        {0x0000a1e4, 0x00000000},
+        {0x0000a1e8, 0x00000000},
+        {0x0000a1ec, 0x00000000},
+        {0x0000a1f0, 0x00000396},
+        {0x0000a1f4, 0x00000396},
+        {0x0000a1f8, 0x00000396},
+        {0x0000a1fc, 0x00000296},
+};
+
+static const u32 ar9485_1_0_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
+        /*   Addr    allmodes  */
+        {0x00018c00, 0x10252e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000580c},
+};
+
+static const u32 ar9485_1_0_pcie_phy_clkreq_enable_L1[][2] = {
+        /*  Addr    allmodes   */
+        {0x00018c00, 0x10253e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000580c},
+};
+
+static const u32 ar9485_1_0_soc_preamble[][2] = {
+        /*   Addr     allmodes */
+        {0x000040a4, 0x00a0c9c9},
+        {0x00007048, 0x00000004},
+};
+
+static const u32 ar9485_fast_clock_1_0_baseband_postamble[][3] = {
+        /*   Addr      5G_HT20     5G_HT40 */
+        {0x00009e00, 0x03721821, 0x03721821},
+        {0x0000a230, 0x0000400b, 0x00004016},
+        {0x0000a254, 0x00000898, 0x00001130},
+};
+
+static const u32 ar9485_1_0_baseband_postamble[][5] = {
+        /* Addr        5G_HT20     5G_HT40     2G_HT40     2G_HT20 */
+        {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
+        {0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
+        {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
+        {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
+        {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
+        {0x00009830, 0x0000059c, 0x0000059c, 0x0000059c, 0x0000059c},
+        {0x00009c00, 0x00000044, 0x00000044, 0x00000044, 0x00000044},
+        {0x00009e00, 0x0372161e, 0x0372161e, 0x037216a0, 0x037216a0},
+        {0x00009e04, 0x00182020, 0x00182020, 0x00182020, 0x00182020},
+        {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
+        {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec80d2e, 0x7ec80d2e},
+        {0x00009e14, 0x31395d5e, 0x3139605e, 0x3139605e, 0x31395d5e},
+        {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
+        {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
+        {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
+        {0x00009e3c, 0xcf946220, 0xcf946220, 0xcf946222, 0xcf946222},
+        {0x00009e44, 0x02321e27, 0x02321e27, 0x02282324, 0x02282324},
+        {0x00009e48, 0x5030201a, 0x5030201a, 0x50302010, 0x50302010},
+        {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
+        {0x0000a204, 0x01303fc0, 0x01303fc4, 0x01303fc4, 0x01303fc0},
+        {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
+        {0x0000a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b},
+        {0x0000a234, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff},
+        {0x0000a238, 0xffb81018, 0xffb81018, 0xffb81018, 0xffb81018},
+        {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
+        {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
+        {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
+        {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01000e0e, 0x01000e0e},
+        {0x0000a260, 0x3a021501, 0x3a021501, 0x3a021501, 0x3a021501},
+        {0x0000a264, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e},
+        {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
+        {0x0000a284, 0x00000000, 0x00000000, 0x000002a0, 0x000002a0},
+        {0x0000a288, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a28c, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
+        {0x0000a2d0, 0x00071981, 0x00071981, 0x00071981, 0x00071982},
+        {0x0000a2d8, 0xf999a83a, 0xf999a83a, 0xf999a83a, 0xf999a83a},
+        {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+        {0x0000be04, 0x00802020, 0x00802020, 0x00802020, 0x00802020},
+        {0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
+};
+
+static const u32 ar9485Modes_low_ob_db_tx_gain_1_0[][5] = {
+        /*  Addr      5G_HT20    5G_HT40     2G_HT40     2G_HT20   */
+        {0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
+        {0x0000a500, 0x00022200, 0x00022200, 0x00000000, 0x00000000},
+        {0x0000a504, 0x05062002, 0x05062002, 0x04000002, 0x04000002},
+        {0x0000a508, 0x0c002e00, 0x0c002e00, 0x08000004, 0x08000004},
+        {0x0000a50c, 0x11062202, 0x11062202, 0x0d000200, 0x0d000200},
+        {0x0000a510, 0x17022e00, 0x17022e00, 0x11000202, 0x11000202},
+        {0x0000a514, 0x1d000ec2, 0x1d000ec2, 0x15000400, 0x15000400},
+        {0x0000a518, 0x25020ec0, 0x25020ec0, 0x19000402, 0x19000402},
+        {0x0000a51c, 0x2b020ec3, 0x2b020ec3, 0x1d000404, 0x1d000404},
+        {0x0000a520, 0x2f001f04, 0x2f001f04, 0x21000603, 0x21000603},
+        {0x0000a524, 0x35001fc4, 0x35001fc4, 0x25000605, 0x25000605},
+        {0x0000a528, 0x3c022f04, 0x3c022f04, 0x2a000a03, 0x2a000a03},
+        {0x0000a52c, 0x41023e85, 0x41023e85, 0x2c000a04, 0x2c000a04},
+        {0x0000a530, 0x48023ec6, 0x48023ec6, 0x2e000a20, 0x2e000a20},
+        {0x0000a534, 0x4d023f01, 0x4d023f01, 0x34000e20, 0x34000e20},
+        {0x0000a538, 0x53023f4b, 0x53023f4b, 0x38000e22, 0x38000e22},
+        {0x0000a53c, 0x5a027f09, 0x5a027f09, 0x3c000e24, 0x3c000e24},
+        {0x0000a540, 0x5f027fc9, 0x5f027fc9, 0x40000e26, 0x40000e26},
+        {0x0000a544, 0x6502feca, 0x6502feca, 0x43001640, 0x43001640},
+        {0x0000a548, 0x6b02ff4a, 0x6b02ff4a, 0x46001660, 0x46001660},
+        {0x0000a54c, 0x7203feca, 0x7203feca, 0x49001861, 0x49001861},
+        {0x0000a550, 0x7703ff0b, 0x7703ff0b, 0x4c001a81, 0x4c001a81},
+        {0x0000a554, 0x7d06ffcb, 0x7d06ffcb, 0x4f001a83, 0x4f001a83},
+        {0x0000a558, 0x8407ff0b, 0x8407ff0b, 0x54001c85, 0x54001c85},
+        {0x0000a55c, 0x8907ffcb, 0x8907ffcb, 0x58001ce5, 0x58001ce5},
+        {0x0000a560, 0x900fff0b, 0x900fff0b, 0x5b001ce9, 0x5b001ce9},
+        {0x0000a564, 0x960fffcb, 0x960fffcb, 0x60001eeb, 0x60001eeb},
+        {0x0000a568, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a56c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a570, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a574, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a578, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x0000a57c, 0x9c1fff0b, 0x9c1fff0b, 0x60001eeb, 0x60001eeb},
+        {0x00016044, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db, 0x05b6b2db},
+};
+
+static const u32 ar9485_1_0_pcie_phy_clkreq_disable_L1[][2] = {
+        /*   Addr     allmodes */
+        {0x00018c00, 0x10213e5e},
+        {0x00018c04, 0x000801d8},
+        {0x00018c08, 0x0000580c},
+};
+
+static const u32 ar9485_1_0_radio_postamble[][2] = {
+        /*   Addr     allmodes */
+        {0x0001609c, 0x0b283f31},
+        {0x000160ac, 0x24611800},
+        {0x000160b0, 0x03284f3e},
+        {0x0001610c, 0x00170000},
+        {0x00016140, 0x10804008},
+};
+
+static const u32 ar9485_1_0_mac_core[][2] = {
+        /*  Addr      allmodes */
+        {0x00000008, 0x00000000},
+        {0x00000030, 0x00020085},
+        {0x00000034, 0x00000005},
+        {0x00000040, 0x00000000},
+        {0x00000044, 0x00000000},
+        {0x00000048, 0x00000008},
+        {0x0000004c, 0x00000010},
+        {0x00000050, 0x00000000},
+        {0x00001040, 0x002ffc0f},
+        {0x00001044, 0x002ffc0f},
+        {0x00001048, 0x002ffc0f},
+        {0x0000104c, 0x002ffc0f},
+        {0x00001050, 0x002ffc0f},
+        {0x00001054, 0x002ffc0f},
+        {0x00001058, 0x002ffc0f},
+        {0x0000105c, 0x002ffc0f},
+        {0x00001060, 0x002ffc0f},
+        {0x00001064, 0x002ffc0f},
+        {0x000010f0, 0x00000100},
+        {0x00001270, 0x00000000},
+        {0x000012b0, 0x00000000},
+        {0x000012f0, 0x00000000},
+        {0x0000143c, 0x00000000},
+        {0x0000147c, 0x00000000},
+        {0x00008000, 0x00000000},
+        {0x00008004, 0x00000000},
+        {0x00008008, 0x00000000},
+        {0x0000800c, 0x00000000},
+        {0x00008018, 0x00000000},
+        {0x00008020, 0x00000000},
+        {0x00008038, 0x00000000},
+        {0x0000803c, 0x00000000},
+        {0x00008040, 0x00000000},
+        {0x00008044, 0x00000000},
+        {0x00008048, 0x00000000},
+        {0x0000804c, 0xffffffff},
+        {0x00008054, 0x00000000},
+        {0x00008058, 0x00000000},
+        {0x0000805c, 0x000fc78f},
+        {0x00008060, 0x0000000f},
+        {0x00008064, 0x00000000},
+        {0x00008070, 0x00000310},
+        {0x00008074, 0x00000020},
+        {0x00008078, 0x00000000},
+        {0x0000809c, 0x0000000f},
+        {0x000080a0, 0x00000000},
+        {0x000080a4, 0x02ff0000},
+        {0x000080a8, 0x0e070605},
+        {0x000080ac, 0x0000000d},
+        {0x000080b0, 0x00000000},
+        {0x000080b4, 0x00000000},
+        {0x000080b8, 0x00000000},
+        {0x000080bc, 0x00000000},
+        {0x000080c0, 0x2a800000},
+        {0x000080c4, 0x06900168},
+        {0x000080c8, 0x13881c20},
+        {0x000080cc, 0x01f40000},
+        {0x000080d0, 0x00252500},
+        {0x000080d4, 0x00a00000},
+        {0x000080d8, 0x00400000},
+        {0x000080dc, 0x00000000},
+        {0x000080e0, 0xffffffff},
+        {0x000080e4, 0x0000ffff},
+        {0x000080e8, 0x3f3f3f3f},
+        {0x000080ec, 0x00000000},
+        {0x000080f0, 0x00000000},
+        {0x000080f4, 0x00000000},
+        {0x000080fc, 0x00020000},
+        {0x00008100, 0x00000000},
+        {0x00008108, 0x00000052},
+        {0x0000810c, 0x00000000},
+        {0x00008110, 0x00000000},
+        {0x00008114, 0x000007ff},
+        {0x00008118, 0x000000aa},
+        {0x0000811c, 0x00003210},
+        {0x00008124, 0x00000000},
+        {0x00008128, 0x00000000},
+        {0x0000812c, 0x00000000},
+        {0x00008130, 0x00000000},
+        {0x00008134, 0x00000000},
+        {0x00008138, 0x00000000},
+        {0x0000813c, 0x0000ffff},
+        {0x00008144, 0xffffffff},
+        {0x00008168, 0x00000000},
+        {0x0000816c, 0x00000000},
+        {0x00008170, 0x18486200},
+        {0x00008174, 0x33332210},
+        {0x00008178, 0x00000000},
+        {0x0000817c, 0x00020000},
+        {0x000081c0, 0x00000000},
+        {0x000081c4, 0x33332210},
+        {0x000081c8, 0x00000000},
+        {0x000081cc, 0x00000000},
+        {0x000081d4, 0x00000000},
+        {0x000081ec, 0x00000000},
+        {0x000081f0, 0x00000000},
+        {0x000081f4, 0x00000000},
+        {0x000081f8, 0x00000000},
+        {0x000081fc, 0x00000000},
+        {0x00008240, 0x00100000},
+        {0x00008244, 0x0010f400},
+        {0x00008248, 0x00000800},
+        {0x0000824c, 0x0001e800},
+        {0x00008250, 0x00000000},
+        {0x00008254, 0x00000000},
+        {0x00008258, 0x00000000},
+        {0x0000825c, 0x40000000},
+        {0x00008260, 0x00080922},
+        {0x00008264, 0x9ca00010},
+        {0x00008268, 0xffffffff},
+        {0x0000826c, 0x0000ffff},
+        {0x00008270, 0x00000000},
+        {0x00008274, 0x40000000},
+        {0x00008278, 0x003e4180},
+        {0x0000827c, 0x00000004},
+        {0x00008284, 0x0000002c},
+        {0x00008288, 0x0000002c},
+        {0x0000828c, 0x000000ff},
+        {0x00008294, 0x00000000},
+        {0x00008298, 0x00000000},
+        {0x0000829c, 0x00000000},
+        {0x00008300, 0x00000140},
+        {0x00008314, 0x00000000},
+        {0x0000831c, 0x0000010d},
+        {0x00008328, 0x00000000},
+        {0x0000832c, 0x00000007},
+        {0x00008330, 0x00000302},
+        {0x00008334, 0x00000700},
+        {0x00008338, 0x00ff0000},
+        {0x0000833c, 0x02400000},
+        {0x00008340, 0x000107ff},
+        {0x00008344, 0xa248105b},
+        {0x00008348, 0x008f0000},
+        {0x0000835c, 0x00000000},
+        {0x00008360, 0xffffffff},
+        {0x00008364, 0xffffffff},
+        {0x00008368, 0x00000000},
+        {0x00008370, 0x00000000},
+        {0x00008374, 0x000000ff},
+        {0x00008378, 0x00000000},
+        {0x0000837c, 0x00000000},
+        {0x00008380, 0xffffffff},
+        {0x00008384, 0xffffffff},
+        {0x00008390, 0xffffffff},
+        {0x00008394, 0xffffffff},
+        {0x00008398, 0x00000000},
+        {0x0000839c, 0x00000000},
+        {0x000083a0, 0x00000000},
+        {0x000083a4, 0x0000fa14},
+        {0x000083a8, 0x000f0c00},
+        {0x000083ac, 0x33332210},
+        {0x000083b0, 0x33332210},
+        {0x000083b4, 0x33332210},
+        {0x000083b8, 0x33332210},
+        {0x000083bc, 0x00000000},
+        {0x000083c0, 0x00000000},
+        {0x000083c4, 0x00000000},
+        {0x000083c8, 0x00000000},
+        {0x000083cc, 0x00000200},
+        {0x000083d0, 0x000301ff},
+};
+#endif
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 0963071e8f90..3681caf54282 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -57,6 +57,8 @@ struct ath_node;
 
 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
 
+#define ATH9K_PM_QOS_DEFAULT_VALUE      55
+
 #define TSF_TO_TU(_h,_l) \
         ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
 
@@ -87,33 +89,19 @@ struct ath_config {
 /**
  * enum buffer_type - Buffer type flags
  *
- * @BUF_HT: Send this buffer using HT capabilities
  * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
  * @BUF_AGGR: Indicates whether the buffer can be aggregated
  *      (used in aggregation scheduling)
- * @BUF_RETRY: Indicates whether the buffer is retried
  * @BUF_XRETRY: To denote excessive retries of the buffer
  */
 enum buffer_type {
-        BUF_HT                  = BIT(1),
         BUF_AMPDU               = BIT(2),
         BUF_AGGR                = BIT(3),
-        BUF_RETRY               = BIT(4),
         BUF_XRETRY              = BIT(5),
 };
 
-#define bf_nframes              bf_state.bfs_nframes
-#define bf_al                   bf_state.bfs_al
-#define bf_frmlen               bf_state.bfs_frmlen
-#define bf_retries              bf_state.bfs_retries
-#define bf_seqno                bf_state.bfs_seqno
-#define bf_tidno                bf_state.bfs_tidno
-#define bf_keyix                bf_state.bfs_keyix
-#define bf_keytype              bf_state.bfs_keytype
-#define bf_isht(bf)             (bf->bf_state.bf_type & BUF_HT)
 #define bf_isampdu(bf)          (bf->bf_state.bf_type & BUF_AMPDU)
 #define bf_isaggr(bf)           (bf->bf_state.bf_type & BUF_AGGR)
-#define bf_isretried(bf)        (bf->bf_state.bf_type & BUF_RETRY)
 #define bf_isxretried(bf)       (bf->bf_state.bf_type & BUF_XRETRY)
 
 #define ATH_TXSTATUS_RING_SIZE 64
@@ -178,8 +166,8 @@ void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
 
 /* returns delimiter padding required given the packet length */
 #define ATH_AGGR_GET_NDELIM(_len)                                       \
-        (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ?           \
-          (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
+       (((_len) >= ATH_AGGR_MINPLEN) ? 0 :                             \
+        DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
 
 #define BAW_WITHIN(_start, _bawsz, _seqno) \
         ((((_seqno) - (_start)) & 4095) < (_bawsz))
@@ -196,12 +184,12 @@ enum ATH_AGGR_STATUS {
 
 #define ATH_TXFIFO_DEPTH 8
 struct ath_txq {
-        int axq_class;
         u32 axq_qnum;
         u32 *axq_link;
         struct list_head axq_q;
         spinlock_t axq_lock;
         u32 axq_depth;
+        u32 axq_ampdu_depth;
         bool stopped;
         bool axq_tx_inprogress;
         struct list_head axq_acq;
@@ -209,27 +197,28 @@ struct ath_txq {
         struct list_head txq_fifo_pending;
         u8 txq_headidx;
         u8 txq_tailidx;
+        int pending_frames;
 };
 
 struct ath_atx_ac {
+        struct ath_txq *txq;
         int sched;
-        int qnum;
         struct list_head list;
         struct list_head tid_q;
 };
 
+struct ath_frame_info {
+        int framelen;
+        u32 keyix;
+        enum ath9k_key_type keytype;
+        u8 retries;
+        u16 seqno;
+};
+
 struct ath_buf_state {
-        int bfs_nframes;
-        u16 bfs_al;
-        u16 bfs_frmlen;
-        int bfs_seqno;
-        int bfs_tidno;
-        int bfs_retries;
         u8 bf_type;
         u8 bfs_paprd;
-        unsigned long bfs_paprd_timestamp;
-        u32 bfs_keyix;
-        enum ath9k_key_type bfs_keytype;
+        enum ath9k_internal_frame_type bfs_ftype;
 };
 
 struct ath_buf {
@@ -242,7 +231,6 @@ struct ath_buf {
         dma_addr_t bf_daddr;            /* physical addr of desc */
         dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
         bool bf_stale;
-        bool bf_tx_aborted;
         u16 bf_flags;
         struct ath_buf_state bf_state;
         struct ath_wiphy *aphy;
@@ -271,7 +259,6 @@ struct ath_node {
         struct ath_atx_ac ac[WME_NUM_AC];
         u16 maxampdu;
         u8 mpdudensity;
-        int last_rssi;
 };
 
 #define AGGR_CLEANUP         BIT(1)
@@ -280,6 +267,7 @@ struct ath_node {
 
 struct ath_tx_control {
         struct ath_txq *txq;
+        struct ath_node *an;
         int if_id;
         enum ath9k_internal_frame_type frame_type;
         u8 paprd;
@@ -292,12 +280,11 @@ struct ath_tx_control {
 struct ath_tx {
         u16 seq_no;
         u32 txqsetup;
-        int hwq_map[WME_NUM_AC];
         spinlock_t txbuflock;
         struct list_head txbuf;
         struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
         struct ath_descdma txdma;
-        int pending_frames[WME_NUM_AC];
+        struct ath_txq *txq_map[WME_NUM_AC];
 };
 
 struct ath_rx_edma {
@@ -311,7 +298,6 @@ struct ath_rx {
         u8 rxotherant;
         u32 *rxlink;
         unsigned int rxfilter;
-        spinlock_t pcu_lock;
         spinlock_t rxbuflock;
         struct list_head rxbuf;
         struct ath_descdma rxdma;
@@ -328,7 +314,6 @@ void ath_rx_cleanup(struct ath_softc *sc);
 int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
-int ath_tx_setup(struct ath_softc *sc, int haltype);
 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
 void ath_draintxq(struct ath_softc *sc,
                      struct ath_txq *txq, bool retry_tx);
@@ -343,7 +328,6 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
                  struct ath_tx_control *txctl);
 void ath_tx_tasklet(struct ath_softc *sc);
 void ath_tx_edma_tasklet(struct ath_softc *sc);
-void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb);
 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                       u16 tid, u16 *ssn);
 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
@@ -564,6 +548,7 @@ struct ath_ant_comb {
 #define SC_OP_BT_PRIORITY_DETECTED   BIT(12)
 #define SC_OP_BT_SCAN                BIT(13)
 #define SC_OP_ANI_RUN                BIT(14)
+#define SC_OP_ENABLE_APM             BIT(15)
 
 /* Powersave flags */
 #define PS_WAIT_FOR_BEACON        BIT(0)
@@ -601,13 +586,14 @@ struct ath_softc {
         struct ath_hw *sc_ah;
         void __iomem *mem;
         int irq;
-        spinlock_t sc_resetlock;
         spinlock_t sc_serial_rw;
         spinlock_t sc_pm_lock;
+        spinlock_t sc_pcu_lock;
         struct mutex mutex;
         struct work_struct paprd_work;
         struct work_struct hw_check_work;
         struct completion paprd_complete;
+        bool paprd_pending;
 
         u32 intrstatus;
         u32 sc_flags; /* SC_OP_* */
@@ -665,11 +651,11 @@ struct ath_wiphy {
         bool idle;
         int chan_idx;
         int chan_is_ht;
+        int last_rssi;
 };
 
 void ath9k_tasklet(unsigned long data);
 int ath_reset(struct ath_softc *sc, bool retry_tx);
-int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
 int ath_cabq_update(struct ath_softc *);
 
 static inline void ath_read_cachesize(struct ath_common *common, int *csz)
@@ -678,17 +664,19 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
 }
 
 extern struct ieee80211_ops ath9k_ops;
-extern int modparam_nohwcrypt;
+extern int ath9k_modparam_nohwcrypt;
 extern int led_blink;
+extern int ath9k_pm_qos_value;
+extern bool is_ath9k_unloaded;
 
 irqreturn_t ath_isr(int irq, void *dev);
+void ath9k_init_crypto(struct ath_softc *sc);
 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
                     const struct ath_bus_ops *bus_ops);
 void ath9k_deinit_device(struct ath_softc *sc);
 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
                            struct ath9k_channel *ichan);
-void ath_update_chainmask(struct ath_softc *sc, int is_ht);
 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
                     struct ath9k_channel *hchan);
 
@@ -715,10 +703,12 @@ static inline void ath_ahb_exit(void) {};
 void ath9k_ps_wakeup(struct ath_softc *sc);
 void ath9k_ps_restore(struct ath_softc *sc);
 
+u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
+
 void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
 int ath9k_wiphy_add(struct ath_softc *sc);
 int ath9k_wiphy_del(struct ath_wiphy *aphy);
-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb);
+void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype);
 int ath9k_wiphy_pause(struct ath_wiphy *aphy);
 int ath9k_wiphy_unpause(struct ath_wiphy *aphy);
 int ath9k_wiphy_select(struct ath_wiphy *aphy);
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 19891e7d49ae..385ba03134ba 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -28,7 +28,7 @@ int ath_beaconq_config(struct ath_softc *sc)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info qi, qi_be;
-        int qnum;
+        struct ath_txq *txq;
 
         ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
@@ -38,16 +38,16 @@ int ath_beaconq_config(struct ath_softc *sc)
                 qi.tqi_cwmax = 0;
         } else {
                 /* Adhoc mode; important thing is to use 2x cwmin. */
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                ath9k_hw_get_txq_props(ah, qnum, &qi_be);
+                txq = sc->tx.txq_map[WME_AC_BE];
+                ath9k_hw_get_txq_props(ah, txq->axq_qnum, &qi_be);
                 qi.tqi_aifs = qi_be.tqi_aifs;
                 qi.tqi_cwmin = 4*qi_be.tqi_cwmin;
                 qi.tqi_cwmax = qi_be.tqi_cwmax;
         }
 
         if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to update h/w beacon queue parameters\n");
+                ath_err(common,
+                        "Unable to update h/w beacon queue parameters\n");
                 return 0;
         } else {
                 ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
@@ -103,12 +103,32 @@ static void ath_beacon_setup(struct ath_softc *sc, struct ath_vif *avp,
         memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
         series[0].Tries = 1;
         series[0].Rate = rate;
-        series[0].ChSel = common->tx_chainmask;
+        series[0].ChSel = ath_txchainmask_reduction(sc,
+                        common->tx_chainmask, series[0].Rate);
         series[0].RateFlags = (ctsrate) ? ATH9K_RATESERIES_RTS_CTS : 0;
         ath9k_hw_set11n_ratescenario(ah, ds, ds, 0, ctsrate, ctsduration,
                                      series, 4, 0);
 }
 
+static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct ath_wiphy *aphy = hw->priv;
+        struct ath_softc *sc = aphy->sc;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_tx_control txctl;
+
+        memset(&txctl, 0, sizeof(struct ath_tx_control));
+        txctl.txq = sc->beacon.cabq;
+
+        ath_dbg(common, ATH_DBG_XMIT,
+                "transmitting CABQ packet, skb: %p\n", skb);
+
+        if (ath_tx_start(hw, skb, &txctl) != 0) {
+                ath_dbg(common, ATH_DBG_XMIT, "CABQ TX failed\n");
+                dev_kfree_skb_any(skb);
+        }
+}
+
 static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
                                            struct ieee80211_vif *vif)
 {
@@ -169,8 +189,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
                 bf->bf_buf_addr = 0;
-                ath_print(common, ATH_DBG_FATAL,
-                          "dma_mapping_error on beaconing\n");
+                ath_err(common, "dma_mapping_error on beaconing\n");
                 return NULL;
         }
 
@@ -190,8 +209,8 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
 
         if (skb && cabq_depth) {
                 if (sc->nvifs > 1) {
-                        ath_print(common, ATH_DBG_BEACON,
-                                  "Flushing previous cabq traffic\n");
+                        ath_dbg(common, ATH_DBG_BEACON,
+                                "Flushing previous cabq traffic\n");
                         ath_draintxq(sc, cabq, false);
                 }
         }
@@ -263,7 +282,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
         /* NB: the beacon data buffer must be 32-bit aligned. */
         skb = ieee80211_beacon_get(sc->hw, vif);
         if (skb == NULL) {
-                ath_print(common, ATH_DBG_BEACON, "cannot get skb\n");
+                ath_dbg(common, ATH_DBG_BEACON, "cannot get skb\n");
                 return -ENOMEM;
         }
 
@@ -287,10 +306,9 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                 tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
                 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
 
-                ath_print(common, ATH_DBG_BEACON,
-                          "stagger beacons, bslot %d intval "
-                          "%u tsfadjust %llu\n",
-                          avp->av_bslot, intval, (unsigned long long)tsfadjust);
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
+                        avp->av_bslot, intval, (unsigned long long)tsfadjust);
 
                 ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
                         avp->tsf_adjust;
@@ -304,8 +322,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
                 dev_kfree_skb_any(skb);
                 bf->bf_mpdu = NULL;
                 bf->bf_buf_addr = 0;
-                ath_print(common, ATH_DBG_FATAL,
-                          "dma_mapping_error on beacon alloc\n");
+                ath_err(common, "dma_mapping_error on beacon alloc\n");
                 return -ENOMEM;
         }
 
@@ -362,13 +379,13 @@ void ath_beacon_tasklet(unsigned long data)
                 sc->beacon.bmisscnt++;
 
                 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
-                        ath_print(common, ATH_DBG_BSTUCK,
-                                  "missed %u consecutive beacons\n",
-                                  sc->beacon.bmisscnt);
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "missed %u consecutive beacons\n",
+                                sc->beacon.bmisscnt);
                         ath9k_hw_bstuck_nfcal(ah);
                 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
-                        ath_print(common, ATH_DBG_BSTUCK,
-                                  "beacon is officially stuck\n");
+                        ath_dbg(common, ATH_DBG_BSTUCK,
+                                "beacon is officially stuck\n");
                         sc->sc_flags |= SC_OP_TSF_RESET;
                         ath_reset(sc, true);
                 }
@@ -377,9 +394,9 @@ void ath_beacon_tasklet(unsigned long data)
         }
 
         if (sc->beacon.bmisscnt != 0) {
-                ath_print(common, ATH_DBG_BSTUCK,
-                          "resume beacon xmit after %u misses\n",
-                          sc->beacon.bmisscnt);
+                ath_dbg(common, ATH_DBG_BSTUCK,
+                        "resume beacon xmit after %u misses\n",
+                        sc->beacon.bmisscnt);
                 sc->beacon.bmisscnt = 0;
         }
 
@@ -405,9 +422,9 @@ void ath_beacon_tasklet(unsigned long data)
         vif = sc->beacon.bslot[slot];
         aphy = sc->beacon.bslot_aphy[slot];
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
-                  slot, tsf, tsftu, intval, vif);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
+                slot, tsf, tsftu, intval, vif);
 
         bfaddr = 0;
         if (vif) {
@@ -449,8 +466,8 @@ void ath_beacon_tasklet(unsigned long data)
                  * are still pending on the queue.
                  */
                 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                "beacon queue %u did not stop?\n", sc->beacon.beaconq);
+                        ath_err(common, "beacon queue %u did not stop?\n",
+                                sc->beacon.beaconq);
                 }
 
                 /* NB: cabq traffic should already be queued and primed */
@@ -503,7 +520,7 @@ static void ath_beacon_config_ap(struct ath_softc *sc,
 
         /* Set the computed AP beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_beacon_init(sc, nexttbtt, intval);
         sc->beacon.bmisscnt = 0;
         ath9k_hw_set_interrupts(ah, ah->imask);
@@ -536,8 +553,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
 
         /* No need to configure beacon if we are not associated */
         if (!common->curaid) {
-                ath_print(common, ATH_DBG_BEACON,
-                         "STA is not yet associated..skipping beacon config\n");
+                ath_dbg(common, ATH_DBG_BEACON,
+                        "STA is not yet associated..skipping beacon config\n");
                 return;
         }
 
@@ -549,8 +566,6 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
          * last beacon we received (which may be none).
          */
         dtimperiod = conf->dtim_period;
-        if (dtimperiod <= 0)            /* NB: 0 if not known */
-                dtimperiod = 1;
         dtimcount = conf->dtim_count;
         if (dtimcount >= dtimperiod)    /* NB: sanity check */
                 dtimcount = 0;
@@ -558,8 +573,6 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
         cfpcount = 0;
 
         sleepduration = conf->listen_interval * intval;
-        if (sleepduration <= 0)
-                sleepduration = intval;
 
         /*
          * Pull nexttbtt forward to reflect the current
@@ -630,23 +643,22 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
         /* TSF out of range threshold fixed at 1 second */
         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
 
-        ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
-        ath_print(common, ATH_DBG_BEACON,
-                  "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
-                  bs.bs_bmissthreshold, bs.bs_sleepduration,
-                  bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
+        ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+                bs.bs_bmissthreshold, bs.bs_sleepduration,
+                bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
 
         /* Set the computed STA beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_hw_set_sta_beacon_timers(ah, &bs);
         ah->imask |= ATH9K_INT_BMISS;
         ath9k_hw_set_interrupts(ah, ah->imask);
 }
 
 static void ath_beacon_config_adhoc(struct ath_softc *sc,
-                                    struct ath_beacon_config *conf,
-                                    struct ieee80211_vif *vif)
+                                    struct ath_beacon_config *conf)
 {
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
@@ -670,9 +682,9 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
                 nexttbtt += intval;
         } while (nexttbtt < tsftu);
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "IBSS nexttbtt %u intval %u (%u)\n",
-                  nexttbtt, intval, conf->beacon_interval);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "IBSS nexttbtt %u intval %u (%u)\n",
+                nexttbtt, intval, conf->beacon_interval);
 
         /*
          * In IBSS mode enable the beacon timers but only enable SWBA interrupts
@@ -686,7 +698,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
 
         /* Set the computed ADHOC beacon timers */
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath9k_beacon_init(sc, nexttbtt, intval);
         sc->beacon.bmisscnt = 0;
         ath9k_hw_set_interrupts(ah, ah->imask);
@@ -701,18 +713,17 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
         /* Setup the beacon configuration parameters */
         if (vif) {
                 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
-
                 iftype = vif->type;
-
                 cur_conf->beacon_interval = bss_conf->beacon_int;
                 cur_conf->dtim_period = bss_conf->dtim_period;
+        } else {
+                iftype = sc->sc_ah->opmode;
+        }
+
                 cur_conf->listen_interval = 1;
                 cur_conf->dtim_count = 1;
                 cur_conf->bmiss_timeout =
                         ATH_DEFAULT_BMISS_LIMIT * cur_conf->beacon_interval;
-        } else {
-                iftype = sc->sc_ah->opmode;
-        }
 
         /*
          * It looks like mac80211 may end up using beacon interval of zero in
@@ -723,20 +734,27 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
         if (cur_conf->beacon_interval == 0)
                 cur_conf->beacon_interval = 100;
 
+        /*
+         * Some times we dont parse dtim period from mac80211, in that case
+         * use a default value
+         */
+        if (cur_conf->dtim_period == 0)
+                cur_conf->dtim_period = 1;
+
         switch (iftype) {
         case NL80211_IFTYPE_AP:
                 ath_beacon_config_ap(sc, cur_conf);
                 break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
-                ath_beacon_config_adhoc(sc, cur_conf, vif);
+                ath_beacon_config_adhoc(sc, cur_conf);
                 break;
         case NL80211_IFTYPE_STATION:
                 ath_beacon_config_sta(sc, cur_conf);
                 break;
         default:
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unsupported beaconing mode\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
                 return;
         }
 
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 6a92e57fddf0..d33bf204c995 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -35,29 +35,6 @@ struct ath_btcoex_config {
         bool bt_hold_rx_clear;
 };
 
-static const u16 ath_subsysid_tbl[] = {
-        AR9280_COEX2WIRE_SUBSYSID,
-        AT9285_COEX3WIRE_SA_SUBSYSID,
-        AT9285_COEX3WIRE_DA_SUBSYSID
-};
-
-/*
- * Checks the subsystem id of the device to see if it
- * supports btcoex
- */
-bool ath9k_hw_btcoex_supported(struct ath_hw *ah)
-{
-        int i;
-
-        if (!ah->hw_version.subsysid)
-                return false;
-
-        for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++)
-                if (ah->hw_version.subsysid == ath_subsysid_tbl[i])
-                        return true;
-
-        return false;
-}
 
 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum)
 {
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.h b/drivers/net/wireless/ath/ath9k/btcoex.h
index 1ee5a15ccbb1..588dfd464dd1 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.h
+++ b/drivers/net/wireless/ath/ath9k/btcoex.h
@@ -49,7 +49,6 @@ struct ath_btcoex_hw {
         u32 bt_coex_mode2;      /* Register setting for AR_BT_COEX_MODE2 */
 };
 
-bool ath9k_hw_btcoex_supported(struct ath_hw *ah);
 void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah);
 void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah);
 void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum);
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 6d509484b5f6..b68a1acbddd0 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -97,12 +97,12 @@ static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
                 if (h[i].privNF > limit->max) {
                         high_nf_mid = true;
 
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NFmid[%d] (%d) > MAX (%d), %s\n",
-                                  i, h[i].privNF, limit->max,
-                                  (cal->nfcal_interference ?
-                                   "not corrected (due to interference)" :
-                                   "correcting to MAX"));
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NFmid[%d] (%d) > MAX (%d), %s\n",
+                                i, h[i].privNF, limit->max,
+                                (cal->nfcal_interference ?
+                                 "not corrected (due to interference)" :
+                                 "correcting to MAX"));
 
                         /*
                          * Normally we limit the average noise floor by the
@@ -180,18 +180,18 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
                 return true;
 
         if (currCal->calState != CAL_DONE) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "Calibration state incorrect, %d\n",
-                          currCal->calState);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Calibration state incorrect, %d\n",
+                        currCal->calState);
                 return true;
         }
 
         if (!(ah->supp_cals & currCal->calData->calType))
                 return true;
 
-        ath_print(common, ATH_DBG_CALIBRATE,
-                  "Resetting Cal %d state for channel %u\n",
-                  currCal->calData->calType, conf->channel->center_freq);
+        ath_dbg(common, ATH_DBG_CALIBRATE,
+                "Resetting Cal %d state for channel %u\n",
+                currCal->calData->calType, conf->channel->center_freq);
 
         ah->caldata->CalValid &= ~currCal->calData->calType;
         currCal->calState = CAL_WAITING;
@@ -279,9 +279,9 @@ void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
          * noisefloor until the next calibration timer.
          */
         if (j == 1000) {
-                ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
-                          "to load: AR_PHY_AGC_CONTROL=0x%x\n",
-                          REG_READ(ah, AR_PHY_AGC_CONTROL));
+                ath_dbg(common, ATH_DBG_ANY,
+                        "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
+                        REG_READ(ah, AR_PHY_AGC_CONTROL));
                 return;
         }
 
@@ -318,19 +318,19 @@ static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
                 if (!nf[i])
                         continue;
 
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "NF calibrated [%s] [chain %d] is %d\n",
-                          (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "NF calibrated [%s] [chain %d] is %d\n",
+                        (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
 
                 if (nf[i] > ATH9K_NF_TOO_HIGH) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NF[%d] (%d) > MAX (%d), correcting to MAX",
-                                  i, nf[i], ATH9K_NF_TOO_HIGH);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
+                                i, nf[i], ATH9K_NF_TOO_HIGH);
                         nf[i] = limit->max;
                 } else if (nf[i] < limit->min) {
-                        ath_print(common, ATH_DBG_CALIBRATE,
-                                  "NF[%d] (%d) < MIN (%d), correcting to NOM",
-                                  i, nf[i], limit->min);
+                        ath_dbg(common, ATH_DBG_CALIBRATE,
+                                "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
+                                i, nf[i], limit->min);
                         nf[i] = limit->nominal;
                 }
         }
@@ -347,8 +347,8 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
 
         chan->channelFlags &= (~CHANNEL_CW_INT);
         if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "NF did not complete in calibration window\n");
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "NF did not complete in calibration window\n");
                 return false;
         }
 
@@ -357,10 +357,9 @@ bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
         nf = nfarray[0];
         if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
             && nf > nfThresh) {
-                ath_print(common, ATH_DBG_CALIBRATE,
-                          "noise floor failed detected; "
-                          "detected %d, threshold %d\n",
-                          nf, nfThresh);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "noise floor failed detected; detected %d, threshold %d\n",
+                        nf, nfThresh);
                 chan->channelFlags |= CHANNEL_CW_INT;
         }
 
diff --git a/drivers/net/wireless/ath/ath9k/common.c b/drivers/net/wireless/ath/ath9k/common.c
index f43a2d98421c..df1998d48253 100644
--- a/drivers/net/wireless/ath/ath9k/common.c
+++ b/drivers/net/wireless/ath/ath9k/common.c
@@ -107,12 +107,10 @@ static u32 ath9k_get_extchanmode(struct ieee80211_channel *chan,
 /*
  * Update internal channel flags.
  */
-void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-                               struct ath9k_channel *ichan)
+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
+                               struct ieee80211_channel *chan,
+                               enum nl80211_channel_type channel_type)
 {
-        struct ieee80211_channel *chan = hw->conf.channel;
-        struct ieee80211_conf *conf = &hw->conf;
-
         ichan->channel = chan->center_freq;
         ichan->chan = chan;
 
@@ -124,9 +122,8 @@ void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
         }
 
-        if (conf_is_ht(conf))
-                ichan->chanmode = ath9k_get_extchanmode(chan,
-                                                        conf->channel_type);
+        if (channel_type != NL80211_CHAN_NO_HT)
+                ichan->chanmode = ath9k_get_extchanmode(chan, channel_type);
 }
 EXPORT_SYMBOL(ath9k_cmn_update_ichannel);
 
@@ -142,7 +139,7 @@ struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
 
         chan_idx = curchan->hw_value;
         channel = &ah->channels[chan_idx];
-        ath9k_cmn_update_ichannel(hw, channel);
+        ath9k_cmn_update_ichannel(channel, curchan, hw->conf.channel_type);
 
         return channel;
 }
@@ -183,8 +180,8 @@ void ath9k_cmn_btcoex_bt_stomp(struct ath_common *common,
                                            AR_STOMP_NONE_WLAN_WGHT);
                 break;
         default:
-                ath_print(common, ATH_DBG_BTCOEX,
-                          "Invalid Stomptype\n");
+                ath_dbg(common, ATH_DBG_BTCOEX,
+                        "Invalid Stomptype\n");
                 break;
         }
 
diff --git a/drivers/net/wireless/ath/ath9k/common.h b/drivers/net/wireless/ath/ath9k/common.h
index fea3b3315391..a126bddebb0a 100644
--- a/drivers/net/wireless/ath/ath9k/common.h
+++ b/drivers/net/wireless/ath/ath9k/common.h
@@ -17,7 +17,6 @@
 #include <net/mac80211.h>
 
 #include "../ath.h"
-#include "../debug.h"
 
 #include "hw.h"
 #include "hw-ops.h"
@@ -31,10 +30,11 @@
 #define WME_MAX_BA              WME_BA_BMP_SIZE
 #define ATH_TID_MAX_BUFS        (2 * WME_MAX_BA)
 
-#define WME_AC_BE   0
-#define WME_AC_BK   1
-#define WME_AC_VI   2
-#define WME_AC_VO   3
+/* These must match mac80211 skb queue mapping numbers */
+#define WME_AC_VO   0
+#define WME_AC_VI   1
+#define WME_AC_BE   2
+#define WME_AC_BK   3
 #define WME_NUM_AC  4
 
 #define ATH_RSSI_DUMMY_MARKER   0x127
@@ -62,8 +62,9 @@ enum ath_stomp_type {
 
 int ath9k_cmn_padpos(__le16 frame_control);
 int ath9k_cmn_get_hw_crypto_keytype(struct sk_buff *skb);
-void ath9k_cmn_update_ichannel(struct ieee80211_hw *hw,
-                               struct ath9k_channel *ichan);
+void ath9k_cmn_update_ichannel(struct ath9k_channel *ichan,
+                               struct ieee80211_channel *chan,
+                               enum nl80211_channel_type channel_type);
 struct ath9k_channel *ath9k_cmn_get_curchannel(struct ieee80211_hw *hw,
                                                struct ath_hw *ah);
 int ath9k_cmn_count_streams(unsigned int chainmask, int max);
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 43e71a944cb1..3586c43077a7 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -24,8 +24,6 @@
 #define REG_READ_D(_ah, _reg) \
         ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
 
-static struct dentry *ath9k_debugfs_root;
-
 static int ath9k_debugfs_open(struct inode *inode, struct file *file)
 {
         file->private_data = inode->i_private;
@@ -461,16 +459,16 @@ static ssize_t read_file_wiphy(struct file *file, char __user *user_buf,
 
         /* Put variable-length stuff down here, and check for overflows. */
         for (i = 0; i < sc->num_sec_wiphy; i++) {
-                struct ath_wiphy *aphy = sc->sec_wiphy[i];
-                if (aphy == NULL)
+                struct ath_wiphy *aphy_tmp = sc->sec_wiphy[i];
+                if (aphy_tmp == NULL)
                         continue;
-                chan = aphy->hw->conf.channel;
+                chan = aphy_tmp->hw->conf.channel;
                 len += snprintf(buf + len, sizeof(buf) - len,
                         "secondary: %s (%s chan=%d ht=%d)\n",
-                        wiphy_name(aphy->hw->wiphy),
-                        ath_wiphy_state_str(aphy->state),
+                        wiphy_name(aphy_tmp->hw->wiphy),
+                        ath_wiphy_state_str(aphy_tmp->state),
                         ieee80211_frequency_to_channel(chan->center_freq),
-                        aphy->chan_is_ht);
+                                                       aphy_tmp->chan_is_ht);
         }
         if (len > sizeof(buf))
                 len = sizeof(buf);
@@ -585,10 +583,10 @@ static const struct file_operations fops_wiphy = {
         do {                                                            \
                 len += snprintf(buf + len, size - len,                  \
                                 "%s%13u%11u%10u%10u\n", str,            \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BE]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_BK]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VI]].elem, \
-                sc->debug.stats.txstats[sc->tx.hwq_map[WME_AC_VO]].elem); \
+                sc->debug.stats.txstats[WME_AC_BE].elem, \
+                sc->debug.stats.txstats[WME_AC_BK].elem, \
+                sc->debug.stats.txstats[WME_AC_VI].elem, \
+                sc->debug.stats.txstats[WME_AC_VO].elem); \
 } while(0)
 
 static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
@@ -630,33 +628,35 @@ static ssize_t read_file_xmit(struct file *file, char __user *user_buf,
         return retval;
 }
 
-void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-                       struct ath_buf *bf, struct ath_tx_status *ts)
+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
+                       struct ath_tx_status *ts)
 {
-        TX_STAT_INC(txq->axq_qnum, tx_pkts_all);
-        sc->debug.stats.txstats[txq->axq_qnum].tx_bytes_all += bf->bf_mpdu->len;
+        int qnum = skb_get_queue_mapping(bf->bf_mpdu);
+
+        TX_STAT_INC(qnum, tx_pkts_all);
+        sc->debug.stats.txstats[qnum].tx_bytes_all += bf->bf_mpdu->len;
 
         if (bf_isampdu(bf)) {
                 if (bf_isxretried(bf))
-                        TX_STAT_INC(txq->axq_qnum, a_xretries);
+                        TX_STAT_INC(qnum, a_xretries);
                 else
-                        TX_STAT_INC(txq->axq_qnum, a_completed);
+                        TX_STAT_INC(qnum, a_completed);
         } else {
-                TX_STAT_INC(txq->axq_qnum, completed);
+                TX_STAT_INC(qnum, completed);
         }
 
         if (ts->ts_status & ATH9K_TXERR_FIFO)
-                TX_STAT_INC(txq->axq_qnum, fifo_underrun);
+                TX_STAT_INC(qnum, fifo_underrun);
         if (ts->ts_status & ATH9K_TXERR_XTXOP)
-                TX_STAT_INC(txq->axq_qnum, xtxop);
+                TX_STAT_INC(qnum, xtxop);
         if (ts->ts_status & ATH9K_TXERR_TIMER_EXPIRED)
-                TX_STAT_INC(txq->axq_qnum, timer_exp);
+                TX_STAT_INC(qnum, timer_exp);
         if (ts->ts_flags & ATH9K_TX_DESC_CFG_ERR)
-                TX_STAT_INC(txq->axq_qnum, desc_cfg_err);
+                TX_STAT_INC(qnum, desc_cfg_err);
         if (ts->ts_flags & ATH9K_TX_DATA_UNDERRUN)
-                TX_STAT_INC(txq->axq_qnum, data_underrun);
+                TX_STAT_INC(qnum, data_underrun);
         if (ts->ts_flags & ATH9K_TX_DELIM_UNDERRUN)
-                TX_STAT_INC(txq->axq_qnum, delim_underrun);
+                TX_STAT_INC(qnum, delim_underrun);
 }
 
 static const struct file_operations fops_xmit = {
@@ -876,11 +876,8 @@ int ath9k_init_debug(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath_softc *sc = (struct ath_softc *) common->priv;
 
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
-
-        sc->debug.debugfs_phy = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
-                                                      ath9k_debugfs_root);
+        sc->debug.debugfs_phy = debugfs_create_dir("ath9k",
+                                                   sc->hw->wiphy->debugfsdir);
         if (!sc->debug.debugfs_phy)
                 return -ENOMEM;
 
@@ -933,29 +930,7 @@ int ath9k_init_debug(struct ath_hw *ah)
         sc->debug.regidx = 0;
         return 0;
 err:
-        ath9k_exit_debug(ah);
-        return -ENOMEM;
-}
-
-void ath9k_exit_debug(struct ath_hw *ah)
-{
-        struct ath_common *common = ath9k_hw_common(ah);
-        struct ath_softc *sc = (struct ath_softc *) common->priv;
-
         debugfs_remove_recursive(sc->debug.debugfs_phy);
-}
-
-int ath9k_debug_create_root(void)
-{
-        ath9k_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
-        if (!ath9k_debugfs_root)
-                return -ENOENT;
-
-        return 0;
-}
-
-void ath9k_debug_remove_root(void)
-{
-        debugfs_remove(ath9k_debugfs_root);
-        ath9k_debugfs_root = NULL;
+        sc->debug.debugfs_phy = NULL;
+        return -ENOMEM;
 }
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index bb0823242ba0..1e5078bd0344 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -164,13 +164,10 @@ struct ath9k_debug {
 };
 
 int ath9k_init_debug(struct ath_hw *ah);
-void ath9k_exit_debug(struct ath_hw *ah);
 
-int ath9k_debug_create_root(void);
-void ath9k_debug_remove_root(void);
 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
-void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
-                       struct ath_buf *bf, struct ath_tx_status *ts);
+void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
+                       struct ath_tx_status *ts);
 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 
 #else
@@ -180,26 +177,12 @@ static inline int ath9k_init_debug(struct ath_hw *ah)
         return 0;
 }
 
-static inline void ath9k_exit_debug(struct ath_hw *ah)
-{
-}
-
-static inline int ath9k_debug_create_root(void)
-{
-        return 0;
-}
-
-static inline void ath9k_debug_remove_root(void)
-{
-}
-
 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
                                             enum ath9k_int status)
 {
 }
 
 static inline void ath_debug_stat_tx(struct ath_softc *sc,
-                                     struct ath_txq *txq,
                                      struct ath_buf *bf,
                                      struct ath_tx_status *ts)
 {
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.c b/drivers/net/wireless/ath/ath9k/eeprom.c
index 2bbf94d0191e..d05163159572 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom.c
@@ -234,7 +234,7 @@ void ath9k_hw_get_target_powers(struct ath_hw *ah,
 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
                                 bool is2GHz, int num_band_edges)
 {
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         int i;
 
         for (i = 0; (i < num_band_edges) &&
@@ -273,12 +273,225 @@ void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
                 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
                 break;
         default:
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Invalid chainmask configuration\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Invalid chainmask configuration\n");
                 break;
         }
 }
 
+void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                void *pRawDataSet,
+                                u8 *bChans, u16 availPiers,
+                                u16 tPdGainOverlap,
+                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
+                                u16 numXpdGains)
+{
+        int i, j, k;
+        int16_t ss;
+        u16 idxL = 0, idxR = 0, numPiers;
+        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
+                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
+
+        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
+        u8 minPwrT4[AR5416_NUM_PD_GAINS];
+        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
+        int16_t vpdStep;
+        int16_t tmpVal;
+        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
+        bool match;
+        int16_t minDelta = 0;
+        struct chan_centers centers;
+        int pdgain_boundary_default;
+        struct cal_data_per_freq *data_def = pRawDataSet;
+        struct cal_data_per_freq_4k *data_4k = pRawDataSet;
+        struct cal_data_per_freq_ar9287 *data_9287 = pRawDataSet;
+        bool eeprom_4k = AR_SREV_9285(ah) || AR_SREV_9271(ah);
+        int intercepts;
+
+        if (AR_SREV_9287(ah))
+                intercepts = AR9287_PD_GAIN_ICEPTS;
+        else
+                intercepts = AR5416_PD_GAIN_ICEPTS;
+
+        memset(&minPwrT4, 0, AR5416_NUM_PD_GAINS);
+        ath9k_hw_get_channel_centers(ah, chan, &centers);
+
+        for (numPiers = 0; numPiers < availPiers; numPiers++) {
+                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
+                        break;
+        }
+
+        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
+                                                             IS_CHAN_2GHZ(chan)),
+                                               bChans, numPiers, &idxL, &idxR);
+
+        if (match) {
+                if (AR_SREV_9287(ah)) {
+                        /* FIXME: array overrun? */
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_9287[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_9287[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_9287[idxL].pwrPdg[i],
+                                                data_9287[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                } else if (eeprom_4k) {
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_4k[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_4k[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_4k[idxL].pwrPdg[i],
+                                                data_4k[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                } else {
+                        for (i = 0; i < numXpdGains; i++) {
+                                minPwrT4[i] = data_def[idxL].pwrPdg[i][0];
+                                maxPwrT4[i] = data_def[idxL].pwrPdg[i][4];
+                                ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                data_def[idxL].pwrPdg[i],
+                                                data_def[idxL].vpdPdg[i],
+                                                intercepts,
+                                                vpdTableI[i]);
+                        }
+                }
+        } else {
+                for (i = 0; i < numXpdGains; i++) {
+                        if (AR_SREV_9287(ah)) {
+                                pVpdL = data_9287[idxL].vpdPdg[i];
+                                pPwrL = data_9287[idxL].pwrPdg[i];
+                                pVpdR = data_9287[idxR].vpdPdg[i];
+                                pPwrR = data_9287[idxR].pwrPdg[i];
+                        } else if (eeprom_4k) {
+                                pVpdL = data_4k[idxL].vpdPdg[i];
+                                pPwrL = data_4k[idxL].pwrPdg[i];
+                                pVpdR = data_4k[idxR].vpdPdg[i];
+                                pPwrR = data_4k[idxR].pwrPdg[i];
+                        } else {
+                                pVpdL = data_def[idxL].vpdPdg[i];
+                                pPwrL = data_def[idxL].pwrPdg[i];
+                                pVpdR = data_def[idxR].vpdPdg[i];
+                                pPwrR = data_def[idxR].pwrPdg[i];
+                        }
+
+                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
+
+                        maxPwrT4[i] =
+                                min(pPwrL[intercepts - 1],
+                                    pPwrR[intercepts - 1]);
+
+
+                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                pPwrL, pVpdL,
+                                                intercepts,
+                                                vpdTableL[i]);
+                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
+                                                pPwrR, pVpdR,
+                                                intercepts,
+                                                vpdTableR[i]);
+
+                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
+                                vpdTableI[i][j] =
+                                        (u8)(ath9k_hw_interpolate((u16)
+                                             FREQ2FBIN(centers.
+                                                       synth_center,
+                                                       IS_CHAN_2GHZ
+                                                       (chan)),
+                                             bChans[idxL], bChans[idxR],
+                                             vpdTableL[i][j], vpdTableR[i][j]));
+                        }
+                }
+        }
+
+        k = 0;
+
+        for (i = 0; i < numXpdGains; i++) {
+                if (i == (numXpdGains - 1))
+                        pPdGainBoundaries[i] =
+                                (u16)(maxPwrT4[i] / 2);
+                else
+                        pPdGainBoundaries[i] =
+                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
+
+                pPdGainBoundaries[i] =
+                        min((u16)MAX_RATE_POWER, pPdGainBoundaries[i]);
+
+                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
+                        minDelta = pPdGainBoundaries[0] - 23;
+                        pPdGainBoundaries[0] = 23;
+                } else {
+                        minDelta = 0;
+                }
+
+                if (i == 0) {
+                        if (AR_SREV_9280_20_OR_LATER(ah))
+                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
+                        else
+                                ss = 0;
+                } else {
+                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
+                                        (minPwrT4[i] / 2)) -
+                                       tPdGainOverlap + 1 + minDelta);
+                }
+                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
+                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+
+                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
+                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
+                        ss++;
+                }
+
+                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
+                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
+                                (minPwrT4[i] / 2));
+                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
+                        tgtIndex : sizeCurrVpdTable;
+
+                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                        pPDADCValues[k++] = vpdTableI[i][ss++];
+                }
+
+                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
+                                    vpdTableI[i][sizeCurrVpdTable - 2]);
+                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
+
+                if (tgtIndex >= maxIndex) {
+                        while ((ss <= tgtIndex) &&
+                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
+                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
+                                                    (ss - maxIndex + 1) * vpdStep));
+                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
+                                                         255 : tmpVal);
+                                ss++;
+                        }
+                }
+        }
+
+        if (eeprom_4k)
+                pdgain_boundary_default = 58;
+        else
+                pdgain_boundary_default = pPdGainBoundaries[i - 1];
+
+        while (i < AR5416_PD_GAINS_IN_MASK) {
+                pPdGainBoundaries[i] = pdgain_boundary_default;
+                i++;
+        }
+
+        while (k < AR5416_NUM_PDADC_VALUES) {
+                pPDADCValues[k] = pPDADCValues[k - 1];
+                k++;
+        }
+}
+
 int ath9k_hw_eeprom_init(struct ath_hw *ah)
 {
         int status;
diff --git a/drivers/net/wireless/ath/ath9k/eeprom.h b/drivers/net/wireless/ath/ath9k/eeprom.h
index dd59f09441a3..58e2ddc927a9 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/eeprom.h
@@ -17,12 +17,12 @@
 #ifndef EEPROM_H
 #define EEPROM_H
 
+#define AR_EEPROM_MODAL_SPURS   5
+
 #include "../ath.h"
 #include <net/cfg80211.h>
 #include "ar9003_eeprom.h"
 
-#define AH_USE_EEPROM   0x1
-
 #ifdef __BIG_ENDIAN
 #define AR5416_EEPROM_MAGIC 0x5aa5
 #else
@@ -149,8 +149,6 @@
 #define AR5416_NUM_PD_GAINS             4
 #define AR5416_PD_GAINS_IN_MASK         4
 #define AR5416_PD_GAIN_ICEPTS           5
-#define AR5416_EEPROM_MODAL_SPURS       5
-#define AR5416_MAX_RATE_POWER           63
 #define AR5416_NUM_PDADC_VALUES         128
 #define AR5416_BCHAN_UNUSED             0xFF
 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
@@ -175,8 +173,6 @@
 #define AR5416_EEP4K_NUM_CTLS                 12
 #define AR5416_EEP4K_NUM_BAND_EDGES           4
 #define AR5416_EEP4K_NUM_PD_GAINS             2
-#define AR5416_EEP4K_PD_GAINS_IN_MASK         4
-#define AR5416_EEP4K_PD_GAIN_ICEPTS           5
 #define AR5416_EEP4K_MAX_CHAINS               1
 
 #define AR9280_TX_GAIN_TABLE_SIZE 22
@@ -198,35 +194,12 @@
 #define AR9287_NUM_2G_40_TARGET_POWERS  3
 #define AR9287_NUM_CTLS                 12
 #define AR9287_NUM_BAND_EDGES           4
-#define AR9287_NUM_PD_GAINS             4
-#define AR9287_PD_GAINS_IN_MASK         4
 #define AR9287_PD_GAIN_ICEPTS           1
-#define AR9287_EEPROM_MODAL_SPURS       5
-#define AR9287_MAX_RATE_POWER           63
-#define AR9287_NUM_PDADC_VALUES         128
-#define AR9287_NUM_RATES                16
-#define AR9287_BCHAN_UNUSED             0xFF
-#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
-#define AR9287_OPFLAGS_11A              0x01
-#define AR9287_OPFLAGS_11G              0x02
-#define AR9287_OPFLAGS_2G_HT40          0x08
-#define AR9287_OPFLAGS_2G_HT20          0x20
-#define AR9287_OPFLAGS_5G_HT40          0x04
-#define AR9287_OPFLAGS_5G_HT20          0x10
 #define AR9287_EEPMISC_BIG_ENDIAN       0x01
 #define AR9287_EEPMISC_WOW              0x02
 #define AR9287_MAX_CHAINS               2
 #define AR9287_ANT_16S                  32
-#define AR9287_custdatasize             20
-
-#define AR9287_NUM_ANT_CHAIN_FIELDS     6
-#define AR9287_NUM_ANT_COMMON_FIELDS    4
-#define AR9287_SIZE_ANT_CHAIN_FIELD     2
-#define AR9287_SIZE_ANT_COMMON_FIELD    4
-#define AR9287_ANT_CHAIN_MASK           0x3
-#define AR9287_ANT_COMMON_MASK          0xf
-#define AR9287_CHAIN_0_IDX              0
-#define AR9287_CHAIN_1_IDX              1
+
 #define AR9287_DATA_SZ                  32
 
 #define AR9287_PWR_TABLE_OFFSET_DB  -5
@@ -280,6 +253,7 @@ enum eeprom_param {
         EEP_PAPRD,
         EEP_MODAL_VER,
         EEP_ANT_DIV_CTL1,
+        EEP_CHAIN_MASK_REDUCE
 };
 
 enum ar5416_rates {
@@ -395,7 +369,7 @@ struct modal_eep_header {
         u16 xpaBiasLvlFreq[3];
         u8 futureModal[6];
 
-        struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct calDataPerFreqOpLoop {
@@ -463,7 +437,7 @@ struct modal_eep_4k_header {
         u8 db2_4:4, reserved:4;
 #endif
         u8 futureModal[4];
-        struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct base_eep_ar9287_header {
@@ -521,7 +495,7 @@ struct modal_eep_ar9287_header {
         u8 ob_qam;
         u8 ob_pal_off;
         u8 futureModal[30];
-        struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
+        struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS];
 } __packed;
 
 struct cal_data_per_freq {
@@ -530,8 +504,8 @@ struct cal_data_per_freq {
 } __packed;
 
 struct cal_data_per_freq_4k {
-        u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
-        u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
+        u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
+        u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 } __packed;
 
 struct cal_target_power_leg {
@@ -557,8 +531,8 @@ struct cal_data_op_loop_ar9287 {
 } __packed;
 
 struct cal_data_per_freq_ar9287 {
-        u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
-        u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+        u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
+        u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
 } __packed;
 
 union cal_data_per_freq_ar9287_u {
@@ -673,15 +647,12 @@ struct eeprom_ops {
         bool (*fill_eeprom)(struct ath_hw *hw);
         int (*get_eeprom_ver)(struct ath_hw *hw);
         int (*get_eeprom_rev)(struct ath_hw *hw);
-        u8 (*get_num_ant_config)(struct ath_hw *hw,
-                                 enum ath9k_hal_freq_band band);
-        u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
-                                      struct ath9k_channel *chan);
         void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
         void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
         void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
                            u16 cfgCtl, u8 twiceAntennaReduction,
-                           u8 twiceMaxRegulatoryPower, u8 powerLimit);
+                           u8 twiceMaxRegulatoryPower, u8 powerLimit,
+                           bool test);
         u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
 };
 
@@ -714,6 +685,14 @@ u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
 int ath9k_hw_eeprom_init(struct ath_hw *ah);
 
+void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah,
+                                struct ath9k_channel *chan,
+                                void *pRawDataSet,
+                                u8 *bChans, u16 availPiers,
+                                u16 tPdGainOverlap,
+                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
+                                u16 numXpdGains);
+
 #define ar5416_get_ntxchains(_txchainmask)                      \
         (((_txchainmask >> 2) & 1) +                            \
          ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 4fa4d8e28c64..fbdff7e47952 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -37,14 +37,14 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
         eep_start_loc = 64;
 
         if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Reading from EEPROM, not flash\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
         }
 
         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Unable to read eeprom region\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
@@ -69,13 +69,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
         if (!ath9k_hw_use_flash(ah)) {
                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
                                          &magic)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Reading Magic # failed\n");
+                        ath_err(common, "Reading Magic # failed\n");
                         return false;
                 }
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -90,16 +89,15 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
@@ -120,8 +118,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                 u32 integer;
                 u16 word;
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "EEPROM Endianness is not native.. Changing\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "EEPROM Endianness is not native.. Changing\n");
 
                 word = swab16(eep->baseEepHeader.length);
                 eep->baseEepHeader.length = word;
@@ -155,7 +153,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
                         eep->modalHeader.antCtrlChain[i] = integer;
                 }
 
-                for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
                         eep->modalHeader.spurChans[i].spurChan = word;
                 }
@@ -163,9 +161,8 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
-                          sum, ah->eep_ops->get_eeprom_ver(ah));
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                        sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
@@ -230,173 +227,6 @@ static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
         }
 }
 
-static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
-                                struct ath9k_channel *chan,
-                                struct cal_data_per_freq_4k *pRawDataSet,
-                                u8 *bChans, u16 availPiers,
-                                u16 tPdGainOverlap,
-                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
-                                u16 numXpdGains)
-{
-#define TMP_VAL_VPD_TABLE \
-        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
-        u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-#define PD_GAIN_BOUNDARY_DEFAULT 58;
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index(
-                                        (u8)FREQ2FBIN(centers.synth_center,
-                                        IS_CHAN_2GHZ(chan)), bChans, numPiers,
-                                        &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                        pRawDataSet[idxL].pwrPdg[i],
-                                        pRawDataSet[idxL].vpdPdg[i],
-                                        AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                        vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] =
-                                min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
-                                    pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
-
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR5416_EEP4K_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] =
-                                        (u8)(ath9k_hw_interpolate((u16)
-                                             FREQ2FBIN(centers.
-                                                       synth_center,
-                                                       IS_CHAN_2GHZ
-                                                       (chan)),
-                                             bChans[idxL], bChans[idxR],
-                                             vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
-
-                pPdGainBoundaries[i] =
-                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
-
-                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
-                        minDelta = pPdGainBoundaries[0] - 23;
-                        pPdGainBoundaries[0] = 23;
-                } else {
-                        minDelta = 0;
-                }
-
-                if (i == 0) {
-                        if (AR_SREV_9280_20_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
-                                (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                        tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex >= maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
-                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
-                                                         255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
-                i++;
-        }
-
-        while (k < AR5416_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k - 1];
-                k++;
-        }
-
-        return;
-#undef TMP_VAL_VPD_TABLE
-}
-
 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                                   struct ath9k_channel *chan,
                                   int16_t *pTxPowerIndexOffset)
@@ -407,7 +237,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
         u8 *pCalBChans = NULL;
         u16 pdGainOverlap_t2;
         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
-        u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
+        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
         u16 numPiers, i, j;
         u16 numXpdGain, xpdMask;
         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
@@ -429,12 +259,12 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 
         numXpdGain = 0;
 
-        for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
-                if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
+        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
                                 break;
                         xpdGainValues[numXpdGain] =
-                                (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
+                                (u16)(AR5416_PD_GAINS_IN_MASK - i);
                         numXpdGain++;
                 }
         }
@@ -458,7 +288,7 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
                         pRawDataset = pEepData->calPierData2G[i];
 
-                        ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
+                        ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
                                             pRawDataset, pCalBChans,
                                             numPiers, pdGainOverlap_t2,
                                             gainBoundaries,
@@ -488,21 +318,20 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
                                 REG_WRITE(ah, regOffset, reg32);
 
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
-                                          i, regChainOffset, regOffset,
-                                          reg32);
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC: Chain %d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d |\n",
-                                          i, 4 * j, pdadcValues[4 * j],
-                                          4 * j + 1, pdadcValues[4 * j + 1],
-                                          4 * j + 2, pdadcValues[4 * j + 2],
-                                          4 * j + 3,
-                                          pdadcValues[4 * j + 3]);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
+                                        i, regChainOffset, regOffset,
+                                        reg32);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC: Chain %d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d |\n",
+                                        i, 4 * j, pdadcValues[4 * j],
+                                        4 * j + 1, pdadcValues[4 * j + 1],
+                                        4 * j + 2, pdadcValues[4 * j + 2],
+                                        4 * j + 3, pdadcValues[4 * j + 3]);
 
                                 regOffset += 4;
                         }
@@ -532,14 +361,16 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
         int i;
         int16_t twiceLargestAntenna;
         u16 twiceMinEdgePower;
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         struct cal_ctl_data_4k *rep;
         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
                 0, { 0, 0, 0, 0}
         };
@@ -550,10 +381,10 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
                 0, {0, 0, 0, 0}
         };
-        u16 ctlModesFor11g[] =
-                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
-                  CTL_2GHT40
-                };
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
 
         ath9k_hw_get_channel_centers(ah, chan, &centers);
 
@@ -615,7 +446,7 @@ static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 
                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+                        twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
                              pEepData->ctlIndex[i]; i++) {
@@ -726,7 +557,7 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
                                     u16 cfgCtl,
                                     u8 twiceAntennaReduction,
                                     u8 twiceMaxRegulatoryPower,
-                                    u8 powerLimit)
+                                    u8 powerLimit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
@@ -751,15 +582,20 @@ static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
-                        ratesArray[i] = AR5416_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
         }
 
+        if (test)
+            return;
 
         /* Update regulatory */
-
         i = rate6mb;
         if (IS_CHAN_HT40(chan))
                 i = rateHt40_0;
@@ -934,8 +770,7 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
         pModal = &eep->modalHeader;
         txRxAttenLocal = 23;
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 
         /* Single chain for 4K EEPROM*/
         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
@@ -1151,21 +986,6 @@ static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
         }
 }
 
-static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                              struct ath9k_channel *chan)
-{
-        struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
-        struct modal_eep_4k_header *pModal = &eep->modalHeader;
-
-        return pModal->antCtrlCommon;
-}
-
-static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
-                                         enum ath9k_hal_freq_band freq_band)
-{
-        return 1;
-}
-
 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 {
 #define EEP_MAP4K_SPURCHAN \
@@ -1174,17 +994,17 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_MAP4K_SPURCHAN;
@@ -1202,8 +1022,6 @@ const struct eeprom_ops eep_4k_ops = {
         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_4k_set_board_values,
         .set_addac              = ath9k_hw_4k_set_addac,
         .set_txpower            = ath9k_hw_4k_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index 195406db3bd8..9b6bc8a953bc 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -37,21 +37,21 @@ static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
         int addr, eep_start_loc;
         eep_data = (u16 *)eep;
 
-        if (AR9287_HTC_DEVID(ah))
+        if (common->bus_ops->ath_bus_type == ATH_USB)
                 eep_start_loc = AR9287_HTC_EEP_START_LOC;
         else
                 eep_start_loc = AR9287_EEP_START_LOC;
 
         if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Reading from EEPROM, not flash\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Reading from EEPROM, not flash\n");
         }
 
         for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
                                          eep_data)) {
-                        ath_print(common, ATH_DBG_EEPROM,
-                                  "Unable to read eeprom region\n");
+                        ath_dbg(common, ATH_DBG_EEPROM,
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
@@ -72,13 +72,12 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
         if (!ath9k_hw_use_flash(ah)) {
                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
                                          &magic)) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Reading Magic # failed\n");
+                        ath_err(common, "Reading Magic # failed\n");
                         return false;
                 }
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -93,16 +92,15 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "Endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
@@ -152,7 +150,7 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
                         eep->modalHeader.antCtrlChain[i] = integer;
                 }
 
-                for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
+                for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
                         eep->modalHeader.spurChans[i].spurChan = word;
                 }
@@ -160,9 +158,8 @@ static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
             || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
-                           sum, ah->eep_ops->get_eeprom_ver(ah));
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                        sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
 
@@ -223,163 +220,6 @@ static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
         }
 }
 
-static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
-                               struct ath9k_channel *chan,
-                               struct cal_data_per_freq_ar9287 *pRawDataSet,
-                               u8 *bChans, u16 availPiers,
-                               u16 tPdGainOverlap,
-                               u16 *pPdGainBoundaries,
-                               u8 *pPDADCValues,
-                               u16 numXpdGains)
-{
-#define TMP_VAL_VPD_TABLE                                               \
-        ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
-
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR9287_NUM_PD_GAINS];
-        u8 maxPwrT4[AR9287_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-        static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index(
-                (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
-                bChans, numPiers, &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pRawDataSet[idxL].pwrPdg[i],
-                                                pRawDataSet[idxL].vpdPdg[i],
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
-                                          pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR9287_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
-                                       (u16)FREQ2FBIN(centers. synth_center,
-                                                      IS_CHAN_2GHZ(chan)),
-                                       bChans[idxL], bChans[idxR],
-                                       vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
-
-                pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
-                                           pPdGainBoundaries[i]);
-
-
-                minDelta = 0;
-
-                if (i == 0) {
-                        if (AR_SREV_9280_20_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i-1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] +
-                                tPdGainOverlap - (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                            tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex > maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                                (k < (AR9287_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
-                                pPDADCValues[k++] =
-                                        (u8)((tmpVal > 255) ? 255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR9287_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
-                i++;
-        }
-
-        while (k < AR9287_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k-1];
-                k++;
-        }
-
-#undef TMP_VAL_VPD_TABLE
-}
-
 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
                             struct ath9k_channel *chan,
                             struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
@@ -392,7 +232,7 @@ static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
         ath9k_hw_get_channel_centers(ah, chan, &centers);
 
         for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
+                if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
                         break;
         }
 
@@ -458,11 +298,11 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
         struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
         u8 *pCalBChans = NULL;
         u16 pdGainOverlap_t2;
-        u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
-        u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
+        u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
+        u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
         u16 numPiers = 0, i, j;
         u16 numXpdGain, xpdMask;
-        u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
+        u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
         u32 reg32, regOffset, regChainOffset, regval;
         int16_t modalIdx, diff = 0;
         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
@@ -490,12 +330,12 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
         numXpdGain = 0;
 
         /* Calculate the value of xpdgains from the xpdGain Mask */
-        for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
-                if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
-                        if (numXpdGain >= AR9287_NUM_PD_GAINS)
+        for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
+                if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
+                        if (numXpdGain >= AR5416_NUM_PD_GAINS)
                                 break;
                         xpdGainValues[numXpdGain] =
-                                (u16)(AR9287_PD_GAINS_IN_MASK-i);
+                                (u16)(AR5416_PD_GAINS_IN_MASK-i);
                         numXpdGain++;
                 }
         }
@@ -528,7 +368,7 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                         (struct cal_data_per_freq_ar9287 *)
                                         pEepData->calPierData2G[i];
 
-                                ath9k_hw_get_ar9287_gain_boundaries_pdadcs(ah, chan,
+                                ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
                                                            pRawDataset,
                                                            pCalBChans, numPiers,
                                                            pdGainOverlap_t2,
@@ -564,13 +404,13 @@ static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
                                              (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
                                 diff *= 2;
 
-                                for (j = 0; j < ((u16)AR9287_NUM_PDADC_VALUES-diff); j++)
+                                for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
                                         pdadcValues[j] = pdadcValues[j+diff];
 
-                                for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
-                                     j < AR9287_NUM_PDADC_VALUES; j++)
+                                for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
+                                     j < AR5416_NUM_PDADC_VALUES; j++)
                                         pdadcValues[j] =
-                                          pdadcValues[AR9287_NUM_PDADC_VALUES-diff];
+                                          pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
                         }
 
                         if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
@@ -613,9 +453,9 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10
 
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
         int i;
         int16_t twiceLargestAntenna;
         struct cal_ctl_data_ar9287 *rep;
@@ -626,13 +466,13 @@ static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
         struct cal_target_power_ht targetPowerHt20,
                                     targetPowerHt40 = {0, {0, 0, 0, 0} };
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11g[] = {CTL_11B,
-                                CTL_11G,
-                                CTL_2GHT20,
-                                CTL_11B_EXT,
-                                CTL_11G_EXT,
-                                CTL_2GHT40};
-        u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
+        u16 numCtlModes = 0;
+        const u16 *pCtlMode = NULL;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         int tx_chainmask;
         u16 twiceMinEdgePower;
@@ -853,7 +693,7 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                                         struct ath9k_channel *chan, u16 cfgCtl,
                                         u8 twiceAntennaReduction,
                                         u8 twiceMaxRegulatoryPower,
-                                        u8 powerLimit)
+                                        u8 powerLimit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
@@ -877,12 +717,26 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR9287_MAX_RATE_POWER)
-                        ratesArray[i] = AR9287_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
         }
 
+        if (test)
+                return;
+
+        if (IS_CHAN_2GHZ(chan))
+                i = rate1l;
+        else
+                i = rate6mb;
+
+        regulatory->max_power_level = ratesArray[i];
+
         if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++)
                         ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
@@ -971,17 +825,6 @@ static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
         }
-
-        if (IS_CHAN_2GHZ(chan))
-                i = rate1l;
-        else
-                i = rate6mb;
-
-        if (AR_SREV_9280_20_OR_LATER(ah))
-                regulatory->max_power_level =
-                        ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
-        else
-                regulatory->max_power_level = ratesArray[i];
 }
 
 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
@@ -1023,8 +866,7 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
                 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
         }
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 
         for (i = 0; i < AR9287_MAX_CHAINS; i++) {
                 regChainOffset = i * 0x1000;
@@ -1125,21 +967,6 @@ static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
                                   pModal->xpaBiasLvl);
 }
 
-static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
-                                             enum ath9k_hal_freq_band freq_band)
-{
-        return 1;
-}
-
-static u32 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                                  struct ath9k_channel *chan)
-{
-        struct ar9287_eeprom *eep = &ah->eeprom.map9287;
-        struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
-
-        return pModal->antCtrlCommon;
-}
-
 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
                                             u16 i, bool is2GHz)
 {
@@ -1149,17 +976,17 @@ static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
         struct ath_common *common = ath9k_hw_common(ah);
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_MAP9287_SPURCHAN;
@@ -1177,8 +1004,6 @@ const struct eeprom_ops eep_ar9287_ops = {
         .fill_eeprom            = ath9k_hw_ar9287_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_ar9287_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_ar9287_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_ar9287_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_ar9287_set_board_values,
         .set_addac              = ath9k_hw_ar9287_set_addac,
         .set_txpower            = ath9k_hw_ar9287_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index a3ccb1b9638d..088f141f2006 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -96,8 +96,8 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
                 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
                                          eep_data)) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "Unable to read eeprom region\n");
+                        ath_err(ath9k_hw_common(ah),
+                                "Unable to read eeprom region\n");
                         return false;
                 }
                 eep_data++;
@@ -117,13 +117,13 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
         int i, addr, size;
 
         if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
-                ath_print(common, ATH_DBG_FATAL, "Reading Magic # failed\n");
+                ath_err(common, "Reading Magic # failed\n");
                 return false;
         }
 
         if (!ath9k_hw_use_flash(ah)) {
-                ath_print(common, ATH_DBG_EEPROM,
-                          "Read Magic = 0x%04X\n", magic);
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "Read Magic = 0x%04X\n", magic);
 
                 if (magic != AR5416_EEPROM_MAGIC) {
                         magic2 = swab16(magic);
@@ -139,16 +139,15 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                                         eepdata++;
                                 }
                         } else {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Invalid EEPROM Magic. "
-                                          "Endianness mismatch.\n");
+                                ath_err(common,
+                                        "Invalid EEPROM Magic. Endianness mismatch.\n");
                                 return -EINVAL;
                         }
                 }
         }
 
-        ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
-                  need_swap ? "True" : "False");
+        ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
+                need_swap ? "True" : "False");
 
         if (need_swap)
                 el = swab16(ah->eeprom.def.baseEepHeader.length);
@@ -169,8 +168,8 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                 u32 integer, j;
                 u16 word;
 
-                ath_print(common, ATH_DBG_EEPROM,
-                          "EEPROM Endianness is not native.. Changing.\n");
+                ath_dbg(common, ATH_DBG_EEPROM,
+                        "EEPROM Endianness is not native.. Changing.\n");
 
                 word = swab16(eep->baseEepHeader.length);
                 eep->baseEepHeader.length = word;
@@ -207,7 +206,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
                                 pModal->antCtrlChain[i] = integer;
                         }
 
-                        for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
+                        for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
                                 word = swab16(pModal->spurChans[i].spurChan);
                                 pModal->spurChans[i].spurChan = word;
                         }
@@ -216,8 +215,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
 
         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
+                ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
                         sum, ah->eep_ops->get_eeprom_ver(ah));
                 return -EINVAL;
         }
@@ -376,8 +374,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
 
-        REG_WRITE(ah, AR_PHY_SWITCH_COM,
-                  ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
+        REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
 
         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
                 if (AR_SREV_9280(ah)) {
@@ -590,168 +587,6 @@ static void ath9k_hw_def_set_addac(struct ath_hw *ah,
 #undef XPA_LVL_FREQ
 }
 
-static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
-                                struct ath9k_channel *chan,
-                                struct cal_data_per_freq *pRawDataSet,
-                                u8 *bChans, u16 availPiers,
-                                u16 tPdGainOverlap,
-                                u16 *pPdGainBoundaries, u8 *pPDADCValues,
-                                u16 numXpdGains)
-{
-        int i, j, k;
-        int16_t ss;
-        u16 idxL = 0, idxR = 0, numPiers;
-        static u8 vpdTableL[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableR[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-        static u8 vpdTableI[AR5416_NUM_PD_GAINS]
-                [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
-
-        u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
-        u8 minPwrT4[AR5416_NUM_PD_GAINS];
-        u8 maxPwrT4[AR5416_NUM_PD_GAINS];
-        int16_t vpdStep;
-        int16_t tmpVal;
-        u16 sizeCurrVpdTable, maxIndex, tgtIndex;
-        bool match;
-        int16_t minDelta = 0;
-        struct chan_centers centers;
-
-        memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
-        ath9k_hw_get_channel_centers(ah, chan, &centers);
-
-        for (numPiers = 0; numPiers < availPiers; numPiers++) {
-                if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
-                        break;
-        }
-
-        match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
-                                                             IS_CHAN_2GHZ(chan)),
-                                               bChans, numPiers, &idxL, &idxR);
-
-        if (match) {
-                for (i = 0; i < numXpdGains; i++) {
-                        minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
-                        maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                        pRawDataSet[idxL].pwrPdg[i],
-                                        pRawDataSet[idxL].vpdPdg[i],
-                                        AR5416_PD_GAIN_ICEPTS,
-                                        vpdTableI[i]);
-                }
-        } else {
-                for (i = 0; i < numXpdGains; i++) {
-                        pVpdL = pRawDataSet[idxL].vpdPdg[i];
-                        pPwrL = pRawDataSet[idxL].pwrPdg[i];
-                        pVpdR = pRawDataSet[idxR].vpdPdg[i];
-                        pPwrR = pRawDataSet[idxR].pwrPdg[i];
-
-                        minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
-
-                        maxPwrT4[i] =
-                                min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
-                                    pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
-
-
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrL, pVpdL,
-                                                AR5416_PD_GAIN_ICEPTS,
-                                                vpdTableL[i]);
-                        ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
-                                                pPwrR, pVpdR,
-                                                AR5416_PD_GAIN_ICEPTS,
-                                                vpdTableR[i]);
-
-                        for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
-                                vpdTableI[i][j] =
-                                        (u8)(ath9k_hw_interpolate((u16)
-                                             FREQ2FBIN(centers.
-                                                       synth_center,
-                                                       IS_CHAN_2GHZ
-                                                       (chan)),
-                                             bChans[idxL], bChans[idxR],
-                                             vpdTableL[i][j], vpdTableR[i][j]));
-                        }
-                }
-        }
-
-        k = 0;
-
-        for (i = 0; i < numXpdGains; i++) {
-                if (i == (numXpdGains - 1))
-                        pPdGainBoundaries[i] =
-                                (u16)(maxPwrT4[i] / 2);
-                else
-                        pPdGainBoundaries[i] =
-                                (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
-
-                pPdGainBoundaries[i] =
-                        min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
-
-                if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
-                        minDelta = pPdGainBoundaries[0] - 23;
-                        pPdGainBoundaries[0] = 23;
-                } else {
-                        minDelta = 0;
-                }
-
-                if (i == 0) {
-                        if (AR_SREV_9280_20_OR_LATER(ah))
-                                ss = (int16_t)(0 - (minPwrT4[i] / 2));
-                        else
-                                ss = 0;
-                } else {
-                        ss = (int16_t)((pPdGainBoundaries[i - 1] -
-                                        (minPwrT4[i] / 2)) -
-                                       tPdGainOverlap + 1 + minDelta);
-                }
-                vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
-                        pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
-                        ss++;
-                }
-
-                sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
-                tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
-                                (minPwrT4[i] / 2));
-                maxIndex = (tgtIndex < sizeCurrVpdTable) ?
-                        tgtIndex : sizeCurrVpdTable;
-
-                while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                        pPDADCValues[k++] = vpdTableI[i][ss++];
-                }
-
-                vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
-                                    vpdTableI[i][sizeCurrVpdTable - 2]);
-                vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
-
-                if (tgtIndex >= maxIndex) {
-                        while ((ss <= tgtIndex) &&
-                               (k < (AR5416_NUM_PDADC_VALUES - 1))) {
-                                tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
-                                                    (ss - maxIndex + 1) * vpdStep));
-                                pPDADCValues[k++] = (u8)((tmpVal > 255) ?
-                                                         255 : tmpVal);
-                                ss++;
-                        }
-                }
-        }
-
-        while (i < AR5416_PD_GAINS_IN_MASK) {
-                pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
-                i++;
-        }
-
-        while (k < AR5416_NUM_PDADC_VALUES) {
-                pPDADCValues[k] = pPDADCValues[k - 1];
-                k++;
-        }
-}
-
 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
                                 u16 *gb,
                                 u16 numXpdGain,
@@ -784,7 +619,7 @@ static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
                 /* Because of a hardware limitation, ensure the gain boundary
                  * is not larger than (63 - overlap)
                  */
-                gb_limit = (u16)(AR5416_MAX_RATE_POWER - pdGainOverlap_t2);
+                gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
 
                 for (k = 0; k < numXpdGain; k++)
                         gb[k] = (u16)min(gb_limit, gb[k]);
@@ -918,7 +753,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
                                                      txPower/2, pdadcValues);
                         } else {
-                                ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
+                                ath9k_hw_get_gain_boundaries_pdadcs(ah,
                                                         chan, pRawDataset,
                                                         pCalBChans, numPiers,
                                                         pdGainOverlap_t2,
@@ -966,20 +801,19 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
                                 REG_WRITE(ah, regOffset, reg32);
 
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC (%d,%4x): %4.4x %8.8x\n",
-                                          i, regChainOffset, regOffset,
-                                          reg32);
-                                ath_print(common, ATH_DBG_EEPROM,
-                                          "PDADC: Chain %d | PDADC %3d "
-                                          "Value %3d | PDADC %3d Value %3d | "
-                                          "PDADC %3d Value %3d | PDADC %3d "
-                                          "Value %3d |\n",
-                                          i, 4 * j, pdadcValues[4 * j],
-                                          4 * j + 1, pdadcValues[4 * j + 1],
-                                          4 * j + 2, pdadcValues[4 * j + 2],
-                                          4 * j + 3,
-                                          pdadcValues[4 * j + 3]);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC (%d,%4x): %4.4x %8.8x\n",
+                                        i, regChainOffset, regOffset,
+                                        reg32);
+                                ath_dbg(common, ATH_DBG_EEPROM,
+                                        "PDADC: Chain %d | PDADC %3d "
+                                        "Value %3d | PDADC %3d Value %3d | "
+                                        "PDADC %3d Value %3d | PDADC %3d "
+                                        "Value %3d |\n",
+                                        i, 4 * j, pdadcValues[4 * j],
+                                        4 * j + 1, pdadcValues[4 * j + 1],
+                                        4 * j + 2, pdadcValues[4 * j + 2],
+                                        4 * j + 3, pdadcValues[4 * j + 3]);
 
                                 regOffset += 4;
                         }
@@ -1004,9 +838,9 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
-        u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+        u16 twiceMaxEdgePower = MAX_RATE_POWER;
         static const u16 tpScaleReductionTable[5] =
-                { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
+                { 0, 3, 6, 9, MAX_RATE_POWER };
 
         int i;
         int16_t twiceLargestAntenna;
@@ -1022,13 +856,16 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
                 0, {0, 0, 0, 0}
         };
         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
-        u16 ctlModesFor11a[] =
-                { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
-        u16 ctlModesFor11g[] =
-                { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
-                  CTL_2GHT40
-                };
-        u16 numCtlModes, *pCtlMode, ctlMode, freq;
+        static const u16 ctlModesFor11a[] = {
+                CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
+        };
+        static const u16 ctlModesFor11g[] = {
+                CTL_11B, CTL_11G, CTL_2GHT20,
+                CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
+        };
+        u16 numCtlModes;
+        const u16 *pCtlMode;
+        u16 ctlMode, freq;
         struct chan_centers centers;
         int tx_chainmask;
         u16 twiceMinEdgePower;
@@ -1148,7 +985,7 @@ static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
 
                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
-                        twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
+                        twiceMaxEdgePower = MAX_RATE_POWER;
 
                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
                         if ((((cfgCtl & ~CTL_MODE_M) |
@@ -1263,7 +1100,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
                                     u16 cfgCtl,
                                     u8 twiceAntennaReduction,
                                     u8 twiceMaxRegulatoryPower,
-                                    u8 powerLimit)
+                                    u8 powerLimit, bool test)
 {
 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
@@ -1290,12 +1127,44 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
 
         ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset);
 
+        regulatory->max_power_level = 0;
         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
-                if (ratesArray[i] > AR5416_MAX_RATE_POWER)
-                        ratesArray[i] = AR5416_MAX_RATE_POWER;
+                if (ratesArray[i] > MAX_RATE_POWER)
+                        ratesArray[i] = MAX_RATE_POWER;
+                if (ratesArray[i] > regulatory->max_power_level)
+                        regulatory->max_power_level = ratesArray[i];
+        }
+
+        if (!test) {
+                i = rate6mb;
+
+                if (IS_CHAN_HT40(chan))
+                        i = rateHt40_0;
+                else if (IS_CHAN_HT20(chan))
+                        i = rateHt20_0;
+
+                regulatory->max_power_level = ratesArray[i];
         }
 
+        switch(ar5416_get_ntxchains(ah->txchainmask)) {
+        case 1:
+                break;
+        case 2:
+                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
+                break;
+        case 3:
+                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
+                break;
+        default:
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
+                        "Invalid chainmask configuration\n");
+                break;
+        }
+
+        if (test)
+                return;
+
         if (AR_SREV_9280_20_OR_LATER(ah)) {
                 for (i = 0; i < Ar5416RateSize; i++) {
                         int8_t pwr_table_offset;
@@ -1392,62 +1261,6 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
-
-        i = rate6mb;
-
-        if (IS_CHAN_HT40(chan))
-                i = rateHt40_0;
-        else if (IS_CHAN_HT20(chan))
-                i = rateHt20_0;
-
-        if (AR_SREV_9280_20_OR_LATER(ah))
-                regulatory->max_power_level =
-                        ratesArray[i] + AR5416_PWR_TABLE_OFFSET_DB * 2;
-        else
-                regulatory->max_power_level = ratesArray[i];
-
-        switch(ar5416_get_ntxchains(ah->txchainmask)) {
-        case 1:
-                break;
-        case 2:
-                regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
-                break;
-        case 3:
-                regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
-                break;
-        default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_EEPROM,
-                          "Invalid chainmask configuration\n");
-                break;
-        }
-}
-
-static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
-                                          enum ath9k_hal_freq_band freq_band)
-{
-        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
-        struct modal_eep_header *pModal =
-                &(eep->modalHeader[freq_band]);
-        struct base_eep_header *pBase = &eep->baseEepHeader;
-        u8 num_ant_config;
-
-        num_ant_config = 1;
-
-        if (pBase->version >= 0x0E0D &&
-            (pModal->lna_ctl & LNA_CTL_USE_ANT1))
-                num_ant_config += 1;
-
-        return num_ant_config;
-}
-
-static u32 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
-                                               struct ath9k_channel *chan)
-{
-        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
-        struct modal_eep_header *pModal =
-                &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
-
-        return pModal->antCtrlCommon;
 }
 
 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
@@ -1458,17 +1271,17 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
 
         u16 spur_val = AR_NO_SPUR;
 
-        ath_print(common, ATH_DBG_ANI,
-                  "Getting spur idx %d is2Ghz. %d val %x\n",
-                  i, is2GHz, ah->config.spurchans[i][is2GHz]);
+        ath_dbg(common, ATH_DBG_ANI,
+                "Getting spur idx:%d is2Ghz:%d val:%x\n",
+                i, is2GHz, ah->config.spurchans[i][is2GHz]);
 
         switch (ah->config.spurmode) {
         case SPUR_DISABLE:
                 break;
         case SPUR_ENABLE_IOCTL:
                 spur_val = ah->config.spurchans[i][is2GHz];
-                ath_print(common, ATH_DBG_ANI,
-                          "Getting spur val from new loc. %d\n", spur_val);
+                ath_dbg(common, ATH_DBG_ANI,
+                        "Getting spur val from new loc. %d\n", spur_val);
                 break;
         case SPUR_ENABLE_EEPROM:
                 spur_val = EEP_DEF_SPURCHAN;
@@ -1486,8 +1299,6 @@ const struct eeprom_ops eep_def_ops = {
         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
-        .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
-        .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
         .set_board_values       = ath9k_hw_def_set_board_values,
         .set_addac              = ath9k_hw_def_set_addac,
         .set_txpower            = ath9k_hw_def_set_txpower,
diff --git a/drivers/net/wireless/ath/ath9k/gpio.c b/drivers/net/wireless/ath/ath9k/gpio.c
index 4a9a68bba324..133764069246 100644
--- a/drivers/net/wireless/ath/ath9k/gpio.c
+++ b/drivers/net/wireless/ath/ath9k/gpio.c
@@ -103,8 +103,8 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 
         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
         if (ret)
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Failed to register led:%s", led->name);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Failed to register led:%s", led->name);
         else
                 led->registered = 1;
         return ret;
@@ -236,13 +236,13 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
                 sc->sc_flags &= ~(SC_OP_BT_PRIORITY_DETECTED | SC_OP_BT_SCAN);
                 /* Detect if colocated bt started scanning */
                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
-                                  "BT scan detected");
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
+                                "BT scan detected\n");
                         sc->sc_flags |= (SC_OP_BT_SCAN |
                                          SC_OP_BT_PRIORITY_DETECTED);
                 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
-                                  "BT priority traffic detected");
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
+                                "BT priority traffic detected\n");
                         sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
                 }
 
@@ -259,7 +259,7 @@ static void ath9k_gen_timer_start(struct ath_hw *ah,
         ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
 
         if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 ah->imask |= ATH9K_INT_GENTIMER;
                 ath9k_hw_set_interrupts(ah, ah->imask);
         }
@@ -273,7 +273,7 @@ static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
 
         /* if no timer is enabled, turn off interrupt mask */
         if (timer_table->timer_mask.val == 0) {
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 ah->imask &= ~ATH9K_INT_GENTIMER;
                 ath9k_hw_set_interrupts(ah, ah->imask);
         }
@@ -310,10 +310,8 @@ static void ath_btcoex_period_timer(unsigned long data)
 
                 timer_period = is_btscan ? btcoex->btscan_no_stomp :
                                            btcoex->btcoex_no_stomp;
-                ath9k_gen_timer_start(ah,
-                                      btcoex->no_stomp_timer,
-                                      (ath9k_hw_gettsf32(ah) +
-                                       timer_period), timer_period * 10);
+                ath9k_gen_timer_start(ah, btcoex->no_stomp_timer, 0,
+                                      timer_period * 10);
                 btcoex->hw_timer_enabled = true;
         }
 
@@ -333,8 +331,8 @@ static void ath_btcoex_no_stomp_timer(void *arg)
         struct ath_common *common = ath9k_hw_common(ah);
         bool is_btscan = sc->sc_flags & SC_OP_BT_SCAN;
 
-        ath_print(common, ATH_DBG_BTCOEX,
-                  "no stomp timer running\n");
+        ath_dbg(common, ATH_DBG_BTCOEX,
+                "no stomp timer running\n");
 
         spin_lock_bh(&btcoex->btcoex_lock);
 
@@ -380,8 +378,8 @@ void ath9k_btcoex_timer_resume(struct ath_softc *sc)
         struct ath_btcoex *btcoex = &sc->btcoex;
         struct ath_hw *ah = sc->sc_ah;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                  "Starting btcoex timers");
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                "Starting btcoex timers\n");
 
         /* make sure duty cycle timer is also stopped when resuming */
         if (btcoex->hw_timer_enabled)
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c
index 0de3c3d3c245..5ab3084eb9cb 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.c
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c
@@ -28,10 +28,7 @@ MODULE_FIRMWARE(FIRMWARE_AR9271);
 static struct usb_device_id ath9k_hif_usb_ids[] = {
         { USB_DEVICE(0x0cf3, 0x9271) }, /* Atheros */
         { USB_DEVICE(0x0cf3, 0x1006) }, /* Atheros */
-        { USB_DEVICE(0x0cf3, 0x7010) }, /* Atheros */
-        { USB_DEVICE(0x0cf3, 0x7015) }, /* Atheros */
         { USB_DEVICE(0x0846, 0x9030) }, /* Netgear N150 */
-        { USB_DEVICE(0x0846, 0x9018) }, /* Netgear WNDA3200 */
         { USB_DEVICE(0x07D1, 0x3A10) }, /* Dlink Wireless 150 */
         { USB_DEVICE(0x13D3, 0x3327) }, /* Azurewave */
         { USB_DEVICE(0x13D3, 0x3328) }, /* Azurewave */
@@ -40,9 +37,21 @@ static struct usb_device_id ath9k_hif_usb_ids[] = {
         { USB_DEVICE(0x13D3, 0x3349) }, /* Azurewave */
         { USB_DEVICE(0x13D3, 0x3350) }, /* Azurewave */
         { USB_DEVICE(0x04CA, 0x4605) }, /* Liteon */
-        { USB_DEVICE(0x083A, 0xA704) }, /* SMC Networks */
         { USB_DEVICE(0x040D, 0x3801) }, /* VIA */
-        { USB_DEVICE(0x1668, 0x1200) }, /* Verizon */
+        { USB_DEVICE(0x0cf3, 0xb003) }, /* Ubiquiti WifiStation Ext */
+
+        { USB_DEVICE(0x0cf3, 0x7015),
+          .driver_info = AR9287_USB },  /* Atheros */
+        { USB_DEVICE(0x1668, 0x1200),
+          .driver_info = AR9287_USB },  /* Verizon */
+
+        { USB_DEVICE(0x0cf3, 0x7010),
+          .driver_info = AR9280_USB },  /* Atheros */
+        { USB_DEVICE(0x0846, 0x9018),
+          .driver_info = AR9280_USB },  /* Netgear WNDA3200 */
+        { USB_DEVICE(0x083A, 0xA704),
+          .driver_info = AR9280_USB },  /* SMC Networks */
+
         { },
 };
 
@@ -144,16 +153,36 @@ static void hif_usb_tx_cb(struct urb *urb)
         case -ENODEV:
         case -ESHUTDOWN:
                 /*
-                 * The URB has been killed, free the SKBs
-                 * and return.
+                 * The URB has been killed, free the SKBs.
                  */
                 ath9k_skb_queue_purge(hif_dev, &tx_buf->skb_queue);
-                return;
+
+                /*
+                 * If the URBs are being flushed, no need to add this
+                 * URB to the free list.
+                 */
+                spin_lock(&hif_dev->tx.tx_lock);
+                if (hif_dev->tx.flags & HIF_USB_TX_FLUSH) {
+                        spin_unlock(&hif_dev->tx.tx_lock);
+                        return;
+                }
+                spin_unlock(&hif_dev->tx.tx_lock);
+
+                /*
+                 * In the stop() case, this URB has to be added to
+                 * the free list.
+                 */
+                goto add_free;
         default:
                 break;
         }
 
-        /* Check if TX has been stopped */
+        /*
+         * Check if TX has been stopped, this is needed because
+         * this CB could have been invoked just after the TX lock
+         * was released in hif_stop() and kill_urb() hasn't been
+         * called yet.
+         */
         spin_lock(&hif_dev->tx.tx_lock);
         if (hif_dev->tx.flags & HIF_USB_TX_STOP) {
                 spin_unlock(&hif_dev->tx.tx_lock);
@@ -305,6 +334,7 @@ static void hif_usb_start(void *hif_handle, u8 pipe_id)
 static void hif_usb_stop(void *hif_handle, u8 pipe_id)
 {
         struct hif_device_usb *hif_dev = (struct hif_device_usb *)hif_handle;
+        struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
         unsigned long flags;
 
         spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
@@ -312,6 +342,12 @@ static void hif_usb_stop(void *hif_handle, u8 pipe_id)
         hif_dev->tx.tx_skb_cnt = 0;
         hif_dev->tx.flags |= HIF_USB_TX_STOP;
         spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
+        /* The pending URBs have to be canceled. */
+        list_for_each_entry_safe(tx_buf, tx_buf_tmp,
+                                 &hif_dev->tx.tx_pending, list) {
+                usb_kill_urb(tx_buf->urb);
+        }
 }
 
 static int hif_usb_send(void *hif_handle, u8 pipe_id, struct sk_buff *skb,
@@ -353,9 +389,9 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
                                     struct sk_buff *skb)
 {
         struct sk_buff *nskb, *skb_pool[MAX_PKT_NUM_IN_TRANSFER];
-        int index = 0, i = 0, chk_idx, len = skb->len;
-        int rx_remain_len = 0, rx_pkt_len = 0;
-        u16 pkt_len, pkt_tag, pool_index = 0;
+        int index = 0, i = 0, len = skb->len;
+        int rx_remain_len, rx_pkt_len;
+        u16 pool_index = 0;
         u8 *ptr;
 
         spin_lock(&hif_dev->rx_lock);
@@ -389,64 +425,64 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev,
         spin_unlock(&hif_dev->rx_lock);
 
         while (index < len) {
+                u16 pkt_len;
+                u16 pkt_tag;
+                u16 pad_len;
+                int chk_idx;
+
                 ptr = (u8 *) skb->data;
 
                 pkt_len = ptr[index] + (ptr[index+1] << 8);
                 pkt_tag = ptr[index+2] + (ptr[index+3] << 8);
 
-                if (pkt_tag == ATH_USB_RX_STREAM_MODE_TAG) {
-                        u16 pad_len;
-
-                        pad_len = 4 - (pkt_len & 0x3);
-                        if (pad_len == 4)
-                                pad_len = 0;
-
-                        chk_idx = index;
-                        index = index + 4 + pkt_len + pad_len;
-
-                        if (index > MAX_RX_BUF_SIZE) {
-                                spin_lock(&hif_dev->rx_lock);
-                                hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE;
-                                hif_dev->rx_transfer_len =
-                                        MAX_RX_BUF_SIZE - chk_idx - 4;
-                                hif_dev->rx_pad_len = pad_len;
-
-                                nskb = __dev_alloc_skb(pkt_len + 32,
-                                                       GFP_ATOMIC);
-                                if (!nskb) {
-                                        dev_err(&hif_dev->udev->dev,
-                                        "ath9k_htc: RX memory allocation"
-                                        " error\n");
-                                        spin_unlock(&hif_dev->rx_lock);
-                                        goto err;
-                                }
-                                skb_reserve(nskb, 32);
-                                RX_STAT_INC(skb_allocated);
-
-                                memcpy(nskb->data, &(skb->data[chk_idx+4]),
-                                       hif_dev->rx_transfer_len);
-
-                                /* Record the buffer pointer */
-                                hif_dev->remain_skb = nskb;
+                if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) {
+                        RX_STAT_INC(skb_dropped);
+                        return;
+                }
+
+                pad_len = 4 - (pkt_len & 0x3);
+                if (pad_len == 4)
+                        pad_len = 0;
+
+                chk_idx = index;
+                index = index + 4 + pkt_len + pad_len;
+
+                if (index > MAX_RX_BUF_SIZE) {
+                        spin_lock(&hif_dev->rx_lock);
+                        hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE;
+                        hif_dev->rx_transfer_len =
+                                MAX_RX_BUF_SIZE - chk_idx - 4;
+                        hif_dev->rx_pad_len = pad_len;
+
+                        nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
+                        if (!nskb) {
+                                dev_err(&hif_dev->udev->dev,
+                                        "ath9k_htc: RX memory allocation error\n");
                                 spin_unlock(&hif_dev->rx_lock);
-                        } else {
-                                nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
-                                if (!nskb) {
-                                        dev_err(&hif_dev->udev->dev,
-                                        "ath9k_htc: RX memory allocation"
-                                        " error\n");
-                                        goto err;
-                                }
-                                skb_reserve(nskb, 32);
-                                RX_STAT_INC(skb_allocated);
-
-                                memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len);
-                                skb_put(nskb, pkt_len);
-                                skb_pool[pool_index++] = nskb;
+                                goto err;
                         }
+                        skb_reserve(nskb, 32);
+                        RX_STAT_INC(skb_allocated);
+
+                        memcpy(nskb->data, &(skb->data[chk_idx+4]),
+                               hif_dev->rx_transfer_len);
+
+                        /* Record the buffer pointer */
+                        hif_dev->remain_skb = nskb;
+                        spin_unlock(&hif_dev->rx_lock);
                 } else {
-                        RX_STAT_INC(skb_dropped);
-                        return;
+                        nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC);
+                        if (!nskb) {
+                                dev_err(&hif_dev->udev->dev,
+                                        "ath9k_htc: RX memory allocation error\n");
+                                goto err;
+                        }
+                        skb_reserve(nskb, 32);
+                        RX_STAT_INC(skb_allocated);
+
+                        memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len);
+                        skb_put(nskb, pkt_len);
+                        skb_pool[pool_index++] = nskb;
                 }
         }
 
@@ -461,7 +497,7 @@ err:
 static void ath9k_hif_usb_rx_cb(struct urb *urb)
 {
         struct sk_buff *skb = (struct sk_buff *) urb->context;
-        struct hif_device_usb *hif_dev = (struct hif_device_usb *)
+        struct hif_device_usb *hif_dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int ret;
 
@@ -508,7 +544,7 @@ static void ath9k_hif_usb_reg_in_cb(struct urb *urb)
 {
         struct sk_buff *skb = (struct sk_buff *) urb->context;
         struct sk_buff *nskb;
-        struct hif_device_usb *hif_dev = (struct hif_device_usb *)
+        struct hif_device_usb *hif_dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
         int ret;
 
@@ -578,6 +614,7 @@ free:
 static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
 {
         struct tx_buf *tx_buf = NULL, *tx_buf_tmp = NULL;
+        unsigned long flags;
 
         list_for_each_entry_safe(tx_buf, tx_buf_tmp,
                                  &hif_dev->tx.tx_buf, list) {
@@ -588,6 +625,10 @@ static void ath9k_hif_usb_dealloc_tx_urbs(struct hif_device_usb *hif_dev)
                 kfree(tx_buf);
         }
 
+        spin_lock_irqsave(&hif_dev->tx.tx_lock, flags);
+        hif_dev->tx.flags |= HIF_USB_TX_FLUSH;
+        spin_unlock_irqrestore(&hif_dev->tx.tx_lock, flags);
+
         list_for_each_entry_safe(tx_buf, tx_buf_tmp,
                                  &hif_dev->tx.tx_pending, list) {
                 usb_kill_urb(tx_buf->urb);
@@ -776,7 +817,8 @@ static void ath9k_hif_usb_dealloc_urbs(struct hif_device_usb *hif_dev)
         ath9k_hif_usb_dealloc_rx_urbs(hif_dev);
 }
 
-static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev,
+                                     u32 drv_info)
 {
         int transfer, err;
         const void *data = hif_dev->firmware->data;
@@ -807,18 +849,10 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
         }
         kfree(buf);
 
-        switch (hif_dev->device_id) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
-        case 0xA704:
-        case 0x1200:
+        if (IS_AR7010_DEVICE(drv_info))
                 firm_offset = AR7010_FIRMWARE_TEXT;
-                break;
-        default:
+        else
                 firm_offset = AR9271_FIRMWARE_TEXT;
-                break;
-        }
 
         /*
          * Issue FW download complete command to firmware.
@@ -836,7 +870,7 @@ static int ath9k_hif_usb_download_fw(struct hif_device_usb *hif_dev)
         return 0;
 }
 
-static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
+static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev, u32 drv_info)
 {
         int ret, idx;
         struct usb_host_interface *alt = &hif_dev->interface->altsetting[0];
@@ -852,7 +886,7 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
         }
 
         /* Download firmware */
-        ret = ath9k_hif_usb_download_fw(hif_dev);
+        ret = ath9k_hif_usb_download_fw(hif_dev, drv_info);
         if (ret) {
                 dev_err(&hif_dev->udev->dev,
                         "ath9k_htc: Firmware - %s download failed\n",
@@ -884,9 +918,9 @@ static int ath9k_hif_usb_dev_init(struct hif_device_usb *hif_dev)
 
         return 0;
 
-err_fw_download:
-        ath9k_hif_usb_dealloc_urbs(hif_dev);
 err_urb:
+        ath9k_hif_usb_dealloc_urbs(hif_dev);
+err_fw_download:
         release_firmware(hif_dev->firmware);
 err_fw_req:
         hif_dev->firmware = NULL;
@@ -931,23 +965,15 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
 
         /* Find out which firmware to load */
 
-        switch(hif_dev->device_id) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
-        case 0xA704:
-        case 0x1200:
+        if (IS_AR7010_DEVICE(id->driver_info))
                 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x0202)
                         hif_dev->fw_name = FIRMWARE_AR7010_1_1;
                 else
                         hif_dev->fw_name = FIRMWARE_AR7010;
-                break;
-        default:
+        else
                 hif_dev->fw_name = FIRMWARE_AR9271;
-                break;
-        }
 
-        ret = ath9k_hif_usb_dev_init(hif_dev);
+        ret = ath9k_hif_usb_dev_init(hif_dev, id->driver_info);
         if (ret) {
                 ret = -EINVAL;
                 goto err_hif_init_usb;
@@ -955,7 +981,7 @@ static int ath9k_hif_usb_probe(struct usb_interface *interface,
 
         ret = ath9k_htc_hw_init(hif_dev->htc_handle,
                                 &hif_dev->udev->dev, hif_dev->device_id,
-                                hif_dev->udev->product);
+                                hif_dev->udev->product, id->driver_info);
         if (ret) {
                 ret = -EINVAL;
                 goto err_htc_hw_init;
@@ -998,18 +1024,17 @@ static void ath9k_hif_usb_reboot(struct usb_device *udev)
 static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
 {
         struct usb_device *udev = interface_to_usbdev(interface);
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+        bool unplugged = (udev->state == USB_STATE_NOTATTACHED) ? true : false;
 
         if (hif_dev) {
-                ath9k_htc_hw_deinit(hif_dev->htc_handle,
-                    (udev->state == USB_STATE_NOTATTACHED) ? true : false);
+                ath9k_htc_hw_deinit(hif_dev->htc_handle, unplugged);
                 ath9k_htc_hw_free(hif_dev->htc_handle);
                 ath9k_hif_usb_dev_deinit(hif_dev);
                 usb_set_intfdata(interface, NULL);
         }
 
-        if (hif_dev->flags & HIF_USB_START)
+        if (!unplugged && (hif_dev->flags & HIF_USB_START))
                 ath9k_hif_usb_reboot(udev);
 
         kfree(hif_dev);
@@ -1021,8 +1046,7 @@ static void ath9k_hif_usb_disconnect(struct usb_interface *interface)
 static int ath9k_hif_usb_suspend(struct usb_interface *interface,
                                  pm_message_t message)
 {
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
 
         /*
          * The device has to be set to FULLSLEEP mode in case no
@@ -1038,8 +1062,8 @@ static int ath9k_hif_usb_suspend(struct usb_interface *interface,
 
 static int ath9k_hif_usb_resume(struct usb_interface *interface)
 {
-        struct hif_device_usb *hif_dev =
-                (struct hif_device_usb *) usb_get_intfdata(interface);
+        struct hif_device_usb *hif_dev = usb_get_intfdata(interface);
+        struct htc_target *htc_handle = hif_dev->htc_handle;
         int ret;
 
         ret = ath9k_hif_usb_alloc_urbs(hif_dev);
@@ -1047,7 +1071,8 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
                 return ret;
 
         if (hif_dev->firmware) {
-                ret = ath9k_hif_usb_download_fw(hif_dev);
+                ret = ath9k_hif_usb_download_fw(hif_dev,
+                                htc_handle->drv_priv->ah->hw_version.usbdev);
                 if (ret)
                         goto fail_resume;
         } else {
@@ -1057,7 +1082,7 @@ static int ath9k_hif_usb_resume(struct usb_interface *interface)
 
         mdelay(100);
 
-        ret = ath9k_htc_resume(hif_dev->htc_handle);
+        ret = ath9k_htc_resume(htc_handle);
 
         if (ret)
                 goto fail_resume;
diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.h b/drivers/net/wireless/ath/ath9k/hif_usb.h
index 2daf97b11c08..7b9d863d4035 100644
--- a/drivers/net/wireless/ath/ath9k/hif_usb.h
+++ b/drivers/net/wireless/ath/ath9k/hif_usb.h
@@ -17,6 +17,8 @@
 #ifndef HTC_USB_H
 #define HTC_USB_H
 
+#define IS_AR7010_DEVICE(_v) (((_v) == AR9280_USB) || ((_v) == AR9287_USB))
+
 #define AR9271_FIRMWARE       0x501000
 #define AR9271_FIRMWARE_TEXT  0x903000
 #define AR7010_FIRMWARE_TEXT  0x906000
@@ -62,6 +64,7 @@ struct tx_buf {
 };
 
 #define HIF_USB_TX_STOP  BIT(0)
+#define HIF_USB_TX_FLUSH BIT(1)
 
 struct hif_usb_tx {
         u8 flags;
diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h
index c3b561daa6c1..a099b3e87ed3 100644
--- a/drivers/net/wireless/ath/ath9k/htc.h
+++ b/drivers/net/wireless/ath/ath9k/htc.h
@@ -331,17 +331,15 @@ void ath_htc_cancel_btcoex_work(struct ath9k_htc_priv *priv);
 
 #define OP_INVALID                 BIT(0)
 #define OP_SCANNING                BIT(1)
-#define OP_FULL_RESET              BIT(2)
-#define OP_LED_ASSOCIATED          BIT(3)
-#define OP_LED_ON                  BIT(4)
-#define OP_PREAMBLE_SHORT          BIT(5)
-#define OP_PROTECT_ENABLE          BIT(6)
-#define OP_ASSOCIATED              BIT(7)
-#define OP_ENABLE_BEACON           BIT(8)
-#define OP_LED_DEINIT              BIT(9)
-#define OP_UNPLUGGED               BIT(10)
-#define OP_BT_PRIORITY_DETECTED    BIT(11)
-#define OP_BT_SCAN                 BIT(12)
+#define OP_LED_ASSOCIATED          BIT(2)
+#define OP_LED_ON                  BIT(3)
+#define OP_PREAMBLE_SHORT          BIT(4)
+#define OP_PROTECT_ENABLE          BIT(5)
+#define OP_ASSOCIATED              BIT(6)
+#define OP_ENABLE_BEACON           BIT(7)
+#define OP_LED_DEINIT              BIT(8)
+#define OP_BT_PRIORITY_DETECTED    BIT(9)
+#define OP_BT_SCAN                 BIT(10)
 
 struct ath9k_htc_priv {
         struct device *dev;
@@ -368,7 +366,7 @@ struct ath9k_htc_priv {
         u16 seq_no;
         u32 bmiss_cnt;
 
-        struct ath9k_hw_cal_data caldata[38];
+        struct ath9k_hw_cal_data caldata[ATH9K_NUM_CHANNELS];
 
         spinlock_t beacon_lock;
 
@@ -378,7 +376,7 @@ struct ath9k_htc_priv {
         struct ieee80211_vif *vif;
         struct htc_beacon_config cur_beacon_conf;
         unsigned int rxfilter;
-        struct tasklet_struct wmi_tasklet;
+        struct tasklet_struct swba_tasklet;
         struct tasklet_struct rx_tasklet;
         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
         struct ath9k_htc_rx rx;
@@ -386,6 +384,7 @@ struct ath9k_htc_priv {
         struct sk_buff_head tx_queue;
         struct delayed_work ath9k_ani_work;
         struct work_struct ps_work;
+        struct work_struct fatal_work;
 
         struct mutex htc_pm_lock;
         unsigned long ps_usecount;
@@ -420,6 +419,8 @@ static inline void ath_read_cachesize(struct ath_common *common, int *csz)
         common->bus_ops->read_cachesize(common, csz);
 }
 
+void ath9k_htc_reset(struct ath9k_htc_priv *priv);
+
 void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv);
 void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
                              struct ieee80211_vif *vif);
@@ -435,6 +436,7 @@ void ath9k_htc_beaconep(void *drv_priv, struct sk_buff *skb,
 void ath9k_htc_station_work(struct work_struct *work);
 void ath9k_htc_aggr_work(struct work_struct *work);
 void ath9k_ani_work(struct work_struct *work);;
+void ath_start_ani(struct ath9k_htc_priv *priv);
 
 int ath9k_tx_init(struct ath9k_htc_priv *priv);
 void ath9k_tx_tasklet(unsigned long data);
@@ -457,13 +459,18 @@ void ath9k_htc_ps_restore(struct ath9k_htc_priv *priv);
 void ath9k_ps_work(struct work_struct *work);
 bool ath9k_htc_setpower(struct ath9k_htc_priv *priv,
                         enum ath9k_power_mode mode);
+void ath_update_txpow(struct ath9k_htc_priv *priv);
 
 void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv);
+void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw);
+void ath9k_htc_radio_enable(struct ieee80211_hw *hw);
+void ath9k_htc_radio_disable(struct ieee80211_hw *hw);
+void ath9k_led_stop_brightness(struct ath9k_htc_priv *priv);
 void ath9k_init_leds(struct ath9k_htc_priv *priv);
 void ath9k_deinit_leds(struct ath9k_htc_priv *priv);
 
 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
-                           u16 devid, char *product);
+                           u16 devid, char *product, u32 drv_info);
 void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug);
 #ifdef CONFIG_PM
 void ath9k_htc_suspend(struct htc_target *htc_handle);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
index 1b72aa482ac7..87cc65a78a3f 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_beacon.c
@@ -123,11 +123,11 @@ static void ath9k_htc_beacon_config_sta(struct ath9k_htc_priv *priv,
         /* TSF out of range threshold fixed at 1 second */
         bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
 
-        ath_print(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
-        ath_print(common, ATH_DBG_BEACON,
-                  "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
-                  bs.bs_bmissthreshold, bs.bs_sleepduration,
-                  bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
+        ath_dbg(common, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
+                bs.bs_bmissthreshold, bs.bs_sleepduration,
+                bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
 
         /* Set the computed STA beacon timers */
 
@@ -154,9 +154,9 @@ static void ath9k_htc_beacon_config_adhoc(struct ath9k_htc_priv *priv,
         if (priv->op_flags & OP_ENABLE_BEACON)
                 imask |= ATH9K_INT_SWBA;
 
-        ath_print(common, ATH_DBG_BEACON,
-                  "IBSS Beacon config, intval: %d, imask: 0x%x\n",
-                  bss_conf->beacon_interval, imask);
+        ath_dbg(common, ATH_DBG_BEACON,
+                "IBSS Beacon config, intval: %d, imask: 0x%x\n",
+                bss_conf->beacon_interval, imask);
 
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
         ath9k_hw_beaconinit(priv->ah, nexttbtt, intval);
@@ -246,8 +246,8 @@ void ath9k_htc_beaconq_config(struct ath9k_htc_priv *priv)
         qi.tqi_cwmax = qi_be.tqi_cwmax;
 
         if (!ath9k_hw_set_txq_props(ah, priv->beaconq, &qi)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unable to update beacon queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(ah),
+                        "Unable to update beacon queue %u!\n", qnum);
         } else {
                 ath9k_hw_resettxqueue(ah, priv->beaconq);
         }
@@ -278,8 +278,8 @@ void ath9k_htc_beacon_config(struct ath9k_htc_priv *priv,
                 ath9k_htc_beacon_config_adhoc(priv, cur_conf);
                 break;
         default:
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unsupported beaconing mode\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unsupported beaconing mode\n");
                 return;
         }
 }
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
index 50eec9a3b88c..fe70f67aa088 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_gpio.c
@@ -1,3 +1,19 @@
+/*
+ * Copyright (c) 2010 Atheros Communications Inc.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
 #include "htc.h"
 
 /******************/
@@ -20,13 +36,13 @@ static void ath_detect_bt_priority(struct ath9k_htc_priv *priv)
                 priv->op_flags &= ~(OP_BT_PRIORITY_DETECTED | OP_BT_SCAN);
                 /* Detect if colocated bt started scanning */
                 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_SCAN_THRESHOLD) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                                  "BT scan detected");
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "BT scan detected\n");
                         priv->op_flags |= (OP_BT_SCAN |
                                          OP_BT_PRIORITY_DETECTED);
                 } else if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                                    "BT priority traffic detected");
+                        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
+                                "BT priority traffic detected\n");
                         priv->op_flags |= OP_BT_PRIORITY_DETECTED;
                 }
 
@@ -83,8 +99,8 @@ static void ath_btcoex_duty_cycle_work(struct work_struct *work)
         struct ath_common *common = ath9k_hw_common(ah);
         bool is_btscan = priv->op_flags & OP_BT_SCAN;
 
-        ath_print(common, ATH_DBG_BTCOEX,
-                  "time slice work for bt and wlan\n");
+        ath_dbg(common, ATH_DBG_BTCOEX,
+                "time slice work for bt and wlan\n");
 
         if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW || is_btscan)
                 ath9k_cmn_btcoex_bt_stomp(common, ATH_BTCOEX_STOMP_NONE);
@@ -114,8 +130,7 @@ void ath_htc_resume_btcoex_work(struct ath9k_htc_priv *priv)
         struct ath_btcoex *btcoex = &priv->btcoex;
         struct ath_hw *ah = priv->ah;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
-                  "Starting btcoex work");
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_BTCOEX, "Starting btcoex work\n");
 
         btcoex->bt_priority_cnt = 0;
         btcoex->bt_priority_time = jiffies;
@@ -132,3 +147,314 @@ void ath_htc_cancel_btcoex_work(struct ath9k_htc_priv *priv)
         cancel_delayed_work_sync(&priv->coex_period_work);
         cancel_delayed_work_sync(&priv->duty_cycle_work);
 }
+
+/*******/
+/* LED */
+/*******/
+
+static void ath9k_led_blink_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   ath9k_led_blink_work.work);
+
+        if (!(priv->op_flags & OP_LED_ASSOCIATED))
+                return;
+
+        if ((priv->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
+            (priv->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
+                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
+        else
+                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
+                                  (priv->op_flags & OP_LED_ON) ? 1 : 0);
+
+        ieee80211_queue_delayed_work(priv->hw,
+                                     &priv->ath9k_led_blink_work,
+                                     (priv->op_flags & OP_LED_ON) ?
+                                     msecs_to_jiffies(priv->led_off_duration) :
+                                     msecs_to_jiffies(priv->led_on_duration));
+
+        priv->led_on_duration = priv->led_on_cnt ?
+                max((ATH_LED_ON_DURATION_IDLE - priv->led_on_cnt), 25) :
+                ATH_LED_ON_DURATION_IDLE;
+        priv->led_off_duration = priv->led_off_cnt ?
+                max((ATH_LED_OFF_DURATION_IDLE - priv->led_off_cnt), 10) :
+                ATH_LED_OFF_DURATION_IDLE;
+        priv->led_on_cnt = priv->led_off_cnt = 0;
+
+        if (priv->op_flags & OP_LED_ON)
+                priv->op_flags &= ~OP_LED_ON;
+        else
+                priv->op_flags |= OP_LED_ON;
+}
+
+static void ath9k_led_brightness_work(struct work_struct *work)
+{
+        struct ath_led *led = container_of(work, struct ath_led,
+                                           brightness_work.work);
+        struct ath9k_htc_priv *priv = led->priv;
+
+        switch (led->brightness) {
+        case LED_OFF:
+                if (led->led_type == ATH_LED_ASSOC ||
+                    led->led_type == ATH_LED_RADIO) {
+                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
+                                          (led->led_type == ATH_LED_RADIO));
+                        priv->op_flags &= ~OP_LED_ASSOCIATED;
+                        if (led->led_type == ATH_LED_RADIO)
+                                priv->op_flags &= ~OP_LED_ON;
+                } else {
+                        priv->led_off_cnt++;
+                }
+                break;
+        case LED_FULL:
+                if (led->led_type == ATH_LED_ASSOC) {
+                        priv->op_flags |= OP_LED_ASSOCIATED;
+                        ieee80211_queue_delayed_work(priv->hw,
+                                             &priv->ath9k_led_blink_work, 0);
+                } else if (led->led_type == ATH_LED_RADIO) {
+                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
+                        priv->op_flags |= OP_LED_ON;
+                } else {
+                        priv->led_on_cnt++;
+                }
+                break;
+        default:
+                break;
+        }
+}
+
+static void ath9k_led_brightness(struct led_classdev *led_cdev,
+                                 enum led_brightness brightness)
+{
+        struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
+        struct ath9k_htc_priv *priv = led->priv;
+
+        led->brightness = brightness;
+        if (!(priv->op_flags & OP_LED_DEINIT))
+                ieee80211_queue_delayed_work(priv->hw,
+                                             &led->brightness_work, 0);
+}
+
+void ath9k_led_stop_brightness(struct ath9k_htc_priv *priv)
+{
+        cancel_delayed_work_sync(&priv->radio_led.brightness_work);
+        cancel_delayed_work_sync(&priv->assoc_led.brightness_work);
+        cancel_delayed_work_sync(&priv->tx_led.brightness_work);
+        cancel_delayed_work_sync(&priv->rx_led.brightness_work);
+}
+
+static int ath9k_register_led(struct ath9k_htc_priv *priv, struct ath_led *led,
+                              char *trigger)
+{
+        int ret;
+
+        led->priv = priv;
+        led->led_cdev.name = led->name;
+        led->led_cdev.default_trigger = trigger;
+        led->led_cdev.brightness_set = ath9k_led_brightness;
+
+        ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &led->led_cdev);
+        if (ret)
+                ath_err(ath9k_hw_common(priv->ah),
+                        "Failed to register led:%s", led->name);
+        else
+                led->registered = 1;
+
+        INIT_DELAYED_WORK(&led->brightness_work, ath9k_led_brightness_work);
+
+        return ret;
+}
+
+static void ath9k_unregister_led(struct ath_led *led)
+{
+        if (led->registered) {
+                led_classdev_unregister(&led->led_cdev);
+                led->registered = 0;
+        }
+}
+
+void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
+{
+        priv->op_flags |= OP_LED_DEINIT;
+        ath9k_unregister_led(&priv->assoc_led);
+        priv->op_flags &= ~OP_LED_ASSOCIATED;
+        ath9k_unregister_led(&priv->tx_led);
+        ath9k_unregister_led(&priv->rx_led);
+        ath9k_unregister_led(&priv->radio_led);
+}
+
+void ath9k_init_leds(struct ath9k_htc_priv *priv)
+{
+        char *trigger;
+        int ret;
+
+        if (AR_SREV_9287(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_9287;
+        else if (AR_SREV_9271(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_9271;
+        else if (AR_DEVID_7010(priv->ah))
+                priv->ah->led_pin = ATH_LED_PIN_7010;
+        else
+                priv->ah->led_pin = ATH_LED_PIN_DEF;
+
+        /* Configure gpio 1 for output */
+        ath9k_hw_cfg_output(priv->ah, priv->ah->led_pin,
+                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+        /* LED off, active low */
+        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
+
+        INIT_DELAYED_WORK(&priv->ath9k_led_blink_work, ath9k_led_blink_work);
+
+        trigger = ieee80211_get_radio_led_name(priv->hw);
+        snprintf(priv->radio_led.name, sizeof(priv->radio_led.name),
+                "ath9k-%s::radio", wiphy_name(priv->hw->wiphy));
+        ret = ath9k_register_led(priv, &priv->radio_led, trigger);
+        priv->radio_led.led_type = ATH_LED_RADIO;
+        if (ret)
+                goto fail;
+
+        trigger = ieee80211_get_assoc_led_name(priv->hw);
+        snprintf(priv->assoc_led.name, sizeof(priv->assoc_led.name),
+                "ath9k-%s::assoc", wiphy_name(priv->hw->wiphy));
+        ret = ath9k_register_led(priv, &priv->assoc_led, trigger);
+        priv->assoc_led.led_type = ATH_LED_ASSOC;
+        if (ret)
+                goto fail;
+
+        trigger = ieee80211_get_tx_led_name(priv->hw);
+        snprintf(priv->tx_led.name, sizeof(priv->tx_led.name),
+                "ath9k-%s::tx", wiphy_name(priv->hw->wiphy));
+        ret = ath9k_register_led(priv, &priv->tx_led, trigger);
+        priv->tx_led.led_type = ATH_LED_TX;
+        if (ret)
+                goto fail;
+
+        trigger = ieee80211_get_rx_led_name(priv->hw);
+        snprintf(priv->rx_led.name, sizeof(priv->rx_led.name),
+                "ath9k-%s::rx", wiphy_name(priv->hw->wiphy));
+        ret = ath9k_register_led(priv, &priv->rx_led, trigger);
+        priv->rx_led.led_type = ATH_LED_RX;
+        if (ret)
+                goto fail;
+
+        priv->op_flags &= ~OP_LED_DEINIT;
+
+        return;
+
+fail:
+        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
+        ath9k_deinit_leds(priv);
+}
+
+/*******************/
+/*      Rfkill     */
+/*******************/
+
+static bool ath_is_rfkill_set(struct ath9k_htc_priv *priv)
+{
+        return ath9k_hw_gpio_get(priv->ah, priv->ah->rfkill_gpio) ==
+                priv->ah->rfkill_polarity;
+}
+
+void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        bool blocked = !!ath_is_rfkill_set(priv);
+
+        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
+}
+
+void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
+{
+        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
+                wiphy_rfkill_start_polling(priv->hw->wiphy);
+}
+
+void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret;
+        u8 cmd_rsp;
+
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        /* Reset the HW */
+        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, ah->curchan->channel);
+        }
+
+        ath_update_txpow(priv);
+
+        /* Start RX */
+        WMI_CMD(WMI_START_RECV_CMDID);
+        ath9k_host_rx_init(priv);
+
+        /* Start TX */
+        htc_start(priv->htc);
+        spin_lock_bh(&priv->tx_lock);
+        priv->tx_queues_stop = false;
+        spin_unlock_bh(&priv->tx_lock);
+        ieee80211_wake_queues(hw);
+
+        WMI_CMD(WMI_ENABLE_INTR_CMDID);
+
+        /* Enable LED */
+        ath9k_hw_cfg_output(ah, ah->led_pin,
+                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
+        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
+}
+
+void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
+{
+        struct ath9k_htc_priv *priv = hw->priv;
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        int ret;
+        u8 cmd_rsp;
+
+        ath9k_htc_ps_wakeup(priv);
+
+        /* Disable LED */
+        ath9k_hw_set_gpio(ah, ah->led_pin, 1);
+        ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
+
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+
+        /* Stop TX */
+        ieee80211_stop_queues(hw);
+        htc_stop(priv->htc);
+        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
+        skb_queue_purge(&priv->tx_queue);
+
+        /* Stop RX */
+        WMI_CMD(WMI_STOP_RECV_CMDID);
+
+        /*
+         * The MIB counters have to be disabled here,
+         * since the target doesn't do it.
+         */
+        ath9k_hw_disable_mib_counters(ah);
+
+        if (!ah->curchan)
+                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
+
+        /* Reset the HW */
+        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, ah->curchan->channel);
+        }
+
+        /* Disable the PHY */
+        ath9k_hw_phy_disable(ah);
+
+        ath9k_htc_ps_restore(priv);
+        ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
+}
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index 8776f49ffd41..38433f9bfe59 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_init.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
@@ -142,7 +142,7 @@ static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
 {
         ath9k_htc_exit_debug(priv->ah);
         ath9k_hw_deinit(priv->ah);
-        tasklet_kill(&priv->wmi_tasklet);
+        tasklet_kill(&priv->swba_tasklet);
         tasklet_kill(&priv->rx_tasklet);
         tasklet_kill(&priv->tx_tasklet);
         kfree(priv->ah);
@@ -181,7 +181,8 @@ static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
         return htc_connect_service(priv->htc, &req, ep_id);
 }
 
-static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
+static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
+                                   u32 drv_info)
 {
         int ret;
 
@@ -245,17 +246,10 @@ static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid)
          * the HIF layer, shouldn't matter much.
          */
 
-        switch(devid) {
-        case 0x7010:
-        case 0x7015:
-        case 0x9018:
-        case 0xA704:
-        case 0x1200:
+        if (IS_AR7010_DEVICE(drv_info))
                 priv->htc->credits = 45;
-                break;
-        default:
+        else
                 priv->htc->credits = 33;
-        }
 
         ret = htc_init(priv->htc);
         if (ret)
@@ -294,9 +288,9 @@ static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
                           (u8 *) &val, sizeof(val),
                           100);
         if (unlikely(r)) {
-                ath_print(common, ATH_DBG_WMI,
-                          "REGISTER READ FAILED: (0x%04x, %d)\n",
-                           reg_offset, r);
+                ath_dbg(common, ATH_DBG_WMI,
+                        "REGISTER READ FAILED: (0x%04x, %d)\n",
+                        reg_offset, r);
                 return -EIO;
         }
 
@@ -308,7 +302,7 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
         struct ath_hw *ah = (struct ath_hw *) hw_priv;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
-        __be32 buf[2] = {
+        const __be32 buf[2] = {
                 cpu_to_be32(reg_offset),
                 cpu_to_be32(val),
         };
@@ -319,9 +313,9 @@ static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
                           (u8 *) &val, sizeof(val),
                           100);
         if (unlikely(r)) {
-                ath_print(common, ATH_DBG_WMI,
-                          "REGISTER WRITE FAILED:(0x%04x, %d)\n",
-                          reg_offset, r);
+                ath_dbg(common, ATH_DBG_WMI,
+                        "REGISTER WRITE FAILED:(0x%04x, %d)\n",
+                        reg_offset, r);
         }
 }
 
@@ -351,9 +345,9 @@ static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
                           (u8 *) &rsp_status, sizeof(rsp_status),
                           100);
                 if (unlikely(r)) {
-                        ath_print(common, ATH_DBG_WMI,
-                                  "REGISTER WRITE FAILED, multi len: %d\n",
-                                  priv->wmi->multi_write_idx);
+                        ath_dbg(common, ATH_DBG_WMI,
+                                "REGISTER WRITE FAILED, multi len: %d\n",
+                                priv->wmi->multi_write_idx);
                 }
                 priv->wmi->multi_write_idx = 0;
         }
@@ -401,9 +395,9 @@ static void ath9k_regwrite_flush(void *hw_priv)
                           (u8 *) &rsp_status, sizeof(rsp_status),
                           100);
                 if (unlikely(r)) {
-                        ath_print(common, ATH_DBG_WMI,
-                                  "REGISTER WRITE FAILED, multi len: %d\n",
-                                  priv->wmi->multi_write_idx);
+                        ath_dbg(common, ATH_DBG_WMI,
+                                "REGISTER WRITE FAILED, multi len: %d\n",
+                                priv->wmi->multi_write_idx);
                 }
                 priv->wmi->multi_write_idx = 0;
         }
@@ -475,9 +469,9 @@ static void setup_ht_cap(struct ath9k_htc_priv *priv,
         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2);
         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "TX streams %d, RX streams: %d\n",
-                  tx_streams, rx_streams);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "TX streams %d, RX streams: %d\n",
+                tx_streams, rx_streams);
 
         if (tx_streams != rx_streams) {
                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -501,37 +495,31 @@ static int ath9k_init_queues(struct ath9k_htc_priv *priv)
 
         priv->beaconq = ath9k_hw_beaconq_setup(priv->ah);
         if (priv->beaconq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup BEACON xmit queue\n");
+                ath_err(common, "Unable to setup BEACON xmit queue\n");
                 goto err;
         }
 
         priv->cabq = ath9k_htc_cabq_setup(priv);
         if (priv->cabq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup CAB xmit queue\n");
+                ath_err(common, "Unable to setup CAB xmit queue\n");
                 goto err;
         }
 
         if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BE traffic\n");
+                ath_err(common, "Unable to setup xmit queue for BE traffic\n");
                 goto err;
         }
 
         if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BK traffic\n");
+                ath_err(common, "Unable to setup xmit queue for BK traffic\n");
                 goto err;
         }
         if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VI traffic\n");
+                ath_err(common, "Unable to setup xmit queue for VI traffic\n");
                 goto err;
         }
         if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VO traffic\n");
+                ath_err(common, "Unable to setup xmit queue for VO traffic\n");
                 goto err;
         }
 
@@ -549,9 +537,9 @@ static void ath9k_init_crypto(struct ath9k_htc_priv *priv)
         /* Get the hardware key cache size. */
         common->keymax = priv->ah->caps.keycache_size;
         if (common->keymax > ATH_KEYMAX) {
-                ath_print(common, ATH_DBG_ANY,
-                          "Warning, using only %u entries in %u key cache\n",
-                          ATH_KEYMAX, common->keymax);
+                ath_dbg(common, ATH_DBG_ANY,
+                        "Warning, using only %u entries in %u key cache\n",
+                        ATH_KEYMAX, common->keymax);
                 common->keymax = ATH_KEYMAX;
         }
 
@@ -627,7 +615,8 @@ static void ath9k_init_btcoex(struct ath9k_htc_priv *priv)
 }
 
 static int ath9k_init_priv(struct ath9k_htc_priv *priv,
-                           u16 devid, char *product)
+                           u16 devid, char *product,
+                           u32 drv_info)
 {
         struct ath_hw *ah = NULL;
         struct ath_common *common;
@@ -641,6 +630,8 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
 
         ah->hw_version.devid = devid;
         ah->hw_version.subsysid = 0; /* FIXME */
+        ah->hw_version.usbdev = drv_info;
+        ah->ah_flags |= AH_USE_EEPROM;
         priv->ah = ah;
 
         common = ath9k_hw_common(ah);
@@ -656,13 +647,15 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
         spin_lock_init(&priv->tx_lock);
         mutex_init(&priv->mutex);
         mutex_init(&priv->htc_pm_lock);
-        tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet,
+        tasklet_init(&priv->swba_tasklet, ath9k_swba_tasklet,
                      (unsigned long)priv);
         tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
                      (unsigned long)priv);
-        tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv);
+        tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet,
+                     (unsigned long)priv);
         INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work);
         INIT_WORK(&priv->ps_work, ath9k_ps_work);
+        INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
 
         /*
          * Cache line size is used to size and align various
@@ -673,16 +666,15 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
 
         ret = ath9k_hw_init(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize hardware; "
-                          "initialization status: %d\n", ret);
+                ath_err(common,
+                        "Unable to initialize hardware; initialization status: %d\n",
+                        ret);
                 goto err_hw;
         }
 
         ret = ath9k_htc_init_debug(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to create debugfs files\n");
+                ath_err(common, "Unable to create debugfs files\n");
                 goto err_debug;
         }
 
@@ -762,7 +754,7 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
 }
 
 static int ath9k_init_device(struct ath9k_htc_priv *priv,
-                             u16 devid, char *product)
+                             u16 devid, char *product, u32 drv_info)
 {
         struct ieee80211_hw *hw = priv->hw;
         struct ath_common *common;
@@ -771,7 +763,7 @@ static int ath9k_init_device(struct ath9k_htc_priv *priv,
         struct ath_regulatory *reg;
 
         /* Bring up device */
-        error = ath9k_init_priv(priv, devid, product);
+        error = ath9k_init_priv(priv, devid, product, drv_info);
         if (error != 0)
                 goto err_init;
 
@@ -829,7 +821,7 @@ err_init:
 }
 
 int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
-                           u16 devid, char *product)
+                           u16 devid, char *product, u32 drv_info)
 {
         struct ieee80211_hw *hw;
         struct ath9k_htc_priv *priv;
@@ -856,14 +848,11 @@ int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
                 goto err_free;
         }
 
-        ret = ath9k_init_htc_services(priv, devid);
+        ret = ath9k_init_htc_services(priv, devid, drv_info);
         if (ret)
                 goto err_init;
 
-        /* The device may have been unplugged earlier. */
-        priv->op_flags &= ~OP_UNPLUGGED;
-
-        ret = ath9k_init_device(priv, devid, product);
+        ret = ath9k_init_device(priv, devid, product, drv_info);
         if (ret)
                 goto err_init;
 
@@ -882,7 +871,7 @@ void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
 
                 /* Check if the device has been yanked out. */
                 if (hotunplug)
-                        htc_handle->drv_priv->op_flags |= OP_UNPLUGGED;
+                        htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
 
                 ath9k_deinit_device(htc_handle->drv_priv);
                 ath9k_deinit_wmi(htc_handle->drv_priv);
@@ -899,14 +888,15 @@ void ath9k_htc_suspend(struct htc_target *htc_handle)
 
 int ath9k_htc_resume(struct htc_target *htc_handle)
 {
+        struct ath9k_htc_priv *priv = htc_handle->drv_priv;
         int ret;
 
-        ret = ath9k_htc_wait_for_target(htc_handle->drv_priv);
+        ret = ath9k_htc_wait_for_target(priv);
         if (ret)
                 return ret;
 
-        ret = ath9k_init_htc_services(htc_handle->drv_priv,
-                              htc_handle->drv_priv->ah->hw_version.devid);
+        ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
+                                      priv->ah->hw_version.usbdev);
         return ret;
 }
 #endif
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_main.c b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
index 51977caca47f..845b4c938d16 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_main.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_main.c
@@ -24,12 +24,12 @@ static struct dentry *ath9k_debugfs_root;
 /* Utilities */
 /*************/
 
-static void ath_update_txpow(struct ath9k_htc_priv *priv)
+void ath_update_txpow(struct ath9k_htc_priv *priv)
 {
         struct ath_hw *ah = priv->ah;
 
         if (priv->curtxpow != priv->txpowlimit) {
-                ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit);
+                ath9k_hw_set_txpowerlimit(ah, priv->txpowlimit, false);
                 /* read back in case value is clamped */
                 priv->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
         }
@@ -116,6 +116,60 @@ void ath9k_ps_work(struct work_struct *work)
         ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
 }
 
+void ath9k_htc_reset(struct ath9k_htc_priv *priv)
+{
+        struct ath_hw *ah = priv->ah;
+        struct ath_common *common = ath9k_hw_common(ah);
+        struct ieee80211_channel *channel = priv->hw->conf.channel;
+        struct ath9k_hw_cal_data *caldata;
+        enum htc_phymode mode;
+        __be16 htc_mode;
+        u8 cmd_rsp;
+        int ret;
+
+        mutex_lock(&priv->mutex);
+        ath9k_htc_ps_wakeup(priv);
+
+        if (priv->op_flags & OP_ASSOCIATED)
+                cancel_delayed_work_sync(&priv->ath9k_ani_work);
+
+        ieee80211_stop_queues(priv->hw);
+        htc_stop(priv->htc);
+        WMI_CMD(WMI_DISABLE_INTR_CMDID);
+        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
+        WMI_CMD(WMI_STOP_RECV_CMDID);
+
+        caldata = &priv->caldata[channel->hw_value];
+        ret = ath9k_hw_reset(ah, ah->curchan, caldata, false);
+        if (ret) {
+                ath_err(common,
+                        "Unable to reset device (%u Mhz) reset status %d\n",
+                        channel->center_freq, ret);
+        }
+
+        ath_update_txpow(priv);
+
+        WMI_CMD(WMI_START_RECV_CMDID);
+        ath9k_host_rx_init(priv);
+
+        mode = ath9k_htc_get_curmode(priv, ah->curchan);
+        htc_mode = cpu_to_be16(mode);
+        WMI_CMD_BUF(WMI_SET_MODE_CMDID, &htc_mode);
+
+        WMI_CMD(WMI_ENABLE_INTR_CMDID);
+        htc_start(priv->htc);
+
+        if (priv->op_flags & OP_ASSOCIATED) {
+                ath9k_htc_beacon_config(priv, priv->vif);
+                ath_start_ani(priv);
+        }
+
+        ieee80211_wake_queues(priv->hw);
+
+        ath9k_htc_ps_restore(priv);
+        mutex_unlock(&priv->mutex);
+}
+
 static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
                                  struct ieee80211_hw *hw,
                                  struct ath9k_channel *hchan)
@@ -123,7 +177,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         struct ath_hw *ah = priv->ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ieee80211_conf *conf = &common->hw->conf;
-        bool fastcc = true;
+        bool fastcc;
         struct ieee80211_channel *channel = hw->conf.channel;
         struct ath9k_hw_cal_data *caldata;
         enum htc_phymode mode;
@@ -134,8 +188,7 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         if (priv->op_flags & OP_INVALID)
                 return -EIO;
 
-        if (priv->op_flags & OP_FULL_RESET)
-                fastcc = false;
+        fastcc = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
 
         ath9k_htc_ps_wakeup(priv);
         htc_stop(priv->htc);
@@ -143,18 +196,18 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
         WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
         WMI_CMD(WMI_STOP_RECV_CMDID);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n",
-                  priv->ah->curchan->channel,
-                  channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf),
-                  fastcc);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "(%u MHz) -> (%u MHz), HT: %d, HT40: %d fastcc: %d\n",
+                priv->ah->curchan->channel,
+                channel->center_freq, conf_is_ht(conf), conf_is_ht40(conf),
+                fastcc);
 
         caldata = &priv->caldata[channel->hw_value];
         ret = ath9k_hw_reset(ah, hchan, caldata, fastcc);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u Mhz) "
-                          "reset status %d\n", channel->center_freq, ret);
+                ath_err(common,
+                        "Unable to reset channel (%u Mhz) reset status %d\n",
+                        channel->center_freq, ret);
                 goto err;
         }
 
@@ -177,23 +230,43 @@ static int ath9k_htc_set_channel(struct ath9k_htc_priv *priv,
                 goto err;
 
         htc_start(priv->htc);
-
-        priv->op_flags &= ~OP_FULL_RESET;
 err:
         ath9k_htc_ps_restore(priv);
         return ret;
 }
 
+static void __ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv)
+{
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+        struct ath9k_htc_target_vif hvif;
+        int ret = 0;
+        u8 cmd_rsp;
+
+        memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
+        memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
+        hvif.index = 0; /* Should do for now */
+        WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
+        priv->nvifs--;
+}
+
 static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         struct ath9k_htc_target_vif hvif;
+        struct ath9k_htc_target_sta tsta;
         int ret = 0;
         u8 cmd_rsp;
 
         if (priv->nvifs > 0)
                 return -ENOBUFS;
 
+        if (priv->nstations >= ATH9K_HTC_MAX_STA)
+                return -ENOBUFS;
+
+        /*
+         * Add an interface.
+         */
+
         memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
         memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
 
@@ -206,23 +279,57 @@ static int ath9k_htc_add_monitor_interface(struct ath9k_htc_priv *priv)
                 return ret;
 
         priv->nvifs++;
+
+        /*
+         * Associate a station with the interface for packet injection.
+         */
+
+        memset(&tsta, 0, sizeof(struct ath9k_htc_target_sta));
+
+        memcpy(&tsta.macaddr, common->macaddr, ETH_ALEN);
+
+        tsta.is_vif_sta = 1;
+        tsta.sta_index = priv->nstations;
+        tsta.vif_index = hvif.index;
+        tsta.maxampdu = 0xffff;
+
+        WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
+        if (ret) {
+                ath_err(common, "Unable to add station entry for monitor mode\n");
+                goto err_vif;
+        }
+
+        priv->nstations++;
+
         return 0;
+
+err_vif:
+        /*
+         * Remove the interface from the target.
+         */
+        __ath9k_htc_remove_monitor_interface(priv);
+        return ret;
 }
 
 static int ath9k_htc_remove_monitor_interface(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
-        struct ath9k_htc_target_vif hvif;
         int ret = 0;
-        u8 cmd_rsp;
+        u8 cmd_rsp, sta_idx;
 
-        memset(&hvif, 0, sizeof(struct ath9k_htc_target_vif));
-        memcpy(&hvif.myaddr, common->macaddr, ETH_ALEN);
-        hvif.index = 0; /* Should do for now */
-        WMI_CMD_BUF(WMI_VAP_REMOVE_CMDID, &hvif);
-        priv->nvifs--;
+        __ath9k_htc_remove_monitor_interface(priv);
 
-        return ret;
+        sta_idx = 0; /* Only single interface, for now */
+
+        WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
+        if (ret) {
+                ath_err(common, "Unable to remove station entry for monitor mode\n");
+                return ret;
+        }
+
+        priv->nstations--;
+
+        return 0;
 }
 
 static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
@@ -263,15 +370,16 @@ static int ath9k_htc_add_station(struct ath9k_htc_priv *priv,
         WMI_CMD_BUF(WMI_NODE_CREATE_CMDID, &tsta);
         if (ret) {
                 if (sta)
-                        ath_print(common, ATH_DBG_FATAL,
-                          "Unable to add station entry for: %pM\n", sta->addr);
+                        ath_err(common,
+                                "Unable to add station entry for: %pM\n",
+                                sta->addr);
                 return ret;
         }
 
         if (sta)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Added a station entry for: %pM (idx: %d)\n",
-                          sta->addr, tsta.sta_index);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Added a station entry for: %pM (idx: %d)\n",
+                        sta->addr, tsta.sta_index);
 
         priv->nstations++;
         return 0;
@@ -296,16 +404,16 @@ static int ath9k_htc_remove_station(struct ath9k_htc_priv *priv,
         WMI_CMD_BUF(WMI_NODE_REMOVE_CMDID, &sta_idx);
         if (ret) {
                 if (sta)
-                        ath_print(common, ATH_DBG_FATAL,
-                          "Unable to remove station entry for: %pM\n",
-                          sta->addr);
+                        ath_err(common,
+                                "Unable to remove station entry for: %pM\n",
+                                sta->addr);
                 return ret;
         }
 
         if (sta)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Removed a station entry for: %pM (idx: %d)\n",
-                          sta->addr, sta_idx);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Removed a station entry for: %pM (idx: %d)\n",
+                        sta->addr, sta_idx);
 
         priv->nstations--;
         return 0;
@@ -390,8 +498,8 @@ static int ath9k_htc_send_rate_cmd(struct ath9k_htc_priv *priv,
 
         WMI_CMD_BUF(WMI_RC_RATE_UPDATE_CMDID, trate);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize Rate information on target\n");
+                ath_err(common,
+                        "Unable to initialize Rate information on target\n");
         }
 
         return ret;
@@ -408,9 +516,9 @@ static void ath9k_htc_init_rate(struct ath9k_htc_priv *priv,
         ath9k_htc_setup_rate(priv, sta, &trate);
         ret = ath9k_htc_send_rate_cmd(priv, &trate);
         if (!ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Updated target sta: %pM, rate caps: 0x%X\n",
-                          sta->addr, be32_to_cpu(trate.capflags));
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Updated target sta: %pM, rate caps: 0x%X\n",
+                        sta->addr, be32_to_cpu(trate.capflags));
 }
 
 static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
@@ -435,9 +543,9 @@ static void ath9k_htc_update_rate(struct ath9k_htc_priv *priv,
 
         ret = ath9k_htc_send_rate_cmd(priv, &trate);
         if (!ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Updated target sta: %pM, rate caps: 0x%X\n",
-                          bss_conf->bssid, be32_to_cpu(trate.capflags));
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Updated target sta: %pM, rate caps: 0x%X\n",
+                        bss_conf->bssid, be32_to_cpu(trate.capflags));
 }
 
 static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
@@ -464,14 +572,14 @@ static int ath9k_htc_tx_aggr_oper(struct ath9k_htc_priv *priv,
 
         WMI_CMD_BUF(WMI_TX_AGGR_ENABLE_CMDID, &aggr);
         if (ret)
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Unable to %s TX aggregation for (%pM, %d)\n",
-                          (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Unable to %s TX aggregation for (%pM, %d)\n",
+                        (aggr.aggr_enable) ? "start" : "stop", sta->addr, tid);
         else
-                ath_print(common, ATH_DBG_CONFIG,
-                          "%s TX aggregation for (%pM, %d)\n",
-                          (aggr.aggr_enable) ? "Starting" : "Stopping",
-                          sta->addr, tid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "%s TX aggregation for (%pM, %d)\n",
+                        (aggr.aggr_enable) ? "Starting" : "Stopping",
+                        sta->addr, tid);
 
         spin_lock_bh(&priv->tx_lock);
         ista->tid_state[tid] = (aggr.aggr_enable && !ret) ? AGGR_START : AGGR_STOP;
@@ -689,7 +797,7 @@ void ath9k_htc_debug_remove_root(void)
 /* ANI */
 /*******/
 
-static void ath_start_ani(struct ath9k_htc_priv *priv)
+void ath_start_ani(struct ath9k_htc_priv *priv)
 {
         struct ath_common *common = ath9k_hw_common(priv->ah);
         unsigned long timestamp = jiffies_to_msecs(jiffies);
@@ -724,7 +832,7 @@ void ath9k_ani_work(struct work_struct *work)
         /* Long calibration runs independently of short calibration. */
         if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
                 longcal = true;
-                ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
+                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -733,8 +841,8 @@ void ath9k_ani_work(struct work_struct *work)
                 if ((timestamp - common->ani.shortcal_timer) >=
                     short_cal_interval) {
                         shortcal = true;
-                        ath_print(common, ATH_DBG_ANI,
-                                  "shortcal @%lu\n", jiffies);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -788,317 +896,6 @@ set_timer:
                                      msecs_to_jiffies(cal_interval));
 }
 
-/*******/
-/* LED */
-/*******/
-
-static void ath9k_led_blink_work(struct work_struct *work)
-{
-        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
-                                                   ath9k_led_blink_work.work);
-
-        if (!(priv->op_flags & OP_LED_ASSOCIATED))
-                return;
-
-        if ((priv->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
-            (priv->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
-                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
-        else
-                ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
-                                  (priv->op_flags & OP_LED_ON) ? 1 : 0);
-
-        ieee80211_queue_delayed_work(priv->hw,
-                                     &priv->ath9k_led_blink_work,
-                                     (priv->op_flags & OP_LED_ON) ?
-                                     msecs_to_jiffies(priv->led_off_duration) :
-                                     msecs_to_jiffies(priv->led_on_duration));
-
-        priv->led_on_duration = priv->led_on_cnt ?
-                max((ATH_LED_ON_DURATION_IDLE - priv->led_on_cnt), 25) :
-                ATH_LED_ON_DURATION_IDLE;
-        priv->led_off_duration = priv->led_off_cnt ?
-                max((ATH_LED_OFF_DURATION_IDLE - priv->led_off_cnt), 10) :
-                ATH_LED_OFF_DURATION_IDLE;
-        priv->led_on_cnt = priv->led_off_cnt = 0;
-
-        if (priv->op_flags & OP_LED_ON)
-                priv->op_flags &= ~OP_LED_ON;
-        else
-                priv->op_flags |= OP_LED_ON;
-}
-
-static void ath9k_led_brightness_work(struct work_struct *work)
-{
-        struct ath_led *led = container_of(work, struct ath_led,
-                                           brightness_work.work);
-        struct ath9k_htc_priv *priv = led->priv;
-
-        switch (led->brightness) {
-        case LED_OFF:
-                if (led->led_type == ATH_LED_ASSOC ||
-                    led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin,
-                                          (led->led_type == ATH_LED_RADIO));
-                        priv->op_flags &= ~OP_LED_ASSOCIATED;
-                        if (led->led_type == ATH_LED_RADIO)
-                                priv->op_flags &= ~OP_LED_ON;
-                } else {
-                        priv->led_off_cnt++;
-                }
-                break;
-        case LED_FULL:
-                if (led->led_type == ATH_LED_ASSOC) {
-                        priv->op_flags |= OP_LED_ASSOCIATED;
-                        ieee80211_queue_delayed_work(priv->hw,
-                                             &priv->ath9k_led_blink_work, 0);
-                } else if (led->led_type == ATH_LED_RADIO) {
-                        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 0);
-                        priv->op_flags |= OP_LED_ON;
-                } else {
-                        priv->led_on_cnt++;
-                }
-                break;
-        default:
-                break;
-        }
-}
-
-static void ath9k_led_brightness(struct led_classdev *led_cdev,
-                                 enum led_brightness brightness)
-{
-        struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
-        struct ath9k_htc_priv *priv = led->priv;
-
-        led->brightness = brightness;
-        if (!(priv->op_flags & OP_LED_DEINIT))
-                ieee80211_queue_delayed_work(priv->hw,
-                                             &led->brightness_work, 0);
-}
-
-static void ath9k_led_stop_brightness(struct ath9k_htc_priv *priv)
-{
-        cancel_delayed_work_sync(&priv->radio_led.brightness_work);
-        cancel_delayed_work_sync(&priv->assoc_led.brightness_work);
-        cancel_delayed_work_sync(&priv->tx_led.brightness_work);
-        cancel_delayed_work_sync(&priv->rx_led.brightness_work);
-}
-
-static int ath9k_register_led(struct ath9k_htc_priv *priv, struct ath_led *led,
-                              char *trigger)
-{
-        int ret;
-
-        led->priv = priv;
-        led->led_cdev.name = led->name;
-        led->led_cdev.default_trigger = trigger;
-        led->led_cdev.brightness_set = ath9k_led_brightness;
-
-        ret = led_classdev_register(wiphy_dev(priv->hw->wiphy), &led->led_cdev);
-        if (ret)
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL,
-                          "Failed to register led:%s", led->name);
-        else
-                led->registered = 1;
-
-        INIT_DELAYED_WORK(&led->brightness_work, ath9k_led_brightness_work);
-
-        return ret;
-}
-
-static void ath9k_unregister_led(struct ath_led *led)
-{
-        if (led->registered) {
-                led_classdev_unregister(&led->led_cdev);
-                led->registered = 0;
-        }
-}
-
-void ath9k_deinit_leds(struct ath9k_htc_priv *priv)
-{
-        priv->op_flags |= OP_LED_DEINIT;
-        ath9k_unregister_led(&priv->assoc_led);
-        priv->op_flags &= ~OP_LED_ASSOCIATED;
-        ath9k_unregister_led(&priv->tx_led);
-        ath9k_unregister_led(&priv->rx_led);
-        ath9k_unregister_led(&priv->radio_led);
-}
-
-void ath9k_init_leds(struct ath9k_htc_priv *priv)
-{
-        char *trigger;
-        int ret;
-
-        if (AR_SREV_9287(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_9287;
-        else if (AR_SREV_9271(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_9271;
-        else if (AR_DEVID_7010(priv->ah))
-                priv->ah->led_pin = ATH_LED_PIN_7010;
-        else
-                priv->ah->led_pin = ATH_LED_PIN_DEF;
-
-        /* Configure gpio 1 for output */
-        ath9k_hw_cfg_output(priv->ah, priv->ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        /* LED off, active low */
-        ath9k_hw_set_gpio(priv->ah, priv->ah->led_pin, 1);
-
-        INIT_DELAYED_WORK(&priv->ath9k_led_blink_work, ath9k_led_blink_work);
-
-        trigger = ieee80211_get_radio_led_name(priv->hw);
-        snprintf(priv->radio_led.name, sizeof(priv->radio_led.name),
-                "ath9k-%s::radio", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->radio_led, trigger);
-        priv->radio_led.led_type = ATH_LED_RADIO;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_assoc_led_name(priv->hw);
-        snprintf(priv->assoc_led.name, sizeof(priv->assoc_led.name),
-                "ath9k-%s::assoc", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->assoc_led, trigger);
-        priv->assoc_led.led_type = ATH_LED_ASSOC;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_tx_led_name(priv->hw);
-        snprintf(priv->tx_led.name, sizeof(priv->tx_led.name),
-                "ath9k-%s::tx", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->tx_led, trigger);
-        priv->tx_led.led_type = ATH_LED_TX;
-        if (ret)
-                goto fail;
-
-        trigger = ieee80211_get_rx_led_name(priv->hw);
-        snprintf(priv->rx_led.name, sizeof(priv->rx_led.name),
-                "ath9k-%s::rx", wiphy_name(priv->hw->wiphy));
-        ret = ath9k_register_led(priv, &priv->rx_led, trigger);
-        priv->rx_led.led_type = ATH_LED_RX;
-        if (ret)
-                goto fail;
-
-        priv->op_flags &= ~OP_LED_DEINIT;
-
-        return;
-
-fail:
-        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
-        ath9k_deinit_leds(priv);
-}
-
-/*******************/
-/*      Rfkill     */
-/*******************/
-
-static bool ath_is_rfkill_set(struct ath9k_htc_priv *priv)
-{
-        return ath9k_hw_gpio_get(priv->ah, priv->ah->rfkill_gpio) ==
-                priv->ah->rfkill_polarity;
-}
-
-static void ath9k_htc_rfkill_poll_state(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        bool blocked = !!ath_is_rfkill_set(priv);
-
-        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
-}
-
-void ath9k_start_rfkill_poll(struct ath9k_htc_priv *priv)
-{
-        if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
-                wiphy_rfkill_start_polling(priv->hw->wiphy);
-}
-
-static void ath9k_htc_radio_enable(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        int ret;
-        u8 cmd_rsp;
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        /* Reset the HW */
-        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, ah->curchan->channel);
-        }
-
-        ath_update_txpow(priv);
-
-        /* Start RX */
-        WMI_CMD(WMI_START_RECV_CMDID);
-        ath9k_host_rx_init(priv);
-
-        /* Start TX */
-        htc_start(priv->htc);
-        spin_lock_bh(&priv->tx_lock);
-        priv->tx_queues_stop = false;
-        spin_unlock_bh(&priv->tx_lock);
-        ieee80211_wake_queues(hw);
-
-        WMI_CMD(WMI_ENABLE_INTR_CMDID);
-
-        /* Enable LED */
-        ath9k_hw_cfg_output(ah, ah->led_pin,
-                            AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
-        ath9k_hw_set_gpio(ah, ah->led_pin, 0);
-}
-
-static void ath9k_htc_radio_disable(struct ieee80211_hw *hw)
-{
-        struct ath9k_htc_priv *priv = hw->priv;
-        struct ath_hw *ah = priv->ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-        int ret;
-        u8 cmd_rsp;
-
-        ath9k_htc_ps_wakeup(priv);
-
-        /* Disable LED */
-        ath9k_hw_set_gpio(ah, ah->led_pin, 1);
-        ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
-
-        WMI_CMD(WMI_DISABLE_INTR_CMDID);
-
-        /* Stop TX */
-        ieee80211_stop_queues(hw);
-        htc_stop(priv->htc);
-        WMI_CMD(WMI_DRAIN_TXQ_ALL_CMDID);
-        skb_queue_purge(&priv->tx_queue);
-
-        /* Stop RX */
-        WMI_CMD(WMI_STOP_RECV_CMDID);
-
-        /*
-         * The MIB counters have to be disabled here,
-         * since the target doesn't do it.
-         */
-        ath9k_hw_disable_mib_counters(ah);
-
-        if (!ah->curchan)
-                ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
-
-        /* Reset the HW */
-        ret = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, ah->curchan->channel);
-        }
-
-        /* Disable the PHY */
-        ath9k_hw_phy_disable(ah);
-
-        ath9k_htc_ps_restore(priv);
-        ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
-}
-
 /**********************/
 /* mac80211 Callbacks */
 /**********************/
@@ -1124,15 +921,15 @@ static int ath9k_htc_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         ret = ath9k_htc_tx_start(priv, skb);
         if (ret != 0) {
                 if (ret == -ENOMEM) {
-                        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                                  "Stopping TX queues\n");
+                        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
+                                "Stopping TX queues\n");
                         ieee80211_stop_queues(hw);
                         spin_lock_bh(&priv->tx_lock);
                         priv->tx_queues_stop = true;
                         spin_unlock_bh(&priv->tx_lock);
                 } else {
-                        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                                  "Tx failed");
+                        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
+                                "Tx failed\n");
                 }
                 goto fail_tx;
         }
@@ -1158,9 +955,9 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
 
         mutex_lock(&priv->mutex);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Starting driver with initial channel: %d MHz\n",
-                  curchan->center_freq);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Starting driver with initial channel: %d MHz\n",
+                curchan->center_freq);
 
         /* Ensure that HW is awake before flushing RX */
         ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
@@ -1169,15 +966,12 @@ static int ath9k_htc_start(struct ieee80211_hw *hw)
         /* setup initial channel */
         init_channel = ath9k_cmn_get_curchannel(hw, ah);
 
-        /* Reset SERDES registers */
-        ath9k_hw_configpcipowersave(ah, 0, 0);
-
         ath9k_hw_htc_resetinit(ah);
         ret = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", ret, curchan->center_freq);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        ret, curchan->center_freq);
                 mutex_unlock(&priv->mutex);
                 return ret;
         }
@@ -1220,19 +1014,20 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
         int ret = 0;
         u8 cmd_rsp;
 
+        /* Cancel all the running timers/work .. */
+        cancel_work_sync(&priv->fatal_work);
+        cancel_work_sync(&priv->ps_work);
+        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
+        ath9k_led_stop_brightness(priv);
+
         mutex_lock(&priv->mutex);
 
         if (priv->op_flags & OP_INVALID) {
-                ath_print(common, ATH_DBG_ANY, "Device not present\n");
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&priv->mutex);
                 return;
         }
 
-        /* Cancel all the running timers/work .. */
-        cancel_work_sync(&priv->ps_work);
-        cancel_delayed_work_sync(&priv->ath9k_led_blink_work);
-        ath9k_led_stop_brightness(priv);
-
         ath9k_htc_ps_wakeup(priv);
         htc_stop(priv->htc);
         WMI_CMD(WMI_DISABLE_INTR_CMDID);
@@ -1243,11 +1038,10 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
         /* Remove monitor interface here */
         if (ah->opmode == NL80211_IFTYPE_MONITOR) {
                 if (ath9k_htc_remove_monitor_interface(priv))
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to remove monitor interface\n");
+                        ath_err(common, "Unable to remove monitor interface\n");
                 else
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "Monitor interface removed\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor interface removed\n");
         }
 
         if (ah->btcoex_hw.enabled) {
@@ -1258,13 +1052,12 @@ static void ath9k_htc_stop(struct ieee80211_hw *hw)
 
         ath9k_hw_phy_disable(ah);
         ath9k_hw_disable(ah);
-        ath9k_hw_configpcipowersave(ah, 1, 1);
         ath9k_htc_ps_restore(priv);
         ath9k_htc_setpower(priv, ATH9K_PM_FULL_SLEEP);
 
         priv->op_flags |= OP_INVALID;
 
-        ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
         mutex_unlock(&priv->mutex);
 }
 
@@ -1298,14 +1091,14 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
                 hvif.opmode = cpu_to_be32(HTC_M_IBSS);
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
+                ath_err(common,
                         "Interface type %d not yet supported\n", vif->type);
                 ret = -EOPNOTSUPP;
                 goto out;
         }
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Attach a VIF of type: %d\n", vif->type);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attach a VIF of type: %d\n", vif->type);
 
         priv->ah->opmode = vif->type;
 
@@ -1328,8 +1121,8 @@ static int ath9k_htc_add_interface(struct ieee80211_hw *hw,
 
         ret = ath9k_htc_update_cap_target(priv);
         if (ret)
-                ath_print(common, ATH_DBG_CONFIG, "Failed to update"
-                          " capability in target \n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Failed to update capability in target\n");
 
         priv->vif = vif;
 out:
@@ -1349,7 +1142,7 @@ static void ath9k_htc_remove_interface(struct ieee80211_hw *hw,
         int ret = 0;
         u8 cmd_rsp;
 
-        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
 
         mutex_lock(&priv->mutex);
         ath9k_htc_ps_wakeup(priv);
@@ -1386,8 +1179,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 mutex_unlock(&priv->htc_pm_lock);
 
                 if (enable_radio) {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "not-idle: enabling radio\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "not-idle: enabling radio\n");
                         ath9k_htc_setpower(priv, ATH9K_PM_AWAKE);
                         ath9k_htc_radio_enable(hw);
                 }
@@ -1397,19 +1190,21 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 struct ieee80211_channel *curchan = hw->conf.channel;
                 int pos = curchan->hw_value;
 
-                ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
-                          curchan->center_freq);
+                ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
+                        curchan->center_freq);
 
-                ath9k_cmn_update_ichannel(hw, &priv->ah->channels[pos]);
+                ath9k_cmn_update_ichannel(&priv->ah->channels[pos],
+                                          hw->conf.channel,
+                                          hw->conf.channel_type);
 
                 if (ath9k_htc_set_channel(priv, hw, &priv->ah->channels[pos]) < 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to set channel\n");
+                        ath_err(common, "Unable to set channel\n");
                         mutex_unlock(&priv->mutex);
                         return -EINVAL;
                 }
 
         }
+
         if (changed & IEEE80211_CONF_CHANGE_PS) {
                 if (conf->flags & IEEE80211_CONF_PS) {
                         ath9k_htc_setpower(priv, ATH9K_PM_NETWORK_SLEEP);
@@ -1421,14 +1216,18 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 }
         }
 
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                priv->txpowlimit = 2 * conf->power_level;
+                ath_update_txpow(priv);
+        }
+
         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
                 if (conf->flags & IEEE80211_CONF_MONITOR) {
                         if (ath9k_htc_add_monitor_interface(priv))
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Failed to set monitor mode\n");
+                                ath_err(common, "Failed to set monitor mode\n");
                         else
-                                ath_print(common, ATH_DBG_CONFIG,
-                                          "HW opmode set to Monitor mode\n");
+                                ath_dbg(common, ATH_DBG_CONFIG,
+                                        "HW opmode set to Monitor mode\n");
                 }
         }
 
@@ -1440,8 +1239,8 @@ static int ath9k_htc_config(struct ieee80211_hw *hw, u32 changed)
                 }
                 mutex_unlock(&priv->htc_pm_lock);
 
-                ath_print(common, ATH_DBG_CONFIG,
-                          "idle: disabling radio\n");
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "idle: disabling radio\n");
                 ath9k_htc_radio_disable(hw);
         }
 
@@ -1478,8 +1277,8 @@ static void ath9k_htc_configure_filter(struct ieee80211_hw *hw,
         rfilt = ath9k_htc_calcrxfilter(priv);
         ath9k_hw_setrxfilter(priv->ah, rfilt);
 
-        ath_print(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
-                  "Set HW RX filter: 0x%x\n", rfilt);
+        ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_CONFIG,
+                "Set HW RX filter: 0x%x\n", rfilt);
 
         ath9k_htc_ps_restore(priv);
         mutex_unlock(&priv->mutex);
@@ -1542,15 +1341,14 @@ static int ath9k_htc_conf_tx(struct ieee80211_hw *hw, u16 queue,
 
         qnum = get_hw_qnum(queue, priv->hwq_map);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Configure tx [queue/hwq] [%d/%d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, qnum, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Configure tx [queue/hwq] [%d/%d],  aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                queue, qnum, params->aifs, params->cw_min,
+                params->cw_max, params->txop);
 
         ret = ath_htc_txq_update(priv, qnum, &qi);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+                ath_err(common, "TXQ Update failed\n");
                 goto out;
         }
 
@@ -1578,7 +1376,7 @@ static int ath9k_htc_set_key(struct ieee80211_hw *hw,
                 return -ENOSPC;
 
         mutex_lock(&priv->mutex);
-        ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
         ath9k_htc_ps_wakeup(priv);
 
         switch (cmd) {
@@ -1624,7 +1422,7 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
         if (changed & BSS_CHANGED_ASSOC) {
                 common->curaid = bss_conf->assoc ?
                                  bss_conf->aid : 0;
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
                         bss_conf->assoc);
 
                 if (bss_conf->assoc) {
@@ -1641,9 +1439,9 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
                 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
                 ath9k_hw_write_associd(ah);
 
-                ath_print(common, ATH_DBG_CONFIG,
-                          "BSSID: %pM aid: 0x%x\n",
-                          common->curbssid, common->curaid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "BSSID: %pM aid: 0x%x\n",
+                        common->curbssid, common->curaid);
         }
 
         if ((changed & BSS_CHANGED_BEACON_INT) ||
@@ -1661,8 +1459,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
-                          bss_conf->use_short_preamble);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
+                        bss_conf->use_short_preamble);
                 if (bss_conf->use_short_preamble)
                         priv->op_flags |= OP_PREAMBLE_SHORT;
                 else
@@ -1670,8 +1468,8 @@ static void ath9k_htc_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
-                          bss_conf->use_cts_prot);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
+                        bss_conf->use_cts_prot);
                 if (bss_conf->use_cts_prot &&
                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
                         priv->op_flags |= OP_PROTECT_ENABLE;
@@ -1762,8 +1560,7 @@ static int ath9k_htc_ampdu_action(struct ieee80211_hw *hw,
                 spin_unlock_bh(&priv->tx_lock);
                 break;
         default:
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_FATAL,
-                          "Unknown AMPDU action\n");
+                ath_err(ath9k_hw_common(priv->ah), "Unknown AMPDU action\n");
         }
 
         return ret;
@@ -1792,7 +1589,6 @@ static void ath9k_htc_sw_scan_complete(struct ieee80211_hw *hw)
         spin_lock_bh(&priv->beacon_lock);
         priv->op_flags &= ~OP_SCANNING;
         spin_unlock_bh(&priv->beacon_lock);
-        priv->op_flags |= OP_FULL_RESET;
         if (priv->op_flags & OP_ASSOCIATED) {
                 ath9k_htc_beacon_config(priv, priv->vif);
                 ath_start_ani(priv);
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
index 29d80ca78393..33f36029fa4f 100644
--- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
+++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c
@@ -20,8 +20,15 @@
 /* TX */
 /******/
 
+static const int subtype_txq_to_hwq[] = {
+        [WME_AC_BE] = ATH_TXQ_AC_BE,
+        [WME_AC_BK] = ATH_TXQ_AC_BK,
+        [WME_AC_VI] = ATH_TXQ_AC_VI,
+        [WME_AC_VO] = ATH_TXQ_AC_VO,
+};
+
 #define ATH9K_HTC_INIT_TXQ(subtype) do {                        \
-                qi.tqi_subtype = subtype;                       \
+                qi.tqi_subtype = subtype_txq_to_hwq[subtype];   \
                 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;             \
                 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;            \
                 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;            \
@@ -62,8 +69,8 @@ int ath_htc_txq_update(struct ath9k_htc_priv *priv, int qnum,
         qi.tqi_readyTime = qinfo->tqi_readyTime;
 
         if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unable to update hardware queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(ah),
+                        "Unable to update hardware queue %u!\n", qnum);
                 error = -EIO;
         } else {
                 ath9k_hw_resettxqueue(ah, qnum);
@@ -244,7 +251,7 @@ void ath9k_tx_tasklet(unsigned long data)
                                 ista = (struct ath9k_htc_sta *)sta->drv_priv;
 
                                 if (ath9k_htc_check_tx_aggr(priv, ista, tid)) {
-                                        ieee80211_start_tx_ba_session(sta, tid);
+                                        ieee80211_start_tx_ba_session(sta, tid, 0);
                                         spin_lock_bh(&priv->tx_lock);
                                         ista->tid_state[tid] = AGGR_PROGRESS;
                                         spin_unlock_bh(&priv->tx_lock);
@@ -263,8 +270,8 @@ void ath9k_tx_tasklet(unsigned long data)
         if (priv->tx_queues_stop) {
                 priv->tx_queues_stop = false;
                 spin_unlock_bh(&priv->tx_lock);
-                ath_print(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
-                          "Waking up TX queues\n");
+                ath_dbg(ath9k_hw_common(priv->ah), ATH_DBG_XMIT,
+                        "Waking up TX queues\n");
                 ieee80211_wake_queues(priv->hw);
                 return;
         }
@@ -289,8 +296,7 @@ void ath9k_htc_txep(void *drv_priv, struct sk_buff *skb,
                    (ep_id == priv->data_vo_ep)) {
                 skb_pull(skb, sizeof(struct tx_frame_hdr));
         } else {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unsupported TX EPID: %d\n", ep_id);
+                ath_err(common, "Unsupported TX EPID: %d\n", ep_id);
                 dev_kfree_skb_any(skb);
                 return;
         }
@@ -330,9 +336,8 @@ bool ath9k_htc_txq_setup(struct ath9k_htc_priv *priv, int subtype)
                 return false;
 
         if (qnum >= ARRAY_SIZE(priv->hwq_map)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "qnum %u out of range, max %u!\n",
-                          qnum, (unsigned int)ARRAY_SIZE(priv->hwq_map));
+                ath_err(common, "qnum %u out of range, max %zu!\n",
+                        qnum, ARRAY_SIZE(priv->hwq_map));
                 ath9k_hw_releasetxqueue(ah, qnum);
                 return false;
         }
@@ -483,8 +488,7 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
         __le16 fc;
 
         if (skb->len <= HTC_RX_FRAME_HEADER_SIZE) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Corrupted RX frame, dropping\n");
+                ath_err(common, "Corrupted RX frame, dropping\n");
                 goto rx_next;
         }
 
@@ -492,10 +496,9 @@ static bool ath9k_rx_prepare(struct ath9k_htc_priv *priv,
 
         if (be16_to_cpu(rxstatus->rs_datalen) -
             (skb->len - HTC_RX_FRAME_HEADER_SIZE) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Corrupted RX data len, dropping "
-                          "(dlen: %d, skblen: %d)\n",
-                          rxstatus->rs_datalen, skb->len);
+                ath_err(common,
+                        "Corrupted RX data len, dropping (dlen: %d, skblen: %d)\n",
+                        rxstatus->rs_datalen, skb->len);
                 goto rx_next;
         }
 
@@ -678,8 +681,8 @@ void ath9k_htc_rxep(void *drv_priv, struct sk_buff *skb,
         spin_unlock(&priv->rx.rxbuflock);
 
         if (rxbuf == NULL) {
-                ath_print(common, ATH_DBG_ANY,
-                          "No free RX buffer\n");
+                ath_dbg(common, ATH_DBG_ANY,
+                        "No free RX buffer\n");
                 goto err;
         }
 
@@ -721,8 +724,7 @@ int ath9k_rx_init(struct ath9k_htc_priv *priv)
         for (i = 0; i < ATH9K_HTC_RXBUF; i++) {
                 rxbuf = kzalloc(sizeof(struct ath9k_htc_rxbuf), GFP_KERNEL);
                 if (rxbuf == NULL) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to allocate RX buffers\n");
+                        ath_err(common, "Unable to allocate RX buffers\n");
                         goto err;
                 }
                 list_add_tail(&rxbuf->list, &priv->rx.rxbuf);
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c
index 861ec9269309..c41ab8c30161 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.c
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.c
@@ -462,9 +462,10 @@ void ath9k_htc_hw_free(struct htc_target *htc)
 }
 
 int ath9k_htc_hw_init(struct htc_target *target,
-                      struct device *dev, u16 devid, char *product)
+                      struct device *dev, u16 devid,
+                      char *product, u32 drv_info)
 {
-        if (ath9k_htc_probe_device(target, dev, devid, product)) {
+        if (ath9k_htc_probe_device(target, dev, devid, product, drv_info)) {
                 printk(KERN_ERR "Failed to initialize the device\n");
                 return -ENODEV;
         }
diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.h b/drivers/net/wireless/ath/ath9k/htc_hst.h
index 07b6509d5896..ecd018798c47 100644
--- a/drivers/net/wireless/ath/ath9k/htc_hst.h
+++ b/drivers/net/wireless/ath/ath9k/htc_hst.h
@@ -77,20 +77,6 @@ struct htc_config_pipe_msg {
         u8 credits;
 } __packed;
 
-struct htc_packet {
-        void *pktcontext;
-        u8 *buf;
-        u8 *buf_payload;
-        u32 buflen;
-        u32 payload_len;
-
-        int endpoint;
-        int status;
-
-        void *context;
-        u32 reserved;
-};
-
 struct htc_ep_callbacks {
         void *priv;
         void (*tx) (void *, struct sk_buff *, enum htc_endpoint_id, bool txok);
@@ -123,11 +109,6 @@ struct htc_endpoint {
 #define HTC_CONTROL_BUFFER_SIZE \
         (HTC_MAX_CONTROL_MESSAGE_LENGTH + sizeof(struct htc_frame_hdr))
 
-struct htc_control_buf {
-        struct htc_packet htc_pkt;
-        u8 buf[HTC_CONTROL_BUFFER_SIZE];
-};
-
 #define HTC_OP_START_WAIT           BIT(0)
 #define HTC_OP_CONFIG_PIPE_CREDITS  BIT(1)
 
@@ -239,7 +220,8 @@ struct htc_target *ath9k_htc_hw_alloc(void *hif_handle,
                                       struct device *dev);
 void ath9k_htc_hw_free(struct htc_target *htc);
 int ath9k_htc_hw_init(struct htc_target *target,
-                      struct device *dev, u16 devid, char *product);
+                      struct device *dev, u16 devid, char *product,
+                      u32 drv_info);
 void ath9k_htc_hw_deinit(struct htc_target *target, bool hot_unplug);
 
 #endif /* HTC_HST_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index 0a4ad348b699..c8f254fe0f0b 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -223,11 +223,6 @@ static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
         return ath9k_hw_private_ops(ah)->rfbus_done(ah);
 }
 
-static inline void ath9k_enable_rfkill(struct ath_hw *ah)
-{
-        return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
-}
-
 static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
 {
         if (!ath9k_hw_private_ops(ah)->restore_chainmask)
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index c7fbe25cc128..fde978665e07 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -54,13 +54,6 @@ static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
 }
 
-static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
-{
-        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-
-        return priv_ops->macversion_supported(ah->hw_version.macVersion);
-}
-
 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
                                         struct ath9k_channel *chan)
 {
@@ -129,9 +122,9 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
                 udelay(AH_TIME_QUANTUM);
         }
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
-                  "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
-                  timeout, reg, REG_READ(ah, reg), mask, val);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
+                "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
+                timeout, reg, REG_READ(ah, reg), mask, val);
 
         return false;
 }
@@ -211,8 +204,8 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
                 }
                 break;
         default:
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Unknown phy %u (rate ix %u)\n", phy, rateix);
+                ath_err(ath9k_hw_common(ah),
+                        "Unknown phy %u (rate ix %u)\n", phy, rateix);
                 txTime = 0;
                 break;
         }
@@ -284,11 +277,9 @@ static void ath9k_hw_read_revisions(struct ath_hw *ah)
 
 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 {
-        if (AR_SREV_9100(ah))
+        if (!AR_SREV_5416(ah))
                 return;
 
-        ENABLE_REGWRITE_BUFFER(ah);
-
         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
@@ -300,8 +291,6 @@ static void ath9k_hw_disablepcie(struct ath_hw *ah)
         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 
         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
-
-        REGWRITE_BUFFER_FLUSH(ah);
 }
 
 /* This should work for all families including legacy */
@@ -310,10 +299,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
         struct ath_common *common = ath9k_hw_common(ah);
         u32 regAddr[2] = { AR_STA_ID0 };
         u32 regHold[2];
-        u32 patternData[4] = { 0x55555555,
-                               0xaaaaaaaa,
-                               0x66666666,
-                               0x99999999 };
+        static const u32 patternData[4] = {
+                0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
+        };
         int i, j, loop_max;
 
         if (!AR_SREV_9300_20_OR_LATER(ah)) {
@@ -332,11 +320,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                         REG_WRITE(ah, addr, wrData);
                         rdData = REG_READ(ah, addr);
                         if (rdData != wrData) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "address test failed "
-                                          "addr: 0x%08x - wr:0x%08x != "
-                                          "rd:0x%08x\n",
-                                          addr, wrData, rdData);
+                                ath_err(common,
+                                        "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+                                        addr, wrData, rdData);
                                 return false;
                         }
                 }
@@ -345,11 +331,9 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
                         REG_WRITE(ah, addr, wrData);
                         rdData = REG_READ(ah, addr);
                         if (wrData != rdData) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "address test failed "
-                                          "addr: 0x%08x - wr:0x%08x != "
-                                          "rd:0x%08x\n",
-                                          addr, wrData, rdData);
+                                ath_err(common,
+                                        "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
+                                        addr, wrData, rdData);
                                 return false;
                         }
                 }
@@ -419,17 +403,12 @@ static void ath9k_hw_init_defaults(struct ath_hw *ah)
         ah->hw_version.magic = AR5416_MAGIC;
         ah->hw_version.subvendorid = 0;
 
-        ah->ah_flags = 0;
-        if (!AR_SREV_9100(ah))
-                ah->ah_flags = AH_USE_EEPROM;
-
         ah->atim_window = 0;
         ah->sta_id1_defaults =
                 AR_STA_ID1_CRPT_MIC_ENABLE |
                 AR_STA_ID1_MCAST_KSRCH;
-        ah->beacon_interval = 100;
         ah->enable_32kHz_clock = DONT_USE_32KHZ;
-        ah->slottime = (u32) -1;
+        ah->slottime = 20;
         ah->globaltxtimeout = (u32) -1;
         ah->power_mode = ATH9K_PM_UNDEFINED;
 }
@@ -440,7 +419,7 @@ static int ath9k_hw_init_macaddr(struct ath_hw *ah)
         u32 sum;
         int i;
         u16 eeval;
-        u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
+        static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 
         sum = 0;
         for (i = 0; i < 3; i++) {
@@ -474,16 +453,15 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
         if (ecode != 0)
                 return ecode;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
-                  "Eeprom VER: %d, REV: %d\n",
-                  ah->eep_ops->get_eeprom_ver(ah),
-                  ah->eep_ops->get_eeprom_rev(ah));
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
+                "Eeprom VER: %d, REV: %d\n",
+                ah->eep_ops->get_eeprom_ver(ah),
+                ah->eep_ops->get_eeprom_rev(ah));
 
         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
         if (ecode) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Failed allocating banks for "
-                          "external radio\n");
+                ath_err(ath9k_hw_common(ah),
+                        "Failed allocating banks for external radio\n");
                 ath9k_hw_rf_free_ext_banks(ah);
                 return ecode;
         }
@@ -514,8 +492,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 
         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Couldn't reset chip\n");
+                ath_err(common, "Couldn't reset chip\n");
                 return -EIO;
         }
 
@@ -525,7 +502,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         ath9k_hw_attach_ops(ah);
 
         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
-                ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
+                ath_err(common, "Couldn't wakeup chip\n");
                 return -EIO;
         }
 
@@ -541,7 +518,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
                 }
         }
 
-        ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
+        ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
                 ah->config.serialize_regmode);
 
         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
@@ -549,11 +526,22 @@ static int __ath9k_hw_init(struct ath_hw *ah)
         else
                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 
-        if (!ath9k_hw_macversion_supported(ah)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Mac Chip Rev 0x%02x.%x is not supported by "
-                          "this driver\n", ah->hw_version.macVersion,
-                          ah->hw_version.macRev);
+        switch (ah->hw_version.macVersion) {
+        case AR_SREV_VERSION_5416_PCI:
+        case AR_SREV_VERSION_5416_PCIE:
+        case AR_SREV_VERSION_9160:
+        case AR_SREV_VERSION_9100:
+        case AR_SREV_VERSION_9280:
+        case AR_SREV_VERSION_9285:
+        case AR_SREV_VERSION_9287:
+        case AR_SREV_VERSION_9271:
+        case AR_SREV_VERSION_9300:
+        case AR_SREV_VERSION_9485:
+                break;
+        default:
+                ath_err(common,
+                        "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
+                        ah->hw_version.macVersion, ah->hw_version.macRev);
                 return -EOPNOTSUPP;
         }
 
@@ -599,8 +587,7 @@ static int __ath9k_hw_init(struct ath_hw *ah)
 
         r = ath9k_hw_init_macaddr(ah);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to initialize MAC address\n");
+                ath_err(common, "Failed to initialize MAC address\n");
                 return r;
         }
 
@@ -634,21 +621,21 @@ int ath9k_hw_init(struct ath_hw *ah)
         case AR9287_DEVID_PCIE:
         case AR2427_DEVID_PCIE:
         case AR9300_DEVID_PCIE:
+        case AR9300_DEVID_AR9485_PCIE:
                 break;
         default:
                 if (common->bus_ops->ath_bus_type == ATH_USB)
                         break;
-                ath_print(common, ATH_DBG_FATAL,
-                          "Hardware device ID 0x%04x not supported\n",
-                          ah->hw_version.devid);
+                ath_err(common, "Hardware device ID 0x%04x not supported\n",
+                        ah->hw_version.devid);
                 return -EOPNOTSUPP;
         }
 
         ret = __ath9k_hw_init(ah);
         if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to initialize hardware; "
-                          "initialization status: %d\n", ret);
+                ath_err(common,
+                        "Unable to initialize hardware; initialization status: %d\n",
+                        ret);
                 return ret;
         }
 
@@ -680,7 +667,12 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
 static void ath9k_hw_init_pll(struct ath_hw *ah,
                               struct ath9k_channel *chan)
 {
-        u32 pll = ath9k_hw_compute_pll_control(ah, chan);
+        u32 pll;
+
+        if (AR_SREV_9485(ah))
+                REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
+
+        pll = ath9k_hw_compute_pll_control(ah, chan);
 
         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 
@@ -772,8 +764,8 @@ static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 {
         if (tu > 0xFFFF) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
-                          "bad global tx timeout %u\n", tu);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
+                        "bad global tx timeout %u\n", tu);
                 ah->globaltxtimeout = (u32) -1;
                 return false;
         } else {
@@ -790,8 +782,8 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
         int slottime;
         int sifstime;
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
-                  ah->misc_mode);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
+                ah->misc_mode);
 
         if (ah->misc_mode != 0)
                 REG_WRITE(ah, AR_PCU_MISC,
@@ -816,7 +808,7 @@ void ath9k_hw_init_global_settings(struct ath_hw *ah)
         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
                 acktimeout += 64 - sifstime - ah->slottime;
 
-        ath9k_hw_setslottime(ah, slottime);
+        ath9k_hw_setslottime(ah, ah->slottime);
         ath9k_hw_set_ack_timeout(ah, acktimeout);
         ath9k_hw_set_cts_timeout(ah, acktimeout);
         if (ah->globaltxtimeout != (u32) -1)
@@ -1034,8 +1026,8 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 
         REG_WRITE(ah, AR_RTC_RC, 0);
         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "RTC stuck in MAC reset\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "RTC stuck in MAC reset\n");
                 return false;
         }
 
@@ -1081,8 +1073,8 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
                            AR_RTC_STATUS_M,
                            AR_RTC_STATUS_ON,
                            AH_WAIT_TIMEOUT)) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "RTC not waking up\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "RTC not waking up\n");
                 return false;
         }
 
@@ -1142,16 +1134,14 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
 
         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
                 if (ath9k_hw_numtxpending(ah, qnum)) {
-                        ath_print(common, ATH_DBG_QUEUE,
-                                  "Transmit frames pending on "
-                                  "queue %d\n", qnum);
+                        ath_dbg(common, ATH_DBG_QUEUE,
+                                "Transmit frames pending on queue %d\n", qnum);
                         return false;
                 }
         }
 
         if (!ath9k_hw_rfbus_req(ah)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Could not kill baseband RX\n");
+                ath_err(common, "Could not kill baseband RX\n");
                 return false;
         }
 
@@ -1159,8 +1149,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
 
         r = ath9k_hw_rf_set_freq(ah, chan);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to set channel\n");
+                ath_err(common, "Failed to set channel\n");
                 return false;
         }
         ath9k_hw_set_clockrate(ah);
@@ -1170,7 +1159,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
                              channel->max_antenna_gain * 2,
                              channel->max_power * 2,
                              min((u32) MAX_RATE_POWER,
-                             (u32) regulatory->power_limit));
+                             (u32) regulatory->power_limit), false);
 
         ath9k_hw_rfbus_done(ah);
 
@@ -1227,7 +1216,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         if (!ah->chip_fullsleep) {
                 ath9k_hw_abortpcurecv(ah);
                 if (!ath9k_hw_stopdmarecv(ah)) {
-                        ath_print(common, ATH_DBG_XMIT,
+                        ath_dbg(common, ATH_DBG_XMIT,
                                 "Failed to stop receive dma\n");
                         bChannelChange = false;
                 }
@@ -1283,6 +1272,8 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
 
         ath9k_hw_mark_phy_inactive(ah);
 
+        ah->paprd_table_write_done = false;
+
         /* Only required on the first reset */
         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
                 REG_WRITE(ah,
@@ -1292,7 +1283,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         }
 
         if (!ath9k_hw_chip_reset(ah, chan)) {
-                ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
+                ath_err(common, "Chip reset failed\n");
                 return -EINVAL;
         }
 
@@ -1394,7 +1385,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
         ath9k_hw_init_qos(ah);
 
         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
-                ath9k_enable_rfkill(ah);
+                ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 
         ath9k_hw_init_global_settings(ah);
 
@@ -1439,13 +1430,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
                 u32 mask;
                 mask = REG_READ(ah, AR_CFG);
                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
-                        ath_print(common, ATH_DBG_RESET,
+                        ath_dbg(common, ATH_DBG_RESET,
                                 "CFG Byte Swap Set 0x%x\n", mask);
                 } else {
                         mask =
                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
                         REG_WRITE(ah, AR_CFG, mask);
-                        ath_print(common, ATH_DBG_RESET,
+                        ath_dbg(common, ATH_DBG_RESET,
                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
                 }
         } else {
@@ -1573,9 +1564,9 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
                                     AR_RTC_FORCE_WAKE_EN);
                 }
                 if (i == 0) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "Failed to wakeup in %uus\n",
-                                  POWER_UP_TIME / 20);
+                        ath_err(ath9k_hw_common(ah),
+                                "Failed to wakeup in %uus\n",
+                                POWER_UP_TIME / 20);
                         return false;
                 }
         }
@@ -1599,8 +1590,8 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
         if (ah->power_mode == mode)
                 return status;
 
-        ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
-                  modes[ah->power_mode], modes[mode]);
+        ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
+                modes[ah->power_mode], modes[mode]);
 
         switch (mode) {
         case ATH9K_PM_AWAKE:
@@ -1614,12 +1605,20 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
                 ath9k_set_power_network_sleep(ah, setChip);
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unknown power mode %u\n", mode);
+                ath_err(common, "Unknown power mode %u\n", mode);
                 return false;
         }
         ah->power_mode = mode;
 
+        /*
+         * XXX: If this warning never comes up after a while then
+         * simply keep the ATH_DBG_WARN_ON_ONCE() but make
+         * ath9k_hw_setpower() return type void.
+         */
+
+        if (!(ah->ah_flags & AH_UNPLUGGED))
+                ATH_DBG_WARN_ON_ONCE(!status);
+
         return status;
 }
 EXPORT_SYMBOL(ath9k_hw_setpower);
@@ -1632,17 +1631,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
 {
         int flags = 0;
 
-        ah->beacon_interval = beacon_period;
-
         ENABLE_REGWRITE_BUFFER(ah);
 
         switch (ah->opmode) {
-        case NL80211_IFTYPE_STATION:
-                REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
-                REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
-                REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
-                flags |= AR_TBTT_TIMER_EN;
-                break;
         case NL80211_IFTYPE_ADHOC:
         case NL80211_IFTYPE_MESH_POINT:
                 REG_SET_BIT(ah, AR_TXCFG,
@@ -1666,17 +1657,9 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
                 break;
         default:
-                if (ah->is_monitoring) {
-                        REG_WRITE(ah, AR_NEXT_TBTT_TIMER,
-                                        TU_TO_USEC(next_beacon));
-                        REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
-                        REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
-                        flags |= AR_TBTT_TIMER_EN;
-                        break;
-                }
-                ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
-                          "%s: unsupported opmode: %d\n",
-                          __func__, ah->opmode);
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
+                        "%s: unsupported opmode: %d\n",
+                        __func__, ah->opmode);
                 return;
                 break;
         }
@@ -1732,10 +1715,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
         else
                 nextTbtt = bs->bs_nexttbtt;
 
-        ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
-        ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
-        ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
-        ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
+        ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
+        ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
+        ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
+        ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -1781,7 +1764,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
 
         u16 capField = 0, eeval;
-        u8 ant_div_ctl1;
+        u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
         regulatory->current_rd = eeval;
@@ -1800,14 +1783,14 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                         regulatory->current_rd += 5;
                 else if (regulatory->current_rd == 0x41)
                         regulatory->current_rd = 0x43;
-                ath_print(common, ATH_DBG_REGULATORY,
-                          "regdomain mapped to 0x%x\n", regulatory->current_rd);
+                ath_dbg(common, ATH_DBG_REGULATORY,
+                        "regdomain mapped to 0x%x\n", regulatory->current_rd);
         }
 
         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "no band has been marked as supported in EEPROM.\n");
+                ath_err(common,
+                        "no band has been marked as supported in EEPROM\n");
                 return -EINVAL;
         }
 
@@ -1833,6 +1816,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
 
         ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
 
+        /* enable key search for every frame in an aggregate */
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
+
         pCap->low_2ghz_chan = 2312;
         pCap->high_2ghz_chan = 2732;
 
@@ -1921,13 +1908,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
             AR_SREV_5416(ah))
                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
 
-        pCap->num_antcfg_5ghz =
-                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
-        pCap->num_antcfg_2ghz =
-                ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
-
-        if (AR_SREV_9280_20_OR_LATER(ah) &&
-            ath9k_hw_btcoex_supported(ah)) {
+        if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
 
@@ -1942,8 +1923,10 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         }
 
         if (AR_SREV_9300_20_OR_LATER(ah)) {
-                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
-                                 ATH9K_HW_CAP_FASTCLOCK;
+                pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
+                if (!AR_SREV_9485(ah))
+                        pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
+
                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
@@ -1963,6 +1946,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
         if (AR_SREV_9300_20_OR_LATER(ah))
                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
 
+        if (AR_SREV_9300_20_OR_LATER(ah))
+                ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
+
         if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
 
@@ -1973,6 +1959,29 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah)
                         if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
                                 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
                 }
+        if (AR_SREV_9300_20_OR_LATER(ah)) {
+                if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
+                        pCap->hw_caps |= ATH9K_HW_CAP_APM;
+        }
+
+
+
+        if (AR_SREV_9485_10(ah)) {
+                pCap->pcie_lcr_extsync_en = true;
+                pCap->pcie_lcr_offset = 0x80;
+        }
+
+        tx_chainmask = pCap->tx_chainmask;
+        rx_chainmask = pCap->rx_chainmask;
+        while (tx_chainmask || rx_chainmask) {
+                if (tx_chainmask & BIT(0))
+                        pCap->max_txchains++;
+                if (rx_chainmask & BIT(0))
+                        pCap->max_rxchains++;
+
+                tx_chainmask >>= 1;
+                rx_chainmask >>= 1;
+        }
 
         return 0;
 }
@@ -2177,7 +2186,7 @@ bool ath9k_hw_disable(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_disable);
 
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
 {
         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
         struct ath9k_channel *chan = ah->curchan;
@@ -2190,7 +2199,7 @@ void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
                                  channel->max_antenna_gain * 2,
                                  channel->max_power * 2,
                                  min((u32) MAX_RATE_POWER,
-                                 (u32) regulatory->power_limit));
+                                 (u32) regulatory->power_limit), test);
 }
 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
 
@@ -2250,8 +2259,8 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
 {
         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
                            AH_TSF_WRITE_TIMEOUT))
-                ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
-                          "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
+                ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
+                        "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
 
         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
 }
@@ -2324,11 +2333,10 @@ static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
         return timer_table->gen_timer_index[b];
 }
 
-u32 ath9k_hw_gettsf32(struct ath_hw *ah)
+static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
 {
         return REG_READ(ah, AR_TSF_L32);
 }
-EXPORT_SYMBOL(ath9k_hw_gettsf32);
 
 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
                                           void (*trigger)(void *),
@@ -2342,9 +2350,9 @@ struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
 
         if (timer == NULL) {
-                ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                          "Failed to allocate memory"
-                          "for hw timer[%d]\n", timer_index);
+                ath_err(ath9k_hw_common(ah),
+                        "Failed to allocate memory for hw timer[%d]\n",
+                        timer_index);
                 return NULL;
         }
 
@@ -2373,9 +2381,9 @@ void ath9k_hw_gen_timer_start(struct ath_hw *ah,
 
         tsf = ath9k_hw_gettsf32(ah);
 
-        ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
-                  "curent tsf %x period %x"
-                  "timer_next %x\n", tsf, timer_period, timer_next);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
+                "current tsf %x period %x timer_next %x\n",
+                tsf, timer_period, timer_next);
 
         /*
          * Pull timer_next forward if the current TSF already passed it
@@ -2455,8 +2463,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
                 index = rightmost_index(timer_table, &thresh_mask);
                 timer = timer_table->timers[index];
                 BUG_ON(!timer);
-                ath_print(common, ATH_DBG_HWTIMER,
-                          "TSF overflow for Gen timer %d\n", index);
+                ath_dbg(common, ATH_DBG_HWTIMER,
+                        "TSF overflow for Gen timer %d\n", index);
                 timer->overflow(timer->arg);
         }
 
@@ -2464,8 +2472,8 @@ void ath_gen_timer_isr(struct ath_hw *ah)
                 index = rightmost_index(timer_table, &trigger_mask);
                 timer = timer_table->timers[index];
                 BUG_ON(!timer);
-                ath_print(common, ATH_DBG_HWTIMER,
-                          "Gen timer[%d] trigger\n", index);
+                ath_dbg(common, ATH_DBG_HWTIMER,
+                        "Gen timer[%d] trigger\n", index);
                 timer->trigger(timer->arg);
         }
 }
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index d47d1b4b6002..5a3dfec45e96 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -30,7 +30,6 @@
 #include "btcoex.h"
 
 #include "../regd.h"
-#include "../debug.h"
 
 #define ATHEROS_VENDOR_ID       0x168c
 
@@ -44,6 +43,7 @@
 #define AR9287_DEVID_PCI        0x002d
 #define AR9287_DEVID_PCIE       0x002e
 #define AR9300_DEVID_PCIE       0x0030
+#define AR9300_DEVID_AR9485_PCIE 0x0032
 
 #define AR5416_AR9100_DEVID     0x000b
 
@@ -157,6 +157,13 @@
 #define PAPRD_GAIN_TABLE_ENTRIES    32
 #define PAPRD_TABLE_SZ              24
 
+enum ath_hw_txq_subtype {
+        ATH_TXQ_AC_BE = 0,
+        ATH_TXQ_AC_BK = 1,
+        ATH_TXQ_AC_VI = 2,
+        ATH_TXQ_AC_VO = 3,
+};
+
 enum ath_ini_subsys {
         ATH_INI_PRE = 0,
         ATH_INI_CORE,
@@ -180,6 +187,7 @@ enum ath9k_hw_caps {
         ATH9K_HW_CAP_ANT_DIV_COMB               = BIT(12),
         ATH9K_HW_CAP_2GHZ                       = BIT(13),
         ATH9K_HW_CAP_5GHZ                       = BIT(14),
+        ATH9K_HW_CAP_APM                        = BIT(15),
 };
 
 struct ath9k_hw_capabilities {
@@ -191,16 +199,18 @@ struct ath9k_hw_capabilities {
         u16 rts_aggr_limit;
         u8 tx_chainmask;
         u8 rx_chainmask;
+        u8 max_txchains;
+        u8 max_rxchains;
         u16 tx_triglevel_max;
         u16 reg_cap;
         u8 num_gpio_pins;
-        u8 num_antcfg_2ghz;
-        u8 num_antcfg_5ghz;
         u8 rx_hp_qdepth;
         u8 rx_lp_qdepth;
         u8 rx_status_len;
         u8 tx_desc_len;
         u8 txs_len;
+        u16 pcie_lcr_offset;
+        bool pcie_lcr_extsync_en;
 };
 
 struct ath9k_ops_config {
@@ -226,7 +236,6 @@ struct ath9k_ops_config {
 #define SPUR_DISABLE            0
 #define SPUR_ENABLE_IOCTL       1
 #define SPUR_ENABLE_EEPROM      2
-#define AR_EEPROM_MODAL_SPURS   5
 #define AR_SPUR_5413_1          1640
 #define AR_SPUR_5413_2          1200
 #define AR_NO_SPUR              0x8000
@@ -434,6 +443,7 @@ struct ath9k_hw_version {
         u16 analog5GhzRev;
         u16 analog2GhzRev;
         u16 subsysid;
+        enum ath_usb_dev usbdev;
 };
 
 /* Generic TSF timer definitions */
@@ -478,6 +488,40 @@ struct ath_hw_antcomb_conf {
 };
 
 /**
+ * struct ath_hw_radar_conf - radar detection initialization parameters
+ *
+ * @pulse_inband: threshold for checking the ratio of in-band power
+ *      to total power for short radar pulses (half dB steps)
+ * @pulse_inband_step: threshold for checking an in-band power to total
+ *      power ratio increase for short radar pulses (half dB steps)
+ * @pulse_height: threshold for detecting the beginning of a short
+ *      radar pulse (dB step)
+ * @pulse_rssi: threshold for detecting if a short radar pulse is
+ *      gone (dB step)
+ * @pulse_maxlen: maximum pulse length (0.8 us steps)
+ *
+ * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
+ * @radar_inband: threshold for checking the ratio of in-band power
+ *      to total power for long radar pulses (half dB steps)
+ * @fir_power: threshold for detecting the end of a long radar pulse (dB)
+ *
+ * @ext_channel: enable extension channel radar detection
+ */
+struct ath_hw_radar_conf {
+        unsigned int pulse_inband;
+        unsigned int pulse_inband_step;
+        unsigned int pulse_height;
+        unsigned int pulse_rssi;
+        unsigned int pulse_maxlen;
+
+        unsigned int radar_rssi;
+        unsigned int radar_inband;
+        int fir_power;
+
+        bool ext_channel;
+};
+
+/**
  * struct ath_hw_private_ops - callbacks used internally by hardware code
  *
  * This structure contains private callbacks designed to only be used internally
@@ -488,7 +532,6 @@ struct ath_hw_antcomb_conf {
  *
  * @init_mode_regs: Initializes mode registers
  * @init_mode_gain_regs: Initialize TX/RX gain registers
- * @macversion_supported: If this specific mac revision is supported
  *
  * @rf_set_freq: change frequency
  * @spur_mitigate_freq: spur mitigation
@@ -510,7 +553,6 @@ struct ath_hw_private_ops {
 
         void (*init_mode_regs)(struct ath_hw *ah);
         void (*init_mode_gain_regs)(struct ath_hw *ah);
-        bool (*macversion_supported)(u32 macversion);
         void (*setup_calibration)(struct ath_hw *ah,
                                   struct ath9k_cal_list *currCal);
 
@@ -534,7 +576,6 @@ struct ath_hw_private_ops {
         void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
         bool (*rfbus_req)(struct ath_hw *ah);
         void (*rfbus_done)(struct ath_hw *ah);
-        void (*enable_rfkill)(struct ath_hw *ah);
         void (*restore_chainmask)(struct ath_hw *ah);
         void (*set_diversity)(struct ath_hw *ah, bool value);
         u32 (*compute_pll_control)(struct ath_hw *ah,
@@ -542,6 +583,8 @@ struct ath_hw_private_ops {
         bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
                             int param);
         void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
+        void (*set_radar_params)(struct ath_hw *ah,
+                                 struct ath_hw_radar_conf *conf);
 
         /* ANI */
         void (*ani_cache_ini_regs)(struct ath_hw *ah);
@@ -603,6 +646,10 @@ struct ath_nf_limits {
         s16 nominal;
 };
 
+/* ah_flags */
+#define AH_USE_EEPROM   0x1
+#define AH_UNPLUGGED    0x2 /* The card has been physically removed. */
+
 struct ath_hw {
         struct ieee80211_hw *hw;
         struct ath_common common;
@@ -718,9 +765,7 @@ struct ath_hw {
         u32 *bank6Temp;
 
         u8 txpower_limit;
-        int16_t txpower_indexoffset;
         int coverage_class;
-        u32 beacon_interval;
         u32 slottime;
         u32 globaltxtimeout;
 
@@ -740,6 +785,8 @@ struct ath_hw {
         u8 txchainmask;
         u8 rxchainmask;
 
+        struct ath_hw_radar_conf radar_conf;
+
         u32 originalGain[22];
         int initPDADC;
         int PDADCdelta;
@@ -789,6 +836,11 @@ struct ath_hw {
         u32 bb_watchdog_last_status;
         u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
 
+        unsigned int paprd_target_power;
+        unsigned int paprd_training_power;
+        unsigned int paprd_ratemask;
+        unsigned int paprd_ratemask_ht40;
+        bool paprd_table_write_done;
         u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
         u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
         /*
@@ -797,6 +849,9 @@ struct ath_hw {
          * this register when in sleep states.
          */
         u32 WARegVal;
+
+        /* Enterprise mode cap */
+        u32 ent_mode;
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -819,10 +874,9 @@ static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
         return &ah->ops;
 }
 
-static inline int sign_extend(int val, const int nbits)
+static inline u8 get_streams(int mask)
 {
-        int order = BIT(nbits-1);
-        return (val ^ order) - order;
+        return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
 }
 
 /* Initialization, Detach, Reset */
@@ -861,7 +915,7 @@ u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
 bool ath9k_hw_phy_disable(struct ath_hw *ah);
 bool ath9k_hw_disable(struct ath_hw *ah);
-void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
+void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
 void ath9k_hw_setopmode(struct ath_hw *ah);
 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
 void ath9k_hw_setbssidmask(struct ath_hw *ah);
@@ -893,7 +947,6 @@ void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
 
 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
 void ath_gen_timer_isr(struct ath_hw *hw);
-u32 ath9k_hw_gettsf32(struct ath_hw *ah);
 
 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
 
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 14b8ab386daf..767d8b86f1e1 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -29,17 +29,27 @@ static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
 module_param_named(debug, ath9k_debug, uint, 0);
 MODULE_PARM_DESC(debug, "Debugging mask");
 
-int modparam_nohwcrypt;
-module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
+int ath9k_modparam_nohwcrypt;
+module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
 
 int led_blink;
 module_param_named(blink, led_blink, int, 0444);
 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
 
+static int ath9k_btcoex_enable;
+module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
+MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
+
+int ath9k_pm_qos_value = ATH9K_PM_QOS_DEFAULT_VALUE;
+module_param_named(pmqos, ath9k_pm_qos_value, int, S_IRUSR | S_IRGRP | S_IROTH);
+MODULE_PARM_DESC(pmqos, "User specified PM-QOS value");
+
+bool is_ath9k_unloaded;
 /* We use the hw_value as an index into our private channel structure */
 
 #define CHAN2G(_freq, _idx)  { \
+        .band = IEEE80211_BAND_2GHZ, \
         .center_freq = (_freq), \
         .hw_value = (_idx), \
         .max_power = 20, \
@@ -206,7 +216,9 @@ static void setup_ht_cap(struct ath_softc *sc,
         ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
         ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
 
-        if (AR_SREV_9300_20_OR_LATER(ah))
+        if (AR_SREV_9485(ah))
+                max_streams = 1;
+        else if (AR_SREV_9300_20_OR_LATER(ah))
                 max_streams = 3;
         else
                 max_streams = 2;
@@ -222,9 +234,9 @@ static void setup_ht_cap(struct ath_softc *sc,
         tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
         rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "TX streams %d, RX streams: %d\n",
-                  tx_streams, rx_streams);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "TX streams %d, RX streams: %d\n",
+                tx_streams, rx_streams);
 
         if (tx_streams != rx_streams) {
                 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
@@ -267,8 +279,8 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
         struct ath_buf *bf;
         int i, bsize, error, desc_len;
 
-        ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
-                  name, nbuf, ndesc);
+        ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
+                name, nbuf, ndesc);
 
         INIT_LIST_HEAD(head);
 
@@ -279,8 +291,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 
         /* ath_desc must be a multiple of DWORDs */
         if ((desc_len % 4) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "ath_desc not DWORD aligned\n");
+                ath_err(common, "ath_desc not DWORD aligned\n");
                 BUG_ON((desc_len % 4) != 0);
                 error = -ENOMEM;
                 goto fail;
@@ -314,9 +325,9 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
                 goto fail;
         }
         ds = (u8 *) dd->dd_desc;
-        ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
-                  name, ds, (u32) dd->dd_desc_len,
-                  ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
+        ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
+                name, ds, (u32) dd->dd_desc_len,
+                ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 
         /* allocate buffers */
         bsize = sizeof(struct ath_buf) * nbuf;
@@ -362,7 +373,7 @@ fail:
 #undef DS2PHYS
 }
 
-static void ath9k_init_crypto(struct ath_softc *sc)
+void ath9k_init_crypto(struct ath_softc *sc)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
@@ -370,9 +381,9 @@ static void ath9k_init_crypto(struct ath_softc *sc)
         /* Get the hardware key cache size. */
         common->keymax = sc->sc_ah->caps.keycache_size;
         if (common->keymax > ATH_KEYMAX) {
-                ath_print(common, ATH_DBG_ANY,
-                          "Warning, using only %u entries in %u key cache\n",
-                          ATH_KEYMAX, common->keymax);
+                ath_dbg(common, ATH_DBG_ANY,
+                        "Warning, using only %u entries in %u key cache\n",
+                        ATH_KEYMAX, common->keymax);
                 common->keymax = ATH_KEYMAX;
         }
 
@@ -395,7 +406,8 @@ static void ath9k_init_crypto(struct ath_softc *sc)
 
 static int ath9k_init_btcoex(struct ath_softc *sc)
 {
-        int r, qnum;
+        struct ath_txq *txq;
+        int r;
 
         switch (sc->sc_ah->btcoex_hw.scheme) {
         case ATH_BTCOEX_CFG_NONE:
@@ -408,8 +420,8 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
                 r = ath_init_btcoex_timer(sc);
                 if (r)
                         return -1;
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
+                txq = sc->tx.txq_map[WME_AC_BE];
+                ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
                 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
                 break;
         default:
@@ -422,59 +434,18 @@ static int ath9k_init_btcoex(struct ath_softc *sc)
 
 static int ath9k_init_queues(struct ath_softc *sc)
 {
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int i = 0;
 
-        for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
-                sc->tx.hwq_map[i] = -1;
-
         sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
-        if (sc->beacon.beaconq == -1) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup a beacon xmit queue\n");
-                goto err;
-        }
-
         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
-        if (sc->beacon.cabq == NULL) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup CAB xmit queue\n");
-                goto err;
-        }
 
         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
         ath_cabq_update(sc);
 
-        if (!ath_tx_setup(sc, WME_AC_BK)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BK traffic\n");
-                goto err;
-        }
-
-        if (!ath_tx_setup(sc, WME_AC_BE)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for BE traffic\n");
-                goto err;
-        }
-        if (!ath_tx_setup(sc, WME_AC_VI)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VI traffic\n");
-                goto err;
-        }
-        if (!ath_tx_setup(sc, WME_AC_VO)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to setup xmit queue for VO traffic\n");
-                goto err;
-        }
+        for (i = 0; i < WME_NUM_AC; i++)
+                sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
 
         return 0;
-
-err:
-        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
-                if (ATH_TXQ_SETUP(sc, i))
-                        ath_tx_cleanupq(sc, &sc->tx.txq[i]);
-
-        return -EIO;
 }
 
 static int ath9k_init_channels_rates(struct ath_softc *sc)
@@ -570,6 +541,9 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         ah->hw_version.subsysid = subsysid;
         sc->sc_ah = ah;
 
+        if (!sc->dev->platform_data)
+                ah->ah_flags |= AH_USE_EEPROM;
+
         common = ath9k_hw_common(ah);
         common->ops = &ath9k_common_ops;
         common->bus_ops = bus_ops;
@@ -577,10 +551,10 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         common->hw = sc->hw;
         common->priv = sc;
         common->debug_mask = ath9k_debug;
+        common->btcoex_enabled = ath9k_btcoex_enable == 1;
         spin_lock_init(&common->cc_lock);
 
         spin_lock_init(&sc->wiphy_lock);
-        spin_lock_init(&sc->sc_resetlock);
         spin_lock_init(&sc->sc_serial_rw);
         spin_lock_init(&sc->sc_pm_lock);
         mutex_init(&sc->mutex);
@@ -600,13 +574,6 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (ret)
                 goto err_hw;
 
-        ret = ath9k_init_debug(ah);
-        if (ret) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to create debugfs files\n");
-                goto err_debug;
-        }
-
         ret = ath9k_init_queues(sc);
         if (ret)
                 goto err_queues;
@@ -629,8 +596,6 @@ err_btcoex:
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 err_queues:
-        ath9k_exit_debug(ah);
-err_debug:
         ath9k_hw_deinit(ah);
 err_hw:
         tasklet_kill(&sc->intr_tq);
@@ -642,6 +607,37 @@ err_hw:
         return ret;
 }
 
+static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
+{
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *chan;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
+        int i;
+
+        sband = &sc->sbands[band];
+        for (i = 0; i < sband->n_channels; i++) {
+                chan = &sband->channels[i];
+                ah->curchan = &ah->channels[chan->hw_value];
+                ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
+                ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
+                chan->max_power = reg->max_power_level / 2;
+        }
+}
+
+static void ath9k_init_txpower_limits(struct ath_softc *sc)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *curchan = ah->curchan;
+
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
+                ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
+        if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
+                ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
+
+        ah->curchan = curchan;
+}
+
 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
@@ -657,7 +653,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
                  hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
 
-        if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
+        if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
 
         hw->wiphy->interface_modes =
@@ -705,6 +701,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
                     const struct ath_bus_ops *bus_ops)
 {
         struct ieee80211_hw *hw = sc->hw;
+        struct ath_wiphy *aphy = hw->priv;
         struct ath_common *common;
         struct ath_hw *ah;
         int error = 0;
@@ -737,11 +734,19 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
         if (error != 0)
                 goto error_rx;
 
+        ath9k_init_txpower_limits(sc);
+
         /* Register with mac80211 */
         error = ieee80211_register_hw(hw);
         if (error)
                 goto error_register;
 
+        error = ath9k_init_debug(ah);
+        if (error) {
+                ath_err(common, "Unable to create debugfs files\n");
+                goto error_world;
+        }
+
         /* Handle world regulatory */
         if (!ath_is_world_regd(reg)) {
                 error = regulatory_hint(hw->wiphy, reg->alpha2);
@@ -754,6 +759,7 @@ int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
+        aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
 
         ath_init_leds(sc);
         ath_start_rfkill_poll(sc);
@@ -799,7 +805,6 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
                 if (ATH_TXQ_SETUP(sc, i))
                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 
-        ath9k_exit_debug(sc->sc_ah);
         ath9k_hw_deinit(sc->sc_ah);
 
         tasklet_kill(&sc->intr_tq);
@@ -866,20 +871,12 @@ static int __init ath9k_init(void)
                 goto err_out;
         }
 
-        error = ath9k_debug_create_root();
-        if (error) {
-                printk(KERN_ERR
-                        "ath9k: Unable to create debugfs root: %d\n",
-                        error);
-                goto err_rate_unregister;
-        }
-
         error = ath_pci_init();
         if (error < 0) {
                 printk(KERN_ERR
                         "ath9k: No PCI devices found, driver not installed.\n");
                 error = -ENODEV;
-                goto err_remove_root;
+                goto err_rate_unregister;
         }
 
         error = ath_ahb_init();
@@ -893,8 +890,6 @@ static int __init ath9k_init(void)
  err_pci_exit:
         ath_pci_exit();
 
- err_remove_root:
-        ath9k_debug_remove_root();
  err_rate_unregister:
         ath_rate_control_unregister();
  err_out:
@@ -904,9 +899,9 @@ module_init(ath9k_init);
 
 static void __exit ath9k_exit(void)
 {
+        is_ath9k_unloaded = true;
         ath_ahb_exit();
         ath_pci_exit();
-        ath9k_debug_remove_root();
         ath_rate_control_unregister();
         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
 }
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index c996963ab339..180170d3ce25 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -20,11 +20,11 @@
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
                                         struct ath9k_tx_queue_info *qi)
 {
-        ath_print(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
-                  "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
-                  ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
-                  ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
-                  ah->txurn_interrupt_mask);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_INTERRUPT,
+                "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
+                ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
+                ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
+                ah->txurn_interrupt_mask);
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -56,8 +56,8 @@ EXPORT_SYMBOL(ath9k_hw_puttxbuf);
 
 void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
 {
-        ath_print(ath9k_hw_common(ah), ATH_DBG_QUEUE,
-                  "Enable TXE on queue: %u\n", q);
+        ath_dbg(ath9k_hw_common(ah), ATH_DBG_QUEUE,
+                "Enable TXE on queue: %u\n", q);
         REG_WRITE(ah, AR_Q_TXE, 1 << q);
 }
 EXPORT_SYMBOL(ath9k_hw_txstart);
@@ -117,12 +117,11 @@ EXPORT_SYMBOL(ath9k_hw_numtxpending);
 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
 {
         u32 txcfg, curLevel, newLevel;
-        enum ath9k_int omask;
 
         if (ah->tx_trig_level >= ah->config.max_txtrig_level)
                 return false;
 
-        omask = ath9k_hw_set_interrupts(ah, ah->imask & ~ATH9K_INT_GLOBAL);
+        ath9k_hw_disable_interrupts(ah);
 
         txcfg = REG_READ(ah, AR_TXCFG);
         curLevel = MS(txcfg, AR_FTRIG);
@@ -136,7 +135,7 @@ bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
                 REG_WRITE(ah, AR_TXCFG,
                           (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
 
-        ath9k_hw_set_interrupts(ah, omask);
+        ath9k_hw_enable_interrupts(ah);
 
         ah->tx_trig_level = newLevel;
 
@@ -155,15 +154,15 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
         u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
 
         if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                          "invalid queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Stopping TX DMA, invalid queue: %u\n", q);
                 return false;
         }
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Stopping TX DMA, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Stopping TX DMA, inactive queue: %u\n", q);
                 return false;
         }
 
@@ -176,9 +175,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
         }
 
         if (ath9k_hw_numtxpending(ah, q)) {
-                ath_print(common, ATH_DBG_QUEUE,
-                          "%s: Num of pending TX Frames %d on Q %d\n",
-                          __func__, ath9k_hw_numtxpending(ah, q), q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "%s: Num of pending TX Frames %d on Q %d\n",
+                        __func__, ath9k_hw_numtxpending(ah, q), q);
 
                 for (j = 0; j < 2; j++) {
                         tsfLow = REG_READ(ah, AR_TSF_L32);
@@ -192,9 +191,9 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
                         if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
                                 break;
 
-                        ath_print(common, ATH_DBG_QUEUE,
-                                  "TSF has moved while trying to set "
-                                  "quiet time TSF: 0x%08x\n", tsfLow);
+                        ath_dbg(common, ATH_DBG_QUEUE,
+                                "TSF has moved while trying to set quiet time TSF: 0x%08x\n",
+                                tsfLow);
                 }
 
                 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
@@ -205,9 +204,8 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
                 wait = wait_time;
                 while (ath9k_hw_numtxpending(ah, q)) {
                         if ((--wait) == 0) {
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "Failed to stop TX DMA in 100 "
-                                          "msec after killing last frame\n");
+                                ath_err(common,
+                                        "Failed to stop TX DMA in 100 msec after killing last frame\n");
                                 break;
                         }
                         udelay(ATH9K_TIME_QUANTUM);
@@ -240,19 +238,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
         struct ath9k_tx_queue_info *qi;
 
         if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                          "invalid queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Set TXQ properties, invalid queue: %u\n", q);
                 return false;
         }
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Set TXQ properties, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Set TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
 
         qi->tqi_ver = qinfo->tqi_ver;
         qi->tqi_subtype = qinfo->tqi_subtype;
@@ -311,15 +309,15 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
         struct ath9k_tx_queue_info *qi;
 
         if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                          "invalid queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Get TXQ properties, invalid queue: %u\n", q);
                 return false;
         }
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Get TXQ properties, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Get TXQ properties, inactive queue: %u\n", q);
                 return false;
         }
 
@@ -369,23 +367,20 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
                             ATH9K_TX_QUEUE_INACTIVE)
                                 break;
                 if (q == pCap->total_queues) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "No available TX queue\n");
+                        ath_err(common, "No available TX queue\n");
                         return -1;
                 }
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "Invalid TX queue type: %u\n", type);
+                ath_err(common, "Invalid TX queue type: %u\n", type);
                 return -1;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
 
         qi = &ah->txq[q];
         if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "TX queue: %u already active\n", q);
+                ath_err(common, "TX queue: %u already active\n", q);
                 return -1;
         }
         memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -417,18 +412,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
         struct ath9k_tx_queue_info *qi;
 
         if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                          "invalid queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Release TXQ, invalid queue: %u\n", q);
                 return false;
         }
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Release TXQ, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Release TXQ, inactive queue: %u\n", q);
                 return false;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
 
         qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
         ah->txok_interrupt_mask &= ~(1 << q);
@@ -451,19 +446,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
         u32 cwMin, chanCwMin, value;
 
         if (q >= pCap->total_queues) {
-                ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                          "invalid queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Reset TXQ, invalid queue: %u\n", q);
                 return false;
         }
 
         qi = &ah->txq[q];
         if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
-                ath_print(common, ATH_DBG_QUEUE, "Reset TXQ, "
-                          "inactive queue: %u\n", q);
+                ath_dbg(common, ATH_DBG_QUEUE,
+                        "Reset TXQ, inactive queue: %u\n", q);
                 return true;
         }
 
-        ath_print(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
+        ath_dbg(common, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
 
         if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
                 if (chan && IS_CHAN_B(chan))
@@ -697,15 +692,16 @@ int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
         if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
                 if (ads.ds_rxstatus8 & AR_CRCErr)
                         rs->rs_status |= ATH9K_RXERR_CRC;
-                else if (ads.ds_rxstatus8 & AR_PHYErr) {
+                if (ads.ds_rxstatus8 & AR_PHYErr) {
                         rs->rs_status |= ATH9K_RXERR_PHY;
                         phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
                         rs->rs_phyerr = phyerr;
-                } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
+                }
+                if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
                         rs->rs_status |= ATH9K_RXERR_DECRYPT;
-                else if (ads.ds_rxstatus8 & AR_MichaelErr)
+                if (ads.ds_rxstatus8 & AR_MichaelErr)
                         rs->rs_status |= ATH9K_RXERR_MIC;
-                else if (ads.ds_rxstatus8 & AR_KeyMiss)
+                if (ads.ds_rxstatus8 & AR_KeyMiss)
                         rs->rs_status |= ATH9K_RXERR_DECRYPT;
         }
 
@@ -735,9 +731,9 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
                                      AR_DIAG_RX_ABORT));
 
                         reg = REG_READ(ah, AR_OBS_BUS_1);
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
-                                  "RX failed to go idle in 10 ms RXSM=0x%x\n",
-                                  reg);
+                        ath_err(ath9k_hw_common(ah),
+                                "RX failed to go idle in 10 ms RXSM=0x%x\n",
+                                reg);
 
                         return false;
                 }
@@ -766,14 +762,6 @@ void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
 }
 EXPORT_SYMBOL(ath9k_hw_startpcureceive);
 
-void ath9k_hw_stoppcurecv(struct ath_hw *ah)
-{
-        REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
-
-        ath9k_hw_disable_mib_counters(ah);
-}
-EXPORT_SYMBOL(ath9k_hw_stoppcurecv);
-
 void ath9k_hw_abortpcurecv(struct ath_hw *ah)
 {
         REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
@@ -799,12 +787,11 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
         }
 
         if (i == 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "DMA failed to stop in %d ms "
-                          "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
-                          AH_RX_STOP_DMA_TIMEOUT / 1000,
-                          REG_READ(ah, AR_CR),
-                          REG_READ(ah, AR_DIAG_SW));
+                ath_err(common,
+                        "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
+                        AH_RX_STOP_DMA_TIMEOUT / 1000,
+                        REG_READ(ah, AR_CR),
+                        REG_READ(ah, AR_DIAG_SW));
                 return false;
         } else {
                 return true;
@@ -848,28 +835,59 @@ bool ath9k_hw_intrpend(struct ath_hw *ah)
 }
 EXPORT_SYMBOL(ath9k_hw_intrpend);
 
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                              enum ath9k_int ints)
+void ath9k_hw_disable_interrupts(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        ath_dbg(common, ATH_DBG_INTERRUPT, "disable IER\n");
+        REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+        (void) REG_READ(ah, AR_IER);
+        if (!AR_SREV_9100(ah)) {
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+                (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+                (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
+        }
+}
+EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
+
+void ath9k_hw_enable_interrupts(struct ath_hw *ah)
+{
+        struct ath_common *common = ath9k_hw_common(ah);
+
+        if (!(ah->imask & ATH9K_INT_GLOBAL))
+                return;
+
+        ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n");
+        REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+        if (!AR_SREV_9100(ah)) {
+                REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
+                          AR_INTR_MAC_IRQ);
+                REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+
+                REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
+                          AR_INTR_SYNC_DEFAULT);
+                REG_WRITE(ah, AR_INTR_SYNC_MASK,
+                          AR_INTR_SYNC_DEFAULT);
+        }
+        ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+                REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+}
+EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
+
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
 {
         enum ath9k_int omask = ah->imask;
         u32 mask, mask2;
         struct ath9k_hw_capabilities *pCap = &ah->caps;
         struct ath_common *common = ath9k_hw_common(ah);
 
-        ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
+        if (!(ints & ATH9K_INT_GLOBAL))
+                ath9k_hw_enable_interrupts(ah);
 
-        if (omask & ATH9K_INT_GLOBAL) {
-                ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
-                REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
-                (void) REG_READ(ah, AR_IER);
-                if (!AR_SREV_9100(ah)) {
-                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
-                        (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
-
-                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-                        (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
-                }
-        }
+        ath_dbg(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
 
         /* TODO: global int Ref count */
         mask = ints & ATH9K_INT_COMMON;
@@ -930,7 +948,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         mask2 |= AR_IMR_S2_CST;
         }
 
-        ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+        ath_dbg(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
         REG_WRITE(ah, AR_IMR, mask);
         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
@@ -945,24 +963,8 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
         }
 
-        if (ints & ATH9K_INT_GLOBAL) {
-                ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
-                REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
-                if (!AR_SREV_9100(ah)) {
-                        REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
-                                  AR_INTR_MAC_IRQ);
-                        REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
-
-
-                        REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
-                                  AR_INTR_SYNC_DEFAULT);
-                        REG_WRITE(ah, AR_INTR_SYNC_MASK,
-                                  AR_INTR_SYNC_DEFAULT);
-                }
-                ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
-                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
-        }
+        ath9k_hw_enable_interrupts(ah);
 
-        return omask;
+        return;
 }
 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 7c1a34d64f6d..7512f97e8f49 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -104,13 +104,11 @@ struct ath_tx_status {
         u32 ts_tstamp;
         u16 ts_seqnum;
         u8 ts_status;
-        u8 ts_ratecode;
         u8 ts_rateindex;
         int8_t ts_rssi;
         u8 ts_shortretry;
         u8 ts_longretry;
         u8 ts_virtcol;
-        u8 ts_antenna;
         u8 ts_flags;
         int8_t ts_rssi_ctl0;
         int8_t ts_rssi_ctl1;
@@ -121,7 +119,6 @@ struct ath_tx_status {
         u8 qid;
         u16 desc_id;
         u8 tid;
-        u8 pad[2];
         u32 ba_low;
         u32 ba_high;
         u32 evm0;
@@ -240,7 +237,7 @@ struct ath_desc {
         u32 ds_ctl1;
         u32 ds_hw[20];
         void *ds_vdata;
-} __packed;
+} __packed __aligned(4);
 
 #define ATH9K_TXDESC_CLRDMASK           0x0001
 #define ATH9K_TXDESC_NOACK              0x0002
@@ -310,7 +307,7 @@ struct ar5416_desc {
                         u32 status8;
                 } rx;
         } u;
-} __packed;
+} __packed __aligned(4);
 
 #define AR5416DESC(_ds)         ((struct ar5416_desc *)(_ds))
 #define AR5416DESC_CONST(_ds)   ((const struct ar5416_desc *)(_ds))
@@ -669,6 +666,7 @@ enum ath9k_key_type {
 
 struct ath_hw;
 struct ath9k_channel;
+enum ath9k_int;
 
 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
@@ -693,15 +691,15 @@ void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning);
-void ath9k_hw_stoppcurecv(struct ath_hw *ah);
 void ath9k_hw_abortpcurecv(struct ath_hw *ah);
 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
 
 /* Interrupt Handling */
 bool ath9k_hw_intrpend(struct ath_hw *ah);
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
-                                       enum ath9k_int ints);
+void ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
+void ath9k_hw_enable_interrupts(struct ath_hw *ah);
+void ath9k_hw_disable_interrupts(struct ath_hw *ah);
 
 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
 
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index c0c3464d3a86..f90a6ca94a76 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -23,7 +23,7 @@ static void ath_update_txpow(struct ath_softc *sc)
         struct ath_hw *ah = sc->sc_ah;
 
         if (sc->curtxpow != sc->config.txpowlimit) {
-                ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
+                ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit, false);
                 /* read back in case value is clamped */
                 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
         }
@@ -234,6 +234,8 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 
         ath9k_ps_wakeup(sc);
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         /*
          * This is only performed if the channel settings have
          * actually changed.
@@ -243,11 +245,9 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
          * hardware at the new frequency, and then re-enable
          * the relevant bits of the h/w.
          */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         stopped = ath_drain_all_txq(sc, false);
 
-        spin_lock_bh(&sc->rx.pcu_lock);
-
         if (!ath_stoprecv(sc))
                 stopped = false;
 
@@ -261,46 +261,39 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
         if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
                 caldata = &aphy->caldata;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
-                  sc->sc_ah->curchan->channel,
-                  channel->center_freq, conf_is_ht40(conf),
-                  fastcc);
-
-        spin_lock_bh(&sc->sc_resetlock);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
+                sc->sc_ah->curchan->channel,
+                channel->center_freq, conf_is_ht40(conf),
+                fastcc);
 
         r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
-                spin_unlock_bh(&sc->sc_resetlock);
-                spin_unlock_bh(&sc->rx.pcu_lock);
+                ath_err(common,
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
                 goto ps_restore;
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to restart recv logic\n");
+                ath_err(common, "Unable to restart recv logic\n");
                 r = -EIO;
-                spin_unlock_bh(&sc->rx.pcu_lock);
                 goto ps_restore;
         }
 
-        spin_unlock_bh(&sc->rx.pcu_lock);
-
         ath_update_txpow(sc);
         ath9k_hw_set_interrupts(ah, ah->imask);
 
         if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
-                ath_beacon_config(sc, NULL);
+                if (sc->sc_flags & SC_OP_BEACONS)
+                        ath_beacon_config(sc, NULL);
                 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
                 ath_start_ani(common);
         }
 
  ps_restore:
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
         return r;
 }
@@ -328,6 +321,42 @@ static void ath_paprd_activate(struct ath_softc *sc)
         ath9k_ps_restore(sc);
 }
 
+static bool ath_paprd_send_frame(struct ath_softc *sc, struct sk_buff *skb, int chain)
+{
+        struct ieee80211_hw *hw = sc->hw;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ath_tx_control txctl;
+        int time_left;
+
+        memset(&txctl, 0, sizeof(txctl));
+        txctl.txq = sc->tx.txq_map[WME_AC_BE];
+
+        memset(tx_info, 0, sizeof(*tx_info));
+        tx_info->band = hw->conf.channel->band;
+        tx_info->flags |= IEEE80211_TX_CTL_NO_ACK;
+        tx_info->control.rates[0].idx = 0;
+        tx_info->control.rates[0].count = 1;
+        tx_info->control.rates[0].flags = IEEE80211_TX_RC_MCS;
+        tx_info->control.rates[1].idx = -1;
+
+        init_completion(&sc->paprd_complete);
+        sc->paprd_pending = true;
+        txctl.paprd = BIT(chain);
+        if (ath_tx_start(hw, skb, &txctl) != 0)
+                return false;
+
+        time_left = wait_for_completion_timeout(&sc->paprd_complete,
+                        msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
+        sc->paprd_pending = false;
+
+        if (!time_left)
+                ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CALIBRATE,
+                        "Timeout waiting for paprd training on TX chain %d\n",
+                        chain);
+
+        return !!time_left;
+}
+
 void ath_paprd_calibrate(struct work_struct *work)
 {
         struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
@@ -335,28 +364,23 @@ void ath_paprd_calibrate(struct work_struct *work)
         struct ath_hw *ah = sc->sc_ah;
         struct ieee80211_hdr *hdr;
         struct sk_buff *skb = NULL;
-        struct ieee80211_tx_info *tx_info;
-        int band = hw->conf.channel->band;
-        struct ieee80211_supported_band *sband = &sc->sbands[band];
-        struct ath_tx_control txctl;
         struct ath9k_hw_cal_data *caldata = ah->caldata;
         struct ath_common *common = ath9k_hw_common(ah);
-        int qnum, ftype;
+        int ftype;
         int chain_ok = 0;
         int chain;
         int len = 1800;
-        int time_left;
-        int i;
 
         if (!caldata)
                 return;
 
+        if (ar9003_paprd_init_table(ah) < 0)
+                return;
+
         skb = alloc_skb(len, GFP_KERNEL);
         if (!skb)
                 return;
 
-        tx_info = IEEE80211_SKB_CB(skb);
-
         skb_put(skb, len);
         memset(skb->data, 0, len);
         hdr = (struct ieee80211_hdr *)skb->data;
@@ -367,40 +391,25 @@ void ath_paprd_calibrate(struct work_struct *work)
         memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
         memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
 
-        memset(&txctl, 0, sizeof(txctl));
-        qnum = sc->tx.hwq_map[WME_AC_BE];
-        txctl.txq = &sc->tx.txq[qnum];
-
         ath9k_ps_wakeup(sc);
-        ar9003_paprd_init_table(ah);
         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
                 if (!(common->tx_chainmask & BIT(chain)))
                         continue;
 
                 chain_ok = 0;
-                memset(tx_info, 0, sizeof(*tx_info));
-                tx_info->band = band;
 
-                for (i = 0; i < 4; i++) {
-                        tx_info->control.rates[i].idx = sband->n_bitrates - 1;
-                        tx_info->control.rates[i].count = 6;
-                }
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Sending PAPRD frame for thermal measurement "
+                        "on chain %d\n", chain);
+                if (!ath_paprd_send_frame(sc, skb, chain))
+                        goto fail_paprd;
 
-                init_completion(&sc->paprd_complete);
                 ar9003_paprd_setup_gain_table(ah, chain);
-                txctl.paprd = BIT(chain);
-                if (ath_tx_start(hw, skb, &txctl) != 0)
-                        break;
 
-                time_left = wait_for_completion_timeout(&sc->paprd_complete,
-                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
-                if (!time_left) {
-                        ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
-                                  "Timeout waiting for paprd training on "
-                                  "TX chain %d\n",
-                                  chain);
+                ath_dbg(common, ATH_DBG_CALIBRATE,
+                        "Sending PAPRD training frame on chain %d\n", chain);
+                if (!ath_paprd_send_frame(sc, skb, chain))
                         goto fail_paprd;
-                }
 
                 if (!ar9003_paprd_is_done(ah))
                         break;
@@ -457,7 +466,7 @@ void ath_ani_calibrate(unsigned long data)
         /* Long calibration runs independently of short calibration. */
         if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
                 longcal = true;
-                ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
+                ath_dbg(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
                 common->ani.longcal_timer = timestamp;
         }
 
@@ -465,8 +474,8 @@ void ath_ani_calibrate(unsigned long data)
         if (!common->ani.caldone) {
                 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
                         shortcal = true;
-                        ath_print(common, ATH_DBG_ANI,
-                                  "shortcal @%lu\n", jiffies);
+                        ath_dbg(common, ATH_DBG_ANI,
+                                "shortcal @%lu\n", jiffies);
                         common->ani.shortcal_timer = timestamp;
                         common->ani.resetcal_timer = timestamp;
                 }
@@ -525,49 +534,25 @@ set_timer:
         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
                 if (!ah->caldata->paprd_done)
                         ieee80211_queue_work(sc->hw, &sc->paprd_work);
-                else
+                else if (!ah->paprd_table_write_done)
                         ath_paprd_activate(sc);
         }
 }
 
-/*
- * Update tx/rx chainmask. For legacy association,
- * hard code chainmask to 1x1, for 11n association, use
- * the chainmask configuration, for bt coexistence, use
- * the chainmask configuration even in legacy mode.
- */
-void ath_update_chainmask(struct ath_softc *sc, int is_ht)
-{
-        struct ath_hw *ah = sc->sc_ah;
-        struct ath_common *common = ath9k_hw_common(ah);
-
-        if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
-            (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
-                common->tx_chainmask = ah->caps.tx_chainmask;
-                common->rx_chainmask = ah->caps.rx_chainmask;
-        } else {
-                common->tx_chainmask = 1;
-                common->rx_chainmask = 1;
-        }
-
-        ath_print(common, ATH_DBG_CONFIG,
-                  "tx chmask: %d, rx chmask: %d\n",
-                  common->tx_chainmask,
-                  common->rx_chainmask);
-}
-
 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 {
         struct ath_node *an;
-
+        struct ath_hw *ah = sc->sc_ah;
         an = (struct ath_node *)sta->drv_priv;
 
+        if ((ah->caps.hw_caps) & ATH9K_HW_CAP_APM)
+                sc->sc_flags |= SC_OP_ENABLE_APM;
+
         if (sc->sc_flags & SC_OP_TXAGGR) {
                 ath_tx_node_init(sc, an);
                 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
                                      sta->ht_cap.ampdu_factor);
                 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
-                an->last_rssi = ATH_RSSI_DUMMY_MARKER;
         }
 }
 
@@ -615,6 +600,8 @@ void ath9k_tasklet(unsigned long data)
                 return;
         }
 
+        spin_lock(&sc->sc_pcu_lock);
+
         if (!ath9k_hw_check_alive(ah))
                 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
 
@@ -625,15 +612,12 @@ void ath9k_tasklet(unsigned long data)
                 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
 
         if (status & rxmask) {
-                spin_lock_bh(&sc->rx.pcu_lock);
-
                 /* Check for high priority Rx first */
                 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
                     (status & ATH9K_INT_RXHP))
                         ath_rx_tasklet(sc, 0, true);
 
                 ath_rx_tasklet(sc, 0, false);
-                spin_unlock_bh(&sc->rx.pcu_lock);
         }
 
         if (status & ATH9K_INT_TX) {
@@ -648,8 +632,8 @@ void ath9k_tasklet(unsigned long data)
                  * TSF sync does not look correct; remain awake to sync with
                  * the next Beacon.
                  */
-                ath_print(common, ATH_DBG_PS,
-                          "TSFOOR - Sync with next Beacon\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "TSFOOR - Sync with next Beacon\n");
                 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
         }
 
@@ -658,7 +642,9 @@ void ath9k_tasklet(unsigned long data)
                         ath_gen_timer_isr(sc->sc_ah);
 
         /* re-enable hardware interrupt */
-        ath9k_hw_set_interrupts(ah, ah->imask);
+        ath9k_hw_enable_interrupts(ah);
+
+        spin_unlock(&sc->sc_pcu_lock);
         ath9k_ps_restore(sc);
 }
 
@@ -757,7 +743,7 @@ irqreturn_t ath_isr(int irq, void *dev)
                  * interrupt; otherwise it will continue to
                  * fire.
                  */
-                ath9k_hw_set_interrupts(ah, 0);
+                ath9k_hw_disable_interrupts(ah);
                 /*
                  * Let the hal handle the event. We assume
                  * it will clear whatever condition caused
@@ -766,11 +752,13 @@ irqreturn_t ath_isr(int irq, void *dev)
                 spin_lock(&common->cc_lock);
                 ath9k_hw_proc_mib_event(ah);
                 spin_unlock(&common->cc_lock);
-                ath9k_hw_set_interrupts(ah, ah->imask);
+                ath9k_hw_enable_interrupts(ah);
         }
 
         if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                 if (status & ATH9K_INT_TIM_TIMER) {
+                        if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
+                                goto chip_reset;
                         /* Clear RxAbort bit so that we can
                          * receive frames */
                         ath9k_setpower(sc, ATH9K_PM_AWAKE);
@@ -783,8 +771,8 @@ chip_reset:
         ath_debug_stat_interrupt(sc, status);
 
         if (sched) {
-                /* turn off every interrupt except SWBA */
-                ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
+                /* turn off every interrupt */
+                ath9k_hw_disable_interrupts(ah);
                 tasklet_schedule(&sc->intr_tq);
         }
 
@@ -836,16 +824,18 @@ static u32 ath_get_extchanmode(struct ath_softc *sc,
 }
 
 static void ath9k_bss_assoc_info(struct ath_softc *sc,
+                                 struct ieee80211_hw *hw,
                                  struct ieee80211_vif *vif,
                                  struct ieee80211_bss_conf *bss_conf)
 {
+        struct ath_wiphy *aphy = hw->priv;
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
 
         if (bss_conf->assoc) {
-                ath_print(common, ATH_DBG_CONFIG,
-                          "Bss Info ASSOC %d, bssid: %pM\n",
-                           bss_conf->aid, common->curbssid);
+                ath_dbg(common, ATH_DBG_CONFIG,
+                        "Bss Info ASSOC %d, bssid: %pM\n",
+                        bss_conf->aid, common->curbssid);
 
                 /* New association, store aid */
                 common->curaid = bss_conf->aid;
@@ -862,12 +852,13 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
                 ath_beacon_config(sc, vif);
 
                 /* Reset rssi stats */
+                aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
                 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
 
                 sc->sc_flags |= SC_OP_ANI_RUN;
                 ath_start_ani(common);
         } else {
-                ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
+                ath_dbg(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
                 common->curaid = 0;
                 /* Stop ANI */
                 sc->sc_flags &= ~SC_OP_ANI_RUN;
@@ -883,31 +874,25 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
         int r;
 
         ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ath9k_hw_configpcipowersave(ah, 0, 0);
 
         if (!ah->curchan)
                 ah->curchan = ath_get_curchannel(sc, sc->hw);
 
-        spin_lock_bh(&sc->rx.pcu_lock);
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
+                ath_err(common,
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         ath_update_txpow(sc);
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to restart recv logic\n");
-                spin_unlock_bh(&sc->rx.pcu_lock);
-                return;
+                ath_err(common, "Unable to restart recv logic\n");
+                goto out;
         }
-        spin_unlock_bh(&sc->rx.pcu_lock);
-
         if (sc->sc_flags & SC_OP_BEACONS)
                 ath_beacon_config(sc, NULL);    /* restart beacons */
 
@@ -920,6 +905,9 @@ void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
         ath9k_hw_set_gpio(ah, ah->led_pin, 0);
 
         ieee80211_wake_queues(hw);
+out:
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
 }
 
@@ -930,6 +918,8 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
         int r;
 
         ath9k_ps_wakeup(sc);
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ieee80211_stop_queues(hw);
 
         /*
@@ -942,34 +932,30 @@ void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
         }
 
         /* Disable interrupts */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
 
         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
 
-        spin_lock_bh(&sc->rx.pcu_lock);
-
         ath_stoprecv(sc);               /* turn off frame recv */
         ath_flushrecv(sc);              /* flush recv queue */
 
         if (!ah->curchan)
                 ah->curchan = ath_get_curchannel(sc, hw);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
         if (r) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to reset channel (%u MHz), "
-                          "reset status %d\n",
-                          channel->center_freq, r);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to reset channel (%u MHz), reset status %d\n",
+                        channel->center_freq, r);
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         ath9k_hw_phy_disable(ah);
 
-        spin_unlock_bh(&sc->rx.pcu_lock);
-
         ath9k_hw_configpcipowersave(ah, 1, 1);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
         ath9k_ps_restore(sc);
+
         ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
 }
 
@@ -983,28 +969,23 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         /* Stop ANI */
         del_timer_sync(&common->ani.timer);
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         ieee80211_stop_queues(hw);
 
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
         ath_drain_all_txq(sc, retry_tx);
 
-        spin_lock_bh(&sc->rx.pcu_lock);
-
         ath_stoprecv(sc);
         ath_flushrecv(sc);
 
-        spin_lock_bh(&sc->sc_resetlock);
         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
         if (r)
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d\n", r);
-        spin_unlock_bh(&sc->sc_resetlock);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d\n", r);
 
         if (ath_startrecv(sc) != 0)
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to start recv logic\n");
-
-        spin_unlock_bh(&sc->rx.pcu_lock);
+                ath_err(common, "Unable to start recv logic\n");
 
         /*
          * We may be doing a reset in response to a request
@@ -1030,6 +1011,7 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         }
 
         ieee80211_wake_queues(hw);
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         /* Start ANI */
         ath_start_ani(common);
@@ -1037,56 +1019,6 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
         return r;
 }
 
-static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
-{
-        int qnum;
-
-        switch (queue) {
-        case 0:
-                qnum = sc->tx.hwq_map[WME_AC_VO];
-                break;
-        case 1:
-                qnum = sc->tx.hwq_map[WME_AC_VI];
-                break;
-        case 2:
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                break;
-        case 3:
-                qnum = sc->tx.hwq_map[WME_AC_BK];
-                break;
-        default:
-                qnum = sc->tx.hwq_map[WME_AC_BE];
-                break;
-        }
-
-        return qnum;
-}
-
-int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
-{
-        int qnum;
-
-        switch (queue) {
-        case WME_AC_VO:
-                qnum = 0;
-                break;
-        case WME_AC_VI:
-                qnum = 1;
-                break;
-        case WME_AC_BE:
-                qnum = 2;
-                break;
-        case WME_AC_BK:
-                qnum = 3;
-                break;
-        default:
-                qnum = -1;
-                break;
-        }
-
-        return qnum;
-}
-
 /* XXX: Remove me once we don't depend on ath9k_channel for all
  * this redundant data */
 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
@@ -1125,9 +1057,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
         struct ath9k_channel *init_channel;
         int r;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Starting driver with initial channel: %d MHz\n",
-                  curchan->center_freq);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Starting driver with initial channel: %d MHz\n",
+                curchan->center_freq);
 
         mutex_lock(&sc->mutex);
 
@@ -1168,19 +1100,15 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * be followed by initialization of the appropriate bits
          * and then setup of the interrupt mask.
          */
-        spin_lock_bh(&sc->rx.pcu_lock);
-        spin_lock_bh(&sc->sc_resetlock);
+        spin_lock_bh(&sc->sc_pcu_lock);
         r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
         if (r) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to reset hardware; reset status %d "
-                          "(freq %u MHz)\n", r,
-                          curchan->center_freq);
-                spin_unlock_bh(&sc->sc_resetlock);
-                spin_unlock_bh(&sc->rx.pcu_lock);
+                ath_err(common,
+                        "Unable to reset hardware; reset status %d (freq %u MHz)\n",
+                        r, curchan->center_freq);
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 goto mutex_unlock;
         }
-        spin_unlock_bh(&sc->sc_resetlock);
 
         /*
          * This is needed only to setup initial state
@@ -1196,13 +1124,12 @@ static int ath9k_start(struct ieee80211_hw *hw)
          * here except setup the interrupt mask.
          */
         if (ath_startrecv(sc) != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Unable to start recv logic\n");
+                ath_err(common, "Unable to start recv logic\n");
                 r = -EIO;
-                spin_unlock_bh(&sc->rx.pcu_lock);
+                spin_unlock_bh(&sc->sc_pcu_lock);
                 goto mutex_unlock;
         }
-        spin_unlock_bh(&sc->rx.pcu_lock);
+        spin_unlock_bh(&sc->sc_pcu_lock);
 
         /* Setup our intr mask. */
         ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
@@ -1244,7 +1171,14 @@ static int ath9k_start(struct ieee80211_hw *hw)
                         ath9k_btcoex_timer_resume(sc);
         }
 
-        pm_qos_update_request(&sc->pm_qos_req, 55);
+        /* User has the option to provide pm-qos value as a module
+         * parameter rather than using the default value of
+         * 'ATH9K_PM_QOS_DEFAULT_VALUE'.
+         */
+        pm_qos_update_request(&sc->pm_qos_req, ath9k_pm_qos_value);
+
+        if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
+                common->bus_ops->extn_synch_en(common);
 
 mutex_unlock:
         mutex_unlock(&sc->mutex);
@@ -1255,19 +1189,16 @@ mutex_unlock:
 static int ath9k_tx(struct ieee80211_hw *hw,
                     struct sk_buff *skb)
 {
-        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_tx_control txctl;
-        int padpos, padsize;
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
-        int qnum;
 
         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
-                ath_print(common, ATH_DBG_XMIT,
-                          "ath9k: %s: TX in unexpected wiphy state "
-                          "%d\n", wiphy_name(hw->wiphy), aphy->state);
+                ath_dbg(common, ATH_DBG_XMIT,
+                        "ath9k: %s: TX in unexpected wiphy state %d\n",
+                        wiphy_name(hw->wiphy), aphy->state);
                 goto exit;
         }
 
@@ -1279,8 +1210,8 @@ static int ath9k_tx(struct ieee80211_hw *hw,
                 if (ieee80211_is_data(hdr->frame_control) &&
                     !ieee80211_is_nullfunc(hdr->frame_control) &&
                     !ieee80211_has_pm(hdr->frame_control)) {
-                        ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
-                                  "while in PS mode\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Add PM=1 for a TX frame while in PS mode\n");
                         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
                 }
         }
@@ -1295,12 +1226,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
                 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
                         ath9k_hw_setrxabort(sc->sc_ah, 0);
                 if (ieee80211_is_pspoll(hdr->frame_control)) {
-                        ath_print(common, ATH_DBG_PS,
-                                  "Sending PS-Poll to pick a buffered frame\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Sending PS-Poll to pick a buffered frame\n");
                         sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
                 } else {
-                        ath_print(common, ATH_DBG_PS,
-                                  "Wake up to complete TX\n");
+                        ath_dbg(common, ATH_DBG_PS,
+                                "Wake up to complete TX\n");
                         sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
                 }
                 /*
@@ -1312,36 +1243,12 @@ static int ath9k_tx(struct ieee80211_hw *hw,
         }
 
         memset(&txctl, 0, sizeof(struct ath_tx_control));
+        txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
 
-        /*
-         * As a temporary workaround, assign seq# here; this will likely need
-         * to be cleaned up to work better with Beacon transmission and virtual
-         * BSSes.
-         */
-        if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
-                if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
-                        sc->tx.seq_no += 0x10;
-                hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
-                hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
-        }
-
-        /* Add the padding after the header if this is not already done */
-        padpos = ath9k_cmn_padpos(hdr->frame_control);
-        padsize = padpos & 3;
-        if (padsize && skb->len>padpos) {
-                if (skb_headroom(skb) < padsize)
-                        return -1;
-                skb_push(skb, padsize);
-                memmove(skb->data, skb->data + padsize, padpos);
-        }
-
-        qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
-        txctl.txq = &sc->tx.txq[qnum];
-
-        ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
+        ath_dbg(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
 
         if (ath_tx_start(hw, skb, &txctl) != 0) {
-                ath_print(common, ATH_DBG_XMIT, "TX failed\n");
+                ath_dbg(common, ATH_DBG_XMIT, "TX failed\n");
                 goto exit;
         }
 
@@ -1381,7 +1288,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
         }
 
         if (sc->sc_flags & SC_OP_INVALID) {
-                ath_print(common, ATH_DBG_ANY, "Device not present\n");
+                ath_dbg(common, ATH_DBG_ANY, "Device not present\n");
                 mutex_unlock(&sc->mutex);
                 return;
         }
@@ -1400,26 +1307,30 @@ static void ath9k_stop(struct ieee80211_hw *hw)
                         ath9k_btcoex_timer_pause(sc);
         }
 
+        spin_lock_bh(&sc->sc_pcu_lock);
+
         /* make sure h/w will not generate any interrupt
          * before setting the invalid flag. */
-        ath9k_hw_set_interrupts(ah, 0);
+        ath9k_hw_disable_interrupts(ah);
 
-        spin_lock_bh(&sc->rx.pcu_lock);
         if (!(sc->sc_flags & SC_OP_INVALID)) {
                 ath_drain_all_txq(sc, false);
                 ath_stoprecv(sc);
                 ath9k_hw_phy_disable(ah);
         } else
                 sc->rx.rxlink = NULL;
-        spin_unlock_bh(&sc->rx.pcu_lock);
 
         /* disable HAL and put h/w to sleep */
         ath9k_hw_disable(ah);
         ath9k_hw_configpcipowersave(ah, 1, 1);
+
+        spin_unlock_bh(&sc->sc_pcu_lock);
+
         ath9k_ps_restore(sc);
 
-        /* Finally, put the chip in FULL SLEEP mode */
-        ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
+        sc->ps_idle = true;
+        ath9k_set_wiphy_idle(aphy, true);
+        ath_radio_disable(sc, hw);
 
         sc->sc_flags |= SC_OP_INVALID;
 
@@ -1427,7 +1338,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
 
         mutex_unlock(&sc->mutex);
 
-        ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Driver halt\n");
 }
 
 static int ath9k_add_interface(struct ieee80211_hw *hw,
@@ -1460,14 +1371,14 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
                 ic_opmode = vif->type;
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                        "Interface type %d not yet supported\n", vif->type);
+                ath_err(common, "Interface type %d not yet supported\n",
+                        vif->type);
                 ret = -EOPNOTSUPP;
                 goto out;
         }
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Attach a VIF of type: %d\n", ic_opmode);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Attach a VIF of type: %d\n", ic_opmode);
 
         /* Set the VIF opmode */
         avp->av_opmode = ic_opmode;
@@ -1513,15 +1424,83 @@ out:
         return ret;
 }
 
+static void ath9k_reclaim_beacon(struct ath_softc *sc,
+                                 struct ieee80211_vif *vif)
+{
+        struct ath_vif *avp = (void *)vif->drv_priv;
+
+        /* Disable SWBA interrupt */
+        sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
+        ath9k_ps_wakeup(sc);
+        ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
+        ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
+        tasklet_kill(&sc->bcon_tasklet);
+        ath9k_ps_restore(sc);
+
+        ath_beacon_return(sc, avp);
+        sc->sc_flags &= ~SC_OP_BEACONS;
+
+        if (sc->nbcnvifs > 0) {
+                /* Re-enable beaconing */
+                sc->sc_ah->imask |= ATH9K_INT_SWBA;
+                ath9k_ps_wakeup(sc);
+                ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
+                ath9k_ps_restore(sc);
+        }
+}
+
+static int ath9k_change_interface(struct ieee80211_hw *hw,
+                                  struct ieee80211_vif *vif,
+                                  enum nl80211_iftype new_type,
+                                  bool p2p)
+{
+        struct ath_wiphy *aphy = hw->priv;
+        struct ath_softc *sc = aphy->sc;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        int ret = 0;
+
+        ath_dbg(common, ATH_DBG_CONFIG, "Change Interface\n");
+        mutex_lock(&sc->mutex);
+
+        switch (new_type) {
+        case NL80211_IFTYPE_AP:
+        case NL80211_IFTYPE_ADHOC:
+                if (sc->nbcnvifs >= ATH_BCBUF) {
+                        ath_err(common, "No beacon slot available\n");
+                        ret = -ENOBUFS;
+                        goto out;
+                }
+                break;
+        case NL80211_IFTYPE_STATION:
+                /* Stop ANI */
+                sc->sc_flags &= ~SC_OP_ANI_RUN;
+                del_timer_sync(&common->ani.timer);
+                if ((vif->type == NL80211_IFTYPE_AP) ||
+                    (vif->type == NL80211_IFTYPE_ADHOC))
+                        ath9k_reclaim_beacon(sc, vif);
+                break;
+        default:
+                ath_err(common, "Interface type %d not yet supported\n",
+                                vif->type);
+                ret = -ENOTSUPP;
+                goto out;
+        }
+        vif->type = new_type;
+        vif->p2p = p2p;
+
+out:
+        mutex_unlock(&sc->mutex);
+        return ret;
+}
+
 static void ath9k_remove_interface(struct ieee80211_hw *hw,
                                    struct ieee80211_vif *vif)
 {
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ath_vif *avp = (void *)vif->drv_priv;
 
-        ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Detach Interface\n");
 
         mutex_lock(&sc->mutex);
 
@@ -1532,26 +1511,8 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
         /* Reclaim beacon resources */
         if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
             (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
-            (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
-                /* Disable SWBA interrupt */
-                sc->sc_ah->imask &= ~ATH9K_INT_SWBA;
-                ath9k_ps_wakeup(sc);
-                ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
-                ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
-                ath9k_ps_restore(sc);
-                tasklet_kill(&sc->bcon_tasklet);
-        }
-
-        ath_beacon_return(sc, avp);
-        sc->sc_flags &= ~SC_OP_BEACONS;
-
-        if (sc->nbcnvifs) {
-                /* Re-enable SWBA interrupt */
-                sc->sc_ah->imask |= ATH9K_INT_SWBA;
-                ath9k_ps_wakeup(sc);
-                ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_ah->imask);
-                ath9k_ps_restore(sc);
-        }
+            (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT))
+                ath9k_reclaim_beacon(sc, vif);
 
         sc->nvifs--;
 
@@ -1631,8 +1592,8 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
                 if (enable_radio) {
                         sc->ps_idle = false;
                         ath_radio_enable(sc, hw);
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "not-idle: enabling radio\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "not-idle: enabling radio\n");
                 }
         }
 
@@ -1654,12 +1615,12 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
 
         if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
                 if (conf->flags & IEEE80211_CONF_MONITOR) {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "Monitor mode is enabled\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor mode is enabled\n");
                         sc->sc_ah->is_monitoring = true;
                 } else {
-                        ath_print(common, ATH_DBG_CONFIG,
-                                  "Monitor mode is disabled\n");
+                        ath_dbg(common, ATH_DBG_CONFIG,
+                                "Monitor mode is disabled\n");
                         sc->sc_ah->is_monitoring = false;
                 }
         }
@@ -1691,14 +1652,12 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
                         goto skip_chan_change;
                 }
 
-                ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
-                          curchan->center_freq);
+                ath_dbg(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
+                        curchan->center_freq);
 
                 /* XXX: remove me eventualy */
                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
 
-                ath_update_chainmask(sc, conf_is_ht(conf));
-
                 /* update survey stats for the old channel before switching */
                 spin_lock_irqsave(&common->cc_lock, flags);
                 ath_update_survey_stats(sc);
@@ -1725,8 +1684,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
                 }
 
                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "Unable to set channel\n");
+                        ath_err(common, "Unable to set channel\n");
                         mutex_unlock(&sc->mutex);
                         return -EINVAL;
                 }
@@ -1751,7 +1709,7 @@ skip_chan_change:
         spin_unlock_bh(&sc->wiphy_lock);
 
         if (disable_radio) {
-                ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
+                ath_dbg(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
                 sc->ps_idle = true;
                 ath_radio_disable(sc, hw);
         }
@@ -1790,8 +1748,8 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
         ath9k_ps_restore(sc);
 
-        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                  "Set HW RX filter: 0x%x\n", rfilt);
+        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                "Set HW RX filter: 0x%x\n", rfilt);
 }
 
 static int ath9k_sta_add(struct ieee80211_hw *hw,
@@ -1824,12 +1782,15 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_txq *txq;
         struct ath9k_tx_queue_info qi;
-        int ret = 0, qnum;
+        int ret = 0;
 
         if (queue >= WME_NUM_AC)
                 return 0;
 
+        txq = sc->tx.txq_map[queue];
+
         mutex_lock(&sc->mutex);
 
         memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
@@ -1838,20 +1799,18 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
         qi.tqi_cwmin = params->cw_min;
         qi.tqi_cwmax = params->cw_max;
         qi.tqi_burstTime = params->txop;
-        qnum = ath_get_hal_qnum(queue, sc);
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "Configure tx [queue/halq] [%d/%d],  "
-                  "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
-                  queue, qnum, params->aifs, params->cw_min,
-                  params->cw_max, params->txop);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
+                queue, txq->axq_qnum, params->aifs, params->cw_min,
+                params->cw_max, params->txop);
 
-        ret = ath_txq_update(sc, qnum, &qi);
+        ret = ath_txq_update(sc, txq->axq_qnum, &qi);
         if (ret)
-                ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
+                ath_err(common, "TXQ Update failed\n");
 
         if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
-                if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
+                if (queue == WME_AC_BE && !ret)
                         ath_beaconq_config(sc);
 
         mutex_unlock(&sc->mutex);
@@ -1870,12 +1829,12 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         int ret = 0;
 
-        if (modparam_nohwcrypt)
+        if (ath9k_modparam_nohwcrypt)
                 return -ENOSPC;
 
         mutex_lock(&sc->mutex);
         ath9k_ps_wakeup(sc);
-        ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
+        ath_dbg(common, ATH_DBG_CONFIG, "Set HW Key\n");
 
         switch (cmd) {
         case SET_KEY:
@@ -1930,13 +1889,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
                 /* Set aggregation protection mode parameters */
                 sc->config.ath_aggr_prot = 0;
 
-                /* Only legacy IBSS for now */
-                if (vif->type == NL80211_IFTYPE_ADHOC)
-                        ath_update_chainmask(sc, 0);
-
-                ath_print(common, ATH_DBG_CONFIG,
-                          "BSSID: %pM aid: 0x%x\n",
-                          common->curbssid, common->curaid);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSSID: %pM aid: 0x%x\n",
+                        common->curbssid, common->curaid);
 
                 /* need to reconfigure the beacon */
                 sc->sc_flags &= ~SC_OP_BEACONS ;
@@ -1992,8 +1946,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
-                          bss_conf->use_short_preamble);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
+                        bss_conf->use_short_preamble);
                 if (bss_conf->use_short_preamble)
                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
                 else
@@ -2001,8 +1955,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
-                          bss_conf->use_cts_prot);
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
+                        bss_conf->use_cts_prot);
                 if (bss_conf->use_cts_prot &&
                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
@@ -2011,9 +1965,9 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
         }
 
         if (changed & BSS_CHANGED_ASSOC) {
-                ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
+                ath_dbg(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
                         bss_conf->assoc);
-                ath9k_bss_assoc_info(sc, vif, bss_conf);
+                ath9k_bss_assoc_info(sc, hw, vif, bss_conf);
         }
 
         mutex_unlock(&sc->mutex);
@@ -2026,7 +1980,9 @@ static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
         struct ath_softc *sc = aphy->sc;
 
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
         tsf = ath9k_hw_gettsf64(sc->sc_ah);
+        ath9k_ps_restore(sc);
         mutex_unlock(&sc->mutex);
 
         return tsf;
@@ -2038,7 +1994,9 @@ static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
         struct ath_softc *sc = aphy->sc;
 
         mutex_lock(&sc->mutex);
+        ath9k_ps_wakeup(sc);
         ath9k_hw_settsf64(sc->sc_ah, tsf);
+        ath9k_ps_restore(sc);
         mutex_unlock(&sc->mutex);
 }
 
@@ -2076,6 +2034,9 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
         case IEEE80211_AMPDU_RX_STOP:
                 break;
         case IEEE80211_AMPDU_TX_START:
+                if (!(sc->sc_flags & SC_OP_TXAGGR))
+                        return -EOPNOTSUPP;
+
                 ath9k_ps_wakeup(sc);
                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
                 if (!ret)
@@ -2094,8 +2055,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                 ath9k_ps_restore(sc);
                 break;
         default:
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unknown AMPDU action\n");
+                ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
         }
 
         local_bh_enable();
@@ -2195,6 +2155,7 @@ struct ieee80211_ops ath9k_ops = {
         .start              = ath9k_start,
         .stop               = ath9k_stop,
         .add_interface      = ath9k_add_interface,
+        .change_interface   = ath9k_change_interface,
         .remove_interface   = ath9k_remove_interface,
         .config             = ath9k_config,
         .configure_filter   = ath9k_configure_filter,
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index b5b651413e77..78ef1f13386f 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -16,6 +16,7 @@
 
 #include <linux/nl80211.h>
 #include <linux/pci.h>
+#include <linux/ath9k_platform.h>
 #include "ath9k.h"
 
 static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
@@ -29,6 +30,7 @@ static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
         { PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
         { PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
         { PCI_VDEVICE(ATHEROS, 0x0030) }, /* PCI-E  AR9300 */
+        { PCI_VDEVICE(ATHEROS, 0x0032) }, /* PCI-E  AR9485 */
         { 0 }
 };
 
@@ -53,21 +55,35 @@ static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
 
 static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
 {
-        struct ath_hw *ah = (struct ath_hw *) common->ah;
-
-        common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
-
-        if (!ath9k_hw_wait(ah,
-                           AR_EEPROM_STATUS_DATA,
-                           AR_EEPROM_STATUS_DATA_BUSY |
-                           AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
-                           AH_WAIT_TIMEOUT)) {
-                return false;
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        struct ath9k_platform_data *pdata = sc->dev->platform_data;
+
+        if (pdata) {
+                if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
+                        ath_err(common,
+                                "%s: eeprom read failed, offset %08x is out of range\n",
+                                __func__, off);
+                }
+
+                *data = pdata->eeprom_data[off];
+        } else {
+                struct ath_hw *ah = (struct ath_hw *) common->ah;
+
+                common->ops->read(ah, AR5416_EEPROM_OFFSET +
+                                      (off << AR5416_EEPROM_S));
+
+                if (!ath9k_hw_wait(ah,
+                                   AR_EEPROM_STATUS_DATA,
+                                   AR_EEPROM_STATUS_DATA_BUSY |
+                                   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
+                                   AH_WAIT_TIMEOUT)) {
+                        return false;
+                }
+
+                *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
+                           AR_EEPROM_STATUS_DATA_VAL);
         }
 
-        *data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
-                   AR_EEPROM_STATUS_DATA_VAL);
-
         return true;
 }
 
@@ -80,7 +96,7 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
         struct pci_dev *pdev = to_pci_dev(sc->dev);
         u8 aspm;
 
-        if (!pdev->is_pcie)
+        if (!pci_is_pcie(pdev))
                 return;
 
         pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
@@ -88,11 +104,23 @@ static void ath_pci_bt_coex_prep(struct ath_common *common)
         pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
 }
 
+static void ath_pci_extn_synch_enable(struct ath_common *common)
+{
+        struct ath_softc *sc = (struct ath_softc *) common->priv;
+        struct pci_dev *pdev = to_pci_dev(sc->dev);
+        u8 lnkctl;
+
+        pci_read_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, &lnkctl);
+        lnkctl |= PCI_EXP_LNKCTL_ES;
+        pci_write_config_byte(pdev, sc->sc_ah->caps.pcie_lcr_offset, lnkctl);
+}
+
 static const struct ath_bus_ops ath_pci_bus_ops = {
         .ath_bus_type = ATH_PCI,
         .read_cachesize = ath_pci_read_cachesize,
         .eeprom_read = ath_pci_eeprom_read,
         .bt_coex_prep = ath_pci_bt_coex_prep,
+        .extn_synch_en = ath_pci_extn_synch_enable,
 };
 
 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
@@ -236,6 +264,8 @@ static void ath_pci_remove(struct pci_dev *pdev)
         struct ath_softc *sc = aphy->sc;
         void __iomem *mem = sc->mem;
 
+        if (!is_ath9k_unloaded)
+                sc->sc_ah->ah_flags |= AH_UNPLUGGED;
         ath9k_deinit_device(sc);
         free_irq(sc->irq, sc);
         ieee80211_free_hw(sc->hw);
@@ -247,34 +277,25 @@ static void ath_pci_remove(struct pci_dev *pdev)
 
 #ifdef CONFIG_PM
 
-static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+static int ath_pci_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
 
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
-        pci_save_state(pdev);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, PCI_D3hot);
-
         return 0;
 }
 
-static int ath_pci_resume(struct pci_dev *pdev)
+static int ath_pci_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
         u32 val;
-        int err;
-
-        pci_restore_state(pdev);
-
-        err = pci_enable_device(pdev);
-        if (err)
-                return err;
 
         /*
          * Suspend/Resume resets the PCI configuration space, so we have to
@@ -290,10 +311,38 @@ static int ath_pci_resume(struct pci_dev *pdev)
                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
         ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
 
+          /*
+           * Reset key cache to sane defaults (all entries cleared) instead of
+           * semi-random values after suspend/resume.
+           */
+        ath9k_ps_wakeup(sc);
+        ath9k_init_crypto(sc);
+        ath9k_ps_restore(sc);
+
+        sc->ps_idle = true;
+        ath9k_set_wiphy_idle(aphy, true);
+        ath_radio_disable(sc, hw);
+
         return 0;
 }
 
-#endif /* CONFIG_PM */
+static const struct dev_pm_ops ath9k_pm_ops = {
+        .suspend = ath_pci_suspend,
+        .resume = ath_pci_resume,
+        .freeze = ath_pci_suspend,
+        .thaw = ath_pci_resume,
+        .poweroff = ath_pci_suspend,
+        .restore = ath_pci_resume,
+};
+
+#define ATH9K_PM_OPS    (&ath9k_pm_ops)
+
+#else /* !CONFIG_PM */
+
+#define ATH9K_PM_OPS    NULL
+
+#endif /* !CONFIG_PM */
+
 
 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 
@@ -302,10 +351,7 @@ static struct pci_driver ath_pci_driver = {
         .id_table   = ath_pci_id_table,
         .probe      = ath_pci_probe,
         .remove     = ath_pci_remove,
-#ifdef CONFIG_PM
-        .suspend    = ath_pci_suspend,
-        .resume     = ath_pci_resume,
-#endif /* CONFIG_PM */
+        .driver.pm  = ATH9K_PM_OPS,
 };
 
 int ath_pci_init(void)
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 17969af842f6..5e3d7496986e 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -19,6 +19,7 @@
 
 #define CHANSEL_DIV             15
 #define CHANSEL_2G(_freq)       (((_freq) * 0x10000) / CHANSEL_DIV)
+#define CHANSEL_2G_9485(_freq)  ((((_freq) * 0x10000) - 215) / CHANSEL_DIV)
 #define CHANSEL_5G(_freq)       (((_freq) * 0x8000) / CHANSEL_DIV)
 
 #define AR_PHY_BASE     0x9800
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 89978d71617f..e45147820eae 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -381,25 +381,6 @@ static const struct ath_rate_table ar5416_11g_ratetable = {
 static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
                                 struct ieee80211_tx_rate *rate);
 
-static inline int8_t median(int8_t a, int8_t b, int8_t c)
-{
-        if (a >= b) {
-                if (b >= c)
-                        return b;
-                else if (a > c)
-                        return c;
-                else
-                        return a;
-        } else {
-                if (a >= c)
-                        return a;
-                else if (b >= c)
-                        return c;
-                else
-                        return b;
-        }
-}
-
 static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
                                    struct ath_rate_priv *ath_rc_priv)
 {
@@ -419,7 +400,7 @@ static void ath_rc_sort_validrates(const struct ath_rate_table *rate_table,
         }
 }
 
-static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
+static void ath_rc_init_valid_rate_idx(struct ath_rate_priv *ath_rc_priv)
 {
         u8 i;
 
@@ -427,7 +408,7 @@ static void ath_rc_init_valid_txmask(struct ath_rate_priv *ath_rc_priv)
                 ath_rc_priv->valid_rate_index[i] = 0;
 }
 
-static inline void ath_rc_set_valid_txmask(struct ath_rate_priv *ath_rc_priv,
+static inline void ath_rc_set_valid_rate_idx(struct ath_rate_priv *ath_rc_priv,
                                            u8 index, int valid_tx_rate)
 {
         BUG_ON(index > ath_rc_priv->rate_table_size);
@@ -508,7 +489,7 @@ static u8 ath_rc_init_validrates(struct ath_rate_priv *ath_rc_priv,
 
                         ath_rc_priv->valid_phy_rateidx[phy][valid_rate_count] = i;
                         ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                        ath_rc_set_valid_txmask(ath_rc_priv, i, 1);
+                        ath_rc_set_valid_rate_idx(ath_rc_priv, i, 1);
                         hi = i;
                 }
         }
@@ -551,7 +532,7 @@ static u8 ath_rc_setvalid_rates(struct ath_rate_priv *ath_rc_priv,
                                 ath_rc_priv->valid_phy_rateidx[phy]
                                         [valid_rate_count] = j;
                                 ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                                ath_rc_set_valid_txmask(ath_rc_priv, j, 1);
+                                ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
                                 hi = A_MAX(hi, j);
                         }
                 }
@@ -587,7 +568,7 @@ static u8 ath_rc_setvalid_htrates(struct ath_rate_priv *ath_rc_priv,
                         ath_rc_priv->valid_phy_rateidx[phy]
                                 [ath_rc_priv->valid_phy_ratecnt[phy]] = j;
                         ath_rc_priv->valid_phy_ratecnt[phy] += 1;
-                        ath_rc_set_valid_txmask(ath_rc_priv, j, 1);
+                        ath_rc_set_valid_rate_idx(ath_rc_priv, j, 1);
                         hi = A_MAX(hi, j);
                 }
         }
@@ -883,7 +864,7 @@ static bool ath_rc_update_per(struct ath_softc *sc,
         bool state_change = false;
         int count, n_bad_frames;
         u8 last_per;
-        static u32 nretry_to_per_lookup[10] = {
+        static const u32 nretry_to_per_lookup[10] = {
                 100 * 0 / 1,
                 100 * 1 / 4,
                 100 * 1 / 2,
@@ -1106,13 +1087,13 @@ static int ath_rc_get_rateindex(const struct ath_rate_table *rate_table,
                                 struct ieee80211_tx_rate *rate)
 {
         int rix = 0, i = 0;
-        int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
+        static const int mcs_rix_off[] = { 7, 15, 20, 21, 22, 23 };
 
         if (!(rate->flags & IEEE80211_TX_RC_MCS))
                 return rate->idx;
 
         while (rate->idx > mcs_rix_off[i] &&
-              i < sizeof(mcs_rix_off)/sizeof(int)) {
+               i < ARRAY_SIZE(mcs_rix_off)) {
                 rix++; i++;
         }
 
@@ -1203,7 +1184,7 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
                         return &ar5416_11na_ratetable;
                 return &ar5416_11a_ratetable;
         default:
-                ath_print(common, ATH_DBG_CONFIG, "Invalid band\n");
+                ath_dbg(common, ATH_DBG_CONFIG, "Invalid band\n");
                 return NULL;
         }
 }
@@ -1229,7 +1210,7 @@ static void ath_rc_init(struct ath_softc *sc,
         }
 
         /* Determine the valid rates */
-        ath_rc_init_valid_txmask(ath_rc_priv);
+        ath_rc_init_valid_rate_idx(ath_rc_priv);
 
         for (i = 0; i < WLAN_RC_PHY_MAX; i++) {
                 for (j = 0; j < MAX_TX_RATE_PHY; j++)
@@ -1278,9 +1259,9 @@ static void ath_rc_init(struct ath_softc *sc,
         ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
         ath_rc_priv->rate_table = rate_table;
 
-        ath_print(common, ATH_DBG_CONFIG,
-                  "RC Initialized with capabilities: 0x%x\n",
-                  ath_rc_priv->ht_cap);
+        ath_dbg(common, ATH_DBG_CONFIG,
+                "RC Initialized with capabilities: 0x%x\n",
+                ath_rc_priv->ht_cap);
 }
 
 static u8 ath_rc_build_ht_caps(struct ath_softc *sc, struct ieee80211_sta *sta,
@@ -1340,7 +1321,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
         struct ath_rate_priv *ath_rc_priv = priv_sta;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         struct ieee80211_hdr *hdr;
-        int final_ts_idx = 0, tx_status = 0, is_underrun = 0;
+        int final_ts_idx = 0, tx_status = 0;
         int long_retry = 0;
         __le16 fc;
         int i;
@@ -1373,32 +1354,17 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
                 tx_info->status.ampdu_len = 1;
         }
 
-        /*
-         * If an underrun error is seen assume it as an excessive retry only
-         * if max frame trigger level has been reached (2 KB for singel stream,
-         * and 4 KB for dual stream). Adjust the long retry as if the frame was
-         * tried hw->max_rate_tries times to affect how ratectrl updates PER for
-         * the failed rate. In case of congestion on the bus penalizing these
-         * type of underruns should help hardware actually transmit new frames
-         * successfully by eventually preferring slower rates. This itself
-         * should also alleviate congestion on the bus.
-         */
-        if ((tx_info->pad[0] & ATH_TX_INFO_UNDERRUN) &&
-            (sc->sc_ah->tx_trig_level >= ath_rc_priv->tx_triglevel_max)) {
-                tx_status = 1;
-                is_underrun = 1;
-        }
-
-        if (tx_info->pad[0] & ATH_TX_INFO_XRETRY)
+        if (!(tx_info->flags & IEEE80211_TX_STAT_ACK))
                 tx_status = 1;
 
         ath_rc_tx_status(sc, ath_rc_priv, tx_info, final_ts_idx, tx_status,
-                         (is_underrun) ? sc->hw->max_rate_tries : long_retry);
+                         long_retry);
 
         /* Check if aggregation has to be enabled for this tid */
         if (conf_is_ht(&sc->hw->conf) &&
             !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
-                if (ieee80211_is_data_qos(fc)) {
+                if (ieee80211_is_data_qos(fc) &&
+                    skb_get_queue_mapping(skb) != IEEE80211_AC_VO) {
                         u8 *qc, tid;
                         struct ath_node *an;
 
@@ -1407,7 +1373,7 @@ static void ath_tx_status(void *priv, struct ieee80211_supported_band *sband,
                         an = (struct ath_node *)sta->drv_priv;
 
                         if(ath_tx_aggr_check(sc, an, tid))
-                                ieee80211_start_tx_ba_session(sta, tid);
+                                ieee80211_start_tx_ba_session(sta, tid, 0);
                 }
         }
 
@@ -1444,12 +1410,12 @@ static void ath_rate_init(void *priv, struct ieee80211_supported_band *sband,
                 ath_rc_priv->neg_ht_rates.rs_nrates = j;
         }
 
-        is_cw40 = sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40;
+        is_cw40 = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40);
 
         if (is_cw40)
-                is_sgi = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40;
+                is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
         else if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
-                is_sgi = sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20;
+                is_sgi = !!(sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
 
         /* Choose rate table first */
 
@@ -1468,10 +1434,8 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
         struct ath_rate_priv *ath_rc_priv = priv_sta;
         const struct ath_rate_table *rate_table = NULL;
         bool oper_cw40 = false, oper_sgi;
-        bool local_cw40 = (ath_rc_priv->ht_cap & WLAN_RC_40_FLAG) ?
-                true : false;
-        bool local_sgi = (ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG) ?
-                true : false;
+        bool local_cw40 = !!(ath_rc_priv->ht_cap & WLAN_RC_40_FLAG);
+        bool local_sgi = !!(ath_rc_priv->ht_cap & WLAN_RC_SGI_FLAG);
 
         /* FIXME: Handle AP mode later when we support CWM */
 
@@ -1499,9 +1463,9 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
                                                    oper_cw40, oper_sgi);
                         ath_rc_init(sc, priv_sta, sband, sta, rate_table);
 
-                        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                                  "Operating HT Bandwidth changed to: %d\n",
-                                  sc->hw->conf.channel_type);
+                        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                                "Operating HT Bandwidth changed to: %d\n",
+                                sc->hw->conf.channel_type);
                 }
         }
 }
@@ -1612,13 +1576,11 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
 
         rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
         if (!rate_priv) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to allocate private rc structure\n");
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to allocate private rc structure\n");
                 return NULL;
         }
 
-        rate_priv->tx_triglevel_max = sc->sc_ah->caps.tx_triglevel_max;
-
         return rate_priv;
 }
 
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 2f46a2266ba1..5d984b8acdb1 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -195,7 +195,6 @@ struct ath_rc_stats {
  * @rate_max_phy: phy index for the max rate
  * @per: PER for every valid rate in %
  * @probe_interval: interval for ratectrl to probe for other rates
- * @prev_data_rix: rate idx of last data frame
  * @ht_cap: HT capabilities
  * @neg_rates: Negotatied rates
  * @neg_ht_rates: Negotiated HT rates
@@ -214,22 +213,14 @@ struct ath_rate_priv {
         u32 probe_time;
         u32 per_down_time;
         u32 probe_interval;
-        u32 prev_data_rix;
-        u32 tx_triglevel_max;
         struct ath_rateset neg_rates;
         struct ath_rateset neg_ht_rates;
-        struct ath_rate_softc *asc;
         const struct ath_rate_table *rate_table;
 
         struct dentry *debugfs_rcstats;
         struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
 };
 
-#define ATH_TX_INFO_FRAME_TYPE_INTERNAL (1 << 0)
-#define ATH_TX_INFO_FRAME_TYPE_PAUSE    (1 << 1)
-#define ATH_TX_INFO_XRETRY              (1 << 3)
-#define ATH_TX_INFO_UNDERRUN            (1 << 4)
-
 enum ath9k_internal_frame_type {
         ATH9K_IFT_NOT_INTERNAL,
         ATH9K_IFT_PAUSE,
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index fdc2ec52b42f..b2497b8601e5 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -165,7 +165,7 @@ static void ath_rx_addbuffer_edma(struct ath_softc *sc,
         u32 nbuf = 0;
 
         if (list_empty(&sc->rx.rxbuf)) {
-                ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n");
+                ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
                 return;
         }
 
@@ -269,7 +269,7 @@ static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
                                 dev_kfree_skb_any(skb);
                                 bf->bf_mpdu = NULL;
                                 bf->bf_buf_addr = 0;
-                                ath_print(common, ATH_DBG_FATAL,
+                                ath_err(common,
                                         "dma_mapping_error() on RX init\n");
                                 error = -ENOMEM;
                                 goto rx_init_fail;
@@ -317,7 +317,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
         struct ath_buf *bf;
         int error = 0;
 
-        spin_lock_init(&sc->rx.pcu_lock);
+        spin_lock_init(&sc->sc_pcu_lock);
         sc->sc_flags &= ~SC_OP_RXFLUSH;
         spin_lock_init(&sc->rx.rxbuflock);
 
@@ -327,17 +327,17 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
                 common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
                                 min(common->cachelsz, (u16)64));
 
-                ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
-                                common->cachelsz, common->rx_bufsize);
+                ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
+                        common->cachelsz, common->rx_bufsize);
 
                 /* Initialize rx descriptors */
 
                 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
                                 "rx", nbufs, 1, 0);
                 if (error != 0) {
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "failed to allocate rx descriptors: %d\n",
-                                  error);
+                        ath_err(common,
+                                "failed to allocate rx descriptors: %d\n",
+                                error);
                         goto err;
                 }
 
@@ -358,8 +358,8 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
                                 dev_kfree_skb_any(skb);
                                 bf->bf_mpdu = NULL;
                                 bf->bf_buf_addr = 0;
-                                ath_print(common, ATH_DBG_FATAL,
-                                          "dma_mapping_error() on RX init\n");
+                                ath_err(common,
+                                        "dma_mapping_error() on RX init\n");
                                 error = -ENOMEM;
                                 goto err;
                         }
@@ -528,6 +528,13 @@ bool ath_stoprecv(struct ath_softc *sc)
                 sc->rx.rxlink = NULL;
         spin_unlock_bh(&sc->rx.rxbuflock);
 
+        if (!(ah->ah_flags & AH_UNPLUGGED) &&
+            unlikely(!stopped)) {
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Could not stop RX, we could be "
+                        "confusing the DMA engine when we start RX up\n");
+                ATH_DBG_WARN_ON_ONCE(!stopped);
+        }
         return stopped;
 }
 
@@ -588,9 +595,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
 
         if (sc->ps_flags & PS_BEACON_SYNC) {
                 sc->ps_flags &= ~PS_BEACON_SYNC;
-                ath_print(common, ATH_DBG_PS,
-                          "Reconfigure Beacon timers based on "
-                          "timestamp from the AP\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "Reconfigure Beacon timers based on timestamp from the AP\n");
                 ath_beacon_config(sc, NULL);
         }
 
@@ -602,8 +608,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                  * a backup trigger for returning into NETWORK SLEEP state,
                  * so we are waiting for it as well.
                  */
-                ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating "
-                          "buffered broadcast/multicast frame(s)\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
                 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
                 return;
         }
@@ -615,8 +621,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
                  * been delivered.
                  */
                 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
-                ath_print(common, ATH_DBG_PS,
-                          "PS wait for CAB frames timed out\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "PS wait for CAB frames timed out\n");
         }
 }
 
@@ -641,15 +647,14 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
                  * point.
                  */
                 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
-                ath_print(common, ATH_DBG_PS,
-                          "All PS CAB frames received, back to sleep\n");
+                ath_dbg(common, ATH_DBG_PS,
+                        "All PS CAB frames received, back to sleep\n");
         } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
                    !is_multicast_ether_addr(hdr->addr1) &&
                    !ieee80211_has_morefrags(hdr->frame_control)) {
                 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
-                ath_print(common, ATH_DBG_PS,
-                          "Going back to sleep after having received "
-                          "PS-Poll data (0x%lx)\n",
+                ath_dbg(common, ATH_DBG_PS,
+                        "Going back to sleep after having received PS-Poll data (0x%lx)\n",
                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                         PS_WAIT_FOR_CAB |
                                         PS_WAIT_FOR_PSPOLL_DATA |
@@ -658,8 +663,7 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
 }
 
 static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw,
-                                    struct ath_softc *sc, struct sk_buff *skb,
-                                    struct ieee80211_rx_status *rxs)
+                                    struct ath_softc *sc, struct sk_buff *skb)
 {
         struct ieee80211_hdr *hdr;
 
@@ -958,8 +962,9 @@ static int ath9k_process_rate(struct ath_common *common,
          * No valid hardware bitrate found -- we should not get here
          * because hardware has already validated this frame as OK.
          */
-        ath_print(common, ATH_DBG_XMIT, "unsupported hw bitrate detected "
-                  "0x%02x using 1 Mbit\n", rx_stats->rs_rate);
+        ath_dbg(common, ATH_DBG_XMIT,
+                "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
+                rx_stats->rs_rate);
 
         return -EINVAL;
 }
@@ -969,36 +974,23 @@ static void ath9k_process_rssi(struct ath_common *common,
                                struct ieee80211_hdr *hdr,
                                struct ath_rx_status *rx_stats)
 {
+        struct ath_wiphy *aphy = hw->priv;
         struct ath_hw *ah = common->ah;
-        struct ieee80211_sta *sta;
-        struct ath_node *an;
-        int last_rssi = ATH_RSSI_DUMMY_MARKER;
+        int last_rssi;
         __le16 fc;
 
+        if (ah->opmode != NL80211_IFTYPE_STATION)
+                return;
+
         fc = hdr->frame_control;
+        if (!ieee80211_is_beacon(fc) ||
+            compare_ether_addr(hdr->addr3, common->curbssid))
+                return;
 
-        rcu_read_lock();
-        /*
-         * XXX: use ieee80211_find_sta! This requires quite a bit of work
-         * under the current ath9k virtual wiphy implementation as we have
-         * no way of tying a vif to wiphy. Typically vifs are attached to
-         * at least one sdata of a wiphy on mac80211 but with ath9k virtual
-         * wiphy you'd have to iterate over every wiphy and each sdata.
-         */
-        if (is_multicast_ether_addr(hdr->addr1))
-                sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, NULL);
-        else
-                sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr2, hdr->addr1);
-
-        if (sta) {
-                an = (struct ath_node *) sta->drv_priv;
-                if (rx_stats->rs_rssi != ATH9K_RSSI_BAD &&
-                   !rx_stats->rs_moreaggr)
-                        ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi);
-                last_rssi = an->last_rssi;
-        }
-        rcu_read_unlock();
+        if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
+                ATH_RSSI_LPF(aphy->last_rssi, rx_stats->rs_rssi);
 
+        last_rssi = aphy->last_rssi;
         if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
                 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
                                               ATH_RSSI_EP_MULTIPLIER);
@@ -1006,8 +998,7 @@ static void ath9k_process_rssi(struct ath_common *common,
                 rx_stats->rs_rssi = 0;
 
         /* Update Beacon RSSI, this is used by ANI. */
-        if (ieee80211_is_beacon(fc))
-                ah->stats.avgbrssi = rx_stats->rs_rssi;
+        ah->stats.avgbrssi = rx_stats->rs_rssi;
 }
 
 /*
@@ -1637,7 +1628,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         /*
-         * The hw can techncically differ from common->hw when using ath9k
+         * The hw can technically differ from common->hw when using ath9k
          * virtual wiphy so to account for that we iterate over the active
          * wiphys and find the appropriate wiphy and therefore hw.
          */
@@ -1744,9 +1735,8 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                         dev_kfree_skb_any(requeue_skb);
                         bf->bf_mpdu = NULL;
                         bf->bf_buf_addr = 0;
-                        ath_print(common, ATH_DBG_FATAL,
-                                  "dma_mapping_error() on RX\n");
-                        ath_rx_send_to_mac80211(hw, sc, skb, rxs);
+                        ath_err(common, "dma_mapping_error() on RX\n");
+                        ath_rx_send_to_mac80211(hw, sc, skb);
                         break;
                 }
 
@@ -1762,17 +1752,18 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
                 }
 
                 spin_lock_irqsave(&sc->sc_pm_lock, flags);
-                if (unlikely(ath9k_check_auto_sleep(sc) ||
-                             (sc->ps_flags & (PS_WAIT_FOR_BEACON |
+
+                if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                               PS_WAIT_FOR_CAB |
-                                              PS_WAIT_FOR_PSPOLL_DATA))))
+                                              PS_WAIT_FOR_PSPOLL_DATA)) ||
+                                        unlikely(ath9k_check_auto_sleep(sc)))
                         ath_rx_ps(sc, skb);
                 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
 
                 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
                         ath_ant_comb_scan(sc, &rs);
 
-                ath_rx_send_to_mac80211(hw, sc, skb, rxs);
+                ath_rx_send_to_mac80211(hw, sc, skb);
 
 requeue:
                 if (edma) {
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 2c6a22fbb0f0..4df5659c6c16 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -787,6 +787,8 @@
 #define AR_SREV_REVISION_9271_11        1
 #define AR_SREV_VERSION_9300            0x1c0
 #define AR_SREV_REVISION_9300_20        2 /* 2.0 and 2.1 */
+#define AR_SREV_VERSION_9485            0x240
+#define AR_SREV_REVISION_9485_10        0
 
 #define AR_SREV_5416(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
@@ -859,20 +861,24 @@
          (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \
           ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20)))
 
+#define AR_SREV_9485(_ah) \
+        (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9485))
+#define AR_SREV_9485_10(_ah) \
+        (AR_SREV_9485(_ah) && \
+         ((_ah)->hw_version.macRev == AR_SREV_REVISION_9485_10))
+
 #define AR_SREV_9285E_20(_ah) \
     (AR_SREV_9285_12_OR_LATER(_ah) && \
      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
 
-#define AR_DEVID_7010(_ah) \
-        (((_ah)->hw_version.devid == 0x7010) || \
-         ((_ah)->hw_version.devid == 0x7015) || \
-         ((_ah)->hw_version.devid == 0x9018) || \
-         ((_ah)->hw_version.devid == 0xA704) || \
-         ((_ah)->hw_version.devid == 0x1200))
+enum ath_usb_dev {
+        AR9280_USB = 1, /* AR7010 + AR9280, UB94 */
+        AR9287_USB = 2, /* AR7010 + AR9287, UB95 */
+};
 
-#define AR9287_HTC_DEVID(_ah) \
-        (((_ah)->hw_version.devid == 0x7015) || \
-         ((_ah)->hw_version.devid == 0x1200))
+#define AR_DEVID_7010(_ah) \
+        (((_ah)->hw_version.usbdev == AR9280_USB) || \
+         ((_ah)->hw_version.usbdev == AR9287_USB))
 
 #define AR_RADIO_SREV_MAJOR                   0xf0
 #define AR_RAD5133_SREV_MAJOR                 0xc0
@@ -1074,6 +1080,9 @@ enum {
 #define AR_INTR_PRIO_ASYNC_MASK   0x40c8
 #define AR_INTR_PRIO_SYNC_MASK    0x40cc
 #define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4
+#define AR_ENT_OTP                0x40d8
+#define AR_ENT_OTP_CHAIN2_DISABLE               0x00020000
+#define AR_ENT_OTP_MPSD         0x00800000
 
 #define AR_RTC_9300_PLL_DIV          0x000003ff
 #define AR_RTC_9300_PLL_DIV_S        0
@@ -1111,6 +1120,8 @@ enum {
 #define AR_RTC_PLL_CONTROL \
         ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
 
+#define AR_RTC_PLL_CONTROL2     0x703c
+
 #define AR_RTC_PLL_DIV          0x0000001f
 #define AR_RTC_PLL_DIV_S        0
 #define AR_RTC_PLL_DIV2         0x00000020
@@ -1574,6 +1585,7 @@ enum {
 #define AR_PCU_TBTT_PROTECT        0x00200000
 #define AR_PCU_CLEAR_VMF           0x01000000
 #define AR_PCU_CLEAR_BA_VALID      0x04000000
+#define AR_PCU_ALWAYS_PERFORM_KEYSEARCH 0x10000000
 
 #define AR_PCU_BT_ANT_PREVENT_RX   0x00100000
 #define AR_PCU_BT_ANT_PREVENT_RX_S 20
diff --git a/drivers/net/wireless/ath/ath9k/virtual.c b/drivers/net/wireless/ath/ath9k/virtual.c
index ec7cf5ee56bc..2dc7095e56d1 100644
--- a/drivers/net/wireless/ath/ath9k/virtual.c
+++ b/drivers/net/wireless/ath/ath9k/virtual.c
@@ -107,6 +107,7 @@ int ath9k_wiphy_add(struct ath_softc *sc)
         aphy->sc = sc;
         aphy->hw = hw;
         sc->sec_wiphy[i] = aphy;
+        aphy->last_rssi = ATH_RSSI_DUMMY_MARKER;
         spin_unlock_bh(&sc->wiphy_lock);
 
         memcpy(addr, common->macaddr, ETH_ALEN);
@@ -186,7 +187,7 @@ static int ath9k_send_nullfunc(struct ath_wiphy *aphy,
         info->control.rates[1].idx = -1;
 
         memset(&txctl, 0, sizeof(struct ath_tx_control));
-        txctl.txq = &sc->tx.txq[sc->tx.hwq_map[WME_AC_VO]];
+        txctl.txq = sc->tx.txq_map[WME_AC_VO];
         txctl.frame_type = ps ? ATH9K_IFT_PAUSE : ATH9K_IFT_UNPAUSE;
 
         if (ath_tx_start(aphy->hw, skb, &txctl) != 0)
@@ -287,7 +288,6 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
         /* sync hw configuration for hw code */
         common->hw = aphy->hw;
 
-        ath_update_chainmask(sc, sc->chan_is_ht);
         if (ath_set_channel(sc, aphy->hw,
                             &sc->sc_ah->channels[sc->chan_idx]) < 0) {
                 printk(KERN_DEBUG "ath9k: Failed to set channel for new "
@@ -304,13 +304,12 @@ void ath9k_wiphy_chan_work(struct work_struct *work)
  * ath9k version of ieee80211_tx_status() for TX frames that are generated
  * internally in the driver.
  */
-void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
+void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, int ftype)
 {
         struct ath_wiphy *aphy = hw->priv;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
 
-        if ((tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_PAUSE) &&
-            aphy->state == ATH_WIPHY_PAUSING) {
+        if (ftype == ATH9K_IFT_PAUSE && aphy->state == ATH_WIPHY_PAUSING) {
                 if (!(tx_info->flags & IEEE80211_TX_STAT_ACK)) {
                         printk(KERN_DEBUG "ath9k: %s: no ACK for pause "
                                "frame\n", wiphy_name(hw->wiphy));
@@ -656,10 +655,9 @@ void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle)
         struct ath_softc *sc = aphy->sc;
 
         aphy->idle = idle;
-        ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
-                  "Marking %s as %s\n",
-                  wiphy_name(aphy->hw->wiphy),
-                  idle ? "idle" : "not-idle");
+        ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
+                "Marking %s as %sidle\n",
+                wiphy_name(aphy->hw->wiphy), idle ? "" : "not-");
 }
 /* Only bother starting a queue on an active virtual wiphy */
 bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue)
diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c
index 93a8bda09c25..dc862f5e1162 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.c
+++ b/drivers/net/wireless/ath/ath9k/wmi.c
@@ -120,17 +120,27 @@ void ath9k_deinit_wmi(struct ath9k_htc_priv *priv)
         kfree(priv->wmi);
 }
 
-void ath9k_wmi_tasklet(unsigned long data)
+void ath9k_swba_tasklet(unsigned long data)
 {
         struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *)data;
         struct ath_common *common = ath9k_hw_common(priv->ah);
 
-        ath_print(common, ATH_DBG_WMI, "SWBA Event received\n");
+        ath_dbg(common, ATH_DBG_WMI, "SWBA Event received\n");
 
         ath9k_htc_swba(priv, priv->wmi->beacon_pending);
 
 }
 
+void ath9k_fatal_work(struct work_struct *work)
+{
+        struct ath9k_htc_priv *priv = container_of(work, struct ath9k_htc_priv,
+                                                   fatal_work);
+        struct ath_common *common = ath9k_hw_common(priv->ah);
+
+        ath_dbg(common, ATH_DBG_FATAL, "FATAL Event received, resetting device\n");
+        ath9k_htc_reset(priv);
+}
+
 static void ath9k_wmi_rsp_callback(struct wmi *wmi, struct sk_buff *skb)
 {
         skb_pull(skb, sizeof(struct wmi_cmd_hdr));
@@ -163,7 +173,11 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb,
                 switch (cmd_id) {
                 case WMI_SWBA_EVENTID:
                         wmi->beacon_pending = *(u8 *)wmi_event;
-                        tasklet_schedule(&wmi->drv_priv->wmi_tasklet);
+                        tasklet_schedule(&wmi->drv_priv->swba_tasklet);
+                        break;
+                case WMI_FATAL_EVENTID:
+                        ieee80211_queue_work(wmi->drv_priv->hw,
+                                             &wmi->drv_priv->fatal_work);
                         break;
                 case WMI_TXRATE_EVENTID:
 #ifdef CONFIG_ATH9K_HTC_DEBUGFS
@@ -250,7 +264,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
         int time_left, ret = 0;
         unsigned long flags;
 
-        if (wmi->drv_priv->op_flags & OP_UNPLUGGED)
+        if (ah->ah_flags & AH_UNPLUGGED)
                 return 0;
 
         skb = alloc_skb(headroom + cmd_len, GFP_ATOMIC);
@@ -286,9 +300,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
 
         time_left = wait_for_completion_timeout(&wmi->cmd_wait, timeout);
         if (!time_left) {
-                ath_print(common, ATH_DBG_WMI,
-                          "Timeout waiting for WMI command: %s\n",
-                          wmi_cmd_to_name(cmd_id));
+                ath_dbg(common, ATH_DBG_WMI,
+                        "Timeout waiting for WMI command: %s\n",
+                        wmi_cmd_to_name(cmd_id));
                 mutex_unlock(&wmi->op_mutex);
                 return -ETIMEDOUT;
         }
@@ -298,8 +312,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
         return 0;
 
 out:
-        ath_print(common, ATH_DBG_WMI,
-                  "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
+        ath_dbg(common, ATH_DBG_WMI,
+                "WMI failure for: %s\n", wmi_cmd_to_name(cmd_id));
         mutex_unlock(&wmi->op_mutex);
         kfree_skb(skb);
 
diff --git a/drivers/net/wireless/ath/ath9k/wmi.h b/drivers/net/wireless/ath/ath9k/wmi.h
index ac61074af8ac..42084277522d 100644
--- a/drivers/net/wireless/ath/ath9k/wmi.h
+++ b/drivers/net/wireless/ath/ath9k/wmi.h
@@ -117,7 +117,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
                   u8 *cmd_buf, u32 cmd_len,
                   u8 *rsp_buf, u32 rsp_len,
                   u32 timeout);
-void ath9k_wmi_tasklet(unsigned long data);
+void ath9k_swba_tasklet(unsigned long data);
+void ath9k_fatal_work(struct work_struct *work);
 
 #define WMI_CMD(_wmi_cmd)                                               \
         do {                                                            \
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index aff04789f794..332d1feb5c18 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -48,19 +48,17 @@ static u16 bits_per_symbol[][2] = {
 
 #define IS_HT_RATE(_rate)     ((_rate) & 0x80)
 
-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
-                                  struct ath_atx_tid *tid,
-                                  struct list_head *bf_head);
+static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+                               struct ath_atx_tid *tid,
+                               struct list_head *bf_head);
 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
                                 struct ath_txq *txq, struct list_head *bf_q,
                                 struct ath_tx_status *ts, int txok, int sendbar);
 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                              struct list_head *head);
-static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
-static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
-                              struct ath_tx_status *ts, int txok);
+static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
-                             int nbad, int txok, bool update_rc);
+                             int nframes, int nbad, int txok, bool update_rc);
 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
                               int seqno);
 
@@ -124,7 +122,7 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
 
 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
-        struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
+        struct ath_txq *txq = tid->ac->txq;
 
         WARN_ON(!tid->paused);
 
@@ -140,12 +138,21 @@ unlock:
         spin_unlock_bh(&txq->axq_lock);
 }
 
+static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
+{
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        BUILD_BUG_ON(sizeof(struct ath_frame_info) >
+                     sizeof(tx_info->rate_driver_data));
+        return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
+}
+
 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
-        struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
+        struct ath_txq *txq = tid->ac->txq;
         struct ath_buf *bf;
         struct list_head bf_head;
         struct ath_tx_status ts;
+        struct ath_frame_info *fi;
 
         INIT_LIST_HEAD(&bf_head);
 
@@ -156,12 +163,15 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
                 list_move_tail(&bf->list, &bf_head);
 
-                if (bf_isretried(bf)) {
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                spin_unlock_bh(&txq->axq_lock);
+                fi = get_frame_info(bf->bf_mpdu);
+                if (fi->retries) {
+                        ath_tx_update_baw(sc, tid, fi->seqno);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
                 } else {
-                        ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
+                        ath_tx_send_normal(sc, txq, tid, &bf_head);
                 }
+                spin_lock_bh(&txq->axq_lock);
         }
 
         spin_unlock_bh(&txq->axq_lock);
@@ -184,14 +194,11 @@ static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
 }
 
 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
-                             struct ath_buf *bf)
+                             u16 seqno)
 {
         int index, cindex;
 
-        if (bf_isretried(bf))
-                return;
-
-        index  = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
+        index  = ATH_BA_INDEX(tid->seq_start, seqno);
         cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
         __set_bit(cindex, tid->tx_buf);
 
@@ -215,6 +222,7 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
         struct ath_buf *bf;
         struct list_head bf_head;
         struct ath_tx_status ts;
+        struct ath_frame_info *fi;
 
         memset(&ts, 0, sizeof(ts));
         INIT_LIST_HEAD(&bf_head);
@@ -226,8 +234,9 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
                 list_move_tail(&bf->list, &bf_head);
 
-                if (bf_isretried(bf))
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                fi = get_frame_info(bf->bf_mpdu);
+                if (fi->retries)
+                        ath_tx_update_baw(sc, tid, fi->seqno);
 
                 spin_unlock(&txq->axq_lock);
                 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
@@ -239,16 +248,15 @@ static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
 }
 
 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
-                             struct ath_buf *bf)
+                             struct sk_buff *skb)
 {
-        struct sk_buff *skb;
+        struct ath_frame_info *fi = get_frame_info(skb);
         struct ieee80211_hdr *hdr;
 
-        bf->bf_state.bf_type |= BUF_RETRY;
-        bf->bf_retries++;
         TX_STAT_INC(txq->axq_qnum, a_retries);
+        if (fi->retries++ > 0)
+                return;
 
-        skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
         hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
 }
@@ -298,9 +306,41 @@ static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
         return tbf;
 }
 
+static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
+                                struct ath_tx_status *ts, int txok,
+                                int *nframes, int *nbad)
+{
+        struct ath_frame_info *fi;
+        u16 seq_st = 0;
+        u32 ba[WME_BA_BMP_SIZE >> 5];
+        int ba_index;
+        int isaggr = 0;
+
+        *nbad = 0;
+        *nframes = 0;
+
+        isaggr = bf_isaggr(bf);
+        if (isaggr) {
+                seq_st = ts->ts_seqnum;
+                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
+        }
+
+        while (bf) {
+                fi = get_frame_info(bf->bf_mpdu);
+                ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
+
+                (*nframes)++;
+                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
+                        (*nbad)++;
+
+                bf = bf->bf_next;
+        }
+}
+
+
 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                  struct ath_buf *bf, struct list_head *bf_q,
-                                 struct ath_tx_status *ts, int txok)
+                                 struct ath_tx_status *ts, int txok, bool retry)
 {
         struct ath_node *an = NULL;
         struct sk_buff *skb;
@@ -316,7 +356,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
         bool rc_update = true;
         struct ieee80211_tx_rate rates[4];
+        struct ath_frame_info *fi;
         int nframes;
+        u8 tidno;
 
         skb = bf->bf_mpdu;
         hdr = (struct ieee80211_hdr *)skb->data;
@@ -325,7 +367,6 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         hw = bf->aphy->hw;
 
         memcpy(rates, tx_info->control.rates, sizeof(rates));
-        nframes = bf->bf_nframes;
 
         rcu_read_lock();
 
@@ -342,7 +383,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                             !bf->bf_stale || bf_next != NULL)
                                 list_move_tail(&bf->list, &bf_head);
 
-                        ath_tx_rc_status(bf, ts, 1, 0, false);
+                        ath_tx_rc_status(bf, ts, 1, 1, 0, false);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
                                 0, 0);
 
@@ -352,14 +393,15 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         }
 
         an = (struct ath_node *)sta->drv_priv;
-        tid = ATH_AN_2_TID(an, bf->bf_tidno);
+        tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+        tid = ATH_AN_2_TID(an, tidno);
 
         /*
          * The hardware occasionally sends a tx status for the wrong TID.
          * In this case, the BA status cannot be considered valid and all
          * subframes need to be retransmitted
          */
-        if (bf->bf_tidno != ts->tid)
+        if (tidno != ts->tid)
                 txok = false;
 
         isaggr = bf_isaggr(bf);
@@ -385,15 +427,16 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
         INIT_LIST_HEAD(&bf_pending);
         INIT_LIST_HEAD(&bf_head);
 
-        nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
+        ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
         while (bf) {
                 txfail = txpending = 0;
                 bf_next = bf->bf_next;
 
                 skb = bf->bf_mpdu;
                 tx_info = IEEE80211_SKB_CB(skb);
+                fi = get_frame_info(skb);
 
-                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
+                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
                         /* transmit completion, subframe is
                          * acked by block ack */
                         acked_cnt++;
@@ -401,10 +444,9 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                         /* transmit completion */
                         acked_cnt++;
                 } else {
-                        if (!(tid->state & AGGR_CLEANUP) &&
-                            !bf_last->bf_tx_aborted) {
-                                if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
-                                        ath_tx_set_retry(sc, txq, bf);
+                        if (!(tid->state & AGGR_CLEANUP) && retry) {
+                                if (fi->retries < ATH_MAX_SW_RETRIES) {
+                                        ath_tx_set_retry(sc, txq, bf->bf_mpdu);
                                         txpending = 1;
                                 } else {
                                         bf->bf_state.bf_type |= BUF_XRETRY;
@@ -442,16 +484,15 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                          * block-ack window
                          */
                         spin_lock_bh(&txq->axq_lock);
-                        ath_tx_update_baw(sc, tid, bf->bf_seqno);
+                        ath_tx_update_baw(sc, tid, fi->seqno);
                         spin_unlock_bh(&txq->axq_lock);
 
                         if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
                                 memcpy(tx_info->control.rates, rates, sizeof(rates));
-                                bf->bf_nframes = nframes;
-                                ath_tx_rc_status(bf, ts, nbad, txok, true);
+                                ath_tx_rc_status(bf, ts, nframes, nbad, txok, true);
                                 rc_update = false;
                         } else {
-                                ath_tx_rc_status(bf, ts, nbad, txok, false);
+                                ath_tx_rc_status(bf, ts, nframes, nbad, txok, false);
                         }
 
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
@@ -470,14 +511,13 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                                          */
                                         if (!tbf) {
                                                 spin_lock_bh(&txq->axq_lock);
-                                                ath_tx_update_baw(sc, tid,
-                                                                bf->bf_seqno);
+                                                ath_tx_update_baw(sc, tid, fi->seqno);
                                                 spin_unlock_bh(&txq->axq_lock);
 
                                                 bf->bf_state.bf_type |=
                                                         BUF_XRETRY;
-                                                ath_tx_rc_status(bf, ts, nbad,
-                                                                0, false);
+                                                ath_tx_rc_status(bf, ts, nframes,
+                                                                nbad, 0, false);
                                                 ath_tx_complete_buf(sc, bf, txq,
                                                                     &bf_head,
                                                                     ts, 0, 0);
@@ -611,6 +651,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
         u16 minlen;
         u8 flags, rix;
         int width, streams, half_gi, ndelim, mindelim;
+        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
 
         /* Select standard number of delimiters based on frame length alone */
         ndelim = ATH_AGGR_GET_NDELIM(frmlen);
@@ -621,7 +662,7 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
          * TODO - this could be improved to be dependent on the rate.
          *      The hardware can keep up at lower rates, but not higher rates
          */
-        if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
+        if (fi->keyix != ATH9K_TXKEYIX_INVALID)
                 ndelim += ATH_AGGR_ENCRYPTDELIM;
 
         /*
@@ -665,7 +706,8 @@ static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                                              struct ath_txq *txq,
                                              struct ath_atx_tid *tid,
-                                             struct list_head *bf_q)
+                                             struct list_head *bf_q,
+                                             int *aggr_len)
 {
 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
         struct ath_buf *bf, *bf_first, *bf_prev = NULL;
@@ -674,14 +716,16 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                 al_delta, h_baw = tid->baw_size / 2;
         enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
         struct ieee80211_tx_info *tx_info;
+        struct ath_frame_info *fi;
 
         bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
 
         do {
                 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
+                fi = get_frame_info(bf->bf_mpdu);
 
                 /* do not step over block-ack window */
-                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
+                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
                         status = ATH_AGGR_BAW_CLOSED;
                         break;
                 }
@@ -692,7 +736,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                 }
 
                 /* do not exceed aggregation limit */
-                al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
+                al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
 
                 if (nframes &&
                     (aggr_limit < (al + bpad + al_delta + prev_al))) {
@@ -719,14 +763,15 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
                  * Get the delimiters needed to meet the MPDU
                  * density for this node.
                  */
-                ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
+                ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
                 bpad = PADBYTES(al_delta) + (ndelim << 2);
 
                 bf->bf_next = NULL;
                 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
 
                 /* link buffers of this frame to the aggregate */
-                ath_tx_addto_baw(sc, tid, bf);
+                if (!fi->retries)
+                        ath_tx_addto_baw(sc, tid, fi->seqno);
                 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
                 list_move_tail(&bf->list, bf_q);
                 if (bf_prev) {
@@ -738,8 +783,7 @@ static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
 
         } while (!list_empty(&tid->buf_q));
 
-        bf_first->bf_al = al;
-        bf_first->bf_nframes = nframes;
+        *aggr_len = al;
 
         return status;
 #undef PADBYTES
@@ -750,7 +794,9 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
 {
         struct ath_buf *bf;
         enum ATH_AGGR_STATUS status;
+        struct ath_frame_info *fi;
         struct list_head bf_q;
+        int aggr_len;
 
         do {
                 if (list_empty(&tid->buf_q))
@@ -758,7 +804,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
 
                 INIT_LIST_HEAD(&bf_q);
 
-                status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
+                status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
 
                 /*
                  * no frames picked up to be aggregated;
@@ -771,18 +817,20 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
 
                 /* if only one frame, send as non-aggregate */
-                if (bf->bf_nframes == 1) {
+                if (bf == bf->bf_lastbf) {
+                        fi = get_frame_info(bf->bf_mpdu);
+
                         bf->bf_state.bf_type &= ~BUF_AGGR;
                         ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
-                        ath_buf_set_rate(sc, bf);
+                        ath_buf_set_rate(sc, bf, fi->framelen);
                         ath_tx_txqaddbuf(sc, txq, &bf_q);
                         continue;
                 }
 
                 /* setup first desc of aggregate */
                 bf->bf_state.bf_type |= BUF_AGGR;
-                ath_buf_set_rate(sc, bf);
-                ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
+                ath_buf_set_rate(sc, bf, aggr_len);
+                ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
 
                 /* anchor last desc of aggregate */
                 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
@@ -790,7 +838,7 @@ static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 ath_tx_txqaddbuf(sc, txq, &bf_q);
                 TX_STAT_INC(txq->axq_qnum, a_aggr);
 
-        } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
+        } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
                  status != ATH_AGGR_BAW_CLOSED);
 }
 
@@ -817,7 +865,7 @@ void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
         struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
-        struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
+        struct ath_txq *txq = txtid->ac->txq;
 
         if (txtid->state & AGGR_CLEANUP)
                 return;
@@ -888,10 +936,16 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
         struct ath_hw *ah = sc->sc_ah;
         struct ath_common *common = ath9k_hw_common(ah);
         struct ath9k_tx_queue_info qi;
+        static const int subtype_txq_to_hwq[] = {
+                [WME_AC_BE] = ATH_TXQ_AC_BE,
+                [WME_AC_BK] = ATH_TXQ_AC_BK,
+                [WME_AC_VI] = ATH_TXQ_AC_VI,
+                [WME_AC_VO] = ATH_TXQ_AC_VO,
+        };
         int qnum, i;
 
         memset(&qi, 0, sizeof(qi));
-        qi.tqi_subtype = subtype;
+        qi.tqi_subtype = subtype_txq_to_hwq[subtype];
         qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
         qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
         qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
@@ -931,22 +985,21 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
                 return NULL;
         }
         if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "qnum %u out of range, max %u!\n",
-                          qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
+                ath_err(common, "qnum %u out of range, max %zu!\n",
+                        qnum, ARRAY_SIZE(sc->tx.txq));
                 ath9k_hw_releasetxqueue(ah, qnum);
                 return NULL;
         }
         if (!ATH_TXQ_SETUP(sc, qnum)) {
                 struct ath_txq *txq = &sc->tx.txq[qnum];
 
-                txq->axq_class = subtype;
                 txq->axq_qnum = qnum;
                 txq->axq_link = NULL;
                 INIT_LIST_HEAD(&txq->axq_q);
                 INIT_LIST_HEAD(&txq->axq_acq);
                 spin_lock_init(&txq->axq_lock);
                 txq->axq_depth = 0;
+                txq->axq_ampdu_depth = 0;
                 txq->axq_tx_inprogress = false;
                 sc->tx.txqsetup |= 1<<qnum;
 
@@ -985,8 +1038,8 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
         qi.tqi_readyTime = qinfo->tqi_readyTime;
 
         if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "Unable to update hardware queue %u!\n", qnum);
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "Unable to update hardware queue %u!\n", qnum);
                 error = -EIO;
         } else {
                 ath9k_hw_resettxqueue(ah, qnum);
@@ -1016,6 +1069,12 @@ int ath_cabq_update(struct ath_softc *sc)
         return 0;
 }
 
+static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
+{
+    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
+    return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
+}
+
 /*
  * Drain a given TX queue (could be Beacon or Data)
  *
@@ -1062,8 +1121,6 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
 
                 lastbf = bf->bf_lastbf;
-                if (!retry_tx)
-                        lastbf->bf_tx_aborted = true;
 
                 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                         list_cut_position(&bf_head,
@@ -1076,11 +1133,13 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
                 }
 
                 txq->axq_depth--;
-
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
+                                             retry_tx);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
         }
@@ -1101,7 +1160,7 @@ void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
 
                         if (bf_isampdu(bf))
                                 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
-                                                     &ts, 0);
+                                                     &ts, 0, retry_tx);
                         else
                                 ath_tx_complete_buf(sc, bf, txq, &bf_head,
                                                     &ts, 0, 0);
@@ -1143,7 +1202,7 @@ bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
         }
 
         if (npend)
-                ath_print(common, ATH_DBG_FATAL, "Failed to stop TX DMA!\n");
+                ath_err(common, "Failed to stop TX DMA!\n");
 
         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
                 if (ATH_TXQ_SETUP(sc, i))
@@ -1202,24 +1261,6 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
         }
 }
 
-int ath_tx_setup(struct ath_softc *sc, int haltype)
-{
-        struct ath_txq *txq;
-
-        if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "HAL AC %u out of range, max %zu!\n",
-                         haltype, ARRAY_SIZE(sc->tx.hwq_map));
-                return 0;
-        }
-        txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
-        if (txq != NULL) {
-                sc->tx.hwq_map[haltype] = txq->axq_qnum;
-                return 1;
-        } else
-                return 0;
-}
-
 /***********/
 /* TX, DMA */
 /***********/
@@ -1245,8 +1286,8 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
 
         bf = list_first_entry(head, struct ath_buf, list);
 
-        ath_print(common, ATH_DBG_QUEUE,
-                  "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
+        ath_dbg(common, ATH_DBG_QUEUE,
+                "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
 
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
                 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
@@ -1254,47 +1295,45 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
                         return;
                 }
                 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "Initializing tx fifo %d which "
-                                  "is non-empty\n",
-                                  txq->txq_headidx);
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Initializing tx fifo %d which is non-empty\n",
+                                txq->txq_headidx);
                 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
                 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
                 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
                 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-                ath_print(common, ATH_DBG_XMIT,
-                          "TXDP[%u] = %llx (%p)\n",
-                          txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
+                ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
+                        txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
         } else {
                 list_splice_tail_init(head, &txq->axq_q);
 
                 if (txq->axq_link == NULL) {
                         ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
-                        ath_print(common, ATH_DBG_XMIT,
-                                        "TXDP[%u] = %llx (%p)\n",
-                                        txq->axq_qnum, ito64(bf->bf_daddr),
-                                        bf->bf_desc);
+                        ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
+                                txq->axq_qnum, ito64(bf->bf_daddr),
+                                bf->bf_desc);
                 } else {
                         *txq->axq_link = bf->bf_daddr;
-                        ath_print(common, ATH_DBG_XMIT,
-                                        "link[%u] (%p)=%llx (%p)\n",
-                                        txq->axq_qnum, txq->axq_link,
-                                        ito64(bf->bf_daddr), bf->bf_desc);
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "link[%u] (%p)=%llx (%p)\n",
+                                txq->axq_qnum, txq->axq_link,
+                                ito64(bf->bf_daddr), bf->bf_desc);
                 }
                 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
                                        &txq->axq_link);
                 ath9k_hw_txstart(ah, txq->axq_qnum);
         }
         txq->axq_depth++;
+        if (bf_is_ampdu_not_probing(bf))
+                txq->axq_ampdu_depth++;
 }
 
 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
-                              struct list_head *bf_head,
-                              struct ath_tx_control *txctl)
+                              struct ath_buf *bf, struct ath_tx_control *txctl)
 {
-        struct ath_buf *bf;
+        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
+        struct list_head bf_head;
 
-        bf = list_first_entry(bf_head, struct ath_buf, list);
         bf->bf_state.bf_type |= BUF_AMPDU;
         TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
 
@@ -1306,56 +1345,47 @@ static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
          * - h/w queue depth exceeds low water mark
          */
         if (!list_empty(&tid->buf_q) || tid->paused ||
-            !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
-            txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
+            !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
+            txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
                 /*
                  * Add this frame to software queue for scheduling later
                  * for aggregation.
                  */
-                list_move_tail(&bf->list, &tid->buf_q);
+                list_add_tail(&bf->list, &tid->buf_q);
                 ath_tx_queue_tid(txctl->txq, tid);
                 return;
         }
 
+        INIT_LIST_HEAD(&bf_head);
+        list_add(&bf->list, &bf_head);
+
         /* Add sub-frame to BAW */
-        ath_tx_addto_baw(sc, tid, bf);
+        if (!fi->retries)
+                ath_tx_addto_baw(sc, tid, fi->seqno);
 
         /* Queue to h/w without aggregation */
-        bf->bf_nframes = 1;
         bf->bf_lastbf = bf;
-        ath_buf_set_rate(sc, bf);
-        ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
+        ath_buf_set_rate(sc, bf, fi->framelen);
+        ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
 }
 
-static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
-                                  struct ath_atx_tid *tid,
-                                  struct list_head *bf_head)
+static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
+                               struct ath_atx_tid *tid,
+                               struct list_head *bf_head)
 {
+        struct ath_frame_info *fi;
         struct ath_buf *bf;
 
         bf = list_first_entry(bf_head, struct ath_buf, list);
         bf->bf_state.bf_type &= ~BUF_AMPDU;
 
         /* update starting sequence number for subsequent ADDBA request */
-        INCR(tid->seq_start, IEEE80211_SEQ_MAX);
-
-        bf->bf_nframes = 1;
-        bf->bf_lastbf = bf;
-        ath_buf_set_rate(sc, bf);
-        ath_tx_txqaddbuf(sc, txq, bf_head);
-        TX_STAT_INC(txq->axq_qnum, queued);
-}
-
-static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
-                               struct list_head *bf_head)
-{
-        struct ath_buf *bf;
-
-        bf = list_first_entry(bf_head, struct ath_buf, list);
+        if (tid)
+                INCR(tid->seq_start, IEEE80211_SEQ_MAX);
 
         bf->bf_lastbf = bf;
-        bf->bf_nframes = 1;
-        ath_buf_set_rate(sc, bf);
+        fi = get_frame_info(bf->bf_mpdu);
+        ath_buf_set_rate(sc, bf, fi->framelen);
         ath_tx_txqaddbuf(sc, txq, bf_head);
         TX_STAT_INC(txq->axq_qnum, queued);
 }
@@ -1383,40 +1413,52 @@ static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
         return htype;
 }
 
-static void assign_aggr_tid_seqno(struct sk_buff *skb,
-                                  struct ath_buf *bf)
+static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
+                             int framelen)
 {
+        struct ath_wiphy *aphy = hw->priv;
+        struct ath_softc *sc = aphy->sc;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_sta *sta = tx_info->control.sta;
+        struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
         struct ieee80211_hdr *hdr;
+        struct ath_frame_info *fi = get_frame_info(skb);
         struct ath_node *an;
         struct ath_atx_tid *tid;
-        __le16 fc;
-        u8 *qc;
+        enum ath9k_key_type keytype;
+        u16 seqno = 0;
+        u8 tidno;
 
-        if (!tx_info->control.sta)
-                return;
+        keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
 
-        an = (struct ath_node *)tx_info->control.sta->drv_priv;
         hdr = (struct ieee80211_hdr *)skb->data;
-        fc = hdr->frame_control;
+        if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
+                conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
 
-        if (ieee80211_is_data_qos(fc)) {
-                qc = ieee80211_get_qos_ctl(hdr);
-                bf->bf_tidno = qc[0] & 0xf;
+                an = (struct ath_node *) sta->drv_priv;
+                tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
+
+                /*
+                 * Override seqno set by upper layer with the one
+                 * in tx aggregation state.
+                 */
+                tid = ATH_AN_2_TID(an, tidno);
+                seqno = tid->seq_next;
+                hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
+                INCR(tid->seq_next, IEEE80211_SEQ_MAX);
         }
 
-        /*
-         * For HT capable stations, we save tidno for later use.
-         * We also override seqno set by upper layer with the one
-         * in tx aggregation state.
-         */
-        tid = ATH_AN_2_TID(an, bf->bf_tidno);
-        hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
-        bf->bf_seqno = tid->seq_next;
-        INCR(tid->seq_next, IEEE80211_SEQ_MAX);
+        memset(fi, 0, sizeof(*fi));
+        if (hw_key)
+                fi->keyix = hw_key->hw_key_idx;
+        else
+                fi->keyix = ATH9K_TXKEYIX_INVALID;
+        fi->keytype = keytype;
+        fi->framelen = framelen;
+        fi->seqno = seqno;
 }
 
-static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
+static int setup_tx_flags(struct sk_buff *skb)
 {
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         int flags = 0;
@@ -1427,7 +1469,7 @@ static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
         if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
                 flags |= ATH9K_TXDESC_NOACK;
 
-        if (use_ldpc)
+        if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
                 flags |= ATH9K_TXDESC_LDPC;
 
         return flags;
@@ -1439,13 +1481,11 @@ static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
  * width  - 0 for 20 MHz, 1 for 40 MHz
  * half_gi - to use 4us v/s 3.6 us for symbol time
  */
-static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
+static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
                             int width, int half_gi, bool shortPreamble)
 {
         u32 nbits, nsymbits, duration, nsymbols;
-        int streams, pktlen;
-
-        pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
+        int streams;
 
         /* find number of symbols: PLCP + data */
         streams = HT_RC_2_STREAMS(rix);
@@ -1464,7 +1504,19 @@ static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
         return duration;
 }
 
-static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
+u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
+{
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath9k_channel *curchan = ah->curchan;
+        if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
+                        (curchan->channelFlags & CHANNEL_5GHZ) &&
+                        (chainmask == 0x7) && (rate < 0x90))
+                return 0x3;
+        else
+                return chainmask;
+}
+
+static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
 {
         struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath9k_11n_rate_series series[4];
@@ -1504,7 +1556,6 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
 
                 rix = rates[i].idx;
                 series[i].Tries = rates[i].count;
-                series[i].ChSel = common->tx_chainmask;
 
                 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
                     (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
@@ -1527,14 +1578,16 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
                         /* MCS rates */
                         series[i].Rate = rix | 0x80;
-                        series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
+                        series[i].ChSel = ath_txchainmask_reduction(sc,
+                                        common->tx_chainmask, series[i].Rate);
+                        series[i].PktDuration = ath_pkt_duration(sc, rix, len,
                                  is_40, is_sgi, is_sp);
                         if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
                                 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
                         continue;
                 }
 
-                /* legcay rates */
+                /* legacy rates */
                 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
                     !(rate->flags & IEEE80211_RATE_ERP_G))
                         phy = WLAN_RC_PHY_CCK;
@@ -1550,12 +1603,18 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                         is_sp = false;
                 }
 
+                if (bf->bf_state.bfs_paprd)
+                        series[i].ChSel = common->tx_chainmask;
+                else
+                        series[i].ChSel = ath_txchainmask_reduction(sc,
+                                        common->tx_chainmask, series[i].Rate);
+
                 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
-                        phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
+                        phy, rate->bitrate * 100, len, rix, is_sp);
         }
 
         /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
-        if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
+        if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
                 flags &= ~ATH9K_TXDESC_RTSENA;
 
         /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
@@ -1572,67 +1631,29 @@ static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
                 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
 }
 
-static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
-                                struct sk_buff *skb,
-                                struct ath_tx_control *txctl)
+static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
+                                           struct ath_txq *txq,
+                                           struct sk_buff *skb)
 {
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
-        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-        int hdrlen;
-        __le16 fc;
-        int padpos, padsize;
-        bool use_ldpc = false;
+        struct ath_hw *ah = sc->sc_ah;
+        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+        struct ath_frame_info *fi = get_frame_info(skb);
+        struct ath_buf *bf;
+        struct ath_desc *ds;
+        int frm_type;
 
-        tx_info->pad[0] = 0;
-        switch (txctl->frame_type) {
-        case ATH9K_IFT_NOT_INTERNAL:
-                break;
-        case ATH9K_IFT_PAUSE:
-                tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
-                /* fall through */
-        case ATH9K_IFT_UNPAUSE:
-                tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
-                break;
+        bf = ath_tx_get_buffer(sc);
+        if (!bf) {
+                ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
+                return NULL;
         }
-        hdrlen = ieee80211_get_hdrlen_from_skb(skb);
-        fc = hdr->frame_control;
 
         ATH_TXBUF_RESET(bf);
 
         bf->aphy = aphy;
-        bf->bf_frmlen = skb->len + FCS_LEN;
-        /* Remove the padding size from bf_frmlen, if any */
-        padpos = ath9k_cmn_padpos(hdr->frame_control);
-        padsize = padpos & 3;
-        if (padsize && skb->len>padpos+padsize) {
-                bf->bf_frmlen -= padsize;
-        }
-
-        if (!txctl->paprd && conf_is_ht(&hw->conf)) {
-                bf->bf_state.bf_type |= BUF_HT;
-                if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
-                        use_ldpc = true;
-        }
-
-        bf->bf_state.bfs_paprd = txctl->paprd;
-        if (txctl->paprd)
-                bf->bf_state.bfs_paprd_timestamp = jiffies;
-        bf->bf_flags = setup_tx_flags(skb, use_ldpc);
-
-        bf->bf_keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
-        if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
-                bf->bf_frmlen += tx_info->control.hw_key->icv_len;
-                bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
-        } else {
-                bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
-        }
-
-        if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
-            (sc->sc_flags & SC_OP_TXAGGR))
-                assign_aggr_tid_seqno(skb, bf);
-
+        bf->bf_flags = setup_tx_flags(skb);
         bf->bf_mpdu = skb;
 
         bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
@@ -1640,42 +1661,19 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
         if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
                 bf->bf_mpdu = NULL;
                 bf->bf_buf_addr = 0;
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
-                          "dma_mapping_error() on TX\n");
-                return -ENOMEM;
+                ath_err(ath9k_hw_common(sc->sc_ah),
+                        "dma_mapping_error() on TX\n");
+                ath_tx_return_buffer(sc, bf);
+                return NULL;
         }
 
-        bf->bf_tx_aborted = false;
-
-        return 0;
-}
-
-/* FIXME: tx power */
-static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
-                             struct ath_tx_control *txctl)
-{
-        struct sk_buff *skb = bf->bf_mpdu;
-        struct ieee80211_tx_info *tx_info =  IEEE80211_SKB_CB(skb);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
-        struct ath_node *an = NULL;
-        struct list_head bf_head;
-        struct ath_desc *ds;
-        struct ath_atx_tid *tid;
-        struct ath_hw *ah = sc->sc_ah;
-        int frm_type;
-        __le16 fc;
-
         frm_type = get_hw_packet_type(skb);
-        fc = hdr->frame_control;
-
-        INIT_LIST_HEAD(&bf_head);
-        list_add_tail(&bf->list, &bf_head);
 
         ds = bf->bf_desc;
         ath9k_hw_set_desc_link(ah, ds, 0);
 
-        ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
-                               bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
+        ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
+                               fi->keyix, fi->keytype, bf->bf_flags);
 
         ath9k_hw_filltxdesc(ah, ds,
                             skb->len,   /* segment length */
@@ -1683,42 +1681,53 @@ static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
                             true,       /* last segment */
                             ds,         /* first descriptor */
                             bf->bf_buf_addr,
-                            txctl->txq->axq_qnum);
+                            txq->axq_qnum);
+
+
+        return bf;
+}
 
-        if (bf->bf_state.bfs_paprd)
-                ar9003_hw_set_paprd_txdesc(ah, ds, bf->bf_state.bfs_paprd);
+/* FIXME: tx power */
+static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
+                             struct ath_tx_control *txctl)
+{
+        struct sk_buff *skb = bf->bf_mpdu;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+        struct list_head bf_head;
+        struct ath_atx_tid *tid = NULL;
+        u8 tidno;
 
         spin_lock_bh(&txctl->txq->axq_lock);
 
-        if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
-            tx_info->control.sta) {
-                an = (struct ath_node *)tx_info->control.sta->drv_priv;
-                tid = ATH_AN_2_TID(an, bf->bf_tidno);
+        if (ieee80211_is_data_qos(hdr->frame_control) && txctl->an) {
+                tidno = ieee80211_get_qos_ctl(hdr)[0] &
+                        IEEE80211_QOS_CTL_TID_MASK;
+                tid = ATH_AN_2_TID(txctl->an, tidno);
 
-                if (!ieee80211_is_data_qos(fc)) {
-                        ath_tx_send_normal(sc, txctl->txq, &bf_head);
-                        goto tx_done;
-                }
+                WARN_ON(tid->ac->txq != txctl->txq);
+        }
 
-                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
-                        /*
-                         * Try aggregation if it's a unicast data frame
-                         * and the destination is HT capable.
-                         */
-                        ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
-                } else {
-                        /*
-                         * Send this frame as regular when ADDBA
-                         * exchange is neither complete nor pending.
-                         */
-                        ath_tx_send_ht_normal(sc, txctl->txq,
-                                              tid, &bf_head);
-                }
+        if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
+                /*
+                 * Try aggregation if it's a unicast data frame
+                 * and the destination is HT capable.
+                 */
+                ath_tx_send_ampdu(sc, tid, bf, txctl);
         } else {
-                ath_tx_send_normal(sc, txctl->txq, &bf_head);
+                INIT_LIST_HEAD(&bf_head);
+                list_add_tail(&bf->list, &bf_head);
+
+                bf->bf_state.bfs_ftype = txctl->frame_type;
+                bf->bf_state.bfs_paprd = txctl->paprd;
+
+                if (bf->bf_state.bfs_paprd)
+                        ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
+                                                   bf->bf_state.bfs_paprd);
+
+                ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
         }
 
-tx_done:
         spin_unlock_bh(&txctl->txq->axq_lock);
 }
 
@@ -1726,66 +1735,23 @@ tx_done:
 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
                  struct ath_tx_control *txctl)
 {
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_sta *sta = info->control.sta;
         struct ath_wiphy *aphy = hw->priv;
         struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
         struct ath_txq *txq = txctl->txq;
         struct ath_buf *bf;
-        int q, r;
-
-        bf = ath_tx_get_buffer(sc);
-        if (!bf) {
-                ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
-                return -1;
-        }
-
-        r = ath_tx_setup_buffer(hw, bf, skb, txctl);
-        if (unlikely(r)) {
-                ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
-
-                /* upon ath_tx_processq() this TX queue will be resumed, we
-                 * guarantee this will happen by knowing beforehand that
-                 * we will at least have to run TX completionon one buffer
-                 * on the queue */
-                spin_lock_bh(&txq->axq_lock);
-                if (!txq->stopped && txq->axq_depth > 1) {
-                        ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-                        txq->stopped = 1;
-                }
-                spin_unlock_bh(&txq->axq_lock);
-
-                ath_tx_return_buffer(sc, bf);
-
-                return r;
-        }
-
-        q = skb_get_queue_mapping(skb);
-        if (q >= 4)
-                q = 0;
-
-        spin_lock_bh(&txq->axq_lock);
-        if (++sc->tx.pending_frames[q] > ATH_MAX_QDEPTH && !txq->stopped) {
-                ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
-                txq->stopped = 1;
-        }
-        spin_unlock_bh(&txq->axq_lock);
-
-        ath_tx_start_dma(sc, bf, txctl);
-
-        return 0;
-}
-
-void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
-{
-        struct ath_wiphy *aphy = hw->priv;
-        struct ath_softc *sc = aphy->sc;
-        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
         int padpos, padsize;
-        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
-        struct ath_tx_control txctl;
+        int frmlen = skb->len + FCS_LEN;
+        int q;
+
+        /* NOTE:  sta can be NULL according to net/mac80211.h */
+        if (sta)
+                txctl->an = (struct ath_node *)sta->drv_priv;
 
-        memset(&txctl, 0, sizeof(struct ath_tx_control));
+        if (info->control.hw_key)
+                frmlen += info->control.hw_key->icv_len;
 
         /*
          * As a temporary workaround, assign seq# here; this will likely need
@@ -1802,30 +1768,37 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
         /* Add the padding after the header if this is not already done */
         padpos = ath9k_cmn_padpos(hdr->frame_control);
         padsize = padpos & 3;
-        if (padsize && skb->len>padpos) {
-                if (skb_headroom(skb) < padsize) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "TX CABQ padding failed\n");
-                        dev_kfree_skb_any(skb);
-                        return;
-                }
+        if (padsize && skb->len > padpos) {
+                if (skb_headroom(skb) < padsize)
+                        return -ENOMEM;
+
                 skb_push(skb, padsize);
                 memmove(skb->data, skb->data + padsize, padpos);
         }
 
-        txctl.txq = sc->beacon.cabq;
+        setup_frame_info(hw, skb, frmlen);
 
-        ath_print(common, ATH_DBG_XMIT,
-                  "transmitting CABQ packet, skb: %p\n", skb);
+        /*
+         * At this point, the vif, hw_key and sta pointers in the tx control
+         * info are no longer valid (overwritten by the ath_frame_info data.
+         */
+
+        bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
+        if (unlikely(!bf))
+                return -ENOMEM;
 
-        if (ath_tx_start(hw, skb, &txctl) != 0) {
-                ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
-                goto exit;
+        q = skb_get_queue_mapping(skb);
+        spin_lock_bh(&txq->axq_lock);
+        if (txq == sc->tx.txq_map[q] &&
+            ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
+                ath_mac80211_stop_queue(sc, q);
+                txq->stopped = 1;
         }
+        spin_unlock_bh(&txq->axq_lock);
 
-        return;
-exit:
-        dev_kfree_skb_any(skb);
+        ath_tx_start_dma(sc, bf, txctl);
+
+        return 0;
 }
 
 /*****************/
@@ -1833,7 +1806,8 @@ exit:
 /*****************/
 
 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
-                            struct ath_wiphy *aphy, int tx_flags)
+                            struct ath_wiphy *aphy, int tx_flags, int ftype,
+                            struct ath_txq *txq)
 {
         struct ieee80211_hw *hw = sc->hw;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -1841,7 +1815,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
         struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
         int q, padpos, padsize;
 
-        ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
+        ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
 
         if (aphy)
                 hw = aphy->hw;
@@ -1867,24 +1841,24 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
 
         if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
                 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
-                ath_print(common, ATH_DBG_PS,
-                          "Going back to sleep after having "
-                          "received TX status (0x%lx)\n",
+                ath_dbg(common, ATH_DBG_PS,
+                        "Going back to sleep after having received TX status (0x%lx)\n",
                         sc->ps_flags & (PS_WAIT_FOR_BEACON |
                                         PS_WAIT_FOR_CAB |
                                         PS_WAIT_FOR_PSPOLL_DATA |
                                         PS_WAIT_FOR_TX_ACK));
         }
 
-        if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
-                ath9k_tx_status(hw, skb);
+        if (unlikely(ftype))
+                ath9k_tx_status(hw, skb, ftype);
         else {
                 q = skb_get_queue_mapping(skb);
-                if (q >= 4)
-                        q = 0;
-
-                if (--sc->tx.pending_frames[q] < 0)
-                        sc->tx.pending_frames[q] = 0;
+                if (txq == sc->tx.txq_map[q]) {
+                        spin_lock_bh(&txq->axq_lock);
+                        if (WARN_ON(--txq->pending_frames < 0))
+                                txq->pending_frames = 0;
+                        spin_unlock_bh(&txq->axq_lock);
+                }
 
                 ieee80211_tx_status(hw, skb);
         }
@@ -1912,15 +1886,14 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
         bf->bf_buf_addr = 0;
 
         if (bf->bf_state.bfs_paprd) {
-                if (time_after(jiffies,
-                               bf->bf_state.bfs_paprd_timestamp +
-                               msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
+                if (!sc->paprd_pending)
                         dev_kfree_skb_any(skb);
                 else
                         complete(&sc->paprd_complete);
         } else {
-                ath_debug_stat_tx(sc, txq, bf, ts);
-                ath_tx_complete(sc, skb, bf->aphy, tx_flags);
+                ath_debug_stat_tx(sc, bf, ts);
+                ath_tx_complete(sc, skb, bf->aphy, tx_flags,
+                                bf->bf_state.bfs_ftype, txq);
         }
         /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
          * accidentally reference it later.
@@ -1935,42 +1908,15 @@ static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
         spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
 }
 
-static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
-                              struct ath_tx_status *ts, int txok)
-{
-        u16 seq_st = 0;
-        u32 ba[WME_BA_BMP_SIZE >> 5];
-        int ba_index;
-        int nbad = 0;
-        int isaggr = 0;
-
-        if (bf->bf_lastbf->bf_tx_aborted)
-                return 0;
-
-        isaggr = bf_isaggr(bf);
-        if (isaggr) {
-                seq_st = ts->ts_seqnum;
-                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
-        }
-
-        while (bf) {
-                ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
-                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
-                        nbad++;
-
-                bf = bf->bf_next;
-        }
-
-        return nbad;
-}
-
 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
-                             int nbad, int txok, bool update_rc)
+                             int nframes, int nbad, int txok, bool update_rc)
 {
         struct sk_buff *skb = bf->bf_mpdu;
         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         struct ieee80211_hw *hw = bf->aphy->hw;
+        struct ath_softc *sc = bf->aphy->sc;
+        struct ath_hw *ah = sc->sc_ah;
         u8 i, tx_rateindex;
 
         if (txok)
@@ -1984,22 +1930,32 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
         if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
                 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
 
-                BUG_ON(nbad > bf->bf_nframes);
+                BUG_ON(nbad > nframes);
 
-                tx_info->status.ampdu_len = bf->bf_nframes;
-                tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
+                tx_info->status.ampdu_len = nframes;
+                tx_info->status.ampdu_ack_len = nframes - nbad;
         }
 
         if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
             (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
-                if (ieee80211_is_data(hdr->frame_control)) {
-                        if (ts->ts_flags &
-                            (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
-                                tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
-                        if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
-                            (ts->ts_status & ATH9K_TXERR_FIFO))
-                                tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
-                }
+                /*
+                 * If an underrun error is seen assume it as an excessive
+                 * retry only if max frame trigger level has been reached
+                 * (2 KB for single stream, and 4 KB for dual stream).
+                 * Adjust the long retry as if the frame was tried
+                 * hw->max_rate_tries times to affect how rate control updates
+                 * PER for the failed rate.
+                 * In case of congestion on the bus penalizing this type of
+                 * underruns should help hardware actually transmit new frames
+                 * successfully by eventually preferring slower rates.
+                 * This itself should also alleviate congestion on the bus.
+                 */
+                if (ieee80211_is_data(hdr->frame_control) &&
+                    (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
+                                     ATH9K_TX_DELIM_UNDERRUN)) &&
+                    ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
+                        tx_info->status.rates[tx_rateindex].count =
+                                hw->max_rate_tries;
         }
 
         for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
@@ -2010,16 +1966,13 @@ static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
         tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
 }
 
-static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
+static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum)
 {
-        int qnum;
-
-        qnum = ath_get_mac80211_qnum(txq->axq_class, sc);
-        if (qnum == -1)
-                return;
+        struct ath_txq *txq;
 
+        txq = sc->tx.txq_map[qnum];
         spin_lock_bh(&txq->axq_lock);
-        if (txq->stopped && sc->tx.pending_frames[qnum] < ATH_MAX_QDEPTH) {
+        if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
                 if (ath_mac80211_start_queue(sc, qnum))
                         txq->stopped = 0;
         }
@@ -2036,10 +1989,11 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
         struct ath_tx_status ts;
         int txok;
         int status;
+        int qnum;
 
-        ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
-                  txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
-                  txq->axq_link);
+        ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
+                txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
+                txq->axq_link);
 
         for (;;) {
                 spin_lock_bh(&txq->axq_lock);
@@ -2096,6 +2050,9 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                 txq->axq_tx_inprogress = false;
                 if (bf_held)
                         list_del(&bf_held->list);
+
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 if (bf_held)
@@ -2108,15 +2065,19 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
                          */
                         if (ts.ts_status & ATH9K_TXERR_XRETRY)
                                 bf->bf_state.bf_type |= BUF_XRETRY;
-                        ath_tx_rc_status(bf, &ts, txok ? 0 : 1, txok, true);
+                        ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true);
                 }
 
+                qnum = skb_get_queue_mapping(bf->bf_mpdu);
+
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
+                                             true);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
 
-                ath_wake_mac80211_queue(sc, txq);
+                if (txq == sc->tx.txq_map[qnum])
+                        ath_wake_mac80211_queue(sc, qnum);
 
                 spin_lock_bh(&txq->axq_lock);
                 if (sc->sc_flags & SC_OP_TXAGGR)
@@ -2150,8 +2111,8 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
                 }
 
         if (needreset) {
-                ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
-                          "tx hung, resetting the chip\n");
+                ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
+                        "tx hung, resetting the chip\n");
                 ath9k_ps_wakeup(sc);
                 ath_reset(sc, true);
                 ath9k_ps_restore(sc);
@@ -2186,14 +2147,15 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
         struct list_head bf_head;
         int status;
         int txok;
+        int qnum;
 
         for (;;) {
                 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
                 if (status == -EINPROGRESS)
                         break;
                 if (status == -EIO) {
-                        ath_print(common, ATH_DBG_XMIT,
-                                  "Error processing tx status\n");
+                        ath_dbg(common, ATH_DBG_XMIT,
+                                "Error processing tx status\n");
                         break;
                 }
 
@@ -2219,6 +2181,8 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
                 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
                 txq->axq_depth--;
                 txq->axq_tx_inprogress = false;
+                if (bf_is_ampdu_not_probing(bf))
+                        txq->axq_ampdu_depth--;
                 spin_unlock_bh(&txq->axq_lock);
 
                 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
@@ -2226,16 +2190,20 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
                 if (!bf_isampdu(bf)) {
                         if (txs.ts_status & ATH9K_TXERR_XRETRY)
                                 bf->bf_state.bf_type |= BUF_XRETRY;
-                        ath_tx_rc_status(bf, &txs, txok ? 0 : 1, txok, true);
+                        ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true);
                 }
 
+                qnum = skb_get_queue_mapping(bf->bf_mpdu);
+
                 if (bf_isampdu(bf))
-                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
+                        ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
+                                             txok, true);
                 else
                         ath_tx_complete_buf(sc, bf, txq, &bf_head,
                                             &txs, txok, 0);
 
-                ath_wake_mac80211_queue(sc, txq);
+                if (txq == sc->tx.txq_map[qnum])
+                        ath_wake_mac80211_queue(sc, qnum);
 
                 spin_lock_bh(&txq->axq_lock);
                 if (!list_empty(&txq->txq_fifo_pending)) {
@@ -2300,16 +2268,16 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
         error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
                                   "tx", nbufs, 1, 1);
         if (error != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to allocate tx descriptors: %d\n", error);
+                ath_err(common,
+                        "Failed to allocate tx descriptors: %d\n", error);
                 goto err;
         }
 
         error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
                                   "beacon", ATH_BCBUF, 1, 1);
         if (error != 0) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "Failed to allocate beacon descriptors: %d\n", error);
+                ath_err(common,
+                        "Failed to allocate beacon descriptors: %d\n", error);
                 goto err;
         }
 
@@ -2367,7 +2335,7 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
         for (acno = 0, ac = &an->ac[acno];
              acno < WME_NUM_AC; acno++, ac++) {
                 ac->sched    = false;
-                ac->qnum = sc->tx.hwq_map[acno];
+                ac->txq = sc->tx.txq_map[acno];
                 INIT_LIST_HEAD(&ac->tid_q);
         }
 }
@@ -2377,17 +2345,13 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
         struct ath_atx_ac *ac;
         struct ath_atx_tid *tid;
         struct ath_txq *txq;
-        int i, tidno;
+        int tidno;
 
         for (tidno = 0, tid = &an->tid[tidno];
              tidno < WME_NUM_TID; tidno++, tid++) {
-                i = tid->ac->qnum;
-
-                if (!ATH_TXQ_SETUP(sc, i))
-                        continue;
 
-                txq = &sc->tx.txq[i];
                 ac = tid->ac;
+                txq = ac->txq;
 
                 spin_lock_bh(&txq->axq_lock);
 
diff --git a/drivers/net/wireless/ath/carl9170/carl9170.h b/drivers/net/wireless/ath/carl9170/carl9170.h
index 6cf0c9ef47aa..d07ff7f2fd92 100644
--- a/drivers/net/wireless/ath/carl9170/carl9170.h
+++ b/drivers/net/wireless/ath/carl9170/carl9170.h
@@ -48,7 +48,7 @@
 #include <linux/usb.h>
 #ifdef CONFIG_CARL9170_LEDS
 #include <linux/leds.h>
-#endif /* CONFIG_CARL170_LEDS */
+#endif /* CONFIG_CARL9170_LEDS */
 #ifdef CONFIG_CARL9170_WPC
 #include <linux/input.h>
 #endif /* CONFIG_CARL9170_WPC */
@@ -215,7 +215,7 @@ enum carl9170_restart_reasons {
         CARL9170_RR_TOO_MANY_FIRMWARE_ERRORS,
         CARL9170_RR_WATCHDOG,
         CARL9170_RR_STUCK_TX,
-        CARL9170_RR_SLOW_SYSTEM,
+        CARL9170_RR_UNRESPONSIVE_DEVICE,
         CARL9170_RR_COMMAND_TIMEOUT,
         CARL9170_RR_TOO_MANY_PHY_ERRORS,
         CARL9170_RR_LOST_RSP,
@@ -287,6 +287,7 @@ struct ar9170 {
 
         /* reset / stuck frames/queue detection */
         struct work_struct restart_work;
+        struct work_struct ping_work;
         unsigned int restart_counter;
         unsigned long queue_stop_timeout[__AR9170_NUM_TXQ];
         unsigned long max_queue_stop_timeout[__AR9170_NUM_TXQ];
diff --git a/drivers/net/wireless/ath/carl9170/cmd.c b/drivers/net/wireless/ath/carl9170/cmd.c
index c21f3364bfec..cdfc94c371b4 100644
--- a/drivers/net/wireless/ath/carl9170/cmd.c
+++ b/drivers/net/wireless/ath/carl9170/cmd.c
@@ -41,7 +41,7 @@
 
 int carl9170_write_reg(struct ar9170 *ar, const u32 reg, const u32 val)
 {
-        __le32 buf[2] = {
+        const __le32 buf[2] = {
                 cpu_to_le32(reg),
                 cpu_to_le32(val),
         };
diff --git a/drivers/net/wireless/ath/carl9170/fwcmd.h b/drivers/net/wireless/ath/carl9170/fwcmd.h
index d552166db505..3680dfc70f46 100644
--- a/drivers/net/wireless/ath/carl9170/fwcmd.h
+++ b/drivers/net/wireless/ath/carl9170/fwcmd.h
@@ -97,13 +97,13 @@ struct carl9170_set_key_cmd {
         __le16          type;
         u8              macAddr[6];
         u32             key[4];
-} __packed;
+} __packed __aligned(4);
 #define CARL9170_SET_KEY_CMD_SIZE               28
 
 struct carl9170_disable_key_cmd {
         __le16          user;
         __le16          padding;
-} __packed;
+} __packed __aligned(4);
 #define CARL9170_DISABLE_KEY_CMD_SIZE           4
 
 struct carl9170_u32_list {
@@ -206,7 +206,7 @@ struct carl9170_cmd {
                 struct carl9170_rx_filter_cmd   rx_filter;
                 u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
         } __packed;
-} __packed;
+} __packed __aligned(4);
 
 #define CARL9170_TX_STATUS_QUEUE        3
 #define CARL9170_TX_STATUS_QUEUE_S      0
@@ -216,6 +216,7 @@ struct carl9170_cmd {
 #define CARL9170_TX_STATUS_TRIES        (7 << CARL9170_TX_STATUS_TRIES_S)
 #define CARL9170_TX_STATUS_SUCCESS      0x80
 
+#ifdef __CARL9170FW__
 /*
  * NOTE:
  * Both structs [carl9170_tx_status and _carl9170_tx_status]
@@ -232,6 +233,8 @@ struct carl9170_tx_status {
         u8 tries:3;
         u8 success:1;
 } __packed;
+#endif /* __CARL9170FW__ */
+
 struct _carl9170_tx_status {
         /*
          * This version should be immune to all alignment bugs.
@@ -272,13 +275,15 @@ struct carl9170_rsp {
                 struct carl9170_rf_init_result  rf_init_res;
                 struct carl9170_u32_list        rreg_res;
                 struct carl9170_u32_list        echo;
+#ifdef __CARL9170FW__
                 struct carl9170_tx_status       tx_status[0];
+#endif /* __CARL9170FW__ */
                 struct _carl9170_tx_status      _tx_status[0];
                 struct carl9170_gpio            gpio;
                 struct carl9170_tsf_rsp         tsf;
                 struct carl9170_psm             psm;
                 u8 data[CARL9170_MAX_CMD_PAYLOAD_LEN];
         } __packed;
-} __packed;
+} __packed __aligned(4);
 
 #endif /* __CARL9170_SHARED_FWCMD_H */
diff --git a/drivers/net/wireless/ath/carl9170/hw.h b/drivers/net/wireless/ath/carl9170/hw.h
index 2f471b3f05af..e85df6edfed3 100644
--- a/drivers/net/wireless/ath/carl9170/hw.h
+++ b/drivers/net/wireless/ath/carl9170/hw.h
@@ -712,7 +712,8 @@ struct ar9170_stream {
         __le16 tag;
 
         u8 payload[0];
-};
+} __packed __aligned(4);
+#define AR9170_STREAM_LEN                               4
 
 #define AR9170_MAX_ACKTABLE_ENTRIES                     8
 #define AR9170_MAX_VIRTUAL_MAC                          7
@@ -736,4 +737,8 @@ struct ar9170_stream {
 
 #define MOD_VAL(reg, value, newvalue)                                   \
         (((value) & ~reg) | (((newvalue) << reg##_S) & reg))
+
+#define GET_VAL(reg, value)                                             \
+        (((value) & reg) >> reg##_S)
+
 #endif  /* __CARL9170_SHARED_HW_H */
diff --git a/drivers/net/wireless/ath/carl9170/mac.c b/drivers/net/wireless/ath/carl9170/mac.c
index 2305bc27151c..385cf508479b 100644
--- a/drivers/net/wireless/ath/carl9170/mac.c
+++ b/drivers/net/wireless/ath/carl9170/mac.c
@@ -205,8 +205,8 @@ int carl9170_init_mac(struct ar9170 *ar)
         carl9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
 
         /* Aggregation MAX number and timeout */
-        carl9170_regwrite(AR9170_MAC_REG_AMPDU_FACTOR, 0xa);
-        carl9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, 0x140a00);
+        carl9170_regwrite(AR9170_MAC_REG_AMPDU_FACTOR, 0x8000a);
+        carl9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, 0x140a07);
 
         carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
                           AR9170_MAC_FTF_DEFAULTS);
@@ -457,8 +457,9 @@ int carl9170_set_beacon_timers(struct ar9170 *ar)
 
 int carl9170_update_beacon(struct ar9170 *ar, const bool submit)
 {
-        struct sk_buff *skb;
+        struct sk_buff *skb = NULL;
         struct carl9170_vif_info *cvif;
+        struct ieee80211_tx_info *txinfo;
         __le32 *data, *old = NULL;
         u32 word, off, addr, len;
         int i = 0, err = 0;
@@ -487,7 +488,13 @@ found:
 
         if (!skb) {
                 err = -ENOMEM;
-                goto out_unlock;
+                goto err_free;
+        }
+
+        txinfo = IEEE80211_SKB_CB(skb);
+        if (txinfo->control.rates[0].flags & IEEE80211_TX_RC_MCS) {
+                err = -EINVAL;
+                goto err_free;
         }
 
         spin_lock_bh(&ar->beacon_lock);
@@ -504,11 +511,8 @@ found:
                         wiphy_err(ar->hw->wiphy, "beacon does not "
                                   "fit into device memory!\n");
                 }
-
-                spin_unlock_bh(&ar->beacon_lock);
-                dev_kfree_skb_any(skb);
                 err = -EINVAL;
-                goto out_unlock;
+                goto err_unlock;
         }
 
         if (len > AR9170_MAC_BCN_LENGTH_MAX) {
@@ -518,22 +522,22 @@ found:
                                  AR9170_MAC_BCN_LENGTH_MAX, len);
                 }
 
-                spin_unlock_bh(&ar->beacon_lock);
-                dev_kfree_skb_any(skb);
                 err = -EMSGSIZE;
-                goto out_unlock;
+                goto err_unlock;
         }
 
-        carl9170_async_regwrite_begin(ar);
+        i = txinfo->control.rates[0].idx;
+        if (txinfo->band != IEEE80211_BAND_2GHZ)
+                i += 4;
 
-        /* XXX: use skb->cb info */
-        if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
-                carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP,
-                                ((skb->len + FCS_LEN) << (3 + 16)) + 0x0400);
-        } else {
-                carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP,
-                                ((skb->len + FCS_LEN) << 16) + 0x001b);
-        }
+        word = __carl9170_ratetable[i].hw_value & 0xf;
+        if (i < 4)
+                word |= ((skb->len + FCS_LEN) << (3 + 16)) + 0x0400;
+        else
+                word |= ((skb->len + FCS_LEN) << 16) + 0x0010;
+
+        carl9170_async_regwrite_begin(ar);
+        carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP, word);
 
         for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
                 /*
@@ -557,7 +561,7 @@ found:
                 cvif->beacon = skb;
         spin_unlock_bh(&ar->beacon_lock);
         if (err)
-                goto out_unlock;
+                goto err_free;
 
         if (submit) {
                 err = carl9170_bcn_ctrl(ar, cvif->id,
@@ -565,10 +569,18 @@ found:
                                         addr, skb->len + FCS_LEN);
 
                 if (err)
-                        goto out_unlock;
+                        goto err_free;
         }
 out_unlock:
         rcu_read_unlock();
+        return 0;
+
+err_unlock:
+        spin_unlock_bh(&ar->beacon_lock);
+
+err_free:
+        rcu_read_unlock();
+        dev_kfree_skb_any(skb);
         return err;
 }
 
diff --git a/drivers/net/wireless/ath/carl9170/main.c b/drivers/net/wireless/ath/carl9170/main.c
index dc7b30b170d0..870df8c42622 100644
--- a/drivers/net/wireless/ath/carl9170/main.c
+++ b/drivers/net/wireless/ath/carl9170/main.c
@@ -428,6 +428,7 @@ static void carl9170_cancel_worker(struct ar9170 *ar)
         cancel_delayed_work_sync(&ar->led_work);
 #endif /* CONFIG_CARL9170_LEDS */
         cancel_work_sync(&ar->ps_work);
+        cancel_work_sync(&ar->ping_work);
         cancel_work_sync(&ar->ampdu_work);
 }
 
@@ -533,6 +534,21 @@ void carl9170_restart(struct ar9170 *ar, const enum carl9170_restart_reasons r)
          */
 }
 
+static void carl9170_ping_work(struct work_struct *work)
+{
+        struct ar9170 *ar = container_of(work, struct ar9170, ping_work);
+        int err;
+
+        if (!IS_STARTED(ar))
+                return;
+
+        mutex_lock(&ar->mutex);
+        err = carl9170_echo_test(ar, 0xdeadbeef);
+        if (err)
+                carl9170_restart(ar, CARL9170_RR_UNRESPONSIVE_DEVICE);
+        mutex_unlock(&ar->mutex);
+}
+
 static int carl9170_init_interface(struct ar9170 *ar,
                                    struct ieee80211_vif *vif)
 {
@@ -1614,6 +1630,7 @@ void *carl9170_alloc(size_t priv_size)
                 skb_queue_head_init(&ar->tx_pending[i]);
         }
         INIT_WORK(&ar->ps_work, carl9170_ps_work);
+        INIT_WORK(&ar->ping_work, carl9170_ping_work);
         INIT_WORK(&ar->restart_work, carl9170_restart_work);
         INIT_WORK(&ar->ampdu_work, carl9170_ampdu_work);
         INIT_DELAYED_WORK(&ar->tx_janitor, carl9170_tx_janitor);
@@ -1829,7 +1846,7 @@ int carl9170_register(struct ar9170 *ar)
         err = carl9170_led_register(ar);
         if (err)
                 goto err_unreg;
-#endif /* CONFIG_CAR9L170_LEDS */
+#endif /* CONFIG_CARL9170_LEDS */
 
 #ifdef CONFIG_CARL9170_WPC
         err = carl9170_register_wps_button(ar);
diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c
index 89deca37a988..b6b0de600506 100644
--- a/drivers/net/wireless/ath/carl9170/phy.c
+++ b/drivers/net/wireless/ath/carl9170/phy.c
@@ -1029,8 +1029,6 @@ static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
         if (err)
                 return err;
 
-        msleep(20);
-
         return 0;
 }
 
@@ -1554,15 +1552,6 @@ static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
         return carl9170_regwrite_result();
 }
 
-/* TODO: replace this with sign_extend32(noise, 8) */
-static int carl9170_calc_noise_dbm(u32 raw_noise)
-{
-        if (raw_noise & 0x100)
-                return ~0x1ff | raw_noise;
-        else
-                return raw_noise;
-}
-
 int carl9170_get_noisefloor(struct ar9170 *ar)
 {
         static const u32 phy_regs[] = {
@@ -1578,11 +1567,11 @@ int carl9170_get_noisefloor(struct ar9170 *ar)
                 return err;
 
         for (i = 0; i < 2; i++) {
-                ar->noise[i] = carl9170_calc_noise_dbm(
-                        (phy_res[i] >> 19) & 0x1ff);
+                ar->noise[i] = sign_extend32(GET_VAL(
+                        AR9170_PHY_CCA_MIN_PWR, phy_res[i]), 8);
 
-                ar->noise[i + 2] = carl9170_calc_noise_dbm(
-                        (phy_res[i + 2] >> 23) & 0x1ff);
+                ar->noise[i + 2] = sign_extend32(GET_VAL(
+                        AR9170_PHY_EXT_CCA_MIN_PWR, phy_res[i + 2]), 8);
         }
 
         return 0;
@@ -1669,12 +1658,6 @@ int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
                         return err;
 
                 cmd = CARL9170_CMD_RF_INIT;
-
-                msleep(100);
-
-                err = carl9170_echo_test(ar, 0xaabbccdd);
-                if (err)
-                        return err;
         } else {
                 cmd = CARL9170_CMD_FREQUENCY;
         }
@@ -1685,6 +1668,8 @@ int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
 
         err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
                                  0x200);
+        if (err)
+                return err;
 
         err = carl9170_init_rf_bank4_pwr(ar,
                 channel->band == IEEE80211_BAND_5GHZ,
diff --git a/drivers/net/wireless/ath/carl9170/phy.h b/drivers/net/wireless/ath/carl9170/phy.h
index 02c34eb4ebde..024fb42bc787 100644
--- a/drivers/net/wireless/ath/carl9170/phy.h
+++ b/drivers/net/wireless/ath/carl9170/phy.h
@@ -139,8 +139,8 @@
 #define         AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF     0x00020000
 
 #define AR9170_PHY_REG_CCA                      (AR9170_PHY_REG_BASE + 0x0064)
-#define         AR9170_PHY_CCA_MINCCA_PWR               0x0ff80000
-#define         AR9170_PHY_CCA_MINCCA_PWR_S             19
+#define         AR9170_PHY_CCA_MIN_PWR                  0x0ff80000
+#define         AR9170_PHY_CCA_MIN_PWR_S                19
 #define         AR9170_PHY_CCA_THRESH62                 0x0007f000
 #define         AR9170_PHY_CCA_THRESH62_S               12
 
@@ -338,8 +338,8 @@
 #define         AR9170_PHY_EXT_CCA_CYCPWR_THR1_S        9
 #define         AR9170_PHY_EXT_CCA_THRESH62             0x007f0000
 #define         AR9170_PHY_EXT_CCA_THRESH62_S           16
-#define         AR9170_PHY_EXT_MINCCA_PWR               0xff800000
-#define         AR9170_PHY_EXT_MINCCA_PWR_S             23
+#define         AR9170_PHY_EXT_CCA_MIN_PWR              0xff800000
+#define         AR9170_PHY_EXT_CCA_MIN_PWR_S            23
 
 #define AR9170_PHY_REG_SFCORR_EXT               (AR9170_PHY_REG_BASE + 0x01c0)
 #define         AR9170_PHY_SFCORR_EXT_M1_THRESH         0x0000007f
@@ -546,19 +546,19 @@
 #define         AR9170_PHY_FORCE_XPA_CFG_S              0
 
 #define AR9170_PHY_REG_CH1_CCA                  (AR9170_PHY_REG_BASE + 0x1064)
-#define         AR9170_PHY_CH1_MINCCA_PWR               0x0ff80000
-#define         AR9170_PHY_CH1_MINCCA_PWR_S             19
+#define         AR9170_PHY_CH1_CCA_MIN_PWR              0x0ff80000
+#define         AR9170_PHY_CH1_CCA_MIN_PWR_S            19
 
 #define AR9170_PHY_REG_CH2_CCA                  (AR9170_PHY_REG_BASE + 0x2064)
-#define         AR9170_PHY_CH2_MINCCA_PWR               0x0ff80000
-#define         AR9170_PHY_CH2_MINCCA_PWR_S             19
+#define         AR9170_PHY_CH2_CCA_MIN_PWR              0x0ff80000
+#define         AR9170_PHY_CH2_CCA_MIN_PWR_S            19
 
 #define AR9170_PHY_REG_CH1_EXT_CCA              (AR9170_PHY_REG_BASE + 0x11bc)
-#define         AR9170_PHY_CH1_EXT_MINCCA_PWR           0xff800000
-#define         AR9170_PHY_CH1_EXT_MINCCA_PWR_S         23
+#define         AR9170_PHY_CH1_EXT_CCA_MIN_PWR          0xff800000
+#define         AR9170_PHY_CH1_EXT_CCA_MIN_PWR_S        23
 
 #define AR9170_PHY_REG_CH2_EXT_CCA              (AR9170_PHY_REG_BASE + 0x21bc)
-#define         AR9170_PHY_CH2_EXT_MINCCA_PWR           0xff800000
-#define         AR9170_PHY_CH2_EXT_MINCCA_PWR_S         23
+#define         AR9170_PHY_CH2_EXT_CCA_MIN_PWR          0xff800000
+#define         AR9170_PHY_CH2_EXT_CCA_MIN_PWR_S        23
 
 #endif  /* __CARL9170_SHARED_PHY_H */
diff --git a/drivers/net/wireless/ath/carl9170/tx.c b/drivers/net/wireless/ath/carl9170/tx.c
index 7e6506a77bbb..6cc58e052d10 100644
--- a/drivers/net/wireless/ath/carl9170/tx.c
+++ b/drivers/net/wireless/ath/carl9170/tx.c
@@ -242,9 +242,11 @@ static void carl9170_tx_release(struct kref *ref)
                         ar->tx_ampdu_schedule = true;
 
                 if (txinfo->flags & IEEE80211_TX_STAT_AMPDU) {
-                        txinfo->status.ampdu_len = txinfo->pad[0];
-                        txinfo->status.ampdu_ack_len = txinfo->pad[1];
-                        txinfo->pad[0] = txinfo->pad[1] = 0;
+                        struct _carl9170_tx_superframe *super;
+
+                        super = (void *)skb->data;
+                        txinfo->status.ampdu_len = super->s.rix;
+                        txinfo->status.ampdu_ack_len = super->s.cnt;
                 } else if (txinfo->flags & IEEE80211_TX_STAT_ACK) {
                         /*
                          * drop redundant tx_status reports:
@@ -337,7 +339,8 @@ static void carl9170_tx_status_process_ampdu(struct ar9170 *ar,
         u8 tid;
 
         if (!(txinfo->flags & IEEE80211_TX_CTL_AMPDU) ||
-            txinfo->flags & IEEE80211_TX_CTL_INJECTED)
+            txinfo->flags & IEEE80211_TX_CTL_INJECTED ||
+           (!(super->f.mac_control & cpu_to_le16(AR9170_TX_MAC_AGGR))))
                 return;
 
         tx_info = IEEE80211_SKB_CB(skb);
@@ -389,8 +392,8 @@ static void carl9170_tx_status_process_ampdu(struct ar9170 *ar,
                 sta_info->stats[tid].ampdu_ack_len++;
 
         if (super->f.mac_control & cpu_to_le16(AR9170_TX_MAC_IMM_BA)) {
-                txinfo->pad[0] = sta_info->stats[tid].ampdu_len;
-                txinfo->pad[1] = sta_info->stats[tid].ampdu_ack_len;
+                super->s.rix = sta_info->stats[tid].ampdu_len;
+                super->s.cnt = sta_info->stats[tid].ampdu_ack_len;
                 txinfo->flags |= IEEE80211_TX_STAT_AMPDU;
                 sta_info->stats[tid].clear = true;
         }
@@ -524,6 +527,59 @@ next:
         }
 }
 
+static void carl9170_tx_ampdu_timeout(struct ar9170 *ar)
+{
+        struct carl9170_sta_tid *iter;
+        struct sk_buff *skb;
+        struct ieee80211_tx_info *txinfo;
+        struct carl9170_tx_info *arinfo;
+        struct _carl9170_tx_superframe *super;
+        struct ieee80211_sta *sta;
+        struct ieee80211_vif *vif;
+        struct ieee80211_hdr *hdr;
+        unsigned int vif_id;
+
+        rcu_read_lock();
+        list_for_each_entry_rcu(iter, &ar->tx_ampdu_list, list) {
+                if (iter->state < CARL9170_TID_STATE_IDLE)
+                        continue;
+
+                spin_lock_bh(&iter->lock);
+                skb = skb_peek(&iter->queue);
+                if (!skb)
+                        goto unlock;
+
+                txinfo = IEEE80211_SKB_CB(skb);
+                arinfo = (void *)txinfo->rate_driver_data;
+                if (time_is_after_jiffies(arinfo->timeout +
+                    msecs_to_jiffies(CARL9170_QUEUE_TIMEOUT)))
+                        goto unlock;
+
+                super = (void *) skb->data;
+                hdr = (void *) super->frame_data;
+
+                vif_id = (super->s.misc & CARL9170_TX_SUPER_MISC_VIF_ID) >>
+                         CARL9170_TX_SUPER_MISC_VIF_ID_S;
+
+                if (WARN_ON(vif_id >= AR9170_MAX_VIRTUAL_MAC))
+                        goto unlock;
+
+                vif = rcu_dereference(ar->vif_priv[vif_id].vif);
+                if (WARN_ON(!vif))
+                        goto unlock;
+
+                sta = ieee80211_find_sta(vif, hdr->addr1);
+                if (WARN_ON(!sta))
+                        goto unlock;
+
+                ieee80211_stop_tx_ba_session(sta, iter->tid);
+unlock:
+                spin_unlock_bh(&iter->lock);
+
+        }
+        rcu_read_unlock();
+}
+
 void carl9170_tx_janitor(struct work_struct *work)
 {
         struct ar9170 *ar = container_of(work, struct ar9170,
@@ -534,6 +590,7 @@ void carl9170_tx_janitor(struct work_struct *work)
         ar->tx_janitor_last_run = jiffies;
 
         carl9170_check_queue_stop_timeout(ar);
+        carl9170_tx_ampdu_timeout(ar);
 
         if (!atomic_read(&ar->tx_total_queued))
                 return;
@@ -842,10 +899,8 @@ static int carl9170_tx_prepare(struct ar9170 *ar, struct sk_buff *skb)
                 if (unlikely(!sta || !cvif))
                         goto err_out;
 
-                factor = min_t(unsigned int, 1u,
-                         info->control.sta->ht_cap.ampdu_factor);
-
-                density = info->control.sta->ht_cap.ampdu_density;
+                factor = min_t(unsigned int, 1u, sta->ht_cap.ampdu_factor);
+                density = sta->ht_cap.ampdu_density;
 
                 if (density) {
                         /*
@@ -1206,6 +1261,7 @@ static void carl9170_tx(struct ar9170 *ar)
 static bool carl9170_tx_ampdu_queue(struct ar9170 *ar,
         struct ieee80211_sta *sta, struct sk_buff *skb)
 {
+        struct _carl9170_tx_superframe *super = (void *) skb->data;
         struct carl9170_sta_info *sta_info;
         struct carl9170_sta_tid *agg;
         struct sk_buff *iter;
@@ -1274,6 +1330,7 @@ err_unlock:
 
 err_unlock_rcu:
         rcu_read_unlock();
+        super->f.mac_control &= ~cpu_to_le16(AR9170_TX_MAC_AGGR);
         carl9170_tx_status(ar, skb, false);
         ar->tx_dropped++;
         return false;
@@ -1302,9 +1359,6 @@ int carl9170_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
          */
 
         if (info->flags & IEEE80211_TX_CTL_AMPDU) {
-                if (WARN_ON_ONCE(!sta))
-                        goto err_free;
-
                 run = carl9170_tx_ampdu_queue(ar, sta, skb);
                 if (run)
                         carl9170_tx_ampdu(ar);
diff --git a/drivers/net/wireless/ath/carl9170/usb.c b/drivers/net/wireless/ath/carl9170/usb.c
index 7504ed14c725..537732e5964f 100644
--- a/drivers/net/wireless/ath/carl9170/usb.c
+++ b/drivers/net/wireless/ath/carl9170/usb.c
@@ -160,8 +160,7 @@ err_acc:
 
 static void carl9170_usb_tx_data_complete(struct urb *urb)
 {
-        struct ar9170 *ar = (struct ar9170 *)
-              usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
+        struct ar9170 *ar = usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
 
         if (WARN_ON_ONCE(!ar)) {
                 dev_kfree_skb_irq(urb->context);
@@ -433,7 +432,7 @@ static void carl9170_usb_rx_complete(struct urb *urb)
                          * device.
                          */
 
-                        carl9170_restart(ar, CARL9170_RR_SLOW_SYSTEM);
+                        ieee80211_queue_work(ar->hw, &ar->ping_work);
                 }
         } else {
                 /*
@@ -835,7 +834,7 @@ static int carl9170_usb_load_firmware(struct ar9170 *ar)
         if (err)
                 goto err_out;
 
-        /* firmware restarts cmd counter */
+        /* now, start the command response counter */
         ar->cmd_seq = -1;
 
         return 0;
@@ -852,7 +851,12 @@ int carl9170_usb_restart(struct ar9170 *ar)
         if (ar->intf->condition != USB_INTERFACE_BOUND)
                 return 0;
 
-        /* Disable command response sequence counter. */
+        /*
+         * Disable the command response sequence counter check.
+         * We already know that the device/firmware is in a bad state.
+         * So, no extra points are awarded to anyone who reminds the
+         * driver about that.
+         */
         ar->cmd_seq = -2;
 
         err = carl9170_reboot(ar);
@@ -904,6 +908,15 @@ static int carl9170_usb_init_device(struct ar9170 *ar)
 {
         int err;
 
+        /*
+         * The carl9170 firmware let's the driver know when it's
+         * ready for action. But we have to be prepared to gracefully
+         * handle all spurious [flushed] messages after each (re-)boot.
+         * Thus the command response counter remains disabled until it
+         * can be safely synchronized.
+         */
+        ar->cmd_seq = -2;
+
         err = carl9170_usb_send_rx_irq_urb(ar);
         if (err)
                 goto err_out;
@@ -912,14 +925,21 @@ static int carl9170_usb_init_device(struct ar9170 *ar)
         if (err)
                 goto err_unrx;
 
+        err = carl9170_usb_open(ar);
+        if (err)
+                goto err_unrx;
+
         mutex_lock(&ar->mutex);
         err = carl9170_usb_load_firmware(ar);
         mutex_unlock(&ar->mutex);
         if (err)
-                goto err_unrx;
+                goto err_stop;
 
         return 0;
 
+err_stop:
+        carl9170_usb_stop(ar);
+
 err_unrx:
         carl9170_usb_cancel_urbs(ar);
 
@@ -965,10 +985,6 @@ static void carl9170_usb_firmware_finish(struct ar9170 *ar)
         if (err)
                 goto err_freefw;
 
-        err = carl9170_usb_open(ar);
-        if (err)
-                goto err_unrx;
-
         err = carl9170_register(ar);
 
         carl9170_usb_stop(ar);
@@ -1044,7 +1060,6 @@ static int carl9170_usb_probe(struct usb_interface *intf,
         atomic_set(&ar->rx_work_urbs, 0);
         atomic_set(&ar->rx_anch_urbs, 0);
         atomic_set(&ar->rx_pool_urbs, 0);
-        ar->cmd_seq = -2;
 
         usb_get_dev(ar->udev);
 
@@ -1091,10 +1106,6 @@ static int carl9170_usb_suspend(struct usb_interface *intf,
 
         carl9170_usb_cancel_urbs(ar);
 
-        /*
-         * firmware automatically reboots for usb suspend.
-         */
-
         return 0;
 }
 
@@ -1107,12 +1118,20 @@ static int carl9170_usb_resume(struct usb_interface *intf)
                 return -ENODEV;
 
         usb_unpoison_anchored_urbs(&ar->rx_anch);
+        carl9170_set_state(ar, CARL9170_STOPPED);
 
-        err = carl9170_usb_init_device(ar);
-        if (err)
-                goto err_unrx;
+        /*
+         * The USB documentation demands that [for suspend] all traffic
+         * to and from the device has to stop. This would be fine, but
+         * there's a catch: the device[usb phy] does not come back.
+         *
+         * Upon resume the firmware will "kill" itself and the
+         * boot-code sorts out the magic voodoo.
+         * Not very nice, but there's not much what could go wrong.
+         */
+        msleep(1100);
 
-        err = carl9170_usb_open(ar);
+        err = carl9170_usb_init_device(ar);
         if (err)
                 goto err_unrx;
 
@@ -1134,6 +1153,7 @@ static struct usb_driver carl9170_driver = {
 #ifdef CONFIG_PM
         .suspend = carl9170_usb_suspend,
         .resume = carl9170_usb_resume,
+        .reset_resume = carl9170_usb_resume,
 #endif /* CONFIG_PM */
 };
 
diff --git a/drivers/net/wireless/ath/carl9170/version.h b/drivers/net/wireless/ath/carl9170/version.h
index ff53f078a0b5..ee0f84f2a2f6 100644
--- a/drivers/net/wireless/ath/carl9170/version.h
+++ b/drivers/net/wireless/ath/carl9170/version.h
@@ -1,7 +1,7 @@
 #ifndef __CARL9170_SHARED_VERSION_H
 #define __CARL9170_SHARED_VERSION_H
 #define CARL9170FW_VERSION_YEAR 10
-#define CARL9170FW_VERSION_MONTH 9
-#define CARL9170FW_VERSION_DAY 28
-#define CARL9170FW_VERSION_GIT "1.8.8.3"
+#define CARL9170FW_VERSION_MONTH 10
+#define CARL9170FW_VERSION_DAY 29
+#define CARL9170FW_VERSION_GIT "1.9.0"
 #endif /* __CARL9170_SHARED_VERSION_H */
diff --git a/drivers/net/wireless/ath/debug.c b/drivers/net/wireless/ath/debug.c
index dacfb234f491..5367b1086e09 100644
--- a/drivers/net/wireless/ath/debug.c
+++ b/drivers/net/wireless/ath/debug.c
@@ -15,21 +15,6 @@
  */
 
 #include "ath.h"
-#include "debug.h"
-
-void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
-{
-        va_list args;
-
-        if (likely(!(common->debug_mask & dbg_mask)))
-                return;
-
-        va_start(args, fmt);
-        printk(KERN_DEBUG "ath: ");
-        vprintk(fmt, args);
-        va_end(args);
-}
-EXPORT_SYMBOL(ath_print);
 
 const char *ath_opmode_to_string(enum nl80211_iftype opmode)
 {
diff --git a/drivers/net/wireless/ath/debug.h b/drivers/net/wireless/ath/debug.h
deleted file mode 100644
index 64e4af2c2887..000000000000
--- a/drivers/net/wireless/ath/debug.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2008-2009 Atheros Communications Inc.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef ATH_DEBUG_H
-#define ATH_DEBUG_H
-
-#include "ath.h"
-
-/**
- * enum ath_debug_level - atheros wireless debug level
- *
- * @ATH_DBG_RESET: reset processing
- * @ATH_DBG_QUEUE: hardware queue management
- * @ATH_DBG_EEPROM: eeprom processing
- * @ATH_DBG_CALIBRATE: periodic calibration
- * @ATH_DBG_INTERRUPT: interrupt processing
- * @ATH_DBG_REGULATORY: regulatory processing
- * @ATH_DBG_ANI: adaptive noise immunitive processing
- * @ATH_DBG_XMIT: basic xmit operation
- * @ATH_DBG_BEACON: beacon handling
- * @ATH_DBG_CONFIG: configuration of the hardware
- * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
- * @ATH_DBG_PS: power save processing
- * @ATH_DBG_HWTIMER: hardware timer handling
- * @ATH_DBG_BTCOEX: bluetooth coexistance
- * @ATH_DBG_BSTUCK: stuck beacons
- * @ATH_DBG_ANY: enable all debugging
- *
- * The debug level is used to control the amount and type of debugging output
- * we want to see. Each driver has its own method for enabling debugging and
- * modifying debug level states -- but this is typically done through a
- * module parameter 'debug' along with a respective 'debug' debugfs file
- * entry.
- */
-enum ATH_DEBUG {
-        ATH_DBG_RESET           = 0x00000001,
-        ATH_DBG_QUEUE           = 0x00000002,
-        ATH_DBG_EEPROM          = 0x00000004,
-        ATH_DBG_CALIBRATE       = 0x00000008,
-        ATH_DBG_INTERRUPT       = 0x00000010,
-        ATH_DBG_REGULATORY      = 0x00000020,
-        ATH_DBG_ANI             = 0x00000040,
-        ATH_DBG_XMIT            = 0x00000080,
-        ATH_DBG_BEACON          = 0x00000100,
-        ATH_DBG_CONFIG          = 0x00000200,
-        ATH_DBG_FATAL           = 0x00000400,
-        ATH_DBG_PS              = 0x00000800,
-        ATH_DBG_HWTIMER         = 0x00001000,
-        ATH_DBG_BTCOEX          = 0x00002000,
-        ATH_DBG_WMI             = 0x00004000,
-        ATH_DBG_BSTUCK          = 0x00008000,
-        ATH_DBG_ANY             = 0xffffffff
-};
-
-#define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
-
-#ifdef CONFIG_ATH_DEBUG
-void ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
-        __attribute__ ((format (printf, 3, 4)));
-#else
-static inline void __attribute__ ((format (printf, 3, 4)))
-ath_print(struct ath_common *common, int dbg_mask, const char *fmt, ...)
-{
-}
-#endif /* CONFIG_ATH_DEBUG */
-
-/** Returns string describing opmode, or NULL if unknown mode. */
-#ifdef CONFIG_ATH_DEBUG
-const char *ath_opmode_to_string(enum nl80211_iftype opmode);
-#else
-static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
-{
-        return "UNKNOWN";
-}
-#endif
-
-#endif /* ATH_DEBUG_H */
diff --git a/drivers/net/wireless/ath/key.c b/drivers/net/wireless/ath/key.c
index bd21a4d82085..5d465e5fcf24 100644
--- a/drivers/net/wireless/ath/key.c
+++ b/drivers/net/wireless/ath/key.c
@@ -20,7 +20,6 @@
 
 #include "ath.h"
 #include "reg.h"
-#include "debug.h"
 
 #define REG_READ                        (common->ops->read)
 #define REG_WRITE(_ah, _reg, _val)      (common->ops->write)(_ah, _val, _reg)
@@ -37,8 +36,7 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
         void *ah = common->ah;
 
         if (entry >= common->keymax) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "keychache entry %u out of range\n", entry);
+                ath_err(common, "keycache entry %u out of range\n", entry);
                 return false;
         }
 
@@ -60,6 +58,8 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
+                if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED)
+                        REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
 
         }
 
@@ -67,15 +67,15 @@ bool ath_hw_keyreset(struct ath_common *common, u16 entry)
 }
 EXPORT_SYMBOL(ath_hw_keyreset);
 
-bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac)
+static bool ath_hw_keysetmac(struct ath_common *common,
+                             u16 entry, const u8 *mac)
 {
         u32 macHi, macLo;
         u32 unicast_flag = AR_KEYTABLE_VALID;
         void *ah = common->ah;
 
         if (entry >= common->keymax) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "keychache entry %u out of range\n", entry);
+                ath_err(common, "keycache entry %u out of range\n", entry);
                 return false;
         }
 
@@ -107,17 +107,16 @@ bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac)
         return true;
 }
 
-bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
-                                 const struct ath_keyval *k,
-                                 const u8 *mac)
+static bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
+                                      const struct ath_keyval *k,
+                                      const u8 *mac)
 {
         void *ah = common->ah;
         u32 key0, key1, key2, key3, key4;
         u32 keyType;
 
         if (entry >= common->keymax) {
-                ath_print(common, ATH_DBG_FATAL,
-                          "keycache entry %u out of range\n", entry);
+                ath_err(common, "keycache entry %u out of range\n", entry);
                 return false;
         }
 
@@ -127,8 +126,8 @@ bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
                 break;
         case ATH_CIPHER_AES_CCM:
                 if (!(common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "AES-CCM not supported by this mac rev\n");
+                        ath_dbg(common, ATH_DBG_ANY,
+                                "AES-CCM not supported by this mac rev\n");
                         return false;
                 }
                 keyType = AR_KEYTABLE_TYPE_CCM;
@@ -136,15 +135,15 @@ bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
         case ATH_CIPHER_TKIP:
                 keyType = AR_KEYTABLE_TYPE_TKIP;
                 if (entry + 64 >= common->keymax) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "entry %u inappropriate for TKIP\n", entry);
+                        ath_dbg(common, ATH_DBG_ANY,
+                                "entry %u inappropriate for TKIP\n", entry);
                         return false;
                 }
                 break;
         case ATH_CIPHER_WEP:
                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
-                        ath_print(common, ATH_DBG_ANY,
-                                  "WEP key length %u too small\n", k->kv_len);
+                        ath_dbg(common, ATH_DBG_ANY,
+                                "WEP key length %u too small\n", k->kv_len);
                         return false;
                 }
                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
@@ -158,8 +157,7 @@ bool ath_hw_set_keycache_entry(struct ath_common *common, u16 entry,
                 keyType = AR_KEYTABLE_TYPE_CLR;
                 break;
         default:
-                ath_print(common, ATH_DBG_FATAL,
-                          "cipher %u not supported\n", k->kv_type);
+                ath_err(common, "cipher %u not supported\n", k->kv_type);
                 return false;
         }
 
@@ -340,8 +338,7 @@ static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
         if (!ath_hw_set_keycache_entry(common, keyix, hk, NULL)) {
                 /* TX MIC entry failed. No need to proceed further */
-                ath_print(common, ATH_DBG_FATAL,
-                          "Setting TX MIC Key Failed\n");
+                ath_err(common, "Setting TX MIC Key Failed\n");
                 return 0;
         }
 
diff --git a/drivers/net/wireless/ath/main.c b/drivers/net/wireless/ath/main.c
index 487193f1de1a..c325202fdc5f 100644
--- a/drivers/net/wireless/ath/main.c
+++ b/drivers/net/wireless/ath/main.c
@@ -56,3 +56,23 @@ struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
         return skb;
 }
 EXPORT_SYMBOL(ath_rxbuf_alloc);
+
+int ath_printk(const char *level, struct ath_common *common,
+               const char *fmt, ...)
+{
+        struct va_format vaf;
+        va_list args;
+        int rtn;
+
+        va_start(args, fmt);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        rtn = printk("%sath: %pV", level, &vaf);
+
+        va_end(args);
+
+        return rtn;
+}
+EXPORT_SYMBOL(ath_printk);
diff --git a/drivers/net/wireless/ath/regd.c b/drivers/net/wireless/ath/regd.c
index 3f4244f56ce5..2b14775e6bc6 100644
--- a/drivers/net/wireless/ath/regd.c
+++ b/drivers/net/wireless/ath/regd.c
@@ -342,6 +342,14 @@ int ath_reg_notifier_apply(struct wiphy *wiphy,
         /* We always apply this */
         ath_reg_apply_radar_flags(wiphy);
 
+        /*
+         * This would happen when we have sent a custom regulatory request
+         * a world regulatory domain and the scheduler hasn't yet processed
+         * any pending requests in the queue.
+         */
+        if (!request)
+                return 0;
+
         switch (request->initiator) {
         case NL80211_REGDOM_SET_BY_DRIVER:
         case NL80211_REGDOM_SET_BY_CORE:
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index c8f7090b27d3..46e382ed46aa 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -1161,7 +1161,7 @@ static irqreturn_t service_interrupt(int irq, void *dev_id)
         struct atmel_private *priv = netdev_priv(dev);
         u8 isr;
         int i = -1;
-        static u8 irq_order[] = {
+        static const u8 irq_order[] = {
                 ISR_OUT_OF_RANGE,
                 ISR_RxCOMPLETE,
                 ISR_TxCOMPLETE,
@@ -3771,7 +3771,9 @@ static int probe_atmel_card(struct net_device *dev)
 
         if (rc) {
                 if (dev->dev_addr[0] == 0xFF) {
-                        u8 default_mac[] = {0x00, 0x04, 0x25, 0x00, 0x00, 0x00};
+                        static const u8 default_mac[] = {
+                                0x00, 0x04, 0x25, 0x00, 0x00, 0x00
+                        };
                         printk(KERN_ALERT "%s: *** Invalid MAC address. UPGRADE Firmware ****\n", dev->name);
                         memcpy(dev->dev_addr, default_mac, 6);
                 }
diff --git a/drivers/net/wireless/b43/Kconfig b/drivers/net/wireless/b43/Kconfig
index 0a00d42642cd..47033f6a1c2b 100644
--- a/drivers/net/wireless/b43/Kconfig
+++ b/drivers/net/wireless/b43/Kconfig
@@ -86,15 +86,16 @@ config B43_PIO
         select SSB_BLOCKIO
         default y
 
-config B43_NPHY
-        bool "Pre IEEE 802.11n support (BROKEN)"
-        depends on B43 && EXPERIMENTAL && BROKEN
+config B43_PHY_N
+        bool "Support for 802.11n (N-PHY) devices (EXPERIMENTAL)"
+        depends on B43 && EXPERIMENTAL
         ---help---
-          Support for the IEEE 802.11n draft.
+          Support for the N-PHY.
 
-          THIS IS BROKEN AND DOES NOT WORK YET.
+          This enables support for devices with N-PHY revision up to 2.
 
-          SAY N.
+          Say N if you expect high stability and performance. Saying Y will not
+          affect other devices support and may provide support for basic needs.
 
 config B43_PHY_LP
         bool "Support for low-power (LP-PHY) devices (EXPERIMENTAL)"
diff --git a/drivers/net/wireless/b43/Makefile b/drivers/net/wireless/b43/Makefile
index 69d4af09a6cb..cef334a8c669 100644
--- a/drivers/net/wireless/b43/Makefile
+++ b/drivers/net/wireless/b43/Makefile
@@ -1,12 +1,12 @@
 b43-y                           += main.o
 b43-y                           += tables.o
-b43-$(CONFIG_B43_NPHY)          += tables_nphy.o
-b43-$(CONFIG_B43_NPHY)          += radio_2055.o
-b43-$(CONFIG_B43_NPHY)          += radio_2056.o
+b43-$(CONFIG_B43_PHY_N)         += tables_nphy.o
+b43-$(CONFIG_B43_PHY_N)         += radio_2055.o
+b43-$(CONFIG_B43_PHY_N)         += radio_2056.o
 b43-y                           += phy_common.o
 b43-y                           += phy_g.o
 b43-y                           += phy_a.o
-b43-$(CONFIG_B43_NPHY)          += phy_n.o
+b43-$(CONFIG_B43_PHY_N)         += phy_n.o
 b43-$(CONFIG_B43_PHY_LP)        += phy_lp.o
 b43-$(CONFIG_B43_PHY_LP)        += tables_lpphy.o
 b43-y                           += sysfs.o
diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 72821c456b02..bd4cb75b6ca3 100644
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -153,6 +153,19 @@
 #define B43_BFH_FEM_BT                  0x0040  /* has FEM and switch to share antenna
                                                  * with bluetooth */
 
+/* SPROM boardflags2_lo values */
+#define B43_BFL2_RXBB_INT_REG_DIS       0x0001  /* external RX BB regulator present */
+#define B43_BFL2_APLL_WAR               0x0002  /* alternative A-band PLL settings implemented */
+#define B43_BFL2_TXPWRCTRL_EN           0x0004  /* permits enabling TX Power Control */
+#define B43_BFL2_2X4_DIV                0x0008  /* 2x4 diversity switch */
+#define B43_BFL2_5G_PWRGAIN             0x0010  /* supports 5G band power gain */
+#define B43_BFL2_PCIEWAR_OVR            0x0020  /* overrides ASPM and Clkreq settings */
+#define B43_BFL2_CAESERS_BRD            0x0040  /* is Caesers board (unused) */
+#define B43_BFL2_BTC3WIRE               0x0080  /* used 3-wire bluetooth coexist */
+#define B43_BFL2_SKWRKFEM_BRD           0x0100  /* 4321mcm93 uses Skyworks FEM */
+#define B43_BFL2_SPUR_WAR               0x0200  /* has a workaround for clock-harmonic spurs */
+#define B43_BFL2_GPLL_WAR               0x0400  /* altenative G-band PLL settings implemented */
+
 /* GPIO register offset, in both ChipCommon and PCI core. */
 #define B43_GPIO_CONTROL                0x6c
 
@@ -403,10 +416,10 @@ enum {
 
 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
 #define B43_TMSLOW_GMODE                0x20000000      /* G Mode Enable */
-#define B43_TMSLOW_PHYCLKSPEED          0x00C00000      /* PHY clock speed mask (N-PHY only) */
-#define  B43_TMSLOW_PHYCLKSPEED_40MHZ   0x00000000      /* 40 MHz PHY */
-#define  B43_TMSLOW_PHYCLKSPEED_80MHZ   0x00400000      /* 80 MHz PHY */
-#define  B43_TMSLOW_PHYCLKSPEED_160MHZ  0x00800000      /* 160 MHz PHY */
+#define B43_TMSLOW_PHY_BANDWIDTH        0x00C00000      /* PHY band width and clock speed mask (N-PHY only) */
+#define  B43_TMSLOW_PHY_BANDWIDTH_10MHZ 0x00000000      /* 10 MHz bandwidth, 40 MHz PHY */
+#define  B43_TMSLOW_PHY_BANDWIDTH_20MHZ 0x00400000      /* 20 MHz bandwidth, 80 MHz PHY */
+#define  B43_TMSLOW_PHY_BANDWIDTH_40MHZ 0x00800000      /* 40 MHz bandwidth, 160 MHz PHY */
 #define B43_TMSLOW_PLLREFSEL            0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
 #define B43_TMSLOW_MACPHYCLKEN          0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 #define B43_TMSLOW_PHYRESET             0x00080000      /* PHY Reset */
diff --git a/drivers/net/wireless/b43/dma.c b/drivers/net/wireless/b43/dma.c
index 10d0aaf754c5..3d5566e7af0a 100644
--- a/drivers/net/wireless/b43/dma.c
+++ b/drivers/net/wireless/b43/dma.c
@@ -415,11 +415,6 @@ static int alloc_ringmemory(struct b43_dmaring *ring)
 
 static void free_ringmemory(struct b43_dmaring *ring)
 {
-        gfp_t flags = GFP_KERNEL;
-
-        if (ring->type == B43_DMA_64BIT)
-                flags |= GFP_DMA;
-
         dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE,
                           ring->descbase, ring->dmabase);
 }
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index a1186525c70d..22bc9f17f634 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -322,59 +322,83 @@ static int b43_ratelimit(struct b43_wl *wl)
 
 void b43info(struct b43_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (b43_modparam_verbose < B43_VERBOSITY_INFO)
                 return;
         if (!b43_ratelimit(wl))
                 return;
+
         va_start(args, fmt);
-        printk(KERN_INFO "b43-%s: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_INFO "b43-%s: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
 void b43err(struct b43_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
                 return;
         if (!b43_ratelimit(wl))
                 return;
+
         va_start(args, fmt);
-        printk(KERN_ERR "b43-%s ERROR: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_ERR "b43-%s ERROR: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (b43_modparam_verbose < B43_VERBOSITY_WARN)
                 return;
         if (!b43_ratelimit(wl))
                 return;
+
         va_start(args, fmt);
-        printk(KERN_WARNING "b43-%s warning: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_WARNING "b43-%s warning: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
                 return;
+
         va_start(args, fmt);
-        printk(KERN_DEBUG "b43-%s debug: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_DEBUG "b43-%s debug: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
@@ -1126,6 +1150,8 @@ void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 
         flags |= B43_TMSLOW_PHYCLKEN;
         flags |= B43_TMSLOW_PHYRESET;
+        if (dev->phy.type == B43_PHYTYPE_N)
+                flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
         ssb_device_enable(dev->dev, flags);
         msleep(2);              /* Wait for the PLL to turn on. */
 
@@ -2095,8 +2121,10 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
                 filename = "ucode13";
         else if (rev == 14)
                 filename = "ucode14";
-        else if (rev >= 15)
+        else if (rev == 15)
                 filename = "ucode15";
+        else if ((rev >= 16) && (rev <= 20))
+                filename = "ucode16_mimo";
         else
                 goto err_no_ucode;
         err = b43_do_request_fw(ctx, filename, &fw->ucode);
@@ -2139,7 +2167,9 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
                         goto err_no_initvals;
                 break;
         case B43_PHYTYPE_N:
-                if ((rev >= 11) && (rev <= 12))
+                if (rev >= 16)
+                        filename = "n0initvals16";
+                else if ((rev >= 11) && (rev <= 12))
                         filename = "n0initvals11";
                 else
                         goto err_no_initvals;
@@ -2183,7 +2213,9 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
                         goto err_no_initvals;
                 break;
         case B43_PHYTYPE_N:
-                if ((rev >= 11) && (rev <= 12))
+                if (rev >= 16)
+                        filename = "n0bsinitvals16";
+                else if ((rev >= 11) && (rev <= 12))
                         filename = "n0bsinitvals11";
                 else
                         goto err_no_initvals;
@@ -4022,9 +4054,9 @@ static int b43_phy_versioning(struct b43_wldev *dev)
                 if (phy_rev > 9)
                         unsupported = 1;
                 break;
-#ifdef CONFIG_B43_NPHY
+#ifdef CONFIG_B43_PHY_N
         case B43_PHYTYPE_N:
-                if (phy_rev > 4)
+                if (phy_rev > 9)
                         unsupported = 1;
                 break;
 #endif
@@ -5067,7 +5099,7 @@ static void b43_print_driverinfo(void)
 #ifdef CONFIG_B43_PCMCIA
         feat_pcmcia = "M";
 #endif
-#ifdef CONFIG_B43_NPHY
+#ifdef CONFIG_B43_PHY_N
         feat_nphy = "N";
 #endif
 #ifdef CONFIG_B43_LEDS
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
index 7b2ea6781457..b5c5ce94d3fd 100644
--- a/drivers/net/wireless/b43/phy_common.c
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -50,7 +50,7 @@ int b43_phy_allocate(struct b43_wldev *dev)
                 phy->ops = &b43_phyops_g;
                 break;
         case B43_PHYTYPE_N:
-#ifdef CONFIG_B43_NPHY
+#ifdef CONFIG_B43_PHY_N
                 phy->ops = &b43_phyops_n;
 #endif
                 break;
@@ -231,6 +231,7 @@ void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
 {
         assert_mac_suspended(dev);
+        dev->phy.writes_counter = 0;
         return dev->phy.ops->phy_read(dev, reg);
 }
 
@@ -238,6 +239,10 @@ void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
 {
         assert_mac_suspended(dev);
         dev->phy.ops->phy_write(dev, reg, value);
+        if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
+                b43_read16(dev, B43_MMIO_PHY_VER);
+                dev->phy.writes_counter = 0;
+        }
 }
 
 void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)
@@ -424,12 +429,21 @@ void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on)
         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 }
 
+
+bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
+{
+        return (channel_type == NL80211_CHAN_HT40MINUS ||
+                channel_type == NL80211_CHAN_HT40PLUS);
+}
+
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */
 struct b43_c32 b43_cordic(int theta)
 {
-        u32 arctg[] = { 2949120, 1740967, 919879, 466945, 234379, 117304,
-                      58666, 29335, 14668, 7334, 3667, 1833, 917, 458,
-                      229, 115, 57, 29, };
+        static const u32 arctg[] = {
+                2949120, 1740967, 919879, 466945, 234379, 117304,
+                  58666,   29335,  14668,   7334,   3667,   1833,
+                    917,     458,    229,    115,     57,     29,
+        };
         u8 i;
         s32 tmp;
         s8 signx = 1;
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
index 0e6194228845..2401bee8b081 100644
--- a/drivers/net/wireless/b43/phy_common.h
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -39,6 +39,9 @@ struct b43_c32 { s32 i, q; };
 #define B43_PHYVER_TYPE_SHIFT           8
 #define B43_PHYVER_VERSION              0x00FF
 
+/* PHY writes need to be flushed if we reach limit */
+#define B43_MAX_WRITES_IN_ROW           24
+
 /**
  * enum b43_interference_mitigation - Interference Mitigation mode
  *
@@ -232,6 +235,9 @@ struct b43_phy {
         /* PHY revision number. */
         u8 rev;
 
+        /* Count writes since last read */
+        u8 writes_counter;
+
         /* Radio versioning */
         u16 radio_manuf;        /* Radio manufacturer */
         u16 radio_ver;          /* Radio version */
@@ -430,6 +436,8 @@ int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset);
  */
 void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on);
 
+bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type);
+
 struct b43_c32 b43_cordic(int theta);
 
 #endif /* LINUX_B43_PHY_COMMON_H_ */
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index e0f2d122e124..ab81ed8b19d7 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -67,6 +67,18 @@ enum b43_nphy_rf_sequence {
         B43_RFSEQ_UPDATE_GAINU,
 };
 
+enum b43_nphy_rssi_type {
+        B43_NPHY_RSSI_X = 0,
+        B43_NPHY_RSSI_Y,
+        B43_NPHY_RSSI_Z,
+        B43_NPHY_RSSI_PWRDET,
+        B43_NPHY_RSSI_TSSI_I,
+        B43_NPHY_RSSI_TSSI_Q,
+        B43_NPHY_RSSI_TBD,
+};
+
+static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev,
+                                                bool enable);
 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
                                         u8 *events, u8 *delays, u8 length);
 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
@@ -76,13 +88,6 @@ static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
                                                 u16 value, u8 core);
 
-static inline bool b43_channel_type_is_40mhz(
-                                        enum nl80211_channel_type channel_type)
-{
-        return (channel_type == NL80211_CHAN_HT40MINUS ||
-                channel_type == NL80211_CHAN_HT40PLUS);
-}
-
 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
 {//TODO
 }
@@ -134,6 +139,99 @@ static void b43_chantab_radio_upload(struct b43_wldev *dev,
         b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
 }
 
+static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
+                                const struct b43_nphy_channeltab_entry_rev3 *e)
+{
+        b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
+        b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
+        b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
+        b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
+        b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
+        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
+                                        e->radio_syn_pll_loopfilter1);
+        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
+                                        e->radio_syn_pll_loopfilter2);
+        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
+                                        e->radio_syn_pll_loopfilter3);
+        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
+                                        e->radio_syn_pll_loopfilter4);
+        b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
+                                        e->radio_syn_pll_loopfilter5);
+        b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
+                                        e->radio_syn_reserved_addr27);
+        b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
+                                        e->radio_syn_reserved_addr28);
+        b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
+                                        e->radio_syn_reserved_addr29);
+        b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
+                                        e->radio_syn_logen_vcobuf1);
+        b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
+        b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
+        b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
+
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
+                                        e->radio_rx0_lnaa_tune);
+        b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
+                                        e->radio_rx0_lnag_tune);
+
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
+                                        e->radio_tx0_intpaa_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
+                                        e->radio_tx0_intpag_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
+                                        e->radio_tx0_pada_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
+                                        e->radio_tx0_padg_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
+                                        e->radio_tx0_pgaa_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
+                                        e->radio_tx0_pgag_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
+                                        e->radio_tx0_mixa_boost_tune);
+        b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
+                                        e->radio_tx0_mixg_boost_tune);
+
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
+                                        e->radio_rx1_lnaa_tune);
+        b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
+                                        e->radio_rx1_lnag_tune);
+
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
+                                        e->radio_tx1_intpaa_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
+                                        e->radio_tx1_intpag_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
+                                        e->radio_tx1_pada_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
+                                        e->radio_tx1_padg_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
+                                        e->radio_tx1_pgaa_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
+                                        e->radio_tx1_pgag_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
+                                        e->radio_tx1_mixa_boost_tune);
+        b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
+                                        e->radio_tx1_mixg_boost_tune);
+}
+
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
+static void b43_radio_2056_setup(struct b43_wldev *dev,
+                                const struct b43_nphy_channeltab_entry_rev3 *e)
+{
+        B43_WARN_ON(dev->phy.rev < 3);
+
+        b43_chantab_radio_2056_upload(dev, e);
+        /* TODO */
+        udelay(50);
+        /* VCO calibration */
+        b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
+        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
+        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
+        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
+        b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
+        udelay(300);
+}
+
 static void b43_chantab_phy_upload(struct b43_wldev *dev,
                                    const struct b43_phy_n_sfo_cfg *e)
 {
@@ -145,9 +243,154 @@ static void b43_chantab_phy_upload(struct b43_wldev *dev,
         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 }
 
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
+static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
+{
+        struct b43_phy_n *nphy = dev->phy.n;
+        u8 i;
+        u16 tmp;
+
+        if (nphy->hang_avoid)
+                b43_nphy_stay_in_carrier_search(dev, 1);
+
+        nphy->txpwrctrl = enable;
+        if (!enable) {
+                if (dev->phy.rev >= 3)
+                        ; /* TODO */
+
+                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
+                for (i = 0; i < 84; i++)
+                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
+
+                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
+                for (i = 0; i < 84; i++)
+                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
+
+                tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
+                if (dev->phy.rev >= 3)
+                        tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
+                b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
+
+                if (dev->phy.rev >= 3) {
+                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
+                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
+                } else {
+                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
+                }
+
+                if (dev->phy.rev == 2)
+                        b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
+                                ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
+                else if (dev->phy.rev < 2)
+                        b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
+                                ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
+
+                if (dev->phy.rev < 2 && 0)
+                        ; /* TODO */
+        } else {
+                b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
+        }
+
+        if (nphy->hang_avoid)
+                b43_nphy_stay_in_carrier_search(dev, 0);
+}
+
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 {
-        //TODO
+        struct b43_phy_n *nphy = dev->phy.n;
+        struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
+
+        u8 txpi[2], bbmult, i;
+        u16 tmp, radio_gain, dac_gain;
+        u16 freq = dev->phy.channel_freq;
+        u32 txgain;
+        /* u32 gaintbl; rev3+ */
+
+        if (nphy->hang_avoid)
+                b43_nphy_stay_in_carrier_search(dev, 1);
+
+        if (dev->phy.rev >= 3) {
+                txpi[0] = 40;
+                txpi[1] = 40;
+        } else if (sprom->revision < 4) {
+                txpi[0] = 72;
+                txpi[1] = 72;
+        } else {
+                if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
+                        txpi[0] = sprom->txpid2g[0];
+                        txpi[1] = sprom->txpid2g[1];
+                } else if (freq >= 4900 && freq < 5100) {
+                        txpi[0] = sprom->txpid5gl[0];
+                        txpi[1] = sprom->txpid5gl[1];
+                } else if (freq >= 5100 && freq < 5500) {
+                        txpi[0] = sprom->txpid5g[0];
+                        txpi[1] = sprom->txpid5g[1];
+                } else if (freq >= 5500) {
+                        txpi[0] = sprom->txpid5gh[0];
+                        txpi[1] = sprom->txpid5gh[1];
+                } else {
+                        txpi[0] = 91;
+                        txpi[1] = 91;
+                }
+        }
+
+        /*
+        for (i = 0; i < 2; i++) {
+                nphy->txpwrindex[i].index_internal = txpi[i];
+                nphy->txpwrindex[i].index_internal_save = txpi[i];
+        }
+        */
+
+        for (i = 0; i < 2; i++) {
+                if (dev->phy.rev >= 3) {
+                        /* FIXME: support 5GHz */
+                        txgain = b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
+                        radio_gain = (txgain >> 16) & 0x1FFFF;
+                } else {
+                        txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
+                        radio_gain = (txgain >> 16) & 0x1FFF;
+                }
+
+                dac_gain = (txgain >> 8) & 0x3F;
+                bbmult = txgain & 0xFF;
+
+                if (dev->phy.rev >= 3) {
+                        if (i == 0)
+                                b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
+                        else
+                                b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
+                } else {
+                        b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
+                }
+
+                if (i == 0)
+                        b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
+                else
+                        b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
+
+                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D10 + i);
+                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, radio_gain);
+
+                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
+                tmp = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
+
+                if (i == 0)
+                        tmp = (tmp & 0x00FF) | (bbmult << 8);
+                else
+                        tmp = (tmp & 0xFF00) | bbmult;
+
+                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C57);
+                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp);
+
+                if (0)
+                        ; /* TODO */
+        }
+
+        b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
+
+        if (nphy->hang_avoid)
+                b43_nphy_stay_in_carrier_search(dev, 0);
 }
 
 
@@ -191,7 +434,8 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
                                 binfo->type != 0x46D ||
                                 binfo->rev < 0x41);
         else
-                workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
+                workaround =
+                        !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
 
         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
         if (workaround) {
@@ -240,23 +484,55 @@ static void b43_radio_init2055_post(struct b43_wldev *dev)
 static void b43_radio_init2055(struct b43_wldev *dev)
 {
         b43_radio_init2055_pre(dev);
-        if (b43_status(dev) < B43_STAT_INITIALIZED)
-                b2055_upload_inittab(dev, 0, 1);
-        else
-                b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
+        if (b43_status(dev) < B43_STAT_INITIALIZED) {
+                /* Follow wl, not specs. Do not force uploading all regs */
+                b2055_upload_inittab(dev, 0, 0);
+        } else {
+                bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
+                b2055_upload_inittab(dev, ghz5, 0);
+        }
         b43_radio_init2055_post(dev);
 }
 
+static void b43_radio_init2056_pre(struct b43_wldev *dev)
+{
+        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
+                     ~B43_NPHY_RFCTL_CMD_CHIP0PU);
+        /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
+        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
+                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
+        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
+                    ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
+        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
+                    B43_NPHY_RFCTL_CMD_CHIP0PU);
+}
+
+static void b43_radio_init2056_post(struct b43_wldev *dev)
+{
+        b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
+        b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
+        b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
+        msleep(1);
+        b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
+        b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
+        b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
+        /*
+        if (nphy->init_por)
+                Call Radio 2056 Recalibrate
+        */
+}
+
 /*
  * Initialize a Broadcom 2056 N-radio
  * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
  */
 static void b43_radio_init2056(struct b43_wldev *dev)
 {
-        /* TODO */
+        b43_radio_init2056_pre(dev);
+        b2056_upload_inittabs(dev, 0, 0);
+        b43_radio_init2056_post(dev);
 }
 
-
 /*
  * Upload the N-PHY tables.
  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
@@ -453,6 +729,8 @@ static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
         }
 }
 
+#if 0
+/* Ready but not used anywhere */
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 {
@@ -534,6 +812,7 @@ static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
         b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
         b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
 }
+#endif
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
@@ -569,7 +848,6 @@ static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
                         ii = est.i1_pwr;
                         qq = est.q1_pwr;
                 } else {
-                        B43_WARN_ON(1);
                         continue;
                 }
 
@@ -651,7 +929,8 @@ static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
-static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
+static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
+                                          const u16 *clip_st)
 {
         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
@@ -727,7 +1006,7 @@ static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
         struct b43_phy_n *nphy = phy->n;
 
         if (enable) {
-                u16 clip[] = { 0xFFFF, 0xFFFF };
+                static const u16 clip[] = { 0xFFFF, 0xFFFF };
                 if (nphy->deaf_count++ == 0) {
                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
                         b43_nphy_classifier(dev, 0x7, 0);
@@ -839,7 +1118,7 @@ static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
         u16 data[4];
         s16 gain[2];
         u16 minmax[2];
-        u16 lna_gain[4] = { -2, 10, 19, 25 };
+        static const u16 lna_gain[4] = { -2, 10, 19, 25 };
 
         if (nphy->hang_avoid)
                 b43_nphy_stay_in_carrier_search(dev, 1);
@@ -871,7 +1150,7 @@ static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
                         data[2] = lna_gain[2] + gain[i];
                         data[3] = lna_gain[3] + gain[i];
                 }
-                b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
+                b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
 
                 minmax[i] = 23 + gain[i];
         }
@@ -891,6 +1170,7 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
         struct b43_phy_n *nphy = dev->phy.n;
         u8 i, j;
         u8 code;
+        u16 tmp;
 
         /* TODO: for PHY >= 3
         s8 *lna1_gain, *lna2_gain;
@@ -913,15 +1193,15 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
                                 B43_NPHY_C2_CGAINI_CL2DETECT);
 
                 /* Set narrowband clip threshold */
-                b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
-                b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
+                b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
+                b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
 
                 if (!dev->phy.is_40mhz) {
                         /* Set dwell lengths */
-                        b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
-                        b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
-                        b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
-                        b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
+                        b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
+                        b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
+                        b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
+                        b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
                 }
 
                 /* Set wideband clip 2 threshold */
@@ -943,7 +1223,7 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
                                 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
                 }
 
-                b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
+                b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
 
                 if (nphy->gain_boost) {
                         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
@@ -964,10 +1244,10 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
                                 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 
                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
-                b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
-                                        (code << 8 | 0x7C));
-                b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
-                                        (code << 8 | 0x7C));
+                /* specs say about 2 loops, but wl does 4 */
+                for (i = 0; i < 4; i++)
+                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
+                                                        (code << 8 | 0x7C));
 
                 b43_nphy_adjust_lna_gain_table(dev);
 
@@ -985,19 +1265,21 @@ static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
 
                         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
-                                        (code << 8 | 0x74));
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
-                                        (code << 8 | 0x74));
+                        /* specs say about 2 loops, but wl does 4 */
+                        for (i = 0; i < 4; i++)
+                                b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
+                                                        (code << 8 | 0x74));
                 }
 
                 if (dev->phy.rev == 2) {
                         for (i = 0; i < 4; i++) {
                                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
                                                 (0x0400 * i) + 0x0020);
-                                for (j = 0; j < 21; j++)
+                                for (j = 0; j < 21; j++) {
+                                        tmp = j * (i < 2 ? 3 : 1);
                                         b43_phy_write(dev,
-                                                B43_NPHY_TABLE_DATALO, 3 * j);
+                                                B43_NPHY_TABLE_DATALO, tmp);
+                                }
                         }
 
                         b43_nphy_set_rf_sequence(dev, 5,
@@ -1026,7 +1308,7 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
         u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
         u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
 
-        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
+        if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
                 b43_nphy_classifier(dev, 1, 0);
         else
                 b43_nphy_classifier(dev, 1, 1);
@@ -1049,29 +1331,18 @@ static void b43_nphy_workarounds(struct b43_wldev *dev)
                         b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
                 }
 
-                /* TODO: convert to b43_ntab_write? */
-                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
-                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
-                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
-                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
-                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
-                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
-                b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
-                b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
+                b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 
                 if (dev->phy.rev < 2) {
-                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
-                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
-                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
-                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
-                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
-                        b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
-                        b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
+                        b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
+                        b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
+                        b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
+                        b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
+                        b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
+                        b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
                 }
 
                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
@@ -1565,19 +1836,20 @@ static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
         }
 }
 
+/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 {
         unsigned int i;
         u16 val;
 
         val = 0x1E1F;
-        for (i = 0; i < 14; i++) {
+        for (i = 0; i < 16; i++) {
                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
                 val -= 0x202;
         }
         val = 0x3E3F;
         for (i = 0; i < 16; i++) {
-                b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
+                b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
                 val -= 0x202;
         }
         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
@@ -1585,7 +1857,8 @@ static void b43_nphy_bphy_init(struct b43_wldev *dev)
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
-                                       s8 offset, u8 core, u8 rail, u8 type)
+                                        s8 offset, u8 core, u8 rail,
+                                        enum b43_nphy_rssi_type type)
 {
         u16 tmp;
         bool core1or5 = (core == 1) || (core == 5);
@@ -1594,53 +1867,59 @@ static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
         offset = clamp_val(offset, -32, 31);
         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 
-        if (core1or5 && (rail == 0) && (type == 2))
+        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
-        if (core1or5 && (rail == 1) && (type == 2))
+        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
-        if (core2or5 && (rail == 0) && (type == 2))
+        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
-        if (core2or5 && (rail == 1) && (type == 2))
+        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
-        if (core1or5 && (rail == 0) && (type == 0))
+
+        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
-        if (core1or5 && (rail == 1) && (type == 0))
+        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
-        if (core2or5 && (rail == 0) && (type == 0))
+        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
-        if (core2or5 && (rail == 1) && (type == 0))
+        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
-        if (core1or5 && (rail == 0) && (type == 1))
+
+        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
-        if (core1or5 && (rail == 1) && (type == 1))
+        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
-        if (core2or5 && (rail == 0) && (type == 1))
+        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
-        if (core2or5 && (rail == 1) && (type == 1))
+        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
-        if (core1or5 && (rail == 0) && (type == 6))
+
+        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
-        if (core1or5 && (rail == 1) && (type == 6))
+        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
-        if (core2or5 && (rail == 0) && (type == 6))
+        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
-        if (core2or5 && (rail == 1) && (type == 6))
+        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
-        if (core1or5 && (rail == 0) && (type == 3))
+
+        if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
-        if (core1or5 && (rail == 1) && (type == 3))
+        if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
-        if (core2or5 && (rail == 0) && (type == 3))
+        if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
-        if (core2or5 && (rail == 1) && (type == 3))
+        if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
-        if (core1or5 && (type == 4))
+
+        if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
-        if (core2or5 && (type == 4))
+        if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
-        if (core1or5 && (type == 5))
+
+        if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
-        if (core2or5 && (type == 5))
+        if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 }
 
@@ -1668,27 +1947,39 @@ static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
                                 (type + 1) << 4);
         }
 
-        /* TODO use some definitions */
         if (code == 0) {
-                b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
+                b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
                 if (type < 3) {
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
+                        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
+                                ~(B43_NPHY_RFCTL_CMD_RXEN |
+                                  B43_NPHY_RFCTL_CMD_CORESEL));
+                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
+                                ~(0x1 << 12 |
+                                  0x1 << 5 |
+                                  0x1 << 1 |
+                                  0x1));
+                        b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
+                                ~B43_NPHY_RFCTL_CMD_START);
                         udelay(20);
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
+                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
                 }
         } else {
-                b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
-                                0x3000);
+                b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
                 if (type < 3) {
                         b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
-                                        0xFEC7, 0x0180);
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
-                                        0xEFDC, (code << 1 | 0x1021));
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
+                                ~(B43_NPHY_RFCTL_CMD_RXEN |
+                                  B43_NPHY_RFCTL_CMD_CORESEL),
+                                (B43_NPHY_RFCTL_CMD_RXEN |
+                                 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
+                        b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
+                                (0x1 << 12 |
+                                  0x1 << 5 |
+                                  0x1 << 1 |
+                                  0x1));
+                        b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
+                                B43_NPHY_RFCTL_CMD_START);
                         udelay(20);
-                        b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
+                        b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
                 }
         }
 }
@@ -1837,6 +2128,14 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
+        } else if (dev->phy.rev == 2) {
+                save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
+                save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
+                save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
+                save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
+                save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
+                save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
+                save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
         }
 
         b43_nphy_rssi_select(dev, 5, type);
@@ -1880,6 +2179,14 @@ static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
+        } else if (dev->phy.rev == 2) {
+                b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
+                b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
+                b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
+                b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
+                b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
+                b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
+                b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
         }
 
         return out;
@@ -1894,7 +2201,10 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
         u16 class, override;
         u8 regs_save_radio[2];
         u16 regs_save_phy[2];
+
         s8 offset[4];
+        u8 core;
+        u8 rail;
 
         u16 clip_state[2];
         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
@@ -1995,16 +2305,15 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
                 if (results_min[i] == 248)
                         offset[i] = code - 32;
 
-                if (i % 2 == 0)
-                        b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
-                                                        type);
-                else
-                        b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
-                                                        type);
+                core = (i / 2) ? 2 : 1;
+                rail = (i % 2) ? 1 : 0;
+
+                b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
+                                                type);
         }
 
         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
-        b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
+        b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
 
         switch (state[2]) {
         case 1:
@@ -2042,6 +2351,9 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
 
         b43_nphy_classifier(dev, 7, class);
         b43_nphy_write_clip_detection(dev, clip_state);
+        /* Specs don't say about reset here, but it makes wl and b43 dumps
+           identical, it really seems wl performs this */
+        b43_nphy_reset_cca(dev);
 }
 
 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
@@ -2059,9 +2371,9 @@ static void b43_nphy_rssi_cal(struct b43_wldev *dev)
         if (dev->phy.rev >= 3) {
                 b43_nphy_rev3_rssi_cal(dev);
         } else {
-                b43_nphy_rev2_rssi_cal(dev, 2);
-                b43_nphy_rev2_rssi_cal(dev, 0);
-                b43_nphy_rev2_rssi_cal(dev, 1);
+                b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
+                b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
+                b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
         }
 }
 
@@ -2295,7 +2607,7 @@ static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
 {
         int i, j;
         /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
-        u16 offset[] = { 0x186, 0x195, 0x2C5 };
+        static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
 
         for (i = 0; i < 3; i++)
                 for (j = 0; j < 15; j++)
@@ -2327,7 +2639,7 @@ static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
         struct nphy_txgains target;
         const u32 *table = NULL;
 
-        if (nphy->txpwrctrl == 0) {
+        if (!nphy->txpwrctrl) {
                 int i;
 
                 if (nphy->hang_avoid)
@@ -2884,7 +3196,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
         u8 rfctl[2];
         u8 afectl_core;
         u16 tmp[6];
-        u16 cur_hpf1, cur_hpf2, cur_lna;
+        u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
         u32 real, imag;
         enum ieee80211_band band;
 
@@ -3077,9 +3389,9 @@ static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
 {
         u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
         if (on)
-                tmslow |= SSB_TMSLOW_PHYCLK;
+                tmslow |= B43_TMSLOW_MACPHYCLKEN;
         else
-                tmslow &= ~SSB_TMSLOW_PHYCLK;
+                tmslow &= ~B43_TMSLOW_MACPHYCLKEN;
         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 }
 
@@ -3088,7 +3400,7 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
 {
         struct b43_phy *phy = &dev->phy;
         struct b43_phy_n *nphy = phy->n;
-        u16 buf[16];
+        /* u16 buf[16]; it's rev3+ */
 
         nphy->phyrxchain = mask;
 
@@ -3232,10 +3544,12 @@ int b43_phy_initn(struct b43_wldev *dev)
 
         b43_nphy_classifier(dev, 0, 0);
         b43_nphy_read_clip_detection(dev, clip);
+        if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
+                b43_nphy_bphy_init(dev);
+
         tx_pwr_state = nphy->txpwrctrl;
-        /* TODO N PHY TX power control with argument 0
-                (turning off power control) */
-        /* TODO Fix the TX Power Settings */
+        b43_nphy_tx_power_ctrl(dev, false);
+        b43_nphy_tx_power_fix(dev);
         /* TODO N PHY TX Power Control Idle TSSI */
         /* TODO N PHY TX Power Control Setup */
 
@@ -3292,21 +3606,18 @@ int b43_phy_initn(struct b43_wldev *dev)
                                         /* TODO N PHY Pre Calibrate TX Gain */
                                         target = b43_nphy_get_tx_gains(dev);
                                 }
-                        }
+                                if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
+                                        if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
+                                                b43_nphy_save_cal(dev);
+                        } else if (nphy->mphase_cal_phase_id == 0)
+                                ;/* N PHY Periodic Calibration with arg 3 */
+                } else {
+                        b43_nphy_restore_cal(dev);
                 }
         }
 
-        if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
-                if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
-                        b43_nphy_save_cal(dev);
-                else if (nphy->mphase_cal_phase_id == 0)
-                        ;/* N PHY Periodic Calibration with argument 3 */
-        } else {
-                b43_nphy_restore_cal(dev);
-        }
-
         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
-        /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
+        b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
         if (phy->rev >= 3 && phy->rev <= 6)
@@ -3315,7 +3626,6 @@ int b43_phy_initn(struct b43_wldev *dev)
         if (phy->rev >= 3)
                 b43_nphy_spur_workaround(dev);
 
-        b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
         return 0;
 }
 
@@ -3357,7 +3667,7 @@ static void b43_nphy_channel_setup(struct b43_wldev *dev,
                         b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
         }
 
-        if (nphy->txpwrctrl)
+        if (!nphy->txpwrctrl)
                 b43_nphy_tx_power_fix(dev);
 
         if (dev->phy.rev < 3)
@@ -3381,7 +3691,6 @@ static int b43_nphy_set_channel(struct b43_wldev *dev,
                                 enum nl80211_channel_type channel_type)
 {
         struct b43_phy *phy = &dev->phy;
-        struct b43_phy_n *nphy = dev->phy.n;
 
         const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
         const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
@@ -3391,7 +3700,6 @@ static int b43_nphy_set_channel(struct b43_wldev *dev,
         if (dev->phy.rev >= 3) {
                 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
                                                         channel->center_freq);
-                tabent_r3 = NULL;
                 if (!tabent_r3)
                         return -ESRCH;
         } else {
@@ -3420,7 +3728,7 @@ static int b43_nphy_set_channel(struct b43_wldev *dev,
         if (dev->phy.rev >= 3) {
                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
                 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
-                /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
+                b43_radio_2056_setup(dev, tabent_r3);
                 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
         } else {
                 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
@@ -3451,7 +3759,11 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
 
         memset(nphy, 0, sizeof(*nphy));
 
-        //TODO init struct b43_phy_n
+        nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
+        nphy->gain_boost = true; /* this way we follow wl, assume it is true */
+        nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
+        nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
+        nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
 }
 
 static void b43_nphy_op_free(struct b43_wldev *dev)
@@ -3500,6 +3812,15 @@ static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 }
 
+static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
+                                 u16 set)
+{
+        check_phyreg(dev, reg);
+        b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
+        b43_write16(dev, B43_MMIO_PHY_DATA,
+                    (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
+}
+
 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 {
         /* Register 1 is a 32-bit register. */
@@ -3524,8 +3845,6 @@ static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
                                         bool blocked)
 {
-        struct b43_phy_n *nphy = dev->phy.n;
-
         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
                 b43err(dev->wl, "MAC not suspended\n");
 
@@ -3596,6 +3915,7 @@ const struct b43_phy_operations b43_phyops_n = {
         .init                   = b43_nphy_op_init,
         .phy_read               = b43_nphy_op_read,
         .phy_write              = b43_nphy_op_write,
+        .phy_maskset            = b43_nphy_op_maskset,
         .radio_read             = b43_nphy_op_radio_read,
         .radio_write            = b43_nphy_op_radio_write,
         .software_rfkill        = b43_nphy_op_software_rfkill,
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h
index c144e59a708b..001e841f118c 100644
--- a/drivers/net/wireless/b43/phy_n.h
+++ b/drivers/net/wireless/b43/phy_n.h
@@ -782,7 +782,7 @@ struct b43_phy_n {
         u16 mphase_txcal_numcmds;
         u16 mphase_txcal_bestcoeffs[11];
 
-        u8 txpwrctrl;
+        bool txpwrctrl;
         u16 txcal_bbmult;
         u16 txiqlocal_bestc[11];
         bool txiqlocal_coeffsvalid;
diff --git a/drivers/net/wireless/b43/radio_2055.c b/drivers/net/wireless/b43/radio_2055.c
index 1b5316586cbf..44c6dea66882 100644
--- a/drivers/net/wireless/b43/radio_2055.c
+++ b/drivers/net/wireless/b43/radio_2055.c
@@ -244,7 +244,7 @@ static const struct b2055_inittab_entry b2055_inittab [] = {
   [0xCB]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [0xCC]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [B2055_C1_LNA_GAINBST]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
-  [0xCE]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+  [0xCE]                        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
   [0xCF]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [0xD0]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [0xD1]                        = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
@@ -256,7 +256,7 @@ static const struct b2055_inittab_entry b2055_inittab [] = {
   [0xD7]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [0xD8]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [B2055_C2_LNA_GAINBST]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
-  [0xDA]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+  [0xDA]                        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
   [0xDB]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [0xDC]                        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
   [0xDD]                        = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
@@ -304,178 +304,178 @@ static const struct b43_nphy_channeltab_entry_rev2 b43_nphy_channeltab_rev2[] =
   {     .channel                = 184,
         .freq                   = 4920, /* MHz */
         .unk2                   = 3280,
-        RADIOREGS(0x71, 0x01, 0xEC, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xEC, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xB407, 0xB007, 0xAC07, 0x1402, 0x1502, 0x1602),
+        PHYREGS(0x07B4, 0x07B0, 0x07AC, 0x0214, 0x0215, 0x0216),
   },
   {     .channel                = 186,
         .freq                   = 4930, /* MHz */
         .unk2                   = 3287,
-        RADIOREGS(0x71, 0x01, 0xED, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xED, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xFF, 0xFF, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xB807, 0xB407, 0xB007, 0x1302, 0x1402, 0x1502),
+        PHYREGS(0x07B8, 0x07B4, 0x07B0, 0x0213, 0x0214, 0x0215),
   },
   {     .channel                = 188,
         .freq                   = 4940, /* MHz */
         .unk2                   = 3293,
-        RADIOREGS(0x71, 0x01, 0xEE, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xEE, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xBC07, 0xB807, 0xB407, 0x1202, 0x1302, 0x1402),
+        PHYREGS(0x07BC, 0x07B8, 0x07B4, 0x0212, 0x0213, 0x0214),
   },
   {     .channel                = 190,
         .freq                   = 4950, /* MHz */
         .unk2                   = 3300,
-        RADIOREGS(0x71, 0x01, 0xEF, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xEF, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xC007, 0xBC07, 0xB807, 0x1102, 0x1202, 0x1302),
+        PHYREGS(0x07C0, 0x07BC, 0x07B8, 0x0211, 0x0212, 0x0213),
   },
   {     .channel                = 192,
         .freq                   = 4960, /* MHz */
         .unk2                   = 3307,
-        RADIOREGS(0x71, 0x01, 0xF0, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF0, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xC407, 0xC007, 0xBC07, 0x0F02, 0x1102, 0x1202),
+        PHYREGS(0x07C4, 0x07C0, 0x07BC, 0x020F, 0x0211, 0x0212),
   },
   {     .channel                = 194,
         .freq                   = 4970, /* MHz */
         .unk2                   = 3313,
-        RADIOREGS(0x71, 0x01, 0xF1, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF1, 0x01, 0x0F, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xEE, 0xEE, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xC807, 0xC407, 0xC007, 0x0E02, 0x0F02, 0x1102),
+        PHYREGS(0x07C8, 0x07C4, 0x07C0, 0x020E, 0x020F, 0x0211),
   },
   {     .channel                = 196,
         .freq                   = 4980, /* MHz */
         .unk2                   = 3320,
-        RADIOREGS(0x71, 0x01, 0xF2, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF2, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xCC07, 0xC807, 0xC407, 0x0D02, 0x0E02, 0x0F02),
+        PHYREGS(0x07CC, 0x07C8, 0x07C4, 0x020D, 0x020E, 0x020F),
   },
   {     .channel                = 198,
         .freq                   = 4990, /* MHz */
         .unk2                   = 3327,
-        RADIOREGS(0x71, 0x01, 0xF3, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF3, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xD007, 0xCC07, 0xC807, 0x0C02, 0x0D02, 0x0E02),
+        PHYREGS(0x07D0, 0x07CC, 0x07C8, 0x020C, 0x020D, 0x020E),
   },
   {     .channel                = 200,
         .freq                   = 5000, /* MHz */
         .unk2                   = 3333,
-        RADIOREGS(0x71, 0x01, 0xF4, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF4, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xD407, 0xD007, 0xCC07, 0x0B02, 0x0C02, 0x0D02),
+        PHYREGS(0x07D4, 0x07D0, 0x07CC, 0x020B, 0x020C, 0x020D),
   },
   {     .channel                = 202,
         .freq                   = 5010, /* MHz */
         .unk2                   = 3340,
-        RADIOREGS(0x71, 0x01, 0xF5, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF5, 0x01, 0x0E, 0xFF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xDD, 0xDD, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xD807, 0xD407, 0xD007, 0x0A02, 0x0B02, 0x0C02),
+        PHYREGS(0x07D8, 0x07D4, 0x07D0, 0x020A, 0x020B, 0x020C),
   },
   {     .channel                = 204,
         .freq                   = 5020, /* MHz */
         .unk2                   = 3347,
-        RADIOREGS(0x71, 0x01, 0xF6, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF6, 0x01, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xDC07, 0xD807, 0xD407, 0x0902, 0x0A02, 0x0B02),
+        PHYREGS(0x07DC, 0x07D8, 0x07D4, 0x0209, 0x020A, 0x020B),
   },
   {     .channel                = 206,
         .freq                   = 5030, /* MHz */
         .unk2                   = 3353,
-        RADIOREGS(0x71, 0x01, 0xF7, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF7, 0x01, 0x0E, 0xF7, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xE007, 0xDC07, 0xD807, 0x0802, 0x0902, 0x0A02),
+        PHYREGS(0x07E0, 0x07DC, 0x07D8, 0x0208, 0x0209, 0x020A),
   },
   {     .channel                = 208,
         .freq                   = 5040, /* MHz */
         .unk2                   = 3360,
-        RADIOREGS(0x71, 0x01, 0xF8, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF8, 0x01, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xE407, 0xE007, 0xDC07, 0x0702, 0x0802, 0x0902),
+        PHYREGS(0x07E4, 0x07E0, 0x07DC, 0x0207, 0x0208, 0x0209),
   },
   {     .channel                = 210,
         .freq                   = 5050, /* MHz */
         .unk2                   = 3367,
-        RADIOREGS(0x71, 0x01, 0xF9, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xF9, 0x01, 0x0D, 0xEF, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xCC, 0xCC, 0xFF, 0x00, 0x0F, 0x0F,
                   0x8F, 0xFF, 0x00, 0x0F, 0x0F, 0x8F),
-        PHYREGS(0xE807, 0xE407, 0xE007, 0x0602, 0x0702, 0x0802),
+        PHYREGS(0x07E8, 0x07E4, 0x07E0, 0x0206, 0x0207, 0x0208),
   },
   {     .channel                = 212,
         .freq                   = 5060, /* MHz */
         .unk2                   = 3373,
-        RADIOREGS(0x71, 0x01, 0xFA, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xFA, 0x01, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F,
                   0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E),
-        PHYREGS(0xEC07, 0xE807, 0xE407, 0x0502, 0x0602, 0x0702),
+        PHYREGS(0x07EC, 0x07E8, 0x07E4, 0x0205, 0x0206, 0x0207),
   },
   {     .channel                = 214,
         .freq                   = 5070, /* MHz */
         .unk2                   = 3380,
-        RADIOREGS(0x71, 0x01, 0xFB, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xFB, 0x01, 0x0D, 0xE6, 0x01, 0x04, 0x0A,
                   0x00, 0x8F, 0xBB, 0xBB, 0xFF, 0x00, 0x0E, 0x0F,
                   0x8E, 0xFF, 0x00, 0x0E, 0x0F, 0x8E),
-        PHYREGS(0xF007, 0xEC07, 0xE807, 0x0402, 0x0502, 0x0602),
+        PHYREGS(0x07F0, 0x07EC, 0x07E8, 0x0204, 0x0205, 0x0206),
   },
   {     .channel                = 216,
         .freq                   = 5080, /* MHz */
         .unk2                   = 3387,
-        RADIOREGS(0x71, 0x01, 0xFC, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xFC, 0x01, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
                   0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F,
                   0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D),
-        PHYREGS(0xF407, 0xF007, 0xEC07, 0x0302, 0x0402, 0x0502),
+        PHYREGS(0x07F4, 0x07F0, 0x07EC, 0x0203, 0x0204, 0x0205),
   },
   {     .channel                = 218,
         .freq                   = 5090, /* MHz */
         .unk2                   = 3393,
-        RADIOREGS(0x71, 0x01, 0xFD, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xFD, 0x01, 0x0D, 0xDE, 0x01, 0x04, 0x0A,
                   0x00, 0x8E, 0xBB, 0xBB, 0xEE, 0x00, 0x0E, 0x0F,
                   0x8D, 0xEE, 0x00, 0x0E, 0x0F, 0x8D),
-        PHYREGS(0xF807, 0xF407, 0xF007, 0x0202, 0x0302, 0x0402),
+        PHYREGS(0x07F8, 0x07F4, 0x07F0, 0x0202, 0x0203, 0x0204),
   },
   {     .channel                = 220,
         .freq                   = 5100, /* MHz */
         .unk2                   = 3400,
-        RADIOREGS(0x71, 0x01, 0xFE, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xFE, 0x01, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
                   0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F,
                   0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D),
-        PHYREGS(0xFC07, 0xF807, 0xF407, 0x0102, 0x0202, 0x0302),
+        PHYREGS(0x07FC, 0x07F8, 0x07F4, 0x0201, 0x0202, 0x0203),
   },
   {     .channel                = 222,
         .freq                   = 5110, /* MHz */
         .unk2                   = 3407,
-        RADIOREGS(0x71, 0x01, 0xFF, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0xFF, 0x01, 0x0C, 0xD6, 0x01, 0x04, 0x0A,
                   0x00, 0x8E, 0xAA, 0xAA, 0xEE, 0x00, 0x0D, 0x0F,
                   0x8D, 0xEE, 0x00, 0x0D, 0x0F, 0x8D),
-        PHYREGS(0x0008, 0xFC07, 0xF807, 0x0002, 0x0102, 0x0202),
+        PHYREGS(0x0800, 0x07FC, 0x07F8, 0x0200, 0x0201, 0x0202),
   },
   {     .channel                = 224,
         .freq                   = 5120, /* MHz */
         .unk2                   = 3413,
-        RADIOREGS(0x71, 0x02, 0x00, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x00, 0x02, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
                   0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F,
                   0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C),
-        PHYREGS(0x0408, 0x0008, 0xFC07, 0xFF01, 0x0002, 0x0102),
+        PHYREGS(0x0804, 0x0800, 0x07FC, 0x01FF, 0x0200, 0x0201),
   },
   {     .channel                = 226,
         .freq                   = 5130, /* MHz */
         .unk2                   = 3420,
-        RADIOREGS(0x71, 0x02, 0x01, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x01, 0x02, 0x0C, 0xCE, 0x01, 0x04, 0x0A,
                   0x00, 0x8D, 0xAA, 0xAA, 0xDD, 0x00, 0x0D, 0x0F,
                   0x8C, 0xDD, 0x00, 0x0D, 0x0F, 0x8C),
-        PHYREGS(0x0808, 0x0408, 0x0008, 0xFE01, 0xFF01, 0x0002),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01FE, 0x01FF, 0x0200),
   },
   {     .channel                = 228,
         .freq                   = 5140, /* MHz */
@@ -483,815 +483,815 @@ static const struct b43_nphy_channeltab_entry_rev2 b43_nphy_channeltab_rev2[] =
         RADIOREGS(0x71, 0x02, 0x02, 0x0C, 0xC6, 0x01, 0x04, 0x0A,
                   0x00, 0x8D, 0x99, 0x99, 0xDD, 0x00, 0x0C, 0x0E,
                   0x8B, 0xDD, 0x00, 0x0C, 0x0E, 0x8B),
-        PHYREGS(0x0C08, 0x0808, 0x0408, 0xFD01, 0xFE01, 0xFF01),
+        PHYREGS(0x080C, 0x0808, 0x0804, 0x01FD, 0x01FE, 0x01FF),
   },
   {     .channel                = 32,
         .freq                   = 5160, /* MHz */
         .unk2                   = 3440,
-        RADIOREGS(0x71, 0x02, 0x04, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x04, 0x02, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
                   0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D,
                   0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A),
-        PHYREGS(0x1408, 0x1008, 0x0C08, 0xFB01, 0xFC01, 0xFD01),
+        PHYREGS(0x0814, 0x0810, 0x080C, 0x01FB, 0x01FC, 0x01FD),
   },
   {     .channel                = 34,
         .freq                   = 5170, /* MHz */
         .unk2                   = 3447,
-        RADIOREGS(0x71, 0x02, 0x05, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x05, 0x02, 0x0B, 0xBE, 0x01, 0x04, 0x0A,
                   0x00, 0x8C, 0x99, 0x99, 0xCC, 0x00, 0x0B, 0x0D,
                   0x8A, 0xCC, 0x00, 0x0B, 0x0D, 0x8A),
-        PHYREGS(0x1808, 0x1408, 0x1008, 0xFA01, 0xFB01, 0xFC01),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01FA, 0x01FB, 0x01FC),
   },
   {     .channel                = 36,
         .freq                   = 5180, /* MHz */
         .unk2                   = 3453,
-        RADIOREGS(0x71, 0x02, 0x06, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x06, 0x02, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
                   0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C,
                   0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89),
-        PHYREGS(0x1C08, 0x1808, 0x1408, 0xF901, 0xFA01, 0xFB01),
+        PHYREGS(0x081C, 0x0818, 0x0814, 0x01F9, 0x01FA, 0x01FB),
   },
   {     .channel                = 38,
         .freq                   = 5190, /* MHz */
         .unk2                   = 3460,
-        RADIOREGS(0x71, 0x02, 0x07, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x07, 0x02, 0x0B, 0xB6, 0x01, 0x04, 0x0A,
                   0x00, 0x8C, 0x88, 0x88, 0xCC, 0x00, 0x0B, 0x0C,
                   0x89, 0xCC, 0x00, 0x0B, 0x0C, 0x89),
-        PHYREGS(0x2008, 0x1C08, 0x1808, 0xF801, 0xF901, 0xFA01),
+        PHYREGS(0x0820, 0x081C, 0x0818, 0x01F8, 0x01F9, 0x01FA),
   },
   {     .channel                = 40,
         .freq                   = 5200, /* MHz */
         .unk2                   = 3467,
-        RADIOREGS(0x71, 0x02, 0x08, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x08, 0x02, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
                   0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B,
                   0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89),
-        PHYREGS(0x2408, 0x2008, 0x1C08, 0xF701, 0xF801, 0xF901),
+        PHYREGS(0x0824, 0x0820, 0x081C, 0x01F7, 0x01F8, 0x01F9),
   },
   {     .channel                = 42,
         .freq                   = 5210, /* MHz */
         .unk2                   = 3473,
-        RADIOREGS(0x71, 0x02, 0x09, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x09, 0x02, 0x0B, 0xAF, 0x01, 0x04, 0x0A,
                   0x00, 0x8B, 0x88, 0x88, 0xBB, 0x00, 0x0A, 0x0B,
                   0x89, 0xBB, 0x00, 0x0A, 0x0B, 0x89),
-        PHYREGS(0x2808, 0x2408, 0x2008, 0xF601, 0xF701, 0xF801),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01F6, 0x01F7, 0x01F8),
   },
   {     .channel                = 44,
         .freq                   = 5220, /* MHz */
         .unk2                   = 3480,
-        RADIOREGS(0x71, 0x02, 0x0A, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x0A, 0x02, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
                   0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A,
                   0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88),
-        PHYREGS(0x2C08, 0x2808, 0x2408, 0xF501, 0xF601, 0xF701),
+        PHYREGS(0x082C, 0x0828, 0x0824, 0x01F5, 0x01F6, 0x01F7),
   },
   {     .channel                = 46,
         .freq                   = 5230, /* MHz */
         .unk2                   = 3487,
-        RADIOREGS(0x71, 0x02, 0x0B, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x0B, 0x02, 0x0A, 0xA7, 0x01, 0x04, 0x0A,
                   0x00, 0x8B, 0x77, 0x77, 0xBB, 0x00, 0x09, 0x0A,
                   0x88, 0xBB, 0x00, 0x09, 0x0A, 0x88),
-        PHYREGS(0x3008, 0x2C08, 0x2808, 0xF401, 0xF501, 0xF601),
+        PHYREGS(0x0830, 0x082C, 0x0828, 0x01F4, 0x01F5, 0x01F6),
   },
   {     .channel                = 48,
         .freq                   = 5240, /* MHz */
         .unk2                   = 3493,
-        RADIOREGS(0x71, 0x02, 0x0C, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x0C, 0x02, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
                   0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A,
                   0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87),
-        PHYREGS(0x3408, 0x3008, 0x2C08, 0xF301, 0xF401, 0xF501),
+        PHYREGS(0x0834, 0x0830, 0x082C, 0x01F3, 0x01F4, 0x01F5),
   },
   {     .channel                = 50,
         .freq                   = 5250, /* MHz */
         .unk2                   = 3500,
-        RADIOREGS(0x71, 0x02, 0x0D, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x0D, 0x02, 0x0A, 0xA0, 0x01, 0x04, 0x0A,
                   0x00, 0x8A, 0x77, 0x77, 0xAA, 0x00, 0x09, 0x0A,
                   0x87, 0xAA, 0x00, 0x09, 0x0A, 0x87),
-        PHYREGS(0x3808, 0x3408, 0x3008, 0xF201, 0xF301, 0xF401),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01F2, 0x01F3, 0x01F4),
   },
   {     .channel                = 52,
         .freq                   = 5260, /* MHz */
         .unk2                   = 3507,
-        RADIOREGS(0x71, 0x02, 0x0E, 0x0A, 0x98, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x0E, 0x02, 0x0A, 0x98, 0x01, 0x04, 0x0A,
                   0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09,
                   0x87, 0xAA, 0x00, 0x08, 0x09, 0x87),
-        PHYREGS(0x3C08, 0x3808, 0x3408, 0xF101, 0xF201, 0xF301),
+        PHYREGS(0x083C, 0x0838, 0x0834, 0x01F1, 0x01F2, 0x01F3),
   },
   {     .channel                = 54,
         .freq                   = 5270, /* MHz */
         .unk2                   = 3513,
-        RADIOREGS(0x71, 0x02, 0x0F, 0x0A, 0x98, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x0F, 0x02, 0x0A, 0x98, 0x01, 0x04, 0x0A,
                   0x00, 0x8A, 0x66, 0x66, 0xAA, 0x00, 0x08, 0x09,
                   0x87, 0xAA, 0x00, 0x08, 0x09, 0x87),
-        PHYREGS(0x4008, 0x3C08, 0x3808, 0xF001, 0xF101, 0xF201),
+        PHYREGS(0x0840, 0x083C, 0x0838, 0x01F0, 0x01F1, 0x01F2),
   },
   {     .channel                = 56,
         .freq                   = 5280, /* MHz */
         .unk2                   = 3520,
-        RADIOREGS(0x71, 0x02, 0x10, 0x09, 0x91, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x10, 0x02, 0x09, 0x91, 0x01, 0x04, 0x0A,
                   0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08,
                   0x86, 0x99, 0x00, 0x08, 0x08, 0x86),
-        PHYREGS(0x4408, 0x4008, 0x3C08, 0xF001, 0xF001, 0xF101),
+        PHYREGS(0x0844, 0x0840, 0x083C, 0x01F0, 0x01F0, 0x01F1),
   },
   {     .channel                = 58,
         .freq                   = 5290, /* MHz */
         .unk2                   = 3527,
-        RADIOREGS(0x71, 0x02, 0x11, 0x09, 0x91, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x11, 0x02, 0x09, 0x91, 0x01, 0x04, 0x0A,
                   0x00, 0x89, 0x66, 0x66, 0x99, 0x00, 0x08, 0x08,
                   0x86, 0x99, 0x00, 0x08, 0x08, 0x86),
-        PHYREGS(0x4808, 0x4408, 0x4008, 0xEF01, 0xF001, 0xF001),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01EF, 0x01F0, 0x01F0),
   },
   {     .channel                = 60,
         .freq                   = 5300, /* MHz */
         .unk2                   = 3533,
-        RADIOREGS(0x71, 0x02, 0x12, 0x09, 0x8A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x12, 0x02, 0x09, 0x8A, 0x01, 0x04, 0x0A,
                   0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07,
                   0x85, 0x99, 0x00, 0x08, 0x07, 0x85),
-        PHYREGS(0x4C08, 0x4808, 0x4408, 0xEE01, 0xEF01, 0xF001),
+        PHYREGS(0x084C, 0x0848, 0x0844, 0x01EE, 0x01EF, 0x01F0),
   },
   {     .channel                = 62,
         .freq                   = 5310, /* MHz */
         .unk2                   = 3540,
-        RADIOREGS(0x71, 0x02, 0x13, 0x09, 0x8A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x13, 0x02, 0x09, 0x8A, 0x01, 0x04, 0x0A,
                   0x00, 0x89, 0x55, 0x55, 0x99, 0x00, 0x08, 0x07,
                   0x85, 0x99, 0x00, 0x08, 0x07, 0x85),
-        PHYREGS(0x5008, 0x4C08, 0x4808, 0xED01, 0xEE01, 0xEF01),
+        PHYREGS(0x0850, 0x084C, 0x0848, 0x01ED, 0x01EE, 0x01EF),
   },
   {     .channel                = 64,
         .freq                   = 5320, /* MHz */
         .unk2                   = 3547,
-        RADIOREGS(0x71, 0x02, 0x14, 0x09, 0x83, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x14, 0x02, 0x09, 0x83, 0x01, 0x04, 0x0A,
                   0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07,
                   0x84, 0x88, 0x00, 0x07, 0x07, 0x84),
-        PHYREGS(0x5408, 0x5008, 0x4C08, 0xEC01, 0xED01, 0xEE01),
+        PHYREGS(0x0854, 0x0850, 0x084C, 0x01EC, 0x01ED, 0x01EE),
   },
   {     .channel                = 66,
         .freq                   = 5330, /* MHz */
         .unk2                   = 3553,
-        RADIOREGS(0x71, 0x02, 0x15, 0x09, 0x83, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x15, 0x02, 0x09, 0x83, 0x01, 0x04, 0x0A,
                   0x00, 0x88, 0x55, 0x55, 0x88, 0x00, 0x07, 0x07,
                   0x84, 0x88, 0x00, 0x07, 0x07, 0x84),
-        PHYREGS(0x5808, 0x5408, 0x5008, 0xEB01, 0xEC01, 0xED01),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01EB, 0x01EC, 0x01ED),
   },
   {     .channel                = 68,
         .freq                   = 5340, /* MHz */
         .unk2                   = 3560,
-        RADIOREGS(0x71, 0x02, 0x16, 0x08, 0x7C, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x16, 0x02, 0x08, 0x7C, 0x01, 0x04, 0x0A,
                   0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06,
                   0x84, 0x88, 0x00, 0x07, 0x06, 0x84),
-        PHYREGS(0x5C08, 0x5808, 0x5408, 0xEA01, 0xEB01, 0xEC01),
+        PHYREGS(0x085C, 0x0858, 0x0854, 0x01EA, 0x01EB, 0x01EC),
   },
   {     .channel                = 70,
         .freq                   = 5350, /* MHz */
         .unk2                   = 3567,
-        RADIOREGS(0x71, 0x02, 0x17, 0x08, 0x7C, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x17, 0x02, 0x08, 0x7C, 0x01, 0x04, 0x0A,
                   0x00, 0x88, 0x44, 0x44, 0x88, 0x00, 0x07, 0x06,
                   0x84, 0x88, 0x00, 0x07, 0x06, 0x84),
-        PHYREGS(0x6008, 0x5C08, 0x5808, 0xE901, 0xEA01, 0xEB01),
+        PHYREGS(0x0860, 0x085C, 0x0858, 0x01E9, 0x01EA, 0x01EB),
   },
   {     .channel                = 72,
         .freq                   = 5360, /* MHz */
         .unk2                   = 3573,
-        RADIOREGS(0x71, 0x02, 0x18, 0x08, 0x75, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x18, 0x02, 0x08, 0x75, 0x01, 0x04, 0x0A,
                   0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05,
                   0x83, 0x77, 0x00, 0x06, 0x05, 0x83),
-        PHYREGS(0x6408, 0x6008, 0x5C08, 0xE801, 0xE901, 0xEA01),
+        PHYREGS(0x0864, 0x0860, 0x085C, 0x01E8, 0x01E9, 0x01EA),
   },
   {     .channel                = 74,
         .freq                   = 5370, /* MHz */
         .unk2                   = 3580,
-        RADIOREGS(0x71, 0x02, 0x19, 0x08, 0x75, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x19, 0x02, 0x08, 0x75, 0x01, 0x04, 0x0A,
                   0x00, 0x87, 0x44, 0x44, 0x77, 0x00, 0x06, 0x05,
                   0x83, 0x77, 0x00, 0x06, 0x05, 0x83),
-        PHYREGS(0x6808, 0x6408, 0x6008, 0xE701, 0xE801, 0xE901),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01E7, 0x01E8, 0x01E9),
   },
   {     .channel                = 76,
         .freq                   = 5380, /* MHz */
         .unk2                   = 3587,
-        RADIOREGS(0x71, 0x02, 0x1A, 0x08, 0x6E, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x1A, 0x02, 0x08, 0x6E, 0x01, 0x04, 0x0A,
                   0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04,
                   0x82, 0x77, 0x00, 0x06, 0x04, 0x82),
-        PHYREGS(0x6C08, 0x6808, 0x6408, 0xE601, 0xE701, 0xE801),
+        PHYREGS(0x086C, 0x0868, 0x0864, 0x01E6, 0x01E7, 0x01E8),
   },
   {     .channel                = 78,
         .freq                   = 5390, /* MHz */
         .unk2                   = 3593,
-        RADIOREGS(0x71, 0x02, 0x1B, 0x08, 0x6E, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x1B, 0x02, 0x08, 0x6E, 0x01, 0x04, 0x0A,
                   0x00, 0x87, 0x33, 0x33, 0x77, 0x00, 0x06, 0x04,
                   0x82, 0x77, 0x00, 0x06, 0x04, 0x82),
-        PHYREGS(0x7008, 0x6C08, 0x6808, 0xE501, 0xE601, 0xE701),
+        PHYREGS(0x0870, 0x086C, 0x0868, 0x01E5, 0x01E6, 0x01E7),
   },
   {     .channel                = 80,
         .freq                   = 5400, /* MHz */
         .unk2                   = 3600,
-        RADIOREGS(0x71, 0x02, 0x1C, 0x07, 0x67, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x1C, 0x02, 0x07, 0x67, 0x01, 0x04, 0x0A,
                   0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04,
                   0x81, 0x66, 0x00, 0x05, 0x04, 0x81),
-        PHYREGS(0x7408, 0x7008, 0x6C08, 0xE501, 0xE501, 0xE601),
+        PHYREGS(0x0874, 0x0870, 0x086C, 0x01E5, 0x01E5, 0x01E6),
   },
   {     .channel                = 82,
         .freq                   = 5410, /* MHz */
         .unk2                   = 3607,
-        RADIOREGS(0x71, 0x02, 0x1D, 0x07, 0x67, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x1D, 0x02, 0x07, 0x67, 0x01, 0x04, 0x0A,
                   0x00, 0x86, 0x33, 0x33, 0x66, 0x00, 0x05, 0x04,
                   0x81, 0x66, 0x00, 0x05, 0x04, 0x81),
-        PHYREGS(0x7808, 0x7408, 0x7008, 0xE401, 0xE501, 0xE501),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01E4, 0x01E5, 0x01E5),
   },
   {     .channel                = 84,
         .freq                   = 5420, /* MHz */
         .unk2                   = 3613,
-        RADIOREGS(0x71, 0x02, 0x1E, 0x07, 0x61, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x1E, 0x02, 0x07, 0x61, 0x01, 0x04, 0x0A,
                   0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03,
                   0x80, 0x66, 0x00, 0x05, 0x03, 0x80),
-        PHYREGS(0x7C08, 0x7808, 0x7408, 0xE301, 0xE401, 0xE501),
+        PHYREGS(0x087C, 0x0878, 0x0874, 0x01E3, 0x01E4, 0x01E5),
   },
   {     .channel                = 86,
         .freq                   = 5430, /* MHz */
         .unk2                   = 3620,
-        RADIOREGS(0x71, 0x02, 0x1F, 0x07, 0x61, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x1F, 0x02, 0x07, 0x61, 0x01, 0x04, 0x0A,
                   0x00, 0x86, 0x22, 0x22, 0x66, 0x00, 0x05, 0x03,
                   0x80, 0x66, 0x00, 0x05, 0x03, 0x80),
-        PHYREGS(0x8008, 0x7C08, 0x7808, 0xE201, 0xE301, 0xE401),
+        PHYREGS(0x0880, 0x087C, 0x0878, 0x01E2, 0x01E3, 0x01E4),
   },
   {     .channel                = 88,
         .freq                   = 5440, /* MHz */
         .unk2                   = 3627,
-        RADIOREGS(0x71, 0x02, 0x20, 0x07, 0x5A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x20, 0x02, 0x07, 0x5A, 0x01, 0x04, 0x0A,
                   0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02,
                   0x80, 0x55, 0x00, 0x04, 0x02, 0x80),
-        PHYREGS(0x8408, 0x8008, 0x7C08, 0xE101, 0xE201, 0xE301),
+        PHYREGS(0x0884, 0x0880, 0x087C, 0x01E1, 0x01E2, 0x01E3),
   },
   {     .channel                = 90,
         .freq                   = 5450, /* MHz */
         .unk2                   = 3633,
-        RADIOREGS(0x71, 0x02, 0x21, 0x07, 0x5A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x21, 0x02, 0x07, 0x5A, 0x01, 0x04, 0x0A,
                   0x00, 0x85, 0x22, 0x22, 0x55, 0x00, 0x04, 0x02,
                   0x80, 0x55, 0x00, 0x04, 0x02, 0x80),
-        PHYREGS(0x8808, 0x8408, 0x8008, 0xE001, 0xE101, 0xE201),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01E0, 0x01E1, 0x01E2),
   },
   {     .channel                = 92,
         .freq                   = 5460, /* MHz */
         .unk2                   = 3640,
-        RADIOREGS(0x71, 0x02, 0x22, 0x06, 0x53, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x22, 0x02, 0x06, 0x53, 0x01, 0x04, 0x0A,
                   0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01,
                   0x80, 0x55, 0x00, 0x04, 0x01, 0x80),
-        PHYREGS(0x8C08, 0x8808, 0x8408, 0xDF01, 0xE001, 0xE101),
+        PHYREGS(0x088C, 0x0888, 0x0884, 0x01DF, 0x01E0, 0x01E1),
   },
   {     .channel                = 94,
         .freq                   = 5470, /* MHz */
         .unk2                   = 3647,
-        RADIOREGS(0x71, 0x02, 0x23, 0x06, 0x53, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x23, 0x02, 0x06, 0x53, 0x01, 0x04, 0x0A,
                   0x00, 0x85, 0x11, 0x11, 0x55, 0x00, 0x04, 0x01,
                   0x80, 0x55, 0x00, 0x04, 0x01, 0x80),
-        PHYREGS(0x9008, 0x8C08, 0x8808, 0xDE01, 0xDF01, 0xE001),
+        PHYREGS(0x0890, 0x088C, 0x0888, 0x01DE, 0x01DF, 0x01E0),
   },
   {     .channel                = 96,
         .freq                   = 5480, /* MHz */
         .unk2                   = 3653,
-        RADIOREGS(0x71, 0x02, 0x24, 0x06, 0x4D, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x24, 0x02, 0x06, 0x4D, 0x01, 0x04, 0x0A,
                   0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00,
                   0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
-        PHYREGS(0x9408, 0x9008, 0x8C08, 0xDD01, 0xDE01, 0xDF01),
+        PHYREGS(0x0894, 0x0890, 0x088C, 0x01DD, 0x01DE, 0x01DF),
   },
   {     .channel                = 98,
         .freq                   = 5490, /* MHz */
         .unk2                   = 3660,
-        RADIOREGS(0x71, 0x02, 0x25, 0x06, 0x4D, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x25, 0x02, 0x06, 0x4D, 0x01, 0x04, 0x0A,
                   0x00, 0x84, 0x11, 0x11, 0x44, 0x00, 0x03, 0x00,
                   0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
-        PHYREGS(0x9808, 0x9408, 0x9008, 0xDD01, 0xDD01, 0xDE01),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01DD, 0x01DD, 0x01DE),
   },
   {     .channel                = 100,
         .freq                   = 5500, /* MHz */
         .unk2                   = 3667,
-        RADIOREGS(0x71, 0x02, 0x26, 0x06, 0x47, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x26, 0x02, 0x06, 0x47, 0x01, 0x04, 0x0A,
                   0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00,
                   0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
-        PHYREGS(0x9C08, 0x9808, 0x9408, 0xDC01, 0xDD01, 0xDD01),
+        PHYREGS(0x089C, 0x0898, 0x0894, 0x01DC, 0x01DD, 0x01DD),
   },
   {     .channel                = 102,
         .freq                   = 5510, /* MHz */
         .unk2                   = 3673,
-        RADIOREGS(0x71, 0x02, 0x27, 0x06, 0x47, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x27, 0x02, 0x06, 0x47, 0x01, 0x04, 0x0A,
                   0x00, 0x84, 0x00, 0x00, 0x44, 0x00, 0x03, 0x00,
                   0x80, 0x44, 0x00, 0x03, 0x00, 0x80),
-        PHYREGS(0xA008, 0x9C08, 0x9808, 0xDB01, 0xDC01, 0xDD01),
+        PHYREGS(0x08A0, 0x089C, 0x0898, 0x01DB, 0x01DC, 0x01DD),
   },
   {     .channel                = 104,
         .freq                   = 5520, /* MHz */
         .unk2                   = 3680,
-        RADIOREGS(0x71, 0x02, 0x28, 0x05, 0x40, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x28, 0x02, 0x05, 0x40, 0x01, 0x04, 0x0A,
                   0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
                   0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
-        PHYREGS(0xA408, 0xA008, 0x9C08, 0xDA01, 0xDB01, 0xDC01),
+        PHYREGS(0x08A4, 0x08A0, 0x089C, 0x01DA, 0x01DB, 0x01DC),
   },
   {     .channel                = 106,
         .freq                   = 5530, /* MHz */
         .unk2                   = 3687,
-        RADIOREGS(0x71, 0x02, 0x29, 0x05, 0x40, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x29, 0x02, 0x05, 0x40, 0x01, 0x04, 0x0A,
                   0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
                   0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
-        PHYREGS(0xA808, 0xA408, 0xA008, 0xD901, 0xDA01, 0xDB01),
+        PHYREGS(0x08A8, 0x08A4, 0x08A0, 0x01D9, 0x01DA, 0x01DB),
   },
   {     .channel                = 108,
         .freq                   = 5540, /* MHz */
         .unk2                   = 3693,
-        RADIOREGS(0x71, 0x02, 0x2A, 0x05, 0x3A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x2A, 0x02, 0x05, 0x3A, 0x01, 0x04, 0x0A,
                   0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
                   0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
-        PHYREGS(0xAC08, 0xA808, 0xA408, 0xD801, 0xD901, 0xDA01),
+        PHYREGS(0x08AC, 0x08A8, 0x08A4, 0x01D8, 0x01D9, 0x01DA),
   },
   {     .channel                = 110,
         .freq                   = 5550, /* MHz */
         .unk2                   = 3700,
-        RADIOREGS(0x71, 0x02, 0x2B, 0x05, 0x3A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x2B, 0x02, 0x05, 0x3A, 0x01, 0x04, 0x0A,
                   0x00, 0x83, 0x00, 0x00, 0x33, 0x00, 0x02, 0x00,
                   0x80, 0x33, 0x00, 0x02, 0x00, 0x80),
-        PHYREGS(0xB008, 0xAC08, 0xA808, 0xD701, 0xD801, 0xD901),
+        PHYREGS(0x08B0, 0x08AC, 0x08A8, 0x01D7, 0x01D8, 0x01D9),
   },
   {     .channel                = 112,
         .freq                   = 5560, /* MHz */
         .unk2                   = 3707,
-        RADIOREGS(0x71, 0x02, 0x2C, 0x05, 0x34, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x2C, 0x02, 0x05, 0x34, 0x01, 0x04, 0x0A,
                   0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
                   0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
-        PHYREGS(0xB408, 0xB008, 0xAC08, 0xD701, 0xD701, 0xD801),
+        PHYREGS(0x08B4, 0x08B0, 0x08AC, 0x01D7, 0x01D7, 0x01D8),
   },
   {     .channel                = 114,
         .freq                   = 5570, /* MHz */
         .unk2                   = 3713,
-        RADIOREGS(0x71, 0x02, 0x2D, 0x05, 0x34, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x2D, 0x02, 0x05, 0x34, 0x01, 0x04, 0x0A,
                   0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
                   0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
-        PHYREGS(0xB808, 0xB408, 0xB008, 0xD601, 0xD701, 0xD701),
+        PHYREGS(0x08B8, 0x08B4, 0x08B0, 0x01D6, 0x01D7, 0x01D7),
   },
   {     .channel                = 116,
         .freq                   = 5580, /* MHz */
         .unk2                   = 3720,
-        RADIOREGS(0x71, 0x02, 0x2E, 0x04, 0x2E, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x2E, 0x02, 0x04, 0x2E, 0x01, 0x04, 0x0A,
                   0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
                   0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
-        PHYREGS(0xBC08, 0xB808, 0xB408, 0xD501, 0xD601, 0xD701),
+        PHYREGS(0x08BC, 0x08B8, 0x08B4, 0x01D5, 0x01D6, 0x01D7),
   },
   {     .channel                = 118,
         .freq                   = 5590, /* MHz */
         .unk2                   = 3727,
-        RADIOREGS(0x71, 0x02, 0x2F, 0x04, 0x2E, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x2F, 0x02, 0x04, 0x2E, 0x01, 0x04, 0x0A,
                   0x00, 0x82, 0x00, 0x00, 0x22, 0x00, 0x01, 0x00,
                   0x80, 0x22, 0x00, 0x01, 0x00, 0x80),
-        PHYREGS(0xC008, 0xBC08, 0xB808, 0xD401, 0xD501, 0xD601),
+        PHYREGS(0x08C0, 0x08BC, 0x08B8, 0x01D4, 0x01D5, 0x01D6),
   },
   {     .channel                = 120,
         .freq                   = 5600, /* MHz */
         .unk2                   = 3733,
-        RADIOREGS(0x71, 0x02, 0x30, 0x04, 0x28, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x30, 0x02, 0x04, 0x28, 0x01, 0x04, 0x0A,
                   0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00,
                   0x80, 0x11, 0x00, 0x01, 0x00, 0x80),
-        PHYREGS(0xC408, 0xC008, 0xBC08, 0xD301, 0xD401, 0xD501),
+        PHYREGS(0x08C4, 0x08C0, 0x08BC, 0x01D3, 0x01D4, 0x01D5),
   },
   {     .channel                = 122,
         .freq                   = 5610, /* MHz */
         .unk2                   = 3740,
-        RADIOREGS(0x71, 0x02, 0x31, 0x04, 0x28, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x31, 0x02, 0x04, 0x28, 0x01, 0x04, 0x0A,
                   0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x01, 0x00,
                   0x80, 0x11, 0x00, 0x01, 0x00, 0x80),
-        PHYREGS(0xC808, 0xC408, 0xC008, 0xD201, 0xD301, 0xD401),
+        PHYREGS(0x08C8, 0x08C4, 0x08C0, 0x01D2, 0x01D3, 0x01D4),
   },
   {     .channel                = 124,
         .freq                   = 5620, /* MHz */
         .unk2                   = 3747,
-        RADIOREGS(0x71, 0x02, 0x32, 0x04, 0x21, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x32, 0x02, 0x04, 0x21, 0x01, 0x04, 0x0A,
                   0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00,
                   0x80, 0x11, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xCC08, 0xC808, 0xC408, 0xD201, 0xD201, 0xD301),
+        PHYREGS(0x08CC, 0x08C8, 0x08C4, 0x01D2, 0x01D2, 0x01D3),
   },
   {     .channel                = 126,
         .freq                   = 5630, /* MHz */
         .unk2                   = 3753,
-        RADIOREGS(0x71, 0x02, 0x33, 0x04, 0x21, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x33, 0x02, 0x04, 0x21, 0x01, 0x04, 0x0A,
                   0x00, 0x81, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00,
                   0x80, 0x11, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xD008, 0xCC08, 0xC808, 0xD101, 0xD201, 0xD201),
+        PHYREGS(0x08D0, 0x08CC, 0x08C8, 0x01D1, 0x01D2, 0x01D2),
   },
   {     .channel                = 128,
         .freq                   = 5640, /* MHz */
         .unk2                   = 3760,
-        RADIOREGS(0x71, 0x02, 0x34, 0x03, 0x1C, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x34, 0x02, 0x03, 0x1C, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xD408, 0xD008, 0xCC08, 0xD001, 0xD101, 0xD201),
+        PHYREGS(0x08D4, 0x08D0, 0x08CC, 0x01D0, 0x01D1, 0x01D2),
   },
   {     .channel                = 130,
         .freq                   = 5650, /* MHz */
         .unk2                   = 3767,
-        RADIOREGS(0x71, 0x02, 0x35, 0x03, 0x1C, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x35, 0x02, 0x03, 0x1C, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xD808, 0xD408, 0xD008, 0xCF01, 0xD001, 0xD101),
+        PHYREGS(0x08D8, 0x08D4, 0x08D0, 0x01CF, 0x01D0, 0x01D1),
   },
   {     .channel                = 132,
         .freq                   = 5660, /* MHz */
         .unk2                   = 3773,
-        RADIOREGS(0x71, 0x02, 0x36, 0x03, 0x16, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x36, 0x02, 0x03, 0x16, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xDC08, 0xD808, 0xD408, 0xCE01, 0xCF01, 0xD001),
+        PHYREGS(0x08DC, 0x08D8, 0x08D4, 0x01CE, 0x01CF, 0x01D0),
   },
   {     .channel                = 134,
         .freq                   = 5670, /* MHz */
         .unk2                   = 3780,
-        RADIOREGS(0x71, 0x02, 0x37, 0x03, 0x16, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x37, 0x02, 0x03, 0x16, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xE008, 0xDC08, 0xD808, 0xCE01, 0xCE01, 0xCF01),
+        PHYREGS(0x08E0, 0x08DC, 0x08D8, 0x01CE, 0x01CE, 0x01CF),
   },
   {     .channel                = 136,
         .freq                   = 5680, /* MHz */
         .unk2                   = 3787,
-        RADIOREGS(0x71, 0x02, 0x38, 0x03, 0x10, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x38, 0x02, 0x03, 0x10, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xE408, 0xE008, 0xDC08, 0xCD01, 0xCE01, 0xCE01),
+        PHYREGS(0x08E4, 0x08E0, 0x08DC, 0x01CD, 0x01CE, 0x01CE),
   },
   {     .channel                = 138,
         .freq                   = 5690, /* MHz */
         .unk2                   = 3793,
-        RADIOREGS(0x71, 0x02, 0x39, 0x03, 0x10, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x39, 0x02, 0x03, 0x10, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xE808, 0xE408, 0xE008, 0xCC01, 0xCD01, 0xCE01),
+        PHYREGS(0x08E8, 0x08E4, 0x08E0, 0x01CC, 0x01CD, 0x01CE),
   },
   {     .channel                = 140,
         .freq                   = 5700, /* MHz */
         .unk2                   = 3800,
-        RADIOREGS(0x71, 0x02, 0x3A, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x3A, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xEC08, 0xE808, 0xE408, 0xCB01, 0xCC01, 0xCD01),
+        PHYREGS(0x08EC, 0x08E8, 0x08E4, 0x01CB, 0x01CC, 0x01CD),
   },
   {     .channel                = 142,
         .freq                   = 5710, /* MHz */
         .unk2                   = 3807,
-        RADIOREGS(0x71, 0x02, 0x3B, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x3B, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xF008, 0xEC08, 0xE808, 0xCA01, 0xCB01, 0xCC01),
+        PHYREGS(0x08F0, 0x08EC, 0x08E8, 0x01CA, 0x01CB, 0x01CC),
   },
   {     .channel                = 144,
         .freq                   = 5720, /* MHz */
         .unk2                   = 3813,
-        RADIOREGS(0x71, 0x02, 0x3C, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x3C, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xF408, 0xF008, 0xEC08, 0xC901, 0xCA01, 0xCB01),
+        PHYREGS(0x08F4, 0x08F0, 0x08EC, 0x01C9, 0x01CA, 0x01CB),
   },
   {     .channel                = 145,
         .freq                   = 5725, /* MHz */
         .unk2                   = 3817,
-        RADIOREGS(0x72, 0x04, 0x79, 0x02, 0x03, 0x01, 0x03, 0x14,
+        RADIOREGS(0x72, 0x79, 0x04, 0x02, 0x03, 0x01, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xF608, 0xF208, 0xEE08, 0xC901, 0xCA01, 0xCB01),
+        PHYREGS(0x08F6, 0x08F2, 0x08EE, 0x01C9, 0x01CA, 0x01CB),
   },
   {     .channel                = 146,
         .freq                   = 5730, /* MHz */
         .unk2                   = 3820,
-        RADIOREGS(0x71, 0x02, 0x3D, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x3D, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xF808, 0xF408, 0xF008, 0xC901, 0xC901, 0xCA01),
+        PHYREGS(0x08F8, 0x08F4, 0x08F0, 0x01C9, 0x01C9, 0x01CA),
   },
   {     .channel                = 147,
         .freq                   = 5735, /* MHz */
         .unk2                   = 3823,
-        RADIOREGS(0x72, 0x04, 0x7B, 0x02, 0x03, 0x01, 0x03, 0x14,
+        RADIOREGS(0x72, 0x7B, 0x04, 0x02, 0x03, 0x01, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xFA08, 0xF608, 0xF208, 0xC801, 0xC901, 0xCA01),
+        PHYREGS(0x08FA, 0x08F6, 0x08F2, 0x01C8, 0x01C9, 0x01CA),
   },
   {     .channel                = 148,
         .freq                   = 5740, /* MHz */
         .unk2                   = 3827,
-        RADIOREGS(0x71, 0x02, 0x3E, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x3E, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xFC08, 0xF808, 0xF408, 0xC801, 0xC901, 0xC901),
+        PHYREGS(0x08FC, 0x08F8, 0x08F4, 0x01C8, 0x01C9, 0x01C9),
   },
   {     .channel                = 149,
         .freq                   = 5745, /* MHz */
         .unk2                   = 3830,
-        RADIOREGS(0x72, 0x04, 0x7D, 0x02, 0xFE, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x7D, 0x04, 0x02, 0xFE, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0xFE08, 0xFA08, 0xF608, 0xC801, 0xC801, 0xC901),
+        PHYREGS(0x08FE, 0x08FA, 0x08F6, 0x01C8, 0x01C8, 0x01C9),
   },
   {     .channel                = 150,
         .freq                   = 5750, /* MHz */
         .unk2                   = 3833,
-        RADIOREGS(0x71, 0x02, 0x3F, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x3F, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0009, 0xFC08, 0xF808, 0xC701, 0xC801, 0xC901),
+        PHYREGS(0x0900, 0x08FC, 0x08F8, 0x01C7, 0x01C8, 0x01C9),
   },
   {     .channel                = 151,
         .freq                   = 5755, /* MHz */
         .unk2                   = 3837,
-        RADIOREGS(0x72, 0x04, 0x7F, 0x02, 0xFE, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x7F, 0x04, 0x02, 0xFE, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0209, 0xFE08, 0xFA08, 0xC701, 0xC801, 0xC801),
+        PHYREGS(0x0902, 0x08FE, 0x08FA, 0x01C7, 0x01C8, 0x01C8),
   },
   {     .channel                = 152,
         .freq                   = 5760, /* MHz */
         .unk2                   = 3840,
-        RADIOREGS(0x71, 0x02, 0x40, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x40, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0409, 0x0009, 0xFC08, 0xC601, 0xC701, 0xC801),
+        PHYREGS(0x0904, 0x0900, 0x08FC, 0x01C6, 0x01C7, 0x01C8),
   },
   {     .channel                = 153,
         .freq                   = 5765, /* MHz */
         .unk2                   = 3843,
-        RADIOREGS(0x72, 0x04, 0x81, 0x02, 0xF8, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x81, 0x04, 0x02, 0xF8, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0609, 0x0209, 0xFE08, 0xC601, 0xC701, 0xC801),
+        PHYREGS(0x0906, 0x0902, 0x08FE, 0x01C6, 0x01C7, 0x01C8),
   },
   {     .channel                = 154,
         .freq                   = 5770, /* MHz */
         .unk2                   = 3847,
-        RADIOREGS(0x71, 0x02, 0x41, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x41, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0809, 0x0409, 0x0009, 0xC601, 0xC601, 0xC701),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01C6, 0x01C6, 0x01C7),
   },
   {     .channel                = 155,
         .freq                   = 5775, /* MHz */
         .unk2                   = 3850,
-        RADIOREGS(0x72, 0x04, 0x83, 0x02, 0xF8, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x83, 0x04, 0x02, 0xF8, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0A09, 0x0609, 0x0209, 0xC501, 0xC601, 0xC701),
+        PHYREGS(0x090A, 0x0906, 0x0902, 0x01C5, 0x01C6, 0x01C7),
   },
   {     .channel                = 156,
         .freq                   = 5780, /* MHz */
         .unk2                   = 3853,
-        RADIOREGS(0x71, 0x02, 0x42, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x42, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0C09, 0x0809, 0x0409, 0xC501, 0xC601, 0xC601),
+        PHYREGS(0x090C, 0x0908, 0x0904, 0x01C5, 0x01C6, 0x01C6),
   },
   {     .channel                = 157,
         .freq                   = 5785, /* MHz */
         .unk2                   = 3857,
-        RADIOREGS(0x72, 0x04, 0x85, 0x02, 0xF2, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x85, 0x04, 0x02, 0xF2, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x0E09, 0x0A09, 0x0609, 0xC401, 0xC501, 0xC601),
+        PHYREGS(0x090E, 0x090A, 0x0906, 0x01C4, 0x01C5, 0x01C6),
   },
   {     .channel                = 158,
         .freq                   = 5790, /* MHz */
         .unk2                   = 3860,
-        RADIOREGS(0x71, 0x02, 0x43, 0x02, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x43, 0x02, 0x02, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1009, 0x0C09, 0x0809, 0xC401, 0xC501, 0xC601),
+        PHYREGS(0x0910, 0x090C, 0x0908, 0x01C4, 0x01C5, 0x01C6),
   },
   {     .channel                = 159,
         .freq                   = 5795, /* MHz */
         .unk2                   = 3863,
-        RADIOREGS(0x72, 0x04, 0x87, 0x02, 0xF2, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x87, 0x04, 0x02, 0xF2, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1209, 0x0E09, 0x0A09, 0xC401, 0xC401, 0xC501),
+        PHYREGS(0x0912, 0x090E, 0x090A, 0x01C4, 0x01C4, 0x01C5),
   },
   {     .channel                = 160,
         .freq                   = 5800, /* MHz */
         .unk2                   = 3867,
-        RADIOREGS(0x71, 0x02, 0x44, 0x01, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x44, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1409, 0x1009, 0x0C09, 0xC301, 0xC401, 0xC501),
+        PHYREGS(0x0914, 0x0910, 0x090C, 0x01C3, 0x01C4, 0x01C5),
   },
   {     .channel                = 161,
         .freq                   = 5805, /* MHz */
         .unk2                   = 3870,
-        RADIOREGS(0x72, 0x04, 0x89, 0x01, 0xED, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x89, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1609, 0x1209, 0x0E09, 0xC301, 0xC401, 0xC401),
+        PHYREGS(0x0916, 0x0912, 0x090E, 0x01C3, 0x01C4, 0x01C4),
   },
   {     .channel                = 162,
         .freq                   = 5810, /* MHz */
         .unk2                   = 3873,
-        RADIOREGS(0x71, 0x02, 0x45, 0x01, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x45, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1809, 0x1409, 0x1009, 0xC201, 0xC301, 0xC401),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01C2, 0x01C3, 0x01C4),
   },
   {     .channel                = 163,
         .freq                   = 5815, /* MHz */
         .unk2                   = 3877,
-        RADIOREGS(0x72, 0x04, 0x8B, 0x01, 0xED, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x8B, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1A09, 0x1609, 0x1209, 0xC201, 0xC301, 0xC401),
+        PHYREGS(0x091A, 0x0916, 0x0912, 0x01C2, 0x01C3, 0x01C4),
   },
   {     .channel                = 164,
         .freq                   = 5820, /* MHz */
         .unk2                   = 3880,
-        RADIOREGS(0x71, 0x02, 0x46, 0x01, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x46, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1C09, 0x1809, 0x1409, 0xC201, 0xC201, 0xC301),
+        PHYREGS(0x091C, 0x0918, 0x0914, 0x01C2, 0x01C2, 0x01C3),
   },
   {     .channel                = 165,
         .freq                   = 5825, /* MHz */
         .unk2                   = 3883,
-        RADIOREGS(0x72, 0x04, 0x8D, 0x01, 0xED, 0x00, 0x03, 0x14,
+        RADIOREGS(0x72, 0x8D, 0x04, 0x01, 0xED, 0x00, 0x03, 0x14,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x1E09, 0x1A09, 0x1609, 0xC101, 0xC201, 0xC301),
+        PHYREGS(0x091E, 0x091A, 0x0916, 0x01C1, 0x01C2, 0x01C3),
   },
   {     .channel                = 166,
         .freq                   = 5830, /* MHz */
         .unk2                   = 3887,
-        RADIOREGS(0x71, 0x02, 0x47, 0x01, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x47, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x2009, 0x1C09, 0x1809, 0xC101, 0xC201, 0xC201),
+        PHYREGS(0x0920, 0x091C, 0x0918, 0x01C1, 0x01C2, 0x01C2),
   },
   {     .channel                = 168,
         .freq                   = 5840, /* MHz */
         .unk2                   = 3893,
-        RADIOREGS(0x71, 0x02, 0x48, 0x01, 0x0A, 0x01, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x48, 0x02, 0x01, 0x0A, 0x01, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x2409, 0x2009, 0x1C09, 0xC001, 0xC101, 0xC201),
+        PHYREGS(0x0924, 0x0920, 0x091C, 0x01C0, 0x01C1, 0x01C2),
   },
   {     .channel                = 170,
         .freq                   = 5850, /* MHz */
         .unk2                   = 3900,
-        RADIOREGS(0x71, 0x02, 0x49, 0x01, 0xE0, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x49, 0x02, 0x01, 0xE0, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x2809, 0x2409, 0x2009, 0xBF01, 0xC001, 0xC101),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01BF, 0x01C0, 0x01C1),
   },
   {     .channel                = 172,
         .freq                   = 5860, /* MHz */
         .unk2                   = 3907,
-        RADIOREGS(0x71, 0x02, 0x4A, 0x01, 0xDE, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x4A, 0x02, 0x01, 0xDE, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x2C09, 0x2809, 0x2409, 0xBF01, 0xBF01, 0xC001),
+        PHYREGS(0x092C, 0x0928, 0x0924, 0x01BF, 0x01BF, 0x01C0),
   },
   {     .channel                = 174,
         .freq                   = 5870, /* MHz */
         .unk2                   = 3913,
-        RADIOREGS(0x71, 0x02, 0x4B, 0x00, 0xDB, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x4B, 0x02, 0x00, 0xDB, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x3009, 0x2C09, 0x2809, 0xBE01, 0xBF01, 0xBF01),
+        PHYREGS(0x0930, 0x092C, 0x0928, 0x01BE, 0x01BF, 0x01BF),
   },
   {     .channel                = 176,
         .freq                   = 5880, /* MHz */
         .unk2                   = 3920,
-        RADIOREGS(0x71, 0x02, 0x4C, 0x00, 0xD8, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x4C, 0x02, 0x00, 0xD8, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x3409, 0x3009, 0x2C09, 0xBD01, 0xBE01, 0xBF01),
+        PHYREGS(0x0934, 0x0930, 0x092C, 0x01BD, 0x01BE, 0x01BF),
   },
   {     .channel                = 178,
         .freq                   = 5890, /* MHz */
         .unk2                   = 3927,
-        RADIOREGS(0x71, 0x02, 0x4D, 0x00, 0xD6, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x4D, 0x02, 0x00, 0xD6, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x3809, 0x3409, 0x3009, 0xBC01, 0xBD01, 0xBE01),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01BC, 0x01BD, 0x01BE),
   },
   {     .channel                = 180,
         .freq                   = 5900, /* MHz */
         .unk2                   = 3933,
-        RADIOREGS(0x71, 0x02, 0x4E, 0x00, 0xD3, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x4E, 0x02, 0x00, 0xD3, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x3C09, 0x3809, 0x3409, 0xBC01, 0xBC01, 0xBD01),
+        PHYREGS(0x093C, 0x0938, 0x0934, 0x01BC, 0x01BC, 0x01BD),
   },
   {     .channel                = 182,
         .freq                   = 5910, /* MHz */
         .unk2                   = 3940,
-        RADIOREGS(0x71, 0x02, 0x4F, 0x00, 0xD6, 0x00, 0x04, 0x0A,
+        RADIOREGS(0x71, 0x4F, 0x02, 0x00, 0xD6, 0x00, 0x04, 0x0A,
                   0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                   0x80, 0x00, 0x00, 0x00, 0x00, 0x80),
-        PHYREGS(0x4009, 0x3C09, 0x3809, 0xBB01, 0xBC01, 0xBC01),
+        PHYREGS(0x0940, 0x093C, 0x0938, 0x01BB, 0x01BC, 0x01BC),
   },
   {     .channel                = 1,
         .freq                   = 2412, /* MHz */
         .unk2                   = 3216,
-        RADIOREGS(0x73, 0x09, 0x6C, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x6C, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0D, 0x0C,
                   0x80, 0xFF, 0x88, 0x0D, 0x0C, 0x80),
-        PHYREGS(0xC903, 0xC503, 0xC103, 0x3A04, 0x3F04, 0x4304),
+        PHYREGS(0x03C9, 0x03C5, 0x03C1, 0x043A, 0x043F, 0x0443),
   },
   {     .channel                = 2,
         .freq                   = 2417, /* MHz */
         .unk2                   = 3223,
-        RADIOREGS(0x73, 0x09, 0x71, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x71, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0B,
                   0x80, 0xFF, 0x88, 0x0C, 0x0B, 0x80),
-        PHYREGS(0xCB03, 0xC703, 0xC303, 0x3804, 0x3D04, 0x4104),
+        PHYREGS(0x03CB, 0x03C7, 0x03C3, 0x0438, 0x043D, 0x0441),
   },
   {     .channel                = 3,
         .freq                   = 2422, /* MHz */
         .unk2                   = 3229,
-        RADIOREGS(0x73, 0x09, 0x76, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x76, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A,
                   0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80),
-        PHYREGS(0xCD03, 0xC903, 0xC503, 0x3604, 0x3A04, 0x3F04),
+        PHYREGS(0x03CD, 0x03C9, 0x03C5, 0x0436, 0x043A, 0x043F),
   },
   {     .channel                = 4,
         .freq                   = 2427, /* MHz */
         .unk2                   = 3236,
-        RADIOREGS(0x73, 0x09, 0x7B, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x7B, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x0A,
                   0x80, 0xFF, 0x88, 0x0C, 0x0A, 0x80),
-        PHYREGS(0xCF03, 0xCB03, 0xC703, 0x3404, 0x3804, 0x3D04),
+        PHYREGS(0x03CF, 0x03CB, 0x03C7, 0x0434, 0x0438, 0x043D),
   },
   {     .channel                = 5,
         .freq                   = 2432, /* MHz */
         .unk2                   = 3243,
-        RADIOREGS(0x73, 0x09, 0x80, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x80, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0C, 0x09,
                   0x80, 0xFF, 0x88, 0x0C, 0x09, 0x80),
-        PHYREGS(0xD103, 0xCD03, 0xC903, 0x3104, 0x3604, 0x3A04),
+        PHYREGS(0x03D1, 0x03CD, 0x03C9, 0x0431, 0x0436, 0x043A),
   },
   {     .channel                = 6,
         .freq                   = 2437, /* MHz */
         .unk2                   = 3249,
-        RADIOREGS(0x73, 0x09, 0x85, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x85, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0B, 0x08,
                   0x80, 0xFF, 0x88, 0x0B, 0x08, 0x80),
-        PHYREGS(0xD303, 0xCF03, 0xCB03, 0x2F04, 0x3404, 0x3804),
+        PHYREGS(0x03D3, 0x03CF, 0x03CB, 0x042F, 0x0434, 0x0438),
   },
   {     .channel                = 7,
         .freq                   = 2442, /* MHz */
         .unk2                   = 3256,
-        RADIOREGS(0x73, 0x09, 0x8A, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x8A, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x07,
                   0x80, 0xFF, 0x88, 0x0A, 0x07, 0x80),
-        PHYREGS(0xD503, 0xD103, 0xCD03, 0x2D04, 0x3104, 0x3604),
+        PHYREGS(0x03D5, 0x03D1, 0x03CD, 0x042D, 0x0431, 0x0436),
   },
   {     .channel                = 8,
         .freq                   = 2447, /* MHz */
         .unk2                   = 3263,
-        RADIOREGS(0x73, 0x09, 0x8F, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x8F, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x0A, 0x06,
                   0x80, 0xFF, 0x88, 0x0A, 0x06, 0x80),
-        PHYREGS(0xD703, 0xD303, 0xCF03, 0x2B04, 0x2F04, 0x3404),
+        PHYREGS(0x03D7, 0x03D3, 0x03CF, 0x042B, 0x042F, 0x0434),
   },
   {     .channel                = 9,
         .freq                   = 2452, /* MHz */
         .unk2                   = 3269,
-        RADIOREGS(0x73, 0x09, 0x94, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x94, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x09, 0x06,
                   0x80, 0xFF, 0x88, 0x09, 0x06, 0x80),
-        PHYREGS(0xD903, 0xD503, 0xD103, 0x2904, 0x2D04, 0x3104),
+        PHYREGS(0x03D9, 0x03D5, 0x03D1, 0x0429, 0x042D, 0x0431),
   },
   {     .channel                = 10,
         .freq                   = 2457, /* MHz */
         .unk2                   = 3276,
-        RADIOREGS(0x73, 0x09, 0x99, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x99, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x05,
                   0x80, 0xFF, 0x88, 0x08, 0x05, 0x80),
-        PHYREGS(0xDB03, 0xD703, 0xD303, 0x2704, 0x2B04, 0x2F04),
+        PHYREGS(0x03DB, 0x03D7, 0x03D3, 0x0427, 0x042B, 0x042F),
   },
   {     .channel                = 11,
         .freq                   = 2462, /* MHz */
         .unk2                   = 3283,
-        RADIOREGS(0x73, 0x09, 0x9E, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0x9E, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x04,
                   0x80, 0xFF, 0x88, 0x08, 0x04, 0x80),
-        PHYREGS(0xDD03, 0xD903, 0xD503, 0x2404, 0x2904, 0x2D04),
+        PHYREGS(0x03DD, 0x03D9, 0x03D5, 0x0424, 0x0429, 0x042D),
   },
   {     .channel                = 12,
         .freq                   = 2467, /* MHz */
         .unk2                   = 3289,
-        RADIOREGS(0x73, 0x09, 0xA3, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0xA3, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x08, 0x03,
                   0x80, 0xFF, 0x88, 0x08, 0x03, 0x80),
-        PHYREGS(0xDF03, 0xDB03, 0xD703, 0x2204, 0x2704, 0x2B04),
+        PHYREGS(0x03DF, 0x03DB, 0x03D7, 0x0422, 0x0427, 0x042B),
   },
   {     .channel                = 13,
         .freq                   = 2472, /* MHz */
         .unk2                   = 3296,
-        RADIOREGS(0x73, 0x09, 0xA8, 0x0F, 0x00, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0xA8, 0x09, 0x0F, 0x00, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x03,
                   0x80, 0xFF, 0x88, 0x07, 0x03, 0x80),
-        PHYREGS(0xE103, 0xDD03, 0xD903, 0x2004, 0x2404, 0x2904),
+        PHYREGS(0x03E1, 0x03DD, 0x03D9, 0x0420, 0x0424, 0x0429),
   },
   {     .channel                = 14,
         .freq                   = 2484, /* MHz */
         .unk2                   = 3312,
-        RADIOREGS(0x73, 0x09, 0xB4, 0x0F, 0xFF, 0x01, 0x07, 0x15,
+        RADIOREGS(0x73, 0xB4, 0x09, 0x0F, 0xFF, 0x01, 0x07, 0x15,
                   0x01, 0x8F, 0xFF, 0xFF, 0xFF, 0x88, 0x07, 0x01,
                   0x80, 0xFF, 0x88, 0x07, 0x01, 0x80),
-        PHYREGS(0xE603, 0xE203, 0xDE03, 0x1B04, 0x1F04, 0x2404),
+        PHYREGS(0x03E6, 0x03E2, 0x03DE, 0x041B, 0x041F, 0x0424),
   },
 };
 
@@ -1299,7 +1299,7 @@ void b2055_upload_inittab(struct b43_wldev *dev,
                           bool ghz5, bool ignore_uploadflag)
 {
         const struct b2055_inittab_entry *e;
-        unsigned int i;
+        unsigned int i, writes = 0;
         u16 value;
 
         for (i = 0; i < ARRAY_SIZE(b2055_inittab); i++) {
@@ -1312,6 +1312,8 @@ void b2055_upload_inittab(struct b43_wldev *dev,
                         else
                                 value = e->ghz2;
                         b43_radio_write16(dev, i, value);
+                        if (++writes % 4 == 0)
+                                b43_read32(dev, B43_MMIO_MACCTL); /* flush */
                 }
         }
 }
diff --git a/drivers/net/wireless/b43/radio_2056.c b/drivers/net/wireless/b43/radio_2056.c
index d8563192ce56..8890df067029 100644
--- a/drivers/net/wireless/b43/radio_2056.c
+++ b/drivers/net/wireless/b43/radio_2056.c
@@ -24,17 +24,9073 @@
 #include "radio_2056.h"
 #include "phy_common.h"
 
+struct b2056_inittab_entry {
+        /* Value to write if we use the 5GHz band. */
+        u16 ghz5;
+        /* Value to write if we use the 2.4GHz band. */
+        u16 ghz2;
+        /* Flags */
+        u8 flags;
+};
+#define B2056_INITTAB_ENTRY_OK  0x01
+#define B2056_INITTAB_UPLOAD    0x02
+#define UPLOAD          .flags = B2056_INITTAB_ENTRY_OK | B2056_INITTAB_UPLOAD
+#define NOUPLOAD        .flags = B2056_INITTAB_ENTRY_OK
+
+struct b2056_inittabs_pts {
+        const struct b2056_inittab_entry *syn;
+        unsigned int syn_length;
+        const struct b2056_inittab_entry *tx;
+        unsigned int tx_length;
+        const struct b2056_inittab_entry *rx;
+        unsigned int rx_length;
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev3_syn[] = {
+        [B2056_SYN_RESERVED_ADDR2]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR3]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR4]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR5]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR6]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR7]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_CTRL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_PU]              = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_COM_OVR]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RESET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RCAL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_TXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXHPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR16]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR17]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR18]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR19]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR20]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR21]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR22]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR23]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR24]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR25]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR26]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR27]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR28]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR29]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR30]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR31]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER1]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER2]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_MASTER]      = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_RCAL]        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_AFEREG]              = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSE]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSEIDAC]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSERCAL]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LPO]                 = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_MASTER]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_IDAC]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_STATUS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_CODE_OUT]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL0]         = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL1]         = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL2]         = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL3]         = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL4]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL5]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL6]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL7]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL8]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL9]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL11]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST1]           = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST2]           = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST3]           = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
+        [B2056_SYN_PLL_BIAS_RESET]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL1]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL3]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL5]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL6]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_REFDIV]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_PFD]             = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_CP1]             = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_CP2]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_SYN_PLL_CP3]             = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER1]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER2]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER3]     = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER4]     = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER5]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD1]            = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD2]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO1]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO2]            = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, },
+        [B2056_SYN_PLL_MONITOR1]        = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, },
+        [B2056_SYN_PLL_MONITOR2]        = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL4]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL5]         = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL6]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL7]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL8]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL9]         = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL11]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL12]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_SYN_PLL_VCOCAL13]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_SYN_PLL_VREG]            = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS3]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU2]           = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU8]           = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BIAS_RESET]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RCCR1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF1]       = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER1]        = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER2]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF1]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGENBUF2]           = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, },
+        [B2056_SYN_LOGEN_BUF3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF4]          = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV1]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV2]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV3]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLOUT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_CALEN]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PEAKDET1]      = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_ACL_OVR]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL_WAITCNT]   = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_CALVALID]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev3_tx[] = {
+        [B2056_TX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_GAIN_BW]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_I]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_Q]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_I]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_Q]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER1]       = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RXIQCAL_TXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_VCM_HG]         = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_IQCAL_IDAC]           = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, },
+        [B2056_TX_TSSI_VCM]             = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_AMP_DET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MUX]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSIA]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSIG]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PA_SPARE1]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_PA_SPARE2]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_INTPAA_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_STAT]     = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_STAT]    = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAA_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAA_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_STAT]     = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_STAT]    = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAG_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAG_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PADA_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_BOOST_TUNE]      = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
+        [B2056_TX_PADA_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PADG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PADG_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PADG_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PGAA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PGAA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAA_BOOST_TUNE]      = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
+        [B2056_TX_PGAA_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAA_MISC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PGAG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PGAG_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAG_MISC]            = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_MIXA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXA_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_MIXG]                 = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXG_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_BB_GM_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_GM]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC]            = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, },
+        [B2056_TX_TXLPF_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL]          = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF0]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF1]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF2]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF3]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF4]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF5]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF6]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_BW]             = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_TXLPF_GAIN]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_0]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_1]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_2]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_3]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_4]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_5]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_6]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_OPAMP_IDAC]     = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_TX_TXLPF_MISC]           = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, },
+        [B2056_TX_TXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_INTPA_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PAD_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PGA_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_BW]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev3_rx[] = {
+        [B2056_RX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXIQCAL_RXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_RX_RSSI_PU]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_SEL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_GAIN]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_RSSI_NB_IDAC]         = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_POLE]            = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_RSSI_WB1_IDAC]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_RSSI_MISC]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_LNAA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAA_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAA_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_A_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAA1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAA2_IDAC]           = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_RX_LNA1A_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_LNAG_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAG_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAG_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_G_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAG1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAG2_IDAC]           = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_RX_LNA1G_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_MIXA_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXA_VCM]             = { .ghz5 = 0x0099, .ghz2 = 0x0099, NOUPLOAD, },
+        [B2056_RX_MIXA_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_LOB_BIAS]        = { .ghz5 = 0x0044, .ghz2 = 0x0044, UPLOAD, },
+        [B2056_RX_MIXA_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_AUX]        = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXA_MAST_BIAS]       = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_RX_MIXG_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXG_VCM]             = { .ghz5 = 0x0099, .ghz2 = 0x0099, NOUPLOAD, },
+        [B2056_RX_MIXG_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_LOB_BIAS]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_MIXG_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXG_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_MASTER]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_IOPAMP]           = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_RX_TIA_QOPAMP]           = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_RX_TIA_IMISC]            = { .ghz5 = 0x0057, .ghz2 = 0x0057, NOUPLOAD, },
+        [B2056_RX_TIA_QMISC]            = { .ghz5 = 0x0057, .ghz2 = 0x0057, NOUPLOAD, },
+        [B2056_RX_TIA_GAIN]             = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_BB_LPF_MASTER]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_AACI_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_RXLPF_IDAC]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_BIAS_DCCANCEL]  = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_RXLPF_OUTVCM]         = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_INVCM_BODY]     = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_CC_OP]          = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RXLPF_GAIN]           = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_Q_BW]           = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, },
+        [B2056_RX_RXLPF_HP_CORNER_BW]   = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_HPC]      = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_LPC]      = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_0]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_UNUSED]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_VGA_MASTER]           = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS]             = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS_DCCANCEL]    = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_VGA_GAIN]             = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_VGA_HP_CORNER_BW]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_VGABUF_BIAS]          = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGABUF_GAIN_BW]       = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_A]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_G]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAA_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAG_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_MIXTIA_GAIN]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_VGA_BUF_GAIN]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_Q]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_BUF_BW]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_HPC_RC]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev4_syn[] = {
+        [B2056_SYN_RESERVED_ADDR2]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR3]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR4]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR5]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR6]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR7]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_CTRL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_PU]              = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_COM_OVR]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RESET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RCAL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_TXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXHPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR16]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR17]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR18]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR19]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR20]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR21]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR22]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR23]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR24]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR25]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR26]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR27]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR28]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR29]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR30]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR31]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER1]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER2]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_MASTER]      = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_RCAL]        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_AFEREG]              = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSE]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSEIDAC]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSERCAL]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LPO]                 = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_MASTER]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_IDAC]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_STATUS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_CODE_OUT]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL0]         = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL1]         = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL2]         = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL3]         = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL4]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL5]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL6]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL7]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL8]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL9]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL11]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST1]           = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST2]           = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST3]           = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
+        [B2056_SYN_PLL_BIAS_RESET]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL1]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL3]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL5]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL6]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_REFDIV]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_PFD]             = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_CP1]             = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_CP2]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_SYN_PLL_CP3]             = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER1]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER2]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER3]     = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER4]     = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER5]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD1]            = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD2]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO1]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO2]            = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, },
+        [B2056_SYN_PLL_MONITOR1]        = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, },
+        [B2056_SYN_PLL_MONITOR2]        = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL4]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL5]         = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL6]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL7]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL8]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL9]         = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL11]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL12]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_SYN_PLL_VCOCAL13]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_SYN_PLL_VREG]            = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS3]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU2]           = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU8]           = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BIAS_RESET]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RCCR1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF1]       = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER1]        = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER2]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF1]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGENBUF2]           = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, },
+        [B2056_SYN_LOGEN_BUF3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF4]          = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV1]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV2]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV3]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLOUT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_CALEN]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PEAKDET1]      = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_ACL_OVR]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL_WAITCNT]   = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_CALVALID]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev4_tx[] = {
+        [B2056_TX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_GAIN_BW]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_I]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_Q]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_I]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_Q]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER1]       = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RXIQCAL_TXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_VCM_HG]         = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_IQCAL_IDAC]           = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, },
+        [B2056_TX_TSSI_VCM]             = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_AMP_DET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MUX]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSIA]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSIG]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PA_SPARE1]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_PA_SPARE2]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_INTPAA_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_STAT]     = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_STAT]    = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAA_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAA_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_STAT]     = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_STAT]    = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAG_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAG_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PADA_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_BOOST_TUNE]      = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
+        [B2056_TX_PADA_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PADG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PADG_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PADG_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PGAA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PGAA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAA_BOOST_TUNE]      = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
+        [B2056_TX_PGAA_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAA_MISC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PGAG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PGAG_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAG_MISC]            = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_MIXA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXA_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_MIXG]                 = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXG_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_BB_GM_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_GM]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC]            = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, },
+        [B2056_TX_TXLPF_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL]          = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF0]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF1]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF2]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF3]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF4]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF5]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF6]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_BW]             = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_TXLPF_GAIN]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_0]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_1]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_2]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_3]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_4]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_5]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_6]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_OPAMP_IDAC]     = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_TX_TXLPF_MISC]           = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, },
+        [B2056_TX_TXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_INTPA_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PAD_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PGA_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_BW]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev4_rx[] = {
+        [B2056_RX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXIQCAL_RXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_RX_RSSI_PU]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_SEL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_GAIN]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_RSSI_NB_IDAC]         = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_POLE]            = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_RSSI_WB1_IDAC]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_RSSI_MISC]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_LNAA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAA_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAA_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_A_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAA1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAA2_IDAC]           = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_RX_LNA1A_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_LNAG_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAG_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAG_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_G_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAG1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAG2_IDAC]           = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_RX_LNA1G_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_MIXA_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXA_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXA_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_LOB_BIAS]        = { .ghz5 = 0x0044, .ghz2 = 0x0044, UPLOAD, },
+        [B2056_RX_MIXA_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_AUX]        = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXA_MAST_BIAS]       = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_RX_MIXG_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXG_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXG_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_LOB_BIAS]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_MIXG_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXG_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_MASTER]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_IOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_QOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_IMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_QMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_GAIN]             = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_BB_LPF_MASTER]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_AACI_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_RXLPF_IDAC]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_BIAS_DCCANCEL]  = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_RXLPF_OUTVCM]         = { .ghz5 = 0x002f, .ghz2 = 0x002f, UPLOAD, },
+        [B2056_RX_RXLPF_INVCM_BODY]     = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_CC_OP]          = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RXLPF_GAIN]           = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_Q_BW]           = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, },
+        [B2056_RX_RXLPF_HP_CORNER_BW]   = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_HPC]      = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_LPC]      = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_0]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_UNUSED]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_VGA_MASTER]           = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS]             = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS_DCCANCEL]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_VGA_GAIN]             = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_VGA_HP_CORNER_BW]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_VGABUF_BIAS]          = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGABUF_GAIN_BW]       = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_A]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_G]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAA_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAG_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_MIXTIA_GAIN]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_VGA_BUF_GAIN]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_Q]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_BUF_BW]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_HPC_RC]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev5_syn[] = {
+        [B2056_SYN_RESERVED_ADDR2]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR3]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR4]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR5]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR6]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR7]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_CTRL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_PU]              = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_COM_OVR]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RESET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RCAL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_TXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXHPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR16]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR17]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR18]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR19]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR20]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR21]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR22]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR23]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR24]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR25]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR26]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR27]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR28]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR29]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR30]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR31]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER1]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER2]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_MASTER]      = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_RCAL]        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_AFEREG]              = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSE]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSEIDAC]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSERCAL]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LPO]                 = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_MASTER]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_IDAC]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_STATUS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_CODE_OUT]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL0]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL1]         = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL2]         = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL3]         = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL4]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL5]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL6]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL7]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL8]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL9]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL11]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST1]           = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST2]           = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST3]           = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
+        [B2056_SYN_PLL_BIAS_RESET]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL1]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL3]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL5]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL6]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_REFDIV]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_PFD]             = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_CP1]             = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_CP2]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_SYN_PLL_CP3]             = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER1]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER2]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER3]     = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER4]     = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER5]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD1]            = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD2]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO1]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO2]            = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, },
+        [B2056_SYN_PLL_MONITOR1]        = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, },
+        [B2056_SYN_PLL_MONITOR2]        = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL4]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL5]         = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL6]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL7]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL8]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL9]         = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL11]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL12]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_SYN_PLL_VCOCAL13]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_SYN_PLL_VREG]            = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS3]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU2]           = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU8]           = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BIAS_RESET]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RCCR1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF1]       = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER1]        = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER2]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF1]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGENBUF2]           = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, },
+        [B2056_SYN_LOGEN_BUF3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF4]          = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV1]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV2]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV3]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLOUT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_CALEN]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PEAKDET1]      = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_ACL_OVR]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL_WAITCNT]   = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_CALVALID]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev5_tx[] = {
+        [B2056_TX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_GAIN_BW]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_I]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_Q]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_I]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_Q]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER1]       = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RXIQCAL_TXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_VCM_HG]         = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_IQCAL_IDAC]           = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, },
+        [B2056_TX_TSSI_VCM]             = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_AMP_DET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MUX]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSIA]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSIG]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PA_SPARE1]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_PA_SPARE2]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_INTPAA_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_STAT]     = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_STAT]    = { .ghz5 = 0x002d, .ghz2 = 0x002d, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAA_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAA_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_STAT]     = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_STAT]    = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAG_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAG_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PADA_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_BOOST_TUNE]      = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
+        [B2056_TX_PADA_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PADG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PADG_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PADG_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PGAA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PGAA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAA_BOOST_TUNE]      = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
+        [B2056_TX_PGAA_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAA_MISC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PGAG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PGAG_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAG_MISC]            = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_MIXA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXA_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_MIXG]                 = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXG_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_BB_GM_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_GM]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_TX_TXLPF_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL]          = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF0]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF1]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF2]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF3]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF4]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF5]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF6]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_BW]             = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_TXLPF_GAIN]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_0]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_1]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_2]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_3]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_4]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_5]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_6]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_OPAMP_IDAC]     = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_TX_TXLPF_MISC]           = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, },
+        [B2056_TX_TXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_INTPA_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PAD_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PGA_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_BW]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC0]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC1]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC2]           = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, },
+        [B2056_TX_GMBB_IDAC3]           = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, },
+        [B2056_TX_GMBB_IDAC4]           = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, },
+        [B2056_TX_GMBB_IDAC5]           = { .ghz5 = 0x0073, .ghz2 = 0x0073, UPLOAD, },
+        [B2056_TX_GMBB_IDAC6]           = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, },
+        [B2056_TX_GMBB_IDAC7]           = { .ghz5 = 0x0075, .ghz2 = 0x0075, UPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev5_rx[] = {
+        [B2056_RX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXIQCAL_RXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_RX_RSSI_PU]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_SEL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_GAIN]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_RSSI_NB_IDAC]         = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_POLE]            = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_RSSI_WB1_IDAC]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_RSSI_MISC]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_LNAA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAA_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAA_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_A_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAA1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAA2_IDAC]           = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_RX_LNA1A_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_LNAG_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAG_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAG_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_G_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAG1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAG2_IDAC]           = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_RX_LNA1G_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_MIXA_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXA_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXA_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_LOB_BIAS]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, },
+        [B2056_RX_MIXA_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_CMFB_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXA_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXG_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXG_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_LOB_BIAS]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_MIXG_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_CMFB_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_MIXG_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXG_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_MASTER]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_IOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_QOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_IMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_QMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_GAIN]             = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_BB_LPF_MASTER]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_AACI_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_RXLPF_IDAC]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_BIAS_DCCANCEL]  = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_RXLPF_OUTVCM]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
+        [B2056_RX_RXLPF_INVCM_BODY]     = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_CC_OP]          = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RXLPF_GAIN]           = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_Q_BW]           = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, },
+        [B2056_RX_RXLPF_HP_CORNER_BW]   = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_HPC]      = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_LPC]      = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_0]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_UNUSED]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_VGA_MASTER]           = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS]             = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS_DCCANCEL]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_VGA_GAIN]             = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_VGA_HP_CORNER_BW]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_VGABUF_BIAS]          = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGABUF_GAIN_BW]       = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_A]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_G]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAA_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAG_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_MIXTIA_GAIN]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_VGA_BUF_GAIN]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_Q]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_BUF_BW]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_HPC_RC]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev6_syn[] = {
+        [B2056_SYN_RESERVED_ADDR2]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR3]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR4]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR5]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR6]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR7]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_CTRL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_PU]              = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_COM_OVR]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RESET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RCAL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_TXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXHPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR16]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR17]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR18]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR19]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR20]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR21]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR22]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR23]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR24]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR25]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR26]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR27]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR28]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR29]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR30]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR31]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER1]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER2]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_MASTER]      = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_RCAL]        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_AFEREG]              = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSE]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSEIDAC]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSERCAL]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LPO]                 = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_MASTER]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_IDAC]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_STATUS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_CODE_OUT]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL0]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL1]         = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL2]         = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL3]         = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL4]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL5]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL6]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL7]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL8]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL9]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL11]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST1]           = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST2]           = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST3]           = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
+        [B2056_SYN_PLL_BIAS_RESET]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL1]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL3]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL5]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL6]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_REFDIV]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_PFD]             = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_CP1]             = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_CP2]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_SYN_PLL_CP3]             = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER1]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER2]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER3]     = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER4]     = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER5]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD1]            = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD2]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO1]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO2]            = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, },
+        [B2056_SYN_PLL_MONITOR1]        = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, },
+        [B2056_SYN_PLL_MONITOR2]        = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL4]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL5]         = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL6]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL7]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL8]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL9]         = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL11]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL12]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_SYN_PLL_VCOCAL13]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_SYN_PLL_VREG]            = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS3]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU2]           = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU8]           = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BIAS_RESET]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RCCR1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF1]       = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER1]        = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER2]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF1]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGENBUF2]           = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, },
+        [B2056_SYN_LOGEN_BUF3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF4]          = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV1]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV2]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV3]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLOUT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_CALEN]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PEAKDET1]      = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_ACL_OVR]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL_WAITCNT]   = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_CALVALID]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev6_tx[] = {
+        [B2056_TX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_GAIN_BW]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_I]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_Q]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_I]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_Q]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER1]       = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RXIQCAL_TXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_VCM_HG]         = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_IQCAL_IDAC]           = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, },
+        [B2056_TX_TSSI_VCM]             = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_AMP_DET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MUX]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSIA]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSIG]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PA_SPARE1]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_PA_SPARE2]            = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, },
+        [B2056_TX_INTPAA_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_STAT]     = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_TX_INTPAA_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_STAT]    = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAA_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAA_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_STAT]     = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_STAT]    = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAG_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAG_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PADA_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_BOOST_TUNE]      = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
+        [B2056_TX_PADA_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PADG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PADG_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PADG_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PGAA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PGAA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAA_BOOST_TUNE]      = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
+        [B2056_TX_PGAA_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAA_MISC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PGAG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PGAG_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAG_MISC]            = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_MIXA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXA_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_MIXG]                 = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXG_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_BB_GM_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_GM]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_TX_TXLPF_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL]          = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF0]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF1]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF2]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF3]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF4]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF5]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF6]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_BW]             = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_TXLPF_GAIN]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_0]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_1]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_2]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_3]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_4]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_5]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_6]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_OPAMP_IDAC]     = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_TX_TXLPF_MISC]           = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, },
+        [B2056_TX_TXSPARE1]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, },
+        [B2056_TX_TXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_INTPA_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PAD_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PGA_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_BW]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC0]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC1]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC2]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC3]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC4]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC5]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC6]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC7]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev6_rx[] = {
+        [B2056_RX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXIQCAL_RXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_RX_RSSI_PU]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_SEL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_GAIN]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_RSSI_NB_IDAC]         = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_POLE]            = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_RSSI_WB1_IDAC]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_RSSI_MISC]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_LNAA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAA_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAA_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_A_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAA1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAA2_IDAC]           = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_RX_LNA1A_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_LNAG_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAG_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAG_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_G_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAG1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAG2_IDAC]           = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_RX_LNA1G_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_MIXA_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXA_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXA_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_LOB_BIAS]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, },
+        [B2056_RX_MIXA_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXA_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXG_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXG_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_LOB_BIAS]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_MIXG_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXG_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_MASTER]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_IOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_QOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_IMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_QMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_GAIN]             = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_BB_LPF_MASTER]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_AACI_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_RXLPF_IDAC]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_BIAS_DCCANCEL]  = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_RXLPF_OUTVCM]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
+        [B2056_RX_RXLPF_INVCM_BODY]     = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_CC_OP]          = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RXLPF_GAIN]           = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_Q_BW]           = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, },
+        [B2056_RX_RXLPF_HP_CORNER_BW]   = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_HPC]      = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_LPC]      = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_0]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_UNUSED]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_VGA_MASTER]           = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS]             = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS_DCCANCEL]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_VGA_GAIN]             = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_VGA_HP_CORNER_BW]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_VGABUF_BIAS]          = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGABUF_GAIN_BW]       = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_A]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_G]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE3]             = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, },
+        [B2056_RX_RXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAA_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAG_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_MIXTIA_GAIN]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_VGA_BUF_GAIN]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_Q]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_BUF_BW]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_HPC_RC]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev7_syn[] = {
+        [B2056_SYN_RESERVED_ADDR2]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR3]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR4]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR5]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR6]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR7]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_CTRL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_PU]              = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_COM_OVR]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RESET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RCAL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_TXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXHPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR16]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR17]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR18]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR19]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR20]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR21]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR22]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR23]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR24]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR25]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR26]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR27]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR28]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR29]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR30]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR31]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER1]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER2]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_MASTER]      = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_RCAL]        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_AFEREG]              = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSE]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSEIDAC]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSERCAL]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LPO]                 = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_MASTER]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_IDAC]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_STATUS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_CODE_OUT]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL0]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL1]         = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL2]         = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL3]         = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL4]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL5]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL6]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL7]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL8]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL9]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL11]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST1]           = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST2]           = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST3]           = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
+        [B2056_SYN_PLL_BIAS_RESET]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL1]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL3]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL5]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL6]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_REFDIV]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_PFD]             = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_CP1]             = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_CP2]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_SYN_PLL_CP3]             = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER1]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER2]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER3]     = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER4]     = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER5]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD1]            = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD2]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO1]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO2]            = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, },
+        [B2056_SYN_PLL_MONITOR1]        = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, },
+        [B2056_SYN_PLL_MONITOR2]        = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL4]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL5]         = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL6]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL7]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL8]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL9]         = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL11]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL12]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_SYN_PLL_VCOCAL13]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_SYN_PLL_VREG]            = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS3]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU2]           = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU8]           = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BIAS_RESET]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RCCR1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF1]       = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER1]        = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER2]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF1]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGENBUF2]           = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, },
+        [B2056_SYN_LOGEN_BUF3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF4]          = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV1]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV2]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV3]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLOUT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_CALEN]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PEAKDET1]      = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_ACL_OVR]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL_WAITCNT]   = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_CALVALID]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev7_tx[] = {
+        [B2056_TX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_GAIN_BW]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_I]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_Q]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_I]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_Q]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER1]       = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RXIQCAL_TXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_VCM_HG]         = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_IQCAL_IDAC]           = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, },
+        [B2056_TX_TSSI_VCM]             = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_AMP_DET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MUX]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSIA]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSIG]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PA_SPARE1]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_PA_SPARE2]            = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, },
+        [B2056_TX_INTPAA_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_STAT]     = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_TX_INTPAA_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_STAT]    = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAA_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAA_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_STAT]     = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_STAT]    = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAG_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAG_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PADA_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_BOOST_TUNE]      = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
+        [B2056_TX_PADA_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PADG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PADG_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PADG_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PGAA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PGAA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAA_BOOST_TUNE]      = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
+        [B2056_TX_PGAA_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAA_MISC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PGAG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PGAG_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAG_MISC]            = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_MIXA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXA_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_MIXG]                 = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXG_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_BB_GM_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_GM]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_TX_TXLPF_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL]          = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF0]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF1]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF2]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF3]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF4]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF5]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF6]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_BW]             = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_TXLPF_GAIN]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_0]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_1]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_2]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_3]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_4]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_5]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_6]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_OPAMP_IDAC]     = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_TX_TXLPF_MISC]           = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, },
+        [B2056_TX_TXSPARE1]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, },
+        [B2056_TX_TXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_INTPA_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PAD_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PGA_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_BW]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC0]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC1]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC2]           = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, },
+        [B2056_TX_GMBB_IDAC3]           = { .ghz5 = 0x0071, .ghz2 = 0x0071, UPLOAD, },
+        [B2056_TX_GMBB_IDAC4]           = { .ghz5 = 0x0072, .ghz2 = 0x0072, UPLOAD, },
+        [B2056_TX_GMBB_IDAC5]           = { .ghz5 = 0x0073, .ghz2 = 0x0073, UPLOAD, },
+        [B2056_TX_GMBB_IDAC6]           = { .ghz5 = 0x0074, .ghz2 = 0x0074, UPLOAD, },
+        [B2056_TX_GMBB_IDAC7]           = { .ghz5 = 0x0075, .ghz2 = 0x0075, UPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev7_rx[] = {
+        [B2056_RX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXIQCAL_RXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_RX_RSSI_PU]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_SEL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_GAIN]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_RSSI_NB_IDAC]         = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_POLE]            = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_RSSI_WB1_IDAC]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_RSSI_MISC]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_LNAA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAA_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAA_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_A_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAA1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAA2_IDAC]           = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_RX_LNA1A_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_LNAG_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAG_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAG_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_G_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAG1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAG2_IDAC]           = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_RX_LNA1G_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_MIXA_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXA_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXA_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_LOB_BIAS]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, },
+        [B2056_RX_MIXA_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_CMFB_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXA_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXG_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXG_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_LOB_BIAS]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_MIXG_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_CMFB_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_MIXG_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXG_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_MASTER]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_IOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_QOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_IMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_QMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_GAIN]             = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_BB_LPF_MASTER]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_AACI_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_RXLPF_IDAC]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_BIAS_DCCANCEL]  = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_RXLPF_OUTVCM]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
+        [B2056_RX_RXLPF_INVCM_BODY]     = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_CC_OP]          = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RXLPF_GAIN]           = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_Q_BW]           = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, },
+        [B2056_RX_RXLPF_HP_CORNER_BW]   = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_HPC]      = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_LPC]      = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_0]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_UNUSED]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_VGA_MASTER]           = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS]             = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS_DCCANCEL]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_VGA_GAIN]             = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_VGA_HP_CORNER_BW]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_VGABUF_BIAS]          = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGABUF_GAIN_BW]       = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_A]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_G]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAA_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAG_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_MIXTIA_GAIN]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_VGA_BUF_GAIN]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_Q]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_BUF_BW]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_HPC_RC]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev8_syn[] = {
+        [B2056_SYN_RESERVED_ADDR2]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR3]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR4]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR5]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR6]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR7]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_CTRL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_PU]              = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_COM_OVR]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RESET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RCAL]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_TXLPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_COM_RC_RXHPF]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR16]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR17]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR18]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR19]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR20]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR21]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR22]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR23]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR24]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR25]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR26]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR27]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR28]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR29]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR30]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RESERVED_ADDR31]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER1]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_GPIO_MASTER2]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_MASTER]      = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_TOPBIAS_RCAL]        = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_AFEREG]              = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSE]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSEIDAC]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_TEMPPROCSENSERCAL]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LPO]                 = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_MASTER]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_IDAC]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_VDDCAL_STATUS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCAL_CODE_OUT]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL0]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL1]         = { .ghz5 = 0x001f, .ghz2 = 0x001f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL2]         = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL3]         = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL4]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL5]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL6]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL7]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL8]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL9]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_RCCAL_CTRL11]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_ZCAL_SPARE2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST1]           = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST2]           = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_MAST3]           = { .ghz5 = 0x0018, .ghz2 = 0x0018, NOUPLOAD, },
+        [B2056_SYN_PLL_BIAS_RESET]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL1]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL3]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL5]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_SYN_PLL_XTAL6]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_REFDIV]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_PFD]             = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_CP1]             = { .ghz5 = 0x000f, .ghz2 = 0x000f, NOUPLOAD, },
+        [B2056_SYN_PLL_CP2]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_SYN_PLL_CP3]             = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER1]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER2]     = { .ghz5 = 0x000d, .ghz2 = 0x000d, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER3]     = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER4]     = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_PLL_LOOPFILTER5]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD1]            = { .ghz5 = 0x001c, .ghz2 = 0x001c, NOUPLOAD, },
+        [B2056_SYN_PLL_MMD2]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO1]            = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCO2]            = { .ghz5 = 0x00f7, .ghz2 = 0x00f7, UPLOAD, },
+        [B2056_SYN_PLL_MONITOR1]        = { .ghz5 = 0x00b4, .ghz2 = 0x00b4, NOUPLOAD, },
+        [B2056_SYN_PLL_MONITOR2]        = { .ghz5 = 0x00d2, .ghz2 = 0x00d2, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL4]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL5]         = { .ghz5 = 0x0096, .ghz2 = 0x0096, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL6]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL7]         = { .ghz5 = 0x003e, .ghz2 = 0x003e, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL8]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL9]         = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL10]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL11]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_SYN_PLL_VCOCAL12]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_SYN_PLL_VCOCAL13]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_SYN_PLL_VREG]            = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS2]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_PLL_STATUS3]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU2]           = { .ghz5 = 0x0040, .ghz2 = 0x0040, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PU8]           = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BIAS_RESET]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RCCR1]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF1]       = { .ghz5 = 0x0060, .ghz2 = 0x0060, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER1]        = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER2]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF1]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGENBUF2]           = { .ghz5 = 0x008f, .ghz2 = 0x008f, UPLOAD, },
+        [B2056_SYN_LOGEN_BUF3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF4]          = { .ghz5 = 0x00cc, .ghz2 = 0x00cc, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV1]          = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV2]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_DIV3]          = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLOUT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACLCAL3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_CALEN]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_PEAKDET1]      = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_ACL_OVR]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_DIFF_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_ACL_OVR]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_VCOBUF2_OVRVAL]= { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_SYN_LOGEN_MIXER3_OVRVAL] = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF5_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_BUF6_OVRVAL]   = { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CBUFTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSRX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX1_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX2_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX3_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CMOSTX4_OVRVAL]= { .ghz5 = 0x0066, .ghz2 = 0x0066, NOUPLOAD, },
+        [B2056_SYN_LOGEN_ACL_WAITCNT]   = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_SYN_LOGEN_CORE_CALVALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_RX_CMOS_CALVALID]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_SYN_LOGEN_TX_CMOS_VALID] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev8_tx[] = {
+        [B2056_TX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_GAIN_BW]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_I]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_FINE_Q]          = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_I]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_LOFT_COARSE_Q]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER1]       = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_TX_COM_MASTER2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_RXIQCAL_TXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_IQCAL_VCM_HG]         = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_IQCAL_IDAC]           = { .ghz5 = 0x0037, .ghz2 = 0x0037, NOUPLOAD, },
+        [B2056_TX_TSSI_VCM]             = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_TX_AMP_DET]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TX_SSI_MUX]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSIA]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSIG]                = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TSSI_MISC3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PA_SPARE1]            = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_TX_PA_SPARE2]            = { .ghz5 = 0x00ee, .ghz2 = 0x00ee, UPLOAD, },
+        [B2056_TX_INTPAA_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAA_IAUX_STAT]     = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_TX_INTPAA_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_STAT]    = { .ghz5 = 0x0050, .ghz2 = 0x0050, UPLOAD, },
+        [B2056_TX_INTPAA_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAA_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAA_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAA_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_MASTER]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_GAIN]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_BOOST_TUNE]    = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_STAT]     = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_TX_INTPAG_IAUX_DYN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_STAT]    = { .ghz5 = 0x001e, .ghz2 = 0x001e, NOUPLOAD, },
+        [B2056_TX_INTPAG_IMAIN_DYN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_INTPAG_CASCBIAS]      = { .ghz5 = 0x006e, .ghz2 = 0x006e, NOUPLOAD, },
+        [B2056_TX_INTPAG_PASLOPE]       = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_TX_INTPAG_PA_MISC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PADA_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADA_BOOST_TUNE]      = { .ghz5 = 0x0038, .ghz2 = 0x0038, NOUPLOAD, },
+        [B2056_TX_PADA_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PADG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PADG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PADG_CASCBIAS]        = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_TX_PADG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PADG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PADG_SLOPE]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, UPLOAD, },
+        [B2056_TX_PGAA_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAA_IDAC]            = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_TX_PGAA_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAA_BOOST_TUNE]      = { .ghz5 = 0x0083, .ghz2 = 0x0083, NOUPLOAD, },
+        [B2056_TX_PGAA_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAA_MISC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_MASTER]          = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_PGAG_IDAC]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_TX_PGAG_GAIN]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_PGAG_BOOST_TUNE]      = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_TX_PGAG_SLOPE]           = { .ghz5 = 0x0077, .ghz2 = 0x0077, UPLOAD, },
+        [B2056_TX_PGAG_MISC]            = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_TX_MIXA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXA_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_MIXG]                 = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_MIXG_BOOST_TUNE]      = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_TX_BB_GM_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_GM]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_TX_TXLPF_MASTER]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL]          = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF0]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF1]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF2]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF3]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF4]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF5]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_RCCAL_OFF6]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_BW]             = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_TX_TXLPF_GAIN]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_0]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_1]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_2]         = { .ghz5 = 0x000e, .ghz2 = 0x000e, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_3]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_4]         = { .ghz5 = 0x0013, .ghz2 = 0x0013, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_5]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_IDAC_6]         = { .ghz5 = 0x001b, .ghz2 = 0x001b, NOUPLOAD, },
+        [B2056_TX_TXLPF_OPAMP_IDAC]     = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_TX_TXLPF_MISC]           = { .ghz5 = 0x005b, .ghz2 = 0x005b, NOUPLOAD, },
+        [B2056_TX_TXSPARE1]             = { .ghz5 = 0x0030, .ghz2 = 0x0030, UPLOAD, },
+        [B2056_TX_TXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE3]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_TXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_INTPA_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PAD_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_PGA_GAIN]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_GM_TXLPF_GAIN] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_BW]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_STATUS_TXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC0]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC1]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC2]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC3]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC4]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC5]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC6]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+        [B2056_TX_GMBB_IDAC7]           = { .ghz5 = 0x0070, .ghz2 = 0x0070, NOUPLOAD, },
+};
+
+static const struct b2056_inittab_entry b2056_inittab_rev8_rx[] = {
+        [B2056_RX_RESERVED_ADDR2]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR3]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR4]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR5]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR6]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR7]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_CTRL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_PU]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_OVR]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RESET]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RCAL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_TXLPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_COM_RC_RXHPF]         = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR16]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR17]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR18]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR19]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR20]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR21]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR22]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR23]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR24]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR25]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR26]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR27]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR28]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR29]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR30]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RESERVED_ADDR31]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXIQCAL_RXMUX]        = { .ghz5 = 0x0003, .ghz2 = 0x0003, NOUPLOAD, },
+        [B2056_RX_RSSI_PU]              = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_SEL]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RSSI_GAIN]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_RSSI_NB_IDAC]         = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2I_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_1]     = { .ghz5 = 0x0015, .ghz2 = 0x0015, NOUPLOAD, },
+        [B2056_RX_RSSI_WB2Q_IDAC_2]     = { .ghz5 = 0x0005, .ghz2 = 0x0005, NOUPLOAD, },
+        [B2056_RX_RSSI_POLE]            = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_RSSI_WB1_IDAC]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_RSSI_MISC]            = { .ghz5 = 0x0090, .ghz2 = 0x0090, NOUPLOAD, },
+        [B2056_RX_LNAA_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAA_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAA_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_A_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAA1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAA2_IDAC]           = { .ghz5 = 0x00ff, .ghz2 = 0x00ff, UPLOAD, },
+        [B2056_RX_LNA1A_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_LNAG_MASTER]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_LNAG_TUNE]            = { .ghz5 = 0x0088, .ghz2 = 0x0088, NOUPLOAD, },
+        [B2056_RX_LNAG_GAIN]            = { .ghz5 = 0x0032, .ghz2 = 0x0032, NOUPLOAD, },
+        [B2056_RX_LNA_G_SLOPE]          = { .ghz5 = 0x0077, .ghz2 = 0x0077, NOUPLOAD, },
+        [B2056_RX_BIASPOLE_LNAG1_IDAC]  = { .ghz5 = 0x0017, .ghz2 = 0x0017, UPLOAD, },
+        [B2056_RX_LNAG2_IDAC]           = { .ghz5 = 0x00f0, .ghz2 = 0x00f0, UPLOAD, },
+        [B2056_RX_LNA1G_MISC]           = { .ghz5 = 0x0020, .ghz2 = 0x0020, NOUPLOAD, },
+        [B2056_RX_MIXA_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXA_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXA_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_LOB_BIAS]        = { .ghz5 = 0x0088, .ghz2 = 0x0088, UPLOAD, },
+        [B2056_RX_MIXA_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXA_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, UPLOAD, },
+        [B2056_RX_MIXA_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXA_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXA_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_MIXG_VCM]             = { .ghz5 = 0x0055, .ghz2 = 0x0055, UPLOAD, },
+        [B2056_RX_MIXG_CTRLPTAT]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_LOB_BIAS]        = { .ghz5 = 0x0011, .ghz2 = 0x0011, NOUPLOAD, },
+        [B2056_RX_MIXG_CORE_IDAC]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_MIXG_CMFB_IDAC]       = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_AUX]        = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MAIN]       = { .ghz5 = 0x0006, .ghz2 = 0x0006, NOUPLOAD, },
+        [B2056_RX_MIXG_BIAS_MISC]       = { .ghz5 = 0x0004, .ghz2 = 0x0004, NOUPLOAD, },
+        [B2056_RX_MIXG_MAST_BIAS]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_MASTER]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_IOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_QOPAMP]           = { .ghz5 = 0x0026, .ghz2 = 0x0026, UPLOAD, },
+        [B2056_RX_TIA_IMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_QMISC]            = { .ghz5 = 0x000f, .ghz2 = 0x000f, UPLOAD, },
+        [B2056_RX_TIA_GAIN]             = { .ghz5 = 0x0044, .ghz2 = 0x0044, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TIA_SPARE2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_BB_LPF_MASTER]        = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_AACI_MASTER]          = { .ghz5 = 0x0008, .ghz2 = 0x0008, NOUPLOAD, },
+        [B2056_RX_RXLPF_IDAC]           = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_LOWQ] = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_OPAMPBIAS_HIGHQ]= { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_RXLPF_BIAS_DCCANCEL]  = { .ghz5 = 0x0002, .ghz2 = 0x0002, NOUPLOAD, },
+        [B2056_RX_RXLPF_OUTVCM]         = { .ghz5 = 0x0004, .ghz2 = 0x0004, UPLOAD, },
+        [B2056_RX_RXLPF_INVCM_BODY]     = { .ghz5 = 0x0007, .ghz2 = 0x0007, NOUPLOAD, },
+        [B2056_RX_RXLPF_CC_OP]          = { .ghz5 = 0x0055, .ghz2 = 0x0055, NOUPLOAD, },
+        [B2056_RX_RXLPF_GAIN]           = { .ghz5 = 0x0023, .ghz2 = 0x0023, NOUPLOAD, },
+        [B2056_RX_RXLPF_Q_BW]           = { .ghz5 = 0x0041, .ghz2 = 0x0041, NOUPLOAD, },
+        [B2056_RX_RXLPF_HP_CORNER_BW]   = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_HPC]      = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF0]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF1]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF2]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF3]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF4]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF5]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF6]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXHPF_OFF7]           = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_RCCAL_LPC]      = { .ghz5 = 0x000c, .ghz2 = 0x000c, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_0]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_1]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_2]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_3]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXLPF_OFF_4]          = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_UNUSED]               = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_VGA_MASTER]           = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS]             = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGA_BIAS_DCCANCEL]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, UPLOAD, },
+        [B2056_RX_VGA_GAIN]             = { .ghz5 = 0x000a, .ghz2 = 0x000a, NOUPLOAD, },
+        [B2056_RX_VGA_HP_CORNER_BW]     = { .ghz5 = 0x0001, .ghz2 = 0x0001, NOUPLOAD, },
+        [B2056_RX_VGABUF_BIAS]          = { .ghz5 = 0x0022, .ghz2 = 0x0022, NOUPLOAD, },
+        [B2056_RX_VGABUF_GAIN_BW]       = { .ghz5 = 0x0030, .ghz2 = 0x0030, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_A]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_TXFBMIX_G]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE1]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE2]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE3]             = { .ghz5 = 0x0005, .ghz2 = 0x0005, UPLOAD, },
+        [B2056_RX_RXSPARE4]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE5]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE6]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE7]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE8]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE9]             = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE10]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE11]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE12]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE13]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE14]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE15]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_RXSPARE16]            = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAA_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_LNAG_GAIN]     = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_MIXTIA_GAIN]   = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_GAIN]    = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_VGA_BUF_GAIN]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_Q]       = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_BUF_BW]  = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_VGA_HPC] = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_RXLPF_RC]      = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+        [B2056_RX_STATUS_HPC_RC]        = { .ghz5 = 0x0000, .ghz2 = 0x0000, NOUPLOAD, },
+};
+
+#define INITTABSPTS(prefix) \
+        .syn            = prefix##_syn,                 \
+        .syn_length     = ARRAY_SIZE(prefix##_syn),     \
+        .tx             = prefix##_tx,                  \
+        .tx_length      = ARRAY_SIZE(prefix##_tx),      \
+        .rx             = prefix##_rx,                  \
+        .rx_length      = ARRAY_SIZE(prefix##_rx)
+
+struct b2056_inittabs_pts b2056_inittabs[] = {
+        [3] = { INITTABSPTS(b2056_inittab_rev3) },
+        [4] = { INITTABSPTS(b2056_inittab_rev4) },
+        [5] = { INITTABSPTS(b2056_inittab_rev5) },
+        [6] = { INITTABSPTS(b2056_inittab_rev6) },
+        [7] = { INITTABSPTS(b2056_inittab_rev7) },
+        [8] = { INITTABSPTS(b2056_inittab_rev8) },
+        [9] = { INITTABSPTS(b2056_inittab_rev7) },
+};
+
+#define RADIOREGS3(r00, r01, r02, r03, r04, r05, r06, r07, r08, r09, \
+                   r10, r11, r12, r13, r14, r15, r16, r17, r18, r19, \
+                   r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, \
+                   r30, r31, r32, r33, r34, r35, r36) \
+        .radio_syn_pll_vcocal1          = r00,  \
+        .radio_syn_pll_vcocal2          = r01,  \
+        .radio_syn_pll_refdiv           = r02,  \
+        .radio_syn_pll_mmd2             = r03,  \
+        .radio_syn_pll_mmd1             = r04,  \
+        .radio_syn_pll_loopfilter1      = r05,  \
+        .radio_syn_pll_loopfilter2      = r06,  \
+        .radio_syn_pll_loopfilter3      = r07,  \
+        .radio_syn_pll_loopfilter4      = r08,  \
+        .radio_syn_pll_loopfilter5      = r09,  \
+        .radio_syn_reserved_addr27      = r10,  \
+        .radio_syn_reserved_addr28      = r11,  \
+        .radio_syn_reserved_addr29      = r12,  \
+        .radio_syn_logen_vcobuf1        = r13,  \
+        .radio_syn_logen_mixer2         = r14,  \
+        .radio_syn_logen_buf3           = r15,  \
+        .radio_syn_logen_buf4           = r16,  \
+        .radio_rx0_lnaa_tune            = r17,  \
+        .radio_rx0_lnag_tune            = r18,  \
+        .radio_tx0_intpaa_boost_tune    = r19,  \
+        .radio_tx0_intpag_boost_tune    = r20,  \
+        .radio_tx0_pada_boost_tune      = r21,  \
+        .radio_tx0_padg_boost_tune      = r22,  \
+        .radio_tx0_pgaa_boost_tune      = r23,  \
+        .radio_tx0_pgag_boost_tune      = r24,  \
+        .radio_tx0_mixa_boost_tune      = r25,  \
+        .radio_tx0_mixg_boost_tune      = r26,  \
+        .radio_rx1_lnaa_tune            = r27,  \
+        .radio_rx1_lnag_tune            = r28,  \
+        .radio_tx1_intpaa_boost_tune    = r29,  \
+        .radio_tx1_intpag_boost_tune    = r30,  \
+        .radio_tx1_pada_boost_tune      = r31,  \
+        .radio_tx1_padg_boost_tune      = r32,  \
+        .radio_tx1_pgaa_boost_tune      = r33,  \
+        .radio_tx1_pgag_boost_tune      = r34,  \
+        .radio_tx1_mixa_boost_tune      = r35,  \
+        .radio_tx1_mixg_boost_tune      = r36
+
+#define PHYREGS(r0, r1, r2, r3, r4, r5) \
+        .phy_regs.phy_bw1a      = r0,   \
+        .phy_regs.phy_bw2       = r1,   \
+        .phy_regs.phy_bw3       = r2,   \
+        .phy_regs.phy_bw4       = r3,   \
+        .phy_regs.phy_bw5       = r4,   \
+        .phy_regs.phy_bw6       = r5
+
+/* http://bcm-v4.sipsolutions.net/802.11/Radio/2056/ChannelTable */
 static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_rev3[] = {
+  {     .freq                   = 4920,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216),
+  },
+  {     .freq                   = 4930,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215),
+  },
+  {     .freq                   = 4940,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214),
+  },
+  {     .freq                   = 4950,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213),
+  },
+  {     .freq                   = 4960,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212),
+  },
+  {     .freq                   = 4970,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211),
+  },
+  {     .freq                   = 4980,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f),
+  },
+  {     .freq                   = 4990,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e),
+  },
+  {     .freq                   = 5000,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d),
+  },
+  {     .freq                   = 5010,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c),
+  },
+  {     .freq                   = 5020,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b),
+  },
+  {     .freq                   = 5030,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a),
+  },
+  {     .freq                   = 5040,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209),
+  },
+  {     .freq                   = 5050,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208),
+  },
+  {     .freq                   = 5060,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207),
+  },
+  {     .freq                   = 5070,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206),
+  },
+  {     .freq                   = 5080,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205),
+  },
+  {     .freq                   = 5090,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204),
+  },
+  {     .freq                   = 5100,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xff, 0x00),
+        PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203),
+  },
+  {     .freq                   = 5110,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202),
+  },
+  {     .freq                   = 5120,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201),
+  },
+  {     .freq                   = 5130,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200),
+  },
+  {     .freq                   = 5140,
+        RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff),
+  },
+  {     .freq                   = 5160,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd),
+  },
+  {     .freq                   = 5170,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xff, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc),
+  },
+  {     .freq                   = 5180,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
+  },
+  {     .freq                   = 5190,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xef, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xfc, 0x00, 0xef, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa),
+  },
+  {     .freq                   = 5200,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xef, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xef, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
+  },
+  {     .freq                   = 5210,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8),
+  },
+  {     .freq                   = 5220,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
+  },
+  {     .freq                   = 5230,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xdf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xdf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6),
+  },
+  {     .freq                   = 5240,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
+  },
+  {     .freq                   = 5250,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4),
+  },
+  {     .freq                   = 5260,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3),
+  },
+  {     .freq                   = 5270,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2),
+  },
+  {     .freq                   = 5280,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1),
+  },
+  {     .freq                   = 5290,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xbf, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xfc, 0x00, 0xbf, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0),
+  },
+  {     .freq                   = 5300,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfc, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfc, 0x00),
+        PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0),
+  },
+  {     .freq                   = 5310,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef),
+  },
+  {     .freq                   = 5320,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xbf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0xbf, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee),
+  },
+  {     .freq                   = 5330,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed),
+  },
+  {     .freq                   = 5340,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xaf, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec),
+  },
+  {     .freq                   = 5350,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb),
+  },
+  {     .freq                   = 5360,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea),
+  },
+  {     .freq                   = 5370,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9),
+  },
+  {     .freq                   = 5380,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8),
+  },
+  {     .freq                   = 5390,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x8f, 0x00, 0x05, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xfa, 0x00, 0x8f, 0x00, 0x05, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7),
+  },
+  {     .freq                   = 5400,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6),
+  },
+  {     .freq                   = 5410,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8f, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xfa, 0x00, 0x8f, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5),
+  },
+  {     .freq                   = 5420,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xfa, 0x00),
+        PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5),
+  },
+  {     .freq                   = 5430,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xfa, 0x00, 0x8e, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4),
+  },
+  {     .freq                   = 5440,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x7e, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xfa, 0x00, 0x7e, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3),
+  },
+  {     .freq                   = 5450,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x7d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xfa, 0x00, 0x7d, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2),
+  },
+  {     .freq                   = 5460,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xf8, 0x00, 0x6d, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xf8, 0x00),
+        PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1),
+  },
+  {     .freq                   = 5470,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x6d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xf8, 0x00, 0x6d, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0),
+  },
+  {     .freq                   = 5480,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x5d, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xf8, 0x00, 0x5d, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df),
+  },
+  {     .freq                   = 5490,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x5c, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x08,
+                   0x00, 0xf8, 0x00, 0x5c, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x08, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de),
+  },
+  {     .freq                   = 5500,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x5c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x5c, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd),
+  },
+  {     .freq                   = 5510,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd),
+  },
+  {     .freq                   = 5520,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x4c, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x4c, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc),
+  },
+  {     .freq                   = 5530,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db),
+  },
+  {     .freq                   = 5540,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da),
+  },
+  {     .freq                   = 5550,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x3b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x3b, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9),
+  },
+  {     .freq                   = 5560,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x2b, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x2b, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8),
+  },
+  {     .freq                   = 5570,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x2a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x2a, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7),
+  },
+  {     .freq                   = 5580,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7),
+  },
+  {     .freq                   = 5590,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6),
+  },
+  {     .freq                   = 5600,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x1a, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x1a, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5),
+  },
+  {     .freq                   = 5610,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4),
+  },
+  {     .freq                   = 5620,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x19, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x19, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3),
+  },
+  {     .freq                   = 5630,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2),
+  },
+  {     .freq                   = 5640,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x09, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x09, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2),
+  },
+  {     .freq                   = 5650,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf8, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf8, 0x00),
+        PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1),
+  },
+  {     .freq                   = 5660,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0),
+  },
+  {     .freq                   = 5670,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf),
+  },
+  {     .freq                   = 5680,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf6, 0x00, 0x08, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce),
+  },
+  {     .freq                   = 5690,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf6, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce),
+  },
+  {     .freq                   = 5700,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf6, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd),
+  },
+  {     .freq                   = 5710,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc),
+  },
+  {     .freq                   = 5720,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x07, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x07, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5725,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5730,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5735,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5740,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9),
+  },
+  {     .freq                   = 5745,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5750,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x06, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5755,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8),
+  },
+  {     .freq                   = 5760,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5765,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5770,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5775,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5780,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x05, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6),
+  },
+  {     .freq                   = 5785,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5790,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5795,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5800,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5805,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
+  },
+  {     .freq                   = 5810,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5815,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5820,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5825,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5830,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2),
+  },
+  {     .freq                   = 5840,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2),
+  },
+  {     .freq                   = 5850,
+        RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf4, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf4, 0x00),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1),
+  },
+  {     .freq                   = 5860,
+        RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf2, 0x00, 0x03, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf2, 0x00),
+        PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0),
+  },
+  {     .freq                   = 5870,
+        RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf),
+  },
+  {     .freq                   = 5880,
+        RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf),
+  },
+  {     .freq                   = 5890,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x06,
+                   0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x06, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be),
+  },
+  {     .freq                   = 5900,
+        RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00,
+                   0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
+                   0x00, 0xf2, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x05, 0x00, 0xf2, 0x00),
+        PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd),
+  },
+  {     .freq                   = 5910,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00,
+                   0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x05,
+                   0x00, 0xf2, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x05, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc),
+  },
+  {     .freq                   = 2412,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
+  },
+  {     .freq                   = 2417,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
+  },
+  {     .freq                   = 2422,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xff, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xff, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
+  },
+  {     .freq                   = 2427,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xfd, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xfd, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
+  },
+  {     .freq                   = 2432,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xfb, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xfb, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
+  },
+  {     .freq                   = 2437,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xfa, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xfa, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
+  },
+  {     .freq                   = 2442,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf8, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xf8, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
+  },
+  {     .freq                   = 2447,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf7, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xf7, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
+  },
+  {     .freq                   = 2452,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf6, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0f, 0x00, 0xf6, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0f),
+        PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
+  },
+  {     .freq                   = 2457,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf5, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0d, 0x00, 0xf5, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0d),
+        PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
+  },
+  {     .freq                   = 2462,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf4, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0d, 0x00, 0xf4, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0d),
+        PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
+  },
+  {     .freq                   = 2467,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf3, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0d, 0x00, 0xf3, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0d),
+        PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
+  },
+  {     .freq                   = 2472,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf2, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0d, 0x00, 0xf2, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0d),
+        PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
+  },
+  {     .freq                   = 2484,
+        RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf0, 0x00, 0x05, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0d, 0x00, 0xf0, 0x00, 0x05, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0d),
+        PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
+  },
+};
+
+static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_rev4[] = {
+  {     .freq                   = 4920,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216),
+  },
+  {     .freq                   = 4930,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215),
+  },
+  {     .freq                   = 4940,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214),
+  },
+  {     .freq                   = 4950,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213),
+  },
+  {     .freq                   = 4960,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212),
+  },
+  {     .freq                   = 4970,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211),
+  },
+  {     .freq                   = 4980,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f),
+  },
+  {     .freq                   = 4990,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0e, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0e, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e),
+  },
+  {     .freq                   = 5000,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d),
+  },
+  {     .freq                   = 5010,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c),
+  },
+  {     .freq                   = 5020,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b),
+  },
+  {     .freq                   = 5030,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a),
+  },
+  {     .freq                   = 5040,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209),
+  },
+  {     .freq                   = 5050,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208),
+  },
+  {     .freq                   = 5060,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207),
+  },
+  {     .freq                   = 5070,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206),
+  },
+  {     .freq                   = 5080,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205),
+  },
+  {     .freq                   = 5090,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0d, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xff, 0x00, 0xff, 0x00, 0x0d, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xff, 0x00),
+        PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204),
+  },
+  {     .freq                   = 5100,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203),
+  },
+  {     .freq                   = 5110,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202),
+  },
+  {     .freq                   = 5120,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201),
+  },
+  {     .freq                   = 5130,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200),
+  },
+  {     .freq                   = 5140,
+        RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff),
+  },
+  {     .freq                   = 5160,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd),
+  },
+  {     .freq                   = 5170,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xff, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc),
+  },
+  {     .freq                   = 5180,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
+  },
+  {     .freq                   = 5190,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xef, 0x00, 0x0c, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfe, 0x00, 0xef, 0x00, 0x0c, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfe, 0x00),
+        PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa),
+  },
+  {     .freq                   = 5200,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xef, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xef, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
+  },
+  {     .freq                   = 5210,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8),
+  },
+  {     .freq                   = 5220,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
+  },
+  {     .freq                   = 5230,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xdf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xdf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6),
+  },
+  {     .freq                   = 5240,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
+  },
+  {     .freq                   = 5250,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4),
+  },
+  {     .freq                   = 5260,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3),
+  },
+  {     .freq                   = 5270,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xcf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xcf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2),
+  },
+  {     .freq                   = 5280,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1),
+  },
+  {     .freq                   = 5290,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xbf, 0x00, 0x0a, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfc, 0x00, 0xbf, 0x00, 0x0a, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfc, 0x00),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0),
+  },
+  {     .freq                   = 5300,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0),
+  },
+  {     .freq                   = 5310,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef),
+  },
+  {     .freq                   = 5320,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xbf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0xbf, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee),
+  },
+  {     .freq                   = 5330,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed),
+  },
+  {     .freq                   = 5340,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xaf, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0xaf, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec),
+  },
+  {     .freq                   = 5350,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb),
+  },
+  {     .freq                   = 5360,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea),
+  },
+  {     .freq                   = 5370,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9),
+  },
+  {     .freq                   = 5380,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x9f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0x9f, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8),
+  },
+  {     .freq                   = 5390,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x8f, 0x00, 0x08, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xfa, 0x00, 0x8f, 0x00, 0x08, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xfa, 0x00),
+        PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7),
+  },
+  {     .freq                   = 5400,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8f, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x8f, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6),
+  },
+  {     .freq                   = 5410,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8f, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x8f, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5),
+  },
+  {     .freq                   = 5420,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x8e, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5),
+  },
+  {     .freq                   = 5430,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x8e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x8e, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4),
+  },
+  {     .freq                   = 5440,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x7e, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x7e, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3),
+  },
+  {     .freq                   = 5450,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x7d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x7d, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2),
+  },
+  {     .freq                   = 5460,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x6d, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1),
+  },
+  {     .freq                   = 5470,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x6d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x6d, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0),
+  },
+  {     .freq                   = 5480,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x5d, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x5d, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df),
+  },
+  {     .freq                   = 5490,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x5c, 0x00, 0x07, 0x00, 0x7f, 0x00, 0x0f,
+                   0x00, 0xf8, 0x00, 0x5c, 0x00, 0x07, 0x00, 0x7f,
+                   0x00, 0x0f, 0x00, 0xf8, 0x00),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de),
+  },
+  {     .freq                   = 5500,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x5c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x5c, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd),
+  },
+  {     .freq                   = 5510,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd),
+  },
+  {     .freq                   = 5520,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x4c, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x4c, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc),
+  },
+  {     .freq                   = 5530,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db),
+  },
+  {     .freq                   = 5540,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da),
+  },
+  {     .freq                   = 5550,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x3b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x3b, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9),
+  },
+  {     .freq                   = 5560,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x2b, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x2b, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8),
+  },
+  {     .freq                   = 5570,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x2a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x2a, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7),
+  },
+  {     .freq                   = 5580,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7),
+  },
+  {     .freq                   = 5590,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x1a, 0x00, 0x06, 0x00, 0x7f, 0x00, 0x0d,
+                   0x00, 0xf6, 0x00, 0x1a, 0x00, 0x06, 0x00, 0x7f,
+                   0x00, 0x0d, 0x00, 0xf6, 0x00),
+        PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6),
+  },
+  {     .freq                   = 5600,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x1a, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x1a, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5),
+  },
+  {     .freq                   = 5610,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4),
+  },
+  {     .freq                   = 5620,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x19, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x19, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3),
+  },
+  {     .freq                   = 5630,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2),
+  },
+  {     .freq                   = 5640,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x09, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x09, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2),
+  },
+  {     .freq                   = 5650,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1),
+  },
+  {     .freq                   = 5660,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0),
+  },
+  {     .freq                   = 5670,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf),
+  },
+  {     .freq                   = 5680,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x08, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x08, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce),
+  },
+  {     .freq                   = 5690,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x07, 0x00, 0x04, 0x00, 0x7f, 0x00, 0x0b,
+                   0x00, 0xf4, 0x00, 0x07, 0x00, 0x04, 0x00, 0x7f,
+                   0x00, 0x0b, 0x00, 0xf4, 0x00),
+        PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce),
+  },
+  {     .freq                   = 5700,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd),
+  },
+  {     .freq                   = 5710,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc),
+  },
+  {     .freq                   = 5720,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x07, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x07, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5725,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5730,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5735,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5740,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9),
+  },
+  {     .freq                   = 5745,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5750,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x06, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x06, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5755,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8),
+  },
+  {     .freq                   = 5760,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5765,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5770,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5775,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5780,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x05, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x05, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6),
+  },
+  {     .freq                   = 5785,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5790,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5795,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x04, 0x00, 0x03, 0x00, 0x7f, 0x00, 0x0a,
+                   0x00, 0xf2, 0x00, 0x04, 0x00, 0x03, 0x00, 0x7f,
+                   0x00, 0x0a, 0x00, 0xf2, 0x00),
+        PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5800,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5805,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
+  },
+  {     .freq                   = 5810,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5815,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x04, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x04, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5820,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5825,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5830,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2),
+  },
+  {     .freq                   = 5840,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2),
+  },
+  {     .freq                   = 5850,
+        RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1),
+  },
+  {     .freq                   = 5860,
+        RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x03, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x03, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0),
+  },
+  {     .freq                   = 5870,
+        RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf),
+  },
+  {     .freq                   = 5880,
+        RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf),
+  },
+  {     .freq                   = 5890,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x02, 0x00, 0x02, 0x00, 0x7f, 0x00, 0x09,
+                   0x00, 0xf0, 0x00, 0x02, 0x00, 0x02, 0x00, 0x7f,
+                   0x00, 0x09, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be),
+  },
+  {     .freq                   = 5900,
+        RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00,
+                   0x00, 0x02, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf0, 0x00, 0x02, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf0, 0x00),
+        PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd),
+  },
+  {     .freq                   = 5910,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00,
+                   0x00, 0x01, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x07,
+                   0x00, 0xf0, 0x00, 0x01, 0x00, 0x00, 0x00, 0x7f,
+                   0x00, 0x07, 0x00, 0xf0, 0x00),
+        PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc),
+  },
+  {     .freq                   = 2412,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
+  },
+  {     .freq                   = 2417,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
+  },
+  {     .freq                   = 2422,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xff, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xff, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
+  },
+  {     .freq                   = 2427,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xfd, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xfd, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
+  },
+  {     .freq                   = 2432,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xfb, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xfb, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
+  },
+  {     .freq                   = 2437,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xfa, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
+  },
+  {     .freq                   = 2442,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf8, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf8, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
+  },
+  {     .freq                   = 2447,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf7, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf7, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
+  },
+  {     .freq                   = 2452,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf6, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf6, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
+  },
+  {     .freq                   = 2457,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf5, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf5, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
+  },
+  {     .freq                   = 2462,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf4, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf4, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
+  },
+  {     .freq                   = 2467,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf3, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf3, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
+  },
+  {     .freq                   = 2472,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf2, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf2, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
+  },
+  {     .freq                   = 2484,
+        RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0xf0, 0x00, 0x04, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0e, 0x00, 0xf0, 0x00, 0x04, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0e),
+        PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
+  },
+};
+
+static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_rev5[] = {
+  {     .freq                   = 4920,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216),
+  },
+  {     .freq                   = 4930,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215),
+  },
+  {     .freq                   = 4940,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214),
+  },
+  {     .freq                   = 4950,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213),
+  },
+  {     .freq                   = 4960,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212),
+  },
+  {     .freq                   = 4970,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211),
+  },
+  {     .freq                   = 4980,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f),
+  },
+  {     .freq                   = 4990,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e),
+  },
+  {     .freq                   = 5000,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d),
+  },
+  {     .freq                   = 5010,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c),
+  },
+  {     .freq                   = 5020,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b),
+  },
+  {     .freq                   = 5030,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a),
+  },
+  {     .freq                   = 5040,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209),
+  },
+  {     .freq                   = 5050,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208),
+  },
+  {     .freq                   = 5060,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207),
+  },
+  {     .freq                   = 5070,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206),
+  },
+  {     .freq                   = 5080,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205),
+  },
+  {     .freq                   = 5090,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204),
+  },
+  {     .freq                   = 5100,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203),
+  },
+  {     .freq                   = 5110,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202),
+  },
+  {     .freq                   = 5120,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201),
+  },
+  {     .freq                   = 5130,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a,
+                   0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200),
+  },
+  {     .freq                   = 5140,
+        RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a,
+                   0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff),
+  },
+  {     .freq                   = 5160,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd),
+  },
+  {     .freq                   = 5170,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc),
+  },
+  {     .freq                   = 5180,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
+  },
+  {     .freq                   = 5190,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa),
+  },
+  {     .freq                   = 5200,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
+  },
+  {     .freq                   = 5210,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8),
+  },
+  {     .freq                   = 5220,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
+  },
+  {     .freq                   = 5230,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6),
+  },
+  {     .freq                   = 5240,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6d, 0x00),
+        PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
+  },
+  {     .freq                   = 5250,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6d, 0x00),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4),
+  },
+  {     .freq                   = 5260,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6d, 0x00),
+        PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3),
+  },
+  {     .freq                   = 5270,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2),
+  },
+  {     .freq                   = 5280,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1),
+  },
+  {     .freq                   = 5290,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0f, 0x00,
+                   0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0),
+  },
+  {     .freq                   = 5300,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0),
+  },
+  {     .freq                   = 5310,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef),
+  },
+  {     .freq                   = 5320,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xb8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xb8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee),
+  },
+  {     .freq                   = 5330,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xb7, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9b, 0x00, 0xb7, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed),
+  },
+  {     .freq                   = 5340,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xb7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9b, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6b, 0x00),
+        PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec),
+  },
+  {     .freq                   = 5350,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xa7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9b, 0x00, 0xa7, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb),
+  },
+  {     .freq                   = 5360,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea),
+  },
+  {     .freq                   = 5370,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x5b, 0x00),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9),
+  },
+  {     .freq                   = 5380,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x96, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9a, 0x00, 0x96, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x5a, 0x00),
+        PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8),
+  },
+  {     .freq                   = 5390,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8f, 0x0e, 0x00,
+                   0xff, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x5a, 0x00),
+        PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7),
+  },
+  {     .freq                   = 5400,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x5a, 0x00),
+        PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6),
+  },
+  {     .freq                   = 5410,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x5a, 0x00),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5),
+  },
+  {     .freq                   = 5420,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x5a, 0x00),
+        PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5),
+  },
+  {     .freq                   = 5430,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x85, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x99, 0x00, 0x85, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x59, 0x00),
+        PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4),
+  },
+  {     .freq                   = 5440,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x59, 0x00),
+        PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3),
+  },
+  {     .freq                   = 5450,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x59, 0x00),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2),
+  },
+  {     .freq                   = 5460,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1),
+  },
+  {     .freq                   = 5470,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x74, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x99, 0x00, 0x74, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0),
+  },
+  {     .freq                   = 5480,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df),
+  },
+  {     .freq                   = 5490,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0d, 0x00,
+                   0xc8, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de),
+  },
+  {     .freq                   = 5500,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd),
+  },
+  {     .freq                   = 5510,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd),
+  },
+  {     .freq                   = 5520,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc),
+  },
+  {     .freq                   = 5530,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x63, 0x00, 0x01, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x98, 0x00, 0x63, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x78, 0x00),
+        PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db),
+  },
+  {     .freq                   = 5540,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x77, 0x00),
+        PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da),
+  },
+  {     .freq                   = 5550,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x77, 0x00),
+        PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9),
+  },
+  {     .freq                   = 5560,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x77, 0x00),
+        PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8),
+  },
+  {     .freq                   = 5570,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7),
+  },
+  {     .freq                   = 5580,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7),
+  },
+  {     .freq                   = 5590,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8d, 0x0b, 0x00,
+                   0x84, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6),
+  },
+  {     .freq                   = 5600,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5),
+  },
+  {     .freq                   = 5610,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4),
+  },
+  {     .freq                   = 5620,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3),
+  },
+  {     .freq                   = 5630,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2),
+  },
+  {     .freq                   = 5640,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x95, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x75, 0x00),
+        PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2),
+  },
+  {     .freq                   = 5650,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x75, 0x00),
+        PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1),
+  },
+  {     .freq                   = 5660,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x75, 0x00),
+        PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0),
+  },
+  {     .freq                   = 5670,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf),
+  },
+  {     .freq                   = 5680,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce),
+  },
+  {     .freq                   = 5690,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8b, 0x09, 0x00,
+                   0x70, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce),
+  },
+  {     .freq                   = 5700,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd),
+  },
+  {     .freq                   = 5710,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc),
+  },
+  {     .freq                   = 5720,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5725,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x74, 0x00),
+        PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5730,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x84, 0x00),
+        PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5735,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x83, 0x00),
+        PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5740,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x83, 0x00),
+        PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9),
+  },
+  {     .freq                   = 5745,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x83, 0x00),
+        PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5750,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x83, 0x00),
+        PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5755,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x83, 0x00),
+        PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8),
+  },
+  {     .freq                   = 5760,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x83, 0x00),
+        PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5765,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5770,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5775,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5780,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x8a, 0x06, 0x00,
+                   0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6),
+  },
+  {     .freq                   = 5785,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5790,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5795,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x8a, 0x06, 0x00,
+                   0x40, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5800,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5805,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
+  },
+  {     .freq                   = 5810,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5815,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5820,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5825,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x82, 0x00),
+        PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5830,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x72, 0x00),
+        PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2),
+  },
+  {     .freq                   = 5840,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x72, 0x00),
+        PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2),
+  },
+  {     .freq                   = 5850,
+        RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x72, 0x00),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1),
+  },
+  {     .freq                   = 5860,
+        RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x72, 0x00),
+        PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0),
+  },
+  {     .freq                   = 5870,
+        RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x71, 0x00),
+        PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf),
+  },
+  {     .freq                   = 5880,
+        RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x71, 0x00),
+        PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf),
+  },
+  {     .freq                   = 5890,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x88, 0x04, 0x00,
+                   0x20, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x71, 0x00),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be),
+  },
+  {     .freq                   = 5900,
+        RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x71, 0x00),
+        PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd),
+  },
+  {     .freq                   = 5910,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x87, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x71, 0x00),
+        PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc),
+  },
+  {     .freq                   = 2412,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0b, 0x00, 0x1f, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0b),
+        PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
+  },
+  {     .freq                   = 2417,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x1f, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0a, 0x00, 0x1f, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0a),
+        PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
+  },
+  {     .freq                   = 2422,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x0e, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0a, 0x00, 0x0e, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0a),
+        PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
+  },
+  {     .freq                   = 2427,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x0d, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x0d, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
+  },
+  {     .freq                   = 2432,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x0c, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x0c, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
+  },
+  {     .freq                   = 2437,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x0b, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
+  },
+  {     .freq                   = 2442,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x09, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x09, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
+  },
+  {     .freq                   = 2447,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x08, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x09, 0x00, 0x08, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x09),
+        PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
+  },
+  {     .freq                   = 2452,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x07, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x09, 0x00, 0x07, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x09),
+        PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
+  },
+  {     .freq                   = 2457,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x06, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x09, 0x00, 0x06, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x09),
+        PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
+  },
+  {     .freq                   = 2462,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x05, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x09, 0x00, 0x05, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x09),
+        PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
+  },
+  {     .freq                   = 2467,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x08, 0x00, 0x04, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x08),
+        PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
+  },
+  {     .freq                   = 2472,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x03, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x08, 0x00, 0x03, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x08),
+        PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
+  },
+  {     .freq                   = 2484,
+        RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x08),
+        PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
+  },
+};
+
+static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_rev6[] = {
+  {     .freq                   = 4920,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216),
+  },
+  {     .freq                   = 4930,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215),
+  },
+  {     .freq                   = 4940,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214),
+  },
+  {     .freq                   = 4950,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213),
+  },
+  {     .freq                   = 4960,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212),
+  },
+  {     .freq                   = 4970,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211),
+  },
+  {     .freq                   = 4980,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f),
+  },
+  {     .freq                   = 4990,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e),
+  },
+  {     .freq                   = 5000,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d),
+  },
+  {     .freq                   = 5010,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c),
+  },
+  {     .freq                   = 5020,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b),
+  },
+  {     .freq                   = 5030,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a),
+  },
+  {     .freq                   = 5040,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209),
+  },
+  {     .freq                   = 5050,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208),
+  },
+  {     .freq                   = 5060,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207),
+  },
+  {     .freq                   = 5070,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206),
+  },
+  {     .freq                   = 5080,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205),
+  },
+  {     .freq                   = 5090,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204),
+  },
+  {     .freq                   = 5100,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203),
+  },
+  {     .freq                   = 5110,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202),
+  },
+  {     .freq                   = 5120,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201),
+  },
+  {     .freq                   = 5130,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200),
+  },
+  {     .freq                   = 5140,
+        RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff),
+  },
+  {     .freq                   = 5160,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
+                   0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd),
+  },
+  {     .freq                   = 5170,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
+                   0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc),
+  },
+  {     .freq                   = 5180,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
+  },
+  {     .freq                   = 5190,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa),
+  },
+  {     .freq                   = 5200,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
+  },
+  {     .freq                   = 5210,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8),
+  },
+  {     .freq                   = 5220,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
+  },
+  {     .freq                   = 5230,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6),
+  },
+  {     .freq                   = 5240,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
+  },
+  {     .freq                   = 5250,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4),
+  },
+  {     .freq                   = 5260,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00,
+                   0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3),
+  },
+  {     .freq                   = 5270,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00,
+                   0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2),
+  },
+  {     .freq                   = 5280,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1),
+  },
+  {     .freq                   = 5290,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0),
+  },
+  {     .freq                   = 5300,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0),
+  },
+  {     .freq                   = 5310,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef),
+  },
+  {     .freq                   = 5320,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee),
+  },
+  {     .freq                   = 5330,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b,
+                   0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed),
+  },
+  {     .freq                   = 5340,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b,
+                   0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec),
+  },
+  {     .freq                   = 5350,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b,
+                   0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb),
+  },
+  {     .freq                   = 5360,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea),
+  },
+  {     .freq                   = 5370,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9),
+  },
+  {     .freq                   = 5380,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8),
+  },
+  {     .freq                   = 5390,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7),
+  },
+  {     .freq                   = 5400,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6),
+  },
+  {     .freq                   = 5410,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5),
+  },
+  {     .freq                   = 5420,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5),
+  },
+  {     .freq                   = 5430,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00,
+                   0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4),
+  },
+  {     .freq                   = 5440,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3),
+  },
+  {     .freq                   = 5450,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2),
+  },
+  {     .freq                   = 5460,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1),
+  },
+  {     .freq                   = 5470,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0),
+  },
+  {     .freq                   = 5480,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df),
+  },
+  {     .freq                   = 5490,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de),
+  },
+  {     .freq                   = 5500,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd),
+  },
+  {     .freq                   = 5510,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd),
+  },
+  {     .freq                   = 5520,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc),
+  },
+  {     .freq                   = 5530,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00,
+                   0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db),
+  },
+  {     .freq                   = 5540,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00,
+                   0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da),
+  },
+  {     .freq                   = 5550,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9),
+  },
+  {     .freq                   = 5560,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8),
+  },
+  {     .freq                   = 5570,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7),
+  },
+  {     .freq                   = 5580,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00,
+                   0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7),
+  },
+  {     .freq                   = 5590,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00,
+                   0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6),
+  },
+  {     .freq                   = 5600,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5),
+  },
+  {     .freq                   = 5610,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4),
+  },
+  {     .freq                   = 5620,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3),
+  },
+  {     .freq                   = 5630,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2),
+  },
+  {     .freq                   = 5640,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2),
+  },
+  {     .freq                   = 5650,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1),
+  },
+  {     .freq                   = 5660,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0),
+  },
+  {     .freq                   = 5670,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf),
+  },
+  {     .freq                   = 5680,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce),
+  },
+  {     .freq                   = 5690,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce),
+  },
+  {     .freq                   = 5700,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd),
+  },
+  {     .freq                   = 5710,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc),
+  },
+  {     .freq                   = 5720,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5725,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5730,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5735,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6d, 0x00),
+        PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5740,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6d, 0x00),
+        PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9),
+  },
+  {     .freq                   = 5745,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6d, 0x00),
+        PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5750,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6d, 0x00),
+        PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5755,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8),
+  },
+  {     .freq                   = 5760,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5765,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5770,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5775,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5780,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6),
+  },
+  {     .freq                   = 5785,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5790,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5795,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5800,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5805,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
+  },
+  {     .freq                   = 5810,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5815,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5820,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5825,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x69, 0x00),
+        PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5830,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x69, 0x00),
+        PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2),
+  },
+  {     .freq                   = 5840,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2),
+  },
+  {     .freq                   = 5850,
+        RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1),
+  },
+  {     .freq                   = 5860,
+        RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0),
+  },
+  {     .freq                   = 5870,
+        RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf),
+  },
+  {     .freq                   = 5880,
+        RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf),
+  },
+  {     .freq                   = 5890,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be),
+  },
+  {     .freq                   = 5900,
+        RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd),
+  },
+  {     .freq                   = 5910,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc),
+  },
+  {     .freq                   = 2412,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0b, 0x00, 0x0a),
+        PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
+  },
+  {     .freq                   = 2417,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0b, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0b, 0x00, 0x0a),
+        PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
+  },
+  {     .freq                   = 2422,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0b, 0x00, 0x0a, 0x00, 0x67, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0b, 0x00, 0x0a),
+        PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
+  },
+  {     .freq                   = 2427,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x57, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
+  },
+  {     .freq                   = 2432,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x56, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
+  },
+  {     .freq                   = 2437,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x46, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
+  },
+  {     .freq                   = 2442,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x45, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
+  },
+  {     .freq                   = 2447,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x09),
+        PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
+  },
+  {     .freq                   = 2452,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x09, 0x00, 0x23, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x09),
+        PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
+  },
+  {     .freq                   = 2457,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x09, 0x00, 0x12, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x09),
+        PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
+  },
+  {     .freq                   = 2462,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x02, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
+  },
+  {     .freq                   = 2467,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
+  },
+  {     .freq                   = 2472,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x01, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
+  },
+  {     .freq                   = 2484,
+        RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
+  },
+};
+
+static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_rev7_9[] = {
+  {     .freq                   = 4920,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0f,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216),
+  },
+  {     .freq                   = 4930,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215),
+  },
+  {     .freq                   = 4940,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214),
+  },
+  {     .freq                   = 4950,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0b, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0b, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213),
+  },
+  {     .freq                   = 4960,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0e,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212),
+  },
+  {     .freq                   = 4970,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211),
+  },
+  {     .freq                   = 4980,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f),
+  },
+  {     .freq                   = 4990,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e),
+  },
+  {     .freq                   = 5000,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d),
+  },
+  {     .freq                   = 5010,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x0a, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x0a, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c),
+  },
+  {     .freq                   = 5020,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0d,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b),
+  },
+  {     .freq                   = 5030,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xff, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xff, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a),
+  },
+  {     .freq                   = 5040,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209),
+  },
+  {     .freq                   = 5050,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208),
+  },
+  {     .freq                   = 5060,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x70, 0x00, 0x0c,
+                   0x00, 0x9f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x70,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207),
+  },
+  {     .freq                   = 5070,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206),
+  },
+  {     .freq                   = 5080,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205),
+  },
+  {     .freq                   = 5090,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204),
+  },
+  {     .freq                   = 5100,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203),
+  },
+  {     .freq                   = 5110,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202),
+  },
+  {     .freq                   = 5120,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0b,
+                   0x00, 0x9f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201),
+  },
+  {     .freq                   = 5130,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x08, 0x00, 0x70, 0x00, 0x0a,
+                   0x00, 0x9f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x70,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200),
+  },
+  {     .freq                   = 5140,
+        RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x0a,
+                   0x00, 0x9f, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff),
+  },
+  {     .freq                   = 5160,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x07, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfb, 0x00, 0x07, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd),
+  },
+  {     .freq                   = 5170,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfb, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc),
+  },
+  {     .freq                   = 5180,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
+  },
+  {     .freq                   = 5190,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa),
+  },
+  {     .freq                   = 5200,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
+  },
+  {     .freq                   = 5210,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8),
+  },
+  {     .freq                   = 5220,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xfe, 0xfa, 0x00, 0x06, 0x00, 0x70, 0x00, 0x09,
+                   0x00, 0x9e, 0x00, 0xfa, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x09, 0x00, 0x6e, 0x00),
+        PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
+  },
+  {     .freq                   = 5230,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xee, 0xea, 0x00, 0x06, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9e, 0x00, 0xea, 0x00, 0x06, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6e, 0x00),
+        PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6),
+  },
+  {     .freq                   = 5240,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xee, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6d, 0x00),
+        PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
+  },
+  {     .freq                   = 5250,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xed, 0xe9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9d, 0x00, 0xe9, 0x00, 0x05, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6d, 0x00),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4),
+  },
+  {     .freq                   = 5260,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00,
+                   0xed, 0xd9, 0x00, 0x05, 0x00, 0x70, 0x00, 0x08,
+                   0x00, 0x9d, 0x00, 0xd9, 0x00, 0x05, 0x00, 0x70,
+                   0x00, 0x08, 0x00, 0x6d, 0x00),
+        PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3),
+  },
+  {     .freq                   = 5270,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00,
+                   0xed, 0xd8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xd8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2),
+  },
+  {     .freq                   = 5280,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1),
+  },
+  {     .freq                   = 5290,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0),
+  },
+  {     .freq                   = 5300,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0),
+  },
+  {     .freq                   = 5310,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xc8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xc8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef),
+  },
+  {     .freq                   = 5320,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdb, 0xb8, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9c, 0x00, 0xb8, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee),
+  },
+  {     .freq                   = 5330,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xcb, 0xb7, 0x00, 0x04, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9b, 0x00, 0xb7, 0x00, 0x04, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed),
+  },
+  {     .freq                   = 5340,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xca, 0xb7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x07,
+                   0x00, 0x9b, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x07, 0x00, 0x6b, 0x00),
+        PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec),
+  },
+  {     .freq                   = 5350,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xca, 0xa7, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9b, 0x00, 0xa7, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb),
+  },
+  {     .freq                   = 5360,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xc9, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea),
+  },
+  {     .freq                   = 5370,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xc9, 0xa6, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9b, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x7b, 0x00),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9),
+  },
+  {     .freq                   = 5380,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x96, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9a, 0x00, 0x96, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x7a, 0x00),
+        PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8),
+  },
+  {     .freq                   = 5390,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x7a, 0x00),
+        PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7),
+  },
+  {     .freq                   = 5400,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x06,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x06, 0x00, 0x7a, 0x00),
+        PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6),
+  },
+  {     .freq                   = 5410,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb7, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x7a, 0x00),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5),
+  },
+  {     .freq                   = 5420,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xa7, 0x95, 0x00, 0x03, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x9a, 0x00, 0x95, 0x00, 0x03, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x7a, 0x00),
+        PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5),
+  },
+  {     .freq                   = 5430,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00,
+                   0xa6, 0x85, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x99, 0x00, 0x85, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x79, 0x00),
+        PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4),
+  },
+  {     .freq                   = 5440,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0xa6, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x79, 0x00),
+        PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3),
+  },
+  {     .freq                   = 5450,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x95, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x05,
+                   0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x05, 0x00, 0x79, 0x00),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2),
+  },
+  {     .freq                   = 5460,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x95, 0x84, 0x00, 0x02, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x99, 0x00, 0x84, 0x00, 0x02, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x79, 0x00),
+        PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1),
+  },
+  {     .freq                   = 5470,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x94, 0x74, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x99, 0x00, 0x74, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x79, 0x00),
+        PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0),
+  },
+  {     .freq                   = 5480,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x84, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df),
+  },
+  {     .freq                   = 5490,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x83, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de),
+  },
+  {     .freq                   = 5500,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x82, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd),
+  },
+  {     .freq                   = 5510,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x82, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd),
+  },
+  {     .freq                   = 5520,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x72, 0x73, 0x00, 0x01, 0x00, 0x70, 0x00, 0x04,
+                   0x00, 0x98, 0x00, 0x73, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x04, 0x00, 0x78, 0x00),
+        PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc),
+  },
+  {     .freq                   = 5530,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00,
+                   0x72, 0x63, 0x00, 0x01, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x98, 0x00, 0x63, 0x00, 0x01, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x78, 0x00),
+        PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db),
+  },
+  {     .freq                   = 5540,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00,
+                   0x71, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x77, 0x00),
+        PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da),
+  },
+  {     .freq                   = 5550,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x77, 0x00),
+        PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9),
+  },
+  {     .freq                   = 5560,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x62, 0x00, 0x00, 0x00, 0x70, 0x00, 0x03,
+                   0x00, 0x97, 0x00, 0x62, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x03, 0x00, 0x77, 0x00),
+        PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8),
+  },
+  {     .freq                   = 5570,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x76, 0x00),
+        PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7),
+  },
+  {     .freq                   = 5580,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00,
+                   0x60, 0x52, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x52, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x86, 0x00),
+        PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7),
+  },
+  {     .freq                   = 5590,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x86, 0x00),
+        PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6),
+  },
+  {     .freq                   = 5600,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x86, 0x00),
+        PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5),
+  },
+  {     .freq                   = 5610,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x86, 0x00),
+        PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4),
+  },
+  {     .freq                   = 5620,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x86, 0x00),
+        PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3),
+  },
+  {     .freq                   = 5630,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x96, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x86, 0x00),
+        PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2),
+  },
+  {     .freq                   = 5640,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x51, 0x00, 0x00, 0x00, 0x70, 0x00, 0x02,
+                   0x00, 0x95, 0x00, 0x51, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x02, 0x00, 0x85, 0x00),
+        PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2),
+  },
+  {     .freq                   = 5650,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x85, 0x00),
+        PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1),
+  },
+  {     .freq                   = 5660,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x50, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x95, 0x00, 0x50, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x85, 0x00),
+        PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0),
+  },
+  {     .freq                   = 5670,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x84, 0x00),
+        PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf),
+  },
+  {     .freq                   = 5680,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x84, 0x00),
+        PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce),
+  },
+  {     .freq                   = 5690,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x94, 0x00),
+        PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce),
+  },
+  {     .freq                   = 5700,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x94, 0x00),
+        PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd),
+  },
+  {     .freq                   = 5710,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x94, 0x00),
+        PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc),
+  },
+  {     .freq                   = 5720,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x94, 0x00),
+        PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5725,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x94, 0x00),
+        PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5730,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x01,
+                   0x00, 0x94, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x01, 0x00, 0x94, 0x00),
+        PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5735,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x93, 0x00),
+        PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5740,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x93, 0x00),
+        PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9),
+  },
+  {     .freq                   = 5745,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x93, 0x00),
+        PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5750,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x93, 0x00),
+        PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5755,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x10, 0x30, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x30, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x93, 0x00),
+        PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8),
+  },
+  {     .freq                   = 5760,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x93, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x93, 0x00),
+        PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5765,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5770,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5775,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x20, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5780,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6),
+  },
+  {     .freq                   = 5785,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5790,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5795,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5800,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5805,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
+  },
+  {     .freq                   = 5810,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5815,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5820,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5825,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5830,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2),
+  },
+  {     .freq                   = 5840,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x10, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2),
+  },
+  {     .freq                   = 5850,
+        RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1),
+  },
+  {     .freq                   = 5860,
+        RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x92, 0x00),
+        PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0),
+  },
+  {     .freq                   = 5870,
+        RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x91, 0x00),
+        PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf),
+  },
+  {     .freq                   = 5880,
+        RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x91, 0x00),
+        PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf),
+  },
+  {     .freq                   = 5890,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x91, 0x00),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be),
+  },
+  {     .freq                   = 5900,
+        RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x91, 0x00),
+        PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd),
+  },
+  {     .freq                   = 5910,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00,
+                   0x00, 0x91, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
+                   0x00, 0x00, 0x00, 0x91, 0x00),
+        PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc),
+  },
+  {     .freq                   = 2412,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0b, 0x00, 0x89, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0b),
+        PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
+  },
+  {     .freq                   = 2417,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0a),
+        PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
+  },
+  {     .freq                   = 2422,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x89, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0f, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0f, 0x00, 0x0a),
+        PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
+  },
+  {     .freq                   = 2427,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
+  },
+  {     .freq                   = 2432,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x77, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
+  },
+  {     .freq                   = 2437,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x76, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
+  },
+  {     .freq                   = 2442,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x66, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x0a),
+        PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
+  },
+  {     .freq                   = 2447,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x55, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x09),
+        PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
+  },
+  {     .freq                   = 2452,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0e, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0e, 0x00, 0x09),
+        PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
+  },
+  {     .freq                   = 2457,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x09),
+        PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
+  },
+  {     .freq                   = 2462,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x33, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x09),
+        PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
+  },
+  {     .freq                   = 2467,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x22, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x08, 0x00, 0x22, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x08),
+        PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
+  },
+  {     .freq                   = 2472,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x08, 0x00, 0x11, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x08),
+        PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
+  },
+  {     .freq                   = 2484,
+        RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0d, 0x00, 0x08, 0x00, 0x00, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0d, 0x00, 0x08),
+        PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
+  },
 };
 
+static const struct b43_nphy_channeltab_entry_rev3 b43_nphy_channeltab_rev8[] = {
+  {     .freq                   = 4920,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xec, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b4, 0x07b0, 0x07ac, 0x0214, 0x0215, 0x0216),
+  },
+  {     .freq                   = 4930,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xed, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07b8, 0x07b4, 0x07b0, 0x0213, 0x0214, 0x0215),
+  },
+  {     .freq                   = 4940,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xee, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07bc, 0x07b8, 0x07b4, 0x0212, 0x0213, 0x0214),
+  },
+  {     .freq                   = 4950,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xef, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x00, 0x00, 0x00, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c0, 0x07bc, 0x07b8, 0x0211, 0x0212, 0x0213),
+  },
+  {     .freq                   = 4960,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf0, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c4, 0x07c0, 0x07bc, 0x020f, 0x0211, 0x0212),
+  },
+  {     .freq                   = 4970,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf1, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07c8, 0x07c4, 0x07c0, 0x020e, 0x020f, 0x0211),
+  },
+  {     .freq                   = 4980,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf2, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07cc, 0x07c8, 0x07c4, 0x020d, 0x020e, 0x020f),
+  },
+  {     .freq                   = 4990,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf3, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d0, 0x07cc, 0x07c8, 0x020c, 0x020d, 0x020e),
+  },
+  {     .freq                   = 5000,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf4, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d4, 0x07d0, 0x07cc, 0x020b, 0x020c, 0x020d),
+  },
+  {     .freq                   = 5010,
+        RADIOREGS3(0xff, 0x01, 0x01, 0x01, 0xf5, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07d8, 0x07d4, 0x07d0, 0x020a, 0x020b, 0x020c),
+  },
+  {     .freq                   = 5020,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf6, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07dc, 0x07d8, 0x07d4, 0x0209, 0x020a, 0x020b),
+  },
+  {     .freq                   = 5030,
+        RADIOREGS3(0xf7, 0x01, 0x01, 0x01, 0xf7, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e0, 0x07dc, 0x07d8, 0x0208, 0x0209, 0x020a),
+  },
+  {     .freq                   = 5040,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf8, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e4, 0x07e0, 0x07dc, 0x0207, 0x0208, 0x0209),
+  },
+  {     .freq                   = 5050,
+        RADIOREGS3(0xef, 0x01, 0x01, 0x01, 0xf9, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07e8, 0x07e4, 0x07e0, 0x0206, 0x0207, 0x0208),
+  },
+  {     .freq                   = 5060,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfa, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfe, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfe, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07ec, 0x07e8, 0x07e4, 0x0205, 0x0206, 0x0207),
+  },
+  {     .freq                   = 5070,
+        RADIOREGS3(0xe6, 0x01, 0x01, 0x01, 0xfb, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f0, 0x07ec, 0x07e8, 0x0204, 0x0205, 0x0206),
+  },
+  {     .freq                   = 5080,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfc, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f4, 0x07f0, 0x07ec, 0x0203, 0x0204, 0x0205),
+  },
+  {     .freq                   = 5090,
+        RADIOREGS3(0xde, 0x01, 0x01, 0x01, 0xfd, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x01, 0x01, 0x01, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x09, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x09, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07f8, 0x07f4, 0x07f0, 0x0202, 0x0203, 0x0204),
+  },
+  {     .freq                   = 5100,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xfe, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfd, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfd, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x07fc, 0x07f8, 0x07f4, 0x0201, 0x0202, 0x0203),
+  },
+  {     .freq                   = 5110,
+        RADIOREGS3(0xd6, 0x01, 0x01, 0x01, 0xff, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0800, 0x07fc, 0x07f8, 0x0200, 0x0201, 0x0202),
+  },
+  {     .freq                   = 5120,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x00, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0804, 0x0800, 0x07fc, 0x01ff, 0x0200, 0x0201),
+  },
+  {     .freq                   = 5130,
+        RADIOREGS3(0xce, 0x01, 0x01, 0x02, 0x01, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfc, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfc, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0808, 0x0804, 0x0800, 0x01fe, 0x01ff, 0x0200),
+  },
+  {     .freq                   = 5140,
+        RADIOREGS3(0xc6, 0x01, 0x01, 0x02, 0x02, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfb, 0x00, 0x08, 0x00, 0x77, 0x00, 0x0f,
+                   0x00, 0x6f, 0x00, 0xfb, 0x00, 0x08, 0x00, 0x77,
+                   0x00, 0x0f, 0x00, 0x6f, 0x00),
+        PHYREGS(0x080c, 0x0808, 0x0804, 0x01fd, 0x01fe, 0x01ff),
+  },
+  {     .freq                   = 5160,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x04, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
+                   0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0814, 0x0810, 0x080c, 0x01fb, 0x01fc, 0x01fd),
+  },
+  {     .freq                   = 5170,
+        RADIOREGS3(0xbe, 0x01, 0x01, 0x02, 0x05, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xfa, 0x00, 0x07, 0x00, 0x77, 0x00, 0x0e,
+                   0x00, 0x6f, 0x00, 0xfa, 0x00, 0x07, 0x00, 0x77,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0818, 0x0814, 0x0810, 0x01fa, 0x01fb, 0x01fc),
+  },
+  {     .freq                   = 5180,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x06, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0e,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77,
+                   0x00, 0x0e, 0x00, 0x6f, 0x00),
+        PHYREGS(0x081c, 0x0818, 0x0814, 0x01f9, 0x01fa, 0x01fb),
+  },
+  {     .freq                   = 5190,
+        RADIOREGS3(0xb6, 0x01, 0x01, 0x02, 0x07, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x06, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x06, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0820, 0x081c, 0x0818, 0x01f8, 0x01f9, 0x01fa),
+  },
+  {     .freq                   = 5200,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x08, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0824, 0x0820, 0x081c, 0x01f7, 0x01f8, 0x01f9),
+  },
+  {     .freq                   = 5210,
+        RADIOREGS3(0xaf, 0x01, 0x01, 0x02, 0x09, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8f, 0x0f, 0x00,
+                   0xff, 0xf9, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xf9, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0828, 0x0824, 0x0820, 0x01f6, 0x01f7, 0x01f8),
+  },
+  {     .freq                   = 5220,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xfe, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x082c, 0x0828, 0x0824, 0x01f5, 0x01f6, 0x01f7),
+  },
+  {     .freq                   = 5230,
+        RADIOREGS3(0xa7, 0x01, 0x01, 0x02, 0x0b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xee, 0xd8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xd8, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0830, 0x082c, 0x0828, 0x01f4, 0x01f5, 0x01f6),
+  },
+  {     .freq                   = 5240,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xee, 0xc8, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xc8, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0834, 0x0830, 0x082c, 0x01f3, 0x01f4, 0x01f5),
+  },
+  {     .freq                   = 5250,
+        RADIOREGS3(0xa0, 0x01, 0x01, 0x02, 0x0d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0f, 0x00,
+                   0xed, 0xc7, 0x00, 0x05, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xc7, 0x00, 0x05, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0838, 0x0834, 0x0830, 0x01f2, 0x01f3, 0x01f4),
+  },
+  {     .freq                   = 5260,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x02, 0x02, 0x02, 0x8e, 0x0e, 0x00,
+                   0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0d,
+                   0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77,
+                   0x00, 0x0d, 0x00, 0x6f, 0x00),
+        PHYREGS(0x083c, 0x0838, 0x0834, 0x01f1, 0x01f2, 0x01f3),
+  },
+  {     .freq                   = 5270,
+        RADIOREGS3(0x98, 0x01, 0x01, 0x02, 0x0f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8e, 0x0e, 0x00,
+                   0xed, 0xc7, 0x00, 0x04, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xc7, 0x00, 0x04, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0840, 0x083c, 0x0838, 0x01f0, 0x01f1, 0x01f2),
+  },
+  {     .freq                   = 5280,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x10, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0844, 0x0840, 0x083c, 0x01f0, 0x01f0, 0x01f1),
+  },
+  {     .freq                   = 5290,
+        RADIOREGS3(0x91, 0x01, 0x01, 0x02, 0x11, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0848, 0x0844, 0x0840, 0x01ef, 0x01f0, 0x01f0),
+  },
+  {     .freq                   = 5300,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x12, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x084c, 0x0848, 0x0844, 0x01ee, 0x01ef, 0x01f0),
+  },
+  {     .freq                   = 5310,
+        RADIOREGS3(0x8a, 0x01, 0x01, 0x02, 0x13, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdc, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0850, 0x084c, 0x0848, 0x01ed, 0x01ee, 0x01ef),
+  },
+  {     .freq                   = 5320,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x14, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0e, 0x00,
+                   0xdb, 0xb7, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0c,
+                   0x00, 0x6f, 0x00, 0xb7, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0c, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0854, 0x0850, 0x084c, 0x01ec, 0x01ed, 0x01ee),
+  },
+  {     .freq                   = 5330,
+        RADIOREGS3(0x83, 0x01, 0x01, 0x02, 0x15, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xcb, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b,
+                   0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0858, 0x0854, 0x0850, 0x01eb, 0x01ec, 0x01ed),
+  },
+  {     .freq                   = 5340,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x16, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8d, 0x0d, 0x00,
+                   0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b,
+                   0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x085c, 0x0858, 0x0854, 0x01ea, 0x01eb, 0x01ec),
+  },
+  {     .freq                   = 5350,
+        RADIOREGS3(0x7c, 0x01, 0x01, 0x02, 0x17, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xca, 0xa6, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0b,
+                   0x00, 0x6f, 0x00, 0xa6, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0b, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0860, 0x085c, 0x0858, 0x01e9, 0x01ea, 0x01eb),
+  },
+  {     .freq                   = 5360,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x18, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0864, 0x0860, 0x085c, 0x01e8, 0x01e9, 0x01ea),
+  },
+  {     .freq                   = 5370,
+        RADIOREGS3(0x75, 0x01, 0x01, 0x02, 0x19, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0d, 0x00,
+                   0xc9, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0868, 0x0864, 0x0860, 0x01e7, 0x01e8, 0x01e9),
+  },
+  {     .freq                   = 5380,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x95, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x95, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x086c, 0x0868, 0x0864, 0x01e6, 0x01e7, 0x01e8),
+  },
+  {     .freq                   = 5390,
+        RADIOREGS3(0x6e, 0x01, 0x01, 0x02, 0x1b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0870, 0x086c, 0x0868, 0x01e5, 0x01e6, 0x01e7),
+  },
+  {     .freq                   = 5400,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb8, 0x84, 0x00, 0x03, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x03, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0874, 0x0870, 0x086c, 0x01e5, 0x01e5, 0x01e6),
+  },
+  {     .freq                   = 5410,
+        RADIOREGS3(0x67, 0x01, 0x01, 0x02, 0x1d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xb7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0878, 0x0874, 0x0870, 0x01e4, 0x01e5, 0x01e5),
+  },
+  {     .freq                   = 5420,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0c, 0x00,
+                   0xa7, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x087c, 0x0878, 0x0874, 0x01e3, 0x01e4, 0x01e5),
+  },
+  {     .freq                   = 5430,
+        RADIOREGS3(0x61, 0x01, 0x01, 0x02, 0x1f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x03, 0x03, 0x03, 0x8c, 0x0b, 0x00,
+                   0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x0a,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x0a, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0880, 0x087c, 0x0878, 0x01e2, 0x01e3, 0x01e4),
+  },
+  {     .freq                   = 5440,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x20, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0xa6, 0x84, 0x00, 0x02, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x02, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0884, 0x0880, 0x087c, 0x01e1, 0x01e2, 0x01e3),
+  },
+  {     .freq                   = 5450,
+        RADIOREGS3(0x5a, 0x01, 0x01, 0x02, 0x21, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0888, 0x0884, 0x0880, 0x01e0, 0x01e1, 0x01e2),
+  },
+  {     .freq                   = 5460,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x22, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x95, 0x84, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x84, 0x00, 0x01, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x088c, 0x0888, 0x0884, 0x01df, 0x01e0, 0x01e1),
+  },
+  {     .freq                   = 5470,
+        RADIOREGS3(0x53, 0x01, 0x01, 0x02, 0x23, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8b, 0x0b, 0x00,
+                   0x94, 0x73, 0x00, 0x01, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x01, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0890, 0x088c, 0x0888, 0x01de, 0x01df, 0x01e0),
+  },
+  {     .freq                   = 5480,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x24, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x84, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0894, 0x0890, 0x088c, 0x01dd, 0x01de, 0x01df),
+  },
+  {     .freq                   = 5490,
+        RADIOREGS3(0x4d, 0x01, 0x01, 0x02, 0x25, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x83, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x0898, 0x0894, 0x0890, 0x01dd, 0x01dd, 0x01de),
+  },
+  {     .freq                   = 5500,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x26, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x089c, 0x0898, 0x0894, 0x01dc, 0x01dd, 0x01dd),
+  },
+  {     .freq                   = 5510,
+        RADIOREGS3(0x47, 0x01, 0x01, 0x02, 0x27, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x82, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08a0, 0x089c, 0x0898, 0x01db, 0x01dc, 0x01dd),
+  },
+  {     .freq                   = 5520,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x28, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x0a, 0x00,
+                   0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08a4, 0x08a0, 0x089c, 0x01da, 0x01db, 0x01dc),
+  },
+  {     .freq                   = 5530,
+        RADIOREGS3(0x40, 0x01, 0x01, 0x02, 0x29, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00,
+                   0x72, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08a8, 0x08a4, 0x08a0, 0x01d9, 0x01da, 0x01db),
+  },
+  {     .freq                   = 5540,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x8a, 0x09, 0x00,
+                   0x71, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08ac, 0x08a8, 0x08a4, 0x01d8, 0x01d9, 0x01da),
+  },
+  {     .freq                   = 5550,
+        RADIOREGS3(0x3a, 0x01, 0x01, 0x02, 0x2b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08b0, 0x08ac, 0x08a8, 0x01d7, 0x01d8, 0x01d9),
+  },
+  {     .freq                   = 5560,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x73, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x73, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08b4, 0x08b0, 0x08ac, 0x01d7, 0x01d7, 0x01d8),
+  },
+  {     .freq                   = 5570,
+        RADIOREGS3(0x34, 0x01, 0x01, 0x02, 0x2d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x09, 0x00,
+                   0x61, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x09,
+                   0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x09, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08b8, 0x08b4, 0x08b0, 0x01d6, 0x01d7, 0x01d7),
+  },
+  {     .freq                   = 5580,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00,
+                   0x60, 0x62, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x62, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08bc, 0x08b8, 0x08b4, 0x01d5, 0x01d6, 0x01d7),
+  },
+  {     .freq                   = 5590,
+        RADIOREGS3(0x2e, 0x01, 0x01, 0x02, 0x2f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x04, 0x04, 0x04, 0x89, 0x08, 0x00,
+                   0x50, 0x61, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x61, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08c0, 0x08bc, 0x08b8, 0x01d4, 0x01d5, 0x01d6),
+  },
+  {     .freq                   = 5600,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x30, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08c4, 0x08c0, 0x08bc, 0x01d3, 0x01d4, 0x01d5),
+  },
+  {     .freq                   = 5610,
+        RADIOREGS3(0x28, 0x01, 0x01, 0x02, 0x31, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x51, 0x00, 0x00, 0x00, 0x77, 0x00, 0x08,
+                   0x00, 0x6f, 0x00, 0x51, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x08, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08c8, 0x08c4, 0x08c0, 0x01d2, 0x01d3, 0x01d4),
+  },
+  {     .freq                   = 5620,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x32, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x89, 0x08, 0x00,
+                   0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08cc, 0x08c8, 0x08c4, 0x01d2, 0x01d2, 0x01d3),
+  },
+  {     .freq                   = 5630,
+        RADIOREGS3(0x21, 0x01, 0x01, 0x02, 0x33, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x50, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08d0, 0x08cc, 0x08c8, 0x01d1, 0x01d2, 0x01d2),
+  },
+  {     .freq                   = 5640,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x34, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x50, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x50, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08d4, 0x08d0, 0x08cc, 0x01d0, 0x01d1, 0x01d2),
+  },
+  {     .freq                   = 5650,
+        RADIOREGS3(0x1c, 0x01, 0x01, 0x02, 0x35, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x07,
+                   0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x07, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08d8, 0x08d4, 0x08d0, 0x01cf, 0x01d0, 0x01d1),
+  },
+  {     .freq                   = 5660,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x36, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x40, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x40, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08dc, 0x08d8, 0x08d4, 0x01ce, 0x01cf, 0x01d0),
+  },
+  {     .freq                   = 5670,
+        RADIOREGS3(0x16, 0x01, 0x01, 0x02, 0x37, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x88, 0x07, 0x00,
+                   0x40, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08e0, 0x08dc, 0x08d8, 0x01ce, 0x01ce, 0x01cf),
+  },
+  {     .freq                   = 5680,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x38, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08e4, 0x08e0, 0x08dc, 0x01cd, 0x01ce, 0x01ce),
+  },
+  {     .freq                   = 5690,
+        RADIOREGS3(0x10, 0x01, 0x01, 0x02, 0x39, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6f, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6f, 0x00),
+        PHYREGS(0x08e8, 0x08e4, 0x08e0, 0x01cc, 0x01cd, 0x01ce),
+  },
+  {     .freq                   = 5700,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08ec, 0x08e8, 0x08e4, 0x01cb, 0x01cc, 0x01cd),
+  },
+  {     .freq                   = 5710,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f0, 0x08ec, 0x08e8, 0x01ca, 0x01cb, 0x01cc),
+  },
+  {     .freq                   = 5720,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f4, 0x08f0, 0x08ec, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5725,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x79, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x06, 0x00,
+                   0x30, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f6, 0x08f2, 0x08ee, 0x01c9, 0x01ca, 0x01cb),
+  },
+  {     .freq                   = 5730,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6e, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6e, 0x00),
+        PHYREGS(0x08f8, 0x08f4, 0x08f0, 0x01c9, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5735,
+        RADIOREGS3(0x03, 0x01, 0x02, 0x04, 0x7b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6d, 0x00),
+        PHYREGS(0x08fa, 0x08f6, 0x08f2, 0x01c8, 0x01c9, 0x01ca),
+  },
+  {     .freq                   = 5740,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6d, 0x00),
+        PHYREGS(0x08fc, 0x08f8, 0x08f4, 0x01c8, 0x01c9, 0x01c9),
+  },
+  {     .freq                   = 5745,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x30, 0x00, 0x00, 0x00, 0x77, 0x00, 0x06,
+                   0x00, 0x6d, 0x00, 0x30, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x06, 0x00, 0x6d, 0x00),
+        PHYREGS(0x08fe, 0x08fa, 0x08f6, 0x01c8, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5750,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x3f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x20, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6d, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6d, 0x00),
+        PHYREGS(0x0900, 0x08fc, 0x08f8, 0x01c7, 0x01c8, 0x01c9),
+  },
+  {     .freq                   = 5755,
+        RADIOREGS3(0xfe, 0x00, 0x02, 0x04, 0x7f, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x87, 0x05, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0902, 0x08fe, 0x08fa, 0x01c7, 0x01c8, 0x01c8),
+  },
+  {     .freq                   = 5760,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x40, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00,
+                   0x10, 0x20, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6c, 0x00, 0x20, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0904, 0x0900, 0x08fc, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5765,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x81, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x05, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6c, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6c, 0x00),
+        PHYREGS(0x0906, 0x0902, 0x08fe, 0x01c6, 0x01c7, 0x01c8),
+  },
+  {     .freq                   = 5770,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x41, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0908, 0x0904, 0x0900, 0x01c6, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5775,
+        RADIOREGS3(0xf8, 0x00, 0x02, 0x04, 0x83, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x090a, 0x0906, 0x0902, 0x01c5, 0x01c6, 0x01c7),
+  },
+  {     .freq                   = 5780,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x42, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x05, 0x05, 0x05, 0x86, 0x04, 0x00,
+                   0x10, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x090c, 0x0908, 0x0904, 0x01c5, 0x01c6, 0x01c6),
+  },
+  {     .freq                   = 5785,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x85, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x090e, 0x090a, 0x0906, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5790,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x43, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x10, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x10, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0910, 0x090c, 0x0908, 0x01c4, 0x01c5, 0x01c6),
+  },
+  {     .freq                   = 5795,
+        RADIOREGS3(0xf2, 0x00, 0x02, 0x04, 0x87, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0912, 0x090e, 0x090a, 0x01c4, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5800,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x44, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6b, 0x00),
+        PHYREGS(0x0914, 0x0910, 0x090c, 0x01c3, 0x01c4, 0x01c5),
+  },
+  {     .freq                   = 5805,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x89, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x0916, 0x0912, 0x090e, 0x01c3, 0x01c4, 0x01c4),
+  },
+  {     .freq                   = 5810,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x45, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x0918, 0x0914, 0x0910, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5815,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8b, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x091a, 0x0916, 0x0912, 0x01c2, 0x01c3, 0x01c4),
+  },
+  {     .freq                   = 5820,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x46, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x6a, 0x00),
+        PHYREGS(0x091c, 0x0918, 0x0914, 0x01c2, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5825,
+        RADIOREGS3(0xed, 0x00, 0x02, 0x04, 0x8d, 0x07, 0x07, 0x04,
+                   0x10, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x69, 0x00),
+        PHYREGS(0x091e, 0x091a, 0x0916, 0x01c1, 0x01c2, 0x01c3),
+  },
+  {     .freq                   = 5830,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x47, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x05, 0x00, 0x69, 0x00),
+        PHYREGS(0x0920, 0x091c, 0x0918, 0x01c1, 0x01c2, 0x01c2),
+  },
+  {     .freq                   = 5840,
+        RADIOREGS3(0x0a, 0x01, 0x01, 0x02, 0x48, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x86, 0x04, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x0924, 0x0920, 0x091c, 0x01c0, 0x01c1, 0x01c2),
+  },
+  {     .freq                   = 5850,
+        RADIOREGS3(0xe0, 0x00, 0x01, 0x02, 0x49, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x0928, 0x0924, 0x0920, 0x01bf, 0x01c0, 0x01c1),
+  },
+  {     .freq                   = 5860,
+        RADIOREGS3(0xde, 0x00, 0x01, 0x02, 0x4a, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x69, 0x00),
+        PHYREGS(0x092c, 0x0928, 0x0924, 0x01bf, 0x01bf, 0x01c0),
+  },
+  {     .freq                   = 5870,
+        RADIOREGS3(0xdb, 0x00, 0x01, 0x02, 0x4b, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0930, 0x092c, 0x0928, 0x01be, 0x01bf, 0x01bf),
+  },
+  {     .freq                   = 5880,
+        RADIOREGS3(0xd8, 0x00, 0x01, 0x02, 0x4c, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0934, 0x0930, 0x092c, 0x01bd, 0x01be, 0x01bf),
+  },
+  {     .freq                   = 5890,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4d, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0938, 0x0934, 0x0930, 0x01bc, 0x01bd, 0x01be),
+  },
+  {     .freq                   = 5900,
+        RADIOREGS3(0xd3, 0x00, 0x01, 0x02, 0x4e, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x093c, 0x0938, 0x0934, 0x01bc, 0x01bc, 0x01bd),
+  },
+  {     .freq                   = 5910,
+        RADIOREGS3(0xd6, 0x00, 0x01, 0x02, 0x4f, 0x05, 0x05, 0x04,
+                   0x0c, 0x01, 0x06, 0x06, 0x06, 0x85, 0x03, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x00, 0x77, 0x00, 0x04,
+                   0x00, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x77,
+                   0x00, 0x04, 0x00, 0x68, 0x00),
+        PHYREGS(0x0940, 0x093c, 0x0938, 0x01bb, 0x01bc, 0x01bc),
+  },
+  {     .freq                   = 2412,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x6c, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x04, 0x04, 0x04, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0b, 0x00, 0x0a),
+        PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
+  },
+  {     .freq                   = 2417,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x71, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x78, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0b, 0x00, 0x0a),
+        PHYREGS(0x03cb, 0x03c7, 0x03c3, 0x0438, 0x043d, 0x0441),
+  },
+  {     .freq                   = 2422,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x76, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x67, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0b, 0x00, 0x0a, 0x00, 0x89, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0b, 0x00, 0x0a),
+        PHYREGS(0x03cd, 0x03c9, 0x03c5, 0x0436, 0x043a, 0x043f),
+  },
+  {     .freq                   = 2427,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x7b, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x57, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x78, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03cf, 0x03cb, 0x03c7, 0x0434, 0x0438, 0x043d),
+  },
+  {     .freq                   = 2432,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x80, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x56, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x77, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03d1, 0x03cd, 0x03c9, 0x0431, 0x0436, 0x043a),
+  },
+  {     .freq                   = 2437,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x85, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x46, 0x00, 0x03, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x76, 0x00, 0x03, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03d3, 0x03cf, 0x03cb, 0x042f, 0x0434, 0x0438),
+  },
+  {     .freq                   = 2442,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8a, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x05, 0x05, 0x05, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x45, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x0a, 0x00, 0x66, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x0a),
+        PHYREGS(0x03d5, 0x03d1, 0x03cd, 0x042d, 0x0431, 0x0436),
+  },
+  {     .freq                   = 2447,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x8f, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x34, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x09, 0x00, 0x55, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x09),
+        PHYREGS(0x03d7, 0x03d3, 0x03cf, 0x042b, 0x042f, 0x0434),
+  },
+  {     .freq                   = 2452,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x94, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x23, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x09, 0x00, 0x45, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x09),
+        PHYREGS(0x03d9, 0x03d5, 0x03d1, 0x0429, 0x042d, 0x0431),
+  },
+  {     .freq                   = 2457,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x99, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x12, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x0a, 0x00, 0x09, 0x00, 0x34, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x0a, 0x00, 0x09),
+        PHYREGS(0x03db, 0x03d7, 0x03d3, 0x0427, 0x042b, 0x042f),
+  },
+  {     .freq                   = 2462,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0x9e, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x02, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x33, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03dd, 0x03d9, 0x03d5, 0x0424, 0x0429, 0x042d),
+  },
+  {     .freq                   = 2467,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa3, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x06, 0x06, 0x06, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x22, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03df, 0x03db, 0x03d7, 0x0422, 0x0427, 0x042b),
+  },
+  {     .freq                   = 2472,
+        RADIOREGS3(0x00, 0x01, 0x03, 0x09, 0xa8, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x30, 0x00,
+                   0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x11, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03e1, 0x03dd, 0x03d9, 0x0420, 0x0424, 0x0429),
+  },
+  {     .freq                   = 2484,
+        RADIOREGS3(0xff, 0x01, 0x03, 0x09, 0xb4, 0x08, 0x08, 0x04,
+                   0x16, 0x01, 0x07, 0x07, 0x07, 0x8f, 0x20, 0x00,
+                   0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x70, 0x00,
+                   0x09, 0x00, 0x09, 0x00, 0x00, 0x00, 0x02, 0x00,
+                   0x70, 0x00, 0x09, 0x00, 0x09),
+        PHYREGS(0x03e6, 0x03e2, 0x03de, 0x041b, 0x041f, 0x0424),
+  },
+};
+
+static void b2056_upload_inittab(struct b43_wldev *dev, bool ghz5,
+                                 bool ignore_uploadflag, u16 routing,
+                                 const struct b2056_inittab_entry *e,
+                                 unsigned int length)
+{
+        unsigned int i;
+        u16 value;
+
+        for (i = 0; i < length; i++, e++) {
+                if (!(e->flags & B2056_INITTAB_ENTRY_OK))
+                        continue;
+                if ((e->flags & B2056_INITTAB_UPLOAD) || ignore_uploadflag) {
+                        if (ghz5)
+                                value = e->ghz5;
+                        else
+                                value = e->ghz2;
+                        b43_radio_write(dev, routing | i, value);
+                }
+        }
+}
+
+void b2056_upload_inittabs(struct b43_wldev *dev,
+                           bool ghz5, bool ignore_uploadflag)
+{
+        struct b2056_inittabs_pts *pts;
+
+        if (dev->phy.rev >= ARRAY_SIZE(b2056_inittabs)) {
+                B43_WARN_ON(1);
+                return;
+        }
+        pts = &b2056_inittabs[dev->phy.rev];
+
+        b2056_upload_inittab(dev, ghz5, ignore_uploadflag,
+                                B2056_SYN, pts->syn, pts->syn_length);
+        b2056_upload_inittab(dev, ghz5, ignore_uploadflag,
+                                B2056_TX0, pts->tx, pts->tx_length);
+        b2056_upload_inittab(dev, ghz5, ignore_uploadflag,
+                                B2056_TX1, pts->tx, pts->tx_length);
+        b2056_upload_inittab(dev, ghz5, ignore_uploadflag,
+                                B2056_RX0, pts->rx, pts->rx_length);
+        b2056_upload_inittab(dev, ghz5, ignore_uploadflag,
+                                B2056_RX1, pts->rx, pts->rx_length);
+}
+
 const struct b43_nphy_channeltab_entry_rev3 *
 b43_nphy_get_chantabent_rev3(struct b43_wldev *dev, u16 freq)
 {
         const struct b43_nphy_channeltab_entry_rev3 *e;
-        unsigned int i;
+        unsigned int length, i;
+
+        switch (dev->phy.rev) {
+        case 3:
+                e = b43_nphy_channeltab_rev3;
+                length = ARRAY_SIZE(b43_nphy_channeltab_rev3);
+                break;
+        case 4:
+                e = b43_nphy_channeltab_rev4;
+                length = ARRAY_SIZE(b43_nphy_channeltab_rev4);
+                break;
+        case 5:
+                e = b43_nphy_channeltab_rev5;
+                length = ARRAY_SIZE(b43_nphy_channeltab_rev5);
+                break;
+        case 6:
+                e = b43_nphy_channeltab_rev6;
+                length = ARRAY_SIZE(b43_nphy_channeltab_rev6);
+                break;
+        case 7:
+        case 9:
+                e = b43_nphy_channeltab_rev7_9;
+                length = ARRAY_SIZE(b43_nphy_channeltab_rev7_9);
+                break;
+        case 8:
+                e = b43_nphy_channeltab_rev8;
+                length = ARRAY_SIZE(b43_nphy_channeltab_rev8);
+                break;
+        default:
+                B43_WARN_ON(1);
+                return NULL;
+        }
 
-        for (i = 0; i < ARRAY_SIZE(b43_nphy_channeltab_rev3); i++) {
-                e = &(b43_nphy_channeltab_rev3[i]);
+        for (i = 0; i < length; i++, e++) {
                 if (e->freq == freq)
                         return e;
         }
diff --git a/drivers/net/wireless/b43/radio_2056.h b/drivers/net/wireless/b43/radio_2056.h
index fda6dafecb8c..d601f6e7e313 100644
--- a/drivers/net/wireless/b43/radio_2056.h
+++ b/drivers/net/wireless/b43/radio_2056.h
@@ -4,6 +4,9 @@
 
   Copyright (c) 2010 Rafał Miłecki <zajec5@gmail.com>
 
+  Some parts of the code in this file are derived from the brcm80211
+  driver  Copyright (c) 2010 Broadcom Corporation
+
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
@@ -28,15 +31,1090 @@
 
 #include "tables_nphy.h"
 
+#define B2056_SYN                       (0x0 << 12)
+#define B2056_TX0                       (0x2 << 12)
+#define B2056_TX1                       (0x3 << 12)
+#define B2056_RX0                       (0x6 << 12)
+#define B2056_RX1                       (0x7 << 12)
+#define B2056_ALLTX                     (0xE << 12)
+#define B2056_ALLRX                     (0xF << 12)
+
+#define B2056_SYN_RESERVED_ADDR0        0x00
+#define B2056_SYN_IDCODE                0x01
+#define B2056_SYN_RESERVED_ADDR2        0x02
+#define B2056_SYN_RESERVED_ADDR3        0x03
+#define B2056_SYN_RESERVED_ADDR4        0x04
+#define B2056_SYN_RESERVED_ADDR5        0x05
+#define B2056_SYN_RESERVED_ADDR6        0x06
+#define B2056_SYN_RESERVED_ADDR7        0x07
+#define B2056_SYN_COM_CTRL              0x08
+#define B2056_SYN_COM_PU                0x09
+#define B2056_SYN_COM_OVR               0x0A
+#define B2056_SYN_COM_RESET             0x0B
+#define B2056_SYN_COM_RCAL              0x0C
+#define B2056_SYN_COM_RC_RXLPF          0x0D
+#define B2056_SYN_COM_RC_TXLPF          0x0E
+#define B2056_SYN_COM_RC_RXHPF          0x0F
+#define B2056_SYN_RESERVED_ADDR16       0x10
+#define B2056_SYN_RESERVED_ADDR17       0x11
+#define B2056_SYN_RESERVED_ADDR18       0x12
+#define B2056_SYN_RESERVED_ADDR19       0x13
+#define B2056_SYN_RESERVED_ADDR20       0x14
+#define B2056_SYN_RESERVED_ADDR21       0x15
+#define B2056_SYN_RESERVED_ADDR22       0x16
+#define B2056_SYN_RESERVED_ADDR23       0x17
+#define B2056_SYN_RESERVED_ADDR24       0x18
+#define B2056_SYN_RESERVED_ADDR25       0x19
+#define B2056_SYN_RESERVED_ADDR26       0x1A
+#define B2056_SYN_RESERVED_ADDR27       0x1B
+#define B2056_SYN_RESERVED_ADDR28       0x1C
+#define B2056_SYN_RESERVED_ADDR29       0x1D
+#define B2056_SYN_RESERVED_ADDR30       0x1E
+#define B2056_SYN_RESERVED_ADDR31       0x1F
+#define B2056_SYN_GPIO_MASTER1          0x20
+#define B2056_SYN_GPIO_MASTER2          0x21
+#define B2056_SYN_TOPBIAS_MASTER        0x22
+#define B2056_SYN_TOPBIAS_RCAL          0x23
+#define B2056_SYN_AFEREG                0x24
+#define B2056_SYN_TEMPPROCSENSE         0x25
+#define B2056_SYN_TEMPPROCSENSEIDAC     0x26
+#define B2056_SYN_TEMPPROCSENSERCAL     0x27
+#define B2056_SYN_LPO                   0x28
+#define B2056_SYN_VDDCAL_MASTER         0x29
+#define B2056_SYN_VDDCAL_IDAC           0x2A
+#define B2056_SYN_VDDCAL_STATUS         0x2B
+#define B2056_SYN_RCAL_MASTER           0x2C
+#define B2056_SYN_RCAL_CODE_OUT         0x2D
+#define B2056_SYN_RCCAL_CTRL0           0x2E
+#define B2056_SYN_RCCAL_CTRL1           0x2F
+#define B2056_SYN_RCCAL_CTRL2           0x30
+#define B2056_SYN_RCCAL_CTRL3           0x31
+#define B2056_SYN_RCCAL_CTRL4           0x32
+#define B2056_SYN_RCCAL_CTRL5           0x33
+#define B2056_SYN_RCCAL_CTRL6           0x34
+#define B2056_SYN_RCCAL_CTRL7           0x35
+#define B2056_SYN_RCCAL_CTRL8           0x36
+#define B2056_SYN_RCCAL_CTRL9           0x37
+#define B2056_SYN_RCCAL_CTRL10          0x38
+#define B2056_SYN_RCCAL_CTRL11          0x39
+#define B2056_SYN_ZCAL_SPARE1           0x3A
+#define B2056_SYN_ZCAL_SPARE2           0x3B
+#define B2056_SYN_PLL_MAST1             0x3C
+#define B2056_SYN_PLL_MAST2             0x3D
+#define B2056_SYN_PLL_MAST3             0x3E
+#define B2056_SYN_PLL_BIAS_RESET        0x3F
+#define B2056_SYN_PLL_XTAL0             0x40
+#define B2056_SYN_PLL_XTAL1             0x41
+#define B2056_SYN_PLL_XTAL3             0x42
+#define B2056_SYN_PLL_XTAL4             0x43
+#define B2056_SYN_PLL_XTAL5             0x44
+#define B2056_SYN_PLL_XTAL6             0x45
+#define B2056_SYN_PLL_REFDIV            0x46
+#define B2056_SYN_PLL_PFD               0x47
+#define B2056_SYN_PLL_CP1               0x48
+#define B2056_SYN_PLL_CP2               0x49
+#define B2056_SYN_PLL_CP3               0x4A
+#define B2056_SYN_PLL_LOOPFILTER1       0x4B
+#define B2056_SYN_PLL_LOOPFILTER2       0x4C
+#define B2056_SYN_PLL_LOOPFILTER3       0x4D
+#define B2056_SYN_PLL_LOOPFILTER4       0x4E
+#define B2056_SYN_PLL_LOOPFILTER5       0x4F
+#define B2056_SYN_PLL_MMD1              0x50
+#define B2056_SYN_PLL_MMD2              0x51
+#define B2056_SYN_PLL_VCO1              0x52
+#define B2056_SYN_PLL_VCO2              0x53
+#define B2056_SYN_PLL_MONITOR1          0x54
+#define B2056_SYN_PLL_MONITOR2          0x55
+#define B2056_SYN_PLL_VCOCAL1           0x56
+#define B2056_SYN_PLL_VCOCAL2           0x57
+#define B2056_SYN_PLL_VCOCAL4           0x58
+#define B2056_SYN_PLL_VCOCAL5           0x59
+#define B2056_SYN_PLL_VCOCAL6           0x5A
+#define B2056_SYN_PLL_VCOCAL7           0x5B
+#define B2056_SYN_PLL_VCOCAL8           0x5C
+#define B2056_SYN_PLL_VCOCAL9           0x5D
+#define B2056_SYN_PLL_VCOCAL10          0x5E
+#define B2056_SYN_PLL_VCOCAL11          0x5F
+#define B2056_SYN_PLL_VCOCAL12          0x60
+#define B2056_SYN_PLL_VCOCAL13          0x61
+#define B2056_SYN_PLL_VREG              0x62
+#define B2056_SYN_PLL_STATUS1           0x63
+#define B2056_SYN_PLL_STATUS2           0x64
+#define B2056_SYN_PLL_STATUS3           0x65
+#define B2056_SYN_LOGEN_PU0             0x66
+#define B2056_SYN_LOGEN_PU1             0x67
+#define B2056_SYN_LOGEN_PU2             0x68
+#define B2056_SYN_LOGEN_PU3             0x69
+#define B2056_SYN_LOGEN_PU5             0x6A
+#define B2056_SYN_LOGEN_PU6             0x6B
+#define B2056_SYN_LOGEN_PU7             0x6C
+#define B2056_SYN_LOGEN_PU8             0x6D
+#define B2056_SYN_LOGEN_BIAS_RESET      0x6E
+#define B2056_SYN_LOGEN_RCCR1           0x6F
+#define B2056_SYN_LOGEN_VCOBUF1         0x70
+#define B2056_SYN_LOGEN_MIXER1          0x71
+#define B2056_SYN_LOGEN_MIXER2          0x72
+#define B2056_SYN_LOGEN_BUF1            0x73
+#define B2056_SYN_LOGENBUF2             0x74
+#define B2056_SYN_LOGEN_BUF3            0x75
+#define B2056_SYN_LOGEN_BUF4            0x76
+#define B2056_SYN_LOGEN_DIV1            0x77
+#define B2056_SYN_LOGEN_DIV2            0x78
+#define B2056_SYN_LOGEN_DIV3            0x79
+#define B2056_SYN_LOGEN_ACL1            0x7A
+#define B2056_SYN_LOGEN_ACL2            0x7B
+#define B2056_SYN_LOGEN_ACL3            0x7C
+#define B2056_SYN_LOGEN_ACL4            0x7D
+#define B2056_SYN_LOGEN_ACL5            0x7E
+#define B2056_SYN_LOGEN_ACL6            0x7F
+#define B2056_SYN_LOGEN_ACLOUT          0x80
+#define B2056_SYN_LOGEN_ACLCAL1         0x81
+#define B2056_SYN_LOGEN_ACLCAL2         0x82
+#define B2056_SYN_LOGEN_ACLCAL3         0x83
+#define B2056_SYN_CALEN                 0x84
+#define B2056_SYN_LOGEN_PEAKDET1        0x85
+#define B2056_SYN_LOGEN_CORE_ACL_OVR    0x86
+#define B2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87
+#define B2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88
+#define B2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89
+#define B2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8A
+#define B2056_SYN_LOGEN_VCOBUF2         0x8B
+#define B2056_SYN_LOGEN_MIXER3          0x8C
+#define B2056_SYN_LOGEN_BUF5            0x8D
+#define B2056_SYN_LOGEN_BUF6            0x8E
+#define B2056_SYN_LOGEN_CBUFRX1         0x8F
+#define B2056_SYN_LOGEN_CBUFRX2         0x90
+#define B2056_SYN_LOGEN_CBUFRX3         0x91
+#define B2056_SYN_LOGEN_CBUFRX4         0x92
+#define B2056_SYN_LOGEN_CBUFTX1         0x93
+#define B2056_SYN_LOGEN_CBUFTX2         0x94
+#define B2056_SYN_LOGEN_CBUFTX3         0x95
+#define B2056_SYN_LOGEN_CBUFTX4         0x96
+#define B2056_SYN_LOGEN_CMOSRX1         0x97
+#define B2056_SYN_LOGEN_CMOSRX2         0x98
+#define B2056_SYN_LOGEN_CMOSRX3         0x99
+#define B2056_SYN_LOGEN_CMOSRX4         0x9A
+#define B2056_SYN_LOGEN_CMOSTX1         0x9B
+#define B2056_SYN_LOGEN_CMOSTX2         0x9C
+#define B2056_SYN_LOGEN_CMOSTX3         0x9D
+#define B2056_SYN_LOGEN_CMOSTX4         0x9E
+#define B2056_SYN_LOGEN_VCOBUF2_OVRVAL  0x9F
+#define B2056_SYN_LOGEN_MIXER3_OVRVAL   0xA0
+#define B2056_SYN_LOGEN_BUF5_OVRVAL     0xA1
+#define B2056_SYN_LOGEN_BUF6_OVRVAL     0xA2
+#define B2056_SYN_LOGEN_CBUFRX1_OVRVAL  0xA3
+#define B2056_SYN_LOGEN_CBUFRX2_OVRVAL  0xA4
+#define B2056_SYN_LOGEN_CBUFRX3_OVRVAL  0xA5
+#define B2056_SYN_LOGEN_CBUFRX4_OVRVAL  0xA6
+#define B2056_SYN_LOGEN_CBUFTX1_OVRVAL  0xA7
+#define B2056_SYN_LOGEN_CBUFTX2_OVRVAL  0xA8
+#define B2056_SYN_LOGEN_CBUFTX3_OVRVAL  0xA9
+#define B2056_SYN_LOGEN_CBUFTX4_OVRVAL  0xAA
+#define B2056_SYN_LOGEN_CMOSRX1_OVRVAL  0xAB
+#define B2056_SYN_LOGEN_CMOSRX2_OVRVAL  0xAC
+#define B2056_SYN_LOGEN_CMOSRX3_OVRVAL  0xAD
+#define B2056_SYN_LOGEN_CMOSRX4_OVRVAL  0xAE
+#define B2056_SYN_LOGEN_CMOSTX1_OVRVAL  0xAF
+#define B2056_SYN_LOGEN_CMOSTX2_OVRVAL  0xB0
+#define B2056_SYN_LOGEN_CMOSTX3_OVRVAL  0xB1
+#define B2056_SYN_LOGEN_CMOSTX4_OVRVAL  0xB2
+#define B2056_SYN_LOGEN_ACL_WAITCNT     0xB3
+#define B2056_SYN_LOGEN_CORE_CALVALID   0xB4
+#define B2056_SYN_LOGEN_RX_CMOS_CALVALID        0xB5
+#define B2056_SYN_LOGEN_TX_CMOS_VALID   0xB6
+
+#define B2056_TX_RESERVED_ADDR0         0x00
+#define B2056_TX_IDCODE                 0x01
+#define B2056_TX_RESERVED_ADDR2         0x02
+#define B2056_TX_RESERVED_ADDR3         0x03
+#define B2056_TX_RESERVED_ADDR4         0x04
+#define B2056_TX_RESERVED_ADDR5         0x05
+#define B2056_TX_RESERVED_ADDR6         0x06
+#define B2056_TX_RESERVED_ADDR7         0x07
+#define B2056_TX_COM_CTRL               0x08
+#define B2056_TX_COM_PU                 0x09
+#define B2056_TX_COM_OVR                0x0A
+#define B2056_TX_COM_RESET              0x0B
+#define B2056_TX_COM_RCAL               0x0C
+#define B2056_TX_COM_RC_RXLPF           0x0D
+#define B2056_TX_COM_RC_TXLPF           0x0E
+#define B2056_TX_COM_RC_RXHPF           0x0F
+#define B2056_TX_RESERVED_ADDR16        0x10
+#define B2056_TX_RESERVED_ADDR17        0x11
+#define B2056_TX_RESERVED_ADDR18        0x12
+#define B2056_TX_RESERVED_ADDR19        0x13
+#define B2056_TX_RESERVED_ADDR20        0x14
+#define B2056_TX_RESERVED_ADDR21        0x15
+#define B2056_TX_RESERVED_ADDR22        0x16
+#define B2056_TX_RESERVED_ADDR23        0x17
+#define B2056_TX_RESERVED_ADDR24        0x18
+#define B2056_TX_RESERVED_ADDR25        0x19
+#define B2056_TX_RESERVED_ADDR26        0x1A
+#define B2056_TX_RESERVED_ADDR27        0x1B
+#define B2056_TX_RESERVED_ADDR28        0x1C
+#define B2056_TX_RESERVED_ADDR29        0x1D
+#define B2056_TX_RESERVED_ADDR30        0x1E
+#define B2056_TX_RESERVED_ADDR31        0x1F
+#define B2056_TX_IQCAL_GAIN_BW          0x20
+#define B2056_TX_LOFT_FINE_I            0x21
+#define B2056_TX_LOFT_FINE_Q            0x22
+#define B2056_TX_LOFT_COARSE_I          0x23
+#define B2056_TX_LOFT_COARSE_Q          0x24
+#define B2056_TX_TX_COM_MASTER1         0x25
+#define B2056_TX_TX_COM_MASTER2         0x26
+#define B2056_TX_RXIQCAL_TXMUX          0x27
+#define B2056_TX_TX_SSI_MASTER          0x28
+#define B2056_TX_IQCAL_VCM_HG           0x29
+#define B2056_TX_IQCAL_IDAC             0x2A
+#define B2056_TX_TSSI_VCM               0x2B
+#define B2056_TX_TX_AMP_DET             0x2C
+#define B2056_TX_TX_SSI_MUX             0x2D
+#define B2056_TX_TSSIA                  0x2E
+#define B2056_TX_TSSIG                  0x2F
+#define B2056_TX_TSSI_MISC1             0x30
+#define B2056_TX_TSSI_MISC2             0x31
+#define B2056_TX_TSSI_MISC3             0x32
+#define B2056_TX_PA_SPARE1              0x33
+#define B2056_TX_PA_SPARE2              0x34
+#define B2056_TX_INTPAA_MASTER          0x35
+#define B2056_TX_INTPAA_GAIN            0x36
+#define B2056_TX_INTPAA_BOOST_TUNE      0x37
+#define B2056_TX_INTPAA_IAUX_STAT       0x38
+#define B2056_TX_INTPAA_IAUX_DYN        0x39
+#define B2056_TX_INTPAA_IMAIN_STAT      0x3A
+#define B2056_TX_INTPAA_IMAIN_DYN       0x3B
+#define B2056_TX_INTPAA_CASCBIAS        0x3C
+#define B2056_TX_INTPAA_PASLOPE         0x3D
+#define B2056_TX_INTPAA_PA_MISC         0x3E
+#define B2056_TX_INTPAG_MASTER          0x3F
+#define B2056_TX_INTPAG_GAIN            0x40
+#define B2056_TX_INTPAG_BOOST_TUNE      0x41
+#define B2056_TX_INTPAG_IAUX_STAT       0x42
+#define B2056_TX_INTPAG_IAUX_DYN        0x43
+#define B2056_TX_INTPAG_IMAIN_STAT      0x44
+#define B2056_TX_INTPAG_IMAIN_DYN       0x45
+#define B2056_TX_INTPAG_CASCBIAS        0x46
+#define B2056_TX_INTPAG_PASLOPE         0x47
+#define B2056_TX_INTPAG_PA_MISC         0x48
+#define B2056_TX_PADA_MASTER            0x49
+#define B2056_TX_PADA_IDAC              0x4A
+#define B2056_TX_PADA_CASCBIAS          0x4B
+#define B2056_TX_PADA_GAIN              0x4C
+#define B2056_TX_PADA_BOOST_TUNE        0x4D
+#define B2056_TX_PADA_SLOPE             0x4E
+#define B2056_TX_PADG_MASTER            0x4F
+#define B2056_TX_PADG_IDAC              0x50
+#define B2056_TX_PADG_CASCBIAS          0x51
+#define B2056_TX_PADG_GAIN              0x52
+#define B2056_TX_PADG_BOOST_TUNE        0x53
+#define B2056_TX_PADG_SLOPE             0x54
+#define B2056_TX_PGAA_MASTER            0x55
+#define B2056_TX_PGAA_IDAC              0x56
+#define B2056_TX_PGAA_GAIN              0x57
+#define B2056_TX_PGAA_BOOST_TUNE        0x58
+#define B2056_TX_PGAA_SLOPE             0x59
+#define B2056_TX_PGAA_MISC              0x5A
+#define B2056_TX_PGAG_MASTER            0x5B
+#define B2056_TX_PGAG_IDAC              0x5C
+#define B2056_TX_PGAG_GAIN              0x5D
+#define B2056_TX_PGAG_BOOST_TUNE        0x5E
+#define B2056_TX_PGAG_SLOPE             0x5F
+#define B2056_TX_PGAG_MISC              0x60
+#define B2056_TX_MIXA_MASTER            0x61
+#define B2056_TX_MIXA_BOOST_TUNE        0x62
+#define B2056_TX_MIXG                   0x63
+#define B2056_TX_MIXG_BOOST_TUNE        0x64
+#define B2056_TX_BB_GM_MASTER           0x65
+#define B2056_TX_GMBB_GM                0x66
+#define B2056_TX_GMBB_IDAC              0x67
+#define B2056_TX_TXLPF_MASTER           0x68
+#define B2056_TX_TXLPF_RCCAL            0x69
+#define B2056_TX_TXLPF_RCCAL_OFF0       0x6A
+#define B2056_TX_TXLPF_RCCAL_OFF1       0x6B
+#define B2056_TX_TXLPF_RCCAL_OFF2       0x6C
+#define B2056_TX_TXLPF_RCCAL_OFF3       0x6D
+#define B2056_TX_TXLPF_RCCAL_OFF4       0x6E
+#define B2056_TX_TXLPF_RCCAL_OFF5       0x6F
+#define B2056_TX_TXLPF_RCCAL_OFF6       0x70
+#define B2056_TX_TXLPF_BW               0x71
+#define B2056_TX_TXLPF_GAIN             0x72
+#define B2056_TX_TXLPF_IDAC             0x73
+#define B2056_TX_TXLPF_IDAC_0           0x74
+#define B2056_TX_TXLPF_IDAC_1           0x75
+#define B2056_TX_TXLPF_IDAC_2           0x76
+#define B2056_TX_TXLPF_IDAC_3           0x77
+#define B2056_TX_TXLPF_IDAC_4           0x78
+#define B2056_TX_TXLPF_IDAC_5           0x79
+#define B2056_TX_TXLPF_IDAC_6           0x7A
+#define B2056_TX_TXLPF_OPAMP_IDAC       0x7B
+#define B2056_TX_TXLPF_MISC             0x7C
+#define B2056_TX_TXSPARE1               0x7D
+#define B2056_TX_TXSPARE2               0x7E
+#define B2056_TX_TXSPARE3               0x7F
+#define B2056_TX_TXSPARE4               0x80
+#define B2056_TX_TXSPARE5               0x81
+#define B2056_TX_TXSPARE6               0x82
+#define B2056_TX_TXSPARE7               0x83
+#define B2056_TX_TXSPARE8               0x84
+#define B2056_TX_TXSPARE9               0x85
+#define B2056_TX_TXSPARE10              0x86
+#define B2056_TX_TXSPARE11              0x87
+#define B2056_TX_TXSPARE12              0x88
+#define B2056_TX_TXSPARE13              0x89
+#define B2056_TX_TXSPARE14              0x8A
+#define B2056_TX_TXSPARE15              0x8B
+#define B2056_TX_TXSPARE16              0x8C
+#define B2056_TX_STATUS_INTPA_GAIN      0x8D
+#define B2056_TX_STATUS_PAD_GAIN        0x8E
+#define B2056_TX_STATUS_PGA_GAIN        0x8F
+#define B2056_TX_STATUS_GM_TXLPF_GAIN   0x90
+#define B2056_TX_STATUS_TXLPF_BW        0x91
+#define B2056_TX_STATUS_TXLPF_RC        0x92
+#define B2056_TX_GMBB_IDAC0             0x93
+#define B2056_TX_GMBB_IDAC1             0x94
+#define B2056_TX_GMBB_IDAC2             0x95
+#define B2056_TX_GMBB_IDAC3             0x96
+#define B2056_TX_GMBB_IDAC4             0x97
+#define B2056_TX_GMBB_IDAC5             0x98
+#define B2056_TX_GMBB_IDAC6             0x99
+#define B2056_TX_GMBB_IDAC7             0x9A
+
+#define B2056_RX_RESERVED_ADDR0         0x00
+#define B2056_RX_IDCODE                 0x01
+#define B2056_RX_RESERVED_ADDR2         0x02
+#define B2056_RX_RESERVED_ADDR3         0x03
+#define B2056_RX_RESERVED_ADDR4         0x04
+#define B2056_RX_RESERVED_ADDR5         0x05
+#define B2056_RX_RESERVED_ADDR6         0x06
+#define B2056_RX_RESERVED_ADDR7         0x07
+#define B2056_RX_COM_CTRL               0x08
+#define B2056_RX_COM_PU                 0x09
+#define B2056_RX_COM_OVR                0x0A
+#define B2056_RX_COM_RESET              0x0B
+#define B2056_RX_COM_RCAL               0x0C
+#define B2056_RX_COM_RC_RXLPF           0x0D
+#define B2056_RX_COM_RC_TXLPF           0x0E
+#define B2056_RX_COM_RC_RXHPF           0x0F
+#define B2056_RX_RESERVED_ADDR16        0x10
+#define B2056_RX_RESERVED_ADDR17        0x11
+#define B2056_RX_RESERVED_ADDR18        0x12
+#define B2056_RX_RESERVED_ADDR19        0x13
+#define B2056_RX_RESERVED_ADDR20        0x14
+#define B2056_RX_RESERVED_ADDR21        0x15
+#define B2056_RX_RESERVED_ADDR22        0x16
+#define B2056_RX_RESERVED_ADDR23        0x17
+#define B2056_RX_RESERVED_ADDR24        0x18
+#define B2056_RX_RESERVED_ADDR25        0x19
+#define B2056_RX_RESERVED_ADDR26        0x1A
+#define B2056_RX_RESERVED_ADDR27        0x1B
+#define B2056_RX_RESERVED_ADDR28        0x1C
+#define B2056_RX_RESERVED_ADDR29        0x1D
+#define B2056_RX_RESERVED_ADDR30        0x1E
+#define B2056_RX_RESERVED_ADDR31        0x1F
+#define B2056_RX_RXIQCAL_RXMUX          0x20
+#define B2056_RX_RSSI_PU                0x21
+#define B2056_RX_RSSI_SEL               0x22
+#define B2056_RX_RSSI_GAIN              0x23
+#define B2056_RX_RSSI_NB_IDAC           0x24
+#define B2056_RX_RSSI_WB2I_IDAC_1       0x25
+#define B2056_RX_RSSI_WB2I_IDAC_2       0x26
+#define B2056_RX_RSSI_WB2Q_IDAC_1       0x27
+#define B2056_RX_RSSI_WB2Q_IDAC_2       0x28
+#define B2056_RX_RSSI_POLE              0x29
+#define B2056_RX_RSSI_WB1_IDAC          0x2A
+#define B2056_RX_RSSI_MISC              0x2B
+#define B2056_RX_LNAA_MASTER            0x2C
+#define B2056_RX_LNAA_TUNE              0x2D
+#define B2056_RX_LNAA_GAIN              0x2E
+#define B2056_RX_LNA_A_SLOPE            0x2F
+#define B2056_RX_BIASPOLE_LNAA1_IDAC    0x30
+#define B2056_RX_LNAA2_IDAC             0x31
+#define B2056_RX_LNA1A_MISC             0x32
+#define B2056_RX_LNAG_MASTER            0x33
+#define B2056_RX_LNAG_TUNE              0x34
+#define B2056_RX_LNAG_GAIN              0x35
+#define B2056_RX_LNA_G_SLOPE            0x36
+#define B2056_RX_BIASPOLE_LNAG1_IDAC    0x37
+#define B2056_RX_LNAG2_IDAC             0x38
+#define B2056_RX_LNA1G_MISC             0x39
+#define B2056_RX_MIXA_MASTER            0x3A
+#define B2056_RX_MIXA_VCM               0x3B
+#define B2056_RX_MIXA_CTRLPTAT          0x3C
+#define B2056_RX_MIXA_LOB_BIAS          0x3D
+#define B2056_RX_MIXA_CORE_IDAC         0x3E
+#define B2056_RX_MIXA_CMFB_IDAC         0x3F
+#define B2056_RX_MIXA_BIAS_AUX          0x40
+#define B2056_RX_MIXA_BIAS_MAIN         0x41
+#define B2056_RX_MIXA_BIAS_MISC         0x42
+#define B2056_RX_MIXA_MAST_BIAS         0x43
+#define B2056_RX_MIXG_MASTER            0x44
+#define B2056_RX_MIXG_VCM               0x45
+#define B2056_RX_MIXG_CTRLPTAT          0x46
+#define B2056_RX_MIXG_LOB_BIAS          0x47
+#define B2056_RX_MIXG_CORE_IDAC         0x48
+#define B2056_RX_MIXG_CMFB_IDAC         0x49
+#define B2056_RX_MIXG_BIAS_AUX          0x4A
+#define B2056_RX_MIXG_BIAS_MAIN         0x4B
+#define B2056_RX_MIXG_BIAS_MISC         0x4C
+#define B2056_RX_MIXG_MAST_BIAS         0x4D
+#define B2056_RX_TIA_MASTER             0x4E
+#define B2056_RX_TIA_IOPAMP             0x4F
+#define B2056_RX_TIA_QOPAMP             0x50
+#define B2056_RX_TIA_IMISC              0x51
+#define B2056_RX_TIA_QMISC              0x52
+#define B2056_RX_TIA_GAIN               0x53
+#define B2056_RX_TIA_SPARE1             0x54
+#define B2056_RX_TIA_SPARE2             0x55
+#define B2056_RX_BB_LPF_MASTER          0x56
+#define B2056_RX_AACI_MASTER            0x57
+#define B2056_RX_RXLPF_IDAC             0x58
+#define B2056_RX_RXLPF_OPAMPBIAS_LOWQ   0x59
+#define B2056_RX_RXLPF_OPAMPBIAS_HIGHQ  0x5A
+#define B2056_RX_RXLPF_BIAS_DCCANCEL    0x5B
+#define B2056_RX_RXLPF_OUTVCM           0x5C
+#define B2056_RX_RXLPF_INVCM_BODY       0x5D
+#define B2056_RX_RXLPF_CC_OP            0x5E
+#define B2056_RX_RXLPF_GAIN             0x5F
+#define B2056_RX_RXLPF_Q_BW             0x60
+#define B2056_RX_RXLPF_HP_CORNER_BW     0x61
+#define B2056_RX_RXLPF_RCCAL_HPC        0x62
+#define B2056_RX_RXHPF_OFF0             0x63
+#define B2056_RX_RXHPF_OFF1             0x64
+#define B2056_RX_RXHPF_OFF2             0x65
+#define B2056_RX_RXHPF_OFF3             0x66
+#define B2056_RX_RXHPF_OFF4             0x67
+#define B2056_RX_RXHPF_OFF5             0x68
+#define B2056_RX_RXHPF_OFF6             0x69
+#define B2056_RX_RXHPF_OFF7             0x6A
+#define B2056_RX_RXLPF_RCCAL_LPC        0x6B
+#define B2056_RX_RXLPF_OFF_0            0x6C
+#define B2056_RX_RXLPF_OFF_1            0x6D
+#define B2056_RX_RXLPF_OFF_2            0x6E
+#define B2056_RX_RXLPF_OFF_3            0x6F
+#define B2056_RX_RXLPF_OFF_4            0x70
+#define B2056_RX_UNUSED                 0x71
+#define B2056_RX_VGA_MASTER             0x72
+#define B2056_RX_VGA_BIAS               0x73
+#define B2056_RX_VGA_BIAS_DCCANCEL      0x74
+#define B2056_RX_VGA_GAIN               0x75
+#define B2056_RX_VGA_HP_CORNER_BW       0x76
+#define B2056_RX_VGABUF_BIAS            0x77
+#define B2056_RX_VGABUF_GAIN_BW         0x78
+#define B2056_RX_TXFBMIX_A              0x79
+#define B2056_RX_TXFBMIX_G              0x7A
+#define B2056_RX_RXSPARE1               0x7B
+#define B2056_RX_RXSPARE2               0x7C
+#define B2056_RX_RXSPARE3               0x7D
+#define B2056_RX_RXSPARE4               0x7E
+#define B2056_RX_RXSPARE5               0x7F
+#define B2056_RX_RXSPARE6               0x80
+#define B2056_RX_RXSPARE7               0x81
+#define B2056_RX_RXSPARE8               0x82
+#define B2056_RX_RXSPARE9               0x83
+#define B2056_RX_RXSPARE10              0x84
+#define B2056_RX_RXSPARE11              0x85
+#define B2056_RX_RXSPARE12              0x86
+#define B2056_RX_RXSPARE13              0x87
+#define B2056_RX_RXSPARE14              0x88
+#define B2056_RX_RXSPARE15              0x89
+#define B2056_RX_RXSPARE16              0x8A
+#define B2056_RX_STATUS_LNAA_GAIN       0x8B
+#define B2056_RX_STATUS_LNAG_GAIN       0x8C
+#define B2056_RX_STATUS_MIXTIA_GAIN     0x8D
+#define B2056_RX_STATUS_RXLPF_GAIN      0x8E
+#define B2056_RX_STATUS_VGA_BUF_GAIN    0x8F
+#define B2056_RX_STATUS_RXLPF_Q         0x90
+#define B2056_RX_STATUS_RXLPF_BUF_BW    0x91
+#define B2056_RX_STATUS_RXLPF_VGA_HPC   0x92
+#define B2056_RX_STATUS_RXLPF_RC        0x93
+#define B2056_RX_STATUS_HPC_RC          0x94
+
+#define B2056_LNA1_A_PU                 0x01
+#define B2056_LNA2_A_PU                 0x02
+#define B2056_LNA1_G_PU                 0x01
+#define B2056_LNA2_G_PU                 0x02
+#define B2056_MIXA_PU_I                 0x01
+#define B2056_MIXA_PU_Q                 0x02
+#define B2056_MIXA_PU_GM                0x10
+#define B2056_MIXG_PU_I                 0x01
+#define B2056_MIXG_PU_Q                 0x02
+#define B2056_MIXG_PU_GM                0x10
+#define B2056_TIA_PU                    0x01
+#define B2056_BB_LPF_PU                 0x20
+#define B2056_W1_PU                     0x02
+#define B2056_W2_PU                     0x04
+#define B2056_NB_PU                     0x08
+#define B2056_RSSI_W1_SEL               0x02
+#define B2056_RSSI_W2_SEL               0x04
+#define B2056_RSSI_NB_SEL               0x08
+#define B2056_VCM_MASK                  0x1C
+#define B2056_RSSI_VCM_SHIFT            0x02
+
+#define B2056_SYN                       (0x0 << 12)
+#define B2056_TX0                       (0x2 << 12)
+#define B2056_TX1                       (0x3 << 12)
+#define B2056_RX0                       (0x6 << 12)
+#define B2056_RX1                       (0x7 << 12)
+#define B2056_ALLTX                     (0xE << 12)
+#define B2056_ALLRX                     (0xF << 12)
+
+#define B2056_SYN_RESERVED_ADDR0        0x00
+#define B2056_SYN_IDCODE                0x01
+#define B2056_SYN_RESERVED_ADDR2        0x02
+#define B2056_SYN_RESERVED_ADDR3        0x03
+#define B2056_SYN_RESERVED_ADDR4        0x04
+#define B2056_SYN_RESERVED_ADDR5        0x05
+#define B2056_SYN_RESERVED_ADDR6        0x06
+#define B2056_SYN_RESERVED_ADDR7        0x07
+#define B2056_SYN_COM_CTRL              0x08
+#define B2056_SYN_COM_PU                0x09
+#define B2056_SYN_COM_OVR               0x0A
+#define B2056_SYN_COM_RESET             0x0B
+#define B2056_SYN_COM_RCAL              0x0C
+#define B2056_SYN_COM_RC_RXLPF          0x0D
+#define B2056_SYN_COM_RC_TXLPF          0x0E
+#define B2056_SYN_COM_RC_RXHPF          0x0F
+#define B2056_SYN_RESERVED_ADDR16       0x10
+#define B2056_SYN_RESERVED_ADDR17       0x11
+#define B2056_SYN_RESERVED_ADDR18       0x12
+#define B2056_SYN_RESERVED_ADDR19       0x13
+#define B2056_SYN_RESERVED_ADDR20       0x14
+#define B2056_SYN_RESERVED_ADDR21       0x15
+#define B2056_SYN_RESERVED_ADDR22       0x16
+#define B2056_SYN_RESERVED_ADDR23       0x17
+#define B2056_SYN_RESERVED_ADDR24       0x18
+#define B2056_SYN_RESERVED_ADDR25       0x19
+#define B2056_SYN_RESERVED_ADDR26       0x1A
+#define B2056_SYN_RESERVED_ADDR27       0x1B
+#define B2056_SYN_RESERVED_ADDR28       0x1C
+#define B2056_SYN_RESERVED_ADDR29       0x1D
+#define B2056_SYN_RESERVED_ADDR30       0x1E
+#define B2056_SYN_RESERVED_ADDR31       0x1F
+#define B2056_SYN_GPIO_MASTER1          0x20
+#define B2056_SYN_GPIO_MASTER2          0x21
+#define B2056_SYN_TOPBIAS_MASTER        0x22
+#define B2056_SYN_TOPBIAS_RCAL          0x23
+#define B2056_SYN_AFEREG                0x24
+#define B2056_SYN_TEMPPROCSENSE         0x25
+#define B2056_SYN_TEMPPROCSENSEIDAC     0x26
+#define B2056_SYN_TEMPPROCSENSERCAL     0x27
+#define B2056_SYN_LPO                   0x28
+#define B2056_SYN_VDDCAL_MASTER         0x29
+#define B2056_SYN_VDDCAL_IDAC           0x2A
+#define B2056_SYN_VDDCAL_STATUS         0x2B
+#define B2056_SYN_RCAL_MASTER           0x2C
+#define B2056_SYN_RCAL_CODE_OUT         0x2D
+#define B2056_SYN_RCCAL_CTRL0           0x2E
+#define B2056_SYN_RCCAL_CTRL1           0x2F
+#define B2056_SYN_RCCAL_CTRL2           0x30
+#define B2056_SYN_RCCAL_CTRL3           0x31
+#define B2056_SYN_RCCAL_CTRL4           0x32
+#define B2056_SYN_RCCAL_CTRL5           0x33
+#define B2056_SYN_RCCAL_CTRL6           0x34
+#define B2056_SYN_RCCAL_CTRL7           0x35
+#define B2056_SYN_RCCAL_CTRL8           0x36
+#define B2056_SYN_RCCAL_CTRL9           0x37
+#define B2056_SYN_RCCAL_CTRL10          0x38
+#define B2056_SYN_RCCAL_CTRL11          0x39
+#define B2056_SYN_ZCAL_SPARE1           0x3A
+#define B2056_SYN_ZCAL_SPARE2           0x3B
+#define B2056_SYN_PLL_MAST1             0x3C
+#define B2056_SYN_PLL_MAST2             0x3D
+#define B2056_SYN_PLL_MAST3             0x3E
+#define B2056_SYN_PLL_BIAS_RESET        0x3F
+#define B2056_SYN_PLL_XTAL0             0x40
+#define B2056_SYN_PLL_XTAL1             0x41
+#define B2056_SYN_PLL_XTAL3             0x42
+#define B2056_SYN_PLL_XTAL4             0x43
+#define B2056_SYN_PLL_XTAL5             0x44
+#define B2056_SYN_PLL_XTAL6             0x45
+#define B2056_SYN_PLL_REFDIV            0x46
+#define B2056_SYN_PLL_PFD               0x47
+#define B2056_SYN_PLL_CP1               0x48
+#define B2056_SYN_PLL_CP2               0x49
+#define B2056_SYN_PLL_CP3               0x4A
+#define B2056_SYN_PLL_LOOPFILTER1       0x4B
+#define B2056_SYN_PLL_LOOPFILTER2       0x4C
+#define B2056_SYN_PLL_LOOPFILTER3       0x4D
+#define B2056_SYN_PLL_LOOPFILTER4       0x4E
+#define B2056_SYN_PLL_LOOPFILTER5       0x4F
+#define B2056_SYN_PLL_MMD1              0x50
+#define B2056_SYN_PLL_MMD2              0x51
+#define B2056_SYN_PLL_VCO1              0x52
+#define B2056_SYN_PLL_VCO2              0x53
+#define B2056_SYN_PLL_MONITOR1          0x54
+#define B2056_SYN_PLL_MONITOR2          0x55
+#define B2056_SYN_PLL_VCOCAL1           0x56
+#define B2056_SYN_PLL_VCOCAL2           0x57
+#define B2056_SYN_PLL_VCOCAL4           0x58
+#define B2056_SYN_PLL_VCOCAL5           0x59
+#define B2056_SYN_PLL_VCOCAL6           0x5A
+#define B2056_SYN_PLL_VCOCAL7           0x5B
+#define B2056_SYN_PLL_VCOCAL8           0x5C
+#define B2056_SYN_PLL_VCOCAL9           0x5D
+#define B2056_SYN_PLL_VCOCAL10          0x5E
+#define B2056_SYN_PLL_VCOCAL11          0x5F
+#define B2056_SYN_PLL_VCOCAL12          0x60
+#define B2056_SYN_PLL_VCOCAL13          0x61
+#define B2056_SYN_PLL_VREG              0x62
+#define B2056_SYN_PLL_STATUS1           0x63
+#define B2056_SYN_PLL_STATUS2           0x64
+#define B2056_SYN_PLL_STATUS3           0x65
+#define B2056_SYN_LOGEN_PU0             0x66
+#define B2056_SYN_LOGEN_PU1             0x67
+#define B2056_SYN_LOGEN_PU2             0x68
+#define B2056_SYN_LOGEN_PU3             0x69
+#define B2056_SYN_LOGEN_PU5             0x6A
+#define B2056_SYN_LOGEN_PU6             0x6B
+#define B2056_SYN_LOGEN_PU7             0x6C
+#define B2056_SYN_LOGEN_PU8             0x6D
+#define B2056_SYN_LOGEN_BIAS_RESET      0x6E
+#define B2056_SYN_LOGEN_RCCR1           0x6F
+#define B2056_SYN_LOGEN_VCOBUF1         0x70
+#define B2056_SYN_LOGEN_MIXER1          0x71
+#define B2056_SYN_LOGEN_MIXER2          0x72
+#define B2056_SYN_LOGEN_BUF1            0x73
+#define B2056_SYN_LOGENBUF2             0x74
+#define B2056_SYN_LOGEN_BUF3            0x75
+#define B2056_SYN_LOGEN_BUF4            0x76
+#define B2056_SYN_LOGEN_DIV1            0x77
+#define B2056_SYN_LOGEN_DIV2            0x78
+#define B2056_SYN_LOGEN_DIV3            0x79
+#define B2056_SYN_LOGEN_ACL1            0x7A
+#define B2056_SYN_LOGEN_ACL2            0x7B
+#define B2056_SYN_LOGEN_ACL3            0x7C
+#define B2056_SYN_LOGEN_ACL4            0x7D
+#define B2056_SYN_LOGEN_ACL5            0x7E
+#define B2056_SYN_LOGEN_ACL6            0x7F
+#define B2056_SYN_LOGEN_ACLOUT          0x80
+#define B2056_SYN_LOGEN_ACLCAL1         0x81
+#define B2056_SYN_LOGEN_ACLCAL2         0x82
+#define B2056_SYN_LOGEN_ACLCAL3         0x83
+#define B2056_SYN_CALEN                 0x84
+#define B2056_SYN_LOGEN_PEAKDET1        0x85
+#define B2056_SYN_LOGEN_CORE_ACL_OVR    0x86
+#define B2056_SYN_LOGEN_RX_DIFF_ACL_OVR 0x87
+#define B2056_SYN_LOGEN_TX_DIFF_ACL_OVR 0x88
+#define B2056_SYN_LOGEN_RX_CMOS_ACL_OVR 0x89
+#define B2056_SYN_LOGEN_TX_CMOS_ACL_OVR 0x8A
+#define B2056_SYN_LOGEN_VCOBUF2         0x8B
+#define B2056_SYN_LOGEN_MIXER3          0x8C
+#define B2056_SYN_LOGEN_BUF5            0x8D
+#define B2056_SYN_LOGEN_BUF6            0x8E
+#define B2056_SYN_LOGEN_CBUFRX1         0x8F
+#define B2056_SYN_LOGEN_CBUFRX2         0x90
+#define B2056_SYN_LOGEN_CBUFRX3         0x91
+#define B2056_SYN_LOGEN_CBUFRX4         0x92
+#define B2056_SYN_LOGEN_CBUFTX1         0x93
+#define B2056_SYN_LOGEN_CBUFTX2         0x94
+#define B2056_SYN_LOGEN_CBUFTX3         0x95
+#define B2056_SYN_LOGEN_CBUFTX4         0x96
+#define B2056_SYN_LOGEN_CMOSRX1         0x97
+#define B2056_SYN_LOGEN_CMOSRX2         0x98
+#define B2056_SYN_LOGEN_CMOSRX3         0x99
+#define B2056_SYN_LOGEN_CMOSRX4         0x9A
+#define B2056_SYN_LOGEN_CMOSTX1         0x9B
+#define B2056_SYN_LOGEN_CMOSTX2         0x9C
+#define B2056_SYN_LOGEN_CMOSTX3         0x9D
+#define B2056_SYN_LOGEN_CMOSTX4         0x9E
+#define B2056_SYN_LOGEN_VCOBUF2_OVRVAL  0x9F
+#define B2056_SYN_LOGEN_MIXER3_OVRVAL   0xA0
+#define B2056_SYN_LOGEN_BUF5_OVRVAL     0xA1
+#define B2056_SYN_LOGEN_BUF6_OVRVAL     0xA2
+#define B2056_SYN_LOGEN_CBUFRX1_OVRVAL  0xA3
+#define B2056_SYN_LOGEN_CBUFRX2_OVRVAL  0xA4
+#define B2056_SYN_LOGEN_CBUFRX3_OVRVAL  0xA5
+#define B2056_SYN_LOGEN_CBUFRX4_OVRVAL  0xA6
+#define B2056_SYN_LOGEN_CBUFTX1_OVRVAL  0xA7
+#define B2056_SYN_LOGEN_CBUFTX2_OVRVAL  0xA8
+#define B2056_SYN_LOGEN_CBUFTX3_OVRVAL  0xA9
+#define B2056_SYN_LOGEN_CBUFTX4_OVRVAL  0xAA
+#define B2056_SYN_LOGEN_CMOSRX1_OVRVAL  0xAB
+#define B2056_SYN_LOGEN_CMOSRX2_OVRVAL  0xAC
+#define B2056_SYN_LOGEN_CMOSRX3_OVRVAL  0xAD
+#define B2056_SYN_LOGEN_CMOSRX4_OVRVAL  0xAE
+#define B2056_SYN_LOGEN_CMOSTX1_OVRVAL  0xAF
+#define B2056_SYN_LOGEN_CMOSTX2_OVRVAL  0xB0
+#define B2056_SYN_LOGEN_CMOSTX3_OVRVAL  0xB1
+#define B2056_SYN_LOGEN_CMOSTX4_OVRVAL  0xB2
+#define B2056_SYN_LOGEN_ACL_WAITCNT     0xB3
+#define B2056_SYN_LOGEN_CORE_CALVALID   0xB4
+#define B2056_SYN_LOGEN_RX_CMOS_CALVALID        0xB5
+#define B2056_SYN_LOGEN_TX_CMOS_VALID   0xB6
+
+#define B2056_TX_RESERVED_ADDR0         0x00
+#define B2056_TX_IDCODE                 0x01
+#define B2056_TX_RESERVED_ADDR2         0x02
+#define B2056_TX_RESERVED_ADDR3         0x03
+#define B2056_TX_RESERVED_ADDR4         0x04
+#define B2056_TX_RESERVED_ADDR5         0x05
+#define B2056_TX_RESERVED_ADDR6         0x06
+#define B2056_TX_RESERVED_ADDR7         0x07
+#define B2056_TX_COM_CTRL               0x08
+#define B2056_TX_COM_PU                 0x09
+#define B2056_TX_COM_OVR                0x0A
+#define B2056_TX_COM_RESET              0x0B
+#define B2056_TX_COM_RCAL               0x0C
+#define B2056_TX_COM_RC_RXLPF           0x0D
+#define B2056_TX_COM_RC_TXLPF           0x0E
+#define B2056_TX_COM_RC_RXHPF           0x0F
+#define B2056_TX_RESERVED_ADDR16        0x10
+#define B2056_TX_RESERVED_ADDR17        0x11
+#define B2056_TX_RESERVED_ADDR18        0x12
+#define B2056_TX_RESERVED_ADDR19        0x13
+#define B2056_TX_RESERVED_ADDR20        0x14
+#define B2056_TX_RESERVED_ADDR21        0x15
+#define B2056_TX_RESERVED_ADDR22        0x16
+#define B2056_TX_RESERVED_ADDR23        0x17
+#define B2056_TX_RESERVED_ADDR24        0x18
+#define B2056_TX_RESERVED_ADDR25        0x19
+#define B2056_TX_RESERVED_ADDR26        0x1A
+#define B2056_TX_RESERVED_ADDR27        0x1B
+#define B2056_TX_RESERVED_ADDR28        0x1C
+#define B2056_TX_RESERVED_ADDR29        0x1D
+#define B2056_TX_RESERVED_ADDR30        0x1E
+#define B2056_TX_RESERVED_ADDR31        0x1F
+#define B2056_TX_IQCAL_GAIN_BW          0x20
+#define B2056_TX_LOFT_FINE_I            0x21
+#define B2056_TX_LOFT_FINE_Q            0x22
+#define B2056_TX_LOFT_COARSE_I          0x23
+#define B2056_TX_LOFT_COARSE_Q          0x24
+#define B2056_TX_TX_COM_MASTER1         0x25
+#define B2056_TX_TX_COM_MASTER2         0x26
+#define B2056_TX_RXIQCAL_TXMUX          0x27
+#define B2056_TX_TX_SSI_MASTER          0x28
+#define B2056_TX_IQCAL_VCM_HG           0x29
+#define B2056_TX_IQCAL_IDAC             0x2A
+#define B2056_TX_TSSI_VCM               0x2B
+#define B2056_TX_TX_AMP_DET             0x2C
+#define B2056_TX_TX_SSI_MUX             0x2D
+#define B2056_TX_TSSIA                  0x2E
+#define B2056_TX_TSSIG                  0x2F
+#define B2056_TX_TSSI_MISC1             0x30
+#define B2056_TX_TSSI_MISC2             0x31
+#define B2056_TX_TSSI_MISC3             0x32
+#define B2056_TX_PA_SPARE1              0x33
+#define B2056_TX_PA_SPARE2              0x34
+#define B2056_TX_INTPAA_MASTER          0x35
+#define B2056_TX_INTPAA_GAIN            0x36
+#define B2056_TX_INTPAA_BOOST_TUNE      0x37
+#define B2056_TX_INTPAA_IAUX_STAT       0x38
+#define B2056_TX_INTPAA_IAUX_DYN        0x39
+#define B2056_TX_INTPAA_IMAIN_STAT      0x3A
+#define B2056_TX_INTPAA_IMAIN_DYN       0x3B
+#define B2056_TX_INTPAA_CASCBIAS        0x3C
+#define B2056_TX_INTPAA_PASLOPE         0x3D
+#define B2056_TX_INTPAA_PA_MISC         0x3E
+#define B2056_TX_INTPAG_MASTER          0x3F
+#define B2056_TX_INTPAG_GAIN            0x40
+#define B2056_TX_INTPAG_BOOST_TUNE      0x41
+#define B2056_TX_INTPAG_IAUX_STAT       0x42
+#define B2056_TX_INTPAG_IAUX_DYN        0x43
+#define B2056_TX_INTPAG_IMAIN_STAT      0x44
+#define B2056_TX_INTPAG_IMAIN_DYN       0x45
+#define B2056_TX_INTPAG_CASCBIAS        0x46
+#define B2056_TX_INTPAG_PASLOPE         0x47
+#define B2056_TX_INTPAG_PA_MISC         0x48
+#define B2056_TX_PADA_MASTER            0x49
+#define B2056_TX_PADA_IDAC              0x4A
+#define B2056_TX_PADA_CASCBIAS          0x4B
+#define B2056_TX_PADA_GAIN              0x4C
+#define B2056_TX_PADA_BOOST_TUNE        0x4D
+#define B2056_TX_PADA_SLOPE             0x4E
+#define B2056_TX_PADG_MASTER            0x4F
+#define B2056_TX_PADG_IDAC              0x50
+#define B2056_TX_PADG_CASCBIAS          0x51
+#define B2056_TX_PADG_GAIN              0x52
+#define B2056_TX_PADG_BOOST_TUNE        0x53
+#define B2056_TX_PADG_SLOPE             0x54
+#define B2056_TX_PGAA_MASTER            0x55
+#define B2056_TX_PGAA_IDAC              0x56
+#define B2056_TX_PGAA_GAIN              0x57
+#define B2056_TX_PGAA_BOOST_TUNE        0x58
+#define B2056_TX_PGAA_SLOPE             0x59
+#define B2056_TX_PGAA_MISC              0x5A
+#define B2056_TX_PGAG_MASTER            0x5B
+#define B2056_TX_PGAG_IDAC              0x5C
+#define B2056_TX_PGAG_GAIN              0x5D
+#define B2056_TX_PGAG_BOOST_TUNE        0x5E
+#define B2056_TX_PGAG_SLOPE             0x5F
+#define B2056_TX_PGAG_MISC              0x60
+#define B2056_TX_MIXA_MASTER            0x61
+#define B2056_TX_MIXA_BOOST_TUNE        0x62
+#define B2056_TX_MIXG                   0x63
+#define B2056_TX_MIXG_BOOST_TUNE        0x64
+#define B2056_TX_BB_GM_MASTER           0x65
+#define B2056_TX_GMBB_GM                0x66
+#define B2056_TX_GMBB_IDAC              0x67
+#define B2056_TX_TXLPF_MASTER           0x68
+#define B2056_TX_TXLPF_RCCAL            0x69
+#define B2056_TX_TXLPF_RCCAL_OFF0       0x6A
+#define B2056_TX_TXLPF_RCCAL_OFF1       0x6B
+#define B2056_TX_TXLPF_RCCAL_OFF2       0x6C
+#define B2056_TX_TXLPF_RCCAL_OFF3       0x6D
+#define B2056_TX_TXLPF_RCCAL_OFF4       0x6E
+#define B2056_TX_TXLPF_RCCAL_OFF5       0x6F
+#define B2056_TX_TXLPF_RCCAL_OFF6       0x70
+#define B2056_TX_TXLPF_BW               0x71
+#define B2056_TX_TXLPF_GAIN             0x72
+#define B2056_TX_TXLPF_IDAC             0x73
+#define B2056_TX_TXLPF_IDAC_0           0x74
+#define B2056_TX_TXLPF_IDAC_1           0x75
+#define B2056_TX_TXLPF_IDAC_2           0x76
+#define B2056_TX_TXLPF_IDAC_3           0x77
+#define B2056_TX_TXLPF_IDAC_4           0x78
+#define B2056_TX_TXLPF_IDAC_5           0x79
+#define B2056_TX_TXLPF_IDAC_6           0x7A
+#define B2056_TX_TXLPF_OPAMP_IDAC       0x7B
+#define B2056_TX_TXLPF_MISC             0x7C
+#define B2056_TX_TXSPARE1               0x7D
+#define B2056_TX_TXSPARE2               0x7E
+#define B2056_TX_TXSPARE3               0x7F
+#define B2056_TX_TXSPARE4               0x80
+#define B2056_TX_TXSPARE5               0x81
+#define B2056_TX_TXSPARE6               0x82
+#define B2056_TX_TXSPARE7               0x83
+#define B2056_TX_TXSPARE8               0x84
+#define B2056_TX_TXSPARE9               0x85
+#define B2056_TX_TXSPARE10              0x86
+#define B2056_TX_TXSPARE11              0x87
+#define B2056_TX_TXSPARE12              0x88
+#define B2056_TX_TXSPARE13              0x89
+#define B2056_TX_TXSPARE14              0x8A
+#define B2056_TX_TXSPARE15              0x8B
+#define B2056_TX_TXSPARE16              0x8C
+#define B2056_TX_STATUS_INTPA_GAIN      0x8D
+#define B2056_TX_STATUS_PAD_GAIN        0x8E
+#define B2056_TX_STATUS_PGA_GAIN        0x8F
+#define B2056_TX_STATUS_GM_TXLPF_GAIN   0x90
+#define B2056_TX_STATUS_TXLPF_BW        0x91
+#define B2056_TX_STATUS_TXLPF_RC        0x92
+#define B2056_TX_GMBB_IDAC0             0x93
+#define B2056_TX_GMBB_IDAC1             0x94
+#define B2056_TX_GMBB_IDAC2             0x95
+#define B2056_TX_GMBB_IDAC3             0x96
+#define B2056_TX_GMBB_IDAC4             0x97
+#define B2056_TX_GMBB_IDAC5             0x98
+#define B2056_TX_GMBB_IDAC6             0x99
+#define B2056_TX_GMBB_IDAC7             0x9A
+
+#define B2056_RX_RESERVED_ADDR0         0x00
+#define B2056_RX_IDCODE                 0x01
+#define B2056_RX_RESERVED_ADDR2         0x02
+#define B2056_RX_RESERVED_ADDR3         0x03
+#define B2056_RX_RESERVED_ADDR4         0x04
+#define B2056_RX_RESERVED_ADDR5         0x05
+#define B2056_RX_RESERVED_ADDR6         0x06
+#define B2056_RX_RESERVED_ADDR7         0x07
+#define B2056_RX_COM_CTRL               0x08
+#define B2056_RX_COM_PU                 0x09
+#define B2056_RX_COM_OVR                0x0A
+#define B2056_RX_COM_RESET              0x0B
+#define B2056_RX_COM_RCAL               0x0C
+#define B2056_RX_COM_RC_RXLPF           0x0D
+#define B2056_RX_COM_RC_TXLPF           0x0E
+#define B2056_RX_COM_RC_RXHPF           0x0F
+#define B2056_RX_RESERVED_ADDR16        0x10
+#define B2056_RX_RESERVED_ADDR17        0x11
+#define B2056_RX_RESERVED_ADDR18        0x12
+#define B2056_RX_RESERVED_ADDR19        0x13
+#define B2056_RX_RESERVED_ADDR20        0x14
+#define B2056_RX_RESERVED_ADDR21        0x15
+#define B2056_RX_RESERVED_ADDR22        0x16
+#define B2056_RX_RESERVED_ADDR23        0x17
+#define B2056_RX_RESERVED_ADDR24        0x18
+#define B2056_RX_RESERVED_ADDR25        0x19
+#define B2056_RX_RESERVED_ADDR26        0x1A
+#define B2056_RX_RESERVED_ADDR27        0x1B
+#define B2056_RX_RESERVED_ADDR28        0x1C
+#define B2056_RX_RESERVED_ADDR29        0x1D
+#define B2056_RX_RESERVED_ADDR30        0x1E
+#define B2056_RX_RESERVED_ADDR31        0x1F
+#define B2056_RX_RXIQCAL_RXMUX          0x20
+#define B2056_RX_RSSI_PU                0x21
+#define B2056_RX_RSSI_SEL               0x22
+#define B2056_RX_RSSI_GAIN              0x23
+#define B2056_RX_RSSI_NB_IDAC           0x24
+#define B2056_RX_RSSI_WB2I_IDAC_1       0x25
+#define B2056_RX_RSSI_WB2I_IDAC_2       0x26
+#define B2056_RX_RSSI_WB2Q_IDAC_1       0x27
+#define B2056_RX_RSSI_WB2Q_IDAC_2       0x28
+#define B2056_RX_RSSI_POLE              0x29
+#define B2056_RX_RSSI_WB1_IDAC          0x2A
+#define B2056_RX_RSSI_MISC              0x2B
+#define B2056_RX_LNAA_MASTER            0x2C
+#define B2056_RX_LNAA_TUNE              0x2D
+#define B2056_RX_LNAA_GAIN              0x2E
+#define B2056_RX_LNA_A_SLOPE            0x2F
+#define B2056_RX_BIASPOLE_LNAA1_IDAC    0x30
+#define B2056_RX_LNAA2_IDAC             0x31
+#define B2056_RX_LNA1A_MISC             0x32
+#define B2056_RX_LNAG_MASTER            0x33
+#define B2056_RX_LNAG_TUNE              0x34
+#define B2056_RX_LNAG_GAIN              0x35
+#define B2056_RX_LNA_G_SLOPE            0x36
+#define B2056_RX_BIASPOLE_LNAG1_IDAC    0x37
+#define B2056_RX_LNAG2_IDAC             0x38
+#define B2056_RX_LNA1G_MISC             0x39
+#define B2056_RX_MIXA_MASTER            0x3A
+#define B2056_RX_MIXA_VCM               0x3B
+#define B2056_RX_MIXA_CTRLPTAT          0x3C
+#define B2056_RX_MIXA_LOB_BIAS          0x3D
+#define B2056_RX_MIXA_CORE_IDAC         0x3E
+#define B2056_RX_MIXA_CMFB_IDAC         0x3F
+#define B2056_RX_MIXA_BIAS_AUX          0x40
+#define B2056_RX_MIXA_BIAS_MAIN         0x41
+#define B2056_RX_MIXA_BIAS_MISC         0x42
+#define B2056_RX_MIXA_MAST_BIAS         0x43
+#define B2056_RX_MIXG_MASTER            0x44
+#define B2056_RX_MIXG_VCM               0x45
+#define B2056_RX_MIXG_CTRLPTAT          0x46
+#define B2056_RX_MIXG_LOB_BIAS          0x47
+#define B2056_RX_MIXG_CORE_IDAC         0x48
+#define B2056_RX_MIXG_CMFB_IDAC         0x49
+#define B2056_RX_MIXG_BIAS_AUX          0x4A
+#define B2056_RX_MIXG_BIAS_MAIN         0x4B
+#define B2056_RX_MIXG_BIAS_MISC         0x4C
+#define B2056_RX_MIXG_MAST_BIAS         0x4D
+#define B2056_RX_TIA_MASTER             0x4E
+#define B2056_RX_TIA_IOPAMP             0x4F
+#define B2056_RX_TIA_QOPAMP             0x50
+#define B2056_RX_TIA_IMISC              0x51
+#define B2056_RX_TIA_QMISC              0x52
+#define B2056_RX_TIA_GAIN               0x53
+#define B2056_RX_TIA_SPARE1             0x54
+#define B2056_RX_TIA_SPARE2             0x55
+#define B2056_RX_BB_LPF_MASTER          0x56
+#define B2056_RX_AACI_MASTER            0x57
+#define B2056_RX_RXLPF_IDAC             0x58
+#define B2056_RX_RXLPF_OPAMPBIAS_LOWQ   0x59
+#define B2056_RX_RXLPF_OPAMPBIAS_HIGHQ  0x5A
+#define B2056_RX_RXLPF_BIAS_DCCANCEL    0x5B
+#define B2056_RX_RXLPF_OUTVCM           0x5C
+#define B2056_RX_RXLPF_INVCM_BODY       0x5D
+#define B2056_RX_RXLPF_CC_OP            0x5E
+#define B2056_RX_RXLPF_GAIN             0x5F
+#define B2056_RX_RXLPF_Q_BW             0x60
+#define B2056_RX_RXLPF_HP_CORNER_BW     0x61
+#define B2056_RX_RXLPF_RCCAL_HPC        0x62
+#define B2056_RX_RXHPF_OFF0             0x63
+#define B2056_RX_RXHPF_OFF1             0x64
+#define B2056_RX_RXHPF_OFF2             0x65
+#define B2056_RX_RXHPF_OFF3             0x66
+#define B2056_RX_RXHPF_OFF4             0x67
+#define B2056_RX_RXHPF_OFF5             0x68
+#define B2056_RX_RXHPF_OFF6             0x69
+#define B2056_RX_RXHPF_OFF7             0x6A
+#define B2056_RX_RXLPF_RCCAL_LPC        0x6B
+#define B2056_RX_RXLPF_OFF_0            0x6C
+#define B2056_RX_RXLPF_OFF_1            0x6D
+#define B2056_RX_RXLPF_OFF_2            0x6E
+#define B2056_RX_RXLPF_OFF_3            0x6F
+#define B2056_RX_RXLPF_OFF_4            0x70
+#define B2056_RX_UNUSED                 0x71
+#define B2056_RX_VGA_MASTER             0x72
+#define B2056_RX_VGA_BIAS               0x73
+#define B2056_RX_VGA_BIAS_DCCANCEL      0x74
+#define B2056_RX_VGA_GAIN               0x75
+#define B2056_RX_VGA_HP_CORNER_BW       0x76
+#define B2056_RX_VGABUF_BIAS            0x77
+#define B2056_RX_VGABUF_GAIN_BW         0x78
+#define B2056_RX_TXFBMIX_A              0x79
+#define B2056_RX_TXFBMIX_G              0x7A
+#define B2056_RX_RXSPARE1               0x7B
+#define B2056_RX_RXSPARE2               0x7C
+#define B2056_RX_RXSPARE3               0x7D
+#define B2056_RX_RXSPARE4               0x7E
+#define B2056_RX_RXSPARE5               0x7F
+#define B2056_RX_RXSPARE6               0x80
+#define B2056_RX_RXSPARE7               0x81
+#define B2056_RX_RXSPARE8               0x82
+#define B2056_RX_RXSPARE9               0x83
+#define B2056_RX_RXSPARE10              0x84
+#define B2056_RX_RXSPARE11              0x85
+#define B2056_RX_RXSPARE12              0x86
+#define B2056_RX_RXSPARE13              0x87
+#define B2056_RX_RXSPARE14              0x88
+#define B2056_RX_RXSPARE15              0x89
+#define B2056_RX_RXSPARE16              0x8A
+#define B2056_RX_STATUS_LNAA_GAIN       0x8B
+#define B2056_RX_STATUS_LNAG_GAIN       0x8C
+#define B2056_RX_STATUS_MIXTIA_GAIN     0x8D
+#define B2056_RX_STATUS_RXLPF_GAIN      0x8E
+#define B2056_RX_STATUS_VGA_BUF_GAIN    0x8F
+#define B2056_RX_STATUS_RXLPF_Q         0x90
+#define B2056_RX_STATUS_RXLPF_BUF_BW    0x91
+#define B2056_RX_STATUS_RXLPF_VGA_HPC   0x92
+#define B2056_RX_STATUS_RXLPF_RC        0x93
+#define B2056_RX_STATUS_HPC_RC          0x94
+
+#define B2056_LNA1_A_PU                 0x01
+#define B2056_LNA2_A_PU                 0x02
+#define B2056_LNA1_G_PU                 0x01
+#define B2056_LNA2_G_PU                 0x02
+#define B2056_MIXA_PU_I                 0x01
+#define B2056_MIXA_PU_Q                 0x02
+#define B2056_MIXA_PU_GM                0x10
+#define B2056_MIXG_PU_I                 0x01
+#define B2056_MIXG_PU_Q                 0x02
+#define B2056_MIXG_PU_GM                0x10
+#define B2056_TIA_PU                    0x01
+#define B2056_BB_LPF_PU                 0x20
+#define B2056_W1_PU                     0x02
+#define B2056_W2_PU                     0x04
+#define B2056_NB_PU                     0x08
+#define B2056_RSSI_W1_SEL               0x02
+#define B2056_RSSI_W2_SEL               0x04
+#define B2056_RSSI_NB_SEL               0x08
+#define B2056_VCM_MASK                  0x1C
+#define B2056_RSSI_VCM_SHIFT            0x02
+
 struct b43_nphy_channeltab_entry_rev3 {
-        /* The channel number */
-        u8 channel;
         /* The channel frequency in MHz */
         u16 freq;
         /* Radio register values on channelswitch */
-        /* TODO */
+        u8 radio_syn_pll_vcocal1;
+        u8 radio_syn_pll_vcocal2;
+        u8 radio_syn_pll_refdiv;
+        u8 radio_syn_pll_mmd2;
+        u8 radio_syn_pll_mmd1;
+        u8 radio_syn_pll_loopfilter1;
+        u8 radio_syn_pll_loopfilter2;
+        u8 radio_syn_pll_loopfilter3;
+        u8 radio_syn_pll_loopfilter4;
+        u8 radio_syn_pll_loopfilter5;
+        u8 radio_syn_reserved_addr27;
+        u8 radio_syn_reserved_addr28;
+        u8 radio_syn_reserved_addr29;
+        u8 radio_syn_logen_vcobuf1;
+        u8 radio_syn_logen_mixer2;
+        u8 radio_syn_logen_buf3;
+        u8 radio_syn_logen_buf4;
+        u8 radio_rx0_lnaa_tune;
+        u8 radio_rx0_lnag_tune;
+        u8 radio_tx0_intpaa_boost_tune;
+        u8 radio_tx0_intpag_boost_tune;
+        u8 radio_tx0_pada_boost_tune;
+        u8 radio_tx0_padg_boost_tune;
+        u8 radio_tx0_pgaa_boost_tune;
+        u8 radio_tx0_pgag_boost_tune;
+        u8 radio_tx0_mixa_boost_tune;
+        u8 radio_tx0_mixg_boost_tune;
+        u8 radio_rx1_lnaa_tune;
+        u8 radio_rx1_lnag_tune;
+        u8 radio_tx1_intpaa_boost_tune;
+        u8 radio_tx1_intpag_boost_tune;
+        u8 radio_tx1_pada_boost_tune;
+        u8 radio_tx1_padg_boost_tune;
+        u8 radio_tx1_pgaa_boost_tune;
+        u8 radio_tx1_pgag_boost_tune;
+        u8 radio_tx1_mixa_boost_tune;
+        u8 radio_tx1_mixg_boost_tune;
         /* PHY register values on channelswitch */
         struct b43_phy_n_sfo_cfg phy_regs;
 };
 
+void b2056_upload_inittabs(struct b43_wldev *dev,
+                           bool ghz5, bool ignore_uploadflag);
+
 #endif /* B43_RADIO_2056_H_ */
diff --git a/drivers/net/wireless/b43/rfkill.c b/drivers/net/wireless/b43/rfkill.c
index 78016ae21c50..86bc0a0f735c 100644
--- a/drivers/net/wireless/b43/rfkill.c
+++ b/drivers/net/wireless/b43/rfkill.c
@@ -28,23 +28,8 @@
 /* Returns TRUE, if the radio is enabled in hardware. */
 bool b43_is_hw_radio_enabled(struct b43_wldev *dev)
 {
-        if (dev->phy.rev >= 3 || dev->phy.type == B43_PHYTYPE_LP) {
-                if (!(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI)
-                      & B43_MMIO_RADIO_HWENABLED_HI_MASK))
-                        return 1;
-        } else {
-                /* To prevent CPU fault on PPC, do not read a register
-                 * unless the interface is started; however, on resume
-                 * for hibernation, this routine is entered early. When
-                 * that happens, unconditionally return TRUE.
-                 */
-                if (b43_status(dev) < B43_STAT_STARTED)
-                        return 1;
-                if (b43_read16(dev, B43_MMIO_RADIO_HWENABLED_LO)
-                    & B43_MMIO_RADIO_HWENABLED_LO_MASK)
-                        return 1;
-        }
-        return 0;
+        return !(b43_read32(dev, B43_MMIO_RADIO_HWENABLED_HI)
+                & B43_MMIO_RADIO_HWENABLED_HI_MASK);
 }
 
 /* The poll callback for the hardware button. */
diff --git a/drivers/net/wireless/b43/tables_nphy.c b/drivers/net/wireless/b43/tables_nphy.c
index d60db078eae2..dc8ef09a8552 100644
--- a/drivers/net/wireless/b43/tables_nphy.c
+++ b/drivers/net/wireless/b43/tables_nphy.c
@@ -28,41 +28,41 @@
 #include "phy_n.h"
 
 static const u8 b43_ntab_adjustpower0[] = {
-        0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01,
-        0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03,
-        0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x05,
-        0x06, 0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07,
-        0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x09,
-        0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B,
-        0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D,
-        0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x0F,
-        0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11, 0x11,
-        0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13,
-        0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15,
-        0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17, 0x17,
-        0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19,
-        0x1A, 0x1A, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1B,
-        0x1C, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
-        0x1E, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x1F,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };
 
 static const u8 b43_ntab_adjustpower1[] = {
-        0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01,
-        0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x03,
-        0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, 0x05,
-        0x06, 0x06, 0x06, 0x06, 0x07, 0x07, 0x07, 0x07,
-        0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x09, 0x09,
-        0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0B, 0x0B, 0x0B,
-        0x0C, 0x0C, 0x0C, 0x0C, 0x0D, 0x0D, 0x0D, 0x0D,
-        0x0E, 0x0E, 0x0E, 0x0E, 0x0F, 0x0F, 0x0F, 0x0F,
-        0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11, 0x11,
-        0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13,
-        0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15,
-        0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17, 0x17,
-        0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x19, 0x19,
-        0x1A, 0x1A, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1B,
-        0x1C, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
-        0x1E, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, 0x1F,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 };
 
 static const u16 b43_ntab_bdi[] = {
@@ -130,8 +130,8 @@ static const u32 b43_ntab_framestruct[] = {
         0x09804506, 0x00100030, 0x09804507, 0x00100030,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
-        0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028,
-        0x0980450E, 0x00100038, 0x0980450F, 0x00100038,
+        0x08004A0C, 0x00100004, 0x01000A0D, 0x00100024,
+        0x0980450E, 0x00100034, 0x0980450F, 0x00100034,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000A04, 0x00100000, 0x11008A05, 0x00100020,
@@ -202,13 +202,13 @@ static const u32 b43_ntab_framestruct[] = {
         0x53028A06, 0x01900060, 0x53028A07, 0x01900060,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
-        0x4002140C, 0x000F4810, 0x6203140D, 0x00100050,
-        0x53028A0E, 0x01900070, 0x53028A0F, 0x01900070,
+        0x4002140C, 0x000F4808, 0x6203140D, 0x00100048,
+        0x53028A0E, 0x01900068, 0x53028A0F, 0x01900068,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
-        0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028,
-        0x1980C50E, 0x00100038, 0x2181050E, 0x00100038,
-        0x2181050E, 0x00100038, 0x0180050C, 0x00100038,
+        0x00000A0C, 0x00100004, 0x11008A0D, 0x00100024,
+        0x1980C50E, 0x00100034, 0x2181050E, 0x00100034,
+        0x2181050E, 0x00100034, 0x0180050C, 0x00100038,
         0x1180850D, 0x00100038, 0x1181850D, 0x00100038,
         0x2981450F, 0x01100038, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -238,9 +238,9 @@ static const u32 b43_ntab_framestruct[] = {
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
-        0x4002140C, 0x00100010, 0x0200140D, 0x00100050,
-        0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070,
-        0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070,
+        0x4002140C, 0x00100008, 0x0200140D, 0x00100048,
+        0x0B004A0E, 0x01900068, 0x13008A0E, 0x01900068,
+        0x13008A0E, 0x01900068, 0x43020A0C, 0x00100070,
         0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070,
         0x23010A0F, 0x01500070, 0x00000000, 0x00000000,
         0x00000000, 0x00000000, 0x00000000, 0x00000000,
@@ -337,73 +337,73 @@ static const u32 b43_ntab_framestruct[] = {
 };
 
 static const u32 b43_ntab_gainctl0[] = {
-        0x007F003F, 0x007E013F, 0x007D023E, 0x007C033E,
-        0x007B043D, 0x007A053D, 0x0079063C, 0x0078073C,
-        0x0077083B, 0x0076093B, 0x00750A3A, 0x00740B3A,
-        0x00730C39, 0x00720D39, 0x00710E38, 0x00700F38,
-        0x006F0037, 0x006E0137, 0x006D0236, 0x006C0336,
-        0x006B0435, 0x006A0535, 0x00690634, 0x00680734,
-        0x00670833, 0x00660933, 0x00650A32, 0x00640B32,
-        0x00630C31, 0x00620D31, 0x00610E30, 0x00600F30,
-        0x005F002F, 0x005E012F, 0x005D022E, 0x005C032E,
-        0x005B042D, 0x005A052D, 0x0059062C, 0x0058072C,
-        0x0057082B, 0x0056092B, 0x00550A2A, 0x00540B2A,
-        0x00530C29, 0x00520D29, 0x00510E28, 0x00500F28,
-        0x004F0027, 0x004E0127, 0x004D0226, 0x004C0326,
-        0x004B0425, 0x004A0525, 0x00490624, 0x00480724,
-        0x00470823, 0x00460923, 0x00450A22, 0x00440B22,
-        0x00430C21, 0x00420D21, 0x00410E20, 0x00400F20,
-        0x003F001F, 0x003E011F, 0x003D021E, 0x003C031E,
-        0x003B041D, 0x003A051D, 0x0039061C, 0x0038071C,
-        0x0037081B, 0x0036091B, 0x00350A1A, 0x00340B1A,
-        0x00330C19, 0x00320D19, 0x00310E18, 0x00300F18,
-        0x002F0017, 0x002E0117, 0x002D0216, 0x002C0316,
-        0x002B0415, 0x002A0515, 0x00290614, 0x00280714,
-        0x00270813, 0x00260913, 0x00250A12, 0x00240B12,
-        0x00230C11, 0x00220D11, 0x00210E10, 0x00200F10,
-        0x001F000F, 0x001E010F, 0x001D020E, 0x001C030E,
-        0x001B040D, 0x001A050D, 0x0019060C, 0x0018070C,
-        0x0017080B, 0x0016090B, 0x00150A0A, 0x00140B0A,
-        0x00130C09, 0x00120D09, 0x00110E08, 0x00100F08,
-        0x000F0007, 0x000E0107, 0x000D0206, 0x000C0306,
-        0x000B0405, 0x000A0505, 0x00090604, 0x00080704,
-        0x00070803, 0x00060903, 0x00050A02, 0x00040B02,
-        0x00030C01, 0x00020D01, 0x00010E00, 0x00000F00,
+        0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E,
+        0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42,
+        0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B,
+        0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34,
+        0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E,
+        0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38,
+        0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32,
+        0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44,
+        0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D,
+        0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36,
+        0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40,
+        0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39,
+        0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33,
+        0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D,
+        0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E,
+        0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38,
+        0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42,
+        0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B,
+        0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34,
+        0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44,
+        0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D,
+        0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36,
+        0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30,
+        0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B,
+        0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26,
+        0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22,
+        0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E,
+        0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B,
+        0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18,
+        0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
+        0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
+        0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00,
 };
 
 static const u32 b43_ntab_gainctl1[] = {
-        0x007F003F, 0x007E013F, 0x007D023E, 0x007C033E,
-        0x007B043D, 0x007A053D, 0x0079063C, 0x0078073C,
-        0x0077083B, 0x0076093B, 0x00750A3A, 0x00740B3A,
-        0x00730C39, 0x00720D39, 0x00710E38, 0x00700F38,
-        0x006F0037, 0x006E0137, 0x006D0236, 0x006C0336,
-        0x006B0435, 0x006A0535, 0x00690634, 0x00680734,
-        0x00670833, 0x00660933, 0x00650A32, 0x00640B32,
-        0x00630C31, 0x00620D31, 0x00610E30, 0x00600F30,
-        0x005F002F, 0x005E012F, 0x005D022E, 0x005C032E,
-        0x005B042D, 0x005A052D, 0x0059062C, 0x0058072C,
-        0x0057082B, 0x0056092B, 0x00550A2A, 0x00540B2A,
-        0x00530C29, 0x00520D29, 0x00510E28, 0x00500F28,
-        0x004F0027, 0x004E0127, 0x004D0226, 0x004C0326,
-        0x004B0425, 0x004A0525, 0x00490624, 0x00480724,
-        0x00470823, 0x00460923, 0x00450A22, 0x00440B22,
-        0x00430C21, 0x00420D21, 0x00410E20, 0x00400F20,
-        0x003F001F, 0x003E011F, 0x003D021E, 0x003C031E,
-        0x003B041D, 0x003A051D, 0x0039061C, 0x0038071C,
-        0x0037081B, 0x0036091B, 0x00350A1A, 0x00340B1A,
-        0x00330C19, 0x00320D19, 0x00310E18, 0x00300F18,
-        0x002F0017, 0x002E0117, 0x002D0216, 0x002C0316,
-        0x002B0415, 0x002A0515, 0x00290614, 0x00280714,
-        0x00270813, 0x00260913, 0x00250A12, 0x00240B12,
-        0x00230C11, 0x00220D11, 0x00210E10, 0x00200F10,
-        0x001F000F, 0x001E010F, 0x001D020E, 0x001C030E,
-        0x001B040D, 0x001A050D, 0x0019060C, 0x0018070C,
-        0x0017080B, 0x0016090B, 0x00150A0A, 0x00140B0A,
-        0x00130C09, 0x00120D09, 0x00110E08, 0x00100F08,
-        0x000F0007, 0x000E0107, 0x000D0206, 0x000C0306,
-        0x000B0405, 0x000A0505, 0x00090604, 0x00080704,
-        0x00070803, 0x00060903, 0x00050A02, 0x00040B02,
-        0x00030C01, 0x00020D01, 0x00010E00, 0x00000F00,
+        0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E,
+        0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42,
+        0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B,
+        0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34,
+        0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E,
+        0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38,
+        0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32,
+        0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44,
+        0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D,
+        0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36,
+        0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40,
+        0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39,
+        0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33,
+        0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D,
+        0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E,
+        0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38,
+        0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42,
+        0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B,
+        0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34,
+        0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44,
+        0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D,
+        0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36,
+        0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30,
+        0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B,
+        0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26,
+        0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22,
+        0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E,
+        0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B,
+        0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18,
+        0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
+        0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18,
+        0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00,
 };
 
 static const u32 b43_ntab_intlevel[] = {
@@ -1811,9 +1811,7 @@ void b43_ntab_write_bulk(struct b43_wldev *dev, u32 offset,
 }
 
 #define ntab_upload(dev, offset, data) do { \
-                unsigned int i;                                         \
-                for (i = 0; i < (offset##_SIZE); i++)                   \
-                        b43_ntab_write(dev, (offset) + i, (data)[i]);   \
+                b43_ntab_write_bulk(dev, offset, offset##_SIZE, data);  \
         } while (0)
 
 void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
@@ -1825,24 +1823,24 @@ void b43_nphy_rev0_1_2_tables_init(struct b43_wldev *dev)
         ntab_upload(dev, B43_NTAB_TDTRN, b43_ntab_tdtrn);
         ntab_upload(dev, B43_NTAB_INTLEVEL, b43_ntab_intlevel);
         ntab_upload(dev, B43_NTAB_PILOT, b43_ntab_pilot);
-        ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
         ntab_upload(dev, B43_NTAB_TDI20A0, b43_ntab_tdi20a0);
         ntab_upload(dev, B43_NTAB_TDI20A1, b43_ntab_tdi20a1);
         ntab_upload(dev, B43_NTAB_TDI40A0, b43_ntab_tdi40a0);
         ntab_upload(dev, B43_NTAB_TDI40A1, b43_ntab_tdi40a1);
-        ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
         ntab_upload(dev, B43_NTAB_CHANEST, b43_ntab_channelest);
         ntab_upload(dev, B43_NTAB_MCS, b43_ntab_mcs);
-
-        /* Volatile tables */
         ntab_upload(dev, B43_NTAB_NOISEVAR10, b43_ntab_noisevar10);
         ntab_upload(dev, B43_NTAB_NOISEVAR11, b43_ntab_noisevar11);
+
+        /* Volatile tables */
+        ntab_upload(dev, B43_NTAB_BDI, b43_ntab_bdi);
+        ntab_upload(dev, B43_NTAB_PILOTLT, b43_ntab_pilotlt);
+        ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
+        ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
         ntab_upload(dev, B43_NTAB_C0_ESTPLT, b43_ntab_estimatepowerlt0);
         ntab_upload(dev, B43_NTAB_C1_ESTPLT, b43_ntab_estimatepowerlt1);
         ntab_upload(dev, B43_NTAB_C0_ADJPLT, b43_ntab_adjustpower0);
         ntab_upload(dev, B43_NTAB_C1_ADJPLT, b43_ntab_adjustpower1);
-        ntab_upload(dev, B43_NTAB_C0_GAINCTL, b43_ntab_gainctl0);
-        ntab_upload(dev, B43_NTAB_C1_GAINCTL, b43_ntab_gainctl1);
         ntab_upload(dev, B43_NTAB_C0_IQLT, b43_ntab_iqlt0);
         ntab_upload(dev, B43_NTAB_C1_IQLT, b43_ntab_iqlt1);
         ntab_upload(dev, B43_NTAB_C0_LOFEEDTH, b43_ntab_loftlt0);
diff --git a/drivers/net/wireless/b43legacy/main.c b/drivers/net/wireless/b43legacy/main.c
index 67f18ecdb3bf..1f11e1670bf0 100644
--- a/drivers/net/wireless/b43legacy/main.c
+++ b/drivers/net/wireless/b43legacy/main.c
@@ -181,52 +181,75 @@ static int b43legacy_ratelimit(struct b43legacy_wl *wl)
 
 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (!b43legacy_ratelimit(wl))
                 return;
+
         va_start(args, fmt);
-        printk(KERN_INFO "b43legacy-%s: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_INFO "b43legacy-%s: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (!b43legacy_ratelimit(wl))
                 return;
+
         va_start(args, fmt);
-        printk(KERN_ERR "b43legacy-%s ERROR: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_ERR "b43legacy-%s ERROR: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         if (!b43legacy_ratelimit(wl))
                 return;
+
         va_start(args, fmt);
-        printk(KERN_WARNING "b43legacy-%s warning: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_WARNING "b43legacy-%s warning: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 
 #if B43legacy_DEBUG
 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 {
+        struct va_format vaf;
         va_list args;
 
         va_start(args, fmt);
-        printk(KERN_DEBUG "b43legacy-%s debug: ",
-               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
-        vprintk(fmt, args);
+
+        vaf.fmt = fmt;
+        vaf.va = &args;
+
+        printk(KERN_DEBUG "b43legacy-%s debug: %pV",
+               (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
+
         va_end(args);
 }
 #endif /* DEBUG */
diff --git a/drivers/net/wireless/b43legacy/rfkill.c b/drivers/net/wireless/b43legacy/rfkill.c
index d579df72b783..b90f223fb31c 100644
--- a/drivers/net/wireless/b43legacy/rfkill.c
+++ b/drivers/net/wireless/b43legacy/rfkill.c
@@ -29,7 +29,7 @@
 /* Returns TRUE, if the radio is enabled in hardware. */
 bool b43legacy_is_hw_radio_enabled(struct b43legacy_wldev *dev)
 {
-        if (dev->phy.rev >= 3) {
+        if (dev->dev->id.revision >= 3) {
                 if (!(b43legacy_read32(dev, B43legacy_MMIO_RADIO_HWENABLED_HI)
                       & B43legacy_MMIO_RADIO_HWENABLED_HI_MASK))
                         return 1;
diff --git a/drivers/net/wireless/hostap/hostap_ap.c b/drivers/net/wireless/hostap/hostap_ap.c
index dbb986946e1a..18d63f57777d 100644
--- a/drivers/net/wireless/hostap/hostap_ap.c
+++ b/drivers/net/wireless/hostap/hostap_ap.c
@@ -858,7 +858,10 @@ void hostap_free_data(struct ap_data *ap)
                 return;
         }
 
+        flush_work_sync(&ap->add_sta_proc_queue);
+
 #ifndef PRISM2_NO_KERNEL_IEEE80211_MGMT
+        flush_work_sync(&ap->wds_oper_queue);
         if (ap->crypt)
                 ap->crypt->deinit(ap->crypt_priv);
         ap->crypt = ap->crypt_priv = NULL;
diff --git a/drivers/net/wireless/hostap/hostap_hw.c b/drivers/net/wireless/hostap/hostap_hw.c
index b7cb165d612b..a8bddd81b4d1 100644
--- a/drivers/net/wireless/hostap/hostap_hw.c
+++ b/drivers/net/wireless/hostap/hostap_hw.c
@@ -3317,7 +3317,13 @@ static void prism2_free_local_data(struct net_device *dev)
 
         unregister_netdev(local->dev);
 
-        flush_scheduled_work();
+        flush_work_sync(&local->reset_queue);
+        flush_work_sync(&local->set_multicast_list_queue);
+        flush_work_sync(&local->set_tim_queue);
+#ifndef PRISM2_NO_STATION_MODES
+        flush_work_sync(&local->info_queue);
+#endif
+        flush_work_sync(&local->comms_qual_update);
 
         lib80211_crypt_info_free(&local->crypt_info);
 
diff --git a/drivers/net/wireless/hostap/hostap_main.c b/drivers/net/wireless/hostap/hostap_main.c
index 25a2722c8a98..1d9aed645723 100644
--- a/drivers/net/wireless/hostap/hostap_main.c
+++ b/drivers/net/wireless/hostap/hostap_main.c
@@ -891,7 +891,6 @@ void hostap_setup_dev(struct net_device *dev, local_info_t *local,
 
         SET_ETHTOOL_OPS(dev, &prism2_ethtool_ops);
 
-        netif_stop_queue(dev);
 }
 
 static int hostap_enable_hostapd(local_info_t *local, int rtnl_locked)
diff --git a/drivers/net/wireless/iwlwifi/Kconfig b/drivers/net/wireless/iwlwifi/Kconfig
index b82364258dc5..ed424574160e 100644
--- a/drivers/net/wireless/iwlwifi/Kconfig
+++ b/drivers/net/wireless/iwlwifi/Kconfig
@@ -106,6 +106,9 @@ config IWL5000
                 Intel WiFi Link 1000BGN
                 Intel Wireless WiFi 5150AGN
                 Intel Wireless WiFi 5100AGN, 5300AGN, and 5350AGN
+                Intel 6000 Gen 2 Series Wi-Fi Adapters (6000G2A and 6000G2B)
+                Intel WIreless WiFi Link 6050BGN Gen 2 Adapter
+                Intel 100 Series Wi-Fi Adapters (100BGN and 130BGN)
 
 config IWL3945
         tristate "Intel PRO/Wireless 3945ABG/BG Network Connection (iwl3945)"
diff --git a/drivers/net/wireless/iwlwifi/Makefile b/drivers/net/wireless/iwlwifi/Makefile
index 63edbe2e557f..93380f97835f 100644
--- a/drivers/net/wireless/iwlwifi/Makefile
+++ b/drivers/net/wireless/iwlwifi/Makefile
@@ -2,20 +2,27 @@ obj-$(CONFIG_IWLWIFI)	+= iwlcore.o
 iwlcore-objs            := iwl-core.o iwl-eeprom.o iwl-hcmd.o iwl-power.o
 iwlcore-objs            += iwl-rx.o iwl-tx.o iwl-sta.o
 iwlcore-objs            += iwl-scan.o iwl-led.o
+iwlcore-$(CONFIG_IWL3945) += iwl-legacy.o
+iwlcore-$(CONFIG_IWL4965) += iwl-legacy.o
 iwlcore-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-debugfs.o
 iwlcore-$(CONFIG_IWLWIFI_DEVICE_TRACING) += iwl-devtrace.o
 
+# If 3945 is selected only, iwl-legacy.o will be added
+# to iwlcore-m above, but it needs to be built in.
+iwlcore-objs += $(iwlcore-m)
+
 CFLAGS_iwl-devtrace.o := -I$(src)
 
 # AGN
 obj-$(CONFIG_IWLAGN)    += iwlagn.o
-iwlagn-objs             := iwl-agn.o iwl-agn-rs.o iwl-agn-led.o iwl-agn-ict.o
-iwlagn-objs             += iwl-agn-ucode.o iwl-agn-hcmd.o iwl-agn-tx.o
+iwlagn-objs             := iwl-agn.o iwl-agn-rs.o iwl-agn-led.o
+iwlagn-objs             += iwl-agn-ucode.o iwl-agn-tx.o
 iwlagn-objs             += iwl-agn-lib.o iwl-agn-rx.o iwl-agn-calib.o
 iwlagn-objs             += iwl-agn-tt.o iwl-agn-sta.o iwl-agn-eeprom.o
 iwlagn-$(CONFIG_IWLWIFI_DEBUGFS) += iwl-agn-debugfs.o
 
 iwlagn-$(CONFIG_IWL4965) += iwl-4965.o
+iwlagn-$(CONFIG_IWL5000) += iwl-agn-rxon.o iwl-agn-hcmd.o iwl-agn-ict.o
 iwlagn-$(CONFIG_IWL5000) += iwl-5000.o
 iwlagn-$(CONFIG_IWL5000) += iwl-6000.o
 iwlagn-$(CONFIG_IWL5000) += iwl-1000.o
diff --git a/drivers/net/wireless/iwlwifi/iwl-1000.c b/drivers/net/wireless/iwlwifi/iwl-1000.c
index db540910b110..ba78bc8a259f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-1000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-1000.c
@@ -147,7 +147,11 @@ static int iwl1000_hw_set_hw_params(struct iwl_priv *priv)
         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 
         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
-        priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
+        if (priv->cfg->rx_with_siso_diversity)
+                priv->hw_params.rx_chains_num = 1;
+        else
+                priv->hw_params.rx_chains_num =
+                        num_of_ant(priv->cfg->valid_rx_ant);
         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 
@@ -211,14 +215,16 @@ static struct iwl_lib_ops iwl1000_lib = {
                 .calib_version  = iwlagn_eeprom_calib_version,
                 .query_addr = iwlagn_eeprom_query_addr,
         },
-        .post_associate = iwl_post_associate,
-        .isr = iwl_isr_ict,
-        .config_ap = iwl_config_ap,
+        .isr_ops = {
+                .isr = iwl_isr_ict,
+                .free = iwl_free_isr_ict,
+                .alloc = iwl_alloc_isr_ict,
+                .reset = iwl_reset_ict,
+                .disable = iwl_disable_ict,
+        },
         .temp_ops = {
                 .temperature = iwlagn_temperature,
          },
-        .manage_ibss_station = iwlagn_manage_ibss_station,
-        .update_bcast_stations = iwl_update_bcast_stations,
         .debugfs_ops = {
                 .rx_stats_read = iwl_ucode_rx_stats_read,
                 .tx_stats_read = iwl_ucode_tx_stats_read,
@@ -226,7 +232,6 @@ static struct iwl_lib_ops iwl1000_lib = {
                 .bt_stats_read = iwl_ucode_bt_stats_read,
                 .reply_tx_error = iwl_reply_tx_error_read,
         },
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
         .check_plcp_health = iwl_good_plcp_health,
         .check_ack_health = iwl_good_ack_health,
         .txfifo_flush = iwlagn_txfifo_flush,
@@ -243,6 +248,7 @@ static const struct iwl_ops iwl1000_ops = {
         .hcmd = &iwlagn_hcmd,
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static struct iwl_base_params iwl1000_base_params = {
@@ -259,7 +265,7 @@ static struct iwl_base_params iwl1000_base_params = {
         .support_ct_kill_exit = true,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF,
         .chain_noise_scale = 1000,
-        .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
+        .wd_timeout = IWL_DEF_WD_TIMEOUT,
         .max_event_log_size = 128,
         .ucode_tracing = true,
         .sensitivity_calib_by_driver = true,
@@ -270,66 +276,49 @@ static struct iwl_ht_params iwl1000_ht_params = {
         .use_rts_for_aggregation = true, /* use rts/cts protection */
 };
 
+#define IWL_DEVICE_1000                                         \
+        .fw_name_pre = IWL1000_FW_PRE,                          \
+        .ucode_api_max = IWL1000_UCODE_API_MAX,                 \
+        .ucode_api_min = IWL1000_UCODE_API_MIN,                 \
+        .eeprom_ver = EEPROM_1000_EEPROM_VERSION,               \
+        .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,       \
+        .ops = &iwl1000_ops,                                    \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl1000_base_params,                    \
+        .led_mode = IWL_LED_BLINK
+
 struct iwl_cfg iwl1000_bgn_cfg = {
         .name = "Intel(R) Centrino(R) Wireless-N 1000 BGN",
-        .fw_name_pre = IWL1000_FW_PRE,
-        .ucode_api_max = IWL1000_UCODE_API_MAX,
-        .ucode_api_min = IWL1000_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_1000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
-        .ops = &iwl1000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl1000_base_params,
+        IWL_DEVICE_1000,
         .ht_params = &iwl1000_ht_params,
 };
 
 struct iwl_cfg iwl1000_bg_cfg = {
         .name = "Intel(R) Centrino(R) Wireless-N 1000 BG",
-        .fw_name_pre = IWL1000_FW_PRE,
-        .ucode_api_max = IWL1000_UCODE_API_MAX,
-        .ucode_api_min = IWL1000_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_1000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
-        .ops = &iwl1000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl1000_base_params,
+        IWL_DEVICE_1000,
 };
 
+#define IWL_DEVICE_100                                          \
+        .fw_name_pre = IWL100_FW_PRE,                           \
+        .ucode_api_max = IWL100_UCODE_API_MAX,                  \
+        .ucode_api_min = IWL100_UCODE_API_MIN,                  \
+        .eeprom_ver = EEPROM_1000_EEPROM_VERSION,               \
+        .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,       \
+        .ops = &iwl1000_ops,                                    \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl1000_base_params,                    \
+        .led_mode = IWL_LED_RF_STATE,                           \
+        .rx_with_siso_diversity = true
+
 struct iwl_cfg iwl100_bgn_cfg = {
-        .name = "Intel(R) 100 Series 1x1 BGN",
-        .fw_name_pre = IWL100_FW_PRE,
-        .ucode_api_max = IWL100_UCODE_API_MAX,
-        .ucode_api_min = IWL100_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_A,
-        .eeprom_ver = EEPROM_1000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
-        .ops = &iwl1000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl1000_base_params,
+        .name = "Intel(R) Centrino(R) Wireless-N 100 BGN",
+        IWL_DEVICE_100,
         .ht_params = &iwl1000_ht_params,
 };
 
 struct iwl_cfg iwl100_bg_cfg = {
-        .name = "Intel(R) 100 Series 1x1 BG",
-        .fw_name_pre = IWL100_FW_PRE,
-        .ucode_api_max = IWL100_UCODE_API_MAX,
-        .ucode_api_min = IWL100_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_A,
-        .eeprom_ver = EEPROM_1000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_1000_TX_POWER_VERSION,
-        .ops = &iwl1000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl1000_base_params,
+        .name = "Intel(R) Centrino(R) Wireless-N 100 BG",
+        IWL_DEVICE_100,
 };
 
 MODULE_FIRMWARE(IWL1000_MODULE_FIRMWARE(IWL1000_UCODE_API_MAX));
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 176e52577673..a9b852be4509 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -51,6 +51,7 @@
 #include "iwl-led.h"
 #include "iwl-3945-led.h"
 #include "iwl-3945-debugfs.h"
+#include "iwl-legacy.h"
 
 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
@@ -115,7 +116,7 @@ void iwl3945_disable_events(struct iwl_priv *priv)
         u32 base;               /* SRAM address of event log header */
         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
         u32 array_size;         /* # of u32 entries in array */
-        u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
+        static const u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
                 0x00000000,     /*   31 -    0  Event id numbers */
                 0x00000000,     /*   63 -   32 */
                 0x00000000,     /*   95 -   64 */
@@ -296,7 +297,7 @@ static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
                         (txq_id != IWL39_CMD_QUEUE_NUM) &&
                         priv->mac80211_registered)
-                iwl_wake_queue(priv, txq_id);
+                iwl_wake_queue(priv, txq);
 }
 
 /**
@@ -324,6 +325,7 @@ static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
                 return;
         }
 
+        txq->time_stamp = jiffies;
         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
         ieee80211_tx_info_clear_status(info);
 
@@ -1451,6 +1453,10 @@ static int iwl3945_send_tx_power(struct iwl_priv *priv)
         };
         u16 chan;
 
+        if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
+                      "TX Power requested while scanning!\n"))
+                return -EAGAIN;
+
         chan = le16_to_cpu(priv->contexts[IWL_RXON_CTX_BSS].active.channel);
 
         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
@@ -1779,6 +1785,9 @@ int iwl3945_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
         int rc = 0;
         bool new_assoc = !!(staging_rxon->filter_flags & RXON_FILTER_ASSOC_MSK);
 
+        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
+                return -EINVAL;
+
         if (!iwl_is_alive(priv))
                 return -1;
 
@@ -2722,11 +2731,9 @@ static struct iwl_lib_ops iwl3945_lib = {
         },
         .send_tx_power  = iwl3945_send_tx_power,
         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
-        .post_associate = iwl3945_post_associate,
-        .isr = iwl_isr_legacy,
-        .config_ap = iwl3945_config_ap,
-        .manage_ibss_station = iwl3945_manage_ibss_station,
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
+        .isr_ops = {
+                .isr = iwl_isr_legacy,
+        },
         .check_plcp_health = iwl3945_good_plcp_health,
 
         .debugfs_ops = {
@@ -2736,10 +2743,16 @@ static struct iwl_lib_ops iwl3945_lib = {
         },
 };
 
+static const struct iwl_legacy_ops iwl3945_legacy_ops = {
+        .post_associate = iwl3945_post_associate,
+        .config_ap = iwl3945_config_ap,
+        .manage_ibss_station = iwl3945_manage_ibss_station,
+};
+
 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
         .get_hcmd_size = iwl3945_get_hcmd_size,
         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
-        .tx_cmd_protection = iwlcore_tx_cmd_protection,
+        .tx_cmd_protection = iwl_legacy_tx_cmd_protection,
         .request_scan = iwl3945_request_scan,
         .post_scan = iwl3945_post_scan,
 };
@@ -2749,6 +2762,8 @@ static const struct iwl_ops iwl3945_ops = {
         .hcmd = &iwl3945_hcmd,
         .utils = &iwl3945_hcmd_utils,
         .led = &iwl3945_led_ops,
+        .legacy = &iwl3945_legacy_ops,
+        .ieee80211_ops = &iwl3945_hw_ops,
 };
 
 static struct iwl_base_params iwl3945_base_params = {
@@ -2761,7 +2776,7 @@ static struct iwl_base_params iwl3945_base_params = {
         .led_compensation = 64,
         .broken_powersave = true,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
-        .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
+        .wd_timeout = IWL_DEF_WD_TIMEOUT,
         .max_event_log_size = 512,
         .tx_power_by_driver = true,
 };
@@ -2776,6 +2791,7 @@ static struct iwl_cfg iwl3945_bg_cfg = {
         .ops = &iwl3945_ops,
         .mod_params = &iwl3945_mod_params,
         .base_params = &iwl3945_base_params,
+        .led_mode = IWL_LED_BLINK,
 };
 
 static struct iwl_cfg iwl3945_abg_cfg = {
@@ -2788,6 +2804,7 @@ static struct iwl_cfg iwl3945_abg_cfg = {
         .ops = &iwl3945_ops,
         .mod_params = &iwl3945_mod_params,
         .base_params = &iwl3945_base_params,
+        .led_mode = IWL_LED_BLINK,
 };
 
 DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.h b/drivers/net/wireless/iwlwifi/iwl-3945.h
index 09391f0ee61f..3eef1eb74a78 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.h
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.h
@@ -264,10 +264,8 @@ void iwl3945_reply_statistics(struct iwl_priv *priv,
                               struct iwl_rx_mem_buffer *rxb);
 extern void iwl3945_disable_events(struct iwl_priv *priv);
 extern int iwl4965_get_temperature(const struct iwl_priv *priv);
-extern void iwl3945_post_associate(struct iwl_priv *priv,
-                                   struct ieee80211_vif *vif);
-extern void iwl3945_config_ap(struct iwl_priv *priv,
-                              struct ieee80211_vif *vif);
+extern void iwl3945_post_associate(struct iwl_priv *priv);
+extern void iwl3945_config_ap(struct iwl_priv *priv);
 
 extern int iwl3945_commit_rxon(struct iwl_priv *priv,
                                struct iwl_rxon_context *ctx);
@@ -282,6 +280,8 @@ extern int iwl3945_commit_rxon(struct iwl_priv *priv,
  */
 extern u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *bssid);
 
+extern struct ieee80211_ops iwl3945_hw_ops;
+
 /*
  * Forward declare iwl-3945.c functions for iwl-base.c
  */
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index b207e3e9299f..3f1e5f1bf847 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -48,6 +48,7 @@
 #include "iwl-agn-led.h"
 #include "iwl-agn.h"
 #include "iwl-agn-debugfs.h"
+#include "iwl-legacy.h"
 
 static int iwl4965_send_tx_power(struct iwl_priv *priv);
 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
@@ -1377,13 +1378,9 @@ static int iwl4965_send_tx_power(struct iwl_priv *priv)
         u8 ctrl_chan_high = 0;
         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
 
-        if (test_bit(STATUS_SCANNING, &priv->status)) {
-                /* If this gets hit a lot, switch it to a BUG() and catch
-                 * the stack trace to find out who is calling this during
-                 * a scan. */
-                IWL_WARN(priv, "TX Power requested while scanning!\n");
+        if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
+                      "TX Power requested while scanning!\n"))
                 return -EAGAIN;
-        }
 
         band = priv->band == IEEE80211_BAND_2GHZ;
 
@@ -1447,6 +1444,142 @@ static int iwl4965_send_rxon_assoc(struct iwl_priv *priv,
         return ret;
 }
 
+static int iwl4965_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
+{
+        /* cast away the const for active_rxon in this function */
+        struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
+        int ret;
+        bool new_assoc =
+                !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
+
+        if (!iwl_is_alive(priv))
+                return -EBUSY;
+
+        if (!ctx->is_active)
+                return 0;
+
+        /* always get timestamp with Rx frame */
+        ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
+
+        ret = iwl_check_rxon_cmd(priv, ctx);
+        if (ret) {
+                IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
+                return -EINVAL;
+        }
+
+        /*
+         * receive commit_rxon request
+         * abort any previous channel switch if still in process
+         */
+        if (priv->switch_rxon.switch_in_progress &&
+            (priv->switch_rxon.channel != ctx->staging.channel)) {
+                IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
+                      le16_to_cpu(priv->switch_rxon.channel));
+                iwl_chswitch_done(priv, false);
+        }
+
+        /* If we don't need to send a full RXON, we can use
+         * iwl_rxon_assoc_cmd which is used to reconfigure filter
+         * and other flags for the current radio configuration. */
+        if (!iwl_full_rxon_required(priv, ctx)) {
+                ret = iwl_send_rxon_assoc(priv, ctx);
+                if (ret) {
+                        IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
+                        return ret;
+                }
+
+                memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
+                iwl_print_rx_config_cmd(priv, ctx);
+                return 0;
+        }
+
+        /* If we are currently associated and the new config requires
+         * an RXON_ASSOC and the new config wants the associated mask enabled,
+         * we must clear the associated from the active configuration
+         * before we apply the new config */
+        if (iwl_is_associated_ctx(ctx) && new_assoc) {
+                IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
+                active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+
+                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
+                                       sizeof(struct iwl_rxon_cmd),
+                                       active_rxon);
+
+                /* If the mask clearing failed then we set
+                 * active_rxon back to what it was previously */
+                if (ret) {
+                        active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
+                        IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
+                        return ret;
+                }
+                iwl_clear_ucode_stations(priv, ctx);
+                iwl_restore_stations(priv, ctx);
+                ret = iwl_restore_default_wep_keys(priv, ctx);
+                if (ret) {
+                        IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
+                        return ret;
+                }
+        }
+
+        IWL_DEBUG_INFO(priv, "Sending RXON\n"
+                       "* with%s RXON_FILTER_ASSOC_MSK\n"
+                       "* channel = %d\n"
+                       "* bssid = %pM\n",
+                       (new_assoc ? "" : "out"),
+                       le16_to_cpu(ctx->staging.channel),
+                       ctx->staging.bssid_addr);
+
+        iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
+
+        /* Apply the new configuration
+         * RXON unassoc clears the station table in uCode so restoration of
+         * stations is needed after it (the RXON command) completes
+         */
+        if (!new_assoc) {
+                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
+                              sizeof(struct iwl_rxon_cmd), &ctx->staging);
+                if (ret) {
+                        IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
+                        return ret;
+                }
+                IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
+                memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
+                iwl_clear_ucode_stations(priv, ctx);
+                iwl_restore_stations(priv, ctx);
+                ret = iwl_restore_default_wep_keys(priv, ctx);
+                if (ret) {
+                        IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
+                        return ret;
+                }
+        }
+        if (new_assoc) {
+                priv->start_calib = 0;
+                /* Apply the new configuration
+                 * RXON assoc doesn't clear the station table in uCode,
+                 */
+                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
+                              sizeof(struct iwl_rxon_cmd), &ctx->staging);
+                if (ret) {
+                        IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
+                        return ret;
+                }
+                memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
+        }
+        iwl_print_rx_config_cmd(priv, ctx);
+
+        iwl_init_sensitivity(priv);
+
+        /* If we issue a new RXON command which required a tune then we must
+         * send a new TXPOWER command or we won't be able to Tx any frames */
+        ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
+        if (ret) {
+                IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
 static int iwl4965_hw_channel_switch(struct iwl_priv *priv,
                                      struct ieee80211_channel_switch *ch_switch)
 {
@@ -1554,22 +1687,6 @@ static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 }
 
 /**
- * sign_extend - Sign extend a value using specified bit as sign-bit
- *
- * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
- * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
- *
- * @param oper value to sign extend
- * @param index 0 based bit index (0<=index<32) to sign bit
- */
-static s32 sign_extend(u32 oper, int index)
-{
-        u8 shift = 31 - index;
-
-        return (s32)(oper << shift) >> shift;
-}
-
-/**
  * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
  * @statistics: Provides the temperature reading from the uCode
  *
@@ -1606,9 +1723,9 @@ static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
          * "initialize" ALIVE response.
          */
         if (!test_bit(STATUS_TEMPERATURE, &priv->status))
-                vt = sign_extend(R4, 23);
+                vt = sign_extend32(R4, 23);
         else
-                vt = sign_extend(le32_to_cpu(priv->_agn.statistics.
+                vt = sign_extend32(le32_to_cpu(priv->_agn.statistics.
                                  general.common.temperature), 23);
 
         IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
@@ -2081,6 +2198,7 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
                 return;
         }
 
+        txq->time_stamp = jiffies;
         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
         memset(&info->status, 0, sizeof(info->status));
 
@@ -2121,12 +2239,8 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
 
                         if (priv->mac80211_registered &&
                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
-                            (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
-                                if (agg->state == IWL_AGG_OFF)
-                                        iwl_wake_queue(priv, txq_id);
-                                else
-                                        iwl_wake_queue(priv, txq->swq_id);
-                        }
+                            (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
+                                iwl_wake_queue(priv, txq);
                 }
         } else {
                 info->status.rates[0].count = tx_resp->failure_frame + 1;
@@ -2150,7 +2264,7 @@ static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
 
                 if (priv->mac80211_registered &&
                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
-                        iwl_wake_queue(priv, txq_id);
+                        iwl_wake_queue(priv, txq);
         }
         if (qc && likely(sta_id != IWL_INVALID_STATION))
                 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
@@ -2216,7 +2330,7 @@ static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
 
 static struct iwl_hcmd_ops iwl4965_hcmd = {
         .rxon_assoc = iwl4965_send_rxon_assoc,
-        .commit_rxon = iwlagn_commit_rxon,
+        .commit_rxon = iwl4965_commit_rxon,
         .set_rxon_chain = iwlagn_set_rxon_chain,
         .send_bt_config = iwl_send_bt_config,
 };
@@ -2233,12 +2347,155 @@ static void iwl4965_post_scan(struct iwl_priv *priv)
                 iwlcore_commit_rxon(priv, ctx);
 }
 
+static void iwl4965_post_associate(struct iwl_priv *priv)
+{
+        struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
+        struct ieee80211_vif *vif = ctx->vif;
+        struct ieee80211_conf *conf = NULL;
+        int ret = 0;
+
+        if (!vif || !priv->is_open)
+                return;
+
+        if (vif->type == NL80211_IFTYPE_AP) {
+                IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
+                return;
+        }
+
+        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
+                return;
+
+        iwl_scan_cancel_timeout(priv, 200);
+
+        conf = ieee80211_get_hw_conf(priv->hw);
+
+        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+        iwlcore_commit_rxon(priv, ctx);
+
+        ret = iwl_send_rxon_timing(priv, ctx);
+        if (ret)
+                IWL_WARN(priv, "RXON timing - "
+                            "Attempting to continue.\n");
+
+        ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
+
+        iwl_set_rxon_ht(priv, &priv->current_ht_config);
+
+        if (priv->cfg->ops->hcmd->set_rxon_chain)
+                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
+
+        ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
+
+        IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
+                        vif->bss_conf.aid, vif->bss_conf.beacon_int);
+
+        if (vif->bss_conf.use_short_preamble)
+                ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
+        else
+                ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
+
+        if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
+                if (vif->bss_conf.use_short_slot)
+                        ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
+                else
+                        ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
+        }
+
+        iwlcore_commit_rxon(priv, ctx);
+
+        IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
+                        vif->bss_conf.aid, ctx->active.bssid_addr);
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_STATION:
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                iwlagn_send_beacon_cmd(priv);
+                break;
+        default:
+                IWL_ERR(priv, "%s Should not be called in %d mode\n",
+                          __func__, vif->type);
+                break;
+        }
+
+        /* the chain noise calibration will enabled PM upon completion
+         * If chain noise has already been run, then we need to enable
+         * power management here */
+        if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
+                iwl_power_update_mode(priv, false);
+
+        /* Enable Rx differential gain and sensitivity calibrations */
+        iwl_chain_noise_reset(priv);
+        priv->start_calib = 1;
+}
+
+static void iwl4965_config_ap(struct iwl_priv *priv)
+{
+        struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
+        struct ieee80211_vif *vif = ctx->vif;
+        int ret = 0;
+
+        lockdep_assert_held(&priv->mutex);
+
+        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
+                return;
+
+        /* The following should be done only at AP bring up */
+        if (!iwl_is_associated_ctx(ctx)) {
+
+                /* RXON - unassoc (to set timing command) */
+                ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+                iwlcore_commit_rxon(priv, ctx);
+
+                /* RXON Timing */
+                ret = iwl_send_rxon_timing(priv, ctx);
+                if (ret)
+                        IWL_WARN(priv, "RXON timing failed - "
+                                        "Attempting to continue.\n");
+
+                /* AP has all antennas */
+                priv->chain_noise_data.active_chains =
+                        priv->hw_params.valid_rx_ant;
+                iwl_set_rxon_ht(priv, &priv->current_ht_config);
+                if (priv->cfg->ops->hcmd->set_rxon_chain)
+                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
+
+                ctx->staging.assoc_id = 0;
+
+                if (vif->bss_conf.use_short_preamble)
+                        ctx->staging.flags |=
+                                RXON_FLG_SHORT_PREAMBLE_MSK;
+                else
+                        ctx->staging.flags &=
+                                ~RXON_FLG_SHORT_PREAMBLE_MSK;
+
+                if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
+                        if (vif->bss_conf.use_short_slot)
+                                ctx->staging.flags |=
+                                        RXON_FLG_SHORT_SLOT_MSK;
+                        else
+                                ctx->staging.flags &=
+                                        ~RXON_FLG_SHORT_SLOT_MSK;
+                }
+                /* need to send beacon cmd before committing assoc RXON! */
+                iwlagn_send_beacon_cmd(priv);
+                /* restore RXON assoc */
+                ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
+                iwlcore_commit_rxon(priv, ctx);
+        }
+        iwlagn_send_beacon_cmd(priv);
+
+        /* FIXME - we need to add code here to detect a totally new
+         * configuration, reset the AP, unassoc, rxon timing, assoc,
+         * clear sta table, add BCAST sta... */
+}
+
 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
         .get_hcmd_size = iwl4965_get_hcmd_size,
         .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
         .chain_noise_reset = iwl4965_chain_noise_reset,
         .gain_computation = iwl4965_gain_computation,
-        .tx_cmd_protection = iwlcore_tx_cmd_protection,
+        .tx_cmd_protection = iwl_legacy_tx_cmd_protection,
         .calc_rssi = iwl4965_calc_rssi,
         .request_scan = iwlagn_request_scan,
         .post_scan = iwl4965_post_scan,
@@ -2285,14 +2542,12 @@ static struct iwl_lib_ops iwl4965_lib = {
         },
         .send_tx_power  = iwl4965_send_tx_power,
         .update_chain_flags = iwl_update_chain_flags,
-        .post_associate = iwl_post_associate,
-        .config_ap = iwl_config_ap,
-        .isr = iwl_isr_legacy,
+        .isr_ops = {
+                .isr = iwl_isr_legacy,
+        },
         .temp_ops = {
                 .temperature = iwl4965_temperature_calib,
         },
-        .manage_ibss_station = iwlagn_manage_ibss_station,
-        .update_bcast_stations = iwl_update_bcast_stations,
         .debugfs_ops = {
                 .rx_stats_read = iwl_ucode_rx_stats_read,
                 .tx_stats_read = iwl_ucode_tx_stats_read,
@@ -2300,15 +2555,46 @@ static struct iwl_lib_ops iwl4965_lib = {
                 .bt_stats_read = iwl_ucode_bt_stats_read,
                 .reply_tx_error = iwl_reply_tx_error_read,
         },
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
         .check_plcp_health = iwl_good_plcp_health,
 };
 
+static const struct iwl_legacy_ops iwl4965_legacy_ops = {
+        .post_associate = iwl4965_post_associate,
+        .config_ap = iwl4965_config_ap,
+        .manage_ibss_station = iwlagn_manage_ibss_station,
+        .update_bcast_stations = iwl_update_bcast_stations,
+};
+
+struct ieee80211_ops iwl4965_hw_ops = {
+        .tx = iwlagn_mac_tx,
+        .start = iwlagn_mac_start,
+        .stop = iwlagn_mac_stop,
+        .add_interface = iwl_mac_add_interface,
+        .remove_interface = iwl_mac_remove_interface,
+        .change_interface = iwl_mac_change_interface,
+        .config = iwl_legacy_mac_config,
+        .configure_filter = iwlagn_configure_filter,
+        .set_key = iwlagn_mac_set_key,
+        .update_tkip_key = iwlagn_mac_update_tkip_key,
+        .conf_tx = iwl_mac_conf_tx,
+        .reset_tsf = iwl_legacy_mac_reset_tsf,
+        .bss_info_changed = iwl_legacy_mac_bss_info_changed,
+        .ampdu_action = iwlagn_mac_ampdu_action,
+        .hw_scan = iwl_mac_hw_scan,
+        .sta_add = iwlagn_mac_sta_add,
+        .sta_remove = iwl_mac_sta_remove,
+        .channel_switch = iwlagn_mac_channel_switch,
+        .flush = iwlagn_mac_flush,
+        .tx_last_beacon = iwl_mac_tx_last_beacon,
+};
+
 static const struct iwl_ops iwl4965_ops = {
         .lib = &iwl4965_lib,
         .hcmd = &iwl4965_hcmd,
         .utils = &iwl4965_hcmd_utils,
         .led = &iwlagn_led_ops,
+        .legacy = &iwl4965_legacy_ops,
+        .ieee80211_ops = &iwl4965_hw_ops,
 };
 
 static struct iwl_base_params iwl4965_base_params = {
@@ -2323,13 +2609,14 @@ static struct iwl_base_params iwl4965_base_params = {
         .led_compensation = 61,
         .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
-        .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
+        .wd_timeout = IWL_DEF_WD_TIMEOUT,
         .temperature_kelvin = true,
         .max_event_log_size = 512,
         .tx_power_by_driver = true,
         .ucode_tracing = true,
         .sensitivity_calib_by_driver = true,
         .chain_noise_calib_by_driver = true,
+        .no_agg_framecnt_info = true,
 };
 
 struct iwl_cfg iwl4965_agn_cfg = {
@@ -2337,7 +2624,6 @@ struct iwl_cfg iwl4965_agn_cfg = {
         .fw_name_pre = IWL4965_FW_PRE,
         .ucode_api_max = IWL4965_UCODE_API_MAX,
         .ucode_api_min = IWL4965_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
         .valid_tx_ant = ANT_AB,
         .valid_rx_ant = ANT_ABC,
         .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
@@ -2345,6 +2631,7 @@ struct iwl_cfg iwl4965_agn_cfg = {
         .ops = &iwl4965_ops,
         .mod_params = &iwlagn_mod_params,
         .base_params = &iwl4965_base_params,
+        .led_mode = IWL_LED_BLINK,
         /*
          * Force use of chains B and C for scan RX on 5 GHz band
          * because the device has off-channel reception on chain A.
diff --git a/drivers/net/wireless/iwlwifi/iwl-5000.c b/drivers/net/wireless/iwlwifi/iwl-5000.c
index fd9fbc93ea1b..79ab0a6b1386 100644
--- a/drivers/net/wireless/iwlwifi/iwl-5000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-5000.c
@@ -385,14 +385,16 @@ static struct iwl_lib_ops iwl5000_lib = {
                 .calib_version  = iwlagn_eeprom_calib_version,
                 .query_addr = iwlagn_eeprom_query_addr,
         },
-        .post_associate = iwl_post_associate,
-        .isr = iwl_isr_ict,
-        .config_ap = iwl_config_ap,
+        .isr_ops = {
+                .isr = iwl_isr_ict,
+                .free = iwl_free_isr_ict,
+                .alloc = iwl_alloc_isr_ict,
+                .reset = iwl_reset_ict,
+                .disable = iwl_disable_ict,
+        },
         .temp_ops = {
                 .temperature = iwlagn_temperature,
          },
-        .manage_ibss_station = iwlagn_manage_ibss_station,
-        .update_bcast_stations = iwl_update_bcast_stations,
         .debugfs_ops = {
                 .rx_stats_read = iwl_ucode_rx_stats_read,
                 .tx_stats_read = iwl_ucode_tx_stats_read,
@@ -400,7 +402,6 @@ static struct iwl_lib_ops iwl5000_lib = {
                 .bt_stats_read = iwl_ucode_bt_stats_read,
                 .reply_tx_error = iwl_reply_tx_error_read,
         },
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
         .check_plcp_health = iwl_good_plcp_health,
         .check_ack_health = iwl_good_ack_health,
         .txfifo_flush = iwlagn_txfifo_flush,
@@ -453,14 +454,16 @@ static struct iwl_lib_ops iwl5150_lib = {
                 .calib_version  = iwlagn_eeprom_calib_version,
                 .query_addr = iwlagn_eeprom_query_addr,
         },
-        .post_associate = iwl_post_associate,
-        .isr = iwl_isr_ict,
-        .config_ap = iwl_config_ap,
+        .isr_ops = {
+                .isr = iwl_isr_ict,
+                .free = iwl_free_isr_ict,
+                .alloc = iwl_alloc_isr_ict,
+                .reset = iwl_reset_ict,
+                .disable = iwl_disable_ict,
+        },
         .temp_ops = {
                 .temperature = iwl5150_temperature,
          },
-        .manage_ibss_station = iwlagn_manage_ibss_station,
-        .update_bcast_stations = iwl_update_bcast_stations,
         .debugfs_ops = {
                 .rx_stats_read = iwl_ucode_rx_stats_read,
                 .tx_stats_read = iwl_ucode_tx_stats_read,
@@ -468,7 +471,6 @@ static struct iwl_lib_ops iwl5150_lib = {
                 .bt_stats_read = iwl_ucode_bt_stats_read,
                 .reply_tx_error = iwl_reply_tx_error_read,
         },
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
         .check_plcp_health = iwl_good_plcp_health,
         .check_ack_health = iwl_good_ack_health,
         .txfifo_flush = iwlagn_txfifo_flush,
@@ -485,6 +487,7 @@ static const struct iwl_ops iwl5000_ops = {
         .hcmd = &iwlagn_hcmd,
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static const struct iwl_ops iwl5150_ops = {
@@ -492,6 +495,7 @@ static const struct iwl_ops iwl5150_ops = {
         .hcmd = &iwlagn_hcmd,
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static struct iwl_base_params iwl5000_base_params = {
@@ -505,7 +509,7 @@ static struct iwl_base_params iwl5000_base_params = {
         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
         .chain_noise_scale = 1000,
-        .monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
+        .wd_timeout = IWL_LONG_WD_TIMEOUT,
         .max_event_log_size = 512,
         .ucode_tracing = true,
         .sensitivity_calib_by_driver = true,
@@ -516,66 +520,43 @@ static struct iwl_ht_params iwl5000_ht_params = {
         .use_rts_for_aggregation = true, /* use rts/cts protection */
 };
 
+#define IWL_DEVICE_5000                                         \
+        .fw_name_pre = IWL5000_FW_PRE,                          \
+        .ucode_api_max = IWL5000_UCODE_API_MAX,                 \
+        .ucode_api_min = IWL5000_UCODE_API_MIN,                 \
+        .eeprom_ver = EEPROM_5000_EEPROM_VERSION,               \
+        .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,       \
+        .ops = &iwl5000_ops,                                    \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl5000_base_params,                    \
+        .led_mode = IWL_LED_BLINK
+
 struct iwl_cfg iwl5300_agn_cfg = {
         .name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
-        .fw_name_pre = IWL5000_FW_PRE,
-        .ucode_api_max = IWL5000_UCODE_API_MAX,
-        .ucode_api_min = IWL5000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_ABC,
-        .valid_rx_ant = ANT_ABC,
-        .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
-        .ops = &iwl5000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl5000_base_params,
+        IWL_DEVICE_5000,
         .ht_params = &iwl5000_ht_params,
 };
 
 struct iwl_cfg iwl5100_bgn_cfg = {
         .name = "Intel(R) WiFi Link 5100 BGN",
-        .fw_name_pre = IWL5000_FW_PRE,
-        .ucode_api_max = IWL5000_UCODE_API_MAX,
-        .ucode_api_min = IWL5000_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_B,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
-        .ops = &iwl5000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl5000_base_params,
+        IWL_DEVICE_5000,
+        .valid_tx_ant = ANT_B,          /* .cfg overwrite */
+        .valid_rx_ant = ANT_AB,         /* .cfg overwrite */
         .ht_params = &iwl5000_ht_params,
 };
 
 struct iwl_cfg iwl5100_abg_cfg = {
         .name = "Intel(R) WiFi Link 5100 ABG",
-        .fw_name_pre = IWL5000_FW_PRE,
-        .ucode_api_max = IWL5000_UCODE_API_MAX,
-        .ucode_api_min = IWL5000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G,
-        .valid_tx_ant = ANT_B,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
-        .ops = &iwl5000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl5000_base_params,
+        IWL_DEVICE_5000,
+        .valid_tx_ant = ANT_B,          /* .cfg overwrite */
+        .valid_rx_ant = ANT_AB,         /* .cfg overwrite */
 };
 
 struct iwl_cfg iwl5100_agn_cfg = {
         .name = "Intel(R) WiFi Link 5100 AGN",
-        .fw_name_pre = IWL5000_FW_PRE,
-        .ucode_api_max = IWL5000_UCODE_API_MAX,
-        .ucode_api_min = IWL5000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_B,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
-        .ops = &iwl5000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl5000_base_params,
+        IWL_DEVICE_5000,
+        .valid_tx_ant = ANT_B,          /* .cfg overwrite */
+        .valid_rx_ant = ANT_AB,         /* .cfg overwrite */
         .ht_params = &iwl5000_ht_params,
 };
 
@@ -584,48 +565,39 @@ struct iwl_cfg iwl5350_agn_cfg = {
         .fw_name_pre = IWL5000_FW_PRE,
         .ucode_api_max = IWL5000_UCODE_API_MAX,
         .ucode_api_min = IWL5000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_ABC,
-        .valid_rx_ant = ANT_ABC,
         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
         .ops = &iwl5000_ops,
         .mod_params = &iwlagn_mod_params,
         .base_params = &iwl5000_base_params,
         .ht_params = &iwl5000_ht_params,
+        .led_mode = IWL_LED_BLINK,
+        .internal_wimax_coex = true,
 };
 
+#define IWL_DEVICE_5150                                         \
+        .fw_name_pre = IWL5150_FW_PRE,                          \
+        .ucode_api_max = IWL5150_UCODE_API_MAX,                 \
+        .ucode_api_min = IWL5150_UCODE_API_MIN,                 \
+        .eeprom_ver = EEPROM_5050_EEPROM_VERSION,               \
+        .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,       \
+        .ops = &iwl5150_ops,                                    \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl5000_base_params,                    \
+        .need_dc_calib = true,                                  \
+        .led_mode = IWL_LED_BLINK,                              \
+        .internal_wimax_coex = true
+
 struct iwl_cfg iwl5150_agn_cfg = {
         .name = "Intel(R) WiMAX/WiFi Link 5150 AGN",
-        .fw_name_pre = IWL5150_FW_PRE,
-        .ucode_api_max = IWL5150_UCODE_API_MAX,
-        .ucode_api_min = IWL5150_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
-        .ops = &iwl5150_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl5000_base_params,
+        IWL_DEVICE_5150,
         .ht_params = &iwl5000_ht_params,
-        .need_dc_calib = true,
+
 };
 
 struct iwl_cfg iwl5150_abg_cfg = {
         .name = "Intel(R) WiMAX/WiFi Link 5150 ABG",
-        .fw_name_pre = IWL5150_FW_PRE,
-        .ucode_api_max = IWL5150_UCODE_API_MAX,
-        .ucode_api_min = IWL5150_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
-        .ops = &iwl5150_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl5000_base_params,
-        .need_dc_calib = true,
+        IWL_DEVICE_5150,
 };
 
 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
diff --git a/drivers/net/wireless/iwlwifi/iwl-6000.c b/drivers/net/wireless/iwlwifi/iwl-6000.c
index 11e6532fc573..af505bcd7ae0 100644
--- a/drivers/net/wireless/iwlwifi/iwl-6000.c
+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c
@@ -53,13 +53,11 @@
 #define IWL6000_UCODE_API_MAX 4
 #define IWL6050_UCODE_API_MAX 5
 #define IWL6000G2_UCODE_API_MAX 5
-#define IWL130_UCODE_API_MAX 5
 
 /* Lowest firmware API version supported */
 #define IWL6000_UCODE_API_MIN 4
 #define IWL6050_UCODE_API_MIN 4
 #define IWL6000G2_UCODE_API_MIN 4
-#define IWL130_UCODE_API_MIN 5
 
 #define IWL6000_FW_PRE "iwlwifi-6000-"
 #define _IWL6000_MODULE_FIRMWARE(api) IWL6000_FW_PRE #api ".ucode"
@@ -77,10 +75,6 @@
 #define _IWL6000G2B_MODULE_FIRMWARE(api) IWL6000G2B_FW_PRE #api ".ucode"
 #define IWL6000G2B_MODULE_FIRMWARE(api) _IWL6000G2B_MODULE_FIRMWARE(api)
 
-#define IWL130_FW_PRE "iwlwifi-130-"
-#define _IWL130_MODULE_FIRMWARE(api) IWL130_FW_PRE #api ".ucode"
-#define IWL130_MODULE_FIRMWARE(api) _IWL130_MODULE_FIRMWARE(api)
-
 static void iwl6000_set_ct_threshold(struct iwl_priv *priv)
 {
         /* want Celsius */
@@ -188,7 +182,11 @@ static int iwl6000_hw_set_hw_params(struct iwl_priv *priv)
         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 
         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
-        priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
+        if (priv->cfg->rx_with_siso_diversity)
+                priv->hw_params.rx_chains_num = 1;
+        else
+                priv->hw_params.rx_chains_num =
+                        num_of_ant(priv->cfg->valid_rx_ant);
         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 
@@ -328,14 +326,16 @@ static struct iwl_lib_ops iwl6000_lib = {
                 .query_addr = iwlagn_eeprom_query_addr,
                 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
         },
-        .post_associate = iwl_post_associate,
-        .isr = iwl_isr_ict,
-        .config_ap = iwl_config_ap,
+        .isr_ops = {
+                .isr = iwl_isr_ict,
+                .free = iwl_free_isr_ict,
+                .alloc = iwl_alloc_isr_ict,
+                .reset = iwl_reset_ict,
+                .disable = iwl_disable_ict,
+        },
         .temp_ops = {
                 .temperature = iwlagn_temperature,
          },
-        .manage_ibss_station = iwlagn_manage_ibss_station,
-        .update_bcast_stations = iwl_update_bcast_stations,
         .debugfs_ops = {
                 .rx_stats_read = iwl_ucode_rx_stats_read,
                 .tx_stats_read = iwl_ucode_tx_stats_read,
@@ -343,7 +343,6 @@ static struct iwl_lib_ops iwl6000_lib = {
                 .bt_stats_read = iwl_ucode_bt_stats_read,
                 .reply_tx_error = iwl_reply_tx_error_read,
         },
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
         .check_plcp_health = iwl_good_plcp_health,
         .check_ack_health = iwl_good_ack_health,
         .txfifo_flush = iwlagn_txfifo_flush,
@@ -399,14 +398,16 @@ static struct iwl_lib_ops iwl6000g2b_lib = {
                 .query_addr = iwlagn_eeprom_query_addr,
                 .update_enhanced_txpower = iwlcore_eeprom_enhanced_txpower,
         },
-        .post_associate = iwl_post_associate,
-        .isr = iwl_isr_ict,
-        .config_ap = iwl_config_ap,
+        .isr_ops = {
+                .isr = iwl_isr_ict,
+                .free = iwl_free_isr_ict,
+                .alloc = iwl_alloc_isr_ict,
+                .reset = iwl_reset_ict,
+                .disable = iwl_disable_ict,
+        },
         .temp_ops = {
                 .temperature = iwlagn_temperature,
          },
-        .manage_ibss_station = iwlagn_manage_ibss_station,
-        .update_bcast_stations = iwl_update_bcast_stations,
         .debugfs_ops = {
                 .rx_stats_read = iwl_ucode_rx_stats_read,
                 .tx_stats_read = iwl_ucode_tx_stats_read,
@@ -414,7 +415,6 @@ static struct iwl_lib_ops iwl6000g2b_lib = {
                 .bt_stats_read = iwl_ucode_bt_stats_read,
                 .reply_tx_error = iwl_reply_tx_error_read,
         },
-        .recover_from_tx_stall = iwl_bg_monitor_recover,
         .check_plcp_health = iwl_good_plcp_health,
         .check_ack_health = iwl_good_ack_health,
         .txfifo_flush = iwlagn_txfifo_flush,
@@ -439,6 +439,7 @@ static const struct iwl_ops iwl6000_ops = {
         .hcmd = &iwlagn_hcmd,
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static const struct iwl_ops iwl6050_ops = {
@@ -447,6 +448,7 @@ static const struct iwl_ops iwl6050_ops = {
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
         .nic = &iwl6050_nic_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static const struct iwl_ops iwl6050g2_ops = {
@@ -455,6 +457,7 @@ static const struct iwl_ops iwl6050g2_ops = {
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
         .nic = &iwl6050g2_nic_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static const struct iwl_ops iwl6000g2b_ops = {
@@ -462,6 +465,7 @@ static const struct iwl_ops iwl6000g2b_ops = {
         .hcmd = &iwlagn_bt_hcmd,
         .utils = &iwlagn_hcmd_utils,
         .led = &iwlagn_led_ops,
+        .ieee80211_ops = &iwlagn_hw_ops,
 };
 
 static struct iwl_base_params iwl6000_base_params = {
@@ -480,11 +484,12 @@ static struct iwl_base_params iwl6000_base_params = {
         .support_ct_kill_exit = true,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
         .chain_noise_scale = 1000,
-        .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
+        .wd_timeout = IWL_DEF_WD_TIMEOUT,
         .max_event_log_size = 512,
         .ucode_tracing = true,
         .sensitivity_calib_by_driver = true,
         .chain_noise_calib_by_driver = true,
+        .shadow_reg_enable = true,
 };
 
 static struct iwl_base_params iwl6050_base_params = {
@@ -503,13 +508,14 @@ static struct iwl_base_params iwl6050_base_params = {
         .support_ct_kill_exit = true,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
         .chain_noise_scale = 1500,
-        .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
+        .wd_timeout = IWL_DEF_WD_TIMEOUT,
         .max_event_log_size = 1024,
         .ucode_tracing = true,
         .sensitivity_calib_by_driver = true,
         .chain_noise_calib_by_driver = true,
+        .shadow_reg_enable = true,
 };
-static struct iwl_base_params iwl6000_coex_base_params = {
+static struct iwl_base_params iwl6000_g2_base_params = {
         .eeprom_size = OTP_LOW_IMAGE_SIZE,
         .num_of_queues = IWLAGN_NUM_QUEUES,
         .num_of_ampdu_queues = IWLAGN_NUM_AMPDU_QUEUES,
@@ -518,18 +524,19 @@ static struct iwl_base_params iwl6000_coex_base_params = {
         .use_bsm = false,
         .max_ll_items = OTP_MAX_LL_ITEMS_6x00,
         .shadow_ram_support = true,
-        .led_compensation = 51,
+        .led_compensation = 57,
         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
         .supports_idle = true,
         .adv_thermal_throttle = true,
         .support_ct_kill_exit = true,
         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
         .chain_noise_scale = 1000,
-        .monitor_recover_period = IWL_LONG_MONITORING_PERIOD,
+        .wd_timeout = IWL_LONG_WD_TIMEOUT,
         .max_event_log_size = 512,
         .ucode_tracing = true,
         .sensitivity_calib_by_driver = true,
         .chain_noise_calib_by_driver = true,
+        .shadow_reg_enable = true,
 };
 
 static struct iwl_ht_params iwl6000_ht_params = {
@@ -541,262 +548,164 @@ static struct iwl_bt_params iwl6000_bt_params = {
         .bt_statistics = true,
         /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
         .advanced_bt_coexist = true,
+        .agg_time_limit = BT_AGG_THRESHOLD_DEF,
         .bt_init_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_NONE,
         .bt_prio_boost = IWLAGN_BT_PRIO_BOOST_DEFAULT,
+        .bt_sco_disable = true,
+};
+
+#define IWL_DEVICE_6005                                         \
+        .fw_name_pre = IWL6000G2A_FW_PRE,                       \
+        .ucode_api_max = IWL6000G2_UCODE_API_MAX,               \
+        .ucode_api_min = IWL6000G2_UCODE_API_MIN,               \
+        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,             \
+        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,     \
+        .ops = &iwl6000_ops,                                    \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl6000_g2_base_params,                 \
+        .need_dc_calib = true,                                  \
+        .need_temp_offset_calib = true,                         \
+        .led_mode = IWL_LED_RF_STATE
+
+struct iwl_cfg iwl6005_2agn_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6205 AGN",
+        IWL_DEVICE_6005,
+        .ht_params = &iwl6000_ht_params,
 };
 
-struct iwl_cfg iwl6000g2a_2agn_cfg = {
-        .name = "6000 Series 2x2 AGN Gen2a",
-        .fw_name_pre = IWL6000G2A_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_base_params,
+struct iwl_cfg iwl6005_2abg_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6205 ABG",
+        IWL_DEVICE_6005,
+};
+
+struct iwl_cfg iwl6005_2bg_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6205 BG",
+        IWL_DEVICE_6005,
+};
+
+#define IWL_DEVICE_6030                                         \
+        .fw_name_pre = IWL6000G2B_FW_PRE,                       \
+        .ucode_api_max = IWL6000G2_UCODE_API_MAX,               \
+        .ucode_api_min = IWL6000G2_UCODE_API_MIN,               \
+        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,             \
+        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,     \
+        .ops = &iwl6000g2b_ops,                                 \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl6000_g2_base_params,                 \
+        .bt_params = &iwl6000_bt_params,                        \
+        .need_dc_calib = true,                                  \
+        .need_temp_offset_calib = true,                         \
+        .led_mode = IWL_LED_RF_STATE,                           \
+        .adv_pm = true                                          \
+
+struct iwl_cfg iwl6030_2agn_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6230 AGN",
+        IWL_DEVICE_6030,
         .ht_params = &iwl6000_ht_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-};
-
-struct iwl_cfg iwl6000g2a_2abg_cfg = {
-        .name = "6000 Series 2x2 ABG Gen2a",
-        .fw_name_pre = IWL6000G2A_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_base_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-};
-
-struct iwl_cfg iwl6000g2a_2bg_cfg = {
-        .name = "6000 Series 2x2 BG Gen2a",
-        .fw_name_pre = IWL6000G2A_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_base_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-};
-
-struct iwl_cfg iwl6000g2b_2agn_cfg = {
-        .name = "6000 Series 2x2 AGN Gen2b",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
+};
+
+struct iwl_cfg iwl6030_2abg_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6230 ABG",
+        IWL_DEVICE_6030,
+};
+
+struct iwl_cfg iwl6030_2bgn_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6230 BGN",
+        IWL_DEVICE_6030,
         .ht_params = &iwl6000_ht_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
-};
-
-struct iwl_cfg iwl6000g2b_2abg_cfg = {
-        .name = "6000 Series 2x2 ABG Gen2b",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
-};
-
-struct iwl_cfg iwl6000g2b_2bgn_cfg = {
-        .name = "6000 Series 2x2 BGN Gen2b",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
+};
+
+struct iwl_cfg iwl6030_2bg_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N 6230 BG",
+        IWL_DEVICE_6030,
+};
+
+struct iwl_cfg iwl1030_bgn_cfg = {
+        .name = "Intel(R) Centrino(R) Wireless-N 1030 BGN",
+        IWL_DEVICE_6030,
         .ht_params = &iwl6000_ht_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
-};
-
-struct iwl_cfg iwl6000g2b_2bg_cfg = {
-        .name = "6000 Series 2x2 BG Gen2b",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
-};
-
-struct iwl_cfg iwl6000g2b_bgn_cfg = {
-        .name = "6000 Series 1x2 BGN Gen2b",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
+};
+
+struct iwl_cfg iwl1030_bg_cfg = {
+        .name = "Intel(R) Centrino(R) Wireless-N 1030 BG",
+        IWL_DEVICE_6030,
+};
+
+struct iwl_cfg iwl130_bgn_cfg = {
+        .name = "Intel(R) Centrino(R) Wireless-N 130 BGN",
+        IWL_DEVICE_6030,
         .ht_params = &iwl6000_ht_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
-};
-
-struct iwl_cfg iwl6000g2b_bg_cfg = {
-        .name = "6000 Series 1x2 BG Gen2b",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL6000G2_UCODE_API_MAX,
-        .ucode_api_min = IWL6000G2_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
-        .need_dc_calib = true,
-        .need_temp_offset_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
+        .rx_with_siso_diversity = true,
+};
+
+struct iwl_cfg iwl130_bg_cfg = {
+        .name = "Intel(R) Centrino(R) Wireless-N 130 BG",
+        IWL_DEVICE_6030,
+        .rx_with_siso_diversity = true,
 };
 
 /*
  * "i": Internal configuration, use internal Power Amplifier
  */
+#define IWL_DEVICE_6000i                                        \
+        .fw_name_pre = IWL6000_FW_PRE,                          \
+        .ucode_api_max = IWL6000_UCODE_API_MAX,                 \
+        .ucode_api_min = IWL6000_UCODE_API_MIN,                 \
+        .valid_tx_ant = ANT_BC,         /* .cfg overwrite */    \
+        .valid_rx_ant = ANT_BC,         /* .cfg overwrite */    \
+        .eeprom_ver = EEPROM_6000_EEPROM_VERSION,               \
+        .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION,       \
+        .ops = &iwl6000_ops,                                    \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl6000_base_params,                    \
+        .pa_type = IWL_PA_INTERNAL,                             \
+        .led_mode = IWL_LED_BLINK
+
 struct iwl_cfg iwl6000i_2agn_cfg = {
         .name = "Intel(R) Centrino(R) Advanced-N 6200 AGN",
-        .fw_name_pre = IWL6000_FW_PRE,
-        .ucode_api_max = IWL6000_UCODE_API_MAX,
-        .ucode_api_min = IWL6000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_BC,
-        .valid_rx_ant = ANT_BC,
-        .eeprom_ver = EEPROM_6000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION,
-        .ops = &iwl6000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_base_params,
+        IWL_DEVICE_6000i,
         .ht_params = &iwl6000_ht_params,
-        .pa_type = IWL_PA_INTERNAL,
 };
 
 struct iwl_cfg iwl6000i_2abg_cfg = {
         .name = "Intel(R) Centrino(R) Advanced-N 6200 ABG",
-        .fw_name_pre = IWL6000_FW_PRE,
-        .ucode_api_max = IWL6000_UCODE_API_MAX,
-        .ucode_api_min = IWL6000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G,
-        .valid_tx_ant = ANT_BC,
-        .valid_rx_ant = ANT_BC,
-        .eeprom_ver = EEPROM_6000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION,
-        .ops = &iwl6000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_base_params,
-        .pa_type = IWL_PA_INTERNAL,
+        IWL_DEVICE_6000i,
 };
 
 struct iwl_cfg iwl6000i_2bg_cfg = {
         .name = "Intel(R) Centrino(R) Advanced-N 6200 BG",
-        .fw_name_pre = IWL6000_FW_PRE,
-        .ucode_api_max = IWL6000_UCODE_API_MAX,
-        .ucode_api_min = IWL6000_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_BC,
-        .valid_rx_ant = ANT_BC,
-        .eeprom_ver = EEPROM_6000_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION,
-        .ops = &iwl6000_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_base_params,
-        .pa_type = IWL_PA_INTERNAL,
-};
+        IWL_DEVICE_6000i,
+};
+
+#define IWL_DEVICE_6050                                         \
+        .fw_name_pre = IWL6050_FW_PRE,                          \
+        .ucode_api_max = IWL6050_UCODE_API_MAX,                 \
+        .ucode_api_min = IWL6050_UCODE_API_MIN,                 \
+        .ops = &iwl6050_ops,                                    \
+        .eeprom_ver = EEPROM_6050_EEPROM_VERSION,               \
+        .eeprom_calib_ver = EEPROM_6050_TX_POWER_VERSION,       \
+        .mod_params = &iwlagn_mod_params,                       \
+        .base_params = &iwl6050_base_params,                    \
+        .need_dc_calib = true,                                  \
+        .led_mode = IWL_LED_BLINK,                              \
+        .internal_wimax_coex = true
 
 struct iwl_cfg iwl6050_2agn_cfg = {
         .name = "Intel(R) Centrino(R) Advanced-N + WiMAX 6250 AGN",
-        .fw_name_pre = IWL6050_FW_PRE,
-        .ucode_api_max = IWL6050_UCODE_API_MAX,
-        .ucode_api_min = IWL6050_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .ops = &iwl6050_ops,
-        .eeprom_ver = EEPROM_6050_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6050_TX_POWER_VERSION,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6050_base_params,
+        IWL_DEVICE_6050,
         .ht_params = &iwl6000_ht_params,
-        .need_dc_calib = true,
 };
 
-struct iwl_cfg iwl6050g2_bgn_cfg = {
-        .name = "6050 Series 1x2 BGN Gen2",
+struct iwl_cfg iwl6050_2abg_cfg = {
+        .name = "Intel(R) Centrino(R) Advanced-N + WiMAX 6250 ABG",
+        IWL_DEVICE_6050,
+};
+
+struct iwl_cfg iwl6150_bgn_cfg = {
+        .name = "Intel(R) Centrino(R) Wireless-N + WiMAX 6150 BGN",
         .fw_name_pre = IWL6050_FW_PRE,
         .ucode_api_max = IWL6050_UCODE_API_MAX,
         .ucode_api_min = IWL6050_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_AB,
         .eeprom_ver = EEPROM_6050G2_EEPROM_VERSION,
         .eeprom_calib_ver = EEPROM_6050G2_TX_POWER_VERSION,
         .ops = &iwl6050g2_ops,
@@ -804,22 +713,8 @@ struct iwl_cfg iwl6050g2_bgn_cfg = {
         .base_params = &iwl6050_base_params,
         .ht_params = &iwl6000_ht_params,
         .need_dc_calib = true,
-};
-
-struct iwl_cfg iwl6050_2abg_cfg = {
-        .name = "Intel(R) Centrino(R) Advanced-N + WiMAX 6250 ABG",
-        .fw_name_pre = IWL6050_FW_PRE,
-        .ucode_api_max = IWL6050_UCODE_API_MAX,
-        .ucode_api_min = IWL6050_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G,
-        .valid_tx_ant = ANT_AB,
-        .valid_rx_ant = ANT_AB,
-        .eeprom_ver = EEPROM_6050_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6050_TX_POWER_VERSION,
-        .ops = &iwl6050_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6050_base_params,
-        .need_dc_calib = true,
+        .led_mode = IWL_LED_RF_STATE,
+        .internal_wimax_coex = true,
 };
 
 struct iwl_cfg iwl6000_3agn_cfg = {
@@ -827,9 +722,6 @@ struct iwl_cfg iwl6000_3agn_cfg = {
         .fw_name_pre = IWL6000_FW_PRE,
         .ucode_api_max = IWL6000_UCODE_API_MAX,
         .ucode_api_min = IWL6000_UCODE_API_MIN,
-        .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_ABC,
-        .valid_rx_ant = ANT_ABC,
         .eeprom_ver = EEPROM_6000_EEPROM_VERSION,
         .eeprom_calib_ver = EEPROM_6000_TX_POWER_VERSION,
         .ops = &iwl6000_ops,
@@ -837,49 +729,10 @@ struct iwl_cfg iwl6000_3agn_cfg = {
         .base_params = &iwl6000_base_params,
         .ht_params = &iwl6000_ht_params,
         .need_dc_calib = true,
-};
-
-struct iwl_cfg iwl130_bgn_cfg = {
-        .name = "Intel(R) 130 Series 1x1 BGN",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL130_UCODE_API_MAX,
-        .ucode_api_min = IWL130_UCODE_API_MIN,
-        .sku = IWL_SKU_G|IWL_SKU_N,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_A,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
-        .ht_params = &iwl6000_ht_params,
-        .need_dc_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
-};
-
-struct iwl_cfg iwl130_bg_cfg = {
-        .name = "Intel(R) 130 Series 1x2 BG",
-        .fw_name_pre = IWL6000G2B_FW_PRE,
-        .ucode_api_max = IWL130_UCODE_API_MAX,
-        .ucode_api_min = IWL130_UCODE_API_MIN,
-        .sku = IWL_SKU_G,
-        .valid_tx_ant = ANT_A,
-        .valid_rx_ant = ANT_A,
-        .eeprom_ver = EEPROM_6000G2_EEPROM_VERSION,
-        .eeprom_calib_ver = EEPROM_6000G2_TX_POWER_VERSION,
-        .ops = &iwl6000g2b_ops,
-        .mod_params = &iwlagn_mod_params,
-        .base_params = &iwl6000_coex_base_params,
-        .bt_params = &iwl6000_bt_params,
-        .need_dc_calib = true,
-        /* Due to bluetooth, we transmit 2.4 GHz probes only on antenna A */
-        .scan_tx_antennas[IEEE80211_BAND_2GHZ] = ANT_A,
+        .led_mode = IWL_LED_BLINK,
 };
 
 MODULE_FIRMWARE(IWL6000_MODULE_FIRMWARE(IWL6000_UCODE_API_MAX));
 MODULE_FIRMWARE(IWL6050_MODULE_FIRMWARE(IWL6050_UCODE_API_MAX));
 MODULE_FIRMWARE(IWL6000G2A_MODULE_FIRMWARE(IWL6000G2_UCODE_API_MAX));
 MODULE_FIRMWARE(IWL6000G2B_MODULE_FIRMWARE(IWL6000G2_UCODE_API_MAX));
-MODULE_FIRMWARE(IWL130_MODULE_FIRMWARE(IWL130_UCODE_API_MAX));
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-calib.c b/drivers/net/wireless/iwlwifi/iwl-agn-calib.c
index e2019e756936..d16bb5ede014 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-calib.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-calib.c
@@ -732,8 +732,122 @@ static inline u8 find_first_chain(u8 mask)
         return CHAIN_C;
 }
 
+/**
+ * Run disconnected antenna algorithm to find out which antennas are
+ * disconnected.
+ */
+static void iwl_find_disconn_antenna(struct iwl_priv *priv, u32* average_sig,
+                                     struct iwl_chain_noise_data *data)
+{
+        u32 active_chains = 0;
+        u32 max_average_sig;
+        u16 max_average_sig_antenna_i;
+        u8 num_tx_chains;
+        u8 first_chain;
+        u16 i = 0;
+
+        average_sig[0] = data->chain_signal_a /
+                         priv->cfg->base_params->chain_noise_num_beacons;
+        average_sig[1] = data->chain_signal_b /
+                         priv->cfg->base_params->chain_noise_num_beacons;
+        average_sig[2] = data->chain_signal_c /
+                         priv->cfg->base_params->chain_noise_num_beacons;
+
+        if (average_sig[0] >= average_sig[1]) {
+                max_average_sig = average_sig[0];
+                max_average_sig_antenna_i = 0;
+                active_chains = (1 << max_average_sig_antenna_i);
+        } else {
+                max_average_sig = average_sig[1];
+                max_average_sig_antenna_i = 1;
+                active_chains = (1 << max_average_sig_antenna_i);
+        }
+
+        if (average_sig[2] >= max_average_sig) {
+                max_average_sig = average_sig[2];
+                max_average_sig_antenna_i = 2;
+                active_chains = (1 << max_average_sig_antenna_i);
+        }
+
+        IWL_DEBUG_CALIB(priv, "average_sig: a %d b %d c %d\n",
+                     average_sig[0], average_sig[1], average_sig[2]);
+        IWL_DEBUG_CALIB(priv, "max_average_sig = %d, antenna %d\n",
+                     max_average_sig, max_average_sig_antenna_i);
+
+        /* Compare signal strengths for all 3 receivers. */
+        for (i = 0; i < NUM_RX_CHAINS; i++) {
+                if (i != max_average_sig_antenna_i) {
+                        s32 rssi_delta = (max_average_sig - average_sig[i]);
+
+                        /* If signal is very weak, compared with
+                         * strongest, mark it as disconnected. */
+                        if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
+                                data->disconn_array[i] = 1;
+                        else
+                                active_chains |= (1 << i);
+                        IWL_DEBUG_CALIB(priv, "i = %d  rssiDelta = %d  "
+                             "disconn_array[i] = %d\n",
+                             i, rssi_delta, data->disconn_array[i]);
+                }
+        }
+
+        /*
+         * The above algorithm sometimes fails when the ucode
+         * reports 0 for all chains. It's not clear why that
+         * happens to start with, but it is then causing trouble
+         * because this can make us enable more chains than the
+         * hardware really has.
+         *
+         * To be safe, simply mask out any chains that we know
+         * are not on the device.
+         */
+        active_chains &= priv->hw_params.valid_rx_ant;
+
+        num_tx_chains = 0;
+        for (i = 0; i < NUM_RX_CHAINS; i++) {
+                /* loops on all the bits of
+                 * priv->hw_setting.valid_tx_ant */
+                u8 ant_msk = (1 << i);
+                if (!(priv->hw_params.valid_tx_ant & ant_msk))
+                        continue;
+
+                num_tx_chains++;
+                if (data->disconn_array[i] == 0)
+                        /* there is a Tx antenna connected */
+                        break;
+                if (num_tx_chains == priv->hw_params.tx_chains_num &&
+                    data->disconn_array[i]) {
+                        /*
+                         * If all chains are disconnected
+                         * connect the first valid tx chain
+                         */
+                        first_chain =
+                                find_first_chain(priv->cfg->valid_tx_ant);
+                        data->disconn_array[first_chain] = 0;
+                        active_chains |= BIT(first_chain);
+                        IWL_DEBUG_CALIB(priv, "All Tx chains are disconnected \
+                                        W/A - declare %d as connected\n",
+                                        first_chain);
+                        break;
+                }
+        }
+
+        if (active_chains != priv->hw_params.valid_rx_ant &&
+            active_chains != priv->chain_noise_data.active_chains)
+                IWL_DEBUG_CALIB(priv,
+                                "Detected that not all antennas are connected! "
+                                "Connected: %#x, valid: %#x.\n",
+                                active_chains, priv->hw_params.valid_rx_ant);
+
+        /* Save for use within RXON, TX, SCAN commands, etc. */
+        data->active_chains = active_chains;
+        IWL_DEBUG_CALIB(priv, "active_chains (bitwise) = 0x%x\n",
+                        active_chains);
+}
+
+
 /*
- * Accumulate 20 beacons of signal and noise statistics for each of
+ * Accumulate 16 beacons of signal and noise statistics for each of
  *   3 receivers/antennas/rx-chains, then figure out:
  * 1)  Which antennas are connected.
  * 2)  Differential rx gain settings to balance the 3 receivers.
@@ -750,8 +864,6 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
         u32 chain_sig_c;
         u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
         u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
-        u32 max_average_sig;
-        u16 max_average_sig_antenna_i;
         u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
         u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
         u16 i = 0;
@@ -759,11 +871,9 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
         u16 stat_chnum = INITIALIZATION_VALUE;
         u8 rxon_band24;
         u8 stat_band24;
-        u32 active_chains = 0;
-        u8 num_tx_chains;
         unsigned long flags;
         struct statistics_rx_non_phy *rx_info;
-        u8 first_chain;
+
         /*
          * MULTI-FIXME:
          * When we support multiple interfaces on different channels,
@@ -869,108 +979,16 @@ void iwl_chain_noise_calibration(struct iwl_priv *priv, void *stat_resp)
                 return;
 
         /* Analyze signal for disconnected antenna */
-        average_sig[0] = data->chain_signal_a /
-                         priv->cfg->base_params->chain_noise_num_beacons;
-        average_sig[1] = data->chain_signal_b /
-                         priv->cfg->base_params->chain_noise_num_beacons;
-        average_sig[2] = data->chain_signal_c /
-                         priv->cfg->base_params->chain_noise_num_beacons;
-
-        if (average_sig[0] >= average_sig[1]) {
-                max_average_sig = average_sig[0];
-                max_average_sig_antenna_i = 0;
-                active_chains = (1 << max_average_sig_antenna_i);
-        } else {
-                max_average_sig = average_sig[1];
-                max_average_sig_antenna_i = 1;
-                active_chains = (1 << max_average_sig_antenna_i);
-        }
-
-        if (average_sig[2] >= max_average_sig) {
-                max_average_sig = average_sig[2];
-                max_average_sig_antenna_i = 2;
-                active_chains = (1 << max_average_sig_antenna_i);
-        }
-
-        IWL_DEBUG_CALIB(priv, "average_sig: a %d b %d c %d\n",
-                     average_sig[0], average_sig[1], average_sig[2]);
-        IWL_DEBUG_CALIB(priv, "max_average_sig = %d, antenna %d\n",
-                     max_average_sig, max_average_sig_antenna_i);
-
-        /* Compare signal strengths for all 3 receivers. */
-        for (i = 0; i < NUM_RX_CHAINS; i++) {
-                if (i != max_average_sig_antenna_i) {
-                        s32 rssi_delta = (max_average_sig - average_sig[i]);
-
-                        /* If signal is very weak, compared with
-                         * strongest, mark it as disconnected. */
-                        if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
-                                data->disconn_array[i] = 1;
-                        else
-                                active_chains |= (1 << i);
-                        IWL_DEBUG_CALIB(priv, "i = %d  rssiDelta = %d  "
-                             "disconn_array[i] = %d\n",
-                             i, rssi_delta, data->disconn_array[i]);
-                }
-        }
-
-        /*
-         * The above algorithm sometimes fails when the ucode
-         * reports 0 for all chains. It's not clear why that
-         * happens to start with, but it is then causing trouble
-         * because this can make us enable more chains than the
-         * hardware really has.
-         *
-         * To be safe, simply mask out any chains that we know
-         * are not on the device.
-         */
         if (priv->cfg->bt_params &&
-            priv->cfg->bt_params->advanced_bt_coexist &&
-            priv->bt_full_concurrent) {
-                /* operated as 1x1 in full concurrency mode */
-                active_chains &= first_antenna(priv->hw_params.valid_rx_ant);
+            priv->cfg->bt_params->advanced_bt_coexist) {
+                /* Disable disconnected antenna algorithm for advanced
+                   bt coex, assuming valid antennas are connected */
+                data->active_chains = priv->hw_params.valid_rx_ant;
+                for (i = 0; i < NUM_RX_CHAINS; i++)
+                        if (!(data->active_chains & (1<<i)))
+                                data->disconn_array[i] = 1;
         } else
-                active_chains &= priv->hw_params.valid_rx_ant;
-
-        num_tx_chains = 0;
-        for (i = 0; i < NUM_RX_CHAINS; i++) {
-                /* loops on all the bits of
-                 * priv->hw_setting.valid_tx_ant */
-                u8 ant_msk = (1 << i);
-                if (!(priv->hw_params.valid_tx_ant & ant_msk))
-                        continue;
-
-                num_tx_chains++;
-                if (data->disconn_array[i] == 0)
-                        /* there is a Tx antenna connected */
-                        break;
-                if (num_tx_chains == priv->hw_params.tx_chains_num &&
-                    data->disconn_array[i]) {
-                        /*
-                         * If all chains are disconnected
-                         * connect the first valid tx chain
-                         */
-                        first_chain =
-                                find_first_chain(priv->cfg->valid_tx_ant);
-                        data->disconn_array[first_chain] = 0;
-                        active_chains |= BIT(first_chain);
-                        IWL_DEBUG_CALIB(priv, "All Tx chains are disconnected W/A - declare %d as connected\n",
-                                        first_chain);
-                        break;
-                }
-        }
-
-        if (active_chains != priv->hw_params.valid_rx_ant &&
-            active_chains != priv->chain_noise_data.active_chains)
-                IWL_DEBUG_CALIB(priv,
-                                "Detected that not all antennas are connected! "
-                                "Connected: %#x, valid: %#x.\n",
-                                active_chains, priv->hw_params.valid_rx_ant);
-
-        /* Save for use within RXON, TX, SCAN commands, etc. */
-        priv->chain_noise_data.active_chains = active_chains;
-        IWL_DEBUG_CALIB(priv, "active_chains (bitwise) = 0x%x\n",
-                        active_chains);
+                iwl_find_disconn_antenna(priv, average_sig, data);
 
         /* Analyze noise for rx balance */
         average_noise[0] = data->chain_noise_a /
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-agn-debugfs.c
index a358d4334a1a..a6dbd8983dac 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-debugfs.c
@@ -856,6 +856,9 @@ ssize_t iwl_ucode_bt_stats_read(struct file *file,
         if (!iwl_is_alive(priv))
                 return -EAGAIN;
 
+        if (!priv->bt_enable_flag)
+                return -EINVAL;
+
         /* make request to uCode to retrieve statistics information */
         mutex_lock(&priv->mutex);
         ret = iwl_send_statistics_request(priv, CMD_SYNC, false);
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
index a650baba0809..97906dd442e6 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-eeprom.c
@@ -75,109 +75,6 @@
 #include "iwl-agn.h"
 #include "iwl-io.h"
 
-/************************** EEPROM BANDS ****************************
- *
- * The iwl_eeprom_band definitions below provide the mapping from the
- * EEPROM contents to the specific channel number supported for each
- * band.
- *
- * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
- * definition below maps to physical channel 42 in the 5.2GHz spectrum.
- * The specific geography and calibration information for that channel
- * is contained in the eeprom map itself.
- *
- * During init, we copy the eeprom information and channel map
- * information into priv->channel_info_24/52 and priv->channel_map_24/52
- *
- * channel_map_24/52 provides the index in the channel_info array for a
- * given channel.  We have to have two separate maps as there is channel
- * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
- * band_2
- *
- * A value of 0xff stored in the channel_map indicates that the channel
- * is not supported by the hardware at all.
- *
- * A value of 0xfe in the channel_map indicates that the channel is not
- * valid for Tx with the current hardware.  This means that
- * while the system can tune and receive on a given channel, it may not
- * be able to associate or transmit any frames on that
- * channel.  There is no corresponding channel information for that
- * entry.
- *
- *********************************************************************/
-
-/**
- * struct iwl_txpwr_section: eeprom section information
- * @offset: indirect address into eeprom image
- * @count: number of "struct iwl_eeprom_enhanced_txpwr" in this section
- * @band: band type for the section
- * @is_common - true: common section, false: channel section
- * @is_cck - true: cck section, false: not cck section
- * @is_ht_40 - true: all channel in the section are HT40 channel,
- *             false: legacy or HT 20 MHz
- *             ignore if it is common section
- * @iwl_eeprom_section_channel: channel array in the section,
- *             ignore if common section
- */
-struct iwl_txpwr_section {
-        u32 offset;
-        u8 count;
-        enum ieee80211_band band;
-        bool is_common;
-        bool is_cck;
-        bool is_ht40;
-        u8 iwl_eeprom_section_channel[EEPROM_MAX_TXPOWER_SECTION_ELEMENTS];
-};
-
-/**
- * section 1 - 3 are regulatory tx power apply to all channels based on
- *    modulation: CCK, OFDM
- *    Band: 2.4GHz, 5.2GHz
- * section 4 - 10 are regulatory tx power apply to specified channels
- *    For example:
- *      1L - Channel 1 Legacy
- *      1HT - Channel 1 HT
- *      (1,+1) - Channel 1 HT40 "_above_"
- *
- * Section 1: all CCK channels
- * Section 2: all 2.4 GHz OFDM (Legacy, HT and HT40) channels
- * Section 3: all 5.2 GHz OFDM (Legacy, HT and HT40) channels
- * Section 4: 2.4 GHz 20MHz channels: 1L, 1HT, 2L, 2HT, 10L, 10HT, 11L, 11HT
- * Section 5: 2.4 GHz 40MHz channels: (1,+1) (2,+1) (6,+1) (7,+1) (9,+1)
- * Section 6: 5.2 GHz 20MHz channels: 36L, 64L, 100L, 36HT, 64HT, 100HT
- * Section 7: 5.2 GHz 40MHz channels: (36,+1) (60,+1) (100,+1)
- * Section 8: 2.4 GHz channel: 13L, 13HT
- * Section 9: 2.4 GHz channel: 140L, 140HT
- * Section 10: 2.4 GHz 40MHz channels: (132,+1)  (44,+1)
- *
- */
-static const struct iwl_txpwr_section enhinfo[] = {
-        { EEPROM_LB_CCK_20_COMMON, 1, IEEE80211_BAND_2GHZ, true, true, false },
-        { EEPROM_LB_OFDM_COMMON, 3, IEEE80211_BAND_2GHZ, true, false, false },
-        { EEPROM_HB_OFDM_COMMON, 3, IEEE80211_BAND_5GHZ, true, false, false },
-        { EEPROM_LB_OFDM_20_BAND, 8, IEEE80211_BAND_2GHZ,
-                false, false, false,
-                {1, 1, 2, 2, 10, 10, 11, 11 } },
-        { EEPROM_LB_OFDM_HT40_BAND, 5, IEEE80211_BAND_2GHZ,
-                false, false, true,
-                { 1, 2, 6, 7, 9 } },
-        { EEPROM_HB_OFDM_20_BAND, 6, IEEE80211_BAND_5GHZ,
-                false, false, false,
-                { 36, 64, 100, 36, 64, 100 } },
-        { EEPROM_HB_OFDM_HT40_BAND, 3, IEEE80211_BAND_5GHZ,
-                false, false, true,
-                { 36, 60, 100 } },
-        { EEPROM_LB_OFDM_20_CHANNEL_13, 2, IEEE80211_BAND_2GHZ,
-                false, false, false,
-                { 13, 13 } },
-        { EEPROM_HB_OFDM_20_CHANNEL_140, 2, IEEE80211_BAND_5GHZ,
-                false, false, false,
-                { 140, 140 } },
-        { EEPROM_HB_OFDM_HT40_BAND_1, 2, IEEE80211_BAND_5GHZ,
-                false, false, true,
-                { 132, 44 } },
-};
-
 /******************************************************************************
  *
  * EEPROM related functions
@@ -248,6 +145,47 @@ err:
 
 }
 
+int iwl_eeprom_check_sku(struct iwl_priv *priv)
+{
+        u16 eeprom_sku;
+        u16 radio_cfg;
+
+        eeprom_sku = iwl_eeprom_query16(priv, EEPROM_SKU_CAP);
+
+        priv->cfg->sku = ((eeprom_sku & EEPROM_SKU_CAP_BAND_SELECTION) >>
+                        EEPROM_SKU_CAP_BAND_POS);
+        if (eeprom_sku & EEPROM_SKU_CAP_11N_ENABLE)
+                priv->cfg->sku |= IWL_SKU_N;
+
+        if (!priv->cfg->sku) {
+                IWL_ERR(priv, "Invalid device sku\n");
+                return -EINVAL;
+        }
+
+        IWL_INFO(priv, "Device SKU: 0X%x\n", priv->cfg->sku);
+
+        if (!priv->cfg->valid_tx_ant && !priv->cfg->valid_rx_ant) {
+                /* not using .cfg overwrite */
+                radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
+                priv->cfg->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
+                priv->cfg->valid_rx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg);
+                if (!priv->cfg->valid_tx_ant || !priv->cfg->valid_rx_ant) {
+                        IWL_ERR(priv, "Invalid chain (0X%x, 0X%x)\n",
+                                priv->cfg->valid_tx_ant,
+                                priv->cfg->valid_rx_ant);
+                        return -EINVAL;
+                }
+                IWL_INFO(priv, "Valid Tx ant: 0X%x, Valid Rx ant: 0X%x\n",
+                         priv->cfg->valid_tx_ant, priv->cfg->valid_rx_ant);
+        }
+        /*
+         * for some special cases,
+         * EEPROM did not reflect the correct antenna setting
+         * so overwrite the valid tx/rx antenna from .cfg
+         */
+        return 0;
+}
+
 void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
 {
         const u8 *addr = priv->cfg->ops->lib->eeprom_ops.query_addr(priv,
@@ -265,15 +203,6 @@ static s8 iwl_get_max_txpower_avg(struct iwl_priv *priv,
 {
         s8 max_txpower_avg = 0; /* (dBm) */
 
-        IWL_DEBUG_INFO(priv, "%d - "
-                        "chain_a: %d dB chain_b: %d dB "
-                        "chain_c: %d dB mimo2: %d dB mimo3: %d dB\n",
-                        element,
-                        enhanced_txpower[element].chain_a_max >> 1,
-                        enhanced_txpower[element].chain_b_max >> 1,
-                        enhanced_txpower[element].chain_c_max >> 1,
-                        enhanced_txpower[element].mimo2_max >> 1,
-                        enhanced_txpower[element].mimo3_max >> 1);
         /* Take the highest tx power from any valid chains */
         if ((priv->cfg->valid_tx_ant & ANT_A) &&
             (enhanced_txpower[element].chain_a_max > max_txpower_avg))
@@ -303,152 +232,106 @@ static s8 iwl_get_max_txpower_avg(struct iwl_priv *priv,
         return (max_txpower_avg & 0x01) + (max_txpower_avg >> 1);
 }
 
-/**
- * iwl_update_common_txpower: update channel tx power
- *     update tx power per band based on EEPROM enhanced tx power info.
- */
-static s8 iwl_update_common_txpower(struct iwl_priv *priv,
-                struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
-                int section, int element, s8 *max_txpower_in_half_dbm)
+static void
+iwlcore_eeprom_enh_txp_read_element(struct iwl_priv *priv,
+                                    struct iwl_eeprom_enhanced_txpwr *txp,
+                                    s8 max_txpower_avg)
 {
-        struct iwl_channel_info *ch_info;
-        int ch;
-        bool is_ht40 = false;
-        s8 max_txpower_avg; /* (dBm) */
-
-        /* it is common section, contain all type (Legacy, HT and HT40)
-         * based on the element in the section to determine
-         * is it HT 40 or not
-         */
-        if (element == EEPROM_TXPOWER_COMMON_HT40_INDEX)
-                is_ht40 = true;
-        max_txpower_avg =
-                iwl_get_max_txpower_avg(priv, enhanced_txpower,
-                                        element, max_txpower_in_half_dbm);
-
-        ch_info = priv->channel_info;
-
-        for (ch = 0; ch < priv->channel_count; ch++) {
-                /* find matching band and update tx power if needed */
-                if ((ch_info->band == enhinfo[section].band) &&
-                    (ch_info->max_power_avg < max_txpower_avg) &&
-                    (!is_ht40)) {
-                        /* Update regulatory-based run-time data */
-                        ch_info->max_power_avg = ch_info->curr_txpow =
-                                max_txpower_avg;
+        int ch_idx;
+        bool is_ht40 = txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ;
+        enum ieee80211_band band;
+
+        band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ?
+                IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
+
+        for (ch_idx = 0; ch_idx < priv->channel_count; ch_idx++) {
+                struct iwl_channel_info *ch_info = &priv->channel_info[ch_idx];
+
+                /* update matching channel or from common data only */
+                if (txp->channel != 0 && ch_info->channel != txp->channel)
+                        continue;
+
+                /* update matching band only */
+                if (band != ch_info->band)
+                        continue;
+
+                if (ch_info->max_power_avg < max_txpower_avg && !is_ht40) {
+                        ch_info->max_power_avg = max_txpower_avg;
+                        ch_info->curr_txpow = max_txpower_avg;
                         ch_info->scan_power = max_txpower_avg;
                 }
-                if ((ch_info->band == enhinfo[section].band) && is_ht40 &&
-                    (ch_info->ht40_max_power_avg < max_txpower_avg)) {
-                        /* Update regulatory-based run-time data */
+
+                if (is_ht40 && ch_info->ht40_max_power_avg < max_txpower_avg)
                         ch_info->ht40_max_power_avg = max_txpower_avg;
-                }
-                ch_info++;
         }
-        return max_txpower_avg;
 }
 
-/**
- * iwl_update_channel_txpower: update channel tx power
- *      update channel tx power based on EEPROM enhanced tx power info.
- */
-static s8 iwl_update_channel_txpower(struct iwl_priv *priv,
-                struct iwl_eeprom_enhanced_txpwr *enhanced_txpower,
-                int section, int element, s8 *max_txpower_in_half_dbm)
-{
-        struct iwl_channel_info *ch_info;
-        int ch;
-        u8 channel;
-        s8 max_txpower_avg; /* (dBm) */
-
-        channel = enhinfo[section].iwl_eeprom_section_channel[element];
-        max_txpower_avg =
-                iwl_get_max_txpower_avg(priv, enhanced_txpower,
-                                        element, max_txpower_in_half_dbm);
-
-        ch_info = priv->channel_info;
-        for (ch = 0; ch < priv->channel_count; ch++) {
-                /* find matching channel and update tx power if needed */
-                if (ch_info->channel == channel) {
-                        if ((ch_info->max_power_avg < max_txpower_avg) &&
-                            (!enhinfo[section].is_ht40)) {
-                                /* Update regulatory-based run-time data */
-                                ch_info->max_power_avg = max_txpower_avg;
-                                ch_info->curr_txpow = max_txpower_avg;
-                                ch_info->scan_power = max_txpower_avg;
-                        }
-                        if ((enhinfo[section].is_ht40) &&
-                            (ch_info->ht40_max_power_avg < max_txpower_avg)) {
-                                /* Update regulatory-based run-time data */
-                                ch_info->ht40_max_power_avg = max_txpower_avg;
-                        }
-                        break;
-                }
-                ch_info++;
-        }
-        return max_txpower_avg;
-}
+#define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT)
+#define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr)
+#define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE)
+
+#define TXP_CHECK_AND_PRINT(x) ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) \
+                            ? # x " " : "")
 
-/**
- * iwlcore_eeprom_enhanced_txpower: process enhanced tx power info
- */
 void iwlcore_eeprom_enhanced_txpower(struct iwl_priv *priv)
 {
-        int eeprom_section_count = 0;
-        int section, element;
-        struct iwl_eeprom_enhanced_txpwr *enhanced_txpower;
-        u32 offset;
-        s8 max_txpower_avg; /* (dBm) */
-        s8 max_txpower_in_half_dbm; /* (half-dBm) */
-
-        /* Loop through all the sections
-         * adjust bands and channel's max tx power
-         * Set the tx_power_user_lmt to the highest power
-         * supported by any channels and chains
-         */
-        for (section = 0; section < ARRAY_SIZE(enhinfo); section++) {
-                eeprom_section_count = enhinfo[section].count;
-                offset = enhinfo[section].offset;
-                enhanced_txpower = (struct iwl_eeprom_enhanced_txpwr *)
-                                iwl_eeprom_query_addr(priv, offset);
+        struct iwl_eeprom_enhanced_txpwr *txp_array, *txp;
+        int idx, entries;
+        __le16 *txp_len;
+        s8 max_txp_avg, max_txp_avg_halfdbm;
+
+        BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8);
+
+        /* the length is in 16-bit words, but we want entries */
+        txp_len = (__le16 *) iwlagn_eeprom_query_addr(priv, EEPROM_TXP_SZ_OFFS);
+        entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN;
+
+        txp_array = (void *) iwlagn_eeprom_query_addr(priv, EEPROM_TXP_OFFS);
+
+        for (idx = 0; idx < entries; idx++) {
+                txp = &txp_array[idx];
+                /* skip invalid entries */
+                if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID))
+                        continue;
+
+                IWL_DEBUG_EEPROM(priv, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n",
+                                 (txp->channel && (txp->flags &
+                                        IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ?
+                                        "Common " : (txp->channel) ?
+                                        "Channel" : "Common",
+                                 (txp->channel),
+                                 TXP_CHECK_AND_PRINT(VALID),
+                                 TXP_CHECK_AND_PRINT(BAND_52G),
+                                 TXP_CHECK_AND_PRINT(OFDM),
+                                 TXP_CHECK_AND_PRINT(40MHZ),
+                                 TXP_CHECK_AND_PRINT(HT_AP),
+                                 TXP_CHECK_AND_PRINT(RES1),
+                                 TXP_CHECK_AND_PRINT(RES2),
+                                 TXP_CHECK_AND_PRINT(COMMON_TYPE),
+                                 txp->flags);
+                IWL_DEBUG_EEPROM(priv, "\t\t chain_A: 0x%02x "
+                                 "chain_B: 0X%02x chain_C: 0X%02x\n",
+                                 txp->chain_a_max, txp->chain_b_max,
+                                 txp->chain_c_max);
+                IWL_DEBUG_EEPROM(priv, "\t\t MIMO2: 0x%02x "
+                                 "MIMO3: 0x%02x High 20_on_40: 0x%02x "
+                                 "Low 20_on_40: 0x%02x\n",
+                                 txp->mimo2_max, txp->mimo3_max,
+                                 ((txp->delta_20_in_40 & 0xf0) >> 4),
+                                 (txp->delta_20_in_40 & 0x0f));
+
+                max_txp_avg = iwl_get_max_txpower_avg(priv, txp_array, idx,
+                                                      &max_txp_avg_halfdbm);
 
                 /*
-                 * check for valid entry -
-                 * different version of EEPROM might contain different set
-                 * of enhanced tx power table
-                 * always check for valid entry before process
-                 * the information
+                 * Update the user limit values values to the highest
+                 * power supported by any channel
                  */
-                if (!enhanced_txpower->common || enhanced_txpower->reserved)
-                        continue;
+                if (max_txp_avg > priv->tx_power_user_lmt)
+                        priv->tx_power_user_lmt = max_txp_avg;
+                if (max_txp_avg_halfdbm > priv->tx_power_lmt_in_half_dbm)
+                        priv->tx_power_lmt_in_half_dbm = max_txp_avg_halfdbm;
 
-                for (element = 0; element < eeprom_section_count; element++) {
-                        if (enhinfo[section].is_common)
-                                max_txpower_avg =
-                                        iwl_update_common_txpower(priv,
-                                                enhanced_txpower, section,
-                                                element,
-                                                &max_txpower_in_half_dbm);
-                        else
-                                max_txpower_avg =
-                                        iwl_update_channel_txpower(priv,
-                                                enhanced_txpower, section,
-                                                element,
-                                                &max_txpower_in_half_dbm);
-
-                        /* Update the tx_power_user_lmt to the highest power
-                         * supported by any channel */
-                        if (max_txpower_avg > priv->tx_power_user_lmt)
-                                priv->tx_power_user_lmt = max_txpower_avg;
-
-                        /*
-                         * Update the tx_power_lmt_in_half_dbm to
-                         * the highest power supported by any channel
-                         */
-                        if (max_txpower_in_half_dbm >
-                            priv->tx_power_lmt_in_half_dbm)
-                                priv->tx_power_lmt_in_half_dbm =
-                                        max_txpower_in_half_dbm;
-                }
+                iwlcore_eeprom_enh_txp_read_element(priv, txp, max_txp_avg);
         }
 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c b/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
index ffb2f4111ad0..366340f3fb0f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-hcmd.c
@@ -307,6 +307,7 @@ static int iwlagn_set_pan_params(struct iwl_priv *priv)
 
         if (ctx_bss->vif && ctx_pan->vif) {
                 int bcnint = ctx_pan->vif->bss_conf.beacon_int;
+                int dtim = ctx_pan->vif->bss_conf.dtim_period ?: 1;
 
                 /* should be set, but seems unused?? */
                 cmd.flags |= cpu_to_le16(IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE);
@@ -329,10 +330,10 @@ static int iwlagn_set_pan_params(struct iwl_priv *priv)
                 if (test_bit(STATUS_SCAN_HW, &priv->status) ||
                     (!ctx_bss->vif->bss_conf.idle &&
                      !ctx_bss->vif->bss_conf.assoc)) {
-                        slot0 = bcnint * 3 - 20;
+                        slot0 = dtim * bcnint * 3 - 20;
                         slot1 = 20;
                 } else if (!ctx_pan->vif->bss_conf.idle &&
-                           !ctx_pan->vif->bss_conf.assoc) {
+                           !ctx_pan->vif->bss_conf.assoc) {
                         slot1 = bcnint * 3 - 20;
                         slot0 = 20;
                 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-lib.c b/drivers/net/wireless/iwlwifi/iwl-agn-lib.c
index b555edd53354..3dee87e8f55d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-lib.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-lib.c
@@ -405,6 +405,7 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
                 return;
         }
 
+        txq->time_stamp = jiffies;
         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
         memset(&info->status, 0, sizeof(info->status));
 
@@ -445,22 +446,17 @@ static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
 
                         if (priv->mac80211_registered &&
                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
-                            (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
-                                if (agg->state == IWL_AGG_OFF)
-                                        iwl_wake_queue(priv, txq_id);
-                                else
-                                        iwl_wake_queue(priv, txq->swq_id);
-                        }
+                            (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
+                                iwl_wake_queue(priv, txq);
                 }
         } else {
-                BUG_ON(txq_id != txq->swq_id);
                 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
                 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 
                 if (priv->mac80211_registered &&
                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
-                        iwl_wake_queue(priv, txq_id);
+                        iwl_wake_queue(priv, txq);
         }
 
         iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
@@ -496,6 +492,10 @@ int iwlagn_send_tx_power(struct iwl_priv *priv)
         struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
         u8 tx_ant_cfg_cmd;
 
+        if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
+                      "TX Power requested while scanning!\n"))
+                return -EAGAIN;
+
         /* half dBm need to multiply */
         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 
@@ -522,9 +522,8 @@ int iwlagn_send_tx_power(struct iwl_priv *priv)
         else
                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 
-        return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
-                                       sizeof(tx_power_cmd), &tx_power_cmd,
-                                       NULL);
+        return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
+                                &tx_power_cmd);
 }
 
 void iwlagn_temperature(struct iwl_priv *priv)
@@ -569,6 +568,12 @@ static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
         case INDIRECT_REGULATORY:
                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
                 break;
+        case INDIRECT_TXP_LIMIT:
+                offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
+                break;
+        case INDIRECT_TXP_LIMIT_SIZE:
+                offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
+                break;
         case INDIRECT_CALIBRATION:
                 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
                 break;
@@ -750,6 +755,12 @@ int iwlagn_hw_nic_init(struct iwl_priv *priv)
         } else
                 iwlagn_txq_ctx_reset(priv);
 
+        if (priv->cfg->base_params->shadow_reg_enable) {
+                /* enable shadow regs in HW */
+                iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
+                        0x800FFFFF);
+        }
+
         set_bit(STATUS_INIT, &priv->status);
 
         return 0;
@@ -1481,15 +1492,11 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
         if (priv->cfg->scan_rx_antennas[band])
                 rx_ant = priv->cfg->scan_rx_antennas[band];
 
-        if (priv->cfg->scan_tx_antennas[band])
-                scan_tx_antennas = priv->cfg->scan_tx_antennas[band];
-
-        if (priv->cfg->bt_params &&
-            priv->cfg->bt_params->advanced_bt_coexist &&
-            priv->bt_full_concurrent) {
-                /* operated as 1x1 in full concurrency mode */
-                scan_tx_antennas = first_antenna(
-                        priv->cfg->scan_tx_antennas[band]);
+        if (band == IEEE80211_BAND_2GHZ &&
+            priv->cfg->bt_params &&
+            priv->cfg->bt_params->advanced_bt_coexist) {
+                /* transmit 2.4 GHz probes only on first antenna */
+                scan_tx_antennas = first_antenna(scan_tx_antennas);
         }
 
         priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
@@ -1584,22 +1591,6 @@ int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
         return ret;
 }
 
-void iwlagn_post_scan(struct iwl_priv *priv)
-{
-        struct iwl_rxon_context *ctx;
-
-        /*
-         * Since setting the RXON may have been deferred while
-         * performing the scan, fire one off if needed
-         */
-        for_each_context(priv, ctx)
-                if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
-                        iwlagn_commit_rxon(priv, ctx);
-
-        if (priv->cfg->ops->hcmd->set_pan_params)
-                priv->cfg->ops->hcmd->set_pan_params(priv);
-}
-
 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
                                struct ieee80211_vif *vif, bool add)
 {
@@ -1790,7 +1781,7 @@ static const __le32 iwlagn_def_3w_lookup[12] = {
         cpu_to_le32(0xc0004000),
         cpu_to_le32(0x00004000),
         cpu_to_le32(0xf0005000),
-        cpu_to_le32(0xf0004000),
+        cpu_to_le32(0xf0005000),
 };
 
 static const __le32 iwlagn_concurrent_lookup[12] = {
@@ -1826,6 +1817,7 @@ void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
                 bt_cmd.prio_boost = 0;
         bt_cmd.kill_ack_mask = priv->kill_ack_mask;
         bt_cmd.kill_cts_mask = priv->kill_cts_mask;
+
         bt_cmd.valid = priv->bt_valid;
         bt_cmd.tx_prio_boost = 0;
         bt_cmd.rx_prio_boost = 0;
@@ -1841,10 +1833,15 @@ void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
         } else {
                 bt_cmd.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
                                         IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
+                if (priv->cfg->bt_params &&
+                    priv->cfg->bt_params->bt_sco_disable)
+                        bt_cmd.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
+
                 if (priv->bt_ch_announce)
                         bt_cmd.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
                 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", bt_cmd.flags);
         }
+        priv->bt_enable_flag = bt_cmd.flags;
         if (priv->bt_full_concurrent)
                 memcpy(bt_cmd.bt3_lookup_table, iwlagn_concurrent_lookup,
                         sizeof(iwlagn_concurrent_lookup));
@@ -1884,12 +1881,20 @@ static void iwlagn_bt_traffic_change_work(struct work_struct *work)
         struct iwl_rxon_context *ctx;
         int smps_request = -1;
 
+        /*
+         * Note: bt_traffic_load can be overridden by scan complete and
+         * coex profile notifications. Ignore that since only bad consequence
+         * can be not matching debug print with actual state.
+         */
         IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
                        priv->bt_traffic_load);
 
         switch (priv->bt_traffic_load) {
         case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
-                smps_request = IEEE80211_SMPS_AUTOMATIC;
+                if (priv->bt_status)
+                        smps_request = IEEE80211_SMPS_DYNAMIC;
+                else
+                        smps_request = IEEE80211_SMPS_AUTOMATIC;
                 break;
         case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
                 smps_request = IEEE80211_SMPS_DYNAMIC;
@@ -1906,6 +1911,16 @@ static void iwlagn_bt_traffic_change_work(struct work_struct *work)
 
         mutex_lock(&priv->mutex);
 
+        /*
+         * We can not send command to firmware while scanning. When the scan
+         * complete we will schedule this work again. We do check with mutex
+         * locked to prevent new scan request to arrive. We do not check
+         * STATUS_SCANNING to avoid race when queue_work two times from
+         * different notifications, but quit and not perform any work at all.
+         */
+        if (test_bit(STATUS_SCAN_HW, &priv->status))
+                goto out;
+
         if (priv->cfg->ops->lib->update_chain_flags)
                 priv->cfg->ops->lib->update_chain_flags(priv);
 
@@ -1915,7 +1930,7 @@ static void iwlagn_bt_traffic_change_work(struct work_struct *work)
                                 ieee80211_request_smps(ctx->vif, smps_request);
                 }
         }
-
+out:
         mutex_unlock(&priv->mutex);
 }
 
@@ -1986,24 +2001,29 @@ static void iwlagn_print_uartmsg(struct iwl_priv *priv,
                         BT_UART_MSG_FRAME7CONNECTABLE_POS);
 }
 
-static void iwlagn_set_kill_ack_msk(struct iwl_priv *priv,
-                                     struct iwl_bt_uart_msg *uart_msg)
+static void iwlagn_set_kill_msk(struct iwl_priv *priv,
+                                struct iwl_bt_uart_msg *uart_msg)
 {
-        u8 kill_ack_msk;
-        __le32 bt_kill_ack_msg[2] = {
-                        cpu_to_le32(0xFFFFFFF), cpu_to_le32(0xFFFFFC00) };
-
-        kill_ack_msk = (((BT_UART_MSG_FRAME3A2DP_MSK |
-                        BT_UART_MSG_FRAME3SNIFF_MSK |
-                        BT_UART_MSG_FRAME3SCOESCO_MSK) &
-                        uart_msg->frame3) == 0) ? 1 : 0;
-        if (priv->kill_ack_mask != bt_kill_ack_msg[kill_ack_msk]) {
+        u8 kill_msk;
+        static const __le32 bt_kill_ack_msg[2] = {
+                IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
+                IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
+        static const __le32 bt_kill_cts_msg[2] = {
+                IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
+                IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
+
+        kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
+                ? 1 : 0;
+        if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
+            priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
                 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
-                priv->kill_ack_mask = bt_kill_ack_msg[kill_ack_msk];
+                priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
+                priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
+                priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
+
                 /* schedule to send runtime bt_config */
                 queue_work(priv->workqueue, &priv->bt_runtime_config);
         }
-
 }
 
 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
@@ -2014,7 +2034,6 @@ void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
         struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
         struct iwlagn_bt_sco_cmd sco_cmd = { .flags = 0 };
         struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
-        u8 last_traffic_load;
 
         IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
         IWL_DEBUG_NOTIF(priv, "    status: %d\n", coex->bt_status);
@@ -2023,11 +2042,10 @@ void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
                         coex->bt_ci_compliance);
         iwlagn_print_uartmsg(priv, uart_msg);
 
-        last_traffic_load = priv->notif_bt_traffic_load;
-        priv->notif_bt_traffic_load = coex->bt_traffic_load;
+        priv->last_bt_traffic_load = priv->bt_traffic_load;
         if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
                 if (priv->bt_status != coex->bt_status ||
-                    last_traffic_load != coex->bt_traffic_load) {
+                    priv->last_bt_traffic_load != coex->bt_traffic_load) {
                         if (coex->bt_status) {
                                 /* BT on */
                                 if (!priv->bt_ch_announce)
@@ -2056,7 +2074,7 @@ void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
                 }
         }
 
-        iwlagn_set_kill_ack_msk(priv, uart_msg);
+        iwlagn_set_kill_msk(priv, uart_msg);
 
         /* FIXME: based on notification, adjust the prio_boost */
 
@@ -2276,7 +2294,7 @@ static const char *get_csr_string(int cmd)
 void iwl_dump_csr(struct iwl_priv *priv)
 {
         int i;
-        u32 csr_tbl[] = {
+        static const u32 csr_tbl[] = {
                 CSR_HW_IF_CONFIG_REG,
                 CSR_INT_COALESCING,
                 CSR_INT,
@@ -2335,7 +2353,7 @@ int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
         int pos = 0;
         size_t bufsz = 0;
 #endif
-        u32 fh_tbl[] = {
+        static const u32 fh_tbl[] = {
                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
                 FH_RSCSR_CHNL0_WPTR,
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
index 065553629de5..75fcd30a7c13 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rs.c
@@ -387,7 +387,7 @@ static int rs_tl_turn_on_agg_for_tid(struct iwl_priv *priv,
         if (load > IWL_AGG_LOAD_THRESHOLD) {
                 IWL_DEBUG_HT(priv, "Starting Tx agg: STA: %pM tid: %d\n",
                                 sta->addr, tid);
-                ret = ieee80211_start_tx_ba_session(sta, tid);
+                ret = ieee80211_start_tx_ba_session(sta, tid, 5000);
                 if (ret == -EAGAIN) {
                         /*
                          * driver and mac80211 is out of sync
@@ -833,17 +833,23 @@ static void rs_bt_update_lq(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
                             struct iwl_lq_sta *lq_sta)
 {
         struct iwl_scale_tbl_info *tbl;
-        bool full_concurrent;
+        bool full_concurrent = priv->bt_full_concurrent;
         unsigned long flags;
 
-        spin_lock_irqsave(&priv->lock, flags);
-        if (priv->bt_ci_compliance && priv->bt_ant_couple_ok)
-                full_concurrent = true;
-        else
-                full_concurrent = false;
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        if (priv->bt_full_concurrent != full_concurrent) {
+        if (priv->bt_ant_couple_ok) {
+                /*
+                 * Is there a need to switch between
+                 * full concurrency and 3-wire?
+                 */
+                spin_lock_irqsave(&priv->lock, flags);
+                if (priv->bt_ci_compliance && priv->bt_ant_couple_ok)
+                        full_concurrent = true;
+                else
+                        full_concurrent = false;
+                spin_unlock_irqrestore(&priv->lock, flags);
+        }
+        if ((priv->bt_traffic_load != priv->last_bt_traffic_load) ||
+            (priv->bt_full_concurrent != full_concurrent)) {
                 priv->bt_full_concurrent = full_concurrent;
 
                 /* Update uCode's rate table. */
@@ -1040,8 +1046,7 @@ done:
         if (sta && sta->supp_rates[sband->band])
                 rs_rate_scale_perform(priv, skb, sta, lq_sta);
 
-        /* Is there a need to switch between full concurrency and 3-wire? */
-        if (priv->bt_ant_couple_ok)
+        if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist)
                 rs_bt_update_lq(priv, ctx, lq_sta);
 }
 
@@ -2868,6 +2873,10 @@ void iwl_rs_rate_init(struct iwl_priv *priv, struct ieee80211_sta *sta, u8 sta_i
                 lq_sta->last_txrate_idx += IWL_FIRST_OFDM_RATE;
         lq_sta->is_agg = 0;
 
+#ifdef CONFIG_MAC80211_DEBUGFS
+        lq_sta->dbg_fixed_rate = 0;
+#endif
+
         rs_initialize_lq(priv, conf, sta, lq_sta);
 }
 
@@ -3010,10 +3019,7 @@ static void rs_fill_link_cmd(struct iwl_priv *priv,
          */
         if (priv && priv->cfg->bt_params &&
             priv->cfg->bt_params->agg_time_limit &&
-            priv->cfg->bt_params->agg_time_limit >=
-                LINK_QUAL_AGG_TIME_LIMIT_MIN &&
-            priv->cfg->bt_params->agg_time_limit <=
-                 LINK_QUAL_AGG_TIME_LIMIT_MAX)
+            priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
                 lq_cmd->agg_params.agg_time_limit =
                         cpu_to_le16(priv->cfg->bt_params->agg_time_limit);
 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
new file mode 100644
index 000000000000..6d140bd53291
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-rxon.c
@@ -0,0 +1,642 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * Intel Linux Wireless <ilw@linux.intel.com>
+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+ *
+ *****************************************************************************/
+
+#include "iwl-dev.h"
+#include "iwl-agn.h"
+#include "iwl-sta.h"
+#include "iwl-core.h"
+#include "iwl-agn-calib.h"
+
+static int iwlagn_disable_bss(struct iwl_priv *priv,
+                              struct iwl_rxon_context *ctx,
+                              struct iwl_rxon_cmd *send)
+{
+        __le32 old_filter = send->filter_flags;
+        int ret;
+
+        send->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+        ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, sizeof(*send), send);
+
+        send->filter_flags = old_filter;
+
+        if (ret)
+                IWL_ERR(priv, "Error clearing ASSOC_MSK on BSS (%d)\n", ret);
+
+        return ret;
+}
+
+static int iwlagn_disable_pan(struct iwl_priv *priv,
+                              struct iwl_rxon_context *ctx,
+                              struct iwl_rxon_cmd *send)
+{
+        __le32 old_filter = send->filter_flags;
+        u8 old_dev_type = send->dev_type;
+        int ret;
+
+        send->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+        send->dev_type = RXON_DEV_TYPE_P2P;
+        ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd, sizeof(*send), send);
+
+        send->filter_flags = old_filter;
+        send->dev_type = old_dev_type;
+
+        if (ret)
+                IWL_ERR(priv, "Error disabling PAN (%d)\n", ret);
+
+        /* FIXME: WAIT FOR PAN DISABLE */
+        msleep(300);
+
+        return ret;
+}
+
+static void iwlagn_update_qos(struct iwl_priv *priv,
+                              struct iwl_rxon_context *ctx)
+{
+        int ret;
+
+        if (!ctx->is_active)
+                return;
+
+        ctx->qos_data.def_qos_parm.qos_flags = 0;
+
+        if (ctx->qos_data.qos_active)
+                ctx->qos_data.def_qos_parm.qos_flags |=
+                        QOS_PARAM_FLG_UPDATE_EDCA_MSK;
+
+        if (ctx->ht.enabled)
+                ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
+
+        IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
+                      ctx->qos_data.qos_active,
+                      ctx->qos_data.def_qos_parm.qos_flags);
+
+        ret = iwl_send_cmd_pdu(priv, ctx->qos_cmd,
+                               sizeof(struct iwl_qosparam_cmd),
+                               &ctx->qos_data.def_qos_parm);
+        if (ret)
+                IWL_ERR(priv, "Failed to update QoS\n");
+}
+
+static int iwlagn_update_beacon(struct iwl_priv *priv,
+                                struct ieee80211_vif *vif)
+{
+        lockdep_assert_held(&priv->mutex);
+
+        dev_kfree_skb(priv->beacon_skb);
+        priv->beacon_skb = ieee80211_beacon_get(priv->hw, vif);
+        if (!priv->beacon_skb)
+                return -ENOMEM;
+        return iwlagn_send_beacon_cmd(priv);
+}
+
+/**
+ * iwlagn_commit_rxon - commit staging_rxon to hardware
+ *
+ * The RXON command in staging_rxon is committed to the hardware and
+ * the active_rxon structure is updated with the new data.  This
+ * function correctly transitions out of the RXON_ASSOC_MSK state if
+ * a HW tune is required based on the RXON structure changes.
+ */
+int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
+{
+        /* cast away the const for active_rxon in this function */
+        struct iwl_rxon_cmd *active = (void *)&ctx->active;
+        bool new_assoc = !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
+        bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
+        int ret;
+
+        lockdep_assert_held(&priv->mutex);
+
+        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
+                return -EINVAL;
+
+        if (!iwl_is_alive(priv))
+                return -EBUSY;
+
+        /* This function hardcodes a bunch of dual-mode assumptions */
+        BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
+
+        if (!ctx->is_active)
+                return 0;
+
+        /* always get timestamp with Rx frame */
+        ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
+
+        if ((ctx->vif && ctx->vif->bss_conf.use_short_slot) ||
+            !(ctx->staging.flags & RXON_FLG_BAND_24G_MSK))
+                ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
+        else
+                ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
+
+        ret = iwl_check_rxon_cmd(priv, ctx);
+        if (ret) {
+                IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
+                return -EINVAL;
+        }
+
+        /*
+         * receive commit_rxon request
+         * abort any previous channel switch if still in process
+         */
+        if (priv->switch_rxon.switch_in_progress &&
+            (priv->switch_rxon.channel != ctx->staging.channel)) {
+                IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
+                      le16_to_cpu(priv->switch_rxon.channel));
+                iwl_chswitch_done(priv, false);
+        }
+
+        /*
+         * If we don't need to send a full RXON, we can use
+         * iwl_rxon_assoc_cmd which is used to reconfigure filter
+         * and other flags for the current radio configuration.
+         */
+        if (!iwl_full_rxon_required(priv, ctx)) {
+                ret = iwl_send_rxon_assoc(priv, ctx);
+                if (ret) {
+                        IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
+                        return ret;
+                }
+
+                memcpy(active, &ctx->staging, sizeof(*active));
+                iwl_print_rx_config_cmd(priv, ctx);
+                return 0;
+        }
+
+        if (priv->cfg->ops->hcmd->set_pan_params) {
+                ret = priv->cfg->ops->hcmd->set_pan_params(priv);
+                if (ret)
+                        return ret;
+        }
+
+        iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
+
+        IWL_DEBUG_INFO(priv,
+                       "Going to commit RXON\n"
+                       "  * with%s RXON_FILTER_ASSOC_MSK\n"
+                       "  * channel = %d\n"
+                       "  * bssid = %pM\n",
+                       (new_assoc ? "" : "out"),
+                       le16_to_cpu(ctx->staging.channel),
+                       ctx->staging.bssid_addr);
+
+        /*
+         * Always clear associated first, but with the correct config.
+         * This is required as for example station addition for the
+         * AP station must be done after the BSSID is set to correctly
+         * set up filters in the device.
+         */
+        if ((old_assoc && new_assoc) || !new_assoc) {
+                if (ctx->ctxid == IWL_RXON_CTX_BSS)
+                        ret = iwlagn_disable_bss(priv, ctx, &ctx->staging);
+                else
+                        ret = iwlagn_disable_pan(priv, ctx, &ctx->staging);
+                if (ret)
+                        return ret;
+
+                memcpy(active, &ctx->staging, sizeof(*active));
+
+                /*
+                 * Un-assoc RXON clears the station table and WEP
+                 * keys, so we have to restore those afterwards.
+                 */
+                iwl_clear_ucode_stations(priv, ctx);
+                iwl_restore_stations(priv, ctx);
+                ret = iwl_restore_default_wep_keys(priv, ctx);
+                if (ret) {
+                        IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
+                        return ret;
+                }
+        }
+
+        /* RXON timing must be before associated RXON */
+        ret = iwl_send_rxon_timing(priv, ctx);
+        if (ret) {
+                IWL_ERR(priv, "Failed to send timing (%d)!\n", ret);
+                return ret;
+        }
+
+        if (new_assoc) {
+                /* QoS info may be cleared by previous un-assoc RXON */
+                iwlagn_update_qos(priv, ctx);
+
+                /*
+                 * We'll run into this code path when beaconing is
+                 * enabled, but then we also need to send the beacon
+                 * to the device.
+                 */
+                if (ctx->vif && (ctx->vif->type == NL80211_IFTYPE_AP)) {
+                        ret = iwlagn_update_beacon(priv, ctx->vif);
+                        if (ret) {
+                                IWL_ERR(priv,
+                                        "Error sending required beacon (%d)!\n",
+                                        ret);
+                                return ret;
+                        }
+                }
+
+                priv->start_calib = 0;
+                /*
+                 * Apply the new configuration.
+                 *
+                 * Associated RXON doesn't clear the station table in uCode,
+                 * so we don't need to restore stations etc. after this.
+                 */
+                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
+                              sizeof(struct iwl_rxon_cmd), &ctx->staging);
+                if (ret) {
+                        IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
+                        return ret;
+                }
+                memcpy(active, &ctx->staging, sizeof(*active));
+
+                iwl_reprogram_ap_sta(priv, ctx);
+
+                /* IBSS beacon needs to be sent after setting assoc */
+                if (ctx->vif && (ctx->vif->type == NL80211_IFTYPE_ADHOC))
+                        if (iwlagn_update_beacon(priv, ctx->vif))
+                                IWL_ERR(priv, "Error sending IBSS beacon\n");
+        }
+
+        iwl_print_rx_config_cmd(priv, ctx);
+
+        iwl_init_sensitivity(priv);
+
+        /*
+         * If we issue a new RXON command which required a tune then we must
+         * send a new TXPOWER command or we won't be able to Tx any frames.
+         *
+         * FIXME: which RXON requires a tune? Can we optimise this out in
+         *        some cases?
+         */
+        ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
+        if (ret) {
+                IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
+                return ret;
+        }
+
+        return 0;
+}
+
+int iwlagn_mac_config(struct ieee80211_hw *hw, u32 changed)
+{
+        struct iwl_priv *priv = hw->priv;
+        struct iwl_rxon_context *ctx;
+        struct ieee80211_conf *conf = &hw->conf;
+        struct ieee80211_channel *channel = conf->channel;
+        const struct iwl_channel_info *ch_info;
+        int ret = 0;
+        bool ht_changed[NUM_IWL_RXON_CTX] = {};
+
+        IWL_DEBUG_MAC80211(priv, "changed %#x", changed);
+
+        mutex_lock(&priv->mutex);
+
+        if (unlikely(test_bit(STATUS_SCANNING, &priv->status))) {
+                IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
+                goto out;
+        }
+
+        if (!iwl_is_ready(priv)) {
+                IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
+                goto out;
+        }
+
+        if (changed & (IEEE80211_CONF_CHANGE_SMPS |
+                       IEEE80211_CONF_CHANGE_CHANNEL)) {
+                /* mac80211 uses static for non-HT which is what we want */
+                priv->current_ht_config.smps = conf->smps_mode;
+
+                /*
+                 * Recalculate chain counts.
+                 *
+                 * If monitor mode is enabled then mac80211 will
+                 * set up the SM PS mode to OFF if an HT channel is
+                 * configured.
+                 */
+                if (priv->cfg->ops->hcmd->set_rxon_chain)
+                        for_each_context(priv, ctx)
+                                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+                unsigned long flags;
+
+                ch_info = iwl_get_channel_info(priv, channel->band,
+                                               channel->hw_value);
+                if (!is_channel_valid(ch_info)) {
+                        IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
+                        ret = -EINVAL;
+                        goto out;
+                }
+
+                spin_lock_irqsave(&priv->lock, flags);
+
+                for_each_context(priv, ctx) {
+                        /* Configure HT40 channels */
+                        if (ctx->ht.enabled != conf_is_ht(conf)) {
+                                ctx->ht.enabled = conf_is_ht(conf);
+                                ht_changed[ctx->ctxid] = true;
+                        }
+
+                        if (ctx->ht.enabled) {
+                                if (conf_is_ht40_minus(conf)) {
+                                        ctx->ht.extension_chan_offset =
+                                                IEEE80211_HT_PARAM_CHA_SEC_BELOW;
+                                        ctx->ht.is_40mhz = true;
+                                } else if (conf_is_ht40_plus(conf)) {
+                                        ctx->ht.extension_chan_offset =
+                                                IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
+                                        ctx->ht.is_40mhz = true;
+                                } else {
+                                        ctx->ht.extension_chan_offset =
+                                                IEEE80211_HT_PARAM_CHA_SEC_NONE;
+                                        ctx->ht.is_40mhz = false;
+                                }
+                        } else
+                                ctx->ht.is_40mhz = false;
+
+                        /*
+                         * Default to no protection. Protection mode will
+                         * later be set from BSS config in iwl_ht_conf
+                         */
+                        ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
+
+                        /* if we are switching from ht to 2.4 clear flags
+                         * from any ht related info since 2.4 does not
+                         * support ht */
+                        if (le16_to_cpu(ctx->staging.channel) !=
+                            channel->hw_value)
+                                ctx->staging.flags = 0;
+
+                        iwl_set_rxon_channel(priv, channel, ctx);
+                        iwl_set_rxon_ht(priv, &priv->current_ht_config);
+
+                        iwl_set_flags_for_band(priv, ctx, channel->band,
+                                               ctx->vif);
+                }
+
+                spin_unlock_irqrestore(&priv->lock, flags);
+
+                iwl_update_bcast_stations(priv);
+
+                /*
+                 * The list of supported rates and rate mask can be different
+                 * for each band; since the band may have changed, reset
+                 * the rate mask to what mac80211 lists.
+                 */
+                iwl_set_rate(priv);
+        }
+
+        if (changed & (IEEE80211_CONF_CHANGE_PS |
+                        IEEE80211_CONF_CHANGE_IDLE)) {
+                ret = iwl_power_update_mode(priv, false);
+                if (ret)
+                        IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
+                        priv->tx_power_user_lmt, conf->power_level);
+
+                iwl_set_tx_power(priv, conf->power_level, false);
+        }
+
+        for_each_context(priv, ctx) {
+                if (!memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
+                        continue;
+                iwlagn_commit_rxon(priv, ctx);
+                if (ht_changed[ctx->ctxid])
+                        iwlagn_update_qos(priv, ctx);
+        }
+ out:
+        mutex_unlock(&priv->mutex);
+        return ret;
+}
+
+static void iwlagn_check_needed_chains(struct iwl_priv *priv,
+                                       struct iwl_rxon_context *ctx,
+                                       struct ieee80211_bss_conf *bss_conf)
+{
+        struct ieee80211_vif *vif = ctx->vif;
+        struct iwl_rxon_context *tmp;
+        struct ieee80211_sta *sta;
+        struct iwl_ht_config *ht_conf = &priv->current_ht_config;
+        bool need_multiple;
+
+        lockdep_assert_held(&priv->mutex);
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_STATION:
+                rcu_read_lock();
+                sta = ieee80211_find_sta(vif, bss_conf->bssid);
+                if (sta) {
+                        struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
+                        int maxstreams;
+
+                        maxstreams = (ht_cap->mcs.tx_params &
+                                      IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
+                                        >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
+                        maxstreams += 1;
+
+                        need_multiple = true;
+
+                        if ((ht_cap->mcs.rx_mask[1] == 0) &&
+                            (ht_cap->mcs.rx_mask[2] == 0))
+                                need_multiple = false;
+                        if (maxstreams <= 1)
+                                need_multiple = false;
+                } else {
+                        /*
+                         * If at all, this can only happen through a race
+                         * when the AP disconnects us while we're still
+                         * setting up the connection, in that case mac80211
+                         * will soon tell us about that.
+                         */
+                        need_multiple = false;
+                }
+                rcu_read_unlock();
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                /* currently */
+                need_multiple = false;
+                break;
+        default:
+                /* only AP really */
+                need_multiple = true;
+                break;
+        }
+
+        ctx->ht_need_multiple_chains = need_multiple;
+
+        if (!need_multiple) {
+                /* check all contexts */
+                for_each_context(priv, tmp) {
+                        if (!tmp->vif)
+                                continue;
+                        if (tmp->ht_need_multiple_chains) {
+                                need_multiple = true;
+                                break;
+                        }
+                }
+        }
+
+        ht_conf->single_chain_sufficient = !need_multiple;
+}
+
+void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
+                             struct ieee80211_vif *vif,
+                             struct ieee80211_bss_conf *bss_conf,
+                             u32 changes)
+{
+        struct iwl_priv *priv = hw->priv;
+        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
+        int ret;
+        bool force = false;
+
+        mutex_lock(&priv->mutex);
+
+        if (unlikely(!iwl_is_ready(priv))) {
+                IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
+                mutex_unlock(&priv->mutex);
+                return;
+        }
+
+        if (unlikely(!ctx->vif)) {
+                IWL_DEBUG_MAC80211(priv, "leave - vif is NULL\n");
+                mutex_unlock(&priv->mutex);
+                return;
+        }
+
+        if (changes & BSS_CHANGED_BEACON_INT)
+                force = true;
+
+        if (changes & BSS_CHANGED_QOS) {
+                ctx->qos_data.qos_active = bss_conf->qos;
+                iwlagn_update_qos(priv, ctx);
+        }
+
+        ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
+        if (vif->bss_conf.use_short_preamble)
+                ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
+        else
+                ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
+
+        if (changes & BSS_CHANGED_ASSOC) {
+                if (bss_conf->assoc) {
+                        iwl_led_associate(priv);
+                        priv->timestamp = bss_conf->timestamp;
+                        ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
+                } else {
+                        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+                        iwl_led_disassociate(priv);
+                }
+        }
+
+        if (ctx->ht.enabled) {
+                ctx->ht.protection = bss_conf->ht_operation_mode &
+                                        IEEE80211_HT_OP_MODE_PROTECTION;
+                ctx->ht.non_gf_sta_present = !!(bss_conf->ht_operation_mode &
+                                        IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
+                iwlagn_check_needed_chains(priv, ctx, bss_conf);
+                iwl_set_rxon_ht(priv, &priv->current_ht_config);
+        }
+
+        if (priv->cfg->ops->hcmd->set_rxon_chain)
+                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
+
+        if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
+                ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
+        else
+                ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
+
+        if (bss_conf->use_cts_prot)
+                ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
+        else
+                ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
+
+        memcpy(ctx->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
+
+        if (vif->type == NL80211_IFTYPE_AP ||
+            vif->type == NL80211_IFTYPE_ADHOC) {
+                if (vif->bss_conf.enable_beacon) {
+                        ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
+                        priv->beacon_ctx = ctx;
+                } else {
+                        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+                        priv->beacon_ctx = NULL;
+                }
+        }
+
+        if (force || memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
+                iwlagn_commit_rxon(priv, ctx);
+
+        if (changes & BSS_CHANGED_ASSOC && bss_conf->assoc) {
+                /*
+                 * The chain noise calibration will enable PM upon
+                 * completion. If calibration has already been run
+                 * then we need to enable power management here.
+                 */
+                if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
+                        iwl_power_update_mode(priv, false);
+
+                /* Enable RX differential gain and sensitivity calibrations */
+                iwl_chain_noise_reset(priv);
+                priv->start_calib = 1;
+        }
+
+        if (changes & BSS_CHANGED_IBSS) {
+                ret = iwlagn_manage_ibss_station(priv, vif,
+                                                 bss_conf->ibss_joined);
+                if (ret)
+                        IWL_ERR(priv, "failed to %s IBSS station %pM\n",
+                                bss_conf->ibss_joined ? "add" : "remove",
+                                bss_conf->bssid);
+        }
+
+        if (changes & BSS_CHANGED_BEACON && vif->type == NL80211_IFTYPE_ADHOC &&
+            priv->beacon_ctx) {
+                if (iwlagn_update_beacon(priv, vif))
+                        IWL_ERR(priv, "Error sending IBSS beacon\n");
+        }
+
+        mutex_unlock(&priv->mutex);
+}
+
+void iwlagn_post_scan(struct iwl_priv *priv)
+{
+        struct iwl_rxon_context *ctx;
+
+        /*
+         * Since setting the RXON may have been deferred while
+         * performing the scan, fire one off if needed
+         */
+        for_each_context(priv, ctx)
+                if (memcmp(&ctx->staging, &ctx->active, sizeof(ctx->staging)))
+                        iwlagn_commit_rxon(priv, ctx);
+
+        if (priv->cfg->ops->hcmd->set_pan_params)
+                priv->cfg->ops->hcmd->set_pan_params(priv);
+}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-sta.c b/drivers/net/wireless/iwlwifi/iwl-agn-sta.c
index 35a30d2e0734..35f085ac336b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-sta.c
@@ -684,7 +684,7 @@ int iwl_sta_rx_agg_stop(struct iwl_priv *priv, struct ieee80211_sta *sta,
         return iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
 }
 
-void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
+static void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
 {
         unsigned long flags;
 
@@ -714,3 +714,33 @@ void iwl_sta_modify_sleep_tx_count(struct iwl_priv *priv, int sta_id, int cnt)
         spin_unlock_irqrestore(&priv->sta_lock, flags);
 
 }
+
+void iwlagn_mac_sta_notify(struct ieee80211_hw *hw,
+                           struct ieee80211_vif *vif,
+                           enum sta_notify_cmd cmd,
+                           struct ieee80211_sta *sta)
+{
+        struct iwl_priv *priv = hw->priv;
+        struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
+        int sta_id;
+
+        switch (cmd) {
+        case STA_NOTIFY_SLEEP:
+                WARN_ON(!sta_priv->client);
+                sta_priv->asleep = true;
+                if (atomic_read(&sta_priv->pending_frames) > 0)
+                        ieee80211_sta_block_awake(hw, sta, true);
+                break;
+        case STA_NOTIFY_AWAKE:
+                WARN_ON(!sta_priv->client);
+                if (!sta_priv->asleep)
+                        break;
+                sta_priv->asleep = false;
+                sta_id = iwl_sta_id(sta);
+                if (sta_id != IWL_INVALID_STATION)
+                        iwl_sta_modify_ps_wake(priv, sta_id);
+                break;
+        default:
+                break;
+        }
+}
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
index 2b078a995729..24a11b8f73bc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-tx.c
@@ -67,8 +67,14 @@
  */
 
 static const u8 tid_to_ac[] = {
-        /* this matches the mac80211 numbers */
-        2, 3, 3, 2, 1, 1, 0, 0
+        IEEE80211_AC_BE,
+        IEEE80211_AC_BK,
+        IEEE80211_AC_BK,
+        IEEE80211_AC_BE,
+        IEEE80211_AC_VI,
+        IEEE80211_AC_VI,
+        IEEE80211_AC_VO,
+        IEEE80211_AC_VO
 };
 
 static inline int get_ac_from_tid(u16 tid)
@@ -518,11 +524,11 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
         struct iwl_cmd_meta *out_meta;
         struct iwl_tx_cmd *tx_cmd;
         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
-        int swq_id, txq_id;
+        int txq_id;
         dma_addr_t phys_addr;
         dma_addr_t txcmd_phys;
         dma_addr_t scratch_phys;
-        u16 len, len_org, firstlen, secondlen;
+        u16 len, firstlen, secondlen;
         u16 seq_number = 0;
         __le16 fc;
         u8 hdr_len;
@@ -531,6 +537,7 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
         u8 tid = 0;
         u8 *qc = NULL;
         unsigned long flags;
+        bool is_agg = false;
 
         if (info->control.vif)
                 ctx = iwl_rxon_ctx_from_vif(info->control.vif);
@@ -567,8 +574,8 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
         if (sta)
                 sta_priv = (void *)sta->drv_priv;
 
-        if (sta_priv && sta_priv->asleep) {
-                WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
+        if (sta_priv && sta_priv->asleep &&
+            (info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE)) {
                 /*
                  * This sends an asynchronous command to the device,
                  * but we can rely on it being processed before the
@@ -616,11 +623,11 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
                 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
                     priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
                         txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
+                        is_agg = true;
                 }
         }
 
         txq = &priv->txq[txq_id];
-        swq_id = txq->swq_id;
         q = &txq->q;
 
         if (unlikely(iwl_queue_space(q) < q->high_mark)) {
@@ -687,30 +694,23 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
          */
         len = sizeof(struct iwl_tx_cmd) +
                 sizeof(struct iwl_cmd_header) + hdr_len;
-
-        len_org = len;
-        firstlen = len = (len + 3) & ~3;
-
-        if (len_org != len)
-                len_org = 1;
-        else
-                len_org = 0;
+        firstlen = (len + 3) & ~3;
 
         /* Tell NIC about any 2-byte padding after MAC header */
-        if (len_org)
+        if (firstlen != len)
                 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
 
         /* Physical address of this Tx command's header (not MAC header!),
          * within command buffer array. */
         txcmd_phys = pci_map_single(priv->pci_dev,
-                                    &out_cmd->hdr, len,
+                                    &out_cmd->hdr, firstlen,
                                     PCI_DMA_BIDIRECTIONAL);
         dma_unmap_addr_set(out_meta, mapping, txcmd_phys);
-        dma_unmap_len_set(out_meta, len, len);
+        dma_unmap_len_set(out_meta, len, firstlen);
         /* Add buffer containing Tx command and MAC(!) header to TFD's
          * first entry */
         priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
-                                                   txcmd_phys, len, 1, 0);
+                                                   txcmd_phys, firstlen, 1, 0);
 
         if (!ieee80211_has_morefrags(hdr->frame_control)) {
                 txq->need_update = 1;
@@ -721,23 +721,21 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
 
         /* Set up TFD's 2nd entry to point directly to remainder of skb,
          * if any (802.11 null frames have no payload). */
-        secondlen = len = skb->len - hdr_len;
-        if (len) {
+        secondlen = skb->len - hdr_len;
+        if (secondlen > 0) {
                 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
-                                           len, PCI_DMA_TODEVICE);
+                                           secondlen, PCI_DMA_TODEVICE);
                 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
-                                                           phys_addr, len,
+                                                           phys_addr, secondlen,
                                                            0, 0);
         }
 
         scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
                                 offsetof(struct iwl_tx_cmd, scratch);
 
-        len = sizeof(struct iwl_tx_cmd) +
-                sizeof(struct iwl_cmd_header) + hdr_len;
         /* take back ownership of DMA buffer to enable update */
         pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
-                                    len, PCI_DMA_BIDIRECTIONAL);
+                                    firstlen, PCI_DMA_BIDIRECTIONAL);
         tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
         tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
 
@@ -753,7 +751,7 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
                                                      le16_to_cpu(tx_cmd->len));
 
         pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
-                                       len, PCI_DMA_BIDIRECTIONAL);
+                                       firstlen, PCI_DMA_BIDIRECTIONAL);
 
         trace_iwlwifi_dev_tx(priv,
                              &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
@@ -773,8 +771,14 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
          * whether or not we should update the write pointer.
          */
 
-        /* avoid atomic ops if it isn't an associated client */
-        if (sta_priv && sta_priv->client)
+        /*
+         * Avoid atomic ops if it isn't an associated client.
+         * Also, if this is a packet for aggregation, don't
+         * increase the counter because the ucode will stop
+         * aggregation queues when their respective station
+         * goes to sleep.
+         */
+        if (sta_priv && sta_priv->client && !is_agg)
                 atomic_inc(&sta_priv->pending_frames);
 
         if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
@@ -784,7 +788,7 @@ int iwlagn_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
                         iwl_txq_update_write_ptr(priv, txq);
                         spin_unlock_irqrestore(&priv->lock, flags);
                 } else {
-                        iwl_stop_queue(priv, txq->swq_id);
+                        iwl_stop_queue(priv, txq);
                 }
         }
 
@@ -1013,7 +1017,7 @@ int iwlagn_tx_agg_start(struct iwl_priv *priv, struct ieee80211_vif *vif,
         tid_data = &priv->stations[sta_id].tid[tid];
         *ssn = SEQ_TO_SN(tid_data->seq_number);
         tid_data->agg.txq_id = txq_id;
-        priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(get_ac_from_tid(tid), txq_id);
+        iwl_set_swq_id(&priv->txq[txq_id], get_ac_from_tid(tid), txq_id);
         spin_unlock_irqrestore(&priv->sta_lock, flags);
 
         ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
@@ -1153,14 +1157,15 @@ int iwlagn_txq_check_empty(struct iwl_priv *priv,
         return 0;
 }
 
-static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info)
+static void iwlagn_non_agg_tx_status(struct iwl_priv *priv,
+                                     struct iwl_rxon_context *ctx,
+                                     const u8 *addr1)
 {
-        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
         struct ieee80211_sta *sta;
         struct iwl_station_priv *sta_priv;
 
         rcu_read_lock();
-        sta = ieee80211_find_sta(tx_info->ctx->vif, hdr->addr1);
+        sta = ieee80211_find_sta(ctx->vif, addr1);
         if (sta) {
                 sta_priv = (void *)sta->drv_priv;
                 /* avoid atomic ops if this isn't a client */
@@ -1169,6 +1174,15 @@ static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info)
                         ieee80211_sta_block_awake(priv->hw, sta, false);
         }
         rcu_read_unlock();
+}
+
+static void iwlagn_tx_status(struct iwl_priv *priv, struct iwl_tx_info *tx_info,
+                             bool is_agg)
+{
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) tx_info->skb->data;
+
+        if (!is_agg)
+                iwlagn_non_agg_tx_status(priv, tx_info->ctx, hdr->addr1);
 
         ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
 }
@@ -1193,7 +1207,8 @@ int iwlagn_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
              q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 
                 tx_info = &txq->txb[txq->q.read_ptr];
-                iwlagn_tx_status(priv, tx_info);
+                iwlagn_tx_status(priv, tx_info,
+                                 txq_id >= IWLAGN_FIRST_AMPDU_QUEUE);
 
                 hdr = (struct ieee80211_hdr *)tx_info->skb->data;
                 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
@@ -1222,7 +1237,6 @@ static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
         int i, sh, ack;
         u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
         u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
-        u64 bitmap, sent_bitmap;
         int successes = 0;
         struct ieee80211_tx_info *info;
 
@@ -1241,40 +1255,68 @@ static int iwlagn_tx_status_reply_compressed_ba(struct iwl_priv *priv,
         if (sh < 0) /* tbw something is wrong with indices */
                 sh += 0x100;
 
-        /* don't use 64-bit values for now */
-        bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
-
         if (agg->frame_count > (64 - sh)) {
                 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
                 return -1;
         }
+        if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
+                /*
+                 * sent and ack information provided by uCode
+                 * use it instead of figure out ourself
+                 */
+                if (ba_resp->txed_2_done > ba_resp->txed) {
+                        IWL_DEBUG_TX_REPLY(priv,
+                                "bogus sent(%d) and ack(%d) count\n",
+                                ba_resp->txed, ba_resp->txed_2_done);
+                        /*
+                         * set txed_2_done = txed,
+                         * so it won't impact rate scale
+                         */
+                        ba_resp->txed = ba_resp->txed_2_done;
+                }
+                IWL_DEBUG_HT(priv, "agg frames sent:%d, acked:%d\n",
+                                ba_resp->txed, ba_resp->txed_2_done);
+        } else {
+                u64 bitmap, sent_bitmap;
+
+                /* don't use 64-bit values for now */
+                bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
+
+                /* check for success or failure according to the
+                 * transmitted bitmap and block-ack bitmap */
+                sent_bitmap = bitmap & agg->bitmap;
+
+                /* For each frame attempted in aggregation,
+                 * update driver's record of tx frame's status. */
+                i = 0;
+                while (sent_bitmap) {
+                        ack = sent_bitmap & 1ULL;
+                        successes += ack;
+                        IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
+                                ack ? "ACK" : "NACK", i,
+                                (agg->start_idx + i) & 0xff,
+                                agg->start_idx + i);
+                        sent_bitmap >>= 1;
+                        ++i;
+                }
 
-        /* check for success or failure according to the
-         * transmitted bitmap and block-ack bitmap */
-        sent_bitmap = bitmap & agg->bitmap;
-
-        /* For each frame attempted in aggregation,
-         * update driver's record of tx frame's status. */
-        i = 0;
-        while (sent_bitmap) {
-                ack = sent_bitmap & 1ULL;
-                successes += ack;
-                IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
-                        ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
-                        agg->start_idx + i);
-                sent_bitmap >>= 1;
-                ++i;
+                IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n",
+                                   (unsigned long long)bitmap);
         }
 
         info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb);
         memset(&info->status, 0, sizeof(info->status));
         info->flags |= IEEE80211_TX_STAT_ACK;
         info->flags |= IEEE80211_TX_STAT_AMPDU;
-        info->status.ampdu_ack_len = successes;
-        info->status.ampdu_len = agg->frame_count;
-        iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
+        if (!priv->cfg->base_params->no_agg_framecnt_info && ba_resp->txed) {
+                info->status.ampdu_ack_len = ba_resp->txed_2_done;
+                info->status.ampdu_len = ba_resp->txed;
 
-        IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
+        } else {
+                info->status.ampdu_ack_len = successes;
+                info->status.ampdu_len = agg->frame_count;
+        }
+        iwlagn_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
 
         return 0;
 }
@@ -1385,7 +1427,7 @@ void iwlagn_rx_reply_compressed_ba(struct iwl_priv *priv,
                 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
                     priv->mac80211_registered &&
                     (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
-                        iwl_wake_queue(priv, txq->swq_id);
+                        iwl_wake_queue(priv, txq);
 
                 iwlagn_txq_check_empty(priv, sta_id, tid, scd_flow);
         }
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
index 703621107dac..24dabcd2a36c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c
@@ -40,30 +40,36 @@
 #include "iwl-agn.h"
 #include "iwl-agn-calib.h"
 
-static const s8 iwlagn_default_queue_to_tx_fifo[] = {
-        IWL_TX_FIFO_VO,
-        IWL_TX_FIFO_VI,
-        IWL_TX_FIFO_BE,
-        IWL_TX_FIFO_BK,
-        IWLAGN_CMD_FIFO_NUM,
-        IWL_TX_FIFO_UNUSED,
-        IWL_TX_FIFO_UNUSED,
-        IWL_TX_FIFO_UNUSED,
-        IWL_TX_FIFO_UNUSED,
-        IWL_TX_FIFO_UNUSED,
+#define IWL_AC_UNSET -1
+
+struct queue_to_fifo_ac {
+        s8 fifo, ac;
+};
+
+static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
+        { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
+        { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
+        { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
+        { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
+        { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
+        { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
+        { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
+        { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
+        { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
+        { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
 };
 
-static const s8 iwlagn_ipan_queue_to_tx_fifo[] = {
-        IWL_TX_FIFO_VO,
-        IWL_TX_FIFO_VI,
-        IWL_TX_FIFO_BE,
-        IWL_TX_FIFO_BK,
-        IWL_TX_FIFO_BK_IPAN,
-        IWL_TX_FIFO_BE_IPAN,
-        IWL_TX_FIFO_VI_IPAN,
-        IWL_TX_FIFO_VO_IPAN,
-        IWL_TX_FIFO_BE_IPAN,
-        IWLAGN_CMD_FIFO_NUM,
+static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
+        { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
+        { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
+        { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
+        { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
+        { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
+        { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
+        { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
+        { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
+        { IWL_TX_FIFO_BE_IPAN, 2, },
+        { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
 };
 
 static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
@@ -429,7 +435,7 @@ void iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
 
 int iwlagn_alive_notify(struct iwl_priv *priv)
 {
-        const s8 *queues;
+        const struct queue_to_fifo_ac *queue_to_fifo;
         u32 a;
         unsigned long flags;
         int i, chan;
@@ -492,9 +498,9 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
 
         /* map queues to FIFOs */
         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
-                queues = iwlagn_ipan_queue_to_tx_fifo;
+                queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
         else
-                queues = iwlagn_default_queue_to_tx_fifo;
+                queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 
         iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
 
@@ -510,18 +516,25 @@ int iwlagn_alive_notify(struct iwl_priv *priv)
         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
 
         for (i = 0; i < 10; i++) {
-                int ac = queues[i];
+                int fifo = queue_to_fifo[i].fifo;
+                int ac = queue_to_fifo[i].ac;
 
                 iwl_txq_ctx_activate(priv, i);
 
-                if (ac == IWL_TX_FIFO_UNUSED)
+                if (fifo == IWL_TX_FIFO_UNUSED)
                         continue;
 
-                iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
+                if (ac != IWL_AC_UNSET)
+                        iwl_set_swq_id(&priv->txq[i], ac, i);
+                iwlagn_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
         }
 
         spin_unlock_irqrestore(&priv->lock, flags);
 
+        /* Enable L1-Active */
+        iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
+                          APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
+
         iwlagn_send_wimax_coex(priv);
 
         iwlagn_set_Xtal_calib(priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c
index 9b912c0b6e59..36335b1b54d4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.c
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c
@@ -90,170 +90,6 @@ MODULE_ALIAS("iwl4965");
 static int iwlagn_ant_coupling;
 static bool iwlagn_bt_ch_announce = 1;
 
-/**
- * iwlagn_commit_rxon - commit staging_rxon to hardware
- *
- * The RXON command in staging_rxon is committed to the hardware and
- * the active_rxon structure is updated with the new data.  This
- * function correctly transitions out of the RXON_ASSOC_MSK state if
- * a HW tune is required based on the RXON structure changes.
- */
-int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
-{
-        /* cast away the const for active_rxon in this function */
-        struct iwl_rxon_cmd *active_rxon = (void *)&ctx->active;
-        int ret;
-        bool new_assoc =
-                !!(ctx->staging.filter_flags & RXON_FILTER_ASSOC_MSK);
-        bool old_assoc = !!(ctx->active.filter_flags & RXON_FILTER_ASSOC_MSK);
-
-        if (!iwl_is_alive(priv))
-                return -EBUSY;
-
-        if (!ctx->is_active)
-                return 0;
-
-        /* always get timestamp with Rx frame */
-        ctx->staging.flags |= RXON_FLG_TSF2HOST_MSK;
-
-        ret = iwl_check_rxon_cmd(priv, ctx);
-        if (ret) {
-                IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
-                return -EINVAL;
-        }
-
-        /*
-         * receive commit_rxon request
-         * abort any previous channel switch if still in process
-         */
-        if (priv->switch_rxon.switch_in_progress &&
-            (priv->switch_rxon.channel != ctx->staging.channel)) {
-                IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
-                      le16_to_cpu(priv->switch_rxon.channel));
-                iwl_chswitch_done(priv, false);
-        }
-
-        /* If we don't need to send a full RXON, we can use
-         * iwl_rxon_assoc_cmd which is used to reconfigure filter
-         * and other flags for the current radio configuration. */
-        if (!iwl_full_rxon_required(priv, ctx)) {
-                ret = iwl_send_rxon_assoc(priv, ctx);
-                if (ret) {
-                        IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
-                        return ret;
-                }
-
-                memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
-                iwl_print_rx_config_cmd(priv, ctx);
-                return 0;
-        }
-
-        /* If we are currently associated and the new config requires
-         * an RXON_ASSOC and the new config wants the associated mask enabled,
-         * we must clear the associated from the active configuration
-         * before we apply the new config */
-        if (iwl_is_associated_ctx(ctx) && new_assoc) {
-                IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
-                active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
-
-                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
-                                       sizeof(struct iwl_rxon_cmd),
-                                       active_rxon);
-
-                /* If the mask clearing failed then we set
-                 * active_rxon back to what it was previously */
-                if (ret) {
-                        active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
-                        IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
-                        return ret;
-                }
-                iwl_clear_ucode_stations(priv, ctx);
-                iwl_restore_stations(priv, ctx);
-                ret = iwl_restore_default_wep_keys(priv, ctx);
-                if (ret) {
-                        IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
-                        return ret;
-                }
-        }
-
-        IWL_DEBUG_INFO(priv, "Sending RXON\n"
-                       "* with%s RXON_FILTER_ASSOC_MSK\n"
-                       "* channel = %d\n"
-                       "* bssid = %pM\n",
-                       (new_assoc ? "" : "out"),
-                       le16_to_cpu(ctx->staging.channel),
-                       ctx->staging.bssid_addr);
-
-        iwl_set_rxon_hwcrypto(priv, ctx, !priv->cfg->mod_params->sw_crypto);
-
-        if (!old_assoc) {
-                /*
-                 * First of all, before setting associated, we need to
-                 * send RXON timing so the device knows about the DTIM
-                 * period and other timing values
-                 */
-                ret = iwl_send_rxon_timing(priv, ctx);
-                if (ret) {
-                        IWL_ERR(priv, "Error setting RXON timing!\n");
-                        return ret;
-                }
-        }
-
-        if (priv->cfg->ops->hcmd->set_pan_params) {
-                ret = priv->cfg->ops->hcmd->set_pan_params(priv);
-                if (ret)
-                        return ret;
-        }
-
-        /* Apply the new configuration
-         * RXON unassoc clears the station table in uCode so restoration of
-         * stations is needed after it (the RXON command) completes
-         */
-        if (!new_assoc) {
-                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
-                              sizeof(struct iwl_rxon_cmd), &ctx->staging);
-                if (ret) {
-                        IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
-                        return ret;
-                }
-                IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
-                memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
-                iwl_clear_ucode_stations(priv, ctx);
-                iwl_restore_stations(priv, ctx);
-                ret = iwl_restore_default_wep_keys(priv, ctx);
-                if (ret) {
-                        IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
-                        return ret;
-                }
-        }
-        if (new_assoc) {
-                priv->start_calib = 0;
-                /* Apply the new configuration
-                 * RXON assoc doesn't clear the station table in uCode,
-                 */
-                ret = iwl_send_cmd_pdu(priv, ctx->rxon_cmd,
-                              sizeof(struct iwl_rxon_cmd), &ctx->staging);
-                if (ret) {
-                        IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
-                        return ret;
-                }
-                memcpy(active_rxon, &ctx->staging, sizeof(*active_rxon));
-        }
-        iwl_print_rx_config_cmd(priv, ctx);
-
-        iwl_init_sensitivity(priv);
-
-        /* If we issue a new RXON command which required a tune then we must
-         * send a new TXPOWER command or we won't be able to Tx any frames */
-        ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
-        if (ret) {
-                IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
-                return ret;
-        }
-
-        return 0;
-}
-
 void iwl_update_chain_flags(struct iwl_priv *priv)
 {
         struct iwl_rxon_context *ctx;
@@ -261,7 +97,8 @@ void iwl_update_chain_flags(struct iwl_priv *priv)
         if (priv->cfg->ops->hcmd->set_rxon_chain) {
                 for_each_context(priv, ctx) {
                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
-                        iwlcore_commit_rxon(priv, ctx);
+                        if (ctx->active.rx_chain != ctx->staging.rx_chain)
+                                iwlcore_commit_rxon(priv, ctx);
                 }
         }
 }
@@ -411,7 +248,8 @@ static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 
         return sizeof(*tx_beacon_cmd) + frame_size;
 }
-static int iwl_send_beacon_cmd(struct iwl_priv *priv)
+
+int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 {
         struct iwl_frame *frame;
         unsigned int frame_size;
@@ -661,7 +499,7 @@ static void iwl_bg_beacon_update(struct work_struct *work)
 
         priv->beacon_skb = beacon;
 
-        iwl_send_beacon_cmd(priv);
+        iwlagn_send_beacon_cmd(priv);
  out:
         mutex_unlock(&priv->mutex);
 }
@@ -2664,7 +2502,7 @@ int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
                 return pos;
         }
 
-        /* enable/disable bt channel announcement */
+        /* enable/disable bt channel inhibition */
         priv->bt_ch_announce = iwlagn_bt_ch_announce;
 
 #ifdef CONFIG_IWLWIFI_DEBUG
@@ -2816,13 +2654,8 @@ static void iwl_alive_start(struct iwl_priv *priv)
         /* After the ALIVE response, we can send host commands to the uCode */
         set_bit(STATUS_ALIVE, &priv->status);
 
-        if (priv->cfg->ops->lib->recover_from_tx_stall) {
-                /* Enable timer to monitor the driver queues */
-                mod_timer(&priv->monitor_recover,
-                        jiffies +
-                        msecs_to_jiffies(
-                          priv->cfg->base_params->monitor_recover_period));
-        }
+        /* Enable watchdog to monitor the driver tx queues */
+        iwl_setup_watchdog(priv);
 
         if (iwl_is_rfkill(priv))
                 return;
@@ -2879,6 +2712,8 @@ static void iwl_alive_start(struct iwl_priv *priv)
 
         iwl_reset_run_time_calib(priv);
 
+        set_bit(STATUS_READY, &priv->status);
+
         /* Configure the adapter for unassociated operation */
         iwlcore_commit_rxon(priv, ctx);
 
@@ -2888,7 +2723,6 @@ static void iwl_alive_start(struct iwl_priv *priv)
         iwl_leds_init(priv);
 
         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
-        set_bit(STATUS_READY, &priv->status);
         wake_up_interruptible(&priv->wait_command_queue);
 
         iwl_power_update_mode(priv, true);
@@ -2916,8 +2750,7 @@ static void __iwl_down(struct iwl_priv *priv)
 
         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
          * to prevent rearm timer */
-        if (priv->cfg->ops->lib->recover_from_tx_stall)
-                del_timer_sync(&priv->monitor_recover);
+        del_timer_sync(&priv->watchdog);
 
         iwl_clear_ucode_stations(priv, NULL);
         iwl_dealloc_bcast_stations(priv);
@@ -2978,7 +2811,8 @@ static void __iwl_down(struct iwl_priv *priv)
                                 STATUS_EXIT_PENDING;
 
         /* device going down, Stop using ICT table */
-        iwl_disable_ict(priv);
+        if (priv->cfg->ops->lib->isr_ops.disable)
+                priv->cfg->ops->lib->isr_ops.disable(priv);
 
         iwlagn_txq_ctx_stop(priv);
         iwlagn_rxq_stop(priv);
@@ -3201,7 +3035,8 @@ static void iwl_bg_alive_start(struct work_struct *data)
                 return;
 
         /* enable dram interrupt */
-        iwl_reset_ict(priv);
+        if (priv->cfg->ops->lib->isr_ops.reset)
+                priv->cfg->ops->lib->isr_ops.reset(priv);
 
         mutex_lock(&priv->mutex);
         iwl_alive_start(priv);
@@ -3309,92 +3144,6 @@ static void iwl_bg_rx_replenish(struct work_struct *data)
         mutex_unlock(&priv->mutex);
 }
 
-#define IWL_DELAY_NEXT_SCAN (HZ*2)
-
-void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
-{
-        struct iwl_rxon_context *ctx;
-        struct ieee80211_conf *conf = NULL;
-        int ret = 0;
-
-        if (!vif || !priv->is_open)
-                return;
-
-        ctx = iwl_rxon_ctx_from_vif(vif);
-
-        if (vif->type == NL80211_IFTYPE_AP) {
-                IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
-                return;
-        }
-
-        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
-                return;
-
-        iwl_scan_cancel_timeout(priv, 200);
-
-        conf = ieee80211_get_hw_conf(priv->hw);
-
-        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
-        iwlcore_commit_rxon(priv, ctx);
-
-        ret = iwl_send_rxon_timing(priv, ctx);
-        if (ret)
-                IWL_WARN(priv, "RXON timing - "
-                            "Attempting to continue.\n");
-
-        ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
-
-        iwl_set_rxon_ht(priv, &priv->current_ht_config);
-
-        if (priv->cfg->ops->hcmd->set_rxon_chain)
-                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
-
-        ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
-
-        IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
-                        vif->bss_conf.aid, vif->bss_conf.beacon_int);
-
-        if (vif->bss_conf.use_short_preamble)
-                ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
-        else
-                ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
-
-        if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
-                if (vif->bss_conf.use_short_slot)
-                        ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
-                else
-                        ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
-        }
-
-        iwlcore_commit_rxon(priv, ctx);
-
-        IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
-                        vif->bss_conf.aid, ctx->active.bssid_addr);
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_STATION:
-                break;
-        case NL80211_IFTYPE_ADHOC:
-                iwl_send_beacon_cmd(priv);
-                break;
-        default:
-                IWL_ERR(priv, "%s Should not be called in %d mode\n",
-                          __func__, vif->type);
-                break;
-        }
-
-        /* the chain noise calibration will enabled PM upon completion
-         * If chain noise has already been run, then we need to enable
-         * power management here */
-        if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
-                iwl_power_update_mode(priv, false);
-
-        /* Enable Rx differential gain and sensitivity calibrations */
-        iwl_chain_noise_reset(priv);
-        priv->start_calib = 1;
-
-}
-
 /*****************************************************************************
  *
  * mac80211 entry point functions
@@ -3420,7 +3169,8 @@ static int iwl_mac_setup_register(struct iwl_priv *priv,
         hw->flags = IEEE80211_HW_SIGNAL_DBM |
                     IEEE80211_HW_AMPDU_AGGREGATION |
                     IEEE80211_HW_NEED_DTIM_PERIOD |
-                    IEEE80211_HW_SPECTRUM_MGMT;
+                    IEEE80211_HW_SPECTRUM_MGMT |
+                    IEEE80211_HW_REPORTS_TX_ACK_STATUS;
 
         if (!priv->cfg->base_params->broken_powersave)
                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
@@ -3474,7 +3224,7 @@ static int iwl_mac_setup_register(struct iwl_priv *priv,
 }
 
 
-static int iwl_mac_start(struct ieee80211_hw *hw)
+int iwlagn_mac_start(struct ieee80211_hw *hw)
 {
         struct iwl_priv *priv = hw->priv;
         int ret;
@@ -3515,7 +3265,7 @@ out:
         return 0;
 }
 
-static void iwl_mac_stop(struct ieee80211_hw *hw)
+void iwlagn_mac_stop(struct ieee80211_hw *hw)
 {
         struct iwl_priv *priv = hw->priv;
 
@@ -3530,14 +3280,15 @@ static void iwl_mac_stop(struct ieee80211_hw *hw)
 
         flush_workqueue(priv->workqueue);
 
-        /* enable interrupts again in order to receive rfkill changes */
+        /* User space software may expect getting rfkill changes
+         * even if interface is down */
         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
-        iwl_enable_interrupts(priv);
+        iwl_enable_rfkill_int(priv);
 
         IWL_DEBUG_MAC80211(priv, "leave\n");
 }
 
-static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
 {
         struct iwl_priv *priv = hw->priv;
 
@@ -3553,73 +3304,12 @@ static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         return NETDEV_TX_OK;
 }
 
-void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
-{
-        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
-        int ret = 0;
-
-        lockdep_assert_held(&priv->mutex);
-
-        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
-                return;
-
-        /* The following should be done only at AP bring up */
-        if (!iwl_is_associated_ctx(ctx)) {
-
-                /* RXON - unassoc (to set timing command) */
-                ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
-                iwlcore_commit_rxon(priv, ctx);
-
-                /* RXON Timing */
-                ret = iwl_send_rxon_timing(priv, ctx);
-                if (ret)
-                        IWL_WARN(priv, "RXON timing failed - "
-                                        "Attempting to continue.\n");
-
-                /* AP has all antennas */
-                priv->chain_noise_data.active_chains =
-                        priv->hw_params.valid_rx_ant;
-                iwl_set_rxon_ht(priv, &priv->current_ht_config);
-                if (priv->cfg->ops->hcmd->set_rxon_chain)
-                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
-
-                ctx->staging.assoc_id = 0;
-
-                if (vif->bss_conf.use_short_preamble)
-                        ctx->staging.flags |=
-                                RXON_FLG_SHORT_PREAMBLE_MSK;
-                else
-                        ctx->staging.flags &=
-                                ~RXON_FLG_SHORT_PREAMBLE_MSK;
-
-                if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
-                        if (vif->bss_conf.use_short_slot)
-                                ctx->staging.flags |=
-                                        RXON_FLG_SHORT_SLOT_MSK;
-                        else
-                                ctx->staging.flags &=
-                                        ~RXON_FLG_SHORT_SLOT_MSK;
-                }
-                /* need to send beacon cmd before committing assoc RXON! */
-                iwl_send_beacon_cmd(priv);
-                /* restore RXON assoc */
-                ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
-                iwlcore_commit_rxon(priv, ctx);
-        }
-        iwl_send_beacon_cmd(priv);
-
-        /* FIXME - we need to add code here to detect a totally new
-         * configuration, reset the AP, unassoc, rxon timing, assoc,
-         * clear sta table, add BCAST sta... */
-}
-
-static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
-                                    struct ieee80211_vif *vif,
-                                    struct ieee80211_key_conf *keyconf,
-                                    struct ieee80211_sta *sta,
-                                    u32 iv32, u16 *phase1key)
+void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
+                                struct ieee80211_vif *vif,
+                                struct ieee80211_key_conf *keyconf,
+                                struct ieee80211_sta *sta,
+                                u32 iv32, u16 *phase1key)
 {
-
         struct iwl_priv *priv = hw->priv;
         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
 
@@ -3631,10 +3321,9 @@ static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
         IWL_DEBUG_MAC80211(priv, "leave\n");
 }
 
-static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
-                           struct ieee80211_vif *vif,
-                           struct ieee80211_sta *sta,
-                           struct ieee80211_key_conf *key)
+int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+                       struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                       struct ieee80211_key_conf *key)
 {
         struct iwl_priv *priv = hw->priv;
         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
@@ -3701,10 +3390,10 @@ static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
         return ret;
 }
 
-static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
-                                struct ieee80211_vif *vif,
-                                enum ieee80211_ampdu_mlme_action action,
-                                struct ieee80211_sta *sta, u16 tid, u16 *ssn)
+int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
+                            struct ieee80211_vif *vif,
+                            enum ieee80211_ampdu_mlme_action action,
+                            struct ieee80211_sta *sta, u16 tid, u16 *ssn)
 {
         struct iwl_priv *priv = hw->priv;
         int ret = -EINVAL;
@@ -3785,39 +3474,9 @@ static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
         return ret;
 }
 
-static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
-                               struct ieee80211_vif *vif,
-                               enum sta_notify_cmd cmd,
-                               struct ieee80211_sta *sta)
-{
-        struct iwl_priv *priv = hw->priv;
-        struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
-        int sta_id;
-
-        switch (cmd) {
-        case STA_NOTIFY_SLEEP:
-                WARN_ON(!sta_priv->client);
-                sta_priv->asleep = true;
-                if (atomic_read(&sta_priv->pending_frames) > 0)
-                        ieee80211_sta_block_awake(hw, sta, true);
-                break;
-        case STA_NOTIFY_AWAKE:
-                WARN_ON(!sta_priv->client);
-                if (!sta_priv->asleep)
-                        break;
-                sta_priv->asleep = false;
-                sta_id = iwl_sta_id(sta);
-                if (sta_id != IWL_INVALID_STATION)
-                        iwl_sta_modify_ps_wake(priv, sta_id);
-                break;
-        default:
-                break;
-        }
-}
-
-static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
-                              struct ieee80211_vif *vif,
-                              struct ieee80211_sta *sta)
+int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
+                       struct ieee80211_vif *vif,
+                       struct ieee80211_sta *sta)
 {
         struct iwl_priv *priv = hw->priv;
         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
@@ -3858,8 +3517,8 @@ static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
         return 0;
 }
 
-static void iwl_mac_channel_switch(struct ieee80211_hw *hw,
-                                   struct ieee80211_channel_switch *ch_switch)
+void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
+                               struct ieee80211_channel_switch *ch_switch)
 {
         struct iwl_priv *priv = hw->priv;
         const struct iwl_channel_info *ch_info;
@@ -3956,10 +3615,10 @@ out_exit:
         IWL_DEBUG_MAC80211(priv, "leave\n");
 }
 
-static void iwlagn_configure_filter(struct ieee80211_hw *hw,
-                                    unsigned int changed_flags,
-                                    unsigned int *total_flags,
-                                    u64 multicast)
+void iwlagn_configure_filter(struct ieee80211_hw *hw,
+                             unsigned int changed_flags,
+                             unsigned int *total_flags,
+                             u64 multicast)
 {
         struct iwl_priv *priv = hw->priv;
         __le32 filter_or = 0, filter_nand = 0;
@@ -3976,7 +3635,8 @@ static void iwlagn_configure_filter(struct ieee80211_hw *hw,
                         changed_flags, *total_flags);
 
         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
-        CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK);
+        /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
+        CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
 
 #undef CHK
@@ -3986,7 +3646,11 @@ static void iwlagn_configure_filter(struct ieee80211_hw *hw,
         for_each_context(priv, ctx) {
                 ctx->staging.filter_flags &= ~filter_nand;
                 ctx->staging.filter_flags |= filter_or;
-                iwlcore_commit_rxon(priv, ctx);
+
+                /*
+                 * Not committing directly because hardware can perform a scan,
+                 * but we'll eventually commit the filter flags change anyway.
+                 */
         }
 
         mutex_unlock(&priv->mutex);
@@ -4001,7 +3665,7 @@ static void iwlagn_configure_filter(struct ieee80211_hw *hw,
                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
 }
 
-static void iwl_mac_flush(struct ieee80211_hw *hw, bool drop)
+void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
 {
         struct iwl_priv *priv = hw->priv;
 
@@ -4074,12 +3738,9 @@ static void iwl_setup_deferred_work(struct iwl_priv *priv)
         priv->ucode_trace.data = (unsigned long)priv;
         priv->ucode_trace.function = iwl_bg_ucode_trace;
 
-        if (priv->cfg->ops->lib->recover_from_tx_stall) {
-                init_timer(&priv->monitor_recover);
-                priv->monitor_recover.data = (unsigned long)priv;
-                priv->monitor_recover.function =
-                        priv->cfg->ops->lib->recover_from_tx_stall;
-        }
+        init_timer(&priv->watchdog);
+        priv->watchdog.data = (unsigned long)priv;
+        priv->watchdog.function = iwl_bg_watchdog;
 
         if (!priv->cfg->base_params->use_isr_legacy)
                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
@@ -4172,13 +3833,13 @@ static int iwl_init_drv(struct iwl_priv *priv)
                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
-                priv->dynamic_agg_thresh = BT_AGG_THRESHOLD_DEF;
         }
 
         /* Set the tx_power_user_lmt to the lowest power level
          * this value will get overwritten by channel max power avg
          * from eeprom */
         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
+        priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
 
         ret = iwl_init_channel_map(priv);
         if (ret) {
@@ -4209,28 +3870,30 @@ static void iwl_uninit_drv(struct iwl_priv *priv)
         kfree(priv->scan_cmd);
 }
 
-static struct ieee80211_ops iwl_hw_ops = {
-        .tx = iwl_mac_tx,
-        .start = iwl_mac_start,
-        .stop = iwl_mac_stop,
+#ifdef CONFIG_IWL5000
+struct ieee80211_ops iwlagn_hw_ops = {
+        .tx = iwlagn_mac_tx,
+        .start = iwlagn_mac_start,
+        .stop = iwlagn_mac_stop,
         .add_interface = iwl_mac_add_interface,
         .remove_interface = iwl_mac_remove_interface,
-        .config = iwl_mac_config,
+        .change_interface = iwl_mac_change_interface,
+        .config = iwlagn_mac_config,
         .configure_filter = iwlagn_configure_filter,
-        .set_key = iwl_mac_set_key,
-        .update_tkip_key = iwl_mac_update_tkip_key,
+        .set_key = iwlagn_mac_set_key,
+        .update_tkip_key = iwlagn_mac_update_tkip_key,
         .conf_tx = iwl_mac_conf_tx,
-        .reset_tsf = iwl_mac_reset_tsf,
-        .bss_info_changed = iwl_bss_info_changed,
-        .ampdu_action = iwl_mac_ampdu_action,
+        .bss_info_changed = iwlagn_bss_info_changed,
+        .ampdu_action = iwlagn_mac_ampdu_action,
         .hw_scan = iwl_mac_hw_scan,
-        .sta_notify = iwl_mac_sta_notify,
+        .sta_notify = iwlagn_mac_sta_notify,
         .sta_add = iwlagn_mac_sta_add,
         .sta_remove = iwl_mac_sta_remove,
-        .channel_switch = iwl_mac_channel_switch,
-        .flush = iwl_mac_flush,
+        .channel_switch = iwlagn_mac_channel_switch,
+        .flush = iwlagn_mac_flush,
         .tx_last_beacon = iwl_mac_tx_last_beacon,
 };
+#endif
 
 static void iwl_hw_detect(struct iwl_priv *priv)
 {
@@ -4298,10 +3961,15 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (cfg->mod_params->disable_hw_scan) {
                 dev_printk(KERN_DEBUG, &(pdev->dev),
                         "sw scan support is deprecated\n");
-                iwl_hw_ops.hw_scan = NULL;
+#ifdef CONFIG_IWL5000
+                iwlagn_hw_ops.hw_scan = NULL;
+#endif
+#ifdef CONFIG_IWL4965
+                iwl4965_hw_ops.hw_scan = NULL;
+#endif
         }
 
-        hw = iwl_alloc_all(cfg, &iwl_hw_ops);
+        hw = iwl_alloc_all(cfg);
         if (!hw) {
                 err = -ENOMEM;
                 goto out;
@@ -4333,6 +4001,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 BIT(NL80211_IFTYPE_ADHOC);
         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
                 BIT(NL80211_IFTYPE_STATION);
+        priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
@@ -4368,8 +4037,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
                 true : false;
 
-        /* enable/disable bt channel announcement */
+        /* enable/disable bt channel inhibition */
         priv->bt_ch_announce = iwlagn_bt_ch_announce;
+        IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
+                       (priv->bt_ch_announce) ? "On" : "Off");
 
         if (iwl_alloc_traffic_mem(priv))
                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
@@ -4461,6 +4132,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         if (err)
                 goto out_free_eeprom;
 
+        err = iwl_eeprom_check_sku(priv);
+        if (err)
+                goto out_free_eeprom;
+
         /* extract MAC Address */
         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
@@ -4500,8 +4175,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         pci_enable_msi(priv->pci_dev);
 
-        iwl_alloc_isr_ict(priv);
-        err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
+        if (priv->cfg->ops->lib->isr_ops.alloc)
+                priv->cfg->ops->lib->isr_ops.alloc(priv);
+
+        err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
                           IRQF_SHARED, DRV_NAME, priv);
         if (err) {
                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
@@ -4515,14 +4192,14 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
          * 8. Enable interrupts and read RFKILL state
          *********************************************/
 
-        /* enable interrupts if needed: hw bug w/a */
+        /* enable rfkill interrupt: hw bug w/a */
         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
         }
 
-        iwl_enable_interrupts(priv);
+        iwl_enable_rfkill_int(priv);
 
         /* If platform's RF_KILL switch is NOT set to KILL */
         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
@@ -4548,7 +4225,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
         destroy_workqueue(priv->workqueue);
         priv->workqueue = NULL;
         free_irq(priv->pci_dev->irq, priv);
-        iwl_free_isr_ict(priv);
+        if (priv->cfg->ops->lib->isr_ops.free)
+                priv->cfg->ops->lib->isr_ops.free(priv);
  out_disable_msi:
         pci_disable_msi(priv->pci_dev);
         iwl_uninit_drv(priv);
@@ -4643,7 +4321,8 @@ static void __devexit iwl_pci_remove(struct pci_dev *pdev)
 
         iwl_uninit_drv(priv);
 
-        iwl_free_isr_ict(priv);
+        if (priv->cfg->ops->lib->isr_ops.free)
+                priv->cfg->ops->lib->isr_ops.free(priv);
 
         dev_kfree_skb(priv->beacon_skb);
 
@@ -4734,51 +4413,32 @@ static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
 
-/* 6x00 Series Gen2a */
-        {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1206, iwl6000g2a_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0085, 0x1216, iwl6000g2a_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1226, iwl6000g2a_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1207, iwl6000g2a_2bg_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6000g2a_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6000g2a_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6000g2a_2bg_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6000g2a_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6000g2a_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6000g2a_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6000g2a_2abg_cfg)},
-
-/* 6x00 Series Gen2b */
-        {IWL_PCI_DEVICE(0x008F, 0x5105, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0090, 0x5115, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5125, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5107, iwl6000g2b_bg_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5201, iwl6000g2b_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5221, iwl6000g2b_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5206, iwl6000g2b_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5226, iwl6000g2b_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x008F, 0x5207, iwl6000g2b_2bg_cfg)},
-        {IWL_PCI_DEVICE(0x008A, 0x5301, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008A, 0x5305, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008A, 0x5307, iwl6000g2b_bg_cfg)},
-        {IWL_PCI_DEVICE(0x008A, 0x5321, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008A, 0x5325, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008B, 0x5311, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x008B, 0x5315, iwl6000g2b_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6000g2b_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6000g2b_2bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6000g2b_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6000g2b_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6000g2b_2bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6000g2b_2abg_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6000g2b_2bg_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6000g2b_2agn_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6000g2b_2bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6000g2b_2abg_cfg)},
+/* 6x05 Series */
+        {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
+        {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
+        {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
+        {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
+        {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
+        {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
+        {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
+
+/* 6x30 Series */
+        {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
+        {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
+        {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
+        {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
+        {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
 
 /* 6x50 WiFi/WiMax Series */
         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
@@ -4788,13 +4448,13 @@ static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
 
-/* 6x50 WiFi/WiMax Series Gen2 */
-        {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6050g2_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6050g2_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6050g2_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6050g2_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6050g2_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6050g2_bgn_cfg)},
+/* 6150 WiFi/WiMax Series */
+        {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
 
 /* 1000 Series WiFi */
         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
@@ -4812,10 +4472,11 @@ static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
 
 /* 100 Series WiFi */
         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
+        {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
-        {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
-        {IWL_PCI_DEVICE(0x08AE, 0x1017, iwl100_bg_cfg)},
+        {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
 
 /* 130 Series WiFi */
         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
@@ -4836,10 +4497,7 @@ static struct pci_driver iwl_driver = {
         .id_table = iwl_hw_card_ids,
         .probe = iwl_pci_probe,
         .remove = __devexit_p(iwl_pci_remove),
-#ifdef CONFIG_PM
-        .suspend = iwl_pci_suspend,
-        .resume = iwl_pci_resume,
-#endif
+        .driver.pm = IWL_PM_OPS,
 };
 
 static int __init iwl_init(void)
@@ -4925,6 +4583,6 @@ module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
 MODULE_PARM_DESC(antenna_coupling,
                  "specify antenna coupling in dB (defualt: 0 dB)");
 
-module_param_named(bt_ch_announce, iwlagn_bt_ch_announce, bool, S_IRUGO);
-MODULE_PARM_DESC(bt_ch_announce,
-                 "Enable BT channel announcement mode (default: enable)");
+module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
+MODULE_PARM_DESC(bt_ch_inhibition,
+                 "Disable BT channel inhibition (default: enable)");
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.h b/drivers/net/wireless/iwlwifi/iwl-agn.h
index f525d55f2c0f..da303585f801 100644
--- a/drivers/net/wireless/iwlwifi/iwl-agn.h
+++ b/drivers/net/wireless/iwlwifi/iwl-agn.h
@@ -74,22 +74,22 @@ extern struct iwl_cfg iwl5100_bgn_cfg;
 extern struct iwl_cfg iwl5100_abg_cfg;
 extern struct iwl_cfg iwl5150_agn_cfg;
 extern struct iwl_cfg iwl5150_abg_cfg;
-extern struct iwl_cfg iwl6000g2a_2agn_cfg;
-extern struct iwl_cfg iwl6000g2a_2abg_cfg;
-extern struct iwl_cfg iwl6000g2a_2bg_cfg;
-extern struct iwl_cfg iwl6000g2b_bgn_cfg;
-extern struct iwl_cfg iwl6000g2b_bg_cfg;
-extern struct iwl_cfg iwl6000g2b_2agn_cfg;
-extern struct iwl_cfg iwl6000g2b_2abg_cfg;
-extern struct iwl_cfg iwl6000g2b_2bgn_cfg;
-extern struct iwl_cfg iwl6000g2b_2bg_cfg;
+extern struct iwl_cfg iwl6005_2agn_cfg;
+extern struct iwl_cfg iwl6005_2abg_cfg;
+extern struct iwl_cfg iwl6005_2bg_cfg;
+extern struct iwl_cfg iwl1030_bgn_cfg;
+extern struct iwl_cfg iwl1030_bg_cfg;
+extern struct iwl_cfg iwl6030_2agn_cfg;
+extern struct iwl_cfg iwl6030_2abg_cfg;
+extern struct iwl_cfg iwl6030_2bgn_cfg;
+extern struct iwl_cfg iwl6030_2bg_cfg;
 extern struct iwl_cfg iwl6000i_2agn_cfg;
 extern struct iwl_cfg iwl6000i_2abg_cfg;
 extern struct iwl_cfg iwl6000i_2bg_cfg;
 extern struct iwl_cfg iwl6000_3agn_cfg;
 extern struct iwl_cfg iwl6050_2agn_cfg;
 extern struct iwl_cfg iwl6050_2abg_cfg;
-extern struct iwl_cfg iwl6050g2_bgn_cfg;
+extern struct iwl_cfg iwl6150_bgn_cfg;
 extern struct iwl_cfg iwl1000_bgn_cfg;
 extern struct iwl_cfg iwl1000_bg_cfg;
 extern struct iwl_cfg iwl100_bgn_cfg;
@@ -102,6 +102,9 @@ extern struct iwl_hcmd_ops iwlagn_hcmd;
 extern struct iwl_hcmd_ops iwlagn_bt_hcmd;
 extern struct iwl_hcmd_utils_ops iwlagn_hcmd_utils;
 
+extern struct ieee80211_ops iwlagn_hw_ops;
+extern struct ieee80211_ops iwl4965_hw_ops;
+
 int iwl_reset_ict(struct iwl_priv *priv);
 void iwl_disable_ict(struct iwl_priv *priv);
 int iwl_alloc_isr_ict(struct iwl_priv *priv);
@@ -132,6 +135,11 @@ void iwl_free_tfds_in_queue(struct iwl_priv *priv,
 /* RXON */
 int iwlagn_commit_rxon(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
+int iwlagn_mac_config(struct ieee80211_hw *hw, u32 changed);
+void iwlagn_bss_info_changed(struct ieee80211_hw *hw,
+                             struct ieee80211_vif *vif,
+                             struct ieee80211_bss_conf *bss_conf,
+                             u32 changes);
 
 /* uCode */
 int iwlagn_load_ucode(struct iwl_priv *priv);
@@ -249,6 +257,7 @@ int iwlagn_manage_ibss_station(struct iwl_priv *priv,
 int iwlagn_send_rxon_assoc(struct iwl_priv *priv,
                            struct iwl_rxon_context *ctx);
 int iwlagn_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant);
+int iwlagn_send_beacon_cmd(struct iwl_priv *priv);
 
 /* bt coex */
 void iwlagn_send_advance_bt_config(struct iwl_priv *priv);
@@ -292,9 +301,12 @@ int iwl_sta_rx_agg_start(struct iwl_priv *priv, struct ieee80211_sta *sta,
                          int tid, u16 ssn);
 int iwl_sta_rx_agg_stop(struct iwl_priv *priv, struct ieee80211_sta *sta,
                         int tid);
-void iwl_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id);
 void iwl_sta_modify_sleep_tx_count(struct iwl_priv *priv, int sta_id, int cnt);
 int iwl_update_bcast_stations(struct iwl_priv *priv);
+void iwlagn_mac_sta_notify(struct ieee80211_hw *hw,
+                           struct ieee80211_vif *vif,
+                           enum sta_notify_cmd cmd,
+                           struct ieee80211_sta *sta);
 
 /* rate */
 static inline u32 iwl_ant_idx_to_flags(u8 ant_idx)
@@ -318,4 +330,31 @@ void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac);
 int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv);
 void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv);
 
+/* mac80211 handlers (for 4965) */
+int iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
+int iwlagn_mac_start(struct ieee80211_hw *hw);
+void iwlagn_mac_stop(struct ieee80211_hw *hw);
+void iwlagn_configure_filter(struct ieee80211_hw *hw,
+                             unsigned int changed_flags,
+                             unsigned int *total_flags,
+                             u64 multicast);
+int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+                       struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                       struct ieee80211_key_conf *key);
+void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
+                                struct ieee80211_vif *vif,
+                                struct ieee80211_key_conf *keyconf,
+                                struct ieee80211_sta *sta,
+                                u32 iv32, u16 *phase1key);
+int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
+                            struct ieee80211_vif *vif,
+                            enum ieee80211_ampdu_mlme_action action,
+                            struct ieee80211_sta *sta, u16 tid, u16 *ssn);
+int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
+                       struct ieee80211_vif *vif,
+                       struct ieee80211_sta *sta);
+void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
+                               struct ieee80211_channel_switch *ch_switch);
+void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop);
+
 #endif /* __iwl_agn_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-commands.h b/drivers/net/wireless/iwlwifi/iwl-commands.h
index 424801abc80e..f893d4a6aa87 100644
--- a/drivers/net/wireless/iwlwifi/iwl-commands.h
+++ b/drivers/net/wireless/iwlwifi/iwl-commands.h
@@ -2022,6 +2022,9 @@ struct iwl_compressed_ba_resp {
         __le64 bitmap;
         __le16 scd_flow;
         __le16 scd_ssn;
+        /* following only for 5000 series and up */
+        u8 txed;        /* number of frames sent */
+        u8 txed_2_done; /* number of frames acked */
 } __packed;
 
 /*
@@ -2407,9 +2410,9 @@ struct iwl_link_quality_cmd {
 #define BT_FRAG_THRESHOLD_MAX   0
 #define BT_FRAG_THRESHOLD_MIN   0
 
-#define BT_AGG_THRESHOLD_DEF    0
-#define BT_AGG_THRESHOLD_MAX    0
-#define BT_AGG_THRESHOLD_MIN    0
+#define BT_AGG_THRESHOLD_DEF    1200
+#define BT_AGG_THRESHOLD_MAX    8000
+#define BT_AGG_THRESHOLD_MIN    400
 
 /*
  * REPLY_BT_CONFIG = 0x9b (command, has simple generic response)
@@ -2436,8 +2439,9 @@ struct iwl_bt_cmd {
 #define IWLAGN_BT_FLAG_COEX_MODE_3W             2
 #define IWLAGN_BT_FLAG_COEX_MODE_4W             3
 
-#define IWLAGN_BT_FLAG_UCODE_DEFAULT    BIT(6)
-#define IWLAGN_BT_FLAG_NOCOEX_NOTIF     BIT(7)
+#define IWLAGN_BT_FLAG_UCODE_DEFAULT            BIT(6)
+/* Disable Sync PSPoll on SCO/eSCO */
+#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE        BIT(7)
 
 #define IWLAGN_BT_PRIO_BOOST_MAX        0xFF
 #define IWLAGN_BT_PRIO_BOOST_MIN        0x00
@@ -2447,8 +2451,9 @@ struct iwl_bt_cmd {
 
 #define IWLAGN_BT3_T7_DEFAULT           1
 
-#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffffffff)
-#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffffffff)
+#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
+#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
+#define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
 
 #define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT  2
 
@@ -2664,9 +2669,16 @@ struct iwl_spectrum_notification {
 #define IWL_POWER_VEC_SIZE 5
 
 #define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK        cpu_to_le16(BIT(0))
+#define IWL_POWER_POWER_SAVE_ENA_MSK            cpu_to_le16(BIT(0))
+#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK      cpu_to_le16(BIT(1))
 #define IWL_POWER_SLEEP_OVER_DTIM_MSK           cpu_to_le16(BIT(2))
 #define IWL_POWER_PCI_PM_MSK                    cpu_to_le16(BIT(3))
 #define IWL_POWER_FAST_PD                       cpu_to_le16(BIT(4))
+#define IWL_POWER_BEACON_FILTERING              cpu_to_le16(BIT(5))
+#define IWL_POWER_SHADOW_REG_ENA                cpu_to_le16(BIT(6))
+#define IWL_POWER_CT_KILL_SET                   cpu_to_le16(BIT(7))
+#define IWL_POWER_BT_SCO_ENA                    cpu_to_le16(BIT(8))
+#define IWL_POWER_ADVANCE_PM_ENA_MSK            cpu_to_le16(BIT(9))
 
 struct iwl3945_powertable_cmd {
         __le16 flags;
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 8700ab38d599..efbde1f1a8bf 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -77,15 +77,15 @@ EXPORT_SYMBOL(iwl_bcast_addr);
 
 
 /* This function both allocates and initializes hw and priv. */
-struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
-                struct ieee80211_ops *hw_ops)
+struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
 {
         struct iwl_priv *priv;
-
         /* mac80211 allocates memory for this device instance, including
          *   space for this driver's private structure */
-        struct ieee80211_hw *hw =
-                ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
+        struct ieee80211_hw *hw;
+
+        hw = ieee80211_alloc_hw(sizeof(struct iwl_priv),
+                                cfg->ops->ieee80211_ops);
         if (hw == NULL) {
                 pr_err("%s: Can not allocate network device\n",
                        cfg->name);
@@ -100,35 +100,6 @@ out:
 }
 EXPORT_SYMBOL(iwl_alloc_all);
 
-/*
- * QoS  support
-*/
-static void iwl_update_qos(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
-{
-        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
-                return;
-
-        if (!ctx->is_active)
-                return;
-
-        ctx->qos_data.def_qos_parm.qos_flags = 0;
-
-        if (ctx->qos_data.qos_active)
-                ctx->qos_data.def_qos_parm.qos_flags |=
-                        QOS_PARAM_FLG_UPDATE_EDCA_MSK;
-
-        if (ctx->ht.enabled)
-                ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
-
-        IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
-                      ctx->qos_data.qos_active,
-                      ctx->qos_data.def_qos_parm.qos_flags);
-
-        iwl_send_cmd_pdu_async(priv, ctx->qos_cmd,
-                               sizeof(struct iwl_qosparam_cmd),
-                               &ctx->qos_data.def_qos_parm, NULL);
-}
-
 #define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
 #define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
@@ -317,40 +288,6 @@ void iwlcore_free_geos(struct iwl_priv *priv)
 }
 EXPORT_SYMBOL(iwlcore_free_geos);
 
-/*
- *  iwlcore_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
- *  function.
- */
-void iwlcore_tx_cmd_protection(struct iwl_priv *priv,
-                               struct ieee80211_tx_info *info,
-                               __le16 fc, __le32 *tx_flags)
-{
-        if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
-                *tx_flags |= TX_CMD_FLG_RTS_MSK;
-                *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
-                *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
-
-                if (!ieee80211_is_mgmt(fc))
-                        return;
-
-                switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
-                case cpu_to_le16(IEEE80211_STYPE_AUTH):
-                case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
-                case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
-                case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
-                        *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
-                        *tx_flags |= TX_CMD_FLG_CTS_MSK;
-                        break;
-                }
-        } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
-                *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
-                *tx_flags |= TX_CMD_FLG_CTS_MSK;
-                *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
-        }
-}
-EXPORT_SYMBOL(iwlcore_tx_cmd_protection);
-
-
 static bool iwl_is_channel_extension(struct iwl_priv *priv,
                                      enum ieee80211_band band,
                                      u16 channel, u8 extension_chan_offset)
@@ -1020,6 +957,22 @@ void iwl_irq_handle_error(struct iwl_priv *priv)
         /* Cancel currently queued command. */
         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
 
+        /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
+        if (priv->cfg->internal_wimax_coex &&
+            (!(iwl_read_prph(priv, APMG_CLK_CTRL_REG) &
+                        APMS_CLK_VAL_MRB_FUNC_MODE) ||
+             (iwl_read_prph(priv, APMG_PS_CTRL_REG) &
+                        APMG_PS_CTRL_VAL_RESET_REQ))) {
+                wake_up_interruptible(&priv->wait_command_queue);
+                /*
+                 *Keep the restart process from trying to send host
+                 * commands by clearing the INIT status bit
+                 */
+                clear_bit(STATUS_READY, &priv->status);
+                IWL_ERR(priv, "RF is used by WiMAX\n");
+                return;
+        }
+
         IWL_ERR(priv, "Loaded firmware version: %s\n",
                 priv->hw->wiphy->fw_version);
 
@@ -1206,8 +1159,16 @@ EXPORT_SYMBOL(iwl_apm_init);
 
 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
 {
-        int ret = 0;
-        s8 prev_tx_power = priv->tx_power_user_lmt;
+        int ret;
+        s8 prev_tx_power;
+
+        lockdep_assert_held(&priv->mutex);
+
+        if (priv->tx_power_user_lmt == tx_power && !force)
+                return 0;
+
+        if (!priv->cfg->ops->lib->send_tx_power)
+                return -EOPNOTSUPP;
 
         if (tx_power < IWLAGN_TX_POWER_TARGET_POWER_MIN) {
                 IWL_WARN(priv,
@@ -1224,93 +1185,29 @@ int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
                 return -EINVAL;
         }
 
-        if (priv->tx_power_user_lmt != tx_power)
-                force = true;
+        if (!iwl_is_ready_rf(priv))
+                return -EIO;
 
-        /* if nic is not up don't send command */
-        if (iwl_is_ready_rf(priv)) {
-                priv->tx_power_user_lmt = tx_power;
-                if (force && priv->cfg->ops->lib->send_tx_power)
-                        ret = priv->cfg->ops->lib->send_tx_power(priv);
-                else if (!priv->cfg->ops->lib->send_tx_power)
-                        ret = -EOPNOTSUPP;
-                /*
-                 * if fail to set tx_power, restore the orig. tx power
-                 */
-                if (ret)
-                        priv->tx_power_user_lmt = prev_tx_power;
+        /* scan complete use tx_power_next, need to be updated */
+        priv->tx_power_next = tx_power;
+        if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
+                IWL_DEBUG_INFO(priv, "Deferring tx power set while scanning\n");
+                return 0;
         }
 
-        /*
-         * Even this is an async host command, the command
-         * will always report success from uCode
-         * So once driver can placing the command into the queue
-         * successfully, driver can use priv->tx_power_user_lmt
-         * to reflect the current tx power
-         */
-        return ret;
-}
-EXPORT_SYMBOL(iwl_set_tx_power);
+        prev_tx_power = priv->tx_power_user_lmt;
+        priv->tx_power_user_lmt = tx_power;
 
-irqreturn_t iwl_isr_legacy(int irq, void *data)
-{
-        struct iwl_priv *priv = data;
-        u32 inta, inta_mask;
-        u32 inta_fh;
-        unsigned long flags;
-        if (!priv)
-                return IRQ_NONE;
-
-        spin_lock_irqsave(&priv->lock, flags);
+        ret = priv->cfg->ops->lib->send_tx_power(priv);
 
-        /* Disable (but don't clear!) interrupts here to avoid
-         *    back-to-back ISRs and sporadic interrupts from our NIC.
-         * If we have something to service, the tasklet will re-enable ints.
-         * If we *don't* have something, we'll re-enable before leaving here. */
-        inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
-        iwl_write32(priv, CSR_INT_MASK, 0x00000000);
-
-        /* Discover which interrupts are active/pending */
-        inta = iwl_read32(priv, CSR_INT);
-        inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
-
-        /* Ignore interrupt if there's nothing in NIC to service.
-         * This may be due to IRQ shared with another device,
-         * or due to sporadic interrupts thrown from our NIC. */
-        if (!inta && !inta_fh) {
-                IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0, inta_fh == 0\n");
-                goto none;
+        /* if fail to set tx_power, restore the orig. tx power */
+        if (ret) {
+                priv->tx_power_user_lmt = prev_tx_power;
+                priv->tx_power_next = prev_tx_power;
         }
-
-        if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
-                /* Hardware disappeared. It might have already raised
-                 * an interrupt */
-                IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
-                goto unplugged;
-        }
-
-        IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
-                      inta, inta_mask, inta_fh);
-
-        inta &= ~CSR_INT_BIT_SCD;
-
-        /* iwl_irq_tasklet() will service interrupts and re-enable them */
-        if (likely(inta || inta_fh))
-                tasklet_schedule(&priv->irq_tasklet);
-
- unplugged:
-        spin_unlock_irqrestore(&priv->lock, flags);
-        return IRQ_HANDLED;
-
- none:
-        /* re-enable interrupts here since we don't have anything to service. */
-        /* only Re-enable if disabled by irq */
-        if (test_bit(STATUS_INT_ENABLED, &priv->status))
-                iwl_enable_interrupts(priv);
-        spin_unlock_irqrestore(&priv->lock, flags);
-        return IRQ_NONE;
+        return ret;
 }
-EXPORT_SYMBOL(iwl_isr_legacy);
+EXPORT_SYMBOL(iwl_set_tx_power);
 
 void iwl_send_bt_config(struct iwl_priv *priv)
 {
@@ -1326,6 +1223,7 @@ void iwl_send_bt_config(struct iwl_priv *priv)
         else
                 bt_cmd.flags = BT_COEX_ENABLE;
 
+        priv->bt_enable_flag = bt_cmd.flags;
         IWL_DEBUG_INFO(priv, "BT coex %s\n",
                 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
 
@@ -1452,318 +1350,51 @@ int iwl_mac_tx_last_beacon(struct ieee80211_hw *hw)
 }
 EXPORT_SYMBOL_GPL(iwl_mac_tx_last_beacon);
 
-static void iwl_ht_conf(struct iwl_priv *priv,
-                        struct ieee80211_vif *vif)
+static int iwl_set_mode(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 {
-        struct iwl_ht_config *ht_conf = &priv->current_ht_config;
-        struct ieee80211_sta *sta;
-        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
-        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
-
-        IWL_DEBUG_MAC80211(priv, "enter:\n");
-
-        if (!ctx->ht.enabled)
-                return;
-
-        ctx->ht.protection =
-                bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
-        ctx->ht.non_gf_sta_present =
-                !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
-
-        ht_conf->single_chain_sufficient = false;
-
-        switch (vif->type) {
-        case NL80211_IFTYPE_STATION:
-                rcu_read_lock();
-                sta = ieee80211_find_sta(vif, bss_conf->bssid);
-                if (sta) {
-                        struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
-                        int maxstreams;
-
-                        maxstreams = (ht_cap->mcs.tx_params &
-                                      IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
-                                        >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
-                        maxstreams += 1;
-
-                        if ((ht_cap->mcs.rx_mask[1] == 0) &&
-                            (ht_cap->mcs.rx_mask[2] == 0))
-                                ht_conf->single_chain_sufficient = true;
-                        if (maxstreams <= 1)
-                                ht_conf->single_chain_sufficient = true;
-                } else {
-                        /*
-                         * If at all, this can only happen through a race
-                         * when the AP disconnects us while we're still
-                         * setting up the connection, in that case mac80211
-                         * will soon tell us about that.
-                         */
-                        ht_conf->single_chain_sufficient = true;
-                }
-                rcu_read_unlock();
-                break;
-        case NL80211_IFTYPE_ADHOC:
-                ht_conf->single_chain_sufficient = true;
-                break;
-        default:
-                break;
-        }
-
-        IWL_DEBUG_MAC80211(priv, "leave\n");
-}
+        iwl_connection_init_rx_config(priv, ctx);
 
-static inline void iwl_set_no_assoc(struct iwl_priv *priv,
-                                    struct ieee80211_vif *vif)
-{
-        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
+        if (priv->cfg->ops->hcmd->set_rxon_chain)
+                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 
-        iwl_led_disassociate(priv);
-        /*
-         * inform the ucode that there is no longer an
-         * association and that no more packets should be
-         * sent
-         */
-        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
-        ctx->staging.assoc_id = 0;
-        iwlcore_commit_rxon(priv, ctx);
+        return iwlcore_commit_rxon(priv, ctx);
 }
 
-static void iwlcore_beacon_update(struct ieee80211_hw *hw,
-                                  struct ieee80211_vif *vif)
+static int iwl_setup_interface(struct iwl_priv *priv,
+                               struct iwl_rxon_context *ctx)
 {
-        struct iwl_priv *priv = hw->priv;
-        unsigned long flags;
-        __le64 timestamp;
-        struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
-
-        if (!skb)
-                return;
-
-        IWL_DEBUG_ASSOC(priv, "enter\n");
+        struct ieee80211_vif *vif = ctx->vif;
+        int err;
 
         lockdep_assert_held(&priv->mutex);
 
-        if (!priv->beacon_ctx) {
-                IWL_ERR(priv, "update beacon but no beacon context!\n");
-                dev_kfree_skb(skb);
-                return;
-        }
-
-        spin_lock_irqsave(&priv->lock, flags);
-
-        if (priv->beacon_skb)
-                dev_kfree_skb(priv->beacon_skb);
-
-        priv->beacon_skb = skb;
-
-        timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
-        priv->timestamp = le64_to_cpu(timestamp);
-
-        IWL_DEBUG_ASSOC(priv, "leave\n");
-
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        if (!iwl_is_ready_rf(priv)) {
-                IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
-                return;
-        }
-
-        priv->cfg->ops->lib->post_associate(priv, priv->beacon_ctx->vif);
-}
-
-void iwl_bss_info_changed(struct ieee80211_hw *hw,
-                          struct ieee80211_vif *vif,
-                          struct ieee80211_bss_conf *bss_conf,
-                          u32 changes)
-{
-        struct iwl_priv *priv = hw->priv;
-        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
-        int ret;
-
-        IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
-
-        if (!iwl_is_alive(priv))
-                return;
-
-        mutex_lock(&priv->mutex);
-
-        if (changes & BSS_CHANGED_QOS) {
-                unsigned long flags;
-
-                spin_lock_irqsave(&priv->lock, flags);
-                ctx->qos_data.qos_active = bss_conf->qos;
-                iwl_update_qos(priv, ctx);
-                spin_unlock_irqrestore(&priv->lock, flags);
-        }
-
-        if (changes & BSS_CHANGED_BEACON_ENABLED) {
-                /*
-                 * the add_interface code must make sure we only ever
-                 * have a single interface that could be beaconing at
-                 * any time.
-                 */
-                if (vif->bss_conf.enable_beacon)
-                        priv->beacon_ctx = ctx;
-                else
-                        priv->beacon_ctx = NULL;
-        }
-
-        if (changes & BSS_CHANGED_BEACON && vif->type == NL80211_IFTYPE_AP) {
-                dev_kfree_skb(priv->beacon_skb);
-                priv->beacon_skb = ieee80211_beacon_get(hw, vif);
-        }
-
-        if (changes & BSS_CHANGED_BEACON_INT && vif->type == NL80211_IFTYPE_AP)
-                iwl_send_rxon_timing(priv, ctx);
-
-        if (changes & BSS_CHANGED_BSSID) {
-                IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
-
-                /*
-                 * If there is currently a HW scan going on in the
-                 * background then we need to cancel it else the RXON
-                 * below/in post_associate will fail.
-                 */
-                if (iwl_scan_cancel_timeout(priv, 100)) {
-                        IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
-                        IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
-                        mutex_unlock(&priv->mutex);
-                        return;
-                }
-
-                /* mac80211 only sets assoc when in STATION mode */
-                if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
-                        memcpy(ctx->staging.bssid_addr,
-                               bss_conf->bssid, ETH_ALEN);
-
-                        /* currently needed in a few places */
-                        memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
-                } else {
-                        ctx->staging.filter_flags &=
-                                ~RXON_FILTER_ASSOC_MSK;
-                }
-
-        }
-
         /*
-         * This needs to be after setting the BSSID in case
-         * mac80211 decides to do both changes at once because
-         * it will invoke post_associate.
+         * This variable will be correct only when there's just
+         * a single context, but all code using it is for hardware
+         * that supports only one context.
          */
-        if (vif->type == NL80211_IFTYPE_ADHOC && changes & BSS_CHANGED_BEACON)
-                iwlcore_beacon_update(hw, vif);
-
-        if (changes & BSS_CHANGED_ERP_PREAMBLE) {
-                IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
-                                   bss_conf->use_short_preamble);
-                if (bss_conf->use_short_preamble)
-                        ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
-                else
-                        ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
-        }
-
-        if (changes & BSS_CHANGED_ERP_CTS_PROT) {
-                IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
-                if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
-                        ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
-                else
-                        ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
-                if (bss_conf->use_cts_prot)
-                        ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
-                else
-                        ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
-        }
-
-        if (changes & BSS_CHANGED_BASIC_RATES) {
-                /* XXX use this information
-                 *
-                 * To do that, remove code from iwl_set_rate() and put something
-                 * like this here:
-                 *
-                if (A-band)
-                        ctx->staging.ofdm_basic_rates =
-                                bss_conf->basic_rates;
-                else
-                        ctx->staging.ofdm_basic_rates =
-                                bss_conf->basic_rates >> 4;
-                        ctx->staging.cck_basic_rates =
-                                bss_conf->basic_rates & 0xF;
-                 */
-        }
-
-        if (changes & BSS_CHANGED_HT) {
-                iwl_ht_conf(priv, vif);
-
-                if (priv->cfg->ops->hcmd->set_rxon_chain)
-                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
-        }
-
-        if (changes & BSS_CHANGED_ASSOC) {
-                IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
-                if (bss_conf->assoc) {
-                        priv->timestamp = bss_conf->timestamp;
-
-                        iwl_led_associate(priv);
-
-                        if (!iwl_is_rfkill(priv))
-                                priv->cfg->ops->lib->post_associate(priv, vif);
-                } else
-                        iwl_set_no_assoc(priv, vif);
-        }
-
-        if (changes && iwl_is_associated_ctx(ctx) && bss_conf->aid) {
-                IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
-                                   changes);
-                ret = iwl_send_rxon_assoc(priv, ctx);
-                if (!ret) {
-                        /* Sync active_rxon with latest change. */
-                        memcpy((void *)&ctx->active,
-                                &ctx->staging,
-                                sizeof(struct iwl_rxon_cmd));
-                }
-        }
+        priv->iw_mode = vif->type;
 
-        if (changes & BSS_CHANGED_BEACON_ENABLED) {
-                if (vif->bss_conf.enable_beacon) {
-                        memcpy(ctx->staging.bssid_addr,
-                               bss_conf->bssid, ETH_ALEN);
-                        memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
-                        iwl_led_associate(priv);
-                        iwlcore_config_ap(priv, vif);
-                } else
-                        iwl_set_no_assoc(priv, vif);
-        }
+        ctx->is_active = true;
 
-        if (changes & BSS_CHANGED_IBSS) {
-                ret = priv->cfg->ops->lib->manage_ibss_station(priv, vif,
-                                                        bss_conf->ibss_joined);
-                if (ret)
-                        IWL_ERR(priv, "failed to %s IBSS station %pM\n",
-                                bss_conf->ibss_joined ? "add" : "remove",
-                                bss_conf->bssid);
+        err = iwl_set_mode(priv, ctx);
+        if (err) {
+                if (!ctx->always_active)
+                        ctx->is_active = false;
+                return err;
         }
 
-        if (changes & BSS_CHANGED_IDLE &&
-            priv->cfg->ops->hcmd->set_pan_params) {
-                if (priv->cfg->ops->hcmd->set_pan_params(priv))
-                        IWL_ERR(priv, "failed to update PAN params\n");
+        if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist &&
+            vif->type == NL80211_IFTYPE_ADHOC) {
+                /*
+                 * pretend to have high BT traffic as long as we
+                 * are operating in IBSS mode, as this will cause
+                 * the rate scaling etc. to behave as intended.
+                 */
+                priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
         }
 
-        mutex_unlock(&priv->mutex);
-
-        IWL_DEBUG_MAC80211(priv, "leave\n");
-}
-EXPORT_SYMBOL(iwl_bss_info_changed);
-
-static int iwl_set_mode(struct iwl_priv *priv, struct ieee80211_vif *vif)
-{
-        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
-
-        iwl_connection_init_rx_config(priv, ctx);
-
-        if (priv->cfg->ops->hcmd->set_rxon_chain)
-                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
-
-        return iwlcore_commit_rxon(priv, ctx);
+        return 0;
 }
 
 int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
@@ -1771,7 +1402,7 @@ int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
         struct iwl_priv *priv = hw->priv;
         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
         struct iwl_rxon_context *tmp, *ctx = NULL;
-        int err = 0;
+        int err;
 
         IWL_DEBUG_MAC80211(priv, "enter: type %d, addr %pM\n",
                            vif->type, vif->addr);
@@ -1813,36 +1444,11 @@ int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
 
         vif_priv->ctx = ctx;
         ctx->vif = vif;
-        /*
-         * This variable will be correct only when there's just
-         * a single context, but all code using it is for hardware
-         * that supports only one context.
-         */
-        priv->iw_mode = vif->type;
-
-        ctx->is_active = true;
 
-        err = iwl_set_mode(priv, vif);
-        if (err) {
-                if (!ctx->always_active)
-                        ctx->is_active = false;
-                goto out_err;
-        }
-
-        if (priv->cfg->bt_params &&
-            priv->cfg->bt_params->advanced_bt_coexist &&
-            vif->type == NL80211_IFTYPE_ADHOC) {
-                /*
-                 * pretend to have high BT traffic as long as we
-                 * are operating in IBSS mode, as this will cause
-                 * the rate scaling etc. to behave as intended.
-                 */
-                priv->bt_traffic_load = IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
-        }
-
-        goto out;
+        err = iwl_setup_interface(priv, ctx);
+        if (!err)
+                goto out;
 
- out_err:
         ctx->vif = NULL;
         priv->iw_mode = NL80211_IFTYPE_STATION;
  out:
@@ -1853,27 +1459,24 @@ int iwl_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
 }
 EXPORT_SYMBOL(iwl_mac_add_interface);
 
-void iwl_mac_remove_interface(struct ieee80211_hw *hw,
-                              struct ieee80211_vif *vif)
+static void iwl_teardown_interface(struct iwl_priv *priv,
+                                   struct ieee80211_vif *vif,
+                                   bool mode_change)
 {
-        struct iwl_priv *priv = hw->priv;
         struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
 
-        IWL_DEBUG_MAC80211(priv, "enter\n");
-
-        mutex_lock(&priv->mutex);
-
-        WARN_ON(ctx->vif != vif);
-        ctx->vif = NULL;
+        lockdep_assert_held(&priv->mutex);
 
         if (priv->scan_vif == vif) {
                 iwl_scan_cancel_timeout(priv, 200);
                 iwl_force_scan_end(priv);
         }
-        iwl_set_mode(priv, vif);
 
-        if (!ctx->always_active)
-                ctx->is_active = false;
+        if (!mode_change) {
+                iwl_set_mode(priv, ctx);
+                if (!ctx->always_active)
+                        ctx->is_active = false;
+        }
 
         /*
          * When removing the IBSS interface, overwrite the
@@ -1883,211 +1486,31 @@ void iwl_mac_remove_interface(struct ieee80211_hw *hw,
          * both values are the same and zero.
          */
         if (vif->type == NL80211_IFTYPE_ADHOC)
-                priv->bt_traffic_load = priv->notif_bt_traffic_load;
-
-        memset(priv->bssid, 0, ETH_ALEN);
-        mutex_unlock(&priv->mutex);
-
-        IWL_DEBUG_MAC80211(priv, "leave\n");
-
-}
-EXPORT_SYMBOL(iwl_mac_remove_interface);
-
-/**
- * iwl_mac_config - mac80211 config callback
- */
-int iwl_mac_config(struct ieee80211_hw *hw, u32 changed)
-{
-        struct iwl_priv *priv = hw->priv;
-        const struct iwl_channel_info *ch_info;
-        struct ieee80211_conf *conf = &hw->conf;
-        struct ieee80211_channel *channel = conf->channel;
-        struct iwl_ht_config *ht_conf = &priv->current_ht_config;
-        struct iwl_rxon_context *ctx;
-        unsigned long flags = 0;
-        int ret = 0;
-        u16 ch;
-        int scan_active = 0;
-
-        mutex_lock(&priv->mutex);
-
-        IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
-                                        channel->hw_value, changed);
-
-        if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
-                        test_bit(STATUS_SCANNING, &priv->status))) {
-                scan_active = 1;
-                IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
-        }
-
-        if (changed & (IEEE80211_CONF_CHANGE_SMPS |
-                       IEEE80211_CONF_CHANGE_CHANNEL)) {
-                /* mac80211 uses static for non-HT which is what we want */
-                priv->current_ht_config.smps = conf->smps_mode;
-
-                /*
-                 * Recalculate chain counts.
-                 *
-                 * If monitor mode is enabled then mac80211 will
-                 * set up the SM PS mode to OFF if an HT channel is
-                 * configured.
-                 */
-                if (priv->cfg->ops->hcmd->set_rxon_chain)
-                        for_each_context(priv, ctx)
-                                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
-        }
-
-        /* during scanning mac80211 will delay channel setting until
-         * scan finish with changed = 0
-         */
-        if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
-                if (scan_active)
-                        goto set_ch_out;
-
-                ch = channel->hw_value;
-                ch_info = iwl_get_channel_info(priv, channel->band, ch);
-                if (!is_channel_valid(ch_info)) {
-                        IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
-                        ret = -EINVAL;
-                        goto set_ch_out;
-                }
-
-                spin_lock_irqsave(&priv->lock, flags);
-
-                for_each_context(priv, ctx) {
-                        /* Configure HT40 channels */
-                        ctx->ht.enabled = conf_is_ht(conf);
-                        if (ctx->ht.enabled) {
-                                if (conf_is_ht40_minus(conf)) {
-                                        ctx->ht.extension_chan_offset =
-                                                IEEE80211_HT_PARAM_CHA_SEC_BELOW;
-                                        ctx->ht.is_40mhz = true;
-                                } else if (conf_is_ht40_plus(conf)) {
-                                        ctx->ht.extension_chan_offset =
-                                                IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
-                                        ctx->ht.is_40mhz = true;
-                                } else {
-                                        ctx->ht.extension_chan_offset =
-                                                IEEE80211_HT_PARAM_CHA_SEC_NONE;
-                                        ctx->ht.is_40mhz = false;
-                                }
-                        } else
-                                ctx->ht.is_40mhz = false;
-
-                        /*
-                         * Default to no protection. Protection mode will
-                         * later be set from BSS config in iwl_ht_conf
-                         */
-                        ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
-
-                        /* if we are switching from ht to 2.4 clear flags
-                         * from any ht related info since 2.4 does not
-                         * support ht */
-                        if ((le16_to_cpu(ctx->staging.channel) != ch))
-                                ctx->staging.flags = 0;
-
-                        iwl_set_rxon_channel(priv, channel, ctx);
-                        iwl_set_rxon_ht(priv, ht_conf);
-
-                        iwl_set_flags_for_band(priv, ctx, channel->band,
-                                               ctx->vif);
-                }
-
-                spin_unlock_irqrestore(&priv->lock, flags);
-
-                if (priv->cfg->ops->lib->update_bcast_stations)
-                        ret = priv->cfg->ops->lib->update_bcast_stations(priv);
-
- set_ch_out:
-                /* The list of supported rates and rate mask can be different
-                 * for each band; since the band may have changed, reset
-                 * the rate mask to what mac80211 lists */
-                iwl_set_rate(priv);
-        }
-
-        if (changed & (IEEE80211_CONF_CHANGE_PS |
-                        IEEE80211_CONF_CHANGE_IDLE)) {
-                ret = iwl_power_update_mode(priv, false);
-                if (ret)
-                        IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
-        }
-
-        if (changed & IEEE80211_CONF_CHANGE_POWER) {
-                IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
-                        priv->tx_power_user_lmt, conf->power_level);
-
-                iwl_set_tx_power(priv, conf->power_level, false);
-        }
-
-        if (!iwl_is_ready(priv)) {
-                IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
-                goto out;
-        }
-
-        if (scan_active)
-                goto out;
-
-        for_each_context(priv, ctx) {
-                if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)))
-                        iwlcore_commit_rxon(priv, ctx);
-                else
-                        IWL_DEBUG_INFO(priv,
-                                "Not re-sending same RXON configuration.\n");
-        }
-
-out:
-        IWL_DEBUG_MAC80211(priv, "leave\n");
-        mutex_unlock(&priv->mutex);
-        return ret;
+                priv->bt_traffic_load = priv->last_bt_traffic_load;
 }
-EXPORT_SYMBOL(iwl_mac_config);
 
-void iwl_mac_reset_tsf(struct ieee80211_hw *hw)
+void iwl_mac_remove_interface(struct ieee80211_hw *hw,
+                              struct ieee80211_vif *vif)
 {
         struct iwl_priv *priv = hw->priv;
-        unsigned long flags;
-        /* IBSS can only be the IWL_RXON_CTX_BSS context */
-        struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
+        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
 
-        mutex_lock(&priv->mutex);
         IWL_DEBUG_MAC80211(priv, "enter\n");
 
-        spin_lock_irqsave(&priv->lock, flags);
-        memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        spin_lock_irqsave(&priv->lock, flags);
-
-        /* new association get rid of ibss beacon skb */
-        if (priv->beacon_skb)
-                dev_kfree_skb(priv->beacon_skb);
-
-        priv->beacon_skb = NULL;
-
-        priv->timestamp = 0;
-
-        spin_unlock_irqrestore(&priv->lock, flags);
-
-        iwl_scan_cancel_timeout(priv, 100);
-        if (!iwl_is_ready_rf(priv)) {
-                IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
-                mutex_unlock(&priv->mutex);
-                return;
-        }
+        mutex_lock(&priv->mutex);
 
-        /* we are restarting association process
-         * clear RXON_FILTER_ASSOC_MSK bit
-         */
-        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
-        iwlcore_commit_rxon(priv, ctx);
+        WARN_ON(ctx->vif != vif);
+        ctx->vif = NULL;
 
-        iwl_set_rate(priv);
+        iwl_teardown_interface(priv, vif, false);
 
+        memset(priv->bssid, 0, ETH_ALEN);
         mutex_unlock(&priv->mutex);
 
         IWL_DEBUG_MAC80211(priv, "leave\n");
+
 }
-EXPORT_SYMBOL(iwl_mac_reset_tsf);
+EXPORT_SYMBOL(iwl_mac_remove_interface);
 
 int iwl_alloc_txq_mem(struct iwl_priv *priv)
 {
@@ -2431,77 +1854,115 @@ int iwl_force_reset(struct iwl_priv *priv, int mode, bool external)
         return 0;
 }
 
-/**
- * iwl_bg_monitor_recover - Timer callback to check for stuck queue and recover
- *
- * During normal condition (no queue is stuck), the timer is continually set to
- * execute every monitor_recover_period milliseconds after the last timer
- * expired.  When the queue read_ptr is at the same place, the timer is
- * shorten to 100mSecs.  This is
- *      1) to reduce the chance that the read_ptr may wrap around (not stuck)
- *      2) to detect the stuck queues quicker before the station and AP can
- *      disassociate each other.
- *
- * This function monitors all the tx queues and recover from it if any
- * of the queues are stuck.
- * 1. It first check the cmd queue for stuck conditions.  If it is stuck,
- *      it will recover by resetting the firmware and return.
- * 2. Then, it checks for station association.  If it associates it will check
- *      other queues.  If any queue is stuck, it will recover by resetting
- *      the firmware.
- * Note: It the number of times the queue read_ptr to be at the same place to
- *      be MAX_REPEAT+1 in order to consider to be stuck.
- */
+int iwl_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
+                             enum nl80211_iftype newtype, bool newp2p)
+{
+        struct iwl_priv *priv = hw->priv;
+        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
+        struct iwl_rxon_context *tmp;
+        u32 interface_modes;
+        int err;
+
+        newtype = ieee80211_iftype_p2p(newtype, newp2p);
+
+        mutex_lock(&priv->mutex);
+
+        interface_modes = ctx->interface_modes | ctx->exclusive_interface_modes;
+
+        if (!(interface_modes & BIT(newtype))) {
+                err = -EBUSY;
+                goto out;
+        }
+
+        if (ctx->exclusive_interface_modes & BIT(newtype)) {
+                for_each_context(priv, tmp) {
+                        if (ctx == tmp)
+                                continue;
+
+                        if (!tmp->vif)
+                                continue;
+
+                        /*
+                         * The current mode switch would be exclusive, but
+                         * another context is active ... refuse the switch.
+                         */
+                        err = -EBUSY;
+                        goto out;
+                }
+        }
+
+        /* success */
+        iwl_teardown_interface(priv, vif, true);
+        vif->type = newtype;
+        err = iwl_setup_interface(priv, ctx);
+        WARN_ON(err);
+        /*
+         * We've switched internally, but submitting to the
+         * device may have failed for some reason. Mask this
+         * error, because otherwise mac80211 will not switch
+         * (and set the interface type back) and we'll be
+         * out of sync with it.
+         */
+        err = 0;
+
+ out:
+        mutex_unlock(&priv->mutex);
+        return err;
+}
+EXPORT_SYMBOL(iwl_mac_change_interface);
+
 /*
- * The maximum number of times the read pointer of the tx queue at the
- * same place without considering to be stuck.
+ * On every watchdog tick we check (latest) time stamp. If it does not
+ * change during timeout period and queue is not empty we reset firmware.
  */
-#define MAX_REPEAT      (2)
 static int iwl_check_stuck_queue(struct iwl_priv *priv, int cnt)
 {
-        struct iwl_tx_queue *txq;
-        struct iwl_queue *q;
+        struct iwl_tx_queue *txq = &priv->txq[cnt];
+        struct iwl_queue *q = &txq->q;
+        unsigned long timeout;
+        int ret;
 
-        txq = &priv->txq[cnt];
-        q = &txq->q;
-        /* queue is empty, skip */
-        if (q->read_ptr == q->write_ptr)
+        if (q->read_ptr == q->write_ptr) {
+                txq->time_stamp = jiffies;
                 return 0;
+        }
 
-        if (q->read_ptr == q->last_read_ptr) {
-                /* a queue has not been read from last time */
-                if (q->repeat_same_read_ptr > MAX_REPEAT) {
-                        IWL_ERR(priv,
-                                "queue %d stuck %d time. Fw reload.\n",
-                                q->id, q->repeat_same_read_ptr);
-                        q->repeat_same_read_ptr = 0;
-                        iwl_force_reset(priv, IWL_FW_RESET, false);
-                } else {
-                        q->repeat_same_read_ptr++;
-                        IWL_DEBUG_RADIO(priv,
-                                        "queue %d, not read %d time\n",
-                                        q->id,
-                                        q->repeat_same_read_ptr);
-                        mod_timer(&priv->monitor_recover,
-                                jiffies + msecs_to_jiffies(
-                                IWL_ONE_HUNDRED_MSECS));
-                        return 1;
-                }
-        } else {
-                q->last_read_ptr = q->read_ptr;
-                q->repeat_same_read_ptr = 0;
+        timeout = txq->time_stamp +
+                  msecs_to_jiffies(priv->cfg->base_params->wd_timeout);
+
+        if (time_after(jiffies, timeout)) {
+                IWL_ERR(priv, "Queue %d stuck for %u ms.\n",
+                                q->id, priv->cfg->base_params->wd_timeout);
+                ret = iwl_force_reset(priv, IWL_FW_RESET, false);
+                return (ret == -EAGAIN) ? 0 : 1;
         }
+
         return 0;
 }
 
-void iwl_bg_monitor_recover(unsigned long data)
+/*
+ * Making watchdog tick be a quarter of timeout assure we will
+ * discover the queue hung between timeout and 1.25*timeout
+ */
+#define IWL_WD_TICK(timeout) ((timeout) / 4)
+
+/*
+ * Watchdog timer callback, we check each tx queue for stuck, if if hung
+ * we reset the firmware. If everything is fine just rearm the timer.
+ */
+void iwl_bg_watchdog(unsigned long data)
 {
         struct iwl_priv *priv = (struct iwl_priv *)data;
         int cnt;
+        unsigned long timeout;
 
         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
                 return;
 
+        timeout = priv->cfg->base_params->wd_timeout;
+        if (timeout == 0)
+                return;
+
         /* monitor and check for stuck cmd queue */
         if (iwl_check_stuck_queue(priv, priv->cmd_queue))
                 return;
@@ -2516,17 +1977,23 @@ void iwl_bg_monitor_recover(unsigned long data)
                                 return;
                 }
         }
-        if (priv->cfg->base_params->monitor_recover_period) {
-                /*
-                 * Reschedule the timer to occur in
-                 * priv->cfg->base_params->monitor_recover_period
-                 */
-                mod_timer(&priv->monitor_recover, jiffies + msecs_to_jiffies(
-                          priv->cfg->base_params->monitor_recover_period));
-        }
+
+        mod_timer(&priv->watchdog, jiffies +
+                  msecs_to_jiffies(IWL_WD_TICK(timeout)));
 }
-EXPORT_SYMBOL(iwl_bg_monitor_recover);
+EXPORT_SYMBOL(iwl_bg_watchdog);
+
+void iwl_setup_watchdog(struct iwl_priv *priv)
+{
+        unsigned int timeout = priv->cfg->base_params->wd_timeout;
 
+        if (timeout)
+                mod_timer(&priv->watchdog,
+                          jiffies + msecs_to_jiffies(IWL_WD_TICK(timeout)));
+        else
+                del_timer(&priv->watchdog);
+}
+EXPORT_SYMBOL(iwl_setup_watchdog);
 
 /*
  * extended beacon time format
@@ -2584,8 +2051,9 @@ EXPORT_SYMBOL(iwl_add_beacon_time);
 
 #ifdef CONFIG_PM
 
-int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+int iwl_pci_suspend(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct iwl_priv *priv = pci_get_drvdata(pdev);
 
         /*
@@ -2597,18 +2065,14 @@ int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
          */
         iwl_apm_stop(priv);
 
-        pci_save_state(pdev);
-        pci_disable_device(pdev);
-        pci_set_power_state(pdev, PCI_D3hot);
-
         return 0;
 }
 EXPORT_SYMBOL(iwl_pci_suspend);
 
-int iwl_pci_resume(struct pci_dev *pdev)
+int iwl_pci_resume(struct device *device)
 {
+        struct pci_dev *pdev = to_pci_dev(device);
         struct iwl_priv *priv = pci_get_drvdata(pdev);
-        int ret;
         bool hw_rfkill = false;
 
         /*
@@ -2617,11 +2081,6 @@ int iwl_pci_resume(struct pci_dev *pdev)
          */
         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
 
-        pci_set_power_state(pdev, PCI_D0);
-        ret = pci_enable_device(pdev);
-        if (ret)
-                return ret;
-        pci_restore_state(pdev);
         iwl_enable_interrupts(priv);
 
         if (!(iwl_read32(priv, CSR_GP_CNTRL) &
@@ -2639,4 +2098,14 @@ int iwl_pci_resume(struct pci_dev *pdev)
 }
 EXPORT_SYMBOL(iwl_pci_resume);
 
+const struct dev_pm_ops iwl_pm_ops = {
+        .suspend = iwl_pci_suspend,
+        .resume = iwl_pci_resume,
+        .freeze = iwl_pci_suspend,
+        .thaw = iwl_pci_resume,
+        .poweroff = iwl_pci_suspend,
+        .restore = iwl_pci_resume,
+};
+EXPORT_SYMBOL(iwl_pm_ops);
+
 #endif /* CONFIG_PM */
diff --git a/drivers/net/wireless/iwlwifi/iwl-core.h b/drivers/net/wireless/iwlwifi/iwl-core.h
index 64527def059f..a3474376fdbc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.h
+++ b/drivers/net/wireless/iwlwifi/iwl-core.h
@@ -120,6 +120,14 @@ struct iwl_apm_ops {
         void (*config)(struct iwl_priv *priv);
 };
 
+struct iwl_isr_ops {
+        irqreturn_t (*isr) (int irq, void *data);
+        void (*free)(struct iwl_priv *priv);
+        int (*alloc)(struct iwl_priv *priv);
+        int (*reset)(struct iwl_priv *priv);
+        void (*disable)(struct iwl_priv *priv);
+};
+
 struct iwl_debugfs_ops {
         ssize_t (*rx_stats_read)(struct file *file, char __user *user_buf,
                                  size_t count, loff_t *ppos);
@@ -193,22 +201,15 @@ struct iwl_lib_ops {
         /* power */
         int (*send_tx_power) (struct iwl_priv *priv);
         void (*update_chain_flags)(struct iwl_priv *priv);
-        void (*post_associate)(struct iwl_priv *priv,
-                               struct ieee80211_vif *vif);
-        void (*config_ap)(struct iwl_priv *priv, struct ieee80211_vif *vif);
-        irqreturn_t (*isr) (int irq, void *data);
+
+        /* isr */
+        struct iwl_isr_ops isr_ops;
 
         /* eeprom operations (as defined in iwl-eeprom.h) */
         struct iwl_eeprom_ops eeprom_ops;
 
         /* temperature */
         struct iwl_temp_ops temp_ops;
-        /* station management */
-        int (*manage_ibss_station)(struct iwl_priv *priv,
-                                   struct ieee80211_vif *vif, bool add);
-        int (*update_bcast_stations)(struct iwl_priv *priv);
-        /* recover from tx queue stall */
-        void (*recover_from_tx_stall)(unsigned long data);
         /* check for plcp health */
         bool (*check_plcp_health)(struct iwl_priv *priv,
                                         struct iwl_rx_packet *pkt);
@@ -235,12 +236,23 @@ struct iwl_nic_ops {
         void (*additional_nic_config)(struct iwl_priv *priv);
 };
 
+struct iwl_legacy_ops {
+        void (*post_associate)(struct iwl_priv *priv);
+        void (*config_ap)(struct iwl_priv *priv);
+        /* station management */
+        int (*update_bcast_stations)(struct iwl_priv *priv);
+        int (*manage_ibss_station)(struct iwl_priv *priv,
+                                   struct ieee80211_vif *vif, bool add);
+};
+
 struct iwl_ops {
         const struct iwl_lib_ops *lib;
         const struct iwl_hcmd_ops *hcmd;
         const struct iwl_hcmd_utils_ops *utils;
         const struct iwl_led_ops *led;
         const struct iwl_nic_ops *nic;
+        const struct iwl_legacy_ops *legacy;
+        const struct ieee80211_ops *ieee80211_ops;
 };
 
 struct iwl_mod_params {
@@ -266,7 +278,7 @@ struct iwl_mod_params {
  * @plcp_delta_threshold: plcp error rate threshold used to trigger
  *      radio tuning when there is a high receiving plcp error rate
  * @chain_noise_scale: default chain noise scale used for gain computation
- * @monitor_recover_period: default timer used to check stuck queues
+ * @wd_timeout: TX queues watchdog timeout
  * @temperature_kelvin: temperature report by uCode in kelvin
  * @max_event_log_size: size of event log buffer size for ucode event logging
  * @tx_power_by_driver: tx power calibration performed by driver
@@ -276,7 +288,10 @@ struct iwl_mod_params {
  *      sensitivity calibration operation
  * @chain_noise_calib_by_driver: driver has the capability to perform
  *      chain noise calibration operation
-*/
+ * @shadow_reg_enable: HW shadhow register bit
+ * @no_agg_framecnt_info: uCode do not provide aggregation frame count
+ *      information
+ */
 struct iwl_base_params {
         int eeprom_size;
         int num_of_queues;      /* def: HW dependent */
@@ -298,14 +313,15 @@ struct iwl_base_params {
         const bool support_wimax_coexist;
         u8 plcp_delta_threshold;
         s32 chain_noise_scale;
-        /* timer period for monitor the driver queues */
-        u32 monitor_recover_period;
+        unsigned int wd_timeout;
         bool temperature_kelvin;
         u32 max_event_log_size;
         const bool tx_power_by_driver;
         const bool ucode_tracing;
         const bool sensitivity_calib_by_driver;
         const bool chain_noise_calib_by_driver;
+        const bool shadow_reg_enable;
+        const bool no_agg_framecnt_info;
 };
 /*
  * @advanced_bt_coexist: support advanced bt coexist
@@ -315,6 +331,7 @@ struct iwl_base_params {
  * @agg_time_limit: maximum number of uSec in aggregation
  * @ampdu_factor: Maximum A-MPDU length factor
  * @ampdu_density: Minimum A-MPDU spacing
+ * @bt_sco_disable: uCode should not response to BT in SCO/ESCO mode
 */
 struct iwl_bt_params {
         bool advanced_bt_coexist;
@@ -324,6 +341,7 @@ struct iwl_bt_params {
         u16 agg_time_limit;
         u8 ampdu_factor;
         u8 ampdu_density;
+        bool bt_sco_disable;
 };
 /*
  * @use_rts_for_aggregation: use rts/cts protection for HT traffic
@@ -344,6 +362,10 @@ struct iwl_ht_params {
  * @need_dc_calib: need to perform init dc calibration
  * @need_temp_offset_calib: need to perform temperature offset calibration
  * @scan_antennas: available antenna for scan operation
+ * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
+ * @adv_pm: advance power management
+ * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
+ * @internal_wimax_coex: internal wifi/wimax combo device
  *
  * We enable the driver to be backward compatible wrt API version. The
  * driver specifies which APIs it supports (with @ucode_api_max being the
@@ -389,15 +411,17 @@ struct iwl_cfg {
         const bool need_dc_calib;         /* if used set to true */
         const bool need_temp_offset_calib; /* if used set to true */
         u8 scan_rx_antennas[IEEE80211_NUM_BANDS];
-        u8 scan_tx_antennas[IEEE80211_NUM_BANDS];
+        enum iwl_led_mode led_mode;
+        const bool adv_pm;
+        const bool rx_with_siso_diversity;
+        const bool internal_wimax_coex;
 };
 
 /***************************
  *   L i b                 *
  ***************************/
 
-struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
-                struct ieee80211_ops *hw_ops);
+struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg);
 int iwl_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
                     const struct ieee80211_tx_queue_params *params);
 int iwl_mac_tx_last_beacon(struct ieee80211_hw *hw);
@@ -425,23 +449,16 @@ int iwl_set_decrypted_flag(struct iwl_priv *priv,
                            u32 decrypt_res,
                            struct ieee80211_rx_status *stats);
 void iwl_irq_handle_error(struct iwl_priv *priv);
-void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif);
-void iwl_bss_info_changed(struct ieee80211_hw *hw,
-                                     struct ieee80211_vif *vif,
-                                     struct ieee80211_bss_conf *bss_conf,
-                                     u32 changes);
 int iwl_mac_add_interface(struct ieee80211_hw *hw,
                           struct ieee80211_vif *vif);
 void iwl_mac_remove_interface(struct ieee80211_hw *hw,
                               struct ieee80211_vif *vif);
-int iwl_mac_config(struct ieee80211_hw *hw, u32 changed);
-void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif);
-void iwl_mac_reset_tsf(struct ieee80211_hw *hw);
+int iwl_mac_change_interface(struct ieee80211_hw *hw,
+                             struct ieee80211_vif *vif,
+                             enum nl80211_iftype newtype, bool newp2p);
 int iwl_alloc_txq_mem(struct iwl_priv *priv);
 void iwl_free_txq_mem(struct iwl_priv *priv);
-void iwlcore_tx_cmd_protection(struct iwl_priv *priv,
-                               struct ieee80211_tx_info *info,
-                               __le16 fc, __le32 *tx_flags);
+
 #ifdef CONFIG_IWLWIFI_DEBUGFS
 int iwl_alloc_traffic_mem(struct iwl_priv *priv);
 void iwl_free_traffic_mem(struct iwl_priv *priv);
@@ -529,6 +546,7 @@ int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
 void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
                         int slots_num, u32 txq_id);
 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id);
+void iwl_setup_watchdog(struct iwl_priv *priv);
 /*****************************************************
  * TX power
  ****************************************************/
@@ -598,7 +616,6 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd);
 /*****************************************************
  * PCI                                               *
  *****************************************************/
-irqreturn_t iwl_isr_legacy(int irq, void *data);
 
 static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
 {
@@ -609,15 +626,23 @@ static inline u16 iwl_pcie_link_ctl(struct iwl_priv *priv)
         return pci_lnk_ctl;
 }
 
-void iwl_bg_monitor_recover(unsigned long data);
+void iwl_bg_watchdog(unsigned long data);
 u32 iwl_usecs_to_beacons(struct iwl_priv *priv, u32 usec, u32 beacon_interval);
 __le32 iwl_add_beacon_time(struct iwl_priv *priv, u32 base,
                            u32 addon, u32 beacon_interval);
 
 #ifdef CONFIG_PM
-int iwl_pci_suspend(struct pci_dev *pdev, pm_message_t state);
-int iwl_pci_resume(struct pci_dev *pdev);
-#endif /* CONFIG_PM */
+int iwl_pci_suspend(struct device *device);
+int iwl_pci_resume(struct device *device);
+extern const struct dev_pm_ops iwl_pm_ops;
+
+#define IWL_PM_OPS      (&iwl_pm_ops)
+
+#else /* !CONFIG_PM */
+
+#define IWL_PM_OPS      NULL
+
+#endif /* !CONFIG_PM */
 
 /*****************************************************
 *  Error Handling Debugging
@@ -724,11 +749,6 @@ static inline int iwlcore_commit_rxon(struct iwl_priv *priv,
 {
         return priv->cfg->ops->hcmd->commit_rxon(priv, ctx);
 }
-static inline void iwlcore_config_ap(struct iwl_priv *priv,
-                                     struct ieee80211_vif *vif)
-{
-        priv->cfg->ops->lib->config_ap(priv, vif);
-}
 static inline const struct ieee80211_supported_band *iwl_get_hw_mode(
                         struct iwl_priv *priv, enum ieee80211_band band)
 {
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
index 2aa15ab13892..b80bf7dff55b 100644
--- a/drivers/net/wireless/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -132,6 +132,8 @@
 
 #define CSR_LED_REG             (CSR_BASE+0x094)
 #define CSR_DRAM_INT_TBL_REG    (CSR_BASE+0x0A0)
+#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
+
 
 /* GIO Chicken Bits (PCI Express bus link power management) */
 #define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
diff --git a/drivers/net/wireless/iwlwifi/iwl-debug.h b/drivers/net/wireless/iwlwifi/iwl-debug.h
index 0b961a353ff6..ebdea3be3ef9 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debug.h
+++ b/drivers/net/wireless/iwlwifi/iwl-debug.h
@@ -120,6 +120,7 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv)
 /* 0x000000F0 - 0x00000010 */
 #define IWL_DL_MACDUMP          (1 << 4)
 #define IWL_DL_HCMD_DUMP        (1 << 5)
+#define IWL_DL_EEPROM           (1 << 6)
 #define IWL_DL_RADIO            (1 << 7)
 /* 0x00000F00 - 0x00000100 */
 #define IWL_DL_POWER            (1 << 8)
@@ -164,6 +165,7 @@ static inline void iwl_dbgfs_unregister(struct iwl_priv *priv)
 #define IWL_DEBUG_WEP(p, f, a...)       IWL_DEBUG(p, IWL_DL_WEP, f, ## a)
 #define IWL_DEBUG_HC(p, f, a...)        IWL_DEBUG(p, IWL_DL_HCMD, f, ## a)
 #define IWL_DEBUG_HC_DUMP(p, f, a...)   IWL_DEBUG(p, IWL_DL_HCMD_DUMP, f, ## a)
+#define IWL_DEBUG_EEPROM(p, f, a...)    IWL_DEBUG(p, IWL_DL_EEPROM, f, ## a)
 #define IWL_DEBUG_CALIB(p, f, a...)     IWL_DEBUG(p, IWL_DL_CALIB, f, ## a)
 #define IWL_DEBUG_FW(p, f, a...)        IWL_DEBUG(p, IWL_DL_FW, f, ## a)
 #define IWL_DEBUG_RF_KILL(p, f, a...)   IWL_DEBUG(p, IWL_DL_RF_KILL, f, ## a)
diff --git a/drivers/net/wireless/iwlwifi/iwl-debugfs.c b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
index 8fdd4efdb1d3..6fe80b5e7a15 100644
--- a/drivers/net/wireless/iwlwifi/iwl-debugfs.c
+++ b/drivers/net/wireless/iwlwifi/iwl-debugfs.c
@@ -992,11 +992,8 @@ static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
                                 " swq_id=%#.2x (ac %d/hwq %d)\n",
                                 cnt, q->read_ptr, q->write_ptr,
                                 !!test_bit(cnt, priv->queue_stopped),
-                                txq->swq_id,
-                                txq->swq_id & 0x80 ? txq->swq_id & 3 :
-                                txq->swq_id,
-                                txq->swq_id & 0x80 ? (txq->swq_id >> 2) &
-                                0x1f : txq->swq_id);
+                                txq->swq_id, txq->swq_id & 3,
+                                (txq->swq_id >> 2) & 0x1f);
                 if (cnt >= 4)
                         continue;
                 /* for the ACs, display the stop count too */
@@ -1537,32 +1534,26 @@ static ssize_t iwl_dbgfs_ucode_bt_stats_read(struct file *file,
                         user_buf, count, ppos);
 }
 
-static ssize_t iwl_dbgfs_monitor_period_write(struct file *file,
+static ssize_t iwl_dbgfs_wd_timeout_write(struct file *file,
                                         const char __user *user_buf,
                                         size_t count, loff_t *ppos) {
 
         struct iwl_priv *priv = file->private_data;
         char buf[8];
         int buf_size;
-        int period;
+        int timeout;
 
         memset(buf, 0, sizeof(buf));
         buf_size = min(count, sizeof(buf) -  1);
         if (copy_from_user(buf, user_buf, buf_size))
                 return -EFAULT;
-        if (sscanf(buf, "%d", &period) != 1)
+        if (sscanf(buf, "%d", &timeout) != 1)
                 return -EINVAL;
-        if (period < 0 || period > IWL_MAX_MONITORING_PERIOD)
-                priv->cfg->base_params->monitor_recover_period =
-                        IWL_DEF_MONITORING_PERIOD;
-        else
-                priv->cfg->base_params->monitor_recover_period = period;
+        if (timeout < 0 || timeout > IWL_MAX_WD_TIMEOUT)
+                timeout = IWL_DEF_WD_TIMEOUT;
 
-        if (priv->cfg->base_params->monitor_recover_period)
-                mod_timer(&priv->monitor_recover, jiffies + msecs_to_jiffies(
-                          priv->cfg->base_params->monitor_recover_period));
-        else
-                del_timer_sync(&priv->monitor_recover);
+        priv->cfg->base_params->wd_timeout = timeout;
+        iwl_setup_watchdog(priv);
         return count;
 }
 
@@ -1576,11 +1567,18 @@ static ssize_t iwl_dbgfs_bt_traffic_read(struct file *file,
         const size_t bufsz = sizeof(buf);
         ssize_t ret;
 
+        if (!priv->bt_enable_flag) {
+                pos += scnprintf(buf + pos, bufsz - pos, "BT coex disabled\n");
+                ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
+                return ret;
+        }
+        pos += scnprintf(buf + pos, bufsz - pos, "BT enable flag: 0x%x\n",
+                priv->bt_enable_flag);
         pos += scnprintf(buf + pos, bufsz - pos, "BT in %s mode\n",
                 priv->bt_full_concurrent ? "full concurrency" : "3-wire");
         pos += scnprintf(buf + pos, bufsz - pos, "BT status: %s, "
                          "last traffic notif: %d\n",
-                priv->bt_status ? "On" : "Off", priv->notif_bt_traffic_load);
+                priv->bt_status ? "On" : "Off", priv->last_bt_traffic_load);
         pos += scnprintf(buf + pos, bufsz - pos, "ch_announcement: %d, "
                          "sco_active: %d, kill_ack_mask: %x, "
                          "kill_cts_mask: %x\n",
@@ -1689,7 +1687,7 @@ DEBUGFS_READ_FILE_OPS(rxon_flags);
 DEBUGFS_READ_FILE_OPS(rxon_filter_flags);
 DEBUGFS_WRITE_FILE_OPS(txfifo_flush);
 DEBUGFS_READ_FILE_OPS(ucode_bt_stats);
-DEBUGFS_WRITE_FILE_OPS(monitor_period);
+DEBUGFS_WRITE_FILE_OPS(wd_timeout);
 DEBUGFS_READ_FILE_OPS(bt_traffic);
 DEBUGFS_READ_WRITE_FILE_OPS(protection_mode);
 DEBUGFS_READ_FILE_OPS(reply_tx_error);
@@ -1766,7 +1764,7 @@ int iwl_dbgfs_register(struct iwl_priv *priv, const char *name)
         DEBUGFS_ADD_FILE(reply_tx_error, dir_debug, S_IRUSR);
         DEBUGFS_ADD_FILE(rxon_flags, dir_debug, S_IWUSR);
         DEBUGFS_ADD_FILE(rxon_filter_flags, dir_debug, S_IWUSR);
-        DEBUGFS_ADD_FILE(monitor_period, dir_debug, S_IWUSR);
+        DEBUGFS_ADD_FILE(wd_timeout, dir_debug, S_IWUSR);
         if (priv->cfg->bt_params && priv->cfg->bt_params->advanced_bt_coexist)
                 DEBUGFS_ADD_FILE(bt_traffic, dir_debug, S_IRUSR);
         if (priv->cfg->base_params->sensitivity_calib_by_driver)
diff --git a/drivers/net/wireless/iwlwifi/iwl-dev.h b/drivers/net/wireless/iwlwifi/iwl-dev.h
index 70e07fa48405..8dda67850af4 100644
--- a/drivers/net/wireless/iwlwifi/iwl-dev.h
+++ b/drivers/net/wireless/iwlwifi/iwl-dev.h
@@ -129,9 +129,6 @@ struct iwl_queue {
         int write_ptr;       /* 1-st empty entry (index) host_w*/
         int read_ptr;         /* last used entry (index) host_r*/
         /* use for monitoring and recovering the stuck queue */
-        int last_read_ptr;      /* storing the last read_ptr */
-        /* number of time read_ptr and last_read_ptr are the same */
-        u8 repeat_same_read_ptr;
         dma_addr_t dma_addr;   /* physical addr for BD's */
         int n_window;          /* safe queue window */
         u32 id;
@@ -155,6 +152,7 @@ struct iwl_tx_info {
  * @meta: array of meta data for each command/tx buffer
  * @dma_addr_cmd: physical address of cmd/tx buffer array
  * @txb: array of per-TFD driver data
+ * @time_stamp: time (in jiffies) of last read_ptr change
  * @need_update: indicates need to update read/write index
  * @sched_retry: indicates queue is high-throughput aggregation (HT AGG) enabled
  *
@@ -170,6 +168,7 @@ struct iwl_tx_queue {
         struct iwl_device_cmd **cmd;
         struct iwl_cmd_meta *meta;
         struct iwl_tx_info *txb;
+        unsigned long time_stamp;
         u8 need_update;
         u8 sched_retry;
         u8 active;
@@ -1104,11 +1103,10 @@ struct iwl_event_log {
 #define IWL_DELAY_NEXT_FORCE_RF_RESET  (HZ*3)
 #define IWL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
 
-/* timer constants use to monitor and recover stuck tx queues in mSecs */
-#define IWL_DEF_MONITORING_PERIOD       (1000)
-#define IWL_LONG_MONITORING_PERIOD      (5000)
-#define IWL_ONE_HUNDRED_MSECS   (100)
-#define IWL_MAX_MONITORING_PERIOD       (60000)
+/* TX queue watchdog timeouts in mSecs */
+#define IWL_DEF_WD_TIMEOUT      (2000)
+#define IWL_LONG_WD_TIMEOUT     (10000)
+#define IWL_MAX_WD_TIMEOUT      (120000)
 
 /* BT Antenna Coupling Threshold (dB) */
 #define IWL_BT_ANTENNA_COUPLING_THRESHOLD       (35)
@@ -1162,6 +1160,8 @@ struct iwl_rxon_context {
          */
         bool always_active, is_active;
 
+        bool ht_need_multiple_chains;
+
         enum iwl_rxon_context_id ctxid;
 
         u32 interface_modes, exclusive_interface_modes;
@@ -1468,8 +1468,9 @@ struct iwl_priv {
         };
 
         /* bt coex */
+        u8 bt_enable_flag;
         u8 bt_status;
-        u8 bt_traffic_load, notif_bt_traffic_load;
+        u8 bt_traffic_load, last_bt_traffic_load;
         bool bt_ch_announce;
         bool bt_sco_active;
         bool bt_full_concurrent;
@@ -1480,7 +1481,6 @@ struct iwl_priv {
         u16 bt_on_thresh;
         u16 bt_duration;
         u16 dynamic_frag_thresh;
-        u16 dynamic_agg_thresh;
         u8 bt_ci_compliance;
         struct work_struct bt_traffic_change_work;
 
@@ -1517,6 +1517,7 @@ struct iwl_priv {
         s8 tx_power_user_lmt;
         s8 tx_power_device_lmt;
         s8 tx_power_lmt_in_half_dbm; /* max tx power in half-dBm format */
+        s8 tx_power_next;
 
 
 #ifdef CONFIG_IWLWIFI_DEBUG
@@ -1542,7 +1543,7 @@ struct iwl_priv {
         struct work_struct run_time_calib_work;
         struct timer_list statistics_periodic;
         struct timer_list ucode_trace;
-        struct timer_list monitor_recover;
+        struct timer_list watchdog;
         bool hw_ready;
 
         struct iwl_event_log event_log;
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.c b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
index 87cd10ff285d..358cfd7e5af1 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.c
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.c
@@ -147,7 +147,7 @@ static int iwl_eeprom_verify_signature(struct iwl_priv *priv)
         u32 gp = iwl_read32(priv, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
         int ret = 0;
 
-        IWL_DEBUG_INFO(priv, "EEPROM signature=0x%08x\n", gp);
+        IWL_DEBUG_EEPROM(priv, "EEPROM signature=0x%08x\n", gp);
         switch (gp) {
         case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP:
                 if (priv->nvm_device_type != NVM_DEVICE_TYPE_OTP) {
@@ -354,7 +354,7 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
                  */
                 valid_addr = next_link_addr;
                 next_link_addr = le16_to_cpu(link_value) * sizeof(u16);
-                IWL_DEBUG_INFO(priv, "OTP blocks %d addr 0x%x\n",
+                IWL_DEBUG_EEPROM(priv, "OTP blocks %d addr 0x%x\n",
                                usedblocks, next_link_addr);
                 if (iwl_read_otp_word(priv, next_link_addr, &link_value))
                         return -EINVAL;
@@ -374,7 +374,7 @@ static int iwl_find_otp_image(struct iwl_priv *priv,
         } while (usedblocks <= priv->cfg->base_params->max_ll_items);
 
         /* OTP has no valid blocks */
-        IWL_DEBUG_INFO(priv, "OTP has no valid blocks\n");
+        IWL_DEBUG_EEPROM(priv, "OTP has no valid blocks\n");
         return -EINVAL;
 }
 
@@ -414,7 +414,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
                 return -ENOENT;
         /* allocate eeprom */
         sz = priv->cfg->base_params->eeprom_size;
-        IWL_DEBUG_INFO(priv, "NVM size = %d\n", sz);
+        IWL_DEBUG_EEPROM(priv, "NVM size = %d\n", sz);
         priv->eeprom = kzalloc(sz, GFP_KERNEL);
         if (!priv->eeprom) {
                 ret = -ENOMEM;
@@ -492,7 +492,7 @@ int iwl_eeprom_init(struct iwl_priv *priv)
                 }
         }
 
-        IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
+        IWL_DEBUG_EEPROM(priv, "NVM Type: %s, version: 0x%x\n",
                        (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
                        ? "OTP" : "EEPROM",
                        iwl_eeprom_query16(priv, EEPROM_VERSION));
@@ -594,7 +594,7 @@ static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
         if (!is_channel_valid(ch_info))
                 return -1;
 
-        IWL_DEBUG_INFO(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
+        IWL_DEBUG_EEPROM(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
                         " Ad-Hoc %ssupported\n",
                         ch_info->channel,
                         is_channel_a_band(ch_info) ?
@@ -634,11 +634,11 @@ int iwl_init_channel_map(struct iwl_priv *priv)
         struct iwl_channel_info *ch_info;
 
         if (priv->channel_count) {
-                IWL_DEBUG_INFO(priv, "Channel map already initialized.\n");
+                IWL_DEBUG_EEPROM(priv, "Channel map already initialized.\n");
                 return 0;
         }
 
-        IWL_DEBUG_INFO(priv, "Initializing regulatory info from EEPROM\n");
+        IWL_DEBUG_EEPROM(priv, "Initializing regulatory info from EEPROM\n");
 
         priv->channel_count =
             ARRAY_SIZE(iwl_eeprom_band_1) +
@@ -647,7 +647,8 @@ int iwl_init_channel_map(struct iwl_priv *priv)
             ARRAY_SIZE(iwl_eeprom_band_4) +
             ARRAY_SIZE(iwl_eeprom_band_5);
 
-        IWL_DEBUG_INFO(priv, "Parsing data for %d channels.\n", priv->channel_count);
+        IWL_DEBUG_EEPROM(priv, "Parsing data for %d channels.\n",
+                        priv->channel_count);
 
         priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
                                      priv->channel_count, GFP_KERNEL);
@@ -686,7 +687,8 @@ int iwl_init_channel_map(struct iwl_priv *priv)
                                         IEEE80211_CHAN_NO_HT40;
 
                         if (!(is_channel_valid(ch_info))) {
-                                IWL_DEBUG_INFO(priv, "Ch. %d Flags %x [%sGHz] - "
+                                IWL_DEBUG_EEPROM(priv,
+                                               "Ch. %d Flags %x [%sGHz] - "
                                                "No traffic\n",
                                                ch_info->channel,
                                                ch_info->flags,
@@ -702,7 +704,8 @@ int iwl_init_channel_map(struct iwl_priv *priv)
                         ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
                         ch_info->min_power = 0;
 
-                        IWL_DEBUG_INFO(priv, "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
+                        IWL_DEBUG_EEPROM(priv, "Ch. %d [%sGHz] "
+                                       "%s%s%s%s%s%s(0x%02x %ddBm):"
                                        " Ad-Hoc %ssupported\n",
                                        ch_info->channel,
                                        is_channel_a_band(ch_info) ?
diff --git a/drivers/net/wireless/iwlwifi/iwl-eeprom.h b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
index d9b590625ae4..9e6f31355eee 100644
--- a/drivers/net/wireless/iwlwifi/iwl-eeprom.h
+++ b/drivers/net/wireless/iwlwifi/iwl-eeprom.h
@@ -110,9 +110,18 @@ enum {
 };
 
 /* SKU Capabilities */
+/* 3945 only */
 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE                (1 << 0)
 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE                (1 << 1)
 
+/* 5000 and up */
+#define EEPROM_SKU_CAP_BAND_POS                         (4)
+#define EEPROM_SKU_CAP_BAND_SELECTION                   \
+                (3 << EEPROM_SKU_CAP_BAND_POS)
+#define EEPROM_SKU_CAP_11N_ENABLE                       (1 << 6)
+#define EEPROM_SKU_CAP_AMT_ENABLE                       (1 << 7)
+#define EEPROM_SKU_CAP_IPAN_ENABLE                      (1 << 8)
+
 /* *regulatory* channel data format in eeprom, one for each channel.
  * There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
 struct iwl_eeprom_channel {
@@ -120,6 +129,17 @@ struct iwl_eeprom_channel {
         s8 max_power_avg;       /* max power (dBm) on this chnl, limit 31 */
 } __packed;
 
+enum iwl_eeprom_enhanced_txpwr_flags {
+        IWL_EEPROM_ENH_TXP_FL_VALID             = BIT(0),
+        IWL_EEPROM_ENH_TXP_FL_BAND_52G          = BIT(1),
+        IWL_EEPROM_ENH_TXP_FL_OFDM              = BIT(2),
+        IWL_EEPROM_ENH_TXP_FL_40MHZ             = BIT(3),
+        IWL_EEPROM_ENH_TXP_FL_HT_AP             = BIT(4),
+        IWL_EEPROM_ENH_TXP_FL_RES1              = BIT(5),
+        IWL_EEPROM_ENH_TXP_FL_RES2              = BIT(6),
+        IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE       = BIT(7),
+};
+
 /**
  * iwl_eeprom_enhanced_txpwr structure
  *    This structure presents the enhanced regulatory tx power limit layout
@@ -127,21 +147,23 @@ struct iwl_eeprom_channel {
  *    Enhanced regulatory tx power portion of eeprom image can be broken down
  *    into individual structures; each one is 8 bytes in size and contain the
  *    following information
- * @common: (desc + channel) not used by driver, should _NOT_ be "zero"
+ * @flags: entry flags
+ * @channel: channel number
  * @chain_a_max_pwr: chain a max power in 1/2 dBm
  * @chain_b_max_pwr: chain b max power in 1/2 dBm
  * @chain_c_max_pwr: chain c max power in 1/2 dBm
- * @reserved: not used, should be "zero"
+ * @delta_20_in_40: 20-in-40 deltas (hi/lo)
  * @mimo2_max_pwr: mimo2 max power in 1/2 dBm
  * @mimo3_max_pwr: mimo3 max power in 1/2 dBm
  *
  */
 struct iwl_eeprom_enhanced_txpwr {
-        __le16 common;
+        u8 flags;
+        u8 channel;
         s8 chain_a_max;
         s8 chain_b_max;
         s8 chain_c_max;
-        s8 reserved;
+        u8 delta_20_in_40;
         s8 mimo2_max;
         s8 mimo3_max;
 } __packed;
@@ -186,6 +208,8 @@ struct iwl_eeprom_enhanced_txpwr {
 #define EEPROM_LINK_CALIBRATION      (2*0x67)
 #define EEPROM_LINK_PROCESS_ADJST    (2*0x68)
 #define EEPROM_LINK_OTHERS           (2*0x69)
+#define EEPROM_LINK_TXP_LIMIT        (2*0x6a)
+#define EEPROM_LINK_TXP_LIMIT_SIZE   (2*0x6b)
 
 /* agn regulatory - indirect access */
 #define EEPROM_REG_BAND_1_CHANNELS       ((0x08)\
@@ -207,59 +231,6 @@ struct iwl_eeprom_enhanced_txpwr {
 #define EEPROM_6000_REG_BAND_24_HT40_CHANNELS  ((0x80)\
                 | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 14  bytes */
 
-/* 6000 and up regulatory tx power - indirect access */
-/* max. elements per section */
-#define EEPROM_MAX_TXPOWER_SECTION_ELEMENTS     (8)
-#define EEPROM_TXPOWER_COMMON_HT40_INDEX        (2)
-
-/**
- * Partition the enhanced tx power portion of eeprom image into
- * 10 sections based on band, modulation, frequency and channel
- *
- * Section 1: all CCK channels
- * Section 2: all 2.4 GHz OFDM (Legacy, HT and HT40 ) channels
- * Section 3: all 5.2 GHz OFDM (Legacy, HT and HT40) channels
- * Section 4: 2.4 GHz 20MHz channels: 1, 2, 10, 11. Both Legacy and HT
- * Section 5: 2.4 GHz 40MHz channels: 1, 2, 6, 7, 9, (_above_)
- * Section 6: 5.2 GHz 20MHz channels: 36, 64, 100, both Legacy and HT
- * Section 7: 5.2 GHz 40MHz channels: 36, 60, 100 (_above_)
- * Section 8: 2.4 GHz channel 13, Both Legacy and HT
- * Section 9: 2.4 GHz channel 140, Both Legacy and HT
- * Section 10: 2.4 GHz 40MHz channels: 132, 44 (_above_)
- */
-/* 2.4 GHz band: CCK */
-#define EEPROM_LB_CCK_20_COMMON       ((0xA8)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 8 bytes */
-/* 2.4 GHz band: 20MHz-Legacy, 20MHz-HT, 40MHz-HT */
-#define EEPROM_LB_OFDM_COMMON       ((0xB0)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 24 bytes */
-/* 5.2 GHz band: 20MHz-Legacy, 20MHz-HT, 40MHz-HT */
-#define EEPROM_HB_OFDM_COMMON       ((0xC8)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 24 bytes */
-/* 2.4GHz band channels:
- *      1Legacy, 1HT, 2Legacy, 2HT, 10Legacy, 10HT, 11Legacy, 11HT */
-#define EEPROM_LB_OFDM_20_BAND       ((0xE0)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 64 bytes */
-/* 2.4 GHz band HT40 channels: (1,+1) (2,+1) (6,+1) (7,+1) (9,+1) */
-#define EEPROM_LB_OFDM_HT40_BAND       ((0x120)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 40 bytes */
-/* 5.2GHz band channels: 36Legacy, 36HT, 64Legacy, 64HT, 100Legacy, 100HT */
-#define EEPROM_HB_OFDM_20_BAND       ((0x148)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 48 bytes */
-/* 5.2 GHz band HT40 channels: (36,+1) (60,+1) (100,+1) */
-#define EEPROM_HB_OFDM_HT40_BAND       ((0x178)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 24 bytes */
-/* 2.4 GHz band, channnel 13: Legacy, HT */
-#define EEPROM_LB_OFDM_20_CHANNEL_13       ((0x190)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 16 bytes */
-/* 5.2 GHz band, channnel 140: Legacy, HT */
-#define EEPROM_HB_OFDM_20_CHANNEL_140       ((0x1A0)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 16 bytes */
-/* 5.2 GHz band, HT40 channnels (132,+1) (44,+1) */
-#define EEPROM_HB_OFDM_HT40_BAND_1       ((0x1B0)\
-                | INDIRECT_ADDRESS | INDIRECT_REGULATORY)   /* 16 bytes */
-
-
 /* 5050 Specific */
 #define EEPROM_5050_TX_POWER_VERSION    (4)
 #define EEPROM_5050_EEPROM_VERSION      (0x21E)
@@ -389,6 +360,8 @@ struct iwl_eeprom_calib_info {
 #define INDIRECT_CALIBRATION        0x00040000
 #define INDIRECT_PROCESS_ADJST      0x00050000
 #define INDIRECT_OTHERS             0x00060000
+#define INDIRECT_TXP_LIMIT          0x00070000
+#define INDIRECT_TXP_LIMIT_SIZE     0x00080000
 #define INDIRECT_ADDRESS            0x00100000
 
 /* General */
@@ -397,11 +370,10 @@ struct iwl_eeprom_calib_info {
 #define EEPROM_BOARD_REVISION               (2*0x35)    /* 2  bytes */
 #define EEPROM_BOARD_PBA_NUMBER             (2*0x3B+1)  /* 9  bytes */
 #define EEPROM_VERSION                      (2*0x44)    /* 2  bytes */
-#define EEPROM_SKU_CAP                      (2*0x45)    /* 1  bytes */
+#define EEPROM_SKU_CAP                      (2*0x45)    /* 2  bytes */
 #define EEPROM_OEM_MODE                     (2*0x46)    /* 2  bytes */
 #define EEPROM_WOWLAN_MODE                  (2*0x47)    /* 2  bytes */
 #define EEPROM_RADIO_CONFIG                 (2*0x48)    /* 2  bytes */
-#define EEPROM_3945_M_VERSION               (2*0x4A)    /* 1  bytes */
 #define EEPROM_NUM_MAC_ADDRESS              (2*0x4C)    /* 2  bytes */
 
 /* The following masks are to be applied on EEPROM_RADIO_CONFIG */
@@ -504,6 +476,7 @@ struct iwl_eeprom_ops {
 int iwl_eeprom_init(struct iwl_priv *priv);
 void iwl_eeprom_free(struct iwl_priv *priv);
 int  iwl_eeprom_check_version(struct iwl_priv *priv);
+int  iwl_eeprom_check_sku(struct iwl_priv *priv);
 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset);
 int iwlcore_eeprom_verify_signature(struct iwl_priv *priv);
 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset);
diff --git a/drivers/net/wireless/iwlwifi/iwl-helpers.h b/drivers/net/wireless/iwlwifi/iwl-helpers.h
index 1aaef70deaec..8821f088ba7f 100644
--- a/drivers/net/wireless/iwlwifi/iwl-helpers.h
+++ b/drivers/net/wireless/iwlwifi/iwl-helpers.h
@@ -44,15 +44,6 @@ static inline struct ieee80211_conf *ieee80211_get_hw_conf(
         return &hw->conf;
 }
 
-static inline unsigned long elapsed_jiffies(unsigned long start,
-                                            unsigned long end)
-{
-        if (end >= start)
-                return end - start;
-
-        return end + (MAX_JIFFY_OFFSET - start) + 1;
-}
-
 /**
  * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
  * @index -- current index
@@ -104,42 +95,36 @@ static inline int iwl_alloc_fw_desc(struct pci_dev *pci_dev,
  * | | | | | | | |
  * | | | | | | +-+-------- AC queue (0-3)
  * | | | | | |
- * | +-+-+-+-+------------ HW A-MPDU queue
+ * | +-+-+-+-+------------ HW queue ID
  * |
- * +---------------------- indicates agg queue
+ * +---------------------- unused
  */
-static inline u8 iwl_virtual_agg_queue_num(u8 ac, u8 hwq)
+static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
 {
         BUG_ON(ac > 3);   /* only have 2 bits */
-        BUG_ON(hwq > 31); /* only have 5 bits */
+        BUG_ON(hwq > 31); /* only use 5 bits */
 
-        return 0x80 | (hwq << 2) | ac;
+        txq->swq_id = (hwq << 2) | ac;
 }
 
-static inline void iwl_wake_queue(struct iwl_priv *priv, u8 queue)
+static inline void iwl_wake_queue(struct iwl_priv *priv,
+                                  struct iwl_tx_queue *txq)
 {
-        u8 ac = queue;
-        u8 hwq = queue;
-
-        if (queue & 0x80) {
-                ac = queue & 3;
-                hwq = (queue >> 2) & 0x1f;
-        }
+        u8 queue = txq->swq_id;
+        u8 ac = queue & 3;
+        u8 hwq = (queue >> 2) & 0x1f;
 
         if (test_and_clear_bit(hwq, priv->queue_stopped))
                 if (atomic_dec_return(&priv->queue_stop_count[ac]) <= 0)
                         ieee80211_wake_queue(priv->hw, ac);
 }
 
-static inline void iwl_stop_queue(struct iwl_priv *priv, u8 queue)
+static inline void iwl_stop_queue(struct iwl_priv *priv,
+                                  struct iwl_tx_queue *txq)
 {
-        u8 ac = queue;
-        u8 hwq = queue;
-
-        if (queue & 0x80) {
-                ac = queue & 3;
-                hwq = (queue >> 2) & 0x1f;
-        }
+        u8 queue = txq->swq_id;
+        u8 ac = queue & 3;
+        u8 hwq = (queue >> 2) & 0x1f;
 
         if (!test_and_set_bit(hwq, priv->queue_stopped))
                 if (atomic_inc_return(&priv->queue_stop_count[ac]) > 0)
@@ -163,6 +148,12 @@ static inline void iwl_disable_interrupts(struct iwl_priv *priv)
         IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
 }
 
+static inline void iwl_enable_rfkill_int(struct iwl_priv *priv)
+{
+        IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n");
+        iwl_write32(priv, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
+}
+
 static inline void iwl_enable_interrupts(struct iwl_priv *priv)
 {
         IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.c b/drivers/net/wireless/iwlwifi/iwl-led.c
index 86c2b6fed0c6..46ccdf406e8e 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.c
+++ b/drivers/net/wireless/iwlwifi/iwl-led.c
@@ -45,9 +45,8 @@
 /* default: IWL_LED_BLINK(0) using blinking index table */
 static int led_mode;
 module_param(led_mode, int, S_IRUGO);
-MODULE_PARM_DESC(led_mode, "led mode: 0=blinking, 1=On(RF On)/Off(RF Off), "
-                           "(default 0)");
-
+MODULE_PARM_DESC(led_mode, "0=system default, "
+                "1=On(RF On)/Off(RF Off), 2=blinking");
 
 static const struct {
         u16 tpt;        /* Mb/s */
@@ -128,12 +127,13 @@ EXPORT_SYMBOL(iwl_led_start);
 int iwl_led_associate(struct iwl_priv *priv)
 {
         IWL_DEBUG_LED(priv, "Associated\n");
-        if (led_mode == IWL_LED_BLINK)
+        if (priv->cfg->led_mode == IWL_LED_BLINK)
                 priv->allow_blinking = 1;
         priv->last_blink_time = jiffies;
 
         return 0;
 }
+EXPORT_SYMBOL(iwl_led_associate);
 
 int iwl_led_disassociate(struct iwl_priv *priv)
 {
@@ -141,6 +141,7 @@ int iwl_led_disassociate(struct iwl_priv *priv)
 
         return 0;
 }
+EXPORT_SYMBOL(iwl_led_disassociate);
 
 /*
  * calculate blink rate according to last second Tx/Rx activities
@@ -221,5 +222,8 @@ void iwl_leds_init(struct iwl_priv *priv)
         priv->last_blink_rate = 0;
         priv->last_blink_time = 0;
         priv->allow_blinking = 0;
+        if (led_mode != IWL_LED_DEFAULT &&
+            led_mode != priv->cfg->led_mode)
+                priv->cfg->led_mode = led_mode;
 }
 EXPORT_SYMBOL(iwl_leds_init);
diff --git a/drivers/net/wireless/iwlwifi/iwl-led.h b/drivers/net/wireless/iwlwifi/iwl-led.h
index 49a70baa3fb6..9079b33486ef 100644
--- a/drivers/net/wireless/iwlwifi/iwl-led.h
+++ b/drivers/net/wireless/iwlwifi/iwl-led.h
@@ -47,14 +47,16 @@ enum led_type {
 
 /*
  * LED mode
- *    IWL_LED_BLINK:    adjust led blink rate based on blink table
+ *    IWL_LED_DEFAULT:  use system default
  *    IWL_LED_RF_STATE: turn LED on/off based on RF state
  *                      LED ON  = RF ON
  *                      LED OFF = RF OFF
+ *    IWL_LED_BLINK:    adjust led blink rate based on blink table
  */
 enum iwl_led_mode {
-        IWL_LED_BLINK,
+        IWL_LED_DEFAULT,
         IWL_LED_RF_STATE,
+        IWL_LED_BLINK,
 };
 
 void iwl_leds_init(struct iwl_priv *priv);
diff --git a/drivers/net/wireless/iwlwifi/iwl-legacy.c b/drivers/net/wireless/iwlwifi/iwl-legacy.c
new file mode 100644
index 000000000000..bb1a742a98a0
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-legacy.c
@@ -0,0 +1,662 @@
+/******************************************************************************
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
+ * USA
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * Contact Information:
+ *  Intel Linux Wireless <ilw@linux.intel.com>
+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+ *****************************************************************************/
+
+#include <linux/kernel.h>
+#include <net/mac80211.h>
+
+#include "iwl-dev.h"
+#include "iwl-core.h"
+#include "iwl-helpers.h"
+#include "iwl-legacy.h"
+
+static void iwl_update_qos(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
+{
+        if (test_bit(STATUS_EXIT_PENDING, &priv->status))
+                return;
+
+        if (!ctx->is_active)
+                return;
+
+        ctx->qos_data.def_qos_parm.qos_flags = 0;
+
+        if (ctx->qos_data.qos_active)
+                ctx->qos_data.def_qos_parm.qos_flags |=
+                        QOS_PARAM_FLG_UPDATE_EDCA_MSK;
+
+        if (ctx->ht.enabled)
+                ctx->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
+
+        IWL_DEBUG_QOS(priv, "send QoS cmd with Qos active=%d FLAGS=0x%X\n",
+                      ctx->qos_data.qos_active,
+                      ctx->qos_data.def_qos_parm.qos_flags);
+
+        iwl_send_cmd_pdu_async(priv, ctx->qos_cmd,
+                               sizeof(struct iwl_qosparam_cmd),
+                               &ctx->qos_data.def_qos_parm, NULL);
+}
+
+/**
+ * iwl_legacy_mac_config - mac80211 config callback
+ */
+int iwl_legacy_mac_config(struct ieee80211_hw *hw, u32 changed)
+{
+        struct iwl_priv *priv = hw->priv;
+        const struct iwl_channel_info *ch_info;
+        struct ieee80211_conf *conf = &hw->conf;
+        struct ieee80211_channel *channel = conf->channel;
+        struct iwl_ht_config *ht_conf = &priv->current_ht_config;
+        struct iwl_rxon_context *ctx;
+        unsigned long flags = 0;
+        int ret = 0;
+        u16 ch;
+        int scan_active = 0;
+        bool ht_changed[NUM_IWL_RXON_CTX] = {};
+
+        if (WARN_ON(!priv->cfg->ops->legacy))
+                return -EOPNOTSUPP;
+
+        mutex_lock(&priv->mutex);
+
+        IWL_DEBUG_MAC80211(priv, "enter to channel %d changed 0x%X\n",
+                                        channel->hw_value, changed);
+
+        if (unlikely(!priv->cfg->mod_params->disable_hw_scan &&
+                        test_bit(STATUS_SCANNING, &priv->status))) {
+                scan_active = 1;
+                IWL_DEBUG_MAC80211(priv, "leave - scanning\n");
+        }
+
+        if (changed & (IEEE80211_CONF_CHANGE_SMPS |
+                       IEEE80211_CONF_CHANGE_CHANNEL)) {
+                /* mac80211 uses static for non-HT which is what we want */
+                priv->current_ht_config.smps = conf->smps_mode;
+
+                /*
+                 * Recalculate chain counts.
+                 *
+                 * If monitor mode is enabled then mac80211 will
+                 * set up the SM PS mode to OFF if an HT channel is
+                 * configured.
+                 */
+                if (priv->cfg->ops->hcmd->set_rxon_chain)
+                        for_each_context(priv, ctx)
+                                priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
+        }
+
+        /* during scanning mac80211 will delay channel setting until
+         * scan finish with changed = 0
+         */
+        if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
+                if (scan_active)
+                        goto set_ch_out;
+
+                ch = channel->hw_value;
+                ch_info = iwl_get_channel_info(priv, channel->band, ch);
+                if (!is_channel_valid(ch_info)) {
+                        IWL_DEBUG_MAC80211(priv, "leave - invalid channel\n");
+                        ret = -EINVAL;
+                        goto set_ch_out;
+                }
+
+                spin_lock_irqsave(&priv->lock, flags);
+
+                for_each_context(priv, ctx) {
+                        /* Configure HT40 channels */
+                        if (ctx->ht.enabled != conf_is_ht(conf)) {
+                                ctx->ht.enabled = conf_is_ht(conf);
+                                ht_changed[ctx->ctxid] = true;
+                        }
+                        if (ctx->ht.enabled) {
+                                if (conf_is_ht40_minus(conf)) {
+                                        ctx->ht.extension_chan_offset =
+                                                IEEE80211_HT_PARAM_CHA_SEC_BELOW;
+                                        ctx->ht.is_40mhz = true;
+                                } else if (conf_is_ht40_plus(conf)) {
+                                        ctx->ht.extension_chan_offset =
+                                                IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
+                                        ctx->ht.is_40mhz = true;
+                                } else {
+                                        ctx->ht.extension_chan_offset =
+                                                IEEE80211_HT_PARAM_CHA_SEC_NONE;
+                                        ctx->ht.is_40mhz = false;
+                                }
+                        } else
+                                ctx->ht.is_40mhz = false;
+
+                        /*
+                         * Default to no protection. Protection mode will
+                         * later be set from BSS config in iwl_ht_conf
+                         */
+                        ctx->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
+
+                        /* if we are switching from ht to 2.4 clear flags
+                         * from any ht related info since 2.4 does not
+                         * support ht */
+                        if ((le16_to_cpu(ctx->staging.channel) != ch))
+                                ctx->staging.flags = 0;
+
+                        iwl_set_rxon_channel(priv, channel, ctx);
+                        iwl_set_rxon_ht(priv, ht_conf);
+
+                        iwl_set_flags_for_band(priv, ctx, channel->band,
+                                               ctx->vif);
+                }
+
+                spin_unlock_irqrestore(&priv->lock, flags);
+
+                if (priv->cfg->ops->legacy->update_bcast_stations)
+                        ret = priv->cfg->ops->legacy->update_bcast_stations(priv);
+
+ set_ch_out:
+                /* The list of supported rates and rate mask can be different
+                 * for each band; since the band may have changed, reset
+                 * the rate mask to what mac80211 lists */
+                iwl_set_rate(priv);
+        }
+
+        if (changed & (IEEE80211_CONF_CHANGE_PS |
+                        IEEE80211_CONF_CHANGE_IDLE)) {
+                ret = iwl_power_update_mode(priv, false);
+                if (ret)
+                        IWL_DEBUG_MAC80211(priv, "Error setting sleep level\n");
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_POWER) {
+                IWL_DEBUG_MAC80211(priv, "TX Power old=%d new=%d\n",
+                        priv->tx_power_user_lmt, conf->power_level);
+
+                iwl_set_tx_power(priv, conf->power_level, false);
+        }
+
+        if (!iwl_is_ready(priv)) {
+                IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
+                goto out;
+        }
+
+        if (scan_active)
+                goto out;
+
+        for_each_context(priv, ctx) {
+                if (memcmp(&ctx->active, &ctx->staging, sizeof(ctx->staging)))
+                        iwlcore_commit_rxon(priv, ctx);
+                else
+                        IWL_DEBUG_INFO(priv,
+                                "Not re-sending same RXON configuration.\n");
+                if (ht_changed[ctx->ctxid])
+                        iwl_update_qos(priv, ctx);
+        }
+
+out:
+        IWL_DEBUG_MAC80211(priv, "leave\n");
+        mutex_unlock(&priv->mutex);
+        return ret;
+}
+EXPORT_SYMBOL(iwl_legacy_mac_config);
+
+void iwl_legacy_mac_reset_tsf(struct ieee80211_hw *hw)
+{
+        struct iwl_priv *priv = hw->priv;
+        unsigned long flags;
+        /* IBSS can only be the IWL_RXON_CTX_BSS context */
+        struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
+
+        if (WARN_ON(!priv->cfg->ops->legacy))
+                return;
+
+        mutex_lock(&priv->mutex);
+        IWL_DEBUG_MAC80211(priv, "enter\n");
+
+        spin_lock_irqsave(&priv->lock, flags);
+        memset(&priv->current_ht_config, 0, sizeof(struct iwl_ht_config));
+        spin_unlock_irqrestore(&priv->lock, flags);
+
+        spin_lock_irqsave(&priv->lock, flags);
+
+        /* new association get rid of ibss beacon skb */
+        if (priv->beacon_skb)
+                dev_kfree_skb(priv->beacon_skb);
+
+        priv->beacon_skb = NULL;
+
+        priv->timestamp = 0;
+
+        spin_unlock_irqrestore(&priv->lock, flags);
+
+        iwl_scan_cancel_timeout(priv, 100);
+        if (!iwl_is_ready_rf(priv)) {
+                IWL_DEBUG_MAC80211(priv, "leave - not ready\n");
+                mutex_unlock(&priv->mutex);
+                return;
+        }
+
+        /* we are restarting association process
+         * clear RXON_FILTER_ASSOC_MSK bit
+         */
+        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+        iwlcore_commit_rxon(priv, ctx);
+
+        iwl_set_rate(priv);
+
+        mutex_unlock(&priv->mutex);
+
+        IWL_DEBUG_MAC80211(priv, "leave\n");
+}
+EXPORT_SYMBOL(iwl_legacy_mac_reset_tsf);
+
+static void iwl_ht_conf(struct iwl_priv *priv,
+                        struct ieee80211_vif *vif)
+{
+        struct iwl_ht_config *ht_conf = &priv->current_ht_config;
+        struct ieee80211_sta *sta;
+        struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
+
+        IWL_DEBUG_ASSOC(priv, "enter:\n");
+
+        if (!ctx->ht.enabled)
+                return;
+
+        ctx->ht.protection =
+                bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
+        ctx->ht.non_gf_sta_present =
+                !!(bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
+
+        ht_conf->single_chain_sufficient = false;
+
+        switch (vif->type) {
+        case NL80211_IFTYPE_STATION:
+                rcu_read_lock();
+                sta = ieee80211_find_sta(vif, bss_conf->bssid);
+                if (sta) {
+                        struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
+                        int maxstreams;
+
+                        maxstreams = (ht_cap->mcs.tx_params &
+                                      IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
+                                        >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
+                        maxstreams += 1;
+
+                        if ((ht_cap->mcs.rx_mask[1] == 0) &&
+                            (ht_cap->mcs.rx_mask[2] == 0))
+                                ht_conf->single_chain_sufficient = true;
+                        if (maxstreams <= 1)
+                                ht_conf->single_chain_sufficient = true;
+                } else {
+                        /*
+                         * If at all, this can only happen through a race
+                         * when the AP disconnects us while we're still
+                         * setting up the connection, in that case mac80211
+                         * will soon tell us about that.
+                         */
+                        ht_conf->single_chain_sufficient = true;
+                }
+                rcu_read_unlock();
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                ht_conf->single_chain_sufficient = true;
+                break;
+        default:
+                break;
+        }
+
+        IWL_DEBUG_ASSOC(priv, "leave\n");
+}
+
+static inline void iwl_set_no_assoc(struct iwl_priv *priv,
+                                    struct ieee80211_vif *vif)
+{
+        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
+
+        iwl_led_disassociate(priv);
+        /*
+         * inform the ucode that there is no longer an
+         * association and that no more packets should be
+         * sent
+         */
+        ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
+        ctx->staging.assoc_id = 0;
+        iwlcore_commit_rxon(priv, ctx);
+}
+
+static void iwlcore_beacon_update(struct ieee80211_hw *hw,
+                                  struct ieee80211_vif *vif)
+{
+        struct iwl_priv *priv = hw->priv;
+        unsigned long flags;
+        __le64 timestamp;
+        struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
+
+        if (!skb)
+                return;
+
+        IWL_DEBUG_MAC80211(priv, "enter\n");
+
+        lockdep_assert_held(&priv->mutex);
+
+        if (!priv->beacon_ctx) {
+                IWL_ERR(priv, "update beacon but no beacon context!\n");
+                dev_kfree_skb(skb);
+                return;
+        }
+
+        spin_lock_irqsave(&priv->lock, flags);
+
+        if (priv->beacon_skb)
+                dev_kfree_skb(priv->beacon_skb);
+
+        priv->beacon_skb = skb;
+
+        timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
+        priv->timestamp = le64_to_cpu(timestamp);
+
+        IWL_DEBUG_MAC80211(priv, "leave\n");
+        spin_unlock_irqrestore(&priv->lock, flags);
+
+        if (!iwl_is_ready_rf(priv)) {
+                IWL_DEBUG_MAC80211(priv, "leave - RF not ready\n");
+                return;
+        }
+
+        priv->cfg->ops->legacy->post_associate(priv);
+}
+
+void iwl_legacy_mac_bss_info_changed(struct ieee80211_hw *hw,
+                                     struct ieee80211_vif *vif,
+                                     struct ieee80211_bss_conf *bss_conf,
+                                     u32 changes)
+{
+        struct iwl_priv *priv = hw->priv;
+        struct iwl_rxon_context *ctx = iwl_rxon_ctx_from_vif(vif);
+        int ret;
+
+        if (WARN_ON(!priv->cfg->ops->legacy))
+                return;
+
+        IWL_DEBUG_MAC80211(priv, "changes = 0x%X\n", changes);
+
+        if (!iwl_is_alive(priv))
+                return;
+
+        mutex_lock(&priv->mutex);
+
+        if (changes & BSS_CHANGED_QOS) {
+                unsigned long flags;
+
+                spin_lock_irqsave(&priv->lock, flags);
+                ctx->qos_data.qos_active = bss_conf->qos;
+                iwl_update_qos(priv, ctx);
+                spin_unlock_irqrestore(&priv->lock, flags);
+        }
+
+        if (changes & BSS_CHANGED_BEACON_ENABLED) {
+                /*
+                 * the add_interface code must make sure we only ever
+                 * have a single interface that could be beaconing at
+                 * any time.
+                 */
+                if (vif->bss_conf.enable_beacon)
+                        priv->beacon_ctx = ctx;
+                else
+                        priv->beacon_ctx = NULL;
+        }
+
+        if (changes & BSS_CHANGED_BEACON && vif->type == NL80211_IFTYPE_AP) {
+                dev_kfree_skb(priv->beacon_skb);
+                priv->beacon_skb = ieee80211_beacon_get(hw, vif);
+        }
+
+        if (changes & BSS_CHANGED_BEACON_INT && vif->type == NL80211_IFTYPE_AP)
+                iwl_send_rxon_timing(priv, ctx);
+
+        if (changes & BSS_CHANGED_BSSID) {
+                IWL_DEBUG_MAC80211(priv, "BSSID %pM\n", bss_conf->bssid);
+
+                /*
+                 * If there is currently a HW scan going on in the
+                 * background then we need to cancel it else the RXON
+                 * below/in post_associate will fail.
+                 */
+                if (iwl_scan_cancel_timeout(priv, 100)) {
+                        IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
+                        IWL_DEBUG_MAC80211(priv, "leaving - scan abort failed.\n");
+                        mutex_unlock(&priv->mutex);
+                        return;
+                }
+
+                /* mac80211 only sets assoc when in STATION mode */
+                if (vif->type == NL80211_IFTYPE_ADHOC || bss_conf->assoc) {
+                        memcpy(ctx->staging.bssid_addr,
+                               bss_conf->bssid, ETH_ALEN);
+
+                        /* currently needed in a few places */
+                        memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
+                } else {
+                        ctx->staging.filter_flags &=
+                                ~RXON_FILTER_ASSOC_MSK;
+                }
+
+        }
+
+        /*
+         * This needs to be after setting the BSSID in case
+         * mac80211 decides to do both changes at once because
+         * it will invoke post_associate.
+         */
+        if (vif->type == NL80211_IFTYPE_ADHOC && changes & BSS_CHANGED_BEACON)
+                iwlcore_beacon_update(hw, vif);
+
+        if (changes & BSS_CHANGED_ERP_PREAMBLE) {
+                IWL_DEBUG_MAC80211(priv, "ERP_PREAMBLE %d\n",
+                                   bss_conf->use_short_preamble);
+                if (bss_conf->use_short_preamble)
+                        ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
+                else
+                        ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
+        }
+
+        if (changes & BSS_CHANGED_ERP_CTS_PROT) {
+                IWL_DEBUG_MAC80211(priv, "ERP_CTS %d\n", bss_conf->use_cts_prot);
+                if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
+                        ctx->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
+                else
+                        ctx->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
+                if (bss_conf->use_cts_prot)
+                        ctx->staging.flags |= RXON_FLG_SELF_CTS_EN;
+                else
+                        ctx->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
+        }
+
+        if (changes & BSS_CHANGED_BASIC_RATES) {
+                /* XXX use this information
+                 *
+                 * To do that, remove code from iwl_set_rate() and put something
+                 * like this here:
+                 *
+                if (A-band)
+                        ctx->staging.ofdm_basic_rates =
+                                bss_conf->basic_rates;
+                else
+                        ctx->staging.ofdm_basic_rates =
+                                bss_conf->basic_rates >> 4;
+                        ctx->staging.cck_basic_rates =
+                                bss_conf->basic_rates & 0xF;
+                 */
+        }
+
+        if (changes & BSS_CHANGED_HT) {
+                iwl_ht_conf(priv, vif);
+
+                if (priv->cfg->ops->hcmd->set_rxon_chain)
+                        priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
+        }
+
+        if (changes & BSS_CHANGED_ASSOC) {
+                IWL_DEBUG_MAC80211(priv, "ASSOC %d\n", bss_conf->assoc);
+                if (bss_conf->assoc) {
+                        priv->timestamp = bss_conf->timestamp;
+
+                        iwl_led_associate(priv);
+
+                        if (!iwl_is_rfkill(priv))
+                                priv->cfg->ops->legacy->post_associate(priv);
+                } else
+                        iwl_set_no_assoc(priv, vif);
+        }
+
+        if (changes && iwl_is_associated_ctx(ctx) && bss_conf->aid) {
+                IWL_DEBUG_MAC80211(priv, "Changes (%#x) while associated\n",
+                                   changes);
+                ret = iwl_send_rxon_assoc(priv, ctx);
+                if (!ret) {
+                        /* Sync active_rxon with latest change. */
+                        memcpy((void *)&ctx->active,
+                                &ctx->staging,
+                                sizeof(struct iwl_rxon_cmd));
+                }
+        }
+
+        if (changes & BSS_CHANGED_BEACON_ENABLED) {
+                if (vif->bss_conf.enable_beacon) {
+                        memcpy(ctx->staging.bssid_addr,
+                               bss_conf->bssid, ETH_ALEN);
+                        memcpy(priv->bssid, bss_conf->bssid, ETH_ALEN);
+                        iwl_led_associate(priv);
+                        priv->cfg->ops->legacy->config_ap(priv);
+                } else
+                        iwl_set_no_assoc(priv, vif);
+        }
+
+        if (changes & BSS_CHANGED_IBSS) {
+                ret = priv->cfg->ops->legacy->manage_ibss_station(priv, vif,
+                                                        bss_conf->ibss_joined);
+                if (ret)
+                        IWL_ERR(priv, "failed to %s IBSS station %pM\n",
+                                bss_conf->ibss_joined ? "add" : "remove",
+                                bss_conf->bssid);
+        }
+
+        mutex_unlock(&priv->mutex);
+
+        IWL_DEBUG_MAC80211(priv, "leave\n");
+}
+EXPORT_SYMBOL(iwl_legacy_mac_bss_info_changed);
+
+irqreturn_t iwl_isr_legacy(int irq, void *data)
+{
+        struct iwl_priv *priv = data;
+        u32 inta, inta_mask;
+        u32 inta_fh;
+        unsigned long flags;
+        if (!priv)
+                return IRQ_NONE;
+
+        spin_lock_irqsave(&priv->lock, flags);
+
+        /* Disable (but don't clear!) interrupts here to avoid
+         *    back-to-back ISRs and sporadic interrupts from our NIC.
+         * If we have something to service, the tasklet will re-enable ints.
+         * If we *don't* have something, we'll re-enable before leaving here. */
+        inta_mask = iwl_read32(priv, CSR_INT_MASK);  /* just for debug */
+        iwl_write32(priv, CSR_INT_MASK, 0x00000000);
+
+        /* Discover which interrupts are active/pending */
+        inta = iwl_read32(priv, CSR_INT);
+        inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
+
+        /* Ignore interrupt if there's nothing in NIC to service.
+         * This may be due to IRQ shared with another device,
+         * or due to sporadic interrupts thrown from our NIC. */
+        if (!inta && !inta_fh) {
+                IWL_DEBUG_ISR(priv,
+                        "Ignore interrupt, inta == 0, inta_fh == 0\n");
+                goto none;
+        }
+
+        if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
+                /* Hardware disappeared. It might have already raised
+                 * an interrupt */
+                IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
+                goto unplugged;
+        }
+
+        IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
+                      inta, inta_mask, inta_fh);
+
+        inta &= ~CSR_INT_BIT_SCD;
+
+        /* iwl_irq_tasklet() will service interrupts and re-enable them */
+        if (likely(inta || inta_fh))
+                tasklet_schedule(&priv->irq_tasklet);
+
+unplugged:
+        spin_unlock_irqrestore(&priv->lock, flags);
+        return IRQ_HANDLED;
+
+none:
+        /* re-enable interrupts here since we don't have anything to service. */
+        /* only Re-enable if disabled by irq */
+        if (test_bit(STATUS_INT_ENABLED, &priv->status))
+                iwl_enable_interrupts(priv);
+        spin_unlock_irqrestore(&priv->lock, flags);
+        return IRQ_NONE;
+}
+EXPORT_SYMBOL(iwl_isr_legacy);
+
+/*
+ *  iwl_legacy_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
+ *  function.
+ */
+void iwl_legacy_tx_cmd_protection(struct iwl_priv *priv,
+                               struct ieee80211_tx_info *info,
+                               __le16 fc, __le32 *tx_flags)
+{
+        if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
+                *tx_flags |= TX_CMD_FLG_RTS_MSK;
+                *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
+                *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
+
+                if (!ieee80211_is_mgmt(fc))
+                        return;
+
+                switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
+                case cpu_to_le16(IEEE80211_STYPE_AUTH):
+                case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
+                case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
+                case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
+                        *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
+                        *tx_flags |= TX_CMD_FLG_CTS_MSK;
+                        break;
+                }
+        } else if (info->control.rates[0].flags &
+                   IEEE80211_TX_RC_USE_CTS_PROTECT) {
+                *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
+                *tx_flags |= TX_CMD_FLG_CTS_MSK;
+                *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
+        }
+}
+EXPORT_SYMBOL(iwl_legacy_tx_cmd_protection);
diff --git a/drivers/net/wireless/iwlwifi/iwl-legacy.h b/drivers/net/wireless/iwlwifi/iwl-legacy.h
new file mode 100644
index 000000000000..9f7b2f935964
--- /dev/null
+++ b/drivers/net/wireless/iwlwifi/iwl-legacy.h
@@ -0,0 +1,79 @@
+/******************************************************************************
+ *
+ * This file is provided under a dual BSD/GPLv2 license.  When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
+ * USA
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * Contact Information:
+ *  Intel Linux Wireless <ilw@linux.intel.com>
+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2005 - 2010 Intel Corporation. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  * Neither the name Intel Corporation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+#ifndef __iwl_legacy_h__
+#define __iwl_legacy_h__
+
+/* mac80211 handlers */
+int iwl_legacy_mac_config(struct ieee80211_hw *hw, u32 changed);
+void iwl_legacy_mac_reset_tsf(struct ieee80211_hw *hw);
+void iwl_legacy_mac_bss_info_changed(struct ieee80211_hw *hw,
+                                     struct ieee80211_vif *vif,
+                                     struct ieee80211_bss_conf *bss_conf,
+                                     u32 changes);
+void iwl_legacy_tx_cmd_protection(struct iwl_priv *priv,
+                                struct ieee80211_tx_info *info,
+                                __le16 fc, __le32 *tx_flags);
+
+irqreturn_t iwl_isr_legacy(int irq, void *data);
+
+#endif /* __iwl_legacy_h__ */
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.c b/drivers/net/wireless/iwlwifi/iwl-power.c
index 49d7788937a9..1eec18d909d8 100644
--- a/drivers/net/wireless/iwlwifi/iwl-power.c
+++ b/drivers/net/wireless/iwlwifi/iwl-power.c
@@ -75,6 +75,10 @@ struct iwl_power_vec_entry {
 
 #define NOSLP cpu_to_le16(0), 0, 0
 #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
+#define ASLP (IWL_POWER_POWER_SAVE_ENA_MSK |    \
+                IWL_POWER_POWER_MANAGEMENT_ENA_MSK | \
+                IWL_POWER_ADVANCE_PM_ENA_MSK)
+#define ASLP_TOUT(T) cpu_to_le32(T)
 #define TU_TO_USEC 1024
 #define SLP_TOUT(T) cpu_to_le32((T) * TU_TO_USEC)
 #define SLP_VEC(X0, X1, X2, X3, X4) {cpu_to_le32(X0), \
@@ -114,6 +118,52 @@ static const struct iwl_power_vec_entry range_2[IWL_POWER_NUM] = {
         {{SLP, SLP_TOUT(25), SLP_TOUT(25), SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
 };
 
+/* advance power management */
+/* DTIM 0 - 2 */
+static const struct iwl_power_vec_entry apm_range_0[IWL_POWER_NUM] = {
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
+};
+
+
+/* for DTIM period IWL_DTIM_RANGE_0_MAX + 1 through IWL_DTIM_RANGE_1_MAX */
+/* DTIM 3 - 10 */
+static const struct iwl_power_vec_entry apm_range_1[IWL_POWER_NUM] = {
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 6, 8, 0xFF), 0}, 2}
+};
+
+/* for DTIM period > IWL_DTIM_RANGE_1_MAX */
+/* DTIM 11 - */
+static const struct iwl_power_vec_entry apm_range_2[IWL_POWER_NUM] = {
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 4, 6, 0xFF), 0}, 0},
+        {{ASLP, 0, 0, ASLP_TOUT(50), ASLP_TOUT(50),
+                SLP_VEC(1, 2, 6, 8, 0xFF), ASLP_TOUT(2)}, 2}
+};
+
 static void iwl_static_sleep_cmd(struct iwl_priv *priv,
                                  struct iwl_powertable_cmd *cmd,
                                  enum iwl_power_level lvl, int period)
@@ -124,11 +174,19 @@ static void iwl_static_sleep_cmd(struct iwl_priv *priv,
         u8 skip;
         u32 slp_itrvl;
 
-        table = range_2;
-        if (period <= IWL_DTIM_RANGE_1_MAX)
-                table = range_1;
-        if (period <= IWL_DTIM_RANGE_0_MAX)
-                table = range_0;
+        if (priv->cfg->adv_pm) {
+                table = apm_range_2;
+                if (period <= IWL_DTIM_RANGE_1_MAX)
+                        table = apm_range_1;
+                if (period <= IWL_DTIM_RANGE_0_MAX)
+                        table = apm_range_0;
+        } else {
+                table = range_2;
+                if (period <= IWL_DTIM_RANGE_1_MAX)
+                        table = range_1;
+                if (period <= IWL_DTIM_RANGE_0_MAX)
+                        table = range_0;
+        }
 
         BUG_ON(lvl < 0 || lvl >= IWL_POWER_NUM);
 
@@ -163,6 +221,20 @@ static void iwl_static_sleep_cmd(struct iwl_priv *priv,
         else
                 cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
 
+        if (priv->cfg->base_params->shadow_reg_enable)
+                cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
+        else
+                cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
+
+        if (priv->cfg->bt_params &&
+            priv->cfg->bt_params->advanced_bt_coexist) {
+                if (!priv->cfg->bt_params->bt_sco_disable)
+                        cmd->flags |= IWL_POWER_BT_SCO_ENA;
+                else
+                        cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
+        }
+
+
         slp_itrvl = le32_to_cpu(cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1]);
         if (slp_itrvl > IWL_CONN_MAX_LISTEN_INTERVAL)
                 cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1] =
@@ -236,6 +308,19 @@ static void iwl_power_fill_sleep_cmd(struct iwl_priv *priv,
         if (priv->power_data.pci_pm)
                 cmd->flags |= IWL_POWER_PCI_PM_MSK;
 
+        if (priv->cfg->base_params->shadow_reg_enable)
+                cmd->flags |= IWL_POWER_SHADOW_REG_ENA;
+        else
+                cmd->flags &= ~IWL_POWER_SHADOW_REG_ENA;
+
+        if (priv->cfg->bt_params &&
+            priv->cfg->bt_params->advanced_bt_coexist) {
+                if (!priv->cfg->bt_params->bt_sco_disable)
+                        cmd->flags |= IWL_POWER_BT_SCO_ENA;
+                else
+                        cmd->flags &= ~IWL_POWER_BT_SCO_ENA;
+        }
+
         cmd->rx_data_timeout = cpu_to_le32(1000 * dynps_ms);
         cmd->tx_data_timeout = cpu_to_le32(1000 * dynps_ms);
 
@@ -263,70 +348,95 @@ static int iwl_set_power(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd)
                                 sizeof(struct iwl_powertable_cmd), cmd);
 }
 
-/* priv->mutex must be held */
-int iwl_power_update_mode(struct iwl_priv *priv, bool force)
+static void iwl_power_build_cmd(struct iwl_priv *priv,
+                                struct iwl_powertable_cmd *cmd)
 {
-        int ret = 0;
         bool enabled = priv->hw->conf.flags & IEEE80211_CONF_PS;
-        bool update_chains;
-        struct iwl_powertable_cmd cmd;
         int dtimper;
 
-        /* Don't update the RX chain when chain noise calibration is running */
-        update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
-                        priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
-
         dtimper = priv->hw->conf.ps_dtim_period ?: 1;
 
         if (priv->cfg->base_params->broken_powersave)
-                iwl_power_sleep_cam_cmd(priv, &cmd);
+                iwl_power_sleep_cam_cmd(priv, cmd);
         else if (priv->cfg->base_params->supports_idle &&
                  priv->hw->conf.flags & IEEE80211_CONF_IDLE)
-                iwl_static_sleep_cmd(priv, &cmd, IWL_POWER_INDEX_5, 20);
+                iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_5, 20);
         else if (priv->cfg->ops->lib->tt_ops.lower_power_detection &&
                  priv->cfg->ops->lib->tt_ops.tt_power_mode &&
                  priv->cfg->ops->lib->tt_ops.lower_power_detection(priv)) {
                 /* in thermal throttling low power state */
-                iwl_static_sleep_cmd(priv, &cmd,
+                iwl_static_sleep_cmd(priv, cmd,
                     priv->cfg->ops->lib->tt_ops.tt_power_mode(priv), dtimper);
         } else if (!enabled)
-                iwl_power_sleep_cam_cmd(priv, &cmd);
+                iwl_power_sleep_cam_cmd(priv, cmd);
         else if (priv->power_data.debug_sleep_level_override >= 0)
-                iwl_static_sleep_cmd(priv, &cmd,
+                iwl_static_sleep_cmd(priv, cmd,
                                      priv->power_data.debug_sleep_level_override,
                                      dtimper);
         else if (no_sleep_autoadjust)
-                iwl_static_sleep_cmd(priv, &cmd, IWL_POWER_INDEX_1, dtimper);
+                iwl_static_sleep_cmd(priv, cmd, IWL_POWER_INDEX_1, dtimper);
         else
-                iwl_power_fill_sleep_cmd(priv, &cmd,
+                iwl_power_fill_sleep_cmd(priv, cmd,
                                          priv->hw->conf.dynamic_ps_timeout,
                                          priv->hw->conf.max_sleep_period);
+}
+
+int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
+                       bool force)
+{
+        int ret;
+        bool update_chains;
+
+        lockdep_assert_held(&priv->mutex);
+
+        /* Don't update the RX chain when chain noise calibration is running */
+        update_chains = priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE ||
+                        priv->chain_noise_data.state == IWL_CHAIN_NOISE_ALIVE;
+
+        if (!memcmp(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
+                return 0;
+
+        if (!iwl_is_ready_rf(priv))
+                return -EIO;
 
-        if (iwl_is_ready_rf(priv) &&
-            (memcmp(&priv->power_data.sleep_cmd, &cmd, sizeof(cmd)) || force)) {
-                if (cmd.flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
-                        set_bit(STATUS_POWER_PMI, &priv->status);
-
-                ret = iwl_set_power(priv, &cmd);
-                if (!ret) {
-                        if (!(cmd.flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
-                                clear_bit(STATUS_POWER_PMI, &priv->status);
-
-                        if (priv->cfg->ops->lib->update_chain_flags &&
-                            update_chains)
-                                priv->cfg->ops->lib->update_chain_flags(priv);
-                        else if (priv->cfg->ops->lib->update_chain_flags)
-                                IWL_DEBUG_POWER(priv,
+        /* scan complete use sleep_power_next, need to be updated */
+        memcpy(&priv->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
+        if (test_bit(STATUS_SCANNING, &priv->status) && !force) {
+                IWL_DEBUG_INFO(priv, "Defer power set mode while scanning\n");
+                return 0;
+        }
+
+        if (cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK)
+                set_bit(STATUS_POWER_PMI, &priv->status);
+
+        ret = iwl_set_power(priv, cmd);
+        if (!ret) {
+                if (!(cmd->flags & IWL_POWER_DRIVER_ALLOW_SLEEP_MSK))
+                        clear_bit(STATUS_POWER_PMI, &priv->status);
+
+                if (priv->cfg->ops->lib->update_chain_flags && update_chains)
+                        priv->cfg->ops->lib->update_chain_flags(priv);
+                else if (priv->cfg->ops->lib->update_chain_flags)
+                        IWL_DEBUG_POWER(priv,
                                         "Cannot update the power, chain noise "
                                         "calibration running: %d\n",
                                         priv->chain_noise_data.state);
-                        memcpy(&priv->power_data.sleep_cmd, &cmd, sizeof(cmd));
-                } else
-                        IWL_ERR(priv, "set power fail, ret = %d", ret);
-        }
+
+                memcpy(&priv->power_data.sleep_cmd, cmd, sizeof(*cmd));
+        } else
+                IWL_ERR(priv, "set power fail, ret = %d", ret);
 
         return ret;
 }
+EXPORT_SYMBOL(iwl_power_set_mode);
+
+int iwl_power_update_mode(struct iwl_priv *priv, bool force)
+{
+        struct iwl_powertable_cmd cmd;
+
+        iwl_power_build_cmd(priv, &cmd);
+        return iwl_power_set_mode(priv, &cmd, force);
+}
 EXPORT_SYMBOL(iwl_power_update_mode);
 
 /* initialize to default */
diff --git a/drivers/net/wireless/iwlwifi/iwl-power.h b/drivers/net/wireless/iwlwifi/iwl-power.h
index df81565a7cc4..fe012032c28c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-power.h
+++ b/drivers/net/wireless/iwlwifi/iwl-power.h
@@ -41,10 +41,13 @@ enum iwl_power_level {
 
 struct iwl_power_mgr {
         struct iwl_powertable_cmd sleep_cmd;
+        struct iwl_powertable_cmd sleep_cmd_next;
         int debug_sleep_level_override;
         bool pci_pm;
 };
 
+int iwl_power_set_mode(struct iwl_priv *priv, struct iwl_powertable_cmd *cmd,
+                       bool force);
 int iwl_power_update_mode(struct iwl_priv *priv, bool force);
 void iwl_power_initialize(struct iwl_priv *priv);
 
diff --git a/drivers/net/wireless/iwlwifi/iwl-prph.h b/drivers/net/wireless/iwlwifi/iwl-prph.h
index 5469655646ae..86f5123bccda 100644
--- a/drivers/net/wireless/iwlwifi/iwl-prph.h
+++ b/drivers/net/wireless/iwlwifi/iwl-prph.h
@@ -83,10 +83,10 @@
 #define APMG_DIGITAL_SVR_REG            (APMG_BASE + 0x0058)
 #define APMG_ANALOG_SVR_REG             (APMG_BASE + 0x006C)
 
+#define APMS_CLK_VAL_MRB_FUNC_MODE      (0x00000001)
 #define APMG_CLK_VAL_DMA_CLK_RQT        (0x00000200)
 #define APMG_CLK_VAL_BSM_CLK_RQT        (0x00000800)
 
-
 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS    (0x00400000)
 #define APMG_PS_CTRL_VAL_RESET_REQ              (0x04000000)
 #define APMG_PS_CTRL_MSK_PWR_SRC                (0x03000000)
diff --git a/drivers/net/wireless/iwlwifi/iwl-rx.c b/drivers/net/wireless/iwlwifi/iwl-rx.c
index f436270ca39a..87a6fd84d4d2 100644
--- a/drivers/net/wireless/iwlwifi/iwl-rx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-rx.c
@@ -134,28 +134,37 @@ void iwl_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q
         if (q->need_update == 0)
                 goto exit_unlock;
 
-        /* If power-saving is in use, make sure device is awake */
-        if (test_bit(STATUS_POWER_PMI, &priv->status)) {
-                reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
+        if (priv->cfg->base_params->shadow_reg_enable) {
+                /* shadow register enabled */
+                /* Device expects a multiple of 8 */
+                q->write_actual = (q->write & ~0x7);
+                iwl_write32(priv, rx_wrt_ptr_reg, q->write_actual);
+        } else {
+                /* If power-saving is in use, make sure device is awake */
+                if (test_bit(STATUS_POWER_PMI, &priv->status)) {
+                        reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
 
-                if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
-                        IWL_DEBUG_INFO(priv, "Rx queue requesting wakeup, GP1 = 0x%x\n",
-                                      reg);
-                        iwl_set_bit(priv, CSR_GP_CNTRL,
-                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
-                        goto exit_unlock;
-                }
+                        if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
+                                IWL_DEBUG_INFO(priv,
+                                        "Rx queue requesting wakeup,"
+                                        " GP1 = 0x%x\n", reg);
+                                iwl_set_bit(priv, CSR_GP_CNTRL,
+                                        CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+                                goto exit_unlock;
+                        }
 
-                q->write_actual = (q->write & ~0x7);
-                iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
+                        q->write_actual = (q->write & ~0x7);
+                        iwl_write_direct32(priv, rx_wrt_ptr_reg,
+                                        q->write_actual);
 
-        /* Else device is assumed to be awake */
-        } else {
-                /* Device expects a multiple of 8 */
-                q->write_actual = (q->write & ~0x7);
-                iwl_write_direct32(priv, rx_wrt_ptr_reg, q->write_actual);
+                /* Else device is assumed to be awake */
+                } else {
+                        /* Device expects a multiple of 8 */
+                        q->write_actual = (q->write & ~0x7);
+                        iwl_write_direct32(priv, rx_wrt_ptr_reg,
+                                q->write_actual);
+                }
         }
-
         q->need_update = 0;
 
  exit_unlock:
diff --git a/drivers/net/wireless/iwlwifi/iwl-scan.c b/drivers/net/wireless/iwlwifi/iwl-scan.c
index 67da31295781..12d9363d0afe 100644
--- a/drivers/net/wireless/iwlwifi/iwl-scan.c
+++ b/drivers/net/wireless/iwlwifi/iwl-scan.c
@@ -252,8 +252,7 @@ static void iwl_rx_scan_complete_notif(struct iwl_priv *priv,
 
         IWL_DEBUG_SCAN(priv, "Scan on %sGHz took %dms\n",
                        (priv->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
-                       jiffies_to_msecs(elapsed_jiffies
-                                        (priv->scan_start, jiffies)));
+                       jiffies_to_msecs(jiffies - priv->scan_start));
 
         queue_work(priv->workqueue, &priv->scan_completed);
 
@@ -603,13 +602,16 @@ out_settings:
         if (!iwl_is_ready_rf(priv))
                 goto out;
 
-        /* Since setting the TXPOWER may have been deferred while
-         * performing the scan, fire one off */
-        iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
+        /*
+         * We do not commit power settings while scan is pending,
+         * do it now if the settings changed.
+         */
+        iwl_power_set_mode(priv, &priv->power_data.sleep_cmd_next, false);
+        iwl_set_tx_power(priv, priv->tx_power_next, false);
 
         priv->cfg->ops->utils->post_scan(priv);
 
- out:
+out:
         mutex_unlock(&priv->mutex);
 }
 
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.c b/drivers/net/wireless/iwlwifi/iwl-sta.c
index 972b738c0e4a..49493d176515 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.c
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.c
@@ -400,7 +400,8 @@ static void iwl_sta_ucode_deactivate(struct iwl_priv *priv, u8 sta_id)
 }
 
 static int iwl_send_remove_station(struct iwl_priv *priv,
-                                   const u8 *addr, int sta_id)
+                                   const u8 *addr, int sta_id,
+                                   bool temporary)
 {
         struct iwl_rx_packet *pkt;
         int ret;
@@ -436,9 +437,11 @@ static int iwl_send_remove_station(struct iwl_priv *priv,
         if (!ret) {
                 switch (pkt->u.rem_sta.status) {
                 case REM_STA_SUCCESS_MSK:
-                        spin_lock_irqsave(&priv->sta_lock, flags_spin);
-                        iwl_sta_ucode_deactivate(priv, sta_id);
-                        spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
+                        if (!temporary) {
+                                spin_lock_irqsave(&priv->sta_lock, flags_spin);
+                                iwl_sta_ucode_deactivate(priv, sta_id);
+                                spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
+                        }
                         IWL_DEBUG_ASSOC(priv, "REPLY_REMOVE_STA PASSED\n");
                         break;
                 default:
@@ -505,7 +508,7 @@ int iwl_remove_station(struct iwl_priv *priv, const u8 sta_id,
 
         spin_unlock_irqrestore(&priv->sta_lock, flags);
 
-        return iwl_send_remove_station(priv, addr, sta_id);
+        return iwl_send_remove_station(priv, addr, sta_id, false);
 out_err:
         spin_unlock_irqrestore(&priv->sta_lock, flags);
         return -EINVAL;
@@ -624,6 +627,49 @@ void iwl_restore_stations(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
 }
 EXPORT_SYMBOL(iwl_restore_stations);
 
+void iwl_reprogram_ap_sta(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
+{
+        unsigned long flags;
+        int sta_id = ctx->ap_sta_id;
+        int ret;
+        struct iwl_addsta_cmd sta_cmd;
+        struct iwl_link_quality_cmd lq;
+        bool active;
+
+        spin_lock_irqsave(&priv->sta_lock, flags);
+        if (!(priv->stations[sta_id].used & IWL_STA_DRIVER_ACTIVE)) {
+                spin_unlock_irqrestore(&priv->sta_lock, flags);
+                return;
+        }
+
+        memcpy(&sta_cmd, &priv->stations[sta_id].sta, sizeof(sta_cmd));
+        sta_cmd.mode = 0;
+        memcpy(&lq, priv->stations[sta_id].lq, sizeof(lq));
+
+        active = priv->stations[sta_id].used & IWL_STA_UCODE_ACTIVE;
+        priv->stations[sta_id].used &= ~IWL_STA_DRIVER_ACTIVE;
+        spin_unlock_irqrestore(&priv->sta_lock, flags);
+
+        if (active) {
+                ret = iwl_send_remove_station(
+                        priv, priv->stations[sta_id].sta.sta.addr,
+                        sta_id, true);
+                if (ret)
+                        IWL_ERR(priv, "failed to remove STA %pM (%d)\n",
+                                priv->stations[sta_id].sta.sta.addr, ret);
+        }
+        spin_lock_irqsave(&priv->sta_lock, flags);
+        priv->stations[sta_id].used |= IWL_STA_DRIVER_ACTIVE;
+        spin_unlock_irqrestore(&priv->sta_lock, flags);
+
+        ret = iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
+        if (ret)
+                IWL_ERR(priv, "failed to re-add STA %pM (%d)\n",
+                        priv->stations[sta_id].sta.sta.addr, ret);
+        iwl_send_lq_cmd(priv, ctx, &lq, CMD_SYNC, true);
+}
+EXPORT_SYMBOL(iwl_reprogram_ap_sta);
+
 int iwl_get_free_ucode_key_index(struct iwl_priv *priv)
 {
         int i;
@@ -736,6 +782,14 @@ int iwl_send_lq_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
         if (WARN_ON(lq->sta_id == IWL_INVALID_STATION))
                 return -EINVAL;
 
+
+        spin_lock_irqsave(&priv->sta_lock, flags_spin);
+        if (!(priv->stations[lq->sta_id].used & IWL_STA_DRIVER_ACTIVE)) {
+                spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
+                return -EINVAL;
+        }
+        spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
+
         iwl_dump_lq_cmd(priv, lq);
         BUG_ON(init && (cmd.flags & CMD_ASYNC));
 
diff --git a/drivers/net/wireless/iwlwifi/iwl-sta.h b/drivers/net/wireless/iwlwifi/iwl-sta.h
index 06475872eee4..206f1e1a0caf 100644
--- a/drivers/net/wireless/iwlwifi/iwl-sta.h
+++ b/drivers/net/wireless/iwlwifi/iwl-sta.h
@@ -63,6 +63,7 @@ u8 iwl_prep_station(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
 
 int iwl_send_lq_cmd(struct iwl_priv *priv, struct iwl_rxon_context *ctx,
                     struct iwl_link_quality_cmd *lq, u8 flags, bool init);
+void iwl_reprogram_ap_sta(struct iwl_priv *priv, struct iwl_rxon_context *ctx);
 
 /**
  * iwl_clear_driver_stations - clear knowledge of all stations from driver
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index 7261ee49f282..073b6ce6141c 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -49,30 +49,39 @@ void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
         if (txq->need_update == 0)
                 return;
 
-        /* if we're trying to save power */
-        if (test_bit(STATUS_POWER_PMI, &priv->status)) {
-                /* wake up nic if it's powered down ...
-                 * uCode will wake up, and interrupt us again, so next
-                 * time we'll skip this part. */
-                reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
-
-                if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
-                        IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
-                                      txq_id, reg);
-                        iwl_set_bit(priv, CSR_GP_CNTRL,
-                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
-                        return;
-                }
-
-                iwl_write_direct32(priv, HBUS_TARG_WRPTR,
-                                     txq->q.write_ptr | (txq_id << 8));
-
-        /* else not in power-save mode, uCode will never sleep when we're
-         * trying to tx (during RFKILL, we're not trying to tx). */
-        } else
+        if (priv->cfg->base_params->shadow_reg_enable) {
+                /* shadow register enabled */
                 iwl_write32(priv, HBUS_TARG_WRPTR,
                             txq->q.write_ptr | (txq_id << 8));
+        } else {
+                /* if we're trying to save power */
+                if (test_bit(STATUS_POWER_PMI, &priv->status)) {
+                        /* wake up nic if it's powered down ...
+                         * uCode will wake up, and interrupt us again, so next
+                         * time we'll skip this part. */
+                        reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
+
+                        if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
+                                IWL_DEBUG_INFO(priv,
+                                        "Tx queue %d requesting wakeup,"
+                                        " GP1 = 0x%x\n", txq_id, reg);
+                                iwl_set_bit(priv, CSR_GP_CNTRL,
+                                        CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+                                return;
+                        }
+
+                        iwl_write_direct32(priv, HBUS_TARG_WRPTR,
+                                     txq->q.write_ptr | (txq_id << 8));
 
+                /*
+                 * else not in power-save mode,
+                 * uCode will never sleep when we're
+                 * trying to tx (during RFKILL, we're not trying to tx).
+                 */
+                } else
+                        iwl_write32(priv, HBUS_TARG_WRPTR,
+                                    txq->q.write_ptr | (txq_id << 8));
+        }
         txq->need_update = 0;
 }
 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
@@ -254,8 +263,6 @@ static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
                 q->high_mark = 2;
 
         q->write_ptr = q->read_ptr = 0;
-        q->last_read_ptr = 0;
-        q->repeat_same_read_ptr = 0;
 
         return 0;
 }
@@ -350,13 +357,12 @@ int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
         txq->need_update = 0;
 
         /*
-         * Aggregation TX queues will get their ID when aggregation begins;
-         * they overwrite the setting done here. The command FIFO doesn't
-         * need an swq_id so don't set one to catch errors, all others can
-         * be set up to the identity mapping.
+         * For the default queues 0-3, set up the swq_id
+         * already -- all others need to get one later
+         * (if they need one at all).
          */
-        if (txq_id != priv->cmd_queue)
-                txq->swq_id = txq_id;
+        if (txq_id < 4)
+                iwl_set_swq_id(txq, txq_id, txq_id);
 
         /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
          * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index 7edf8c2fb8c7..371abbf60eac 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -61,6 +61,7 @@
 #include "iwl-helpers.h"
 #include "iwl-dev.h"
 #include "iwl-spectrum.h"
+#include "iwl-legacy.h"
 
 /*
  * module name, copyright, version, etc.
@@ -474,7 +475,7 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
         dma_addr_t phys_addr;
         dma_addr_t txcmd_phys;
         int txq_id = skb_get_queue_mapping(skb);
-        u16 len, idx, len_org, hdr_len; /* TODO: len_org is not used */
+        u16 len, idx, hdr_len;
         u8 id;
         u8 unicast;
         u8 sta_id;
@@ -611,15 +612,8 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
          */
         len = sizeof(struct iwl3945_tx_cmd) +
                         sizeof(struct iwl_cmd_header) + hdr_len;
-
-        len_org = len;
         len = (len + 3) & ~3;
 
-        if (len_org != len)
-                len_org = 1;
-        else
-                len_org = 0;
-
         /* Physical address of this Tx command's header (not MAC header!),
          * within command buffer array. */
         txcmd_phys = pci_map_single(priv->pci_dev, &out_cmd->hdr,
@@ -661,7 +655,7 @@ static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
                         spin_unlock_irqrestore(&priv->lock, flags);
                 }
 
-                iwl_stop_queue(priv, skb_get_queue_mapping(skb));
+                iwl_stop_queue(priv, txq);
         }
 
         return 0;
@@ -2515,13 +2509,8 @@ static void iwl3945_alive_start(struct iwl_priv *priv)
         /* After the ALIVE response, we can send commands to 3945 uCode */
         set_bit(STATUS_ALIVE, &priv->status);
 
-        if (priv->cfg->ops->lib->recover_from_tx_stall) {
-                /* Enable timer to monitor the driver queues */
-                mod_timer(&priv->monitor_recover,
-                        jiffies +
-                        msecs_to_jiffies(
-                          priv->cfg->base_params->monitor_recover_period));
-        }
+        /* Enable watchdog to monitor the driver tx queues */
+        iwl_setup_watchdog(priv);
 
         if (iwl_is_rfkill(priv))
                 return;
@@ -2578,8 +2567,7 @@ static void __iwl3945_down(struct iwl_priv *priv)
 
         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
          * to prevent rearm timer */
-        if (priv->cfg->ops->lib->recover_from_tx_stall)
-                del_timer_sync(&priv->monitor_recover);
+        del_timer_sync(&priv->watchdog);
 
         /* Station information will now be cleared in device */
         iwl_clear_ucode_stations(priv, NULL);
@@ -3057,22 +3045,22 @@ static void iwl3945_bg_rx_replenish(struct work_struct *data)
         mutex_unlock(&priv->mutex);
 }
 
-void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
+void iwl3945_post_associate(struct iwl_priv *priv)
 {
         int rc = 0;
         struct ieee80211_conf *conf = NULL;
         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
 
-        if (!vif || !priv->is_open)
+        if (!ctx->vif || !priv->is_open)
                 return;
 
-        if (vif->type == NL80211_IFTYPE_AP) {
+        if (ctx->vif->type == NL80211_IFTYPE_AP) {
                 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
                 return;
         }
 
         IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
-                        vif->bss_conf.aid, ctx->active.bssid_addr);
+                        ctx->vif->bss_conf.aid, ctx->active.bssid_addr);
 
         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
                 return;
@@ -3091,18 +3079,18 @@ void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
 
         ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
 
-        ctx->staging.assoc_id = cpu_to_le16(vif->bss_conf.aid);
+        ctx->staging.assoc_id = cpu_to_le16(ctx->vif->bss_conf.aid);
 
         IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
-                        vif->bss_conf.aid, vif->bss_conf.beacon_int);
+                        ctx->vif->bss_conf.aid, ctx->vif->bss_conf.beacon_int);
 
-        if (vif->bss_conf.use_short_preamble)
+        if (ctx->vif->bss_conf.use_short_preamble)
                 ctx->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
         else
                 ctx->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
 
         if (ctx->staging.flags & RXON_FLG_BAND_24G_MSK) {
-                if (vif->bss_conf.use_short_slot)
+                if (ctx->vif->bss_conf.use_short_slot)
                         ctx->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
                 else
                         ctx->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
@@ -3110,7 +3098,7 @@ void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
 
         iwl3945_commit_rxon(priv, ctx);
 
-        switch (vif->type) {
+        switch (ctx->vif->type) {
         case NL80211_IFTYPE_STATION:
                 iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
                 break;
@@ -3119,7 +3107,7 @@ void iwl3945_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
                 break;
         default:
                 IWL_ERR(priv, "%s Should not be called in %d mode\n",
-                        __func__, vif->type);
+                        __func__, ctx->vif->type);
                 break;
         }
 }
@@ -3234,9 +3222,10 @@ static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         return NETDEV_TX_OK;
 }
 
-void iwl3945_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
+void iwl3945_config_ap(struct iwl_priv *priv)
 {
         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
+        struct ieee80211_vif *vif = ctx->vif;
         int rc = 0;
 
         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
@@ -3407,9 +3396,9 @@ static void iwl3945_configure_filter(struct ieee80211_hw *hw,
         ctx->staging.filter_flags |= filter_or;
 
         /*
-         * Committing directly here breaks for some reason,
-         * but we'll eventually commit the filter flags
-         * change anyway.
+         * Not committing directly because hardware can perform a scan,
+         * but even if hw is ready, committing here breaks for some reason,
+         * we'll eventually commit the filter flags change anyway.
          */
 
         mutex_unlock(&priv->mutex);
@@ -3780,12 +3769,9 @@ static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
 
         iwl3945_hw_setup_deferred_work(priv);
 
-        if (priv->cfg->ops->lib->recover_from_tx_stall) {
-                init_timer(&priv->monitor_recover);
-                priv->monitor_recover.data = (unsigned long)priv;
-                priv->monitor_recover.function =
-                        priv->cfg->ops->lib->recover_from_tx_stall;
-        }
+        init_timer(&priv->watchdog);
+        priv->watchdog.data = (unsigned long)priv;
+        priv->watchdog.function = iwl_bg_watchdog;
 
         tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
                      iwl3945_irq_tasklet, (unsigned long)priv);
@@ -3824,18 +3810,19 @@ static struct attribute_group iwl3945_attribute_group = {
         .attrs = iwl3945_sysfs_entries,
 };
 
-static struct ieee80211_ops iwl3945_hw_ops = {
+struct ieee80211_ops iwl3945_hw_ops = {
         .tx = iwl3945_mac_tx,
         .start = iwl3945_mac_start,
         .stop = iwl3945_mac_stop,
         .add_interface = iwl_mac_add_interface,
         .remove_interface = iwl_mac_remove_interface,
-        .config = iwl_mac_config,
+        .change_interface = iwl_mac_change_interface,
+        .config = iwl_legacy_mac_config,
         .configure_filter = iwl3945_configure_filter,
         .set_key = iwl3945_mac_set_key,
         .conf_tx = iwl_mac_conf_tx,
-        .reset_tsf = iwl_mac_reset_tsf,
-        .bss_info_changed = iwl_bss_info_changed,
+        .reset_tsf = iwl_legacy_mac_reset_tsf,
+        .bss_info_changed = iwl_legacy_mac_bss_info_changed,
         .hw_scan = iwl_mac_hw_scan,
         .sta_add = iwl3945_mac_sta_add,
         .sta_remove = iwl_mac_sta_remove,
@@ -3865,7 +3852,15 @@ static int iwl3945_init_drv(struct iwl_priv *priv)
         priv->iw_mode = NL80211_IFTYPE_STATION;
         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
 
+        /* initialize force reset */
+        priv->force_reset[IWL_RF_RESET].reset_duration =
+                IWL_DELAY_NEXT_FORCE_RF_RESET;
+        priv->force_reset[IWL_FW_RESET].reset_duration =
+                IWL_DELAY_NEXT_FORCE_FW_RELOAD;
+
+
         priv->tx_power_user_lmt = IWL_DEFAULT_TX_POWER;
+        priv->tx_power_next = IWL_DEFAULT_TX_POWER;
 
         if (eeprom->version < EEPROM_3945_EEPROM_VERSION) {
                 IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
@@ -3965,7 +3960,7 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
 
         /* mac80211 allocates memory for this device instance, including
          *   space for this driver's private structure */
-        hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
+        hw = iwl_alloc_all(cfg);
         if (hw == NULL) {
                 pr_err("Can not allocate network device\n");
                 err = -ENOMEM;
@@ -4117,7 +4112,7 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e
 
         pci_enable_msi(priv->pci_dev);
 
-        err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
+        err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
                           IRQF_SHARED, DRV_NAME, priv);
         if (err) {
                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
@@ -4275,10 +4270,7 @@ static struct pci_driver iwl3945_driver = {
         .id_table = iwl3945_hw_card_ids,
         .probe = iwl3945_pci_probe,
         .remove = __devexit_p(iwl3945_pci_remove),
-#ifdef CONFIG_PM
-        .suspend = iwl_pci_suspend,
-        .resume = iwl_pci_resume,
-#endif
+        .driver.pm = IWL_PM_OPS,
 };
 
 static int __init iwl3945_init(void)
diff --git a/drivers/net/wireless/iwmc3200wifi/cfg80211.c b/drivers/net/wireless/iwmc3200wifi/cfg80211.c
index c6c0eff9b5ed..5a4982271e96 100644
--- a/drivers/net/wireless/iwmc3200wifi/cfg80211.c
+++ b/drivers/net/wireless/iwmc3200wifi/cfg80211.c
@@ -225,7 +225,8 @@ static int iwm_cfg80211_del_key(struct wiphy *wiphy, struct net_device *ndev,
 
 static int iwm_cfg80211_set_default_key(struct wiphy *wiphy,
                                         struct net_device *ndev,
-                                        u8 key_index)
+                                        u8 key_index, bool unicast,
+                                        bool multicast)
 {
         struct iwm_priv *iwm = ndev_to_iwm(ndev);
 
diff --git a/drivers/net/wireless/iwmc3200wifi/commands.c b/drivers/net/wireless/iwmc3200wifi/commands.c
index 330c7d9cf101..50dee6a0a5ca 100644
--- a/drivers/net/wireless/iwmc3200wifi/commands.c
+++ b/drivers/net/wireless/iwmc3200wifi/commands.c
@@ -908,7 +908,7 @@ int iwm_scan_ssids(struct iwm_priv *iwm, struct cfg80211_ssid *ssids,
                 return ret;
         }
 
-        iwm->scan_id = iwm->scan_id++ % IWM_SCAN_ID_MAX;
+        iwm->scan_id = (iwm->scan_id + 1) % IWM_SCAN_ID_MAX;
 
         return 0;
 }
diff --git a/drivers/net/wireless/libertas/cfg.c b/drivers/net/wireless/libertas/cfg.c
index 373930afc26b..698a1f7694ed 100644
--- a/drivers/net/wireless/libertas/cfg.c
+++ b/drivers/net/wireless/libertas/cfg.c
@@ -9,8 +9,6 @@
 #include <linux/sched.h>
 #include <linux/wait.h>
 #include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/wait.h>
 #include <linux/ieee80211.h>
 #include <net/cfg80211.h>
 #include <asm/unaligned.h>
@@ -619,7 +617,7 @@ static int lbs_ret_scan(struct lbs_private *priv, unsigned long dummy,
                                      print_ssid(ssid_buf, ssid, ssid_len),
                                      LBS_SCAN_RSSI_TO_MBM(rssi)/100);
 
-                        if (channel ||
+                        if (channel &&
                             !(channel->flags & IEEE80211_CHAN_DISABLED))
                                 cfg80211_inform_bss(wiphy, channel,
                                         bssid, le64_to_cpu(*(__le64 *)tsfdesc),
@@ -1424,7 +1422,8 @@ static int lbs_cfg_disconnect(struct wiphy *wiphy, struct net_device *dev,
 
 static int lbs_cfg_set_default_key(struct wiphy *wiphy,
                                    struct net_device *netdev,
-                                   u8 key_index)
+                                   u8 key_index, bool unicast,
+                                   bool multicast)
 {
         struct lbs_private *priv = wiphy_priv(wiphy);
 
@@ -2062,7 +2061,7 @@ static void lbs_cfg_set_regulatory_hint(struct lbs_private *priv)
         };
 
         /* Section 5.17.2 */
-        static struct region_code_mapping regmap[] = {
+        static const struct region_code_mapping regmap[] = {
                 {"US ", 0x10}, /* US FCC */
                 {"CA ", 0x20}, /* Canada */
                 {"EU ", 0x30}, /* ETSI   */
diff --git a/drivers/net/wireless/libertas/cmd.c b/drivers/net/wireless/libertas/cmd.c
index 70745928f3f8..78c4da150a74 100644
--- a/drivers/net/wireless/libertas/cmd.c
+++ b/drivers/net/wireless/libertas/cmd.c
@@ -177,6 +177,14 @@ int lbs_host_sleep_cfg(struct lbs_private *priv, uint32_t criteria,
         struct cmd_ds_host_sleep cmd_config;
         int ret;
 
+        /*
+         * Certain firmware versions do not support EHS_REMOVE_WAKEUP command
+         * and the card will return a failure.  Since we need to be
+         * able to reset the mask, in those cases we set a 0 mask instead.
+         */
+        if (criteria == EHS_REMOVE_WAKEUP && !priv->ehs_remove_supported)
+                criteria = 0;
+
         cmd_config.hdr.size = cpu_to_le16(sizeof(cmd_config));
         cmd_config.criteria = cpu_to_le32(criteria);
         cmd_config.gpio = priv->wol_gpio;
diff --git a/drivers/net/wireless/libertas/dev.h b/drivers/net/wireless/libertas/dev.h
index cb14c38caf3a..18dd9a02c459 100644
--- a/drivers/net/wireless/libertas/dev.h
+++ b/drivers/net/wireless/libertas/dev.h
@@ -138,6 +138,7 @@ struct lbs_private {
         uint32_t wol_criteria;
         uint8_t wol_gpio;
         uint8_t wol_gap;
+        bool ehs_remove_supported;
 
         /* Transmitting */
         int tx_pending_len;             /* -1 while building packet */
diff --git a/drivers/net/wireless/libertas/if_spi.c b/drivers/net/wireless/libertas/if_spi.c
index ecd4d04b2c3c..00600239a053 100644
--- a/drivers/net/wireless/libertas/if_spi.c
+++ b/drivers/net/wireless/libertas/if_spi.c
@@ -784,7 +784,7 @@ static int lbs_spi_thread(void *data)
                                 up(&card->spi_thread_terminated);
                                 do_exit(0);
                         }
-                } while (err == EINTR);
+                } while (err == -EINTR);
 
                 /* Read the host interrupt status register to see what we
                  * can do. */
diff --git a/drivers/net/wireless/libertas/if_usb.c b/drivers/net/wireless/libertas/if_usb.c
index efaf85032208..6524c70363d9 100644
--- a/drivers/net/wireless/libertas/if_usb.c
+++ b/drivers/net/wireless/libertas/if_usb.c
@@ -345,6 +345,13 @@ static int if_usb_probe(struct usb_interface *intf,
         if (device_create_file(&priv->dev->dev, &dev_attr_lbs_flash_boot2))
                 lbs_pr_err("cannot register lbs_flash_boot2 attribute\n");
 
+        /*
+         * EHS_REMOVE_WAKEUP is not supported on all versions of the firmware.
+         */
+        priv->wol_criteria = EHS_REMOVE_WAKEUP;
+        if (lbs_host_sleep_cfg(priv, priv->wol_criteria, NULL))
+                priv->ehs_remove_supported = false;
+
         return 0;
 
 err_start_card:
@@ -1090,12 +1097,6 @@ static int if_usb_suspend(struct usb_interface *intf, pm_message_t message)
         if (priv->psstate != PS_STATE_FULL_POWER)
                 return -1;
 
-        if (priv->wol_criteria == EHS_REMOVE_WAKEUP) {
-                lbs_pr_info("Suspend attempt without "
-                                                "configuring wake params!\n");
-                return -ENOSYS;
-        }
-
         ret = lbs_suspend(priv);
         if (ret)
                 goto out;
diff --git a/drivers/net/wireless/libertas/main.c b/drivers/net/wireless/libertas/main.c
index fcd1bbfc632d..6836a6dd9853 100644
--- a/drivers/net/wireless/libertas/main.c
+++ b/drivers/net/wireless/libertas/main.c
@@ -851,9 +851,10 @@ struct lbs_private *lbs_add_card(void *card, struct device *dmdev)
         priv->work_thread = create_singlethread_workqueue("lbs_worker");
         INIT_WORK(&priv->mcast_work, lbs_set_mcast_worker);
 
-        priv->wol_criteria = 0xffffffff;
+        priv->wol_criteria = EHS_REMOVE_WAKEUP;
         priv->wol_gpio = 0xff;
         priv->wol_gap = 20;
+        priv->ehs_remove_supported = true;
 
         goto done;
 
diff --git a/drivers/net/wireless/libertas/rx.c b/drivers/net/wireless/libertas/rx.c
index a4d0bca9ef2c..a2b1df21d286 100644
--- a/drivers/net/wireless/libertas/rx.c
+++ b/drivers/net/wireless/libertas/rx.c
@@ -55,7 +55,9 @@ int lbs_process_rxed_packet(struct lbs_private *priv, struct sk_buff *skb)
         struct rxpd *p_rx_pd;
         int hdrchop;
         struct ethhdr *p_ethhdr;
-        const u8 rfc1042_eth_hdr[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
+        static const u8 rfc1042_eth_hdr[] = {
+                0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00
+        };
 
         lbs_deb_enter(LBS_DEB_RX);
 
diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c
index 7eaaa3bab547..454f045ddff3 100644
--- a/drivers/net/wireless/mac80211_hwsim.c
+++ b/drivers/net/wireless/mac80211_hwsim.c
@@ -309,6 +309,8 @@ struct mac80211_hwsim_data {
          */
         u64 group;
         struct dentry *debugfs_group;
+
+        int power_level;
 };
 
 
@@ -497,7 +499,7 @@ static bool mac80211_hwsim_tx_frame(struct ieee80211_hw *hw,
         rx_status.band = data->channel->band;
         rx_status.rate_idx = info->control.rates[0].idx;
         /* TODO: simulate real signal strength (and optional packet loss) */
-        rx_status.signal = -50;
+        rx_status.signal = data->power_level - 50;
 
         if (data->ps != PS_DISABLED)
                 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
@@ -698,6 +700,7 @@ static int mac80211_hwsim_config(struct ieee80211_hw *hw, u32 changed)
         data->idle = !!(conf->flags & IEEE80211_CONF_IDLE);
 
         data->channel = conf->channel;
+        data->power_level = conf->power_level;
         if (!data->started || !data->beacon_int)
                 del_timer(&data->beacon_timer);
         else
diff --git a/drivers/net/wireless/mwl8k.c b/drivers/net/wireless/mwl8k.c
index f152a25be59f..9ecf8407cb1b 100644
--- a/drivers/net/wireless/mwl8k.c
+++ b/drivers/net/wireless/mwl8k.c
@@ -29,6 +29,12 @@
 #define MWL8K_NAME      KBUILD_MODNAME
 #define MWL8K_VERSION   "0.12"
 
+/* Module parameters */
+static unsigned ap_mode_default;
+module_param(ap_mode_default, bool, 0);
+MODULE_PARM_DESC(ap_mode_default,
+                 "Set to 1 to make ap mode the default instead of sta mode");
+
 /* Register definitions */
 #define MWL8K_HIU_GEN_PTR                       0x00000c10
 #define  MWL8K_MODE_STA                          0x0000005a
@@ -92,8 +98,10 @@ struct rxd_ops {
 struct mwl8k_device_info {
         char *part_name;
         char *helper_image;
-        char *fw_image;
+        char *fw_image_sta;
+        char *fw_image_ap;
         struct rxd_ops *ap_rxd_ops;
+        u32 fw_api_ap;
 };
 
 struct mwl8k_rx_queue {
@@ -136,8 +144,8 @@ struct mwl8k_priv {
         void __iomem *regs;
 
         /* firmware */
-        struct firmware *fw_helper;
-        struct firmware *fw_ucode;
+        const struct firmware *fw_helper;
+        const struct firmware *fw_ucode;
 
         /* hardware/firmware parameters */
         bool ap_fw;
@@ -210,6 +218,18 @@ struct mwl8k_priv {
 
         /* Most recently reported noise in dBm */
         s8 noise;
+
+        /*
+         * preserve the queue configurations so they can be restored if/when
+         * the firmware image is swapped.
+         */
+        struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_QUEUES];
+
+        /* async firmware loading state */
+        unsigned fw_state;
+        char *fw_pref;
+        char *fw_alt;
+        struct completion firmware_loading_complete;
 };
 
 /* Per interface specific private data */
@@ -285,8 +305,9 @@ static const struct ieee80211_rate mwl8k_rates_50[] = {
 };
 
 /* Set or get info from Firmware */
-#define MWL8K_CMD_SET                   0x0001
 #define MWL8K_CMD_GET                   0x0000
+#define MWL8K_CMD_SET                   0x0001
+#define MWL8K_CMD_SET_LIST              0x0002
 
 /* Firmware command codes */
 #define MWL8K_CMD_CODE_DNLD             0x0001
@@ -296,6 +317,7 @@ static const struct ieee80211_rate mwl8k_rates_50[] = {
 #define MWL8K_CMD_GET_STAT              0x0014
 #define MWL8K_CMD_RADIO_CONTROL         0x001c
 #define MWL8K_CMD_RF_TX_POWER           0x001e
+#define MWL8K_CMD_TX_POWER              0x001f
 #define MWL8K_CMD_RF_ANTENNA            0x0020
 #define MWL8K_CMD_SET_BEACON            0x0100          /* per-vif */
 #define MWL8K_CMD_SET_PRE_SCAN          0x0107
@@ -333,6 +355,7 @@ static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
                 MWL8K_CMDNAME(GET_STAT);
                 MWL8K_CMDNAME(RADIO_CONTROL);
                 MWL8K_CMDNAME(RF_TX_POWER);
+                MWL8K_CMDNAME(TX_POWER);
                 MWL8K_CMDNAME(RF_ANTENNA);
                 MWL8K_CMDNAME(SET_BEACON);
                 MWL8K_CMDNAME(SET_PRE_SCAN);
@@ -372,7 +395,7 @@ static void mwl8k_hw_reset(struct mwl8k_priv *priv)
 }
 
 /* Release fw image */
-static void mwl8k_release_fw(struct firmware **fw)
+static void mwl8k_release_fw(const struct firmware **fw)
 {
         if (*fw == NULL)
                 return;
@@ -386,37 +409,68 @@ static void mwl8k_release_firmware(struct mwl8k_priv *priv)
         mwl8k_release_fw(&priv->fw_helper);
 }
 
+/* states for asynchronous f/w loading */
+static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
+enum {
+        FW_STATE_INIT = 0,
+        FW_STATE_LOADING_PREF,
+        FW_STATE_LOADING_ALT,
+        FW_STATE_ERROR,
+};
+
 /* Request fw image */
 static int mwl8k_request_fw(struct mwl8k_priv *priv,
-                            const char *fname, struct firmware **fw)
+                            const char *fname, const struct firmware **fw,
+                            bool nowait)
 {
         /* release current image */
         if (*fw != NULL)
                 mwl8k_release_fw(fw);
 
-        return request_firmware((const struct firmware **)fw,
-                                fname, &priv->pdev->dev);
+        if (nowait)
+                return request_firmware_nowait(THIS_MODULE, 1, fname,
+                                               &priv->pdev->dev, GFP_KERNEL,
+                                               priv, mwl8k_fw_state_machine);
+        else
+                return request_firmware(fw, fname, &priv->pdev->dev);
 }
 
-static int mwl8k_request_firmware(struct mwl8k_priv *priv)
+static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
+                                  bool nowait)
 {
         struct mwl8k_device_info *di = priv->device_info;
         int rc;
 
         if (di->helper_image != NULL) {
-                rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
-                if (rc) {
-                        printk(KERN_ERR "%s: Error requesting helper "
-                               "firmware file %s\n", pci_name(priv->pdev),
-                               di->helper_image);
+                if (nowait)
+                        rc = mwl8k_request_fw(priv, di->helper_image,
+                                              &priv->fw_helper, true);
+                else
+                        rc = mwl8k_request_fw(priv, di->helper_image,
+                                              &priv->fw_helper, false);
+                if (rc)
+                        printk(KERN_ERR "%s: Error requesting helper fw %s\n",
+                               pci_name(priv->pdev), di->helper_image);
+
+                if (rc || nowait)
                         return rc;
-                }
         }
 
-        rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
+        if (nowait) {
+                /*
+                 * if we get here, no helper image is needed.  Skip the
+                 * FW_STATE_INIT state.
+                 */
+                priv->fw_state = FW_STATE_LOADING_PREF;
+                rc = mwl8k_request_fw(priv, fw_image,
+                                      &priv->fw_ucode,
+                                      true);
+        } else
+                rc = mwl8k_request_fw(priv, fw_image,
+                                      &priv->fw_ucode, false);
         if (rc) {
                 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
-                       pci_name(priv->pdev), di->fw_image);
+                       pci_name(priv->pdev), fw_image);
                 mwl8k_release_fw(&priv->fw_helper);
                 return rc;
         }
@@ -577,12 +631,12 @@ static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
 static int mwl8k_load_firmware(struct ieee80211_hw *hw)
 {
         struct mwl8k_priv *priv = hw->priv;
-        struct firmware *fw = priv->fw_ucode;
+        const struct firmware *fw = priv->fw_ucode;
         int rc;
         int loops;
 
         if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
-                struct firmware *helper = priv->fw_helper;
+                const struct firmware *helper = priv->fw_helper;
 
                 if (helper == NULL) {
                         printk(KERN_ERR "%s: helper image needed but none "
@@ -1811,6 +1865,7 @@ struct mwl8k_cmd_get_hw_spec_ap {
         __le32 wcbbase1;
         __le32 wcbbase2;
         __le32 wcbbase3;
+        __le32 fw_api_version;
 } __packed;
 
 static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
@@ -1818,6 +1873,7 @@ static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
         struct mwl8k_priv *priv = hw->priv;
         struct mwl8k_cmd_get_hw_spec_ap *cmd;
         int rc;
+        u32 api_version;
 
         cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
         if (cmd == NULL)
@@ -1834,6 +1890,16 @@ static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
         if (!rc) {
                 int off;
 
+                api_version = le32_to_cpu(cmd->fw_api_version);
+                if (priv->device_info->fw_api_ap != api_version) {
+                        printk(KERN_ERR "%s: Unsupported fw API version for %s."
+                               "  Expected %d got %d.\n", MWL8K_NAME,
+                               priv->device_info->part_name,
+                               priv->device_info->fw_api_ap,
+                               api_version);
+                        rc = -EINVAL;
+                        goto done;
+                }
                 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
                 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
                 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
@@ -1861,6 +1927,7 @@ static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
                 iowrite32(priv->txq[3].txd_dma, priv->sram + off);
         }
 
+done:
         kfree(cmd);
         return rc;
 }
@@ -2084,7 +2151,7 @@ mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
 /*
  * CMD_RF_TX_POWER.
  */
-#define MWL8K_TX_POWER_LEVEL_TOTAL      8
+#define MWL8K_RF_TX_POWER_LEVEL_TOTAL   8
 
 struct mwl8k_cmd_rf_tx_power {
         struct mwl8k_cmd_pkt header;
@@ -2092,7 +2159,7 @@ struct mwl8k_cmd_rf_tx_power {
         __le16 support_level;
         __le16 current_level;
         __le16 reserved;
-        __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
+        __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
 } __packed;
 
 static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
@@ -2116,6 +2183,65 @@ static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
 }
 
 /*
+ * CMD_TX_POWER.
+ */
+#define MWL8K_TX_POWER_LEVEL_TOTAL      12
+
+struct mwl8k_cmd_tx_power {
+        struct mwl8k_cmd_pkt header;
+        __le16 action;
+        __le16 band;
+        __le16 channel;
+        __le16 bw;
+        __le16 sub_ch;
+        __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
+} __attribute__((packed));
+
+static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
+                                     struct ieee80211_conf *conf,
+                                     unsigned short pwr)
+{
+        struct ieee80211_channel *channel = conf->channel;
+        struct mwl8k_cmd_tx_power *cmd;
+        int rc;
+        int i;
+
+        cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+        if (cmd == NULL)
+                return -ENOMEM;
+
+        cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
+        cmd->header.length = cpu_to_le16(sizeof(*cmd));
+        cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
+
+        if (channel->band == IEEE80211_BAND_2GHZ)
+                cmd->band = cpu_to_le16(0x1);
+        else if (channel->band == IEEE80211_BAND_5GHZ)
+                cmd->band = cpu_to_le16(0x4);
+
+        cmd->channel = channel->hw_value;
+
+        if (conf->channel_type == NL80211_CHAN_NO_HT ||
+            conf->channel_type == NL80211_CHAN_HT20) {
+                cmd->bw = cpu_to_le16(0x2);
+        } else {
+                cmd->bw = cpu_to_le16(0x4);
+                if (conf->channel_type == NL80211_CHAN_HT40MINUS)
+                        cmd->sub_ch = cpu_to_le16(0x3);
+                else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
+                        cmd->sub_ch = cpu_to_le16(0x1);
+        }
+
+        for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
+                cmd->power_level_list[i] = cpu_to_le16(pwr);
+
+        rc = mwl8k_post_cmd(hw, &cmd->header);
+        kfree(cmd);
+
+        return rc;
+}
+
+/*
  * CMD_RF_ANTENNA.
  */
 struct mwl8k_cmd_rf_antenna {
@@ -3283,13 +3409,16 @@ static void mwl8k_stop(struct ieee80211_hw *hw)
                 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
 }
 
+static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
+
 static int mwl8k_add_interface(struct ieee80211_hw *hw,
                                struct ieee80211_vif *vif)
 {
         struct mwl8k_priv *priv = hw->priv;
         struct mwl8k_vif *mwl8k_vif;
         u32 macids_supported;
-        int macid;
+        int macid, rc;
+        struct mwl8k_device_info *di;
 
         /*
          * Reject interface creation if sniffer mode is active, as
@@ -3302,12 +3431,28 @@ static int mwl8k_add_interface(struct ieee80211_hw *hw,
                 return -EINVAL;
         }
 
-
+        di = priv->device_info;
         switch (vif->type) {
         case NL80211_IFTYPE_AP:
+                if (!priv->ap_fw && di->fw_image_ap) {
+                        /* we must load the ap fw to meet this request */
+                        if (!list_empty(&priv->vif_list))
+                                return -EBUSY;
+                        rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
+                        if (rc)
+                                return rc;
+                }
                 macids_supported = priv->ap_macids_supported;
                 break;
         case NL80211_IFTYPE_STATION:
+                if (priv->ap_fw && di->fw_image_sta) {
+                        /* we must load the sta fw to meet this request */
+                        if (!list_empty(&priv->vif_list))
+                                return -EBUSY;
+                        rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
+                        if (rc)
+                                return rc;
+                }
                 macids_supported = priv->sta_macids_supported;
                 break;
         default:
@@ -3377,15 +3522,19 @@ static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
 
         if (conf->power_level > 18)
                 conf->power_level = 18;
-        rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
-        if (rc)
-                goto out;
 
         if (priv->ap_fw) {
+                rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
+                if (rc)
+                        goto out;
+
                 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
                 if (!rc)
                         rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
         } else {
+                rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
+                if (rc)
+                        goto out;
                 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
         }
 
@@ -3739,6 +3888,9 @@ static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
 
         rc = mwl8k_fw_lock(hw);
         if (!rc) {
+                BUG_ON(queue > MWL8K_TX_QUEUES - 1);
+                memcpy(&priv->wmm_params[queue], params, sizeof(*params));
+
                 if (!priv->wmm_enabled)
                         rc = mwl8k_cmd_set_wmm_mode(hw, 1);
 
@@ -3838,21 +3990,27 @@ enum {
         MWL8366,
 };
 
+#define MWL8K_8366_AP_FW_API 1
+#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
+#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
+
 static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
         [MWL8363] = {
                 .part_name      = "88w8363",
                 .helper_image   = "mwl8k/helper_8363.fw",
-                .fw_image       = "mwl8k/fmimage_8363.fw",
+                .fw_image_sta   = "mwl8k/fmimage_8363.fw",
         },
         [MWL8687] = {
                 .part_name      = "88w8687",
                 .helper_image   = "mwl8k/helper_8687.fw",
-                .fw_image       = "mwl8k/fmimage_8687.fw",
+                .fw_image_sta   = "mwl8k/fmimage_8687.fw",
         },
         [MWL8366] = {
                 .part_name      = "88w8366",
                 .helper_image   = "mwl8k/helper_8366.fw",
-                .fw_image       = "mwl8k/fmimage_8366.fw",
+                .fw_image_sta   = "mwl8k/fmimage_8366.fw",
+                .fw_image_ap    = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
+                .fw_api_ap      = MWL8K_8366_AP_FW_API,
                 .ap_rxd_ops     = &rxd_8366_ap_ops,
         },
 };
@@ -3863,6 +4021,7 @@ MODULE_FIRMWARE("mwl8k/helper_8687.fw");
 MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
 MODULE_FIRMWARE("mwl8k/helper_8366.fw");
 MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
+MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
 
 static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
         { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
@@ -3876,94 +4035,133 @@ static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
 };
 MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
 
-static int __devinit mwl8k_probe(struct pci_dev *pdev,
-                                 const struct pci_device_id *id)
+static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
 {
-        static int printed_version = 0;
-        struct ieee80211_hw *hw;
-        struct mwl8k_priv *priv;
         int rc;
-        int i;
-
-        if (!printed_version) {
-                printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
-                printed_version = 1;
-        }
-
-
-        rc = pci_enable_device(pdev);
+        printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
+               "Trying alternative firmware %s\n", pci_name(priv->pdev),
+               priv->fw_pref, priv->fw_alt);
+        rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
         if (rc) {
-                printk(KERN_ERR "%s: Cannot enable new PCI device\n",
-                       MWL8K_NAME);
+                printk(KERN_ERR "%s: Error requesting alt fw %s\n",
+                       pci_name(priv->pdev), priv->fw_alt);
                 return rc;
         }
+        return 0;
+}
 
-        rc = pci_request_regions(pdev, MWL8K_NAME);
-        if (rc) {
-                printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
-                       MWL8K_NAME);
-                goto err_disable_device;
-        }
-
-        pci_set_master(pdev);
-
-
-        hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
-        if (hw == NULL) {
-                printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
-                rc = -ENOMEM;
-                goto err_free_reg;
-        }
+static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
+static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
+{
+        struct mwl8k_priv *priv = context;
+        struct mwl8k_device_info *di = priv->device_info;
+        int rc;
 
-        SET_IEEE80211_DEV(hw, &pdev->dev);
-        pci_set_drvdata(pdev, hw);
+        switch (priv->fw_state) {
+        case FW_STATE_INIT:
+                if (!fw) {
+                        printk(KERN_ERR "%s: Error requesting helper fw %s\n",
+                               pci_name(priv->pdev), di->helper_image);
+                        goto fail;
+                }
+                priv->fw_helper = fw;
+                rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
+                                      true);
+                if (rc && priv->fw_alt) {
+                        rc = mwl8k_request_alt_fw(priv);
+                        if (rc)
+                                goto fail;
+                        priv->fw_state = FW_STATE_LOADING_ALT;
+                } else if (rc)
+                        goto fail;
+                else
+                        priv->fw_state = FW_STATE_LOADING_PREF;
+                break;
 
-        priv = hw->priv;
-        priv->hw = hw;
-        priv->pdev = pdev;
-        priv->device_info = &mwl8k_info_tbl[id->driver_data];
+        case FW_STATE_LOADING_PREF:
+                if (!fw) {
+                        if (priv->fw_alt) {
+                                rc = mwl8k_request_alt_fw(priv);
+                                if (rc)
+                                        goto fail;
+                                priv->fw_state = FW_STATE_LOADING_ALT;
+                        } else
+                                goto fail;
+                } else {
+                        priv->fw_ucode = fw;
+                        rc = mwl8k_firmware_load_success(priv);
+                        if (rc)
+                                goto fail;
+                        else
+                                complete(&priv->firmware_loading_complete);
+                }
+                break;
 
+        case FW_STATE_LOADING_ALT:
+                if (!fw) {
+                        printk(KERN_ERR "%s: Error requesting alt fw %s\n",
+                               pci_name(priv->pdev), di->helper_image);
+                        goto fail;
+                }
+                priv->fw_ucode = fw;
+                rc = mwl8k_firmware_load_success(priv);
+                if (rc)
+                        goto fail;
+                else
+                        complete(&priv->firmware_loading_complete);
+                break;
 
-        priv->sram = pci_iomap(pdev, 0, 0x10000);
-        if (priv->sram == NULL) {
-                wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
-                goto err_iounmap;
+        default:
+                printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
+                       MWL8K_NAME, priv->fw_state);
+                BUG_ON(1);
         }
 
-        /*
-         * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
-         * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
-         */
-        priv->regs = pci_iomap(pdev, 1, 0x10000);
-        if (priv->regs == NULL) {
-                priv->regs = pci_iomap(pdev, 2, 0x10000);
-                if (priv->regs == NULL) {
-                        wiphy_err(hw->wiphy, "Cannot map device registers\n");
-                        goto err_iounmap;
-                }
-        }
+        return;
 
+fail:
+        priv->fw_state = FW_STATE_ERROR;
+        complete(&priv->firmware_loading_complete);
+        device_release_driver(&priv->pdev->dev);
+        mwl8k_release_firmware(priv);
+}
+
+static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
+                               bool nowait)
+{
+        struct mwl8k_priv *priv = hw->priv;
+        int rc;
 
         /* Reset firmware and hardware */
         mwl8k_hw_reset(priv);
 
         /* Ask userland hotplug daemon for the device firmware */
-        rc = mwl8k_request_firmware(priv);
+        rc = mwl8k_request_firmware(priv, fw_image, nowait);
         if (rc) {
                 wiphy_err(hw->wiphy, "Firmware files not found\n");
-                goto err_stop_firmware;
+                return rc;
         }
 
+        if (nowait)
+                return rc;
+
         /* Load firmware into hardware */
         rc = mwl8k_load_firmware(hw);
-        if (rc) {
+        if (rc)
                 wiphy_err(hw->wiphy, "Cannot start firmware\n");
-                goto err_stop_firmware;
-        }
 
         /* Reclaim memory once firmware is successfully loaded */
         mwl8k_release_firmware(priv);
 
+        return rc;
+}
+
+/* initialize hw after successfully loading a firmware image */
+static int mwl8k_probe_hw(struct ieee80211_hw *hw)
+{
+        struct mwl8k_priv *priv = hw->priv;
+        int rc = 0;
+        int i;
 
         if (priv->ap_fw) {
                 priv->rxd_ops = priv->device_info->ap_rxd_ops;
@@ -3980,58 +4178,11 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
         priv->wmm_enabled = false;
         priv->pending_tx_pkts = 0;
 
-
-        /*
-         * Extra headroom is the size of the required DMA header
-         * minus the size of the smallest 802.11 frame (CTS frame).
-         */
-        hw->extra_tx_headroom =
-                sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
-
-        hw->channel_change_time = 10;
-
-        hw->queues = MWL8K_TX_QUEUES;
-
-        /* Set rssi values to dBm */
-        hw->flags |= IEEE80211_HW_SIGNAL_DBM;
-        hw->vif_data_size = sizeof(struct mwl8k_vif);
-        hw->sta_data_size = sizeof(struct mwl8k_sta);
-
-        priv->macids_used = 0;
-        INIT_LIST_HEAD(&priv->vif_list);
-
-        /* Set default radio state and preamble */
-        priv->radio_on = 0;
-        priv->radio_short_preamble = 0;
-
-        /* Finalize join worker */
-        INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
-
-        /* TX reclaim and RX tasklets.  */
-        tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
-        tasklet_disable(&priv->poll_tx_task);
-        tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
-        tasklet_disable(&priv->poll_rx_task);
-
-        /* Power management cookie */
-        priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
-        if (priv->cookie == NULL)
-                goto err_stop_firmware;
-
         rc = mwl8k_rxq_init(hw, 0);
         if (rc)
-                goto err_free_cookie;
+                goto err_stop_firmware;
         rxq_refill(hw, 0, INT_MAX);
 
-        mutex_init(&priv->fw_mutex);
-        priv->fw_mutex_owner = NULL;
-        priv->fw_mutex_depth = 0;
-        priv->hostcmd_wait = NULL;
-
-        spin_lock_init(&priv->tx_lock);
-
-        priv->tx_wait = NULL;
-
         for (i = 0; i < MWL8K_TX_QUEUES; i++) {
                 rc = mwl8k_txq_init(hw, i);
                 if (rc)
@@ -4071,13 +4222,6 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
                 goto err_free_irq;
         }
 
-        hw->wiphy->interface_modes = 0;
-        if (priv->ap_macids_supported)
-                hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
-        if (priv->sta_macids_supported)
-                hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
-
-
         /* Turn radio off */
         rc = mwl8k_cmd_radio_disable(hw);
         if (rc) {
@@ -4096,12 +4240,6 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
         iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
         free_irq(priv->pdev->irq, hw);
 
-        rc = ieee80211_register_hw(hw);
-        if (rc) {
-                wiphy_err(hw->wiphy, "Cannot register device\n");
-                goto err_free_queues;
-        }
-
         wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
                    priv->device_info->part_name,
                    priv->hw_rev, hw->wiphy->perm_addr,
@@ -4120,14 +4258,238 @@ err_free_queues:
                 mwl8k_txq_deinit(hw, i);
         mwl8k_rxq_deinit(hw, 0);
 
+err_stop_firmware:
+        mwl8k_hw_reset(priv);
+
+        return rc;
+}
+
+/*
+ * invoke mwl8k_reload_firmware to change the firmware image after the device
+ * has already been registered
+ */
+static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
+{
+        int i, rc = 0;
+        struct mwl8k_priv *priv = hw->priv;
+
+        mwl8k_stop(hw);
+        mwl8k_rxq_deinit(hw, 0);
+
+        for (i = 0; i < MWL8K_TX_QUEUES; i++)
+                mwl8k_txq_deinit(hw, i);
+
+        rc = mwl8k_init_firmware(hw, fw_image, false);
+        if (rc)
+                goto fail;
+
+        rc = mwl8k_probe_hw(hw);
+        if (rc)
+                goto fail;
+
+        rc = mwl8k_start(hw);
+        if (rc)
+                goto fail;
+
+        rc = mwl8k_config(hw, ~0);
+        if (rc)
+                goto fail;
+
+        for (i = 0; i < MWL8K_TX_QUEUES; i++) {
+                rc = mwl8k_conf_tx(hw, i, &priv->wmm_params[i]);
+                if (rc)
+                        goto fail;
+        }
+
+        return rc;
+
+fail:
+        printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
+        return rc;
+}
+
+static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
+{
+        struct ieee80211_hw *hw = priv->hw;
+        int i, rc;
+
+        rc = mwl8k_load_firmware(hw);
+        mwl8k_release_firmware(priv);
+        if (rc) {
+                wiphy_err(hw->wiphy, "Cannot start firmware\n");
+                return rc;
+        }
+
+        /*
+         * Extra headroom is the size of the required DMA header
+         * minus the size of the smallest 802.11 frame (CTS frame).
+         */
+        hw->extra_tx_headroom =
+                sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
+
+        hw->channel_change_time = 10;
+
+        hw->queues = MWL8K_TX_QUEUES;
+
+        /* Set rssi values to dBm */
+        hw->flags |= IEEE80211_HW_SIGNAL_DBM;
+        hw->vif_data_size = sizeof(struct mwl8k_vif);
+        hw->sta_data_size = sizeof(struct mwl8k_sta);
+
+        priv->macids_used = 0;
+        INIT_LIST_HEAD(&priv->vif_list);
+
+        /* Set default radio state and preamble */
+        priv->radio_on = 0;
+        priv->radio_short_preamble = 0;
+
+        /* Finalize join worker */
+        INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
+
+        /* TX reclaim and RX tasklets.  */
+        tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
+        tasklet_disable(&priv->poll_tx_task);
+        tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
+        tasklet_disable(&priv->poll_rx_task);
+
+        /* Power management cookie */
+        priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
+        if (priv->cookie == NULL)
+                return -ENOMEM;
+
+        mutex_init(&priv->fw_mutex);
+        priv->fw_mutex_owner = NULL;
+        priv->fw_mutex_depth = 0;
+        priv->hostcmd_wait = NULL;
+
+        spin_lock_init(&priv->tx_lock);
+
+        priv->tx_wait = NULL;
+
+        rc = mwl8k_probe_hw(hw);
+        if (rc)
+                goto err_free_cookie;
+
+        hw->wiphy->interface_modes = 0;
+        if (priv->ap_macids_supported || priv->device_info->fw_image_ap)
+                hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
+        if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
+                hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
+
+        rc = ieee80211_register_hw(hw);
+        if (rc) {
+                wiphy_err(hw->wiphy, "Cannot register device\n");
+                goto err_unprobe_hw;
+        }
+
+        return 0;
+
+err_unprobe_hw:
+        for (i = 0; i < MWL8K_TX_QUEUES; i++)
+                mwl8k_txq_deinit(hw, i);
+        mwl8k_rxq_deinit(hw, 0);
+
 err_free_cookie:
         if (priv->cookie != NULL)
                 pci_free_consistent(priv->pdev, 4,
                                 priv->cookie, priv->cookie_dma);
 
+        return rc;
+}
+static int __devinit mwl8k_probe(struct pci_dev *pdev,
+                                 const struct pci_device_id *id)
+{
+        static int printed_version;
+        struct ieee80211_hw *hw;
+        struct mwl8k_priv *priv;
+        struct mwl8k_device_info *di;
+        int rc;
+
+        if (!printed_version) {
+                printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
+                printed_version = 1;
+        }
+
+
+        rc = pci_enable_device(pdev);
+        if (rc) {
+                printk(KERN_ERR "%s: Cannot enable new PCI device\n",
+                       MWL8K_NAME);
+                return rc;
+        }
+
+        rc = pci_request_regions(pdev, MWL8K_NAME);
+        if (rc) {
+                printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
+                       MWL8K_NAME);
+                goto err_disable_device;
+        }
+
+        pci_set_master(pdev);
+
+
+        hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
+        if (hw == NULL) {
+                printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
+                rc = -ENOMEM;
+                goto err_free_reg;
+        }
+
+        SET_IEEE80211_DEV(hw, &pdev->dev);
+        pci_set_drvdata(pdev, hw);
+
+        priv = hw->priv;
+        priv->hw = hw;
+        priv->pdev = pdev;
+        priv->device_info = &mwl8k_info_tbl[id->driver_data];
+
+
+        priv->sram = pci_iomap(pdev, 0, 0x10000);
+        if (priv->sram == NULL) {
+                wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
+                goto err_iounmap;
+        }
+
+        /*
+         * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
+         * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
+         */
+        priv->regs = pci_iomap(pdev, 1, 0x10000);
+        if (priv->regs == NULL) {
+                priv->regs = pci_iomap(pdev, 2, 0x10000);
+                if (priv->regs == NULL) {
+                        wiphy_err(hw->wiphy, "Cannot map device registers\n");
+                        goto err_iounmap;
+                }
+        }
+
+        /*
+         * Choose the initial fw image depending on user input.  If a second
+         * image is available, make it the alternative image that will be
+         * loaded if the first one fails.
+         */
+        init_completion(&priv->firmware_loading_complete);
+        di = priv->device_info;
+        if (ap_mode_default && di->fw_image_ap) {
+                priv->fw_pref = di->fw_image_ap;
+                priv->fw_alt = di->fw_image_sta;
+        } else if (!ap_mode_default && di->fw_image_sta) {
+                priv->fw_pref = di->fw_image_sta;
+                priv->fw_alt = di->fw_image_ap;
+        } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
+                printk(KERN_WARNING "AP fw is unavailable.  Using STA fw.");
+                priv->fw_pref = di->fw_image_sta;
+        } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
+                printk(KERN_WARNING "STA fw is unavailable.  Using AP fw.");
+                priv->fw_pref = di->fw_image_ap;
+        }
+        rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
+        if (rc)
+                goto err_stop_firmware;
+        return rc;
+
 err_stop_firmware:
         mwl8k_hw_reset(priv);
-        mwl8k_release_firmware(priv);
 
 err_iounmap:
         if (priv->regs != NULL)
@@ -4163,6 +4525,13 @@ static void __devexit mwl8k_remove(struct pci_dev *pdev)
                 return;
         priv = hw->priv;
 
+        wait_for_completion(&priv->firmware_loading_complete);
+
+        if (priv->fw_state == FW_STATE_ERROR) {
+                mwl8k_hw_reset(priv);
+                goto unmap;
+        }
+
         ieee80211_stop_queues(hw);
 
         ieee80211_unregister_hw(hw);
@@ -4185,6 +4554,7 @@ static void __devexit mwl8k_remove(struct pci_dev *pdev)
 
         pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
 
+unmap:
         pci_iounmap(pdev, priv->regs);
         pci_iounmap(pdev, priv->sram);
         pci_set_drvdata(pdev, NULL);
diff --git a/drivers/net/wireless/orinoco/wext.c b/drivers/net/wireless/orinoco/wext.c
index e5afabee60d1..e793679e2e19 100644
--- a/drivers/net/wireless/orinoco/wext.c
+++ b/drivers/net/wireless/orinoco/wext.c
@@ -893,6 +893,14 @@ static int orinoco_ioctl_set_auth(struct net_device *dev,
                  */
                 break;
 
+        case IW_AUTH_MFP:
+                /* Management Frame Protection not supported.
+                 * Only fail if set to required.
+                 */
+                if (param->value == IW_AUTH_MFP_REQUIRED)
+                        ret = -EINVAL;
+                break;
+
         case IW_AUTH_KEY_MGMT:
                 /* wl_lkm implies value 2 == PSK for Hermes I
                  * which ties in with WEXT
diff --git a/drivers/net/wireless/p54/p54usb.c b/drivers/net/wireless/p54/p54usb.c
index d5bc21e5a02c..21713a7638c4 100644
--- a/drivers/net/wireless/p54/p54usb.c
+++ b/drivers/net/wireless/p54/p54usb.c
@@ -43,6 +43,7 @@ MODULE_FIRMWARE("isl3887usb");
 
 static struct usb_device_id p54u_table[] __devinitdata = {
         /* Version 1 devices (pci chip + net2280) */
+        {USB_DEVICE(0x0411, 0x0050)},   /* Buffalo WLI2-USB2-G54 */
         {USB_DEVICE(0x045e, 0x00c2)},   /* Microsoft MN-710 */
         {USB_DEVICE(0x0506, 0x0a11)},   /* 3COM 3CRWE254G72 */
         {USB_DEVICE(0x06b9, 0x0120)},   /* Thomson SpeedTouch 120g */
@@ -56,9 +57,13 @@ static struct usb_device_id p54u_table[] __devinitdata = {
         {USB_DEVICE(0x0846, 0x4220)},   /* Netgear WG111 */
         {USB_DEVICE(0x09aa, 0x1000)},   /* Spinnaker Proto board */
         {USB_DEVICE(0x0cde, 0x0006)},   /* Medion 40900, Roper Europe */
+        {USB_DEVICE(0x0db0, 0x6826)},   /* MSI UB54G (MS-6826) */
         {USB_DEVICE(0x107b, 0x55f2)},   /* Gateway WGU-210 (Gemtek) */
         {USB_DEVICE(0x124a, 0x4023)},   /* Shuttle PN15, Airvast WM168g, IOGear GWU513 */
+        {USB_DEVICE(0x1435, 0x0210)},   /* Inventel UR054G */
+        {USB_DEVICE(0x15a9, 0x0002)},   /* Gemtek WUBI-100GW 802.11g */
         {USB_DEVICE(0x1630, 0x0005)},   /* 2Wire 802.11g USB (v1) / Z-Com */
+        {USB_DEVICE(0x182d, 0x096b)},   /* Sitecom WL-107 */
         {USB_DEVICE(0x1915, 0x2234)},   /* Linksys WUSB54G OEM */
         {USB_DEVICE(0x1915, 0x2235)},   /* Linksys WUSB54G Portable OEM */
         {USB_DEVICE(0x2001, 0x3701)},   /* DLink DWL-G120 Spinnaker */
@@ -94,6 +99,7 @@ static struct usb_device_id p54u_table[] __devinitdata = {
         {USB_DEVICE(0x1435, 0x0427)},   /* Inventel UR054G */
         {USB_DEVICE(0x1668, 0x1050)},   /* Actiontec 802UIG-1 */
         {USB_DEVICE(0x2001, 0x3704)},   /* DLink DWL-G122 rev A2 */
+        {USB_DEVICE(0x2001, 0x3705)},   /* D-Link DWL-G120 rev C1 */
         {USB_DEVICE(0x413c, 0x5513)},   /* Dell WLA3310 USB Wireless Adapter */
         {USB_DEVICE(0x413c, 0x8102)},   /* Spinnaker DUT */
         {USB_DEVICE(0x413c, 0x8104)},   /* Cohiba Proto board */
@@ -183,7 +189,7 @@ static void p54u_rx_cb(struct urb *urb)
 static void p54u_tx_cb(struct urb *urb)
 {
         struct sk_buff *skb = urb->context;
-        struct ieee80211_hw *dev = (struct ieee80211_hw *)
+        struct ieee80211_hw *dev =
                 usb_get_intfdata(usb_ifnum_to_if(urb->dev, 0));
 
         p54_free_skb(dev, skb);
diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c
index 97007d9e2c1f..0764d1a30d13 100644
--- a/drivers/net/wireless/ray_cs.c
+++ b/drivers/net/wireless/ray_cs.c
@@ -1776,11 +1776,8 @@ static void ray_update_multi_list(struct net_device *dev, int all)
                 /* Copy the kernel's list of MC addresses to card */
                 netdev_for_each_mc_addr(ha, dev) {
                         memcpy_toio(p, ha->addr, ETH_ALEN);
-                        dev_dbg(&link->dev,
-                              "ray_update_multi add addr %02x%02x%02x%02x%02x%02x\n",
-                              ha->addr[0], ha->addr[1],
-                              ha->addr[2], ha->addr[3],
-                              ha->addr[4], ha->addr[5]);
+                        dev_dbg(&link->dev, "ray_update_multi add addr %pm\n",
+                                ha->addr);
                         p += ETH_ALEN;
                         i++;
                 }
@@ -2015,11 +2012,8 @@ static irqreturn_t ray_interrupt(int irq, void *dev_id)
                                 memcpy_fromio(&local->bss_id,
                                               prcs->var.rejoin_net_complete.
                                               bssid, ADDRLEN);
-                                dev_dbg(&link->dev,
-                                      "ray_cs new BSSID = %02x%02x%02x%02x%02x%02x\n",
-                                      local->bss_id[0], local->bss_id[1],
-                                      local->bss_id[2], local->bss_id[3],
-                                      local->bss_id[4], local->bss_id[5]);
+                                dev_dbg(&link->dev, "ray_cs new BSSID = %pm\n",
+                                        local->bss_id);
                                 if (!sniffer)
                                         authenticate(local);
                         }
@@ -2286,8 +2280,8 @@ static void untranslate(ray_dev_t *local, struct sk_buff *skb, int len)
         struct ethhdr *peth;
         UCHAR srcaddr[ADDRLEN];
         UCHAR destaddr[ADDRLEN];
-        static UCHAR org_bridge[3] = { 0, 0, 0xf8 };
-        static UCHAR org_1042[3] = { 0, 0, 0 };
+        static const UCHAR org_bridge[3] = { 0, 0, 0xf8 };
+        static const UCHAR org_1042[3] = { 0, 0, 0 };
 
         memcpy(destaddr, ieee80211_get_DA(pmac), ADDRLEN);
         memcpy(srcaddr, ieee80211_get_SA(pmac), ADDRLEN);
diff --git a/drivers/net/wireless/rndis_wlan.c b/drivers/net/wireless/rndis_wlan.c
index 71b5971da597..848cc2cce247 100644
--- a/drivers/net/wireless/rndis_wlan.c
+++ b/drivers/net/wireless/rndis_wlan.c
@@ -129,6 +129,7 @@ MODULE_PARM_DESC(workaround_interval,
 #define OID_802_11_RTS_THRESHOLD                cpu_to_le32(0x0d01020a)
 #define OID_802_11_SUPPORTED_RATES              cpu_to_le32(0x0d01020e)
 #define OID_802_11_CONFIGURATION                cpu_to_le32(0x0d010211)
+#define OID_802_11_POWER_MODE                   cpu_to_le32(0x0d010216)
 #define OID_802_11_BSSID_LIST                   cpu_to_le32(0x0d010217)
 
 
@@ -156,6 +157,12 @@ MODULE_PARM_DESC(workaround_interval,
 #define RNDIS_STATUS_ADAPTER_NOT_OPEN           cpu_to_le32(0xc0010012)
 
 
+/* Known device types */
+#define RNDIS_UNKNOWN   0
+#define RNDIS_BCM4320A  1
+#define RNDIS_BCM4320B  2
+
+
 /* NDIS data structures. Taken from wpa_supplicant driver_ndis.c
  * slightly modified for datatype endianess, etc
  */
@@ -233,6 +240,12 @@ enum ndis_80211_addwep_bits {
         NDIS_80211_ADDWEP_TRANSMIT_KEY = cpu_to_le32(1 << 31)
 };
 
+enum ndis_80211_power_mode {
+        NDIS_80211_POWER_MODE_CAM,
+        NDIS_80211_POWER_MODE_MAX_PSP,
+        NDIS_80211_POWER_MODE_FAST_PSP,
+};
+
 struct ndis_80211_auth_request {
         __le32 length;
         u8 bssid[6];
@@ -472,12 +485,16 @@ struct rndis_wlan_private {
         struct mutex command_lock;
         unsigned long work_pending;
         int last_qual;
+        s32 cqm_rssi_thold;
+        u32 cqm_rssi_hyst;
+        int last_cqm_event_rssi;
 
         struct ieee80211_supported_band band;
         struct ieee80211_channel channels[ARRAY_SIZE(rndis_channels)];
         struct ieee80211_rate rates[ARRAY_SIZE(rndis_rates)];
         u32 cipher_suites[ARRAY_SIZE(rndis_cipher_suites)];
 
+        int device_type;
         int caps;
         int multicast_size;
 
@@ -493,10 +510,10 @@ struct rndis_wlan_private {
 
         /* hardware state */
         bool radio_on;
+        int power_mode;
         int infra_mode;
         bool connected;
         u8 bssid[ETH_ALEN];
-        struct ndis_80211_ssid essid;
         __le32 current_command_oid;
 
         /* encryption stuff */
@@ -547,7 +564,7 @@ static int rndis_del_key(struct wiphy *wiphy, struct net_device *netdev,
                          u8 key_index, bool pairwise, const u8 *mac_addr);
 
 static int rndis_set_default_key(struct wiphy *wiphy, struct net_device *netdev,
-                                                                u8 key_index);
+                                 u8 key_index, bool unicast, bool multicast);
 
 static int rndis_get_station(struct wiphy *wiphy, struct net_device *dev,
                                         u8 *mac, struct station_info *sinfo);
@@ -563,7 +580,14 @@ static int rndis_del_pmksa(struct wiphy *wiphy, struct net_device *netdev,
 
 static int rndis_flush_pmksa(struct wiphy *wiphy, struct net_device *netdev);
 
-static struct cfg80211_ops rndis_config_ops = {
+static int rndis_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
+                                bool enabled, int timeout);
+
+static int rndis_set_cqm_rssi_config(struct wiphy *wiphy,
+                                        struct net_device *dev,
+                                        s32 rssi_thold, u32 rssi_hyst);
+
+static const struct cfg80211_ops rndis_config_ops = {
         .change_virtual_intf = rndis_change_virtual_intf,
         .scan = rndis_scan,
         .set_wiphy_params = rndis_set_wiphy_params,
@@ -582,6 +606,8 @@ static struct cfg80211_ops rndis_config_ops = {
         .set_pmksa = rndis_set_pmksa,
         .del_pmksa = rndis_del_pmksa,
         .flush_pmksa = rndis_flush_pmksa,
+        .set_power_mgmt = rndis_set_power_mgmt,
+        .set_cqm_rssi_config = rndis_set_cqm_rssi_config,
 };
 
 static void *rndis_wiphy_privid = &rndis_wiphy_privid;
@@ -680,6 +706,7 @@ static const char *oid_to_string(__le32 oid)
                 OID_STR(OID_802_11_ADD_KEY);
                 OID_STR(OID_802_11_REMOVE_KEY);
                 OID_STR(OID_802_11_ASSOCIATION_INFORMATION);
+                OID_STR(OID_802_11_CAPABILITY);
                 OID_STR(OID_802_11_PMKID);
                 OID_STR(OID_802_11_NETWORK_TYPES_SUPPORTED);
                 OID_STR(OID_802_11_NETWORK_TYPE_IN_USE);
@@ -690,6 +717,7 @@ static const char *oid_to_string(__le32 oid)
                 OID_STR(OID_802_11_RTS_THRESHOLD);
                 OID_STR(OID_802_11_SUPPORTED_RATES);
                 OID_STR(OID_802_11_CONFIGURATION);
+                OID_STR(OID_802_11_POWER_MODE);
                 OID_STR(OID_802_11_BSSID_LIST);
 #undef OID_STR
         }
@@ -810,7 +838,8 @@ exit_unlock:
         return ret;
 }
 
-static int rndis_set_oid(struct usbnet *dev, __le32 oid, void *data, int len)
+static int rndis_set_oid(struct usbnet *dev, __le32 oid, const void *data,
+                         int len)
 {
         struct rndis_wlan_private *priv = get_rndis_wlan_priv(dev);
         union {
@@ -994,7 +1023,18 @@ static int level_to_qual(int level)
  */
 static int set_infra_mode(struct usbnet *usbdev, int mode);
 static void restore_keys(struct usbnet *usbdev);
-static int rndis_check_bssid_list(struct usbnet *usbdev);
+static int rndis_check_bssid_list(struct usbnet *usbdev, u8 *match_bssid,
+                                        bool *matched);
+
+static int rndis_start_bssid_list_scan(struct usbnet *usbdev)
+{
+        __le32 tmp;
+
+        /* Note: OID_802_11_BSSID_LIST_SCAN clears internal BSS list. */
+        tmp = cpu_to_le32(1);
+        return rndis_set_oid(usbdev, OID_802_11_BSSID_LIST_SCAN, &tmp,
+                                                        sizeof(tmp));
+}
 
 static int set_essid(struct usbnet *usbdev, struct ndis_80211_ssid *ssid)
 {
@@ -1007,7 +1047,6 @@ static int set_essid(struct usbnet *usbdev, struct ndis_80211_ssid *ssid)
                 return ret;
         }
         if (ret == 0) {
-                memcpy(&priv->essid, ssid, sizeof(priv->essid));
                 priv->radio_on = true;
                 netdev_dbg(usbdev->net, "%s(): radio_on = true\n", __func__);
         }
@@ -1015,7 +1054,7 @@ static int set_essid(struct usbnet *usbdev, struct ndis_80211_ssid *ssid)
         return ret;
 }
 
-static int set_bssid(struct usbnet *usbdev, u8 bssid[ETH_ALEN])
+static int set_bssid(struct usbnet *usbdev, const u8 *bssid)
 {
         int ret;
 
@@ -1031,7 +1070,9 @@ static int set_bssid(struct usbnet *usbdev, u8 bssid[ETH_ALEN])
 
 static int clear_bssid(struct usbnet *usbdev)
 {
-        u8 broadcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+        static const u8 broadcast_mac[ETH_ALEN] = {
+                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+        };
 
         return set_bssid(usbdev, broadcast_mac);
 }
@@ -1904,14 +1945,14 @@ static int rndis_scan(struct wiphy *wiphy, struct net_device *dev,
         struct usbnet *usbdev = netdev_priv(dev);
         struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev);
         int ret;
-        __le32 tmp;
+        int delay = SCAN_DELAY_JIFFIES;
 
         netdev_dbg(usbdev->net, "cfg80211.scan\n");
 
         /* Get current bssid list from device before new scan, as new scan
          * clears internal bssid list.
          */
-        rndis_check_bssid_list(usbdev);
+        rndis_check_bssid_list(usbdev, NULL, NULL);
 
         if (!request)
                 return -EINVAL;
@@ -1921,13 +1962,13 @@ static int rndis_scan(struct wiphy *wiphy, struct net_device *dev,
 
         priv->scan_request = request;
 
-        tmp = cpu_to_le32(1);
-        ret = rndis_set_oid(usbdev, OID_802_11_BSSID_LIST_SCAN, &tmp,
-                                                        sizeof(tmp));
+        ret = rndis_start_bssid_list_scan(usbdev);
         if (ret == 0) {
+                if (priv->device_type == RNDIS_BCM4320A)
+                        delay = HZ;
+
                 /* Wait before retrieving scan results from device */
-                queue_delayed_work(priv->workqueue, &priv->scan_work,
-                        SCAN_DELAY_JIFFIES);
+                queue_delayed_work(priv->workqueue, &priv->scan_work, delay);
         }
 
         return ret;
@@ -1946,8 +1987,8 @@ static struct cfg80211_bss *rndis_bss_info_update(struct usbnet *usbdev,
         int ie_len, bssid_len;
         u8 *ie;
 
-        netdev_dbg(usbdev->net, " found bssid: '%.32s' [%pM]\n",
-                   bssid->ssid.essid, bssid->mac);
+        netdev_dbg(usbdev->net, " found bssid: '%.32s' [%pM], len: %d\n",
+                   bssid->ssid.essid, bssid->mac, le32_to_cpu(bssid->length));
 
         /* parse bssid structure */
         bssid_len = le32_to_cpu(bssid->length);
@@ -1981,49 +2022,98 @@ static struct cfg80211_bss *rndis_bss_info_update(struct usbnet *usbdev,
                 GFP_KERNEL);
 }
 
-static int rndis_check_bssid_list(struct usbnet *usbdev)
+static struct ndis_80211_bssid_ex *next_bssid_list_item(
+                                        struct ndis_80211_bssid_ex *bssid,
+                                        int *bssid_len, void *buf, int len)
+{
+        void *buf_end, *bssid_end;
+
+        buf_end = (char *)buf + len;
+        bssid_end = (char *)bssid + *bssid_len;
+
+        if ((int)(buf_end - bssid_end) < sizeof(bssid->length)) {
+                *bssid_len = 0;
+                return NULL;
+        } else {
+                bssid = (void *)((char *)bssid + *bssid_len);
+                *bssid_len = le32_to_cpu(bssid->length);
+                return bssid;
+        }
+}
+
+static bool check_bssid_list_item(struct ndis_80211_bssid_ex *bssid,
+                                  int bssid_len, void *buf, int len)
+{
+        void *buf_end, *bssid_end;
+
+        if (!bssid || bssid_len <= 0 || bssid_len > len)
+                return false;
+
+        buf_end = (char *)buf + len;
+        bssid_end = (char *)bssid + bssid_len;
+
+        return (int)(buf_end - bssid_end) >= 0 && (int)(bssid_end - buf) >= 0;
+}
+
+static int rndis_check_bssid_list(struct usbnet *usbdev, u8 *match_bssid,
+                                        bool *matched)
 {
         void *buf = NULL;
         struct ndis_80211_bssid_list_ex *bssid_list;
         struct ndis_80211_bssid_ex *bssid;
-        int ret = -EINVAL, len, count, bssid_len;
-        bool resized = false;
+        int ret = -EINVAL, len, count, bssid_len, real_count, new_len;
 
-        netdev_dbg(usbdev->net, "check_bssid_list\n");
+        netdev_dbg(usbdev->net, "%s()\n", __func__);
 
         len = CONTROL_BUFFER_SIZE;
 resize_buf:
-        buf = kmalloc(len, GFP_KERNEL);
+        buf = kzalloc(len, GFP_KERNEL);
         if (!buf) {
                 ret = -ENOMEM;
                 goto out;
         }
 
-        ret = rndis_query_oid(usbdev, OID_802_11_BSSID_LIST, buf, &len);
-        if (ret != 0)
+        /* BSSID-list might have got bigger last time we checked, keep
+         * resizing until it won't get any bigger.
+         */
+        new_len = len;
+        ret = rndis_query_oid(usbdev, OID_802_11_BSSID_LIST, buf, &new_len);
+        if (ret != 0 || new_len < sizeof(struct ndis_80211_bssid_list_ex))
                 goto out;
 
-        if (!resized && len > CONTROL_BUFFER_SIZE) {
-                resized = true;
+        if (new_len > len) {
+                len = new_len;
                 kfree(buf);
                 goto resize_buf;
         }
 
+        len = new_len;
+
         bssid_list = buf;
-        bssid = bssid_list->bssid;
-        bssid_len = le32_to_cpu(bssid->length);
         count = le32_to_cpu(bssid_list->num_items);
-        netdev_dbg(usbdev->net, "check_bssid_list: %d BSSIDs found (buflen: %d)\n",
-                   count, len);
+        real_count = 0;
+        netdev_dbg(usbdev->net, "%s(): buflen: %d\n", __func__, len);
+
+        bssid_len = 0;
+        bssid = next_bssid_list_item(bssid_list->bssid, &bssid_len, buf, len);
 
-        while (count && ((void *)bssid + bssid_len) <= (buf + len)) {
-                rndis_bss_info_update(usbdev, bssid);
+        /* Device returns incorrect 'num_items'. Workaround by ignoring the
+         * received 'num_items' and walking through full bssid buffer instead.
+         */
+        while (check_bssid_list_item(bssid, bssid_len, buf, len)) {
+                if (rndis_bss_info_update(usbdev, bssid) && match_bssid &&
+                    matched) {
+                        if (compare_ether_addr(bssid->mac, match_bssid))
+                                *matched = true;
+                }
 
-                bssid = (void *)bssid + bssid_len;
-                bssid_len = le32_to_cpu(bssid->length);
-                count--;
+                real_count++;
+                bssid = next_bssid_list_item(bssid, &bssid_len, buf, len);
         }
 
+        netdev_dbg(usbdev->net, "%s(): num_items from device: %d, really found:"
+                                " %d\n", __func__, count, real_count);
+
 out:
         kfree(buf);
         return ret;
@@ -2041,7 +2131,7 @@ static void rndis_get_scan_results(struct work_struct *work)
         if (!priv->scan_request)
                 return;
 
-        ret = rndis_check_bssid_list(usbdev);
+        ret = rndis_check_bssid_list(usbdev, NULL, NULL);
 
         cfg80211_scan_done(priv->scan_request, ret < 0);
 
@@ -2355,7 +2445,7 @@ static int rndis_del_key(struct wiphy *wiphy, struct net_device *netdev,
 }
 
 static int rndis_set_default_key(struct wiphy *wiphy, struct net_device *netdev,
-                                                                u8 key_index)
+                                 u8 key_index, bool unicast, bool multicast)
 {
         struct rndis_wlan_private *priv = wiphy_priv(wiphy);
         struct usbnet *usbdev = priv->usbdev;
@@ -2365,6 +2455,9 @@ static int rndis_set_default_key(struct wiphy *wiphy, struct net_device *netdev,
 
         priv->encr_tx_key_index = key_index;
 
+        if (is_wpa_key(priv, key_index))
+                return 0;
+
         key = priv->encr_keys[key_index];
 
         return add_wep_key(usbdev, key.material, key.len, key_index);
@@ -2495,6 +2588,136 @@ static int rndis_flush_pmksa(struct wiphy *wiphy, struct net_device *netdev)
         return rndis_set_oid(usbdev, OID_802_11_PMKID, &pmkid, sizeof(pmkid));
 }
 
+static int rndis_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
+                                bool enabled, int timeout)
+{
+        struct rndis_wlan_private *priv = wiphy_priv(wiphy);
+        struct usbnet *usbdev = priv->usbdev;
+        int power_mode;
+        __le32 mode;
+        int ret;
+
+        netdev_dbg(usbdev->net, "%s(): %s, %d\n", __func__,
+                                enabled ? "enabled" : "disabled",
+                                timeout);
+
+        if (enabled)
+                power_mode = NDIS_80211_POWER_MODE_FAST_PSP;
+        else
+                power_mode = NDIS_80211_POWER_MODE_CAM;
+
+        if (power_mode == priv->power_mode)
+                return 0;
+
+        priv->power_mode = power_mode;
+
+        mode = cpu_to_le32(power_mode);
+        ret = rndis_set_oid(usbdev, OID_802_11_POWER_MODE, &mode, sizeof(mode));
+
+        netdev_dbg(usbdev->net, "%s(): OID_802_11_POWER_MODE -> %d\n",
+                                __func__, ret);
+
+        return ret;
+}
+
+static int rndis_set_cqm_rssi_config(struct wiphy *wiphy,
+                                        struct net_device *dev,
+                                        s32 rssi_thold, u32 rssi_hyst)
+{
+        struct rndis_wlan_private *priv = wiphy_priv(wiphy);
+
+        priv->cqm_rssi_thold = rssi_thold;
+        priv->cqm_rssi_hyst = rssi_hyst;
+        priv->last_cqm_event_rssi = 0;
+
+        return 0;
+}
+
+static void rndis_wlan_craft_connected_bss(struct usbnet *usbdev, u8 *bssid,
+                                           struct ndis_80211_assoc_info *info)
+{
+        struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev);
+        struct ieee80211_channel *channel;
+        struct ndis_80211_conf config;
+        struct ndis_80211_ssid ssid;
+        s32 signal;
+        u64 timestamp;
+        u16 capability;
+        u16 beacon_interval;
+        __le32 rssi;
+        u8 ie_buf[34];
+        int len, ret, ie_len;
+
+        /* Get signal quality, in case of error use rssi=0 and ignore error. */
+        len = sizeof(rssi);
+        rssi = 0;
+        ret = rndis_query_oid(usbdev, OID_802_11_RSSI, &rssi, &len);
+        signal = level_to_qual(le32_to_cpu(rssi));
+
+        netdev_dbg(usbdev->net, "%s(): OID_802_11_RSSI -> %d, "
+                   "rssi:%d, qual: %d\n", __func__, ret, le32_to_cpu(rssi),
+                   level_to_qual(le32_to_cpu(rssi)));
+
+        /* Get AP capabilities */
+        if (info) {
+                capability = le16_to_cpu(info->resp_ie.capa);
+        } else {
+                /* Set atleast ESS/IBSS capability */
+                capability = (priv->infra_mode == NDIS_80211_INFRA_INFRA) ?
+                                WLAN_CAPABILITY_ESS : WLAN_CAPABILITY_IBSS;
+        }
+
+        /* Get channel and beacon interval */
+        len = sizeof(config);
+        ret = rndis_query_oid(usbdev, OID_802_11_CONFIGURATION, &config, &len);
+        netdev_dbg(usbdev->net, "%s(): OID_802_11_CONFIGURATION -> %d\n",
+                                __func__, ret);
+        if (ret >= 0) {
+                beacon_interval = le16_to_cpu(config.beacon_period);
+                channel = ieee80211_get_channel(priv->wdev.wiphy,
+                                KHZ_TO_MHZ(le32_to_cpu(config.ds_config)));
+                if (!channel) {
+                        netdev_warn(usbdev->net, "%s(): could not get channel."
+                                                 "\n", __func__);
+                        return;
+                }
+        } else {
+                netdev_warn(usbdev->net, "%s(): could not get configuration.\n",
+                                         __func__);
+                return;
+        }
+
+        /* Get SSID, in case of error, use zero length SSID and ignore error. */
+        len = sizeof(ssid);
+        memset(&ssid, 0, sizeof(ssid));
+        ret = rndis_query_oid(usbdev, OID_802_11_SSID, &ssid, &len);
+        netdev_dbg(usbdev->net, "%s(): OID_802_11_SSID -> %d, len: %d, ssid: "
+                                "'%.32s'\n", __func__, ret,
+                                le32_to_cpu(ssid.length), ssid.essid);
+
+        if (le32_to_cpu(ssid.length) > 32)
+                ssid.length = cpu_to_le32(32);
+
+        ie_buf[0] = WLAN_EID_SSID;
+        ie_buf[1] = le32_to_cpu(ssid.length);
+        memcpy(&ie_buf[2], ssid.essid, le32_to_cpu(ssid.length));
+
+        ie_len = le32_to_cpu(ssid.length) + 2;
+
+        /* no tsf */
+        timestamp = 0;
+
+        netdev_dbg(usbdev->net, "%s(): channel:%d(freq), bssid:[%pM], tsf:%d, "
+                "capa:%x, beacon int:%d, resp_ie(len:%d, essid:'%.32s'), "
+                "signal:%d\n", __func__, (channel ? channel->center_freq : -1),
+                bssid, (u32)timestamp, capability, beacon_interval, ie_len,
+                ssid.essid, signal);
+
+        cfg80211_inform_bss(priv->wdev.wiphy, channel, bssid,
+                timestamp, capability, beacon_interval, ie_buf, ie_len,
+                signal, GFP_KERNEL);
+}
+
 /*
  * workers, indication handlers, device poller
  */
@@ -2507,6 +2730,7 @@ static void rndis_wlan_do_link_up_work(struct usbnet *usbdev)
         u8 *req_ie, *resp_ie;
         int ret, offset;
         bool roamed = false;
+        bool match_bss;
 
         if (priv->infra_mode == NDIS_80211_INFRA_INFRA && priv->connected) {
                 /* received media connect indication while connected, either
@@ -2558,6 +2782,13 @@ static void rndis_wlan_do_link_up_work(struct usbnet *usbdev)
                                         resp_ie_len =
                                                 CONTROL_BUFFER_SIZE - offset;
                         }
+                } else {
+                        /* Since rndis_wlan_craft_connected_bss() might use info
+                         * later and expects info to contain valid data if
+                         * non-null, free info and set NULL here.
+                         */
+                        kfree(info);
+                        info = NULL;
                 }
         } else if (WARN_ON(priv->infra_mode != NDIS_80211_INFRA_ADHOC))
                 return;
@@ -2569,13 +2800,26 @@ static void rndis_wlan_do_link_up_work(struct usbnet *usbdev)
         netdev_dbg(usbdev->net, "link up work: [%pM]%s\n",
                    bssid, roamed ? " roamed" : "");
 
-        /* Internal bss list in device always contains at least the currently
+        /* Internal bss list in device should contain at least the currently
          * connected bss and we can get it to cfg80211 with
          * rndis_check_bssid_list().
-         * NOTE: This is true for Broadcom chip, but not mentioned in RNDIS
-         * spec.
+         *
+         * NDIS spec says: "If the device is associated, but the associated
+         *  BSSID is not in its BSSID scan list, then the driver must add an
+         *  entry for the BSSID at the end of the data that it returns in
+         *  response to query of OID_802_11_BSSID_LIST."
+         *
+         * NOTE: Seems to be true for BCM4320b variant, but not BCM4320a.
          */
-        rndis_check_bssid_list(usbdev);
+        match_bss = false;
+        rndis_check_bssid_list(usbdev, bssid, &match_bss);
+
+        if (!is_zero_ether_addr(bssid) && !match_bss) {
+                /* Couldn't get bss from device, we need to manually craft bss
+                 * for cfg80211.
+                 */
+                rndis_wlan_craft_connected_bss(usbdev, bssid, info);
+        }
 
         if (priv->infra_mode == NDIS_80211_INFRA_INFRA) {
                 if (!roamed)
@@ -2918,6 +3162,32 @@ static int rndis_wlan_get_caps(struct usbnet *usbdev, struct wiphy *wiphy)
         return retval;
 }
 
+static void rndis_do_cqm(struct usbnet *usbdev, s32 rssi)
+{
+        struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev);
+        enum nl80211_cqm_rssi_threshold_event event;
+        int thold, hyst, last_event;
+
+        if (priv->cqm_rssi_thold >= 0 || rssi >= 0)
+                return;
+        if (priv->infra_mode != NDIS_80211_INFRA_INFRA)
+                return;
+
+        last_event = priv->last_cqm_event_rssi;
+        thold = priv->cqm_rssi_thold;
+        hyst = priv->cqm_rssi_hyst;
+
+        if (rssi < thold && (last_event == 0 || rssi < last_event - hyst))
+                event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW;
+        else if (rssi > thold && (last_event == 0 || rssi > last_event + hyst))
+                event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH;
+        else
+                return;
+
+        priv->last_cqm_event_rssi = rssi;
+        cfg80211_cqm_rssi_notify(usbdev->net, event, GFP_KERNEL);
+}
+
 #define DEVICE_POLLER_JIFFIES (HZ)
 static void rndis_device_poller(struct work_struct *work)
 {
@@ -2934,13 +3204,28 @@ static void rndis_device_poller(struct work_struct *work)
          * also polls device with rndis_command() and catches for media link
          * indications.
          */
-        if (!is_associated(usbdev))
+        if (!is_associated(usbdev)) {
+                /* Workaround bad scanning in BCM4320a devices with active
+                 * background scanning when not associated.
+                 */
+                if (priv->device_type == RNDIS_BCM4320A && priv->radio_on &&
+                    !priv->scan_request) {
+                        /* Get previous scan results */
+                        rndis_check_bssid_list(usbdev, NULL, NULL);
+
+                        /* Initiate new scan */
+                        rndis_start_bssid_list_scan(usbdev);
+                }
+
                 goto end;
+        }
 
         len = sizeof(rssi);
         ret = rndis_query_oid(usbdev, OID_802_11_RSSI, &rssi, &len);
-        if (ret == 0)
+        if (ret == 0) {
                 priv->last_qual = level_to_qual(le32_to_cpu(rssi));
+                rndis_do_cqm(usbdev, le32_to_cpu(rssi));
+        }
 
         netdev_dbg(usbdev->net, "dev-poller: OID_802_11_RSSI -> %d, rssi:%d, qual: %d\n",
                    ret, le32_to_cpu(rssi), level_to_qual(le32_to_cpu(rssi)));
@@ -2992,10 +3277,12 @@ end:
 /*
  * driver/device initialization
  */
-static void rndis_copy_module_params(struct usbnet *usbdev)
+static void rndis_copy_module_params(struct usbnet *usbdev, int device_type)
 {
         struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev);
 
+        priv->device_type = device_type;
+
         priv->param_country[0] = modparam_country[0];
         priv->param_country[1] = modparam_country[1];
         priv->param_country[2] = 0;
@@ -3038,12 +3325,25 @@ static void rndis_copy_module_params(struct usbnet *usbdev)
                 priv->param_workaround_interval = modparam_workaround_interval;
 }
 
+static int unknown_early_init(struct usbnet *usbdev)
+{
+        /* copy module parameters for unknown so that iwconfig reports txpower
+         * and workaround parameter is copied to private structure correctly.
+         */
+        rndis_copy_module_params(usbdev, RNDIS_UNKNOWN);
+
+        /* This is unknown device, so do not try set configuration parameters.
+         */
+
+        return 0;
+}
+
 static int bcm4320a_early_init(struct usbnet *usbdev)
 {
         /* copy module parameters for bcm4320a so that iwconfig reports txpower
          * and workaround parameter is copied to private structure correctly.
          */
-        rndis_copy_module_params(usbdev);
+        rndis_copy_module_params(usbdev, RNDIS_BCM4320A);
 
         /* bcm4320a doesn't handle configuration parameters well. Try
          * set any and you get partially zeroed mac and broken device.
@@ -3057,7 +3357,7 @@ static int bcm4320b_early_init(struct usbnet *usbdev)
         struct rndis_wlan_private *priv = get_rndis_wlan_priv(usbdev);
         char buf[8];
 
-        rndis_copy_module_params(usbdev);
+        rndis_copy_module_params(usbdev, RNDIS_BCM4320B);
 
         /* Early initialization settings, setting these won't have effect
          * if called after generic_rndis_bind().
@@ -3187,13 +3487,15 @@ static int rndis_wlan_bind(struct usbnet *usbdev, struct usb_interface *intf)
 
         set_default_iw_params(usbdev);
 
+        priv->power_mode = -1;
+
         /* set default rts/frag */
         rndis_set_wiphy_params(wiphy,
                         WIPHY_PARAM_FRAG_THRESHOLD | WIPHY_PARAM_RTS_THRESHOLD);
 
-        /* turn radio on */
-        priv->radio_on = true;
-        disassociate(usbdev, true);
+        /* turn radio off on init */
+        priv->radio_on = false;
+        disassociate(usbdev, false);
         netif_carrier_off(usbdev->net);
 
         return 0;
@@ -3320,7 +3622,7 @@ static const struct driver_info rndis_wlan_info = {
         .tx_fixup =     rndis_tx_fixup,
         .reset =        rndis_wlan_reset,
         .stop =         rndis_wlan_stop,
-        .early_init =   bcm4320a_early_init,
+        .early_init =   unknown_early_init,
         .indication =   rndis_wlan_indication,
 };
 
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 4396d4b9bfb9..6f383cd684b0 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -53,51 +53,41 @@ config RT61PCI
 
           When compiled as a module, this driver will be called rt61pci.
 
-config RT2800PCI_PCI
-        boolean
-        depends on PCI
-        default y
-
-config RT2800PCI_SOC
-        boolean
-        depends on RALINK_RT288X || RALINK_RT305X
-        default y
-
 config RT2800PCI
-        tristate "Ralink rt28xx/rt30xx/rt35xx (PCI/PCIe/PCMCIA) support (EXPERIMENTAL)"
-        depends on (RT2800PCI_PCI || RT2800PCI_SOC) && EXPERIMENTAL
+        tristate "Ralink rt27xx/rt28xx/rt30xx (PCI/PCIe/PCMCIA) support"
+        depends on PCI || RALINK_RT288X || RALINK_RT305X
         select RT2800_LIB
-        select RT2X00_LIB_PCI if RT2800PCI_PCI
-        select RT2X00_LIB_SOC if RT2800PCI_SOC
+        select RT2X00_LIB_PCI if PCI
+        select RT2X00_LIB_SOC if RALINK_RT288X || RALINK_RT305X
         select RT2X00_LIB_HT
         select RT2X00_LIB_FIRMWARE
         select RT2X00_LIB_CRYPTO
         select CRC_CCITT
         select EEPROM_93CX6
         ---help---
-          This adds support for rt2800/rt3000/rt3500 wireless chipset family.
-          Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890 & RT3052
-
-          This driver is non-functional at the moment and is intended for
-          developers.
+          This adds support for rt27xx/rt28xx/rt30xx wireless chipset family.
+          Supported chips: RT2760, RT2790, RT2860, RT2880, RT2890, RT3052,
+                           RT3090, RT3091 & RT3092
 
           When compiled as a module, this driver will be called "rt2800pci.ko".
 
 if RT2800PCI
 
-config RT2800PCI_RT30XX
-        bool "rt2800pci - Include support for rt30xx (PCI/PCIe/PCMCIA) devices"
-        default y
+config RT2800PCI_RT33XX
+        bool "rt2800pci - Include support for rt33xx devices (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        default n
         ---help---
-          This adds support for rt30xx wireless chipset family to the
+          This adds support for rt33xx wireless chipset family to the
           rt2800pci driver.
-          Supported chips: RT3090, RT3091 & RT3092
+          Supported chips: RT3390
 
           Support for these devices is non-functional at the moment and is
           intended for testers and developers.
 
 config RT2800PCI_RT35XX
-        bool "rt2800pci - Include support for rt35xx (PCI/PCIe/PCMCIA) devices"
+        bool "rt2800pci - Include support for rt35xx devices (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
         default n
         ---help---
           This adds support for rt35xx wireless chipset family to the
@@ -134,8 +124,8 @@ config RT73USB
           When compiled as a module, this driver will be called rt73usb.
 
 config RT2800USB
-        tristate "Ralink rt2800 (USB) support (EXPERIMENTAL)"
-        depends on USB && EXPERIMENTAL
+        tristate "Ralink rt27xx/rt28xx/rt30xx (USB) support"
+        depends on USB
         select RT2800_LIB
         select RT2X00_LIB_USB
         select RT2X00_LIB_HT
@@ -143,30 +133,28 @@ config RT2800USB
         select RT2X00_LIB_CRYPTO
         select CRC_CCITT
         ---help---
-          This adds experimental support for rt2800 wireless chipset family.
-          Supported chips: RT2770, RT2870 & RT3070.
-
-          Known issues:
-          - support for RT2870 chips doesn't work with 802.11n APs yet
-          - support for RT3070 chips is non-functional at the moment
+          This adds support for rt27xx/rt28xx/rt30xx wireless chipset family.
+          Supported chips: RT2770, RT2870 & RT3070, RT3071 & RT3072
 
           When compiled as a module, this driver will be called "rt2800usb.ko".
 
 if RT2800USB
 
-config RT2800USB_RT30XX
-        bool "rt2800usb - Include support for rt30xx (USB) devices"
-        default y
+config RT2800USB_RT33XX
+        bool "rt2800usb - Include support for rt33xx devices (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
+        default n
         ---help---
-          This adds support for rt30xx wireless chipset family to the
+          This adds support for rt33xx wireless chipset family to the
           rt2800usb driver.
-          Supported chips: RT3070, RT3071 & RT3072
+          Supported chips: RT3370
 
           Support for these devices is non-functional at the moment and is
           intended for testers and developers.
 
 config RT2800USB_RT35XX
-        bool "rt2800usb - Include support for rt35xx (USB) devices"
+        bool "rt2800usb - Include support for rt35xx devices (EXPERIMENTAL)"
+        depends on EXPERIMENTAL
         default n
         ---help---
           This adds support for rt35xx wireless chipset family to the
@@ -180,9 +168,9 @@ config RT2800USB_UNKNOWN
         bool "rt2800usb - Include support for unknown (USB) devices"
         default n
         ---help---
-          This adds support for rt2800 family devices that are known to
-          have a rt2800 family chipset, but for which the exact chipset
-          is unknown.
+          This adds support for rt2800usb devices that are known to
+          have a rt28xx family compatible chipset, but for which the exact
+          chipset is unknown.
 
           Support status for these devices is unknown, and enabling these
           devices may or may not work.
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 4f420a9ec5dc..54ca49ad3472 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -633,6 +633,88 @@ static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
 }
 
 /*
+ * Queue handlers.
+ */
+static void rt2400pci_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
+                rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
+                rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
+                rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
+                rt2x00_set_field32(&reg, CSR14_TBCN, 1);
+                rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
+                rt2x00pci_register_write(rt2x00dev, CSR14, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2400pci_kick_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        case QID_AC_VI:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        case QID_ATIM:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2400pci_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_ATIM:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        case QID_RX:
+                rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
+                rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
+                rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
+                rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
+                rt2x00_set_field32(&reg, CSR14_TBCN, 0);
+                rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
+                rt2x00pci_register_write(rt2x00dev, CSR14, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+/*
  * Initialization functions.
  */
 static bool rt2400pci_get_entry_state(struct queue_entry *entry)
@@ -878,18 +960,6 @@ static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 /*
  * Device state switch handlers.
  */
-static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-        u32 reg;
-
-        rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
-        rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
-                           (state == STATE_RADIO_RX_OFF) ||
-                           (state == STATE_RADIO_RX_OFF_LINK));
-        rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
                                  enum dev_state state)
 {
@@ -988,12 +1058,6 @@ static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
         case STATE_RADIO_OFF:
                 rt2400pci_disable_radio(rt2x00dev);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt2400pci_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -1125,32 +1189,6 @@ static void rt2400pci_write_beacon(struct queue_entry *entry,
         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 }
 
-static void rt2400pci_kick_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-        rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE));
-        rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK));
-        rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM));
-        rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-}
-
-static void rt2400pci_kill_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        if (queue->qid == QID_BEACON) {
-                rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-        } else {
-                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-                rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
-                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-        }
-}
-
 /*
  * RX control handlers
  */
@@ -1284,13 +1322,13 @@ static irqreturn_t rt2400pci_interrupt_thread(int irq, void *dev_instance)
          * 4 - Priority ring transmit done interrupt.
          */
         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
-                rt2400pci_txdone(rt2x00dev, QID_AC_BE);
+                rt2400pci_txdone(rt2x00dev, QID_AC_VO);
 
         /*
          * 5 - Tx ring transmit done interrupt.
          */
         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
-                rt2400pci_txdone(rt2x00dev, QID_AC_BK);
+                rt2400pci_txdone(rt2x00dev, QID_AC_VI);
 
         /* Enable interrupts again. */
         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
@@ -1612,6 +1650,7 @@ static const struct ieee80211_ops rt2400pci_mac80211_ops = {
         .get_tsf                = rt2400pci_get_tsf,
         .tx_last_beacon         = rt2400pci_tx_last_beacon,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
+        .flush                  = rt2x00mac_flush,
 };
 
 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
@@ -1627,10 +1666,11 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
         .link_stats             = rt2400pci_link_stats,
         .reset_tuner            = rt2400pci_reset_tuner,
         .link_tuner             = rt2400pci_link_tuner,
+        .start_queue            = rt2400pci_start_queue,
+        .kick_queue             = rt2400pci_kick_queue,
+        .stop_queue             = rt2400pci_stop_queue,
         .write_tx_desc          = rt2400pci_write_tx_desc,
         .write_beacon           = rt2400pci_write_beacon,
-        .kick_tx_queue          = rt2400pci_kick_tx_queue,
-        .kill_tx_queue          = rt2400pci_kill_tx_queue,
         .fill_rxdone            = rt2400pci_fill_rxdone,
         .config_filter          = rt2400pci_config_filter,
         .config_intf            = rt2400pci_config_intf,
@@ -1640,28 +1680,28 @@ static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt2400pci_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 24,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = RXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2400pci_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 24,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2400pci_queue_bcn = {
-        .entry_num              = BEACON_ENTRIES,
+        .entry_num              = 1,
         .data_size              = MGMT_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2400pci_queue_atim = {
-        .entry_num              = ATIM_ENTRIES,
+        .entry_num              = 8,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.h b/drivers/net/wireless/rt2x00/rt2400pci.h
index c048b18f4133..d3a4a68cc439 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.h
+++ b/drivers/net/wireless/rt2x00/rt2400pci.h
@@ -809,8 +809,8 @@
 /*
  * DMA descriptor defines.
  */
-#define TXD_DESC_SIZE                   ( 8 * sizeof(__le32) )
-#define RXD_DESC_SIZE                   ( 8 * sizeof(__le32) )
+#define TXD_DESC_SIZE                   (8 * sizeof(__le32))
+#define RXD_DESC_SIZE                   (8 * sizeof(__le32))
 
 /*
  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
@@ -948,6 +948,6 @@
         ((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)
 
 #define TXPOWER_TO_DEV(__txpower) \
-        MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER)
+        (MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER))
 
 #endif /* RT2400PCI_H */
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 97feb7aef809..a9ff26a27724 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -723,6 +723,88 @@ dynamic_cca_tune:
 }
 
 /*
+ * Queue handlers.
+ */
+static void rt2500pci_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
+                rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
+                rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
+                rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
+                rt2x00_set_field32(&reg, CSR14_TBCN, 1);
+                rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
+                rt2x00pci_register_write(rt2x00dev, CSR14, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2500pci_kick_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        case QID_AC_VI:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        case QID_ATIM:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2500pci_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_ATIM:
+                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
+                rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
+                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
+                break;
+        case QID_RX:
+                rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
+                rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
+                rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
+                rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
+                rt2x00_set_field32(&reg, CSR14_TBCN, 0);
+                rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
+                rt2x00pci_register_write(rt2x00dev, CSR14, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+/*
  * Initialization functions.
  */
 static bool rt2500pci_get_entry_state(struct queue_entry *entry)
@@ -1033,18 +1115,6 @@ static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 /*
  * Device state switch handlers.
  */
-static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-        u32 reg;
-
-        rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
-        rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
-                           (state == STATE_RADIO_RX_OFF) ||
-                           (state == STATE_RADIO_RX_OFF_LINK));
-        rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
-}
-
 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
                                  enum dev_state state)
 {
@@ -1143,12 +1213,6 @@ static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
         case STATE_RADIO_OFF:
                 rt2500pci_disable_radio(rt2x00dev);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt2500pci_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -1193,9 +1257,9 @@ static void rt2500pci_write_tx_desc(struct queue_entry *entry,
 
         rt2x00_desc_read(txd, 2, &word);
         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
-        rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
-        rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
-        rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
+        rt2x00_set_field32(&word, TXD_W2_AIFS, entry->queue->aifs);
+        rt2x00_set_field32(&word, TXD_W2_CWMIN, entry->queue->cw_min);
+        rt2x00_set_field32(&word, TXD_W2_CWMAX, entry->queue->cw_max);
         rt2x00_desc_write(txd, 2, word);
 
         rt2x00_desc_read(txd, 3, &word);
@@ -1279,32 +1343,6 @@ static void rt2500pci_write_beacon(struct queue_entry *entry,
         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 }
 
-static void rt2500pci_kick_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-        rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue->qid == QID_AC_BE));
-        rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue->qid == QID_AC_BK));
-        rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue->qid == QID_ATIM));
-        rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-}
-
-static void rt2500pci_kill_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        if (queue->qid == QID_BEACON) {
-                rt2x00pci_register_write(rt2x00dev, CSR14, 0);
-        } else {
-                rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
-                rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
-                rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
-        }
-}
-
 /*
  * RX control handlers
  */
@@ -1417,13 +1455,13 @@ static irqreturn_t rt2500pci_interrupt_thread(int irq, void *dev_instance)
          * 4 - Priority ring transmit done interrupt.
          */
         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
-                rt2500pci_txdone(rt2x00dev, QID_AC_BE);
+                rt2500pci_txdone(rt2x00dev, QID_AC_VO);
 
         /*
          * 5 - Tx ring transmit done interrupt.
          */
         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
-                rt2500pci_txdone(rt2x00dev, QID_AC_BK);
+                rt2500pci_txdone(rt2x00dev, QID_AC_VI);
 
         /* Enable interrupts again. */
         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
@@ -1909,6 +1947,7 @@ static const struct ieee80211_ops rt2500pci_mac80211_ops = {
         .get_tsf                = rt2500pci_get_tsf,
         .tx_last_beacon         = rt2500pci_tx_last_beacon,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
+        .flush                  = rt2x00mac_flush,
 };
 
 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
@@ -1924,10 +1963,11 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
         .link_stats             = rt2500pci_link_stats,
         .reset_tuner            = rt2500pci_reset_tuner,
         .link_tuner             = rt2500pci_link_tuner,
+        .start_queue            = rt2500pci_start_queue,
+        .kick_queue             = rt2500pci_kick_queue,
+        .stop_queue             = rt2500pci_stop_queue,
         .write_tx_desc          = rt2500pci_write_tx_desc,
         .write_beacon           = rt2500pci_write_beacon,
-        .kick_tx_queue          = rt2500pci_kick_tx_queue,
-        .kill_tx_queue          = rt2500pci_kill_tx_queue,
         .fill_rxdone            = rt2500pci_fill_rxdone,
         .config_filter          = rt2500pci_config_filter,
         .config_intf            = rt2500pci_config_intf,
@@ -1937,28 +1977,28 @@ static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt2500pci_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = RXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2500pci_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2500pci_queue_bcn = {
-        .entry_num              = BEACON_ENTRIES,
+        .entry_num              = 1,
         .data_size              = MGMT_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2500pci_queue_atim = {
-        .entry_num              = ATIM_ENTRIES,
+        .entry_num              = 8,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.h b/drivers/net/wireless/rt2x00/rt2500pci.h
index d708031361ac..2aad7ba8a100 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.h
+++ b/drivers/net/wireless/rt2x00/rt2500pci.h
@@ -1088,8 +1088,8 @@
 /*
  * DMA descriptor defines.
  */
-#define TXD_DESC_SIZE                   ( 11 * sizeof(__le32) )
-#define RXD_DESC_SIZE                   ( 11 * sizeof(__le32) )
+#define TXD_DESC_SIZE                   (11 * sizeof(__le32))
+#define RXD_DESC_SIZE                   (11 * sizeof(__le32))
 
 /*
  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 93e44c7f3a74..6b3b1de46792 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -39,7 +39,7 @@
 /*
  * Allow hardware encryption to be disabled.
  */
-static int modparam_nohwcrypt = 0;
+static int modparam_nohwcrypt;
 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
 
@@ -739,6 +739,55 @@ static void rt2500usb_reset_tuner(struct rt2x00_dev *rt2x00dev,
 }
 
 /*
+ * Queue handlers.
+ */
+static void rt2500usb_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u16 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
+                rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 0);
+                rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
+                break;
+        case QID_BEACON:
+                rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
+                rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
+                rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
+                rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
+                rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2500usb_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u16 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
+                rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX, 1);
+                rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
+                break;
+        case QID_BEACON:
+                rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
+                rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 0);
+                rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 0);
+                rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 0);
+                rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+/*
  * Initialization functions.
  */
 static int rt2500usb_init_registers(struct rt2x00_dev *rt2x00dev)
@@ -931,18 +980,6 @@ static int rt2500usb_init_bbp(struct rt2x00_dev *rt2x00dev)
 /*
  * Device state switch handlers.
  */
-static void rt2500usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-        u16 reg;
-
-        rt2500usb_register_read(rt2x00dev, TXRX_CSR2, &reg);
-        rt2x00_set_field16(&reg, TXRX_CSR2_DISABLE_RX,
-                           (state == STATE_RADIO_RX_OFF) ||
-                           (state == STATE_RADIO_RX_OFF_LINK));
-        rt2500usb_register_write(rt2x00dev, TXRX_CSR2, reg);
-}
-
 static int rt2500usb_enable_radio(struct rt2x00_dev *rt2x00dev)
 {
         /*
@@ -1018,12 +1055,6 @@ static int rt2500usb_set_device_state(struct rt2x00_dev *rt2x00dev,
         case STATE_RADIO_OFF:
                 rt2500usb_disable_radio(rt2x00dev);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt2500usb_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -1081,9 +1112,9 @@ static void rt2500usb_write_tx_desc(struct queue_entry *entry,
 
         rt2x00_desc_read(txd, 1, &word);
         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
-        rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
-        rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
-        rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
+        rt2x00_set_field32(&word, TXD_W1_AIFS, entry->queue->aifs);
+        rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
+        rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
         rt2x00_desc_write(txd, 1, word);
 
         rt2x00_desc_read(txd, 2, &word);
@@ -1206,14 +1237,6 @@ static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
         return length;
 }
 
-static void rt2500usb_kill_tx_queue(struct data_queue *queue)
-{
-        if (queue->qid == QID_BEACON)
-                rt2500usb_register_write(queue->rt2x00dev, TXRX_CSR19, 0);
-
-        rt2x00usb_kill_tx_queue(queue);
-}
-
 /*
  * RX control handlers
  */
@@ -1801,6 +1824,7 @@ static const struct ieee80211_ops rt2500usb_mac80211_ops = {
         .bss_info_changed       = rt2x00mac_bss_info_changed,
         .conf_tx                = rt2x00mac_conf_tx,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
+        .flush                  = rt2x00mac_flush,
 };
 
 static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
@@ -1813,11 +1837,13 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
         .link_stats             = rt2500usb_link_stats,
         .reset_tuner            = rt2500usb_reset_tuner,
         .watchdog               = rt2x00usb_watchdog,
+        .start_queue            = rt2500usb_start_queue,
+        .kick_queue             = rt2x00usb_kick_queue,
+        .stop_queue             = rt2500usb_stop_queue,
+        .flush_queue            = rt2x00usb_flush_queue,
         .write_tx_desc          = rt2500usb_write_tx_desc,
         .write_beacon           = rt2500usb_write_beacon,
         .get_tx_data_len        = rt2500usb_get_tx_data_len,
-        .kick_tx_queue          = rt2x00usb_kick_tx_queue,
-        .kill_tx_queue          = rt2500usb_kill_tx_queue,
         .fill_rxdone            = rt2500usb_fill_rxdone,
         .config_shared_key      = rt2500usb_config_key,
         .config_pairwise_key    = rt2500usb_config_key,
@@ -1829,28 +1855,28 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt2500usb_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = RXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
 };
 
 static const struct data_queue_desc rt2500usb_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
 };
 
 static const struct data_queue_desc rt2500usb_queue_bcn = {
-        .entry_num              = BEACON_ENTRIES,
+        .entry_num              = 1,
         .data_size              = MGMT_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb_bcn),
 };
 
 static const struct data_queue_desc rt2500usb_queue_atim = {
-        .entry_num              = ATIM_ENTRIES,
+        .entry_num              = 8,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index eb8b6cab9925..4c55e8525cad 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -46,7 +46,11 @@
  * RF2020 2.4G B/G
  * RF3021 2.4G 1T2R
  * RF3022 2.4G 2T2R
- * RF3052 2.4G 2T2R
+ * RF3052 2.4G/5G 2T2R
+ * RF2853 2.4G/5G 3T3R
+ * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390)
+ * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392)
+ * RF3853 2.4G/5G 3T3R(RT3883/RT3563/RT3573/RT3593/RT3662)
  */
 #define RF2820                          0x0001
 #define RF2850                          0x0002
@@ -57,7 +61,10 @@
 #define RF3021                          0x0007
 #define RF3022                          0x0008
 #define RF3052                          0x0009
+#define RF2853                          0x000a
 #define RF3320                          0x000b
+#define RF3322                          0x000c
+#define RF3853                          0x000d
 
 /*
  * Chipset revisions.
@@ -206,10 +213,10 @@
 
 /*
  * WMM_AIFSN_CFG: Aifsn for each EDCA AC
- * AIFSN0: AC_BE
- * AIFSN1: AC_BK
- * AIFSN2: AC_VI
- * AIFSN3: AC_VO
+ * AIFSN0: AC_VO
+ * AIFSN1: AC_VI
+ * AIFSN2: AC_BE
+ * AIFSN3: AC_BK
  */
 #define WMM_AIFSN_CFG                   0x0214
 #define WMM_AIFSN_CFG_AIFSN0            FIELD32(0x0000000f)
@@ -219,10 +226,10 @@
 
 /*
  * WMM_CWMIN_CSR: CWmin for each EDCA AC
- * CWMIN0: AC_BE
- * CWMIN1: AC_BK
- * CWMIN2: AC_VI
- * CWMIN3: AC_VO
+ * CWMIN0: AC_VO
+ * CWMIN1: AC_VI
+ * CWMIN2: AC_BE
+ * CWMIN3: AC_BK
  */
 #define WMM_CWMIN_CFG                   0x0218
 #define WMM_CWMIN_CFG_CWMIN0            FIELD32(0x0000000f)
@@ -232,10 +239,10 @@
 
 /*
  * WMM_CWMAX_CSR: CWmax for each EDCA AC
- * CWMAX0: AC_BE
- * CWMAX1: AC_BK
- * CWMAX2: AC_VI
- * CWMAX3: AC_VO
+ * CWMAX0: AC_VO
+ * CWMAX1: AC_VI
+ * CWMAX2: AC_BE
+ * CWMAX3: AC_BK
  */
 #define WMM_CWMAX_CFG                   0x021c
 #define WMM_CWMAX_CFG_CWMAX0            FIELD32(0x0000000f)
@@ -244,18 +251,18 @@
 #define WMM_CWMAX_CFG_CWMAX3            FIELD32(0x0000f000)
 
 /*
- * AC_TXOP0: AC_BK/AC_BE TXOP register
- * AC0TXOP: AC_BK in unit of 32us
- * AC1TXOP: AC_BE in unit of 32us
+ * AC_TXOP0: AC_VO/AC_VI TXOP register
+ * AC0TXOP: AC_VO in unit of 32us
+ * AC1TXOP: AC_VI in unit of 32us
  */
 #define WMM_TXOP0_CFG                   0x0220
 #define WMM_TXOP0_CFG_AC0TXOP           FIELD32(0x0000ffff)
 #define WMM_TXOP0_CFG_AC1TXOP           FIELD32(0xffff0000)
 
 /*
- * AC_TXOP1: AC_VO/AC_VI TXOP register
- * AC2TXOP: AC_VI in unit of 32us
- * AC3TXOP: AC_VO in unit of 32us
+ * AC_TXOP1: AC_BE/AC_BK TXOP register
+ * AC2TXOP: AC_BE in unit of 32us
+ * AC3TXOP: AC_BK in unit of 32us
  */
 #define WMM_TXOP1_CFG                   0x0224
 #define WMM_TXOP1_CFG_AC2TXOP           FIELD32(0x0000ffff)
@@ -281,7 +288,7 @@
 #define MCU_CMD_CFG                     0x022c
 
 /*
- * AC_BK register offsets
+ * AC_VO register offsets
  */
 #define TX_BASE_PTR0                    0x0230
 #define TX_MAX_CNT0                     0x0234
@@ -289,7 +296,7 @@
 #define TX_DTX_IDX0                     0x023c
 
 /*
- * AC_BE register offsets
+ * AC_VI register offsets
  */
 #define TX_BASE_PTR1                    0x0240
 #define TX_MAX_CNT1                     0x0244
@@ -297,7 +304,7 @@
 #define TX_DTX_IDX1                     0x024c
 
 /*
- * AC_VI register offsets
+ * AC_BE register offsets
  */
 #define TX_BASE_PTR2                    0x0250
 #define TX_MAX_CNT2                     0x0254
@@ -305,7 +312,7 @@
 #define TX_DTX_IDX2                     0x025c
 
 /*
- * AC_VO register offsets
+ * AC_BK register offsets
  */
 #define TX_BASE_PTR3                    0x0260
 #define TX_MAX_CNT3                     0x0264
@@ -412,10 +419,22 @@
 #define BCN_OFFSET1_BCN7                FIELD32(0xff000000)
 
 /*
- * PBF registers
- * Most are for debug. Driver doesn't touch PBF register.
+ * TXRXQ_PCNT: PBF register
+ * PCNT_TX0Q: Page count for TX hardware queue 0
+ * PCNT_TX1Q: Page count for TX hardware queue 1
+ * PCNT_TX2Q: Page count for TX hardware queue 2
+ * PCNT_RX0Q: Page count for RX hardware queue
  */
 #define TXRXQ_PCNT                      0x0438
+#define TXRXQ_PCNT_TX0Q                 FIELD32(0x000000ff)
+#define TXRXQ_PCNT_TX1Q                 FIELD32(0x0000ff00)
+#define TXRXQ_PCNT_TX2Q                 FIELD32(0x00ff0000)
+#define TXRXQ_PCNT_RX0Q                 FIELD32(0xff000000)
+
+/*
+ * PBF register
+ * Debug. Driver doesn't touch PBF register.
+ */
 #define PBF_DBG                         0x043c
 
 /*
@@ -686,8 +705,18 @@
 
 /*
  * CH_TIME_CFG: count as channel busy
+ * EIFS_BUSY: Count EIFS as channel busy
+ * NAV_BUSY: Count NAS as channel busy
+ * RX_BUSY: Count RX as channel busy
+ * TX_BUSY: Count TX as channel busy
+ * TMR_EN: Enable channel statistics timer
  */
 #define CH_TIME_CFG                     0x110c
+#define CH_TIME_CFG_EIFS_BUSY           FIELD32(0x00000010)
+#define CH_TIME_CFG_NAV_BUSY            FIELD32(0x00000008)
+#define CH_TIME_CFG_RX_BUSY             FIELD32(0x00000004)
+#define CH_TIME_CFG_TX_BUSY             FIELD32(0x00000002)
+#define CH_TIME_CFG_TMR_EN              FIELD32(0x00000001)
 
 /*
  * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
@@ -960,8 +989,31 @@
 
 /*
  * TXOP_CTRL_CFG:
+ * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation
+ * AC_TRUN_EN: Enable/Disable truncation for AC change
+ * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change
+ * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode
+ * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS
+ * RESERVED_TRUN_EN: Reserved
+ * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection
+ * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz
+ *             transmissions if extension CCA is clear).
+ * EXT_CCA_DLY: Extension CCA signal delay time (unit: us)
+ * EXT_CWMIN: CwMin for extension channel backoff
+ *            0: Disabled
+ *
  */
 #define TXOP_CTRL_CFG                   0x1340
+#define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN   FIELD32(0x00000001)
+#define TXOP_CTRL_CFG_AC_TRUN_EN        FIELD32(0x00000002)
+#define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN FIELD32(0x00000004)
+#define TXOP_CTRL_CFG_USER_MODE_TRUN_EN FIELD32(0x00000008)
+#define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN   FIELD32(0x00000010)
+#define TXOP_CTRL_CFG_RESERVED_TRUN_EN  FIELD32(0x00000020)
+#define TXOP_CTRL_CFG_LSIG_TXOP_EN      FIELD32(0x00000040)
+#define TXOP_CTRL_CFG_EXT_CCA_EN        FIELD32(0x00000080)
+#define TXOP_CTRL_CFG_EXT_CCA_DLY       FIELD32(0x0000ff00)
+#define TXOP_CTRL_CFG_EXT_CWMIN         FIELD32(0x000f0000)
 
 /*
  * TX_RTS_CFG:
@@ -1485,17 +1537,17 @@
 #define SHARED_KEY_MODE_BASE            0x7000
 
 #define MAC_WCID_ENTRY(__idx) \
-        ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
+        (MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)))
 #define PAIRWISE_KEY_ENTRY(__idx) \
-        ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
+        (PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
 #define MAC_IVEIV_ENTRY(__idx) \
-        ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
+        (MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)))
 #define MAC_WCID_ATTR_ENTRY(__idx) \
-        ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
+        (MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)))
 #define SHARED_KEY_ENTRY(__idx) \
-        ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
+        (SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)))
 #define SHARED_KEY_MODE_ENTRY(__idx) \
-        ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
+        (SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)))
 
 struct mac_wcid_entry {
         u8 mac[6];
@@ -1635,9 +1687,9 @@ struct mac_iveiv_entry {
 #define HW_BEACON_BASE7                 0x5bc0
 
 #define HW_BEACON_OFFSET(__index) \
-        ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
-          (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
-          (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
+        (((__index) < 4) ? (HW_BEACON_BASE0 + (__index * 0x0200)) : \
+          (((__index) < 6) ? (HW_BEACON_BASE4 + ((__index - 4) * 0x0200)) : \
+          (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))))
 
 /*
  * BBP registers.
@@ -1805,32 +1857,51 @@ struct mac_iveiv_entry {
 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 
 /*
- * EEPROM ANTENNA config
+ * EEPROM NIC Configuration 0
  * RXPATH: 1: 1R, 2: 2R, 3: 3R
- * TXPATH: 1: 1T, 2: 2T
- */
-#define EEPROM_ANTENNA                  0x001a
-#define EEPROM_ANTENNA_RXPATH           FIELD16(0x000f)
-#define EEPROM_ANTENNA_TXPATH           FIELD16(0x00f0)
-#define EEPROM_ANTENNA_RF_TYPE          FIELD16(0x0f00)
-
-/*
- * EEPROM NIC config
- * CARDBUS_ACCEL: 0 - enable, 1 - disable
- */
-#define EEPROM_NIC                      0x001b
-#define EEPROM_NIC_HW_RADIO             FIELD16(0x0001)
-#define EEPROM_NIC_DYNAMIC_TX_AGC       FIELD16(0x0002)
-#define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0004)
-#define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0008)
-#define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0010)
-#define EEPROM_NIC_BW40M_SB_BG          FIELD16(0x0020)
-#define EEPROM_NIC_BW40M_SB_A           FIELD16(0x0040)
-#define EEPROM_NIC_WPS_PBC              FIELD16(0x0080)
-#define EEPROM_NIC_BW40M_BG             FIELD16(0x0100)
-#define EEPROM_NIC_BW40M_A              FIELD16(0x0200)
-#define EEPROM_NIC_ANT_DIVERSITY        FIELD16(0x0800)
-#define EEPROM_NIC_DAC_TEST             FIELD16(0x8000)
+ * TXPATH: 1: 1T, 2: 2T, 3: 3T
+ * RF_TYPE: RFIC type
+ */
+#define EEPROM_NIC_CONF0                0x001a
+#define EEPROM_NIC_CONF0_RXPATH         FIELD16(0x000f)
+#define EEPROM_NIC_CONF0_TXPATH         FIELD16(0x00f0)
+#define EEPROM_NIC_CONF0_RF_TYPE                FIELD16(0x0f00)
+
+/*
+ * EEPROM NIC Configuration 1
+ * HW_RADIO: 0: disable, 1: enable
+ * EXTERNAL_TX_ALC: 0: disable, 1: enable
+ * EXTERNAL_LNA_2G: 0: disable, 1: enable
+ * EXTERNAL_LNA_5G: 0: disable, 1: enable
+ * CARDBUS_ACCEL: 0: enable, 1: disable
+ * BW40M_SB_2G: 0: disable, 1: enable
+ * BW40M_SB_5G: 0: disable, 1: enable
+ * WPS_PBC: 0: disable, 1: enable
+ * BW40M_2G: 0: enable, 1: disable
+ * BW40M_5G: 0: enable, 1: disable
+ * BROADBAND_EXT_LNA: 0: disable, 1: enable
+ * ANT_DIVERSITY: 00: Disable, 01: Diversity,
+ *                                10: Main antenna, 11: Aux antenna
+ * INTERNAL_TX_ALC: 0: disable, 1: enable
+ * BT_COEXIST: 0: disable, 1: enable
+ * DAC_TEST: 0: disable, 1: enable
+ */
+#define EEPROM_NIC_CONF1                0x001b
+#define EEPROM_NIC_CONF1_HW_RADIO               FIELD16(0x0001)
+#define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC                FIELD16(0x0002)
+#define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G                FIELD16(0x0004)
+#define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G                FIELD16(0x0008)
+#define EEPROM_NIC_CONF1_CARDBUS_ACCEL          FIELD16(0x0010)
+#define EEPROM_NIC_CONF1_BW40M_SB_2G            FIELD16(0x0020)
+#define EEPROM_NIC_CONF1_BW40M_SB_5G            FIELD16(0x0040)
+#define EEPROM_NIC_CONF1_WPS_PBC                FIELD16(0x0080)
+#define EEPROM_NIC_CONF1_BW40M_2G               FIELD16(0x0100)
+#define EEPROM_NIC_CONF1_BW40M_5G               FIELD16(0x0200)
+#define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA              FIELD16(0x400)
+#define EEPROM_NIC_CONF1_ANT_DIVERSITY          FIELD16(0x1800)
+#define EEPROM_NIC_CONF1_INTERNAL_TX_ALC                FIELD16(0x2000)
+#define EEPROM_NIC_CONF1_BT_COEXIST             FIELD16(0x4000)
+#define EEPROM_NIC_CONF1_DAC_TEST               FIELD16(0x8000)
 
 /*
  * EEPROM frequency
@@ -1852,9 +1923,9 @@ struct mac_iveiv_entry {
  * POLARITY_GPIO_4: Polarity GPIO4 setting.
  * LED_MODE: Led mode.
  */
-#define EEPROM_LED1                     0x001e
-#define EEPROM_LED2                     0x001f
-#define EEPROM_LED3                     0x0020
+#define EEPROM_LED_AG_CONF              0x001e
+#define EEPROM_LED_ACT_CONF             0x001f
+#define EEPROM_LED_POLARITY             0x0020
 #define EEPROM_LED_POLARITY_RDY_BG      FIELD16(0x0001)
 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
@@ -1866,6 +1937,17 @@ struct mac_iveiv_entry {
 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
 
 /*
+ * EEPROM NIC Configuration 2
+ * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
+ * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream
+ * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved
+ */
+#define EEPROM_NIC_CONF2                0x0021
+#define EEPROM_NIC_CONF2_RX_STREAM              FIELD16(0x000f)
+#define EEPROM_NIC_CONF2_TX_STREAM              FIELD16(0x00f0)
+#define EEPROM_NIC_CONF2_CRYSTAL                FIELD16(0x0600)
+
+/*
  * EEPROM LNA
  */
 #define EEPROM_LNA                      0x0022
@@ -1915,7 +1997,7 @@ struct mac_iveiv_entry {
 
 /*
  * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
- *      This is delta in 40MHZ.
+ * This is delta in 40MHZ.
  * VALUE: Tx Power dalta value (MAX=4)
  * TYPE: 1: Plus the delta value, 0: minus the delta value
  * TXPOWER: Enable:
@@ -1971,9 +2053,9 @@ struct mac_iveiv_entry {
 #define MCU_CURRENT                     0x36
 #define MCU_LED                         0x50
 #define MCU_LED_STRENGTH                0x51
-#define MCU_LED_1                       0x52
-#define MCU_LED_2                       0x53
-#define MCU_LED_3                       0x54
+#define MCU_LED_AG_CONF         0x52
+#define MCU_LED_ACT_CONF                0x53
+#define MCU_LED_LED_POLARITY            0x54
 #define MCU_RADAR                       0x60
 #define MCU_BOOT_SIGNAL                 0x72
 #define MCU_BBP_SIGNAL                  0x80
@@ -1987,8 +2069,8 @@ struct mac_iveiv_entry {
 /*
  * DMA descriptor defines.
  */
-#define TXWI_DESC_SIZE                  ( 4 * sizeof(__le32) )
-#define RXWI_DESC_SIZE                  ( 4 * sizeof(__le32) )
+#define TXWI_DESC_SIZE                  (4 * sizeof(__le32))
+#define RXWI_DESC_SIZE                  (4 * sizeof(__le32))
 
 /*
  * TX WI structure
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index 5f00e00789d8..54917a281398 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -277,13 +277,17 @@ int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
         unsigned int i;
         u32 reg;
 
+        /*
+         * Some devices are really slow to respond here. Wait a whole second
+         * before timing out.
+         */
         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
                         return 0;
 
-                msleep(1);
+                msleep(10);
         }
 
         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
@@ -483,7 +487,7 @@ void rt2800_write_tx_data(struct queue_entry *entry,
                            txdesc->key_idx : 0xff);
         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
                            txdesc->length);
-        rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, txdesc->qid);
+        rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
         rt2x00_desc_write(txwi, 1, word);
 
@@ -727,7 +731,7 @@ void rt2800_txdone(struct rt2x00_dev *rt2x00dev)
          * that the TX_STA_FIFO stack has a size of 16. We stick to our
          * tx ring size for now.
          */
-        for (i = 0; i < TX_ENTRIES; i++) {
+        for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
                         break;
@@ -768,6 +772,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
         unsigned int beacon_base;
+        unsigned int padding_len;
         u32 reg;
 
         /*
@@ -802,11 +807,13 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 
         /*
-         * Write entire beacon with TXWI to register.
+         * Write entire beacon with TXWI and padding to register.
          */
+        padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
+        skb_pad(entry->skb, padding_len);
         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
-        rt2800_register_multiwrite(rt2x00dev, beacon_base,
-                                   entry->skb->data, entry->skb->len);
+        rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
+                                   entry->skb->len + padding_len);
 
         /*
          * Enable beaconing again.
@@ -824,7 +831,7 @@ void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
 }
 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
 
-static void inline rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
+static inline void rt2800_clear_beacon(struct rt2x00_dev *rt2x00dev,
                                        unsigned int beacon_base)
 {
         int i;
@@ -1144,6 +1151,7 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
                         struct rt2x00intf_conf *conf, const unsigned int flags)
 {
         u32 reg;
+        bool update_bssid = false;
 
         if (flags & CONFIG_UPDATE_TYPE) {
                 /*
@@ -1173,6 +1181,16 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
         }
 
         if (flags & CONFIG_UPDATE_MAC) {
+                if (flags & CONFIG_UPDATE_TYPE &&
+                    conf->sync == TSF_SYNC_AP_NONE) {
+                        /*
+                         * The BSSID register has to be set to our own mac
+                         * address in AP mode.
+                         */
+                        memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
+                        update_bssid = true;
+                }
+
                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
                         reg = le32_to_cpu(conf->mac[1]);
                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
@@ -1183,7 +1201,7 @@ void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
                                               conf->mac, sizeof(conf->mac));
         }
 
-        if (flags & CONFIG_UPDATE_BSSID) {
+        if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
                         reg = le32_to_cpu(conf->bssid[1]);
                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
@@ -1529,7 +1547,8 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
             rt2x00_rf(rt2x00dev, RF3020) ||
             rt2x00_rf(rt2x00dev, RF3021) ||
             rt2x00_rf(rt2x00dev, RF3022) ||
-            rt2x00_rf(rt2x00dev, RF3052))
+            rt2x00_rf(rt2x00dev, RF3052) ||
+            rt2x00_rf(rt2x00dev, RF3320))
                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
         else
                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
@@ -1609,6 +1628,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
         }
 
         msleep(1);
+
+        /*
+         * Clear channel statistic counters
+         */
+        rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
+        rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
+        rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
 }
 
 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
@@ -1914,8 +1940,8 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
-                        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-                        if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
+                        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+                        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
                                                       0x0000002c);
                         else
@@ -2097,7 +2123,23 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
         }
 
-        rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
+        /*
+         * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
+         * although it is reserved.
+         */
+        rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
+        rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
+        rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
+
         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
 
         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
@@ -2134,7 +2176,7 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
                                          SHARED_KEY_MODE_ENTRY(i), 0);
 
         for (i = 0; i < 256; i++) {
-                u32 wcid[2] = { 0xffffffff, 0x00ffffff };
+                static const u32 wcid[2] = { 0xffffffff, 0x00ffffff };
                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
                                               wcid, sizeof(wcid));
 
@@ -2227,6 +2269,17 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
 
+        /*
+         * Set up channel statistics timer
+         */
+        rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
+        rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
+        rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
+        rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
+        rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
+        rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
+        rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
+
         return 0;
 }
 
@@ -2344,10 +2397,10 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
             rt2x00_rt(rt2x00dev, RT3390)) {
                 rt2800_bbp_read(rt2x00dev, 138, &value);
 
-                rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-                if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
+                rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
+                if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
                         value |= 0x20;
-                if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
+                if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
                         value &= ~0x02;
 
                 rt2800_bbp_write(rt2x00dev, 138, value);
@@ -2559,8 +2612,8 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
-                        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
-                        if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
+                        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
+                        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
                         else
                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
@@ -2633,10 +2686,10 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
         if (rt2x00_rt(rt2x00dev, RT3090)) {
                 rt2800_bbp_read(rt2x00dev, 138, &bbp);
 
-                rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
-                if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
+                rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
+                if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
-                if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
+                if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
 
                 rt2800_bbp_write(rt2x00dev, 138, bbp);
@@ -2735,16 +2788,16 @@ int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
         /*
          * Initialize LED control
          */
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
-        rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
+        rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
                            word & 0xff, (word >> 8) & 0xff);
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
-        rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
+        rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
                            word & 0xff, (word >> 8) & 0xff);
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
-        rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
+        rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
                            word & 0xff, (word >> 8) & 0xff);
 
         return 0;
@@ -2838,38 +2891,41 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
         }
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
         if (word == 0xffff) {
-                rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
-                rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
-                rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
-                rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
+                rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
                    rt2x00_rt(rt2x00dev, RT2872)) {
                 /*
                  * There is a max of 2 RX streams for RT28x0 series
                  */
-                if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
-                        rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
-                rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
+                if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
+                        rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
+                rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
         }
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
         if (word == 0xffff) {
-                rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_ANT_DIVERSITY, 0);
-                rt2x00_set_field16(&word, EEPROM_NIC_DAC_TEST, 0);
-                rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
+                rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
+                rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
         }
 
@@ -2884,9 +2940,9 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
                                    LED_MODE_TXRX_ACTIVITY);
                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
-                rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
-                rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
-                rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
+                rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
+                rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
+                rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
                 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
         }
 
@@ -2950,12 +3006,12 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
         /*
          * Read EEPROM word for configuration.
          */
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
 
         /*
          * Identify RF chipset.
          */
-        value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
+        value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
 
         rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
@@ -2981,7 +3037,8 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
             !rt2x00_rf(rt2x00dev, RF2020) &&
             !rt2x00_rf(rt2x00dev, RF3021) &&
             !rt2x00_rf(rt2x00dev, RF3022) &&
-            !rt2x00_rf(rt2x00dev, RF3052)) {
+            !rt2x00_rf(rt2x00dev, RF3052) &&
+            !rt2x00_rf(rt2x00dev, RF3320)) {
                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
                 return -ENODEV;
         }
@@ -2990,9 +3047,9 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
          * Identify default antenna configuration.
          */
         rt2x00dev->default_ant.tx =
-            rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
+            rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
         rt2x00dev->default_ant.rx =
-            rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
+            rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
 
         /*
          * Read frequency offset and RF programming sequence.
@@ -3003,17 +3060,17 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
         /*
          * Read external LNA informations.
          */
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
 
-        if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
+        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
-        if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
+        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 
         /*
          * Detect if this device has an hardware controlled radio.
          */
-        if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
+        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
 
         /*
@@ -3225,7 +3282,7 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
         rt2x00dev->hw->max_report_rates = 7;
         rt2x00dev->hw->max_rate_tries = 1;
 
-        rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
+        rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
 
         /*
          * Initialize hw_mode information.
@@ -3245,7 +3302,8 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
         } else if (rt2x00_rf(rt2x00dev, RF3020) ||
                    rt2x00_rf(rt2x00dev, RF2020) ||
                    rt2x00_rf(rt2x00dev, RF3021) ||
-                   rt2x00_rf(rt2x00dev, RF3022)) {
+                   rt2x00_rf(rt2x00dev, RF3022) ||
+                   rt2x00_rf(rt2x00dev, RF3320)) {
                 spec->num_channels = 14;
                 spec->channels = rf_vals_3x;
         } else if (rt2x00_rf(rt2x00dev, RF3052)) {
@@ -3268,11 +3326,11 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
             IEEE80211_HT_CAP_SGI_20 |
             IEEE80211_HT_CAP_SGI_40;
 
-        if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) >= 2)
+        if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
 
         spec->ht.cap |=
-            rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) <<
+            rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
                 IEEE80211_HT_CAP_RX_STBC_SHIFT;
 
         spec->ht.ampdu_factor = 3;
@@ -3280,10 +3338,10 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
         spec->ht.mcs.tx_params =
             IEEE80211_HT_MCS_TX_DEFINED |
             IEEE80211_HT_MCS_TX_RX_DIFF |
-            ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
+            ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
 
-        switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
+        switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
         case 3:
                 spec->ht.mcs.rx_mask[2] = 0xff;
         case 2:
@@ -3502,6 +3560,37 @@ int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 }
 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
 
+int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
+                      struct survey_info *survey)
+{
+        struct rt2x00_dev *rt2x00dev = hw->priv;
+        struct ieee80211_conf *conf = &hw->conf;
+        u32 idle, busy, busy_ext;
+
+        if (idx != 0)
+                return -ENOENT;
+
+        survey->channel = conf->channel;
+
+        rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
+        rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
+        rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
+
+        if (idle || busy) {
+                survey->filled = SURVEY_INFO_CHANNEL_TIME |
+                                 SURVEY_INFO_CHANNEL_TIME_BUSY |
+                                 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
+
+                survey->channel_time = (idle + busy) / 1000;
+                survey->channel_time_busy = busy / 1000;
+                survey->channel_time_ext_busy = busy_ext / 1000;
+        }
+
+        return 0;
+
+}
+EXPORT_SYMBOL_GPL(rt2800_get_survey);
+
 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
 MODULE_VERSION(DRV_VERSION);
 MODULE_DESCRIPTION("Ralink RT2800 library");
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
index 81cbc92e7857..e3c995a9dec4 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -199,5 +199,7 @@ u64 rt2800_get_tsf(struct ieee80211_hw *hw);
 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
                         enum ieee80211_ampdu_mlme_action action,
                         struct ieee80211_sta *sta, u16 tid, u16 *ssn);
+int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
+                      struct survey_info *survey);
 
 #endif /* RT2800LIB_H */
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index b26739535986..aa97971a38af 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -84,20 +84,22 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 }
 
-#ifdef CONFIG_RT2800PCI_SOC
+#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 {
-        u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
+        void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
 
         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
+
+        iounmap(base_addr);
 }
 #else
 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 {
 }
-#endif /* CONFIG_RT2800PCI_SOC */
+#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
 
-#ifdef CONFIG_RT2800PCI_PCI
+#ifdef CONFIG_PCI
 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 {
         struct rt2x00_dev *rt2x00dev = eeprom->data;
@@ -181,7 +183,78 @@ static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 {
 }
-#endif /* CONFIG_RT2800PCI_PCI */
+#endif /* CONFIG_PCI */
+
+/*
+ * Queue handlers.
+ */
+static void rt2800pci_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
+                rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
+                rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
+                break;
+        case QID_BEACON:
+                rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
+                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
+                break;
+        default:
+                break;
+        };
+}
+
+static void rt2800pci_kick_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        struct queue_entry *entry;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_AC_BE:
+        case QID_AC_BK:
+                entry = rt2x00queue_get_entry(queue, Q_INDEX);
+                rt2800_register_write(rt2x00dev, TX_CTX_IDX(queue->qid), entry->entry_idx);
+                break;
+        case QID_MGMT:
+                entry = rt2x00queue_get_entry(queue, Q_INDEX);
+                rt2800_register_write(rt2x00dev, TX_CTX_IDX(5), entry->entry_idx);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2800pci_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
+                rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
+                rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
+                break;
+        case QID_BEACON:
+                rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
+                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
+                break;
+        default:
+                break;
+        }
+}
 
 /*
  * Firmware functions
@@ -321,18 +394,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 /*
  * Device state switch handlers.
  */
-static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-        u32 reg;
-
-        rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
-        rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
-                           (state == STATE_RADIO_RX_ON) ||
-                           (state == STATE_RADIO_RX_ON_LINK));
-        rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
-}
-
 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
                                  enum dev_state state)
 {
@@ -442,7 +503,7 @@ static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
          * if the device is booting and wasn't asleep it will return
          * failure when attempting to wakeup.
          */
-        rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
+        rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
 
         if (state == STATE_AWAKE) {
                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
@@ -476,12 +537,6 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
                 rt2800pci_disable_radio(rt2x00dev);
                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt2800pci_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -567,41 +622,6 @@ static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 }
 
 /*
- * TX data initialization
- */
-static void rt2800pci_kick_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
-        unsigned int qidx;
-
-        if (queue->qid == QID_MGMT)
-                qidx = 5;
-        else
-                qidx = queue->qid;
-
-        rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), entry->entry_idx);
-}
-
-static void rt2800pci_kill_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        if (queue->qid == QID_BEACON) {
-                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
-                return;
-        }
-
-        rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
-        rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (queue->qid == QID_AC_BE));
-        rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (queue->qid == QID_AC_BK));
-        rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (queue->qid == QID_AC_VI));
-        rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (queue->qid == QID_AC_VO));
-        rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
-}
-
-/*
  * RX control handlers
  */
 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
@@ -668,14 +688,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
         u32 status;
         u8 qid;
 
-        while (!kfifo_is_empty(&rt2x00dev->txstatus_fifo)) {
-                /* Now remove the tx status from the FIFO */
-                if (kfifo_out(&rt2x00dev->txstatus_fifo, &status,
-                              sizeof(status)) != sizeof(status)) {
-                        WARN_ON(1);
-                        break;
-                }
-
+        while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
                 if (qid >= QID_RX) {
                         /*
@@ -683,7 +696,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
                          * this tx status.
                          */
                         WARNING(rt2x00dev, "Got TX status report with "
-                                           "unexpected pid %u, dropping", qid);
+                                           "unexpected pid %u, dropping\n", qid);
                         break;
                 }
 
@@ -694,7 +707,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
                          * processing here and drop the tx status
                          */
                         WARNING(rt2x00dev, "Got TX status for an unavailable "
-                                           "queue %u, dropping", qid);
+                                           "queue %u, dropping\n", qid);
                         break;
                 }
 
@@ -704,7 +717,7 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
                          * and drop the tx status.
                          */
                         WARNING(rt2x00dev, "Got TX status for an empty "
-                                           "queue %u, dropping", qid);
+                                           "queue %u, dropping\n", qid);
                         break;
                 }
 
@@ -777,20 +790,13 @@ static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
          * Since we have only one producer and one consumer we don't
          * need to lock the kfifo.
          */
-        for (i = 0; i < TX_ENTRIES; i++) {
+        for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &status);
 
                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
                         break;
 
-                if (kfifo_is_full(&rt2x00dev->txstatus_fifo)) {
-                        WARNING(rt2x00dev, "TX status FIFO overrun,"
-                                " drop tx status report.\n");
-                        break;
-                }
-
-                if (kfifo_in(&rt2x00dev->txstatus_fifo, &status,
-                             sizeof(status)) != sizeof(status)) {
+                if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
                         WARNING(rt2x00dev, "TX status FIFO overrun,"
                                 "drop tx status report.\n");
                         break;
@@ -912,6 +918,7 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
         __set_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags);
+        __set_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags);
         if (!modparam_nohwcrypt)
                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
@@ -943,6 +950,8 @@ static const struct ieee80211_ops rt2800pci_mac80211_ops = {
         .get_tsf                = rt2800_get_tsf,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
         .ampdu_action           = rt2800_ampdu_action,
+        .flush                  = rt2x00mac_flush,
+        .get_survey             = rt2800_get_survey,
 };
 
 static const struct rt2800_ops rt2800pci_rt2800_ops = {
@@ -975,11 +984,12 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
         .link_stats             = rt2800_link_stats,
         .reset_tuner            = rt2800_reset_tuner,
         .link_tuner             = rt2800_link_tuner,
+        .start_queue            = rt2800pci_start_queue,
+        .kick_queue             = rt2800pci_kick_queue,
+        .stop_queue             = rt2800pci_stop_queue,
         .write_tx_desc          = rt2800pci_write_tx_desc,
         .write_tx_data          = rt2800_write_tx_data,
         .write_beacon           = rt2800_write_beacon,
-        .kick_tx_queue          = rt2800pci_kick_tx_queue,
-        .kill_tx_queue          = rt2800pci_kill_tx_queue,
         .fill_rxdone            = rt2800pci_fill_rxdone,
         .config_shared_key      = rt2800_config_shared_key,
         .config_pairwise_key    = rt2800_config_pairwise_key,
@@ -991,21 +1001,21 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt2800pci_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 128,
         .data_size              = AGGREGATION_SIZE,
         .desc_size              = RXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2800pci_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 64,
         .data_size              = AGGREGATION_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt2800pci_queue_bcn = {
-        .entry_num              = 8 * BEACON_ENTRIES,
+        .entry_num              = 8,
         .data_size              = 0, /* No DMA required for beacons */
         .desc_size              = TXWI_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
@@ -1033,12 +1043,15 @@ static const struct rt2x00_ops rt2800pci_ops = {
 /*
  * RT2800pci module information.
  */
-#ifdef CONFIG_RT2800PCI_PCI
+#ifdef CONFIG_PCI
 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
+        { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
+        { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
+        { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
@@ -1046,12 +1059,10 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
-        { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
-#ifdef CONFIG_RT2800PCI_RT30XX
-        { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
-        { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
-        { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
+        { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
+#ifdef CONFIG_RT2800PCI_RT33XX
+        { PCI_DEVICE(0x1814, 0x3390), PCI_DEVICE_DATA(&rt2800pci_ops) },
 #endif
 #ifdef CONFIG_RT2800PCI_RT35XX
         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
@@ -1062,19 +1073,19 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
 #endif
         { 0, }
 };
-#endif /* CONFIG_RT2800PCI_PCI */
+#endif /* CONFIG_PCI */
 
 MODULE_AUTHOR(DRV_PROJECT);
 MODULE_VERSION(DRV_VERSION);
 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
-#ifdef CONFIG_RT2800PCI_PCI
+#ifdef CONFIG_PCI
 MODULE_FIRMWARE(FIRMWARE_RT2860);
 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
-#endif /* CONFIG_RT2800PCI_PCI */
+#endif /* CONFIG_PCI */
 MODULE_LICENSE("GPL");
 
-#ifdef CONFIG_RT2800PCI_SOC
+#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
 static int rt2800soc_probe(struct platform_device *pdev)
 {
         return rt2x00soc_probe(pdev, &rt2800pci_ops);
@@ -1091,9 +1102,9 @@ static struct platform_driver rt2800soc_driver = {
         .suspend        = rt2x00soc_suspend,
         .resume         = rt2x00soc_resume,
 };
-#endif /* CONFIG_RT2800PCI_SOC */
+#endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
 
-#ifdef CONFIG_RT2800PCI_PCI
+#ifdef CONFIG_PCI
 static struct pci_driver rt2800pci_driver = {
         .name           = KBUILD_MODNAME,
         .id_table       = rt2800pci_device_table,
@@ -1102,21 +1113,21 @@ static struct pci_driver rt2800pci_driver = {
         .suspend        = rt2x00pci_suspend,
         .resume         = rt2x00pci_resume,
 };
-#endif /* CONFIG_RT2800PCI_PCI */
+#endif /* CONFIG_PCI */
 
 static int __init rt2800pci_init(void)
 {
         int ret = 0;
 
-#ifdef CONFIG_RT2800PCI_SOC
+#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
         ret = platform_driver_register(&rt2800soc_driver);
         if (ret)
                 return ret;
 #endif
-#ifdef CONFIG_RT2800PCI_PCI
+#ifdef CONFIG_PCI
         ret = pci_register_driver(&rt2800pci_driver);
         if (ret) {
-#ifdef CONFIG_RT2800PCI_SOC
+#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
                 platform_driver_unregister(&rt2800soc_driver);
 #endif
                 return ret;
@@ -1128,10 +1139,10 @@ static int __init rt2800pci_init(void)
 
 static void __exit rt2800pci_exit(void)
 {
-#ifdef CONFIG_RT2800PCI_PCI
+#ifdef CONFIG_PCI
         pci_unregister_driver(&rt2800pci_driver);
 #endif
-#ifdef CONFIG_RT2800PCI_SOC
+#if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
         platform_driver_unregister(&rt2800soc_driver);
 #endif
 }
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.h b/drivers/net/wireless/rt2x00/rt2800pci.h
index 5a8dda9b5b5a..70e050d904c8 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.h
+++ b/drivers/net/wireless/rt2x00/rt2800pci.h
@@ -38,10 +38,10 @@
  * Queue register offset macros
  */
 #define TX_QUEUE_REG_OFFSET             0x10
-#define TX_BASE_PTR(__x)                TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
-#define TX_MAX_CNT(__x)                 TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
-#define TX_CTX_IDX(__x)                 TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
-#define TX_DTX_IDX(__x)                 TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
+#define TX_BASE_PTR(__x)                (TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET))
+#define TX_MAX_CNT(__x)                 (TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET))
+#define TX_CTX_IDX(__x)                 (TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
+#define TX_DTX_IDX(__x)                 (TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET))
 
 /*
  * 8051 firmware image.
@@ -52,8 +52,8 @@
 /*
  * DMA descriptor defines.
  */
-#define TXD_DESC_SIZE                   ( 4 * sizeof(__le32) )
-#define RXD_DESC_SIZE                   ( 4 * sizeof(__le32) )
+#define TXD_DESC_SIZE                   (4 * sizeof(__le32))
+#define RXD_DESC_SIZE                   (4 * sizeof(__le32))
 
 /*
  * TX descriptor format for TX, PRIO and Beacon Ring.
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 3dff56ec195a..b97a4a54ff4c 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -45,11 +45,60 @@
 /*
  * Allow hardware encryption to be disabled.
  */
-static int modparam_nohwcrypt = 0;
+static int modparam_nohwcrypt;
 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
 
 /*
+ * Queue handlers.
+ */
+static void rt2800usb_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
+                rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
+                rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
+                break;
+        case QID_BEACON:
+                rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
+                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt2800usb_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
+                rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
+                rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
+                break;
+        case QID_BEACON:
+                rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
+                rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
+                rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+/*
  * Firmware functions
  */
 static char *rt2800usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -107,18 +156,6 @@ static int rt2800usb_write_firmware(struct rt2x00_dev *rt2x00dev,
 /*
  * Device state switch handlers.
  */
-static void rt2800usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                                enum dev_state state)
-{
-        u32 reg;
-
-        rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
-        rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
-                           (state == STATE_RADIO_RX_ON) ||
-                           (state == STATE_RADIO_RX_ON_LINK));
-        rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
-}
-
 static int rt2800usb_init_registers(struct rt2x00_dev *rt2x00dev)
 {
         u32 reg;
@@ -165,7 +202,8 @@ static int rt2800usb_enable_radio(struct rt2x00_dev *rt2x00dev)
          * this limit so reduce the number to prevent errors.
          */
         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_AGG_LIMIT,
-                           ((RX_ENTRIES * DATA_FRAME_SIZE) / 1024) - 3);
+                           ((rt2x00dev->ops->rx->entry_num * DATA_FRAME_SIZE)
+                            / 1024) - 3);
         rt2x00_set_field32(&reg, USB_DMA_CFG_RX_BULK_EN, 1);
         rt2x00_set_field32(&reg, USB_DMA_CFG_TX_BULK_EN, 1);
         rt2800_register_write(rt2x00dev, USB_DMA_CFG, reg);
@@ -183,9 +221,9 @@ static int rt2800usb_set_state(struct rt2x00_dev *rt2x00dev,
                                enum dev_state state)
 {
         if (state == STATE_AWAKE)
-                rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
+                rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 2);
         else
-                rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
+                rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0xff, 2);
 
         return 0;
 }
@@ -214,12 +252,6 @@ static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
                 rt2800usb_disable_radio(rt2x00dev);
                 rt2800usb_set_state(rt2x00dev, STATE_SLEEP);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt2800usb_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -245,6 +277,49 @@ static int rt2800usb_set_device_state(struct rt2x00_dev *rt2x00dev,
 }
 
 /*
+ * Watchdog handlers
+ */
+static void rt2800usb_watchdog(struct rt2x00_dev *rt2x00dev)
+{
+        unsigned int i;
+        u32 reg;
+
+        rt2800_register_read(rt2x00dev, TXRXQ_PCNT, &reg);
+        if (rt2x00_get_field32(reg, TXRXQ_PCNT_TX0Q)) {
+                WARNING(rt2x00dev, "TX HW queue 0 timed out,"
+                        " invoke forced kick\n");
+
+                rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40012);
+
+                for (i = 0; i < 10; i++) {
+                        udelay(10);
+                        if (!rt2x00_get_field32(reg, TXRXQ_PCNT_TX0Q))
+                                break;
+                }
+
+                rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
+        }
+
+        rt2800_register_read(rt2x00dev, TXRXQ_PCNT, &reg);
+        if (rt2x00_get_field32(reg, TXRXQ_PCNT_TX1Q)) {
+                WARNING(rt2x00dev, "TX HW queue 1 timed out,"
+                        " invoke forced kick\n");
+
+                rt2800_register_write(rt2x00dev, PBF_CFG, 0xf4000a);
+
+                for (i = 0; i < 10; i++) {
+                        udelay(10);
+                        if (!rt2x00_get_field32(reg, TXRXQ_PCNT_TX1Q))
+                                break;
+                }
+
+                rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
+        }
+
+        rt2x00usb_watchdog(rt2x00dev);
+}
+
+/*
  * TX descriptor initialization
  */
 static __le32 *rt2800usb_get_txwi(struct queue_entry *entry)
@@ -266,8 +341,14 @@ static void rt2800usb_write_tx_desc(struct queue_entry *entry,
          * Initialize TXINFO descriptor
          */
         rt2x00_desc_read(txi, 0, &word);
+
+        /*
+         * The size of TXINFO_W0_USB_DMA_TX_PKT_LEN is
+         * TXWI + 802.11 header + L2 pad + payload + pad,
+         * so need to decrease size of TXINFO and USB end pad.
+         */
         rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
-                           entry->skb->len - TXINFO_DESC_SIZE);
+                           entry->skb->len - TXINFO_DESC_SIZE - 4);
         rt2x00_set_field32(&word, TXINFO_W0_WIV,
                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
         rt2x00_set_field32(&word, TXINFO_W0_QSEL, 2);
@@ -285,22 +366,37 @@ static void rt2800usb_write_tx_desc(struct queue_entry *entry,
         skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
 }
 
-/*
- * TX data initialization
- */
-static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
+static void rt2800usb_write_tx_data(struct queue_entry *entry,
+                                        struct txentry_desc *txdesc)
 {
-        int length;
+        unsigned int len;
+        int err;
+
+        rt2800_write_tx_data(entry, txdesc);
 
         /*
-         * The length _must_ include 4 bytes padding,
-         * it should always be multiple of 4,
-         * but it must _not_ be a multiple of the USB packet size.
+         * pad(1~3 bytes) is added after each 802.11 payload.
+         * USB end pad(4 bytes) is added at each USB bulk out packet end.
+         * TX frame format is :
+         * | TXINFO | TXWI | 802.11 header | L2 pad | payload | pad | USB end pad |
+         *                 |<------------- tx_pkt_len ------------->|
          */
-        length = roundup(entry->skb->len + 4, 4);
-        length += (4 * !(length % entry->queue->usb_maxpacket));
+        len = roundup(entry->skb->len, 4) + 4;
+        err = skb_padto(entry->skb, len);
+        if (unlikely(err)) {
+                WARNING(entry->queue->rt2x00dev, "TX SKB padding error, out of memory\n");
+                return;
+        }
 
-        return length;
+        entry->skb->len = len;
+}
+
+/*
+ * TX data initialization
+ */
+static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
+{
+        return entry->skb->len;
 }
 
 /*
@@ -335,14 +431,6 @@ static void rt2800usb_work_txdone(struct work_struct *work)
         }
 }
 
-static void rt2800usb_kill_tx_queue(struct data_queue *queue)
-{
-        if (queue->qid == QID_BEACON)
-                rt2x00usb_register_write(queue->rt2x00dev, BCN_TIME_CFG, 0);
-
-        rt2x00usb_kill_tx_queue(queue);
-}
-
 /*
  * RX control handlers
  */
@@ -507,6 +595,8 @@ static const struct ieee80211_ops rt2800usb_mac80211_ops = {
         .get_tsf                = rt2800_get_tsf,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
         .ampdu_action           = rt2800_ampdu_action,
+        .flush                  = rt2x00mac_flush,
+        .get_survey             = rt2800_get_survey,
 };
 
 static const struct rt2800_ops rt2800usb_rt2800_ops = {
@@ -535,13 +625,15 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
         .link_stats             = rt2800_link_stats,
         .reset_tuner            = rt2800_reset_tuner,
         .link_tuner             = rt2800_link_tuner,
-        .watchdog               = rt2x00usb_watchdog,
+        .watchdog               = rt2800usb_watchdog,
+        .start_queue            = rt2800usb_start_queue,
+        .kick_queue             = rt2x00usb_kick_queue,
+        .stop_queue             = rt2800usb_stop_queue,
+        .flush_queue            = rt2x00usb_flush_queue,
         .write_tx_desc          = rt2800usb_write_tx_desc,
-        .write_tx_data          = rt2800_write_tx_data,
+        .write_tx_data          = rt2800usb_write_tx_data,
         .write_beacon           = rt2800_write_beacon,
         .get_tx_data_len        = rt2800usb_get_tx_data_len,
-        .kick_tx_queue          = rt2x00usb_kick_tx_queue,
-        .kill_tx_queue          = rt2800usb_kill_tx_queue,
         .fill_rxdone            = rt2800usb_fill_rxdone,
         .config_shared_key      = rt2800_config_shared_key,
         .config_pairwise_key    = rt2800_config_pairwise_key,
@@ -553,21 +645,21 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt2800usb_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 128,
         .data_size              = AGGREGATION_SIZE,
         .desc_size              = RXINFO_DESC_SIZE + RXWI_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
 };
 
 static const struct data_queue_desc rt2800usb_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 64,
         .data_size              = AGGREGATION_SIZE,
         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
 };
 
 static const struct data_queue_desc rt2800usb_queue_bcn = {
-        .entry_num              = 8 * BEACON_ENTRIES,
+        .entry_num              = 8,
         .data_size              = MGMT_FRAME_SIZE,
         .desc_size              = TXINFO_DESC_SIZE + TXWI_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
@@ -599,11 +691,19 @@ static struct usb_device_id rt2800usb_device_table[] = {
         /* Abocom */
         { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* AirTies */
+        { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Allwin */
         { USB_DEVICE(0x8516, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x8516, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x8516, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x8516, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x8516, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x8516, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Amit */
         { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Askey */
@@ -612,8 +712,13 @@ static struct usb_device_id rt2800usb_device_table[] = {
         { USB_DEVICE(0x0b05, 0x1731), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0b05, 0x1732), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0b05, 0x1742), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* AzureWave */
         { USB_DEVICE(0x13d3, 0x3247), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x13d3, 0x3307), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x13d3, 0x3321), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Belkin */
         { USB_DEVICE(0x050d, 0x8053), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x050d, 0x805c), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -624,6 +729,7 @@ static struct usb_device_id rt2800usb_device_table[] = {
         { USB_DEVICE(0x14b2, 0x3c06), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x14b2, 0x3c07), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x14b2, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x14b2, 0x3c23), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x14b2, 0x3c25), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x14b2, 0x3c27), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -632,17 +738,36 @@ static struct usb_device_id rt2800usb_device_table[] = {
         { USB_DEVICE(0x07aa, 0x002f), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x07aa, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x07aa, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* D-Link */
         { USB_DEVICE(0x07d1, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x07d1, 0x3c11), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* Draytek */
+        { USB_DEVICE(0x07fa, 0x7712), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Edimax */
+        { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* Encore */
+        { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* EnGenius */
         { USB_DEVICE(0x1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Gigabyte */
         { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Hawking */
         { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -651,6 +776,10 @@ static struct usb_device_id rt2800usb_device_table[] = {
         { USB_DEVICE(0x0e66, 0x0013), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0e66, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0e66, 0x0018), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* I-O DATA */
+        { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Linksys */
         { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -658,17 +787,44 @@ static struct usb_device_id rt2800usb_device_table[] = {
         { USB_DEVICE(0x0789, 0x0162), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0789, 0x0163), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0789, 0x0164), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0789, 0x0166), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Motorola */
         { USB_DEVICE(0x100d, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* MSI */
+        { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0db0, 0x6899), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x822b), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x822c), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x871b), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x871c), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* Para */
+        { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* Pegatron */
+        { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Philips */
         { USB_DEVICE(0x0471, 0x200f), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Planex */
+        { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x2019, 0xed06), USB_DEVICE_DATA(&rt2800usb_ops) },
+        /* Quanta */
+        { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Ralink */
+        { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x148f, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x148f, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Samsung */
         { USB_DEVICE(0x04e8, 0x2018), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Siemens */
@@ -681,13 +837,22 @@ static struct usb_device_id rt2800usb_device_table[] = {
         { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* SMC */
         { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x083a, 0x7512), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x083a, 0x7522), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x083a, 0x8522), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x083a, 0xa618), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x083a, 0xa703), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x083a, 0xb522), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Sparklan */
         { USB_DEVICE(0x15a9, 0x0006), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -701,101 +866,16 @@ static struct usb_device_id rt2800usb_device_table[] = {
         /* Zinwell */
         { USB_DEVICE(0x5a57, 0x0280), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x5a57, 0x0282), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Zyxel */
         { USB_DEVICE(0x0586, 0x3416), USB_DEVICE_DATA(&rt2800usb_ops) },
-#ifdef CONFIG_RT2800USB_RT30XX
-        /* Abocom */
-        { USB_DEVICE(0x07b8, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x07b8, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* AirTies */
-        { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Allwin */
-        { USB_DEVICE(0x8516, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x8516, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x8516, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* ASUS */
-        { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* AzureWave */
-        { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x13d3, 0x3307), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x13d3, 0x3321), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Conceptronic */
-        { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Corega */
-        { USB_DEVICE(0x18c5, 0x0012), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* D-Link */
-        { USB_DEVICE(0x07d1, 0x3c0a), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Draytek */
-        { USB_DEVICE(0x07fa, 0x7712), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Edimax */
-        { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Encore */
-        { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* EnGenius */
-        { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Gigabyte */
-        { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* I-O DATA */
-        { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Logitec */
-        { USB_DEVICE(0x0789, 0x0166), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* MSI */
-        { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x822b), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x822c), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x871b), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x871c), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Para */
-        { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Pegatron */
-        { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Planex */
-        { USB_DEVICE(0x2019, 0xab25), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Quanta */
-        { USB_DEVICE(0x1a32, 0x0304), USB_DEVICE_DATA(&rt2800usb_ops) },
+#ifdef CONFIG_RT2800USB_RT33XX
         /* Ralink */
-        { USB_DEVICE(0x148f, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x148f, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x148f, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x148f, 0x3370), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Sitecom */
-        { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* SMC */
-        { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x083a, 0xa703), USB_DEVICE_DATA(&rt2800usb_ops) },
-        /* Zinwell */
-        { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
+        { USB_DEVICE(0x0df6, 0x0050), USB_DEVICE_DATA(&rt2800usb_ops) },
 #endif
 #ifdef CONFIG_RT2800USB_RT35XX
         /* Allwin */
@@ -809,12 +889,9 @@ static struct usb_device_id rt2800usb_device_table[] = {
         /* I-O DATA */
         { USB_DEVICE(0x04bb, 0x0944), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Ralink */
-        { USB_DEVICE(0x148f, 0x3370), USB_DEVICE_DATA(&rt2800usb_ops) },
         { USB_DEVICE(0x148f, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Sitecom */
         { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) },
-        { USB_DEVICE(0x0df6, 0x0050), USB_DEVICE_DATA(&rt2800usb_ops) },
         /* Zinwell */
         { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) },
 #endif
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
index 0722badccf86..671ea3592610 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.h
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -40,8 +40,8 @@
 /*
  * DMA descriptor defines.
  */
-#define TXINFO_DESC_SIZE                ( 1 * sizeof(__le32) )
-#define RXINFO_DESC_SIZE                ( 1 * sizeof(__le32) )
+#define TXINFO_DESC_SIZE                (1 * sizeof(__le32))
+#define RXINFO_DESC_SIZE                (1 * sizeof(__le32))
 
 /*
  * TX Info structure
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index 94fe589acfaa..84aaf393da43 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -66,7 +66,7 @@
 
 #ifdef CONFIG_RT2X00_DEBUG
 #define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \
-        DEBUG_PRINTK_MSG(__dev, __kernlvl, __lvl, __msg, ##__args);
+        DEBUG_PRINTK_MSG(__dev, __kernlvl, __lvl, __msg, ##__args)
 #else
 #define DEBUG_PRINTK(__dev, __kernlvl, __lvl, __msg, __args...) \
         do { } while (0)
@@ -347,6 +347,10 @@ struct link {
         struct delayed_work watchdog_work;
 };
 
+enum rt2x00_delayed_flags {
+        DELAYED_UPDATE_BEACON,
+};
+
 /*
  * Interface structure
  * Per interface configuration details, this structure
@@ -354,22 +358,6 @@ struct link {
  */
 struct rt2x00_intf {
         /*
-         * All fields within the rt2x00_intf structure
-         * must be protected with a spinlock.
-         */
-        spinlock_t lock;
-
-        /*
-         * MAC of the device.
-         */
-        u8 mac[ETH_ALEN];
-
-        /*
-         * BBSID of the AP to associate with.
-         */
-        u8 bssid[ETH_ALEN];
-
-        /*
          * beacon->skb must be protected with the mutex.
          */
         struct mutex beacon_skb_mutex;
@@ -384,8 +372,7 @@ struct rt2x00_intf {
         /*
          * Actions that needed rescheduling.
          */
-        unsigned int delayed_flags;
-#define DELAYED_UPDATE_BEACON           0x00000001
+        unsigned long delayed_flags;
 
         /*
          * Software sequence counter, this is only required
@@ -567,7 +554,15 @@ struct rt2x00lib_ops {
                              struct link_qual *qual);
         void (*link_tuner) (struct rt2x00_dev *rt2x00dev,
                             struct link_qual *qual, const u32 count);
+
+        /*
+         * Data queue handlers.
+         */
         void (*watchdog) (struct rt2x00_dev *rt2x00dev);
+        void (*start_queue) (struct data_queue *queue);
+        void (*kick_queue) (struct data_queue *queue);
+        void (*stop_queue) (struct data_queue *queue);
+        void (*flush_queue) (struct data_queue *queue);
 
         /*
          * TX control handlers
@@ -579,8 +574,6 @@ struct rt2x00lib_ops {
         void (*write_beacon) (struct queue_entry *entry,
                               struct txentry_desc *txdesc);
         int (*get_tx_data_len) (struct queue_entry *entry);
-        void (*kick_tx_queue) (struct data_queue *queue);
-        void (*kill_tx_queue) (struct data_queue *queue);
 
         /*
          * RX control handlers
@@ -664,6 +657,7 @@ enum rt2x00_flags {
         DRIVER_REQUIRE_COPY_IV,
         DRIVER_REQUIRE_L2PAD,
         DRIVER_REQUIRE_TXSTATUS_FIFO,
+        DRIVER_REQUIRE_TASKLET_CONTEXT,
 
         /*
          * Driver features
@@ -901,7 +895,7 @@ struct rt2x00_dev {
         /*
          * FIFO for storing tx status reports between isr and tasklet.
          */
-        struct kfifo txstatus_fifo;
+        DECLARE_KFIFO_PTR(txstatus_fifo, u32);
 
         /*
          * Tasklet for processing tx status reports (rt2800pci).
@@ -915,7 +909,7 @@ struct rt2x00_dev {
  * in those cases REGISTER_BUSY_COUNT attempts should be
  * taken with a REGISTER_BUSY_DELAY interval.
  */
-#define REGISTER_BUSY_COUNT     5
+#define REGISTER_BUSY_COUNT     100
 #define REGISTER_BUSY_DELAY     100
 
 /*
@@ -1067,6 +1061,78 @@ struct data_queue *rt2x00queue_get_queue(struct rt2x00_dev *rt2x00dev,
 struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
                                           enum queue_index index);
 
+/**
+ * rt2x00queue_pause_queue - Pause a data queue
+ * @queue: Pointer to &struct data_queue.
+ *
+ * This function will pause the data queue locally, preventing
+ * new frames to be added to the queue (while the hardware is
+ * still allowed to run).
+ */
+void rt2x00queue_pause_queue(struct data_queue *queue);
+
+/**
+ * rt2x00queue_unpause_queue - unpause a data queue
+ * @queue: Pointer to &struct data_queue.
+ *
+ * This function will unpause the data queue locally, allowing
+ * new frames to be added to the queue again.
+ */
+void rt2x00queue_unpause_queue(struct data_queue *queue);
+
+/**
+ * rt2x00queue_start_queue - Start a data queue
+ * @queue: Pointer to &struct data_queue.
+ *
+ * This function will start handling all pending frames in the queue.
+ */
+void rt2x00queue_start_queue(struct data_queue *queue);
+
+/**
+ * rt2x00queue_stop_queue - Halt a data queue
+ * @queue: Pointer to &struct data_queue.
+ *
+ * This function will stop all pending frames in the queue.
+ */
+void rt2x00queue_stop_queue(struct data_queue *queue);
+
+/**
+ * rt2x00queue_flush_queue - Flush a data queue
+ * @queue: Pointer to &struct data_queue.
+ * @drop: True to drop all pending frames.
+ *
+ * This function will flush the queue. After this call
+ * the queue is guarenteed to be empty.
+ */
+void rt2x00queue_flush_queue(struct data_queue *queue, bool drop);
+
+/**
+ * rt2x00queue_start_queues - Start all data queues
+ * @rt2x00dev: Pointer to &struct rt2x00_dev.
+ *
+ * This function will loop through all available queues to start them
+ */
+void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev);
+
+/**
+ * rt2x00queue_stop_queues - Halt all data queues
+ * @rt2x00dev: Pointer to &struct rt2x00_dev.
+ *
+ * This function will loop through all available queues to stop
+ * any pending frames.
+ */
+void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev);
+
+/**
+ * rt2x00queue_flush_queues - Flush all data queues
+ * @rt2x00dev: Pointer to &struct rt2x00_dev.
+ * @drop: True to drop all pending frames.
+ *
+ * This function will loop through all available queues to flush
+ * any pending frames.
+ */
+void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop);
+
 /*
  * Debugfs handlers.
  */
@@ -1092,6 +1158,7 @@ static inline void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
  */
 void rt2x00lib_beacondone(struct rt2x00_dev *rt2x00dev);
 void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev);
+void rt2x00lib_dmastart(struct queue_entry *entry);
 void rt2x00lib_dmadone(struct queue_entry *entry);
 void rt2x00lib_txdone(struct queue_entry *entry,
                       struct txdone_entry_desc *txdesc);
@@ -1133,6 +1200,7 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
 int rt2x00mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
                       const struct ieee80211_tx_queue_params *params);
 void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw);
+void rt2x00mac_flush(struct ieee80211_hw *hw, bool drop);
 
 /*
  * Driver allocation handlers.
diff --git a/drivers/net/wireless/rt2x00/rt2x00config.c b/drivers/net/wireless/rt2x00/rt2x00config.c
index 54ffb5aeb34e..e7f67d5eda52 100644
--- a/drivers/net/wireless/rt2x00/rt2x00config.c
+++ b/drivers/net/wireless/rt2x00/rt2x00config.c
@@ -62,13 +62,13 @@ void rt2x00lib_config_intf(struct rt2x00_dev *rt2x00dev,
          * This will prevent the device being confused when it wants
          * to ACK frames or consideres itself associated.
          */
-        memset(&conf.mac, 0, sizeof(conf.mac));
+        memset(conf.mac, 0, sizeof(conf.mac));
         if (mac)
-                memcpy(&conf.mac, mac, ETH_ALEN);
+                memcpy(conf.mac, mac, ETH_ALEN);
 
-        memset(&conf.bssid, 0, sizeof(conf.bssid));
+        memset(conf.bssid, 0, sizeof(conf.bssid));
         if (bssid)
-                memcpy(&conf.bssid, bssid, ETH_ALEN);
+                memcpy(conf.bssid, bssid, ETH_ALEN);
 
         flags |= CONFIG_UPDATE_TYPE;
         if (mac || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count))
@@ -133,7 +133,7 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
          */
         if (!(ant->flags & ANTENNA_RX_DIVERSITY))
                 config.rx = rt2x00lib_config_antenna_check(config.rx, def->rx);
-        else if(config.rx == ANTENNA_SW_DIVERSITY)
+        else if (config.rx == ANTENNA_SW_DIVERSITY)
                 config.rx = active->rx;
 
         if (!(ant->flags & ANTENNA_TX_DIVERSITY))
@@ -146,7 +146,7 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
          * else the changes will be ignored by the device.
          */
         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
-                rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF_LINK);
+                rt2x00queue_stop_queue(rt2x00dev->rx);
 
         /*
          * Write new antenna setup to device and reset the link tuner.
@@ -160,7 +160,7 @@ void rt2x00lib_config_antenna(struct rt2x00_dev *rt2x00dev,
         memcpy(active, &config, sizeof(config));
 
         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
-                rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON_LINK);
+                rt2x00queue_start_queue(rt2x00dev->rx);
 }
 
 void rt2x00lib_config(struct rt2x00_dev *rt2x00dev,
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c
index fcdb6b0dc40f..c92db3264741 100644
--- a/drivers/net/wireless/rt2x00/rt2x00debug.c
+++ b/drivers/net/wireless/rt2x00/rt2x00debug.c
@@ -162,11 +162,11 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
         struct timeval timestamp;
         u32 data_len;
 
-        do_gettimeofday(&timestamp);
-
-        if (!test_bit(FRAME_DUMP_FILE_OPEN, &intf->frame_dump_flags))
+        if (likely(!test_bit(FRAME_DUMP_FILE_OPEN, &intf->frame_dump_flags)))
                 return;
 
+        do_gettimeofday(&timestamp);
+
         if (skb_queue_len(&intf->frame_dump_skbqueue) > 20) {
                 DEBUG(rt2x00dev, "txrx dump queue length exceeded.\n");
                 return;
@@ -339,18 +339,19 @@ static ssize_t rt2x00debug_read_queue_stats(struct file *file,
                 return -ENOMEM;
 
         temp = data +
-            sprintf(data, "qid\tcount\tlimit\tlength\tindex\tdma done\tdone\n");
+            sprintf(data, "qid\tflags\t\tcount\tlimit\tlength\tindex\tdma done\tdone\n");
 
         queue_for_each(intf->rt2x00dev, queue) {
-                spin_lock_irqsave(&queue->lock, irqflags);
+                spin_lock_irqsave(&queue->index_lock, irqflags);
 
-                temp += sprintf(temp, "%d\t%d\t%d\t%d\t%d\t%d\t%d\n", queue->qid,
+                temp += sprintf(temp, "%d\t0x%.8x\t%d\t%d\t%d\t%d\t%d\t\t%d\n",
+                                queue->qid, (unsigned int)queue->flags,
                                 queue->count, queue->limit, queue->length,
                                 queue->index[Q_INDEX],
                                 queue->index[Q_INDEX_DMA_DONE],
                                 queue->index[Q_INDEX_DONE]);
 
-                spin_unlock_irqrestore(&queue->lock, irqflags);
+                spin_unlock_irqrestore(&queue->index_lock, irqflags);
         }
 
         size = strlen(data);
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index 5ba79b935f09..9597a03242cc 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -66,20 +66,16 @@ int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev)
         set_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags);
 
         /*
-         * Enable RX.
+         * Enable queues.
          */
-        rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
+        rt2x00queue_start_queues(rt2x00dev);
+        rt2x00link_start_tuner(rt2x00dev);
 
         /*
          * Start watchdog monitoring.
          */
         rt2x00link_start_watchdog(rt2x00dev);
 
-        /*
-         * Start the TX queues.
-         */
-        ieee80211_wake_queues(rt2x00dev->hw);
-
         return 0;
 }
 
@@ -89,20 +85,16 @@ void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev)
                 return;
 
         /*
-         * Stop the TX queues in mac80211.
-         */
-        ieee80211_stop_queues(rt2x00dev->hw);
-        rt2x00queue_stop_queues(rt2x00dev);
-
-        /*
          * Stop watchdog monitoring.
          */
         rt2x00link_stop_watchdog(rt2x00dev);
 
         /*
-         * Disable RX.
+         * Stop all queues
          */
-        rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
+        rt2x00link_stop_tuner(rt2x00dev);
+        rt2x00queue_stop_queues(rt2x00dev);
+        rt2x00queue_flush_queues(rt2x00dev, true);
 
         /*
          * Disable radio.
@@ -113,41 +105,11 @@ void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev)
         rt2x00leds_led_radio(rt2x00dev, false);
 }
 
-void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state)
-{
-        /*
-         * When we are disabling the RX, we should also stop the link tuner.
-         */
-        if (state == STATE_RADIO_RX_OFF)
-                rt2x00link_stop_tuner(rt2x00dev);
-
-        rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
-
-        /*
-         * When we are enabling the RX, we should also start the link tuner.
-         */
-        if (state == STATE_RADIO_RX_ON)
-                rt2x00link_start_tuner(rt2x00dev);
-}
-
 static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
                                           struct ieee80211_vif *vif)
 {
         struct rt2x00_dev *rt2x00dev = data;
         struct rt2x00_intf *intf = vif_to_intf(vif);
-        int delayed_flags;
-
-        /*
-         * Copy all data we need during this action under the protection
-         * of a spinlock. Otherwise race conditions might occur which results
-         * into an invalid configuration.
-         */
-        spin_lock(&intf->lock);
-
-        delayed_flags = intf->delayed_flags;
-        intf->delayed_flags = 0;
-
-        spin_unlock(&intf->lock);
 
         /*
          * It is possible the radio was disabled while the work had been
@@ -158,7 +120,7 @@ static void rt2x00lib_intf_scheduled_iter(void *data, u8 *mac,
         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
                 return;
 
-        if (delayed_flags & DELAYED_UPDATE_BEACON)
+        if (test_and_clear_bit(DELAYED_UPDATE_BEACON, &intf->delayed_flags))
                 rt2x00queue_update_beacon(rt2x00dev, vif, true);
 }
 
@@ -251,8 +213,16 @@ void rt2x00lib_pretbtt(struct rt2x00_dev *rt2x00dev)
 }
 EXPORT_SYMBOL_GPL(rt2x00lib_pretbtt);
 
+void rt2x00lib_dmastart(struct queue_entry *entry)
+{
+        set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
+        rt2x00queue_index_inc(entry->queue, Q_INDEX);
+}
+EXPORT_SYMBOL_GPL(rt2x00lib_dmastart);
+
 void rt2x00lib_dmadone(struct queue_entry *entry)
 {
+        set_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags);
         clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
         rt2x00queue_index_inc(entry->queue, Q_INDEX_DMA_DONE);
 }
@@ -264,11 +234,9 @@ void rt2x00lib_txdone(struct queue_entry *entry,
         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
-        enum data_queue_qid qid = skb_get_queue_mapping(entry->skb);
-        unsigned int header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
+        unsigned int header_length, i;
         u8 rate_idx, rate_flags, retry_rates;
         u8 skbdesc_flags = skbdesc->flags;
-        unsigned int i;
         bool success;
 
         /*
@@ -287,6 +255,11 @@ void rt2x00lib_txdone(struct queue_entry *entry,
         skbdesc->flags &= ~SKBDESC_DESC_IN_SKB;
 
         /*
+         * Determine the length of 802.11 header.
+         */
+        header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
+
+        /*
          * Remove L2 padding which was added during
          */
         if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags))
@@ -390,9 +363,12 @@ void rt2x00lib_txdone(struct queue_entry *entry,
          * through a mac80211 library call (RTS/CTS) then we should not
          * send the status report back.
          */
-        if (!(skbdesc_flags & SKBDESC_NOT_MAC80211))
-                ieee80211_tx_status(rt2x00dev->hw, entry->skb);
-        else
+        if (!(skbdesc_flags & SKBDESC_NOT_MAC80211)) {
+                if (test_bit(DRIVER_REQUIRE_TASKLET_CONTEXT, &rt2x00dev->flags))
+                        ieee80211_tx_status(rt2x00dev->hw, entry->skb);
+                else
+                        ieee80211_tx_status_ni(rt2x00dev->hw, entry->skb);
+        } else
                 dev_kfree_skb_any(entry->skb);
 
         /*
@@ -411,7 +387,7 @@ void rt2x00lib_txdone(struct queue_entry *entry,
          * is reenabled when the txdone handler has finished.
          */
         if (!rt2x00queue_threshold(entry->queue))
-                ieee80211_wake_queue(rt2x00dev->hw, qid);
+                rt2x00queue_unpause_queue(entry->queue);
 }
 EXPORT_SYMBOL_GPL(rt2x00lib_txdone);
 
@@ -483,6 +459,10 @@ void rt2x00lib_rxdone(struct queue_entry *entry)
         unsigned int header_length;
         int rate_idx;
 
+        if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) ||
+            !test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
+                goto submit_entry;
+
         if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
                 goto submit_entry;
 
@@ -567,9 +547,11 @@ void rt2x00lib_rxdone(struct queue_entry *entry)
         entry->skb = skb;
 
 submit_entry:
-        rt2x00dev->ops->lib->clear_entry(entry);
-        rt2x00queue_index_inc(entry->queue, Q_INDEX);
+        entry->flags = 0;
         rt2x00queue_index_inc(entry->queue, Q_INDEX_DONE);
+        if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
+            test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
+                rt2x00dev->ops->lib->clear_entry(entry);
 }
 EXPORT_SYMBOL_GPL(rt2x00lib_rxdone);
 
@@ -678,7 +660,7 @@ static void rt2x00lib_rate(struct ieee80211_rate *entry,
 {
         entry->flags = 0;
         entry->bitrate = rate->bitrate;
-        entry->hw_value =index;
+        entry->hw_value = index;
         entry->hw_value_short = index;
 
         if (rate->flags & DEV_RATE_SHORT_PREAMBLE)
@@ -818,8 +800,7 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
         /*
          * Allocate tx status FIFO for driver use.
          */
-        if (test_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags) &&
-            rt2x00dev->ops->lib->txstatus_tasklet) {
+        if (test_bit(DRIVER_REQUIRE_TXSTATUS_FIFO, &rt2x00dev->flags)) {
                 /*
                  * Allocate txstatus fifo and tasklet, we use a size of 512
                  * for the kfifo which is big enough to store 512/4=128 tx
@@ -833,9 +814,10 @@ static int rt2x00lib_probe_hw(struct rt2x00_dev *rt2x00dev)
                         return status;
 
                 /* tasklet for processing the tx status reports. */
-                tasklet_init(&rt2x00dev->txstatus_tasklet,
-                             rt2x00dev->ops->lib->txstatus_tasklet,
-                             (unsigned long)rt2x00dev);
+                if (rt2x00dev->ops->lib->txstatus_tasklet)
+                        tasklet_init(&rt2x00dev->txstatus_tasklet,
+                                     rt2x00dev->ops->lib->txstatus_tasklet,
+                                     (unsigned long)rt2x00dev);
 
         }
 
diff --git a/drivers/net/wireless/rt2x00/rt2x00ht.c b/drivers/net/wireless/rt2x00/rt2x00ht.c
index c637bcaec5f8..b7ad46ecaa1d 100644
--- a/drivers/net/wireless/rt2x00/rt2x00ht.c
+++ b/drivers/net/wireless/rt2x00/rt2x00ht.c
@@ -40,8 +40,6 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
         if (tx_info->control.sta)
                 txdesc->mpdu_density =
                     tx_info->control.sta->ht_cap.ampdu_density;
-        else
-                txdesc->mpdu_density = 0;
 
         txdesc->ba_size = 7;    /* FIXME: What value is needed? */
 
diff --git a/drivers/net/wireless/rt2x00/rt2x00lib.h b/drivers/net/wireless/rt2x00/rt2x00lib.h
index 619da23b7b56..a105c500627b 100644
--- a/drivers/net/wireless/rt2x00/rt2x00lib.h
+++ b/drivers/net/wireless/rt2x00/rt2x00lib.h
@@ -57,7 +57,7 @@ static inline const struct rt2x00_rate *rt2x00_get_rate(const u16 hw_value)
 }
 
 #define RATE_MCS(__mode, __mcs) \
-        ( (((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff) )
+        ((((__mode) & 0x00ff) << 8) | ((__mcs) & 0x00ff))
 
 static inline int rt2x00_get_rate_mcs(const u16 mcs_value)
 {
@@ -69,7 +69,6 @@ static inline int rt2x00_get_rate_mcs(const u16 mcs_value)
  */
 int rt2x00lib_enable_radio(struct rt2x00_dev *rt2x00dev);
 void rt2x00lib_disable_radio(struct rt2x00_dev *rt2x00dev);
-void rt2x00lib_toggle_rx(struct rt2x00_dev *rt2x00dev, enum dev_state state);
 
 /*
  * Initialization handlers.
@@ -179,15 +178,6 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
 void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index);
 
 /**
- * rt2x00queue_stop_queues - Halt all data queues
- * @rt2x00dev: Pointer to &struct rt2x00_dev.
- *
- * This function will loop through all available queues to stop
- * any pending outgoing frames.
- */
-void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev);
-
-/**
  * rt2x00queue_init_queues - Initialize all data queues
  * @rt2x00dev: Pointer to &struct rt2x00_dev.
  *
diff --git a/drivers/net/wireless/rt2x00/rt2x00link.c b/drivers/net/wireless/rt2x00/rt2x00link.c
index b971d8798ebf..bfda60eaf4ef 100644
--- a/drivers/net/wireless/rt2x00/rt2x00link.c
+++ b/drivers/net/wireless/rt2x00/rt2x00link.c
@@ -67,7 +67,7 @@
             (__avg).avg_weight  ? \
                 ((((__avg).avg_weight * ((AVG_SAMPLES) - 1)) + \
                   ((__val) * (AVG_FACTOR))) / \
-                 (AVG_SAMPLES) ) : \
+                 (AVG_SAMPLES)) : \
                 ((__val) * (AVG_FACTOR)); \
         __new.avg = __new.avg_weight / (AVG_FACTOR); \
         __new; \
diff --git a/drivers/net/wireless/rt2x00/rt2x00mac.c b/drivers/net/wireless/rt2x00/rt2x00mac.c
index a7d3f4c3ee0d..f3da051df39e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00mac.c
+++ b/drivers/net/wireless/rt2x00/rt2x00mac.c
@@ -104,7 +104,7 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         struct rt2x00_dev *rt2x00dev = hw->priv;
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
         enum data_queue_qid qid = skb_get_queue_mapping(skb);
-        struct data_queue *queue;
+        struct data_queue *queue = NULL;
 
         /*
          * Mac80211 might be calling this function while we are trying
@@ -153,7 +153,7 @@ int rt2x00mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
                 goto exit_fail;
 
         if (rt2x00queue_threshold(queue))
-                ieee80211_stop_queue(rt2x00dev->hw, qid);
+                rt2x00queue_pause_queue(queue);
 
         return NETDEV_TX_OK;
 
@@ -268,7 +268,6 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
         else
                 rt2x00dev->intf_sta_count++;
 
-        spin_lock_init(&intf->lock);
         spin_lock_init(&intf->seqlock);
         mutex_init(&intf->beacon_skb_mutex);
         intf->beacon = entry;
@@ -282,15 +281,8 @@ int rt2x00mac_add_interface(struct ieee80211_hw *hw,
          * STA interfaces at this time, since this can cause
          * invalid behavior in the device.
          */
-        memcpy(&intf->mac, vif->addr, ETH_ALEN);
-        if (vif->type == NL80211_IFTYPE_AP) {
-                memcpy(&intf->bssid, vif->addr, ETH_ALEN);
-                rt2x00lib_config_intf(rt2x00dev, intf, vif->type,
-                                      intf->mac, intf->bssid);
-        } else {
-                rt2x00lib_config_intf(rt2x00dev, intf, vif->type,
-                                      intf->mac, NULL);
-        }
+        rt2x00lib_config_intf(rt2x00dev, intf, vif->type,
+                              vif->addr, NULL);
 
         /*
          * Some filters depend on the current working mode. We can force
@@ -358,7 +350,7 @@ int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed)
          * if for any reason the link tuner must be reset, this will be
          * handled by rt2x00lib_config().
          */
-        rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF_LINK);
+        rt2x00queue_stop_queue(rt2x00dev->rx);
 
         /*
          * When we've just turned on the radio, we want to reprogram
@@ -376,7 +368,7 @@ int rt2x00mac_config(struct ieee80211_hw *hw, u32 changed)
         rt2x00lib_config_antenna(rt2x00dev, rt2x00dev->default_ant);
 
         /* Turn RX back on */
-        rt2x00lib_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON_LINK);
+        rt2x00queue_start_queue(rt2x00dev->rx);
 
         return 0;
 }
@@ -451,9 +443,7 @@ static void rt2x00mac_set_tim_iter(void *data, u8 *mac,
             vif->type != NL80211_IFTYPE_WDS)
                 return;
 
-        spin_lock(&intf->lock);
-        intf->delayed_flags |= DELAYED_UPDATE_BEACON;
-        spin_unlock(&intf->lock);
+        set_bit(DELAYED_UPDATE_BEACON, &intf->delayed_flags);
 }
 
 int rt2x00mac_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
@@ -478,17 +468,17 @@ EXPORT_SYMBOL_GPL(rt2x00mac_set_tim);
 static void memcpy_tkip(struct rt2x00lib_crypto *crypto, u8 *key, u8 key_len)
 {
         if (key_len > NL80211_TKIP_DATA_OFFSET_ENCR_KEY)
-                memcpy(&crypto->key,
+                memcpy(crypto->key,
                        &key[NL80211_TKIP_DATA_OFFSET_ENCR_KEY],
                        sizeof(crypto->key));
 
         if (key_len > NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY)
-                memcpy(&crypto->tx_mic,
+                memcpy(crypto->tx_mic,
                        &key[NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY],
                        sizeof(crypto->tx_mic));
 
         if (key_len > NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY)
-                memcpy(&crypto->rx_mic,
+                memcpy(crypto->rx_mic,
                        &key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY],
                        sizeof(crypto->rx_mic));
 }
@@ -498,7 +488,6 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
                       struct ieee80211_key_conf *key)
 {
         struct rt2x00_dev *rt2x00dev = hw->priv;
-        struct rt2x00_intf *intf = vif_to_intf(vif);
         int (*set_key) (struct rt2x00_dev *rt2x00dev,
                         struct rt2x00lib_crypto *crypto,
                         struct ieee80211_key_conf *key);
@@ -522,7 +511,7 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
         if (rt2x00dev->intf_sta_count)
                 crypto.bssidx = 0;
         else
-                crypto.bssidx = intf->mac[5] & (rt2x00dev->ops->max_ap_intf - 1);
+                crypto.bssidx = vif->addr[5] & (rt2x00dev->ops->max_ap_intf - 1);
 
         crypto.cipher = rt2x00crypto_key_to_cipher(key);
         if (crypto.cipher == CIPHER_NONE)
@@ -540,7 +529,7 @@ int rt2x00mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
         if (crypto.cipher == CIPHER_TKIP)
                 memcpy_tkip(&crypto, &key->key[0], key->keylen);
         else
-                memcpy(&crypto.key, &key->key[0], key->keylen);
+                memcpy(crypto.key, &key->key[0], key->keylen);
         /*
          * Each BSS has a maximum of 4 shared keys.
          * Shared key index values:
@@ -620,22 +609,8 @@ void rt2x00mac_bss_info_changed(struct ieee80211_hw *hw,
         if (!test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags))
                 return;
 
-        spin_lock(&intf->lock);
-
         /*
-         * conf->bssid can be NULL if coming from the internal
-         * beacon update routine.
-         */
-        if (changes & BSS_CHANGED_BSSID)
-                memcpy(&intf->bssid, bss_conf->bssid, ETH_ALEN);
-
-        spin_unlock(&intf->lock);
-
-        /*
-         * Call rt2x00_config_intf() outside of the spinlock context since
-         * the call will sleep for USB drivers. By using the ieee80211_if_conf
-         * values as arguments we make keep access to rt2x00_intf thread safe
-         * even without the lock.
+         * Update the BSSID.
          */
         if (changes & BSS_CHANGED_BSSID)
                 rt2x00lib_config_intf(rt2x00dev, intf, vif->type, NULL,
@@ -719,3 +694,13 @@ void rt2x00mac_rfkill_poll(struct ieee80211_hw *hw)
         wiphy_rfkill_set_hw_state(hw->wiphy, !active);
 }
 EXPORT_SYMBOL_GPL(rt2x00mac_rfkill_poll);
+
+void rt2x00mac_flush(struct ieee80211_hw *hw, bool drop)
+{
+        struct rt2x00_dev *rt2x00dev = hw->priv;
+        struct data_queue *queue;
+
+        tx_queue_for_each(rt2x00dev, queue)
+                rt2x00queue_flush_queue(queue, drop);
+}
+EXPORT_SYMBOL_GPL(rt2x00mac_flush);
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index 2449d785cf8d..73631c6fbb30 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -82,6 +82,13 @@ void rt2x00pci_rxdone(struct rt2x00_dev *rt2x00dev)
                 skbdesc->desc_len = entry->queue->desc_size;
 
                 /*
+                 * DMA is already done, notify rt2x00lib that
+                 * it finished successfully.
+                 */
+                rt2x00lib_dmastart(entry);
+                rt2x00lib_dmadone(entry);
+
+                /*
                  * Send the frame to rt2x00lib for further processing.
                  */
                 rt2x00lib_rxdone(entry);
@@ -105,7 +112,7 @@ static int rt2x00pci_alloc_queue_dma(struct rt2x00_dev *rt2x00dev,
          */
         addr = dma_alloc_coherent(rt2x00dev->dev,
                                   queue->limit * queue->desc_size,
-                                  &dma, GFP_KERNEL | GFP_DMA);
+                                  &dma, GFP_KERNEL);
         if (!addr)
                 return -ENOMEM;
 
@@ -279,7 +286,7 @@ int rt2x00pci_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
         rt2x00dev->irq = pci_dev->irq;
         rt2x00dev->name = pci_name(pci_dev);
 
-        if (pci_dev->is_pcie)
+        if (pci_is_pcie(pci_dev))
                 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCIE);
         else
                 rt2x00_set_chip_intf(rt2x00dev, RT2X00_CHIP_INTF_PCI);
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index b854d62ff99b..746ce8fe8cf4 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -64,7 +64,7 @@ static inline void rt2x00pci_register_multiwrite(struct rt2x00_dev *rt2x00dev,
                                                  const void *value,
                                                  const u32 length)
 {
-        memcpy_toio(rt2x00dev->csr.base + offset, value, length);
+        __iowrite32_copy(rt2x00dev->csr.base + offset, value, length >> 2);
 }
 
 /**
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index e360d287defb..ca82b3a91697 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -199,7 +199,12 @@ void rt2x00queue_insert_l2pad(struct sk_buff *skb, unsigned int header_length)
 
 void rt2x00queue_remove_l2pad(struct sk_buff *skb, unsigned int header_length)
 {
-        unsigned int l2pad = L2PAD_SIZE(header_length);
+        /*
+         * L2 padding is only present if the skb contains more than just the
+         * IEEE 802.11 header.
+         */
+        unsigned int l2pad = (skb->len > header_length) ?
+                                L2PAD_SIZE(header_length) : 0;
 
         if (!l2pad)
                 return;
@@ -311,14 +316,6 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
         memset(txdesc, 0, sizeof(*txdesc));
 
         /*
-         * Initialize information from queue
-         */
-        txdesc->qid = entry->queue->qid;
-        txdesc->cw_min = entry->queue->cw_min;
-        txdesc->cw_max = entry->queue->cw_max;
-        txdesc->aifs = entry->queue->aifs;
-
-        /*
          * Header and frame information.
          */
         txdesc->length = entry->skb->len;
@@ -460,12 +457,9 @@ static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
         rt2x00debug_dump_frame(queue->rt2x00dev, DUMP_FRAME_TX, entry->skb);
 }
 
-static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
+static void rt2x00queue_kick_tx_queue(struct data_queue *queue,
                                       struct txentry_desc *txdesc)
 {
-        struct data_queue *queue = entry->queue;
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-
         /*
          * Check if we need to kick the queue, there are however a few rules
          *      1) Don't kick unless this is the last in frame in a burst.
@@ -477,7 +471,7 @@ static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
          */
         if (rt2x00queue_threshold(queue) ||
             !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
-                rt2x00dev->ops->lib->kick_tx_queue(queue);
+                queue->rt2x00dev->ops->lib->kick_queue(queue);
 }
 
 int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
@@ -567,7 +561,7 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
 
         rt2x00queue_index_inc(queue, Q_INDEX);
         rt2x00queue_write_tx_descriptor(entry, &txdesc);
-        rt2x00queue_kick_tx_queue(entry, &txdesc);
+        rt2x00queue_kick_tx_queue(queue, &txdesc);
 
         return 0;
 }
@@ -591,7 +585,7 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
         rt2x00queue_free_skb(intf->beacon);
 
         if (!enable_beacon) {
-                rt2x00dev->ops->lib->kill_tx_queue(intf->beacon->queue);
+                rt2x00queue_stop_queue(intf->beacon->queue);
                 mutex_unlock(&intf->beacon_skb_mutex);
                 return 0;
         }
@@ -649,10 +643,10 @@ void rt2x00queue_for_each_entry(struct data_queue *queue,
          * it should not be kicked during this run, since it
          * is part of another TX operation.
          */
-        spin_lock_irqsave(&queue->lock, irqflags);
+        spin_lock_irqsave(&queue->index_lock, irqflags);
         index_start = queue->index[start];
         index_end = queue->index[end];
-        spin_unlock_irqrestore(&queue->lock, irqflags);
+        spin_unlock_irqrestore(&queue->index_lock, irqflags);
 
         /*
          * Start from the TX done pointer, this guarentees that we will
@@ -706,11 +700,11 @@ struct queue_entry *rt2x00queue_get_entry(struct data_queue *queue,
                 return NULL;
         }
 
-        spin_lock_irqsave(&queue->lock, irqflags);
+        spin_lock_irqsave(&queue->index_lock, irqflags);
 
         entry = &queue->entries[queue->index[index]];
 
-        spin_unlock_irqrestore(&queue->lock, irqflags);
+        spin_unlock_irqrestore(&queue->index_lock, irqflags);
 
         return entry;
 }
@@ -726,7 +720,7 @@ void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
                 return;
         }
 
-        spin_lock_irqsave(&queue->lock, irqflags);
+        spin_lock_irqsave(&queue->index_lock, irqflags);
 
         queue->index[index]++;
         if (queue->index[index] >= queue->limit)
@@ -741,15 +735,219 @@ void rt2x00queue_index_inc(struct data_queue *queue, enum queue_index index)
                 queue->count++;
         }
 
-        spin_unlock_irqrestore(&queue->lock, irqflags);
+        spin_unlock_irqrestore(&queue->index_lock, irqflags);
 }
 
+void rt2x00queue_pause_queue(struct data_queue *queue)
+{
+        if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
+            !test_bit(QUEUE_STARTED, &queue->flags) ||
+            test_and_set_bit(QUEUE_PAUSED, &queue->flags))
+                return;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_AC_BE:
+        case QID_AC_BK:
+                /*
+                 * For TX queues, we have to disable the queue
+                 * inside mac80211.
+                 */
+                ieee80211_stop_queue(queue->rt2x00dev->hw, queue->qid);
+                break;
+        default:
+                break;
+        }
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_pause_queue);
+
+void rt2x00queue_unpause_queue(struct data_queue *queue)
+{
+        if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
+            !test_bit(QUEUE_STARTED, &queue->flags) ||
+            !test_and_clear_bit(QUEUE_PAUSED, &queue->flags))
+                return;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_AC_BE:
+        case QID_AC_BK:
+                /*
+                 * For TX queues, we have to enable the queue
+                 * inside mac80211.
+                 */
+                ieee80211_wake_queue(queue->rt2x00dev->hw, queue->qid);
+                break;
+        case QID_RX:
+                /*
+                 * For RX we need to kick the queue now in order to
+                 * receive frames.
+                 */
+                queue->rt2x00dev->ops->lib->kick_queue(queue);
+        default:
+                break;
+        }
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_unpause_queue);
+
+void rt2x00queue_start_queue(struct data_queue *queue)
+{
+        mutex_lock(&queue->status_lock);
+
+        if (!test_bit(DEVICE_STATE_PRESENT, &queue->rt2x00dev->flags) ||
+            test_and_set_bit(QUEUE_STARTED, &queue->flags)) {
+                mutex_unlock(&queue->status_lock);
+                return;
+        }
+
+        set_bit(QUEUE_PAUSED, &queue->flags);
+
+        queue->rt2x00dev->ops->lib->start_queue(queue);
+
+        rt2x00queue_unpause_queue(queue);
+
+        mutex_unlock(&queue->status_lock);
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_start_queue);
+
+void rt2x00queue_stop_queue(struct data_queue *queue)
+{
+        mutex_lock(&queue->status_lock);
+
+        if (!test_and_clear_bit(QUEUE_STARTED, &queue->flags)) {
+                mutex_unlock(&queue->status_lock);
+                return;
+        }
+
+        rt2x00queue_pause_queue(queue);
+
+        queue->rt2x00dev->ops->lib->stop_queue(queue);
+
+        mutex_unlock(&queue->status_lock);
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_stop_queue);
+
+void rt2x00queue_flush_queue(struct data_queue *queue, bool drop)
+{
+        unsigned int i;
+        bool started;
+        bool tx_queue =
+                (queue->qid == QID_AC_VO) ||
+                (queue->qid == QID_AC_VI) ||
+                (queue->qid == QID_AC_BE) ||
+                (queue->qid == QID_AC_BK);
+
+        mutex_lock(&queue->status_lock);
+
+        /*
+         * If the queue has been started, we must stop it temporarily
+         * to prevent any new frames to be queued on the device. If
+         * we are not dropping the pending frames, the queue must
+         * only be stopped in the software and not the hardware,
+         * otherwise the queue will never become empty on its own.
+         */
+        started = test_bit(QUEUE_STARTED, &queue->flags);
+        if (started) {
+                /*
+                 * Pause the queue
+                 */
+                rt2x00queue_pause_queue(queue);
+
+                /*
+                 * If we are not supposed to drop any pending
+                 * frames, this means we must force a start (=kick)
+                 * to the queue to make sure the hardware will
+                 * start transmitting.
+                 */
+                if (!drop && tx_queue)
+                        queue->rt2x00dev->ops->lib->kick_queue(queue);
+        }
+
+        /*
+         * Check if driver supports flushing, we can only guarentee
+         * full support for flushing if the driver is able
+         * to cancel all pending frames (drop = true).
+         */
+        if (drop && queue->rt2x00dev->ops->lib->flush_queue)
+                queue->rt2x00dev->ops->lib->flush_queue(queue);
+
+        /*
+         * When we don't want to drop any frames, or when
+         * the driver doesn't fully flush the queue correcly,
+         * we must wait for the queue to become empty.
+         */
+        for (i = 0; !rt2x00queue_empty(queue) && i < 100; i++)
+                msleep(10);
+
+        /*
+         * The queue flush has failed...
+         */
+        if (unlikely(!rt2x00queue_empty(queue)))
+                WARNING(queue->rt2x00dev, "Queue %d failed to flush", queue->qid);
+
+        /*
+         * Restore the queue to the previous status
+         */
+        if (started)
+                rt2x00queue_unpause_queue(queue);
+
+        mutex_unlock(&queue->status_lock);
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_flush_queue);
+
+void rt2x00queue_start_queues(struct rt2x00_dev *rt2x00dev)
+{
+        struct data_queue *queue;
+
+        /*
+         * rt2x00queue_start_queue will call ieee80211_wake_queue
+         * for each queue after is has been properly initialized.
+         */
+        tx_queue_for_each(rt2x00dev, queue)
+                rt2x00queue_start_queue(queue);
+
+        rt2x00queue_start_queue(rt2x00dev->rx);
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_start_queues);
+
+void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
+{
+        struct data_queue *queue;
+
+        /*
+         * rt2x00queue_stop_queue will call ieee80211_stop_queue
+         * as well, but we are completely shutting doing everything
+         * now, so it is much safer to stop all TX queues at once,
+         * and use rt2x00queue_stop_queue for cleaning up.
+         */
+        ieee80211_stop_queues(rt2x00dev->hw);
+
+        tx_queue_for_each(rt2x00dev, queue)
+                rt2x00queue_stop_queue(queue);
+
+        rt2x00queue_stop_queue(rt2x00dev->rx);
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_stop_queues);
+
+void rt2x00queue_flush_queues(struct rt2x00_dev *rt2x00dev, bool drop)
+{
+        struct data_queue *queue;
+
+        tx_queue_for_each(rt2x00dev, queue)
+                rt2x00queue_flush_queue(queue, drop);
+
+        rt2x00queue_flush_queue(rt2x00dev->rx, drop);
+}
+EXPORT_SYMBOL_GPL(rt2x00queue_flush_queues);
+
 static void rt2x00queue_reset(struct data_queue *queue)
 {
         unsigned long irqflags;
         unsigned int i;
 
-        spin_lock_irqsave(&queue->lock, irqflags);
+        spin_lock_irqsave(&queue->index_lock, irqflags);
 
         queue->count = 0;
         queue->length = 0;
@@ -759,15 +957,7 @@ static void rt2x00queue_reset(struct data_queue *queue)
                 queue->last_action[i] = jiffies;
         }
 
-        spin_unlock_irqrestore(&queue->lock, irqflags);
-}
-
-void rt2x00queue_stop_queues(struct rt2x00_dev *rt2x00dev)
-{
-        struct data_queue *queue;
-
-        txall_queue_for_each(rt2x00dev, queue)
-                rt2x00dev->ops->lib->kill_tx_queue(queue);
+        spin_unlock_irqrestore(&queue->index_lock, irqflags);
 }
 
 void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
@@ -778,11 +968,8 @@ void rt2x00queue_init_queues(struct rt2x00_dev *rt2x00dev)
         queue_for_each(rt2x00dev, queue) {
                 rt2x00queue_reset(queue);
 
-                for (i = 0; i < queue->limit; i++) {
+                for (i = 0; i < queue->limit; i++)
                         rt2x00dev->ops->lib->clear_entry(&queue->entries[i]);
-                        if (queue->qid == QID_RX)
-                                rt2x00queue_index_inc(queue, Q_INDEX);
-                }
         }
 }
 
@@ -809,8 +996,8 @@ static int rt2x00queue_alloc_entries(struct data_queue *queue,
                 return -ENOMEM;
 
 #define QUEUE_ENTRY_PRIV_OFFSET(__base, __index, __limit, __esize, __psize) \
-        ( ((char *)(__base)) + ((__limit) * (__esize)) + \
-            ((__index) * (__psize)) )
+        (((char *)(__base)) + ((__limit) * (__esize)) + \
+            ((__index) * (__psize)))
 
         for (i = 0; i < queue->limit; i++) {
                 entries[i].flags = 0;
@@ -911,7 +1098,8 @@ void rt2x00queue_uninitialize(struct rt2x00_dev *rt2x00dev)
 static void rt2x00queue_init(struct rt2x00_dev *rt2x00dev,
                              struct data_queue *queue, enum data_queue_qid qid)
 {
-        spin_lock_init(&queue->lock);
+        mutex_init(&queue->status_lock);
+        spin_lock_init(&queue->index_lock);
 
         queue->rt2x00dev = rt2x00dev;
         queue->qid = qid;
@@ -953,7 +1141,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
         /*
          * Initialize queue parameters.
          * RX: qid = QID_RX
-         * TX: qid = QID_AC_BE + index
+         * TX: qid = QID_AC_VO + index
          * TX: cw_min: 2^5 = 32.
          * TX: cw_max: 2^10 = 1024.
          * BCN: qid = QID_BEACON
@@ -961,7 +1149,7 @@ int rt2x00queue_allocate(struct rt2x00_dev *rt2x00dev)
          */
         rt2x00queue_init(rt2x00dev, rt2x00dev->rx, QID_RX);
 
-        qid = QID_AC_BE;
+        qid = QID_AC_VO;
         tx_queue_for_each(rt2x00dev, queue)
                 rt2x00queue_init(rt2x00dev, queue, qid++);
 
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index d81d85f34866..fab8e2687f29 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -43,28 +43,12 @@
 #define AGGREGATION_SIZE        3840
 
 /**
- * DOC: Number of entries per queue
- *
- * Under normal load without fragmentation, 12 entries are sufficient
- * without the queue being filled up to the maximum. When using fragmentation
- * and the queue threshold code, we need to add some additional margins to
- * make sure the queue will never (or only under extreme load) fill up
- * completely.
- * Since we don't use preallocated DMA, having a large number of queue entries
- * will have minimal impact on the memory requirements for the queue.
- */
-#define RX_ENTRIES      24
-#define TX_ENTRIES      24
-#define BEACON_ENTRIES  1
-#define ATIM_ENTRIES    8
-
-/**
  * enum data_queue_qid: Queue identification
  *
+ * @QID_AC_VO: AC VO queue
+ * @QID_AC_VI: AC VI queue
  * @QID_AC_BE: AC BE queue
  * @QID_AC_BK: AC BK queue
- * @QID_AC_VI: AC VI queue
- * @QID_AC_VO: AC VO queue
  * @QID_HCCA: HCCA queue
  * @QID_MGMT: MGMT queue (prio queue)
  * @QID_RX: RX queue
@@ -73,10 +57,10 @@
  * @QID_ATIM: Atim queue (value unspeficied, don't send it to device)
  */
 enum data_queue_qid {
-        QID_AC_BE = 0,
-        QID_AC_BK = 1,
-        QID_AC_VI = 2,
-        QID_AC_VO = 3,
+        QID_AC_VO = 0,
+        QID_AC_VI = 1,
+        QID_AC_BE = 2,
+        QID_AC_BK = 3,
         QID_HCCA = 4,
         QID_MGMT = 13,
         QID_RX = 14,
@@ -296,7 +280,6 @@ enum txentry_desc_flags {
  * Summary of information for the frame descriptor before sending a TX frame.
  *
  * @flags: Descriptor flags (See &enum queue_entry_flags).
- * @qid: Queue identification (See &enum data_queue_qid).
  * @length: Length of the entire frame.
  * @header_length: Length of 802.11 header.
  * @length_high: PLCP length high word.
@@ -309,11 +292,8 @@ enum txentry_desc_flags {
  * @rate_mode: Rate mode (See @enum rate_modulation).
  * @mpdu_density: MDPU density.
  * @retry_limit: Max number of retries.
- * @aifs: AIFS value.
  * @ifs: IFS value.
  * @txop: IFS value for 11n capable chips.
- * @cw_min: cwmin value.
- * @cw_max: cwmax value.
  * @cipher: Cipher type used for encryption.
  * @key_idx: Key index used for encryption.
  * @iv_offset: Position where IV should be inserted by hardware.
@@ -322,8 +302,6 @@ enum txentry_desc_flags {
 struct txentry_desc {
         unsigned long flags;
 
-        enum data_queue_qid qid;
-
         u16 length;
         u16 header_length;
 
@@ -339,11 +317,8 @@ struct txentry_desc {
         u16 mpdu_density;
 
         short retry_limit;
-        short aifs;
         short ifs;
         short txop;
-        short cw_min;
-        short cw_max;
 
         enum cipher cipher;
         u16 key_idx;
@@ -365,12 +340,16 @@ struct txentry_desc {
  * @ENTRY_DATA_IO_FAILED: Hardware indicated that an IO error occured
  *      while transfering the data to the hardware. No TX status report will
  *      be expected from the hardware.
+ * @ENTRY_DATA_STATUS_PENDING: The entry has been send to the device and
+ *      returned. It is now waiting for the status reporting before the
+ *      entry can be reused again.
  */
 enum queue_entry_flags {
         ENTRY_BCN_ASSIGNED,
         ENTRY_OWNER_DEVICE_DATA,
         ENTRY_DATA_PENDING,
-        ENTRY_DATA_IO_FAILED
+        ENTRY_DATA_IO_FAILED,
+        ENTRY_DATA_STATUS_PENDING,
 };
 
 /**
@@ -417,13 +396,33 @@ enum queue_index {
 };
 
 /**
+ * enum data_queue_flags: Status flags for data queues
+ *
+ * @QUEUE_STARTED: The queue has been started. Fox RX queues this means the
+ *      device might be DMA'ing skbuffers. TX queues will accept skbuffers to
+ *      be transmitted and beacon queues will start beaconing the configured
+ *      beacons.
+ * @QUEUE_PAUSED: The queue has been started but is currently paused.
+ *      When this bit is set, the queue has been stopped in mac80211,
+ *      preventing new frames to be enqueued. However, a few frames
+ *      might still appear shortly after the pausing...
+ */
+enum data_queue_flags {
+        QUEUE_STARTED,
+        QUEUE_PAUSED,
+};
+
+/**
  * struct data_queue: Data queue
  *
  * @rt2x00dev: Pointer to main &struct rt2x00dev where this queue belongs to.
  * @entries: Base address of the &struct queue_entry which are
  *      part of this queue.
  * @qid: The queue identification, see &enum data_queue_qid.
- * @lock: Spinlock to protect index handling. Whenever @index, @index_done or
+ * @flags: Entry flags, see &enum queue_entry_flags.
+ * @status_lock: The mutex for protecting the start/stop/flush
+ *      handling on this queue.
+ * @index_lock: Spinlock to protect index handling. Whenever @index, @index_done or
  *      @index_crypt needs to be changed this lock should be grabbed to prevent
  *      index corruption due to concurrency.
  * @count: Number of frames handled in the queue.
@@ -446,8 +445,11 @@ struct data_queue {
         struct queue_entry *entries;
 
         enum data_queue_qid qid;
+        unsigned long flags;
+
+        struct mutex status_lock;
+        spinlock_t index_lock;
 
-        spinlock_t lock;
         unsigned int count;
         unsigned short limit;
         unsigned short threshold;
@@ -618,10 +620,10 @@ static inline int rt2x00queue_threshold(struct data_queue *queue)
 }
 
 /**
- * rt2x00queue_timeout - Check if a timeout occured for STATUS reorts
+ * rt2x00queue_status_timeout - Check if a timeout occured for STATUS reports
  * @queue: Queue to check.
  */
-static inline int rt2x00queue_timeout(struct data_queue *queue)
+static inline int rt2x00queue_status_timeout(struct data_queue *queue)
 {
         return time_after(queue->last_action[Q_INDEX_DMA_DONE],
                           queue->last_action[Q_INDEX_DONE] + (HZ / 10));
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
index cef94621cef7..e8259ae48ced 100644
--- a/drivers/net/wireless/rt2x00/rt2x00reg.h
+++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
@@ -83,10 +83,6 @@ enum dev_state {
  */
         STATE_RADIO_ON,
         STATE_RADIO_OFF,
-        STATE_RADIO_RX_ON,
-        STATE_RADIO_RX_OFF,
-        STATE_RADIO_RX_ON_LINK,
-        STATE_RADIO_RX_OFF_LINK,
         STATE_RADIO_IRQ_ON,
         STATE_RADIO_IRQ_OFF,
         STATE_RADIO_IRQ_ON_ISR,
diff --git a/drivers/net/wireless/rt2x00/rt2x00soc.c b/drivers/net/wireless/rt2x00/rt2x00soc.c
index fc98063de71d..2aa5c38022f3 100644
--- a/drivers/net/wireless/rt2x00/rt2x00soc.c
+++ b/drivers/net/wireless/rt2x00/rt2x00soc.c
@@ -40,6 +40,8 @@ static void rt2x00soc_free_reg(struct rt2x00_dev *rt2x00dev)
 
         kfree(rt2x00dev->eeprom);
         rt2x00dev->eeprom = NULL;
+
+        iounmap(rt2x00dev->csr.base);
 }
 
 static int rt2x00soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
@@ -51,9 +53,9 @@ static int rt2x00soc_alloc_reg(struct rt2x00_dev *rt2x00dev)
         if (!res)
                 return -ENODEV;
 
-        rt2x00dev->csr.base = (void __iomem *)KSEG1ADDR(res->start);
+        rt2x00dev->csr.base = ioremap(res->start, resource_size(res));
         if (!rt2x00dev->csr.base)
-                goto exit;
+                return -ENOMEM;
 
         rt2x00dev->eeprom = kzalloc(rt2x00dev->ops->eeprom_size, GFP_KERNEL);
         if (!rt2x00dev->eeprom)
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index b3317df7a7d4..1a9937d5aff6 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -195,7 +195,8 @@ static void rt2x00usb_work_txdone(struct work_struct *work)
                 while (!rt2x00queue_empty(queue)) {
                         entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 
-                        if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
+                        if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
+                            !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
                                 break;
 
                         rt2x00usb_work_txdone_entry(entry);
@@ -226,9 +227,7 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb)
          * Schedule the delayed work for reading the TX status
          * from the device.
          */
-        if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
-            test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
-                ieee80211_queue_work(rt2x00dev->hw, &rt2x00dev->txdone_work);
+        ieee80211_queue_work(rt2x00dev->hw, &rt2x00dev->txdone_work);
 }
 
 static void rt2x00usb_kick_tx_entry(struct queue_entry *entry)
@@ -237,8 +236,10 @@ static void rt2x00usb_kick_tx_entry(struct queue_entry *entry)
         struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
         struct queue_entry_priv_usb *entry_priv = entry->priv_data;
         u32 length;
+        int status;
 
-        if (!test_and_clear_bit(ENTRY_DATA_PENDING, &entry->flags))
+        if (!test_and_clear_bit(ENTRY_DATA_PENDING, &entry->flags) ||
+            test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
                 return;
 
         /*
@@ -253,121 +254,15 @@ static void rt2x00usb_kick_tx_entry(struct queue_entry *entry)
                           entry->skb->data, length,
                           rt2x00usb_interrupt_txdone, entry);
 
-        if (usb_submit_urb(entry_priv->urb, GFP_ATOMIC)) {
+        status = usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
+        if (status) {
+                if (status == -ENODEV)
+                        clear_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
                 set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
                 rt2x00lib_dmadone(entry);
         }
 }
 
-void rt2x00usb_kick_tx_queue(struct data_queue *queue)
-{
-        rt2x00queue_for_each_entry(queue, Q_INDEX_DONE, Q_INDEX,
-                                   rt2x00usb_kick_tx_entry);
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_kick_tx_queue);
-
-static void rt2x00usb_kill_tx_entry(struct queue_entry *entry)
-{
-        struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
-        struct queue_entry_priv_usb *entry_priv = entry->priv_data;
-        struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
-
-        if (!test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
-                return;
-
-        usb_kill_urb(entry_priv->urb);
-
-        /*
-         * Kill guardian urb (if required by driver).
-         */
-        if ((entry->queue->qid == QID_BEACON) &&
-            (test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags)))
-                usb_kill_urb(bcn_priv->guardian_urb);
-}
-
-void rt2x00usb_kill_tx_queue(struct data_queue *queue)
-{
-        rt2x00queue_for_each_entry(queue, Q_INDEX_DONE, Q_INDEX,
-                                   rt2x00usb_kill_tx_entry);
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_kill_tx_queue);
-
-static void rt2x00usb_watchdog_tx_dma(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        unsigned short threshold = queue->threshold;
-
-        WARNING(queue->rt2x00dev, "TX queue %d DMA timed out,"
-                " invoke forced forced reset", queue->qid);
-
-        /*
-         * Temporarily disable the TX queue, this will force mac80211
-         * to use the other queues until this queue has been restored.
-         *
-         * Set the queue threshold to the queue limit. This prevents the
-         * queue from being enabled during the txdone handler.
-         */
-        queue->threshold = queue->limit;
-        ieee80211_stop_queue(rt2x00dev->hw, queue->qid);
-
-        /*
-         * Kill all entries in the queue, afterwards we need to
-         * wait a bit for all URBs to be cancelled.
-         */
-        rt2x00usb_kill_tx_queue(queue);
-
-        /*
-         * In case that a driver has overriden the txdone_work
-         * function, we invoke the TX done through there.
-         */
-        rt2x00dev->txdone_work.func(&rt2x00dev->txdone_work);
-
-        /*
-         * Security measure: if the driver did override the
-         * txdone_work function, and the hardware did arrive
-         * in a state which causes it to malfunction, it is
-         * possible that the driver couldn't handle the txdone
-         * event correctly. So after giving the driver the
-         * chance to cleanup, we now force a cleanup of any
-         * leftovers.
-         */
-        if (!rt2x00queue_empty(queue)) {
-                WARNING(queue->rt2x00dev, "TX queue %d DMA timed out,"
-                        " status handling failed, invoke hard reset", queue->qid);
-                rt2x00usb_work_txdone(&rt2x00dev->txdone_work);
-        }
-
-        /*
-         * The queue has been reset, and mac80211 is allowed to use the
-         * queue again.
-         */
-        queue->threshold = threshold;
-        ieee80211_wake_queue(rt2x00dev->hw, queue->qid);
-}
-
-static void rt2x00usb_watchdog_tx_status(struct data_queue *queue)
-{
-        WARNING(queue->rt2x00dev, "TX queue %d status timed out,"
-                " invoke forced tx handler", queue->qid);
-
-        ieee80211_queue_work(queue->rt2x00dev->hw, &queue->rt2x00dev->txdone_work);
-}
-
-void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev)
-{
-        struct data_queue *queue;
-
-        tx_queue_for_each(rt2x00dev, queue) {
-                if (!rt2x00queue_empty(queue)) {
-                        if (rt2x00queue_dma_timeout(queue))
-                                rt2x00usb_watchdog_tx_dma(queue);
-                        if (rt2x00queue_timeout(queue))
-                                rt2x00usb_watchdog_tx_status(queue);
-                }
-        }
-}
-EXPORT_SYMBOL_GPL(rt2x00usb_watchdog);
-
 /*
  * RX data handlers.
  */
@@ -382,7 +277,8 @@ static void rt2x00usb_work_rxdone(struct work_struct *work)
         while (!rt2x00queue_empty(rt2x00dev->rx)) {
                 entry = rt2x00queue_get_entry(rt2x00dev->rx, Q_INDEX_DONE);
 
-                if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
+                if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
+                    !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
                         break;
 
                 /*
@@ -424,11 +320,157 @@ static void rt2x00usb_interrupt_rxdone(struct urb *urb)
          * Schedule the delayed work for reading the RX status
          * from the device.
          */
-        if (test_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags) &&
-            test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
-                ieee80211_queue_work(rt2x00dev->hw, &rt2x00dev->rxdone_work);
+        ieee80211_queue_work(rt2x00dev->hw, &rt2x00dev->rxdone_work);
 }
 
+static void rt2x00usb_kick_rx_entry(struct queue_entry *entry)
+{
+        struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
+        struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
+        struct queue_entry_priv_usb *entry_priv = entry->priv_data;
+        int status;
+
+        if (test_and_set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
+            test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
+                return;
+
+        rt2x00lib_dmastart(entry);
+
+        usb_fill_bulk_urb(entry_priv->urb, usb_dev,
+                          usb_rcvbulkpipe(usb_dev, entry->queue->usb_endpoint),
+                          entry->skb->data, entry->skb->len,
+                          rt2x00usb_interrupt_rxdone, entry);
+
+        status = usb_submit_urb(entry_priv->urb, GFP_ATOMIC);
+        if (status) {
+                if (status == -ENODEV)
+                        clear_bit(DEVICE_STATE_PRESENT, &rt2x00dev->flags);
+                set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
+                rt2x00lib_dmadone(entry);
+        }
+}
+
+void rt2x00usb_kick_queue(struct data_queue *queue)
+{
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_AC_BE:
+        case QID_AC_BK:
+                if (!rt2x00queue_empty(queue))
+                        rt2x00queue_for_each_entry(queue, Q_INDEX_DONE, Q_INDEX,
+                                                   rt2x00usb_kick_tx_entry);
+                break;
+        case QID_RX:
+                if (!rt2x00queue_full(queue))
+                        rt2x00queue_for_each_entry(queue, Q_INDEX_DONE, Q_INDEX,
+                                                   rt2x00usb_kick_rx_entry);
+                break;
+        default:
+                break;
+        }
+}
+EXPORT_SYMBOL_GPL(rt2x00usb_kick_queue);
+
+static void rt2x00usb_flush_entry(struct queue_entry *entry)
+{
+        struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
+        struct queue_entry_priv_usb *entry_priv = entry->priv_data;
+        struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
+
+        if (!test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags))
+                return;
+
+        usb_kill_urb(entry_priv->urb);
+
+        /*
+         * Kill guardian urb (if required by driver).
+         */
+        if ((entry->queue->qid == QID_BEACON) &&
+            (test_bit(DRIVER_REQUIRE_BEACON_GUARD, &rt2x00dev->flags)))
+                usb_kill_urb(bcn_priv->guardian_urb);
+}
+
+void rt2x00usb_flush_queue(struct data_queue *queue)
+{
+        struct work_struct *completion;
+        unsigned int i;
+
+        rt2x00queue_for_each_entry(queue, Q_INDEX_DONE, Q_INDEX,
+                                   rt2x00usb_flush_entry);
+
+        /*
+         * Obtain the queue completion handler
+         */
+        switch (queue->qid) {
+        case QID_AC_VO:
+        case QID_AC_VI:
+        case QID_AC_BE:
+        case QID_AC_BK:
+                completion = &queue->rt2x00dev->txdone_work;
+                break;
+        case QID_RX:
+                completion = &queue->rt2x00dev->rxdone_work;
+                break;
+        default:
+                return;
+        }
+
+        for (i = 0; i < 20; i++) {
+                /*
+                 * Check if the driver is already done, otherwise we
+                 * have to sleep a little while to give the driver/hw
+                 * the oppurtunity to complete interrupt process itself.
+                 */
+                if (rt2x00queue_empty(queue))
+                        break;
+
+                /*
+                 * Schedule the completion handler manually, when this
+                 * worker function runs, it should cleanup the queue.
+                 */
+                ieee80211_queue_work(queue->rt2x00dev->hw, completion);
+
+                /*
+                 * Wait for a little while to give the driver
+                 * the oppurtunity to recover itself.
+                 */
+                msleep(10);
+        }
+}
+EXPORT_SYMBOL_GPL(rt2x00usb_flush_queue);
+
+static void rt2x00usb_watchdog_tx_dma(struct data_queue *queue)
+{
+        WARNING(queue->rt2x00dev, "TX queue %d DMA timed out,"
+                " invoke forced forced reset\n", queue->qid);
+
+        rt2x00queue_flush_queue(queue, true);
+}
+
+static void rt2x00usb_watchdog_tx_status(struct data_queue *queue)
+{
+        WARNING(queue->rt2x00dev, "TX queue %d status timed out,"
+                " invoke forced tx handler\n", queue->qid);
+
+        ieee80211_queue_work(queue->rt2x00dev->hw, &queue->rt2x00dev->txdone_work);
+}
+
+void rt2x00usb_watchdog(struct rt2x00_dev *rt2x00dev)
+{
+        struct data_queue *queue;
+
+        tx_queue_for_each(rt2x00dev, queue) {
+                if (!rt2x00queue_empty(queue)) {
+                        if (rt2x00queue_dma_timeout(queue))
+                                rt2x00usb_watchdog_tx_dma(queue);
+                        if (rt2x00queue_status_timeout(queue))
+                                rt2x00usb_watchdog_tx_status(queue);
+                }
+        }
+}
+EXPORT_SYMBOL_GPL(rt2x00usb_watchdog);
+
 /*
  * Radio handlers
  */
@@ -436,12 +478,6 @@ void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev)
 {
         rt2x00usb_vendor_request_sw(rt2x00dev, USB_RX_CONTROL, 0, 0,
                                     REGISTER_TIMEOUT);
-
-        /*
-         * The USB version of kill_tx_queue also works
-         * on the RX queue.
-         */
-        rt2x00dev->ops->lib->kill_tx_queue(rt2x00dev->rx);
 }
 EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
 
@@ -450,25 +486,10 @@ EXPORT_SYMBOL_GPL(rt2x00usb_disable_radio);
  */
 void rt2x00usb_clear_entry(struct queue_entry *entry)
 {
-        struct usb_device *usb_dev =
-            to_usb_device_intf(entry->queue->rt2x00dev->dev);
-        struct queue_entry_priv_usb *entry_priv = entry->priv_data;
-        int pipe;
-
         entry->flags = 0;
 
-        if (entry->queue->qid == QID_RX) {
-                pipe = usb_rcvbulkpipe(usb_dev, entry->queue->usb_endpoint);
-                usb_fill_bulk_urb(entry_priv->urb, usb_dev, pipe,
-                                entry->skb->data, entry->skb->len,
-                                rt2x00usb_interrupt_rxdone, entry);
-
-                set_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
-                if (usb_submit_urb(entry_priv->urb, GFP_ATOMIC)) {
-                        set_bit(ENTRY_DATA_IO_FAILED, &entry->flags);
-                        rt2x00lib_dmadone(entry);
-                }
-        }
+        if (entry->queue->qid == QID_RX)
+                rt2x00usb_kick_rx_entry(entry);
 }
 EXPORT_SYMBOL_GPL(rt2x00usb_clear_entry);
 
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index c2d997f67b3e..6aaf51fc7ad8 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -378,22 +378,22 @@ struct queue_entry_priv_usb_bcn {
 };
 
 /**
- * rt2x00usb_kick_tx_queue - Kick data queue
+ * rt2x00usb_kick_queue - Kick data queue
  * @queue: Data queue to kick
  *
  * This will walk through all entries of the queue and push all pending
  * frames to the hardware as a single burst.
  */
-void rt2x00usb_kick_tx_queue(struct data_queue *queue);
+void rt2x00usb_kick_queue(struct data_queue *queue);
 
 /**
- * rt2x00usb_kill_tx_queue - Kill data queue
- * @queue: Data queue to kill
+ * rt2x00usb_flush_queue - Flush data queue
+ * @queue: Data queue to stop
  *
  * This will walk through all entries of the queue and kill all
- * previously kicked frames before they can be send.
+ * URB's which were send to the device.
  */
-void rt2x00usb_kill_tx_queue(struct data_queue *queue);
+void rt2x00usb_flush_queue(struct data_queue *queue);
 
 /**
  * rt2x00usb_watchdog - Watchdog for USB communication
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index af548c87f108..8de44dd401e0 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -1140,6 +1140,106 @@ dynamic_cca_tune:
 }
 
 /*
+ * Queue handlers.
+ */
+static void rt61pci_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
+                rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
+                rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
+                rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt61pci_kick_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_AC_VI:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_AC_BE:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_AC_BK:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt61pci_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_AC_VO:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_AC_VI:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_AC_BE:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_AC_BK:
+                rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
+                rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
+                rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
+                break;
+        case QID_RX:
+                rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
+                rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
+                rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
+                rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+/*
  * Firmware functions
  */
 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1616,18 +1716,6 @@ static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 /*
  * Device state switch handlers.
  */
-static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                              enum dev_state state)
-{
-        u32 reg;
-
-        rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
-        rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
-                           (state == STATE_RADIO_RX_OFF) ||
-                           (state == STATE_RADIO_RX_OFF_LINK));
-        rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
-}
-
 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
                                enum dev_state state)
 {
@@ -1744,12 +1832,6 @@ static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
         case STATE_RADIO_OFF:
                 rt61pci_disable_radio(rt2x00dev);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt61pci_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -1789,10 +1871,10 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
          * Start writing the descriptor words.
          */
         rt2x00_desc_read(txd, 1, &word);
-        rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid);
-        rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
-        rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
-        rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
+        rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
+        rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
+        rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
+        rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
@@ -1820,7 +1902,7 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
         rt2x00_desc_write(txd, 5, word);
 
-        if (txdesc->qid != QID_BEACON) {
+        if (entry->queue->qid != QID_BEACON) {
                 rt2x00_desc_read(txd, 6, &word);
                 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
                                    skbdesc->skb_dma);
@@ -1866,8 +1948,8 @@ static void rt61pci_write_tx_desc(struct queue_entry *entry,
          * Register descriptor details in skb frame descriptor.
          */
         skbdesc->desc = txd;
-        skbdesc->desc_len =
-                (txdesc->qid == QID_BEACON) ?  TXINFO_SIZE : TXD_DESC_SIZE;
+        skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE :
+                            TXD_DESC_SIZE;
 }
 
 /*
@@ -1879,6 +1961,7 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
         unsigned int beacon_base;
+        unsigned int padding_len;
         u32 reg;
 
         /*
@@ -1900,13 +1983,16 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 
         /*
-         * Write entire beacon with descriptor to register.
+         * Write entire beacon with descriptor and padding to register.
          */
+        padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
+        skb_pad(entry->skb, padding_len);
         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
                                       entry_priv->desc, TXINFO_SIZE);
         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
-                                      entry->skb->data, entry->skb->len);
+                                      entry->skb->data,
+                                      entry->skb->len + padding_len);
 
         /*
          * Enable beaconing again.
@@ -1928,37 +2014,6 @@ static void rt61pci_write_beacon(struct queue_entry *entry,
         entry->skb = NULL;
 }
 
-static void rt61pci_kick_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue->qid == QID_AC_BE));
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue->qid == QID_AC_BK));
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue->qid == QID_AC_VI));
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue->qid == QID_AC_VO));
-        rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
-}
-
-static void rt61pci_kill_tx_queue(struct data_queue *queue)
-{
-        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
-        u32 reg;
-
-        if (queue->qid == QID_BEACON) {
-                rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
-                return;
-        }
-
-        rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, (queue->qid == QID_AC_BE));
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, (queue->qid == QID_AC_BK));
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, (queue->qid == QID_AC_VI));
-        rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, (queue->qid == QID_AC_VO));
-        rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
-}
-
 /*
  * RX control handlers
  */
@@ -2078,7 +2133,7 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
          * that the TX_STA_FIFO stack has a size of 16. We stick to our
          * tx ring size for now.
          */
-        for (i = 0; i < TX_ENTRIES; i++) {
+        for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
                         break;
@@ -2824,6 +2879,7 @@ static const struct ieee80211_ops rt61pci_mac80211_ops = {
         .conf_tx                = rt61pci_conf_tx,
         .get_tsf                = rt61pci_get_tsf,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
+        .flush                  = rt2x00mac_flush,
 };
 
 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
@@ -2842,10 +2898,11 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
         .link_stats             = rt61pci_link_stats,
         .reset_tuner            = rt61pci_reset_tuner,
         .link_tuner             = rt61pci_link_tuner,
+        .start_queue            = rt61pci_start_queue,
+        .kick_queue             = rt61pci_kick_queue,
+        .stop_queue             = rt61pci_stop_queue,
         .write_tx_desc          = rt61pci_write_tx_desc,
         .write_beacon           = rt61pci_write_beacon,
-        .kick_tx_queue          = rt61pci_kick_tx_queue,
-        .kill_tx_queue          = rt61pci_kill_tx_queue,
         .fill_rxdone            = rt61pci_fill_rxdone,
         .config_shared_key      = rt61pci_config_shared_key,
         .config_pairwise_key    = rt61pci_config_pairwise_key,
@@ -2857,21 +2914,21 @@ static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt61pci_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = RXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt61pci_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
 };
 
 static const struct data_queue_desc rt61pci_queue_bcn = {
-        .entry_num              = 4 * BEACON_ENTRIES,
+        .entry_num              = 4,
         .data_size              = 0, /* No DMA required for beacons */
         .desc_size              = TXINFO_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_pci),
diff --git a/drivers/net/wireless/rt2x00/rt61pci.h b/drivers/net/wireless/rt2x00/rt61pci.h
index e2e728ab0b2e..e3cd6db76b0e 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.h
+++ b/drivers/net/wireless/rt2x00/rt61pci.h
@@ -412,7 +412,7 @@ struct hw_pairwise_ta_entry {
  * DROP_VERSION_ERROR: Drop version error frame.
  * DROP_MULTICAST: Drop multicast frames.
  * DROP_BORADCAST: Drop broadcast frames.
- * ROP_ACK_CTS: Drop received ACK and CTS.
+ * DROP_ACK_CTS: Drop received ACK and CTS.
  */
 #define TXRX_CSR0                       0x3040
 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
@@ -784,25 +784,25 @@ struct hw_pairwise_ta_entry {
  */
 
 /*
- * AC0_BASE_CSR: AC_BK base address.
+ * AC0_BASE_CSR: AC_VO base address.
  */
 #define AC0_BASE_CSR                    0x3400
 #define AC0_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 
 /*
- * AC1_BASE_CSR: AC_BE base address.
+ * AC1_BASE_CSR: AC_VI base address.
  */
 #define AC1_BASE_CSR                    0x3404
 #define AC1_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 
 /*
- * AC2_BASE_CSR: AC_VI base address.
+ * AC2_BASE_CSR: AC_BE base address.
  */
 #define AC2_BASE_CSR                    0x3408
 #define AC2_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 
 /*
- * AC3_BASE_CSR: AC_VO base address.
+ * AC3_BASE_CSR: AC_BK base address.
  */
 #define AC3_BASE_CSR                    0x340c
 #define AC3_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
@@ -814,7 +814,7 @@ struct hw_pairwise_ta_entry {
 #define MGMT_BASE_CSR_RING_REGISTER     FIELD32(0xffffffff)
 
 /*
- * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
+ * TX_RING_CSR0: TX Ring size for AC_VO, AC_VI, AC_BE, AC_BK.
  */
 #define TX_RING_CSR0                    0x3418
 #define TX_RING_CSR0_AC0_RING_SIZE      FIELD32(0x000000ff)
@@ -833,10 +833,10 @@ struct hw_pairwise_ta_entry {
 
 /*
  * AIFSN_CSR: AIFSN for each EDCA AC.
- * AIFSN0: For AC_BK.
- * AIFSN1: For AC_BE.
- * AIFSN2: For AC_VI.
- * AIFSN3: For AC_VO.
+ * AIFSN0: For AC_VO.
+ * AIFSN1: For AC_VI.
+ * AIFSN2: For AC_BE.
+ * AIFSN3: For AC_BK.
  */
 #define AIFSN_CSR                       0x3420
 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
@@ -846,10 +846,10 @@ struct hw_pairwise_ta_entry {
 
 /*
  * CWMIN_CSR: CWmin for each EDCA AC.
- * CWMIN0: For AC_BK.
- * CWMIN1: For AC_BE.
- * CWMIN2: For AC_VI.
- * CWMIN3: For AC_VO.
+ * CWMIN0: For AC_VO.
+ * CWMIN1: For AC_VI.
+ * CWMIN2: For AC_BE.
+ * CWMIN3: For AC_BK.
  */
 #define CWMIN_CSR                       0x3424
 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
@@ -859,10 +859,10 @@ struct hw_pairwise_ta_entry {
 
 /*
  * CWMAX_CSR: CWmax for each EDCA AC.
- * CWMAX0: For AC_BK.
- * CWMAX1: For AC_BE.
- * CWMAX2: For AC_VI.
- * CWMAX3: For AC_VO.
+ * CWMAX0: For AC_VO.
+ * CWMAX1: For AC_VI.
+ * CWMAX2: For AC_BE.
+ * CWMAX3: For AC_BK.
  */
 #define CWMAX_CSR                       0x3428
 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
@@ -883,14 +883,14 @@ struct hw_pairwise_ta_entry {
 
 /*
  * TX_CNTL_CSR: KICK/Abort TX.
- * KICK_TX_AC0: For AC_BK.
- * KICK_TX_AC1: For AC_BE.
- * KICK_TX_AC2: For AC_VI.
- * KICK_TX_AC3: For AC_VO.
- * ABORT_TX_AC0: For AC_BK.
- * ABORT_TX_AC1: For AC_BE.
- * ABORT_TX_AC2: For AC_VI.
- * ABORT_TX_AC3: For AC_VO.
+ * KICK_TX_AC0: For AC_VO.
+ * KICK_TX_AC1: For AC_VI.
+ * KICK_TX_AC2: For AC_BE.
+ * KICK_TX_AC3: For AC_BK.
+ * ABORT_TX_AC0: For AC_VO.
+ * ABORT_TX_AC1: For AC_VI.
+ * ABORT_TX_AC2: For AC_BE.
+ * ABORT_TX_AC3: For AC_BK.
  */
 #define TX_CNTL_CSR                     0x3430
 #define TX_CNTL_CSR_KICK_TX_AC0         FIELD32(0x00000001)
@@ -1010,18 +1010,18 @@ struct hw_pairwise_ta_entry {
 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
 
 /*
- * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
- * AC0_TX_OP: For AC_BK, in unit of 32us.
- * AC1_TX_OP: For AC_BE, in unit of 32us.
+ * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
+ * AC0_TX_OP: For AC_VO, in unit of 32us.
+ * AC1_TX_OP: For AC_VI, in unit of 32us.
  */
 #define AC_TXOP_CSR0                    0x3474
 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
 
 /*
- * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
- * AC2_TX_OP: For AC_VI, in unit of 32us.
- * AC3_TX_OP: For AC_VO, in unit of 32us.
+ * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
+ * AC2_TX_OP: For AC_BE, in unit of 32us.
+ * AC3_TX_OP: For AC_BK, in unit of 32us.
  */
 #define AC_TXOP_CSR1                    0x3478
 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index 9be8089317e4..0b4e8590cbb7 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -40,7 +40,7 @@
 /*
  * Allow hardware encryption to be disabled.
  */
-static int modparam_nohwcrypt = 0;
+static int modparam_nohwcrypt;
 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
 
@@ -1031,6 +1031,55 @@ dynamic_cca_tune:
 }
 
 /*
+ * Queue handlers.
+ */
+static void rt73usb_start_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
+                rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
+                rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
+                rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+static void rt73usb_stop_queue(struct data_queue *queue)
+{
+        struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
+        u32 reg;
+
+        switch (queue->qid) {
+        case QID_RX:
+                rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 1);
+                rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
+                break;
+        case QID_BEACON:
+                rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
+                rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
+                rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
+                rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
+                break;
+        default:
+                break;
+        }
+}
+
+/*
  * Firmware functions
  */
 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
@@ -1324,18 +1373,6 @@ static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
 /*
  * Device state switch handlers.
  */
-static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
-                              enum dev_state state)
-{
-        u32 reg;
-
-        rt2x00usb_register_read(rt2x00dev, TXRX_CSR0, &reg);
-        rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
-                           (state == STATE_RADIO_RX_OFF) ||
-                           (state == STATE_RADIO_RX_OFF_LINK));
-        rt2x00usb_register_write(rt2x00dev, TXRX_CSR0, reg);
-}
-
 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
 {
         /*
@@ -1402,12 +1439,6 @@ static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
         case STATE_RADIO_OFF:
                 rt73usb_disable_radio(rt2x00dev);
                 break;
-        case STATE_RADIO_RX_ON:
-        case STATE_RADIO_RX_ON_LINK:
-        case STATE_RADIO_RX_OFF:
-        case STATE_RADIO_RX_OFF_LINK:
-                rt73usb_toggle_rx(rt2x00dev, state);
-                break;
         case STATE_RADIO_IRQ_ON:
         case STATE_RADIO_IRQ_ON_ISR:
         case STATE_RADIO_IRQ_OFF:
@@ -1472,10 +1503,10 @@ static void rt73usb_write_tx_desc(struct queue_entry *entry,
         rt2x00_desc_write(txd, 0, word);
 
         rt2x00_desc_read(txd, 1, &word);
-        rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->qid);
-        rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
-        rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
-        rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
+        rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid);
+        rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs);
+        rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min);
+        rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max);
         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE,
                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
@@ -1515,6 +1546,7 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
 {
         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
         unsigned int beacon_base;
+        unsigned int padding_len;
         u32 reg;
 
         /*
@@ -1542,11 +1574,13 @@ static void rt73usb_write_beacon(struct queue_entry *entry,
         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
 
         /*
-         * Write entire beacon with descriptor to register.
+         * Write entire beacon with descriptor and padding to register.
          */
+        padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
+        skb_pad(entry->skb, padding_len);
         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
-        rt2x00usb_register_multiwrite(rt2x00dev, beacon_base,
-                                      entry->skb->data, entry->skb->len);
+        rt2x00usb_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
+                                      entry->skb->len + padding_len);
 
         /*
          * Enable beaconing again.
@@ -1582,14 +1616,6 @@ static int rt73usb_get_tx_data_len(struct queue_entry *entry)
         return length;
 }
 
-static void rt73usb_kill_tx_queue(struct data_queue *queue)
-{
-        if (queue->qid == QID_BEACON)
-                rt2x00usb_register_write(queue->rt2x00dev, TXRX_CSR9, 0);
-
-        rt2x00usb_kill_tx_queue(queue);
-}
-
 /*
  * RX control handlers
  */
@@ -2264,6 +2290,7 @@ static const struct ieee80211_ops rt73usb_mac80211_ops = {
         .conf_tx                = rt73usb_conf_tx,
         .get_tsf                = rt73usb_get_tsf,
         .rfkill_poll            = rt2x00mac_rfkill_poll,
+        .flush                  = rt2x00mac_flush,
 };
 
 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
@@ -2280,11 +2307,13 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
         .reset_tuner            = rt73usb_reset_tuner,
         .link_tuner             = rt73usb_link_tuner,
         .watchdog               = rt2x00usb_watchdog,
+        .start_queue            = rt73usb_start_queue,
+        .kick_queue             = rt2x00usb_kick_queue,
+        .stop_queue             = rt73usb_stop_queue,
+        .flush_queue            = rt2x00usb_flush_queue,
         .write_tx_desc          = rt73usb_write_tx_desc,
         .write_beacon           = rt73usb_write_beacon,
         .get_tx_data_len        = rt73usb_get_tx_data_len,
-        .kick_tx_queue          = rt2x00usb_kick_tx_queue,
-        .kill_tx_queue          = rt73usb_kill_tx_queue,
         .fill_rxdone            = rt73usb_fill_rxdone,
         .config_shared_key      = rt73usb_config_shared_key,
         .config_pairwise_key    = rt73usb_config_pairwise_key,
@@ -2296,21 +2325,21 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
 };
 
 static const struct data_queue_desc rt73usb_queue_rx = {
-        .entry_num              = RX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = RXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
 };
 
 static const struct data_queue_desc rt73usb_queue_tx = {
-        .entry_num              = TX_ENTRIES,
+        .entry_num              = 32,
         .data_size              = DATA_FRAME_SIZE,
         .desc_size              = TXD_DESC_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
 };
 
 static const struct data_queue_desc rt73usb_queue_bcn = {
-        .entry_num              = 4 * BEACON_ENTRIES,
+        .entry_num              = 4,
         .data_size              = MGMT_FRAME_SIZE,
         .desc_size              = TXINFO_SIZE,
         .priv_size              = sizeof(struct queue_entry_priv_usb),
diff --git a/drivers/net/wireless/rt2x00/rt73usb.h b/drivers/net/wireless/rt2x00/rt73usb.h
index 44d5b2bebd39..9f6b470414d3 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.h
+++ b/drivers/net/wireless/rt2x00/rt73usb.h
@@ -322,7 +322,7 @@ struct hw_pairwise_ta_entry {
  * DROP_VERSION_ERROR: Drop version error frame.
  * DROP_MULTICAST: Drop multicast frames.
  * DROP_BORADCAST: Drop broadcast frames.
- * ROP_ACK_CTS: Drop received ACK and CTS.
+ * DROP_ACK_CTS: Drop received ACK and CTS.
  */
 #define TXRX_CSR0                       0x3040
 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
@@ -689,10 +689,10 @@ struct hw_pairwise_ta_entry {
 
 /*
  * AIFSN_CSR: AIFSN for each EDCA AC.
- * AIFSN0: For AC_BK.
- * AIFSN1: For AC_BE.
- * AIFSN2: For AC_VI.
- * AIFSN3: For AC_VO.
+ * AIFSN0: For AC_VO.
+ * AIFSN1: For AC_VI.
+ * AIFSN2: For AC_BE.
+ * AIFSN3: For AC_BK.
  */
 #define AIFSN_CSR                       0x0400
 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
@@ -702,10 +702,10 @@ struct hw_pairwise_ta_entry {
 
 /*
  * CWMIN_CSR: CWmin for each EDCA AC.
- * CWMIN0: For AC_BK.
- * CWMIN1: For AC_BE.
- * CWMIN2: For AC_VI.
- * CWMIN3: For AC_VO.
+ * CWMIN0: For AC_VO.
+ * CWMIN1: For AC_VI.
+ * CWMIN2: For AC_BE.
+ * CWMIN3: For AC_BK.
  */
 #define CWMIN_CSR                       0x0404
 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
@@ -715,10 +715,10 @@ struct hw_pairwise_ta_entry {
 
 /*
  * CWMAX_CSR: CWmax for each EDCA AC.
- * CWMAX0: For AC_BK.
- * CWMAX1: For AC_BE.
- * CWMAX2: For AC_VI.
- * CWMAX3: For AC_VO.
+ * CWMAX0: For AC_VO.
+ * CWMAX1: For AC_VI.
+ * CWMAX2: For AC_BE.
+ * CWMAX3: For AC_BK.
  */
 #define CWMAX_CSR                       0x0408
 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
@@ -727,18 +727,18 @@ struct hw_pairwise_ta_entry {
 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 
 /*
- * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
- * AC0_TX_OP: For AC_BK, in unit of 32us.
- * AC1_TX_OP: For AC_BE, in unit of 32us.
+ * AC_TXOP_CSR0: AC_VO/AC_VI TXOP register.
+ * AC0_TX_OP: For AC_VO, in unit of 32us.
+ * AC1_TX_OP: For AC_VI, in unit of 32us.
  */
 #define AC_TXOP_CSR0                    0x040c
 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
 
 /*
- * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
- * AC2_TX_OP: For AC_VI, in unit of 32us.
- * AC3_TX_OP: For AC_VO, in unit of 32us.
+ * AC_TXOP_CSR1: AC_BE/AC_BK TXOP register.
+ * AC2_TX_OP: For AC_BE, in unit of 32us.
+ * AC3_TX_OP: For AC_BK, in unit of 32us.
  */
 #define AC_TXOP_CSR1                    0x0410
 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
diff --git a/drivers/net/wireless/rtl818x/Makefile b/drivers/net/wireless/rtl818x/Makefile
index 93cbfbedb46d..997569076923 100644
--- a/drivers/net/wireless/rtl818x/Makefile
+++ b/drivers/net/wireless/rtl818x/Makefile
@@ -1,7 +1,2 @@
-rtl8180-objs            := rtl8180_dev.o rtl8180_rtl8225.o rtl8180_sa2400.o rtl8180_max2820.o rtl8180_grf5101.o
-rtl8187-objs            := rtl8187_dev.o rtl8187_rtl8225.o rtl8187_leds.o rtl8187_rfkill.o
-
-obj-$(CONFIG_RTL8180)   += rtl8180.o
-obj-$(CONFIG_RTL8187)   += rtl8187.o
-
-
+obj-$(CONFIG_RTL8180)   += rtl8180/
+obj-$(CONFIG_RTL8187)   += rtl8187/
diff --git a/drivers/net/wireless/rtl818x/rtl8180/Makefile b/drivers/net/wireless/rtl818x/rtl8180/Makefile
new file mode 100644
index 000000000000..cb4fb8596f0b
--- /dev/null
+++ b/drivers/net/wireless/rtl818x/rtl8180/Makefile
@@ -0,0 +1,5 @@
+rtl8180-objs            := dev.o rtl8225.o sa2400.o max2820.o grf5101.o
+
+obj-$(CONFIG_RTL8180)   += rtl8180.o
+
+ccflags-y += -Idrivers/net/wireless/rtl818x
diff --git a/drivers/net/wireless/rtl818x/rtl8180_dev.c b/drivers/net/wireless/rtl818x/rtl8180/dev.c
index 707c688da618..5851cbc1e957 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_dev.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/dev.c
@@ -24,10 +24,10 @@
 #include <net/mac80211.h>
 
 #include "rtl8180.h"
-#include "rtl8180_rtl8225.h"
-#include "rtl8180_sa2400.h"
-#include "rtl8180_max2820.h"
-#include "rtl8180_grf5101.h"
+#include "rtl8225.h"
+#include "sa2400.h"
+#include "max2820.h"
+#include "grf5101.h"
 
 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
diff --git a/drivers/net/wireless/rtl818x/rtl8180_grf5101.c b/drivers/net/wireless/rtl818x/rtl8180/grf5101.c
index 5cab9dfa8c07..5ee7589dd546 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_grf5101.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/grf5101.c
@@ -25,7 +25,7 @@
 #include <net/mac80211.h>
 
 #include "rtl8180.h"
-#include "rtl8180_grf5101.h"
+#include "grf5101.h"
 
 static const int grf5101_encode[] = {
         0x0, 0x8, 0x4, 0xC,
diff --git a/drivers/net/wireless/rtl818x/rtl8180_grf5101.h b/drivers/net/wireless/rtl818x/rtl8180/grf5101.h
index 76647111bcff..76647111bcff 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_grf5101.h
+++ b/drivers/net/wireless/rtl818x/rtl8180/grf5101.h
diff --git a/drivers/net/wireless/rtl818x/rtl8180_max2820.c b/drivers/net/wireless/rtl818x/rtl8180/max2820.c
index 16c4655181c0..667b3363d437 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_max2820.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/max2820.c
@@ -24,7 +24,7 @@
 #include <net/mac80211.h>
 
 #include "rtl8180.h"
-#include "rtl8180_max2820.h"
+#include "max2820.h"
 
 static const u32 max2820_chan[] = {
         12, /* CH 1 */
diff --git a/drivers/net/wireless/rtl818x/rtl8180_max2820.h b/drivers/net/wireless/rtl818x/rtl8180/max2820.h
index 61cf6d1e7d57..61cf6d1e7d57 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_max2820.h
+++ b/drivers/net/wireless/rtl818x/rtl8180/max2820.h
diff --git a/drivers/net/wireless/rtl818x/rtl8180.h b/drivers/net/wireless/rtl818x/rtl8180/rtl8180.h
index 30523314da43..30523314da43 100644
--- a/drivers/net/wireless/rtl818x/rtl8180.h
+++ b/drivers/net/wireless/rtl818x/rtl8180/rtl8180.h
diff --git a/drivers/net/wireless/rtl818x/rtl8180_rtl8225.c b/drivers/net/wireless/rtl818x/rtl8180/rtl8225.c
index 69e4d4745dae..7c4574ba9d75 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_rtl8225.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/rtl8225.c
@@ -21,7 +21,7 @@
 #include <net/mac80211.h>
 
 #include "rtl8180.h"
-#include "rtl8180_rtl8225.h"
+#include "rtl8225.h"
 
 static void rtl8225_write(struct ieee80211_hw *dev, u8 addr, u16 data)
 {
diff --git a/drivers/net/wireless/rtl818x/rtl8180_rtl8225.h b/drivers/net/wireless/rtl818x/rtl8180/rtl8225.h
index 310013a2d726..310013a2d726 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_rtl8225.h
+++ b/drivers/net/wireless/rtl818x/rtl8180/rtl8225.h
diff --git a/drivers/net/wireless/rtl818x/rtl8180_sa2400.c b/drivers/net/wireless/rtl818x/rtl8180/sa2400.c
index d064fcc5ec08..44771a6286af 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_sa2400.c
+++ b/drivers/net/wireless/rtl818x/rtl8180/sa2400.c
@@ -25,7 +25,7 @@
 #include <net/mac80211.h>
 
 #include "rtl8180.h"
-#include "rtl8180_sa2400.h"
+#include "sa2400.h"
 
 static const u32 sa2400_chan[] = {
         0x00096c, /* ch1 */
diff --git a/drivers/net/wireless/rtl818x/rtl8180_sa2400.h b/drivers/net/wireless/rtl818x/rtl8180/sa2400.h
index a4aaa0d413f1..a4aaa0d413f1 100644
--- a/drivers/net/wireless/rtl818x/rtl8180_sa2400.h
+++ b/drivers/net/wireless/rtl818x/rtl8180/sa2400.h
diff --git a/drivers/net/wireless/rtl818x/rtl8187/Makefile b/drivers/net/wireless/rtl818x/rtl8187/Makefile
new file mode 100644
index 000000000000..7b6299268ecf
--- /dev/null
+++ b/drivers/net/wireless/rtl818x/rtl8187/Makefile
@@ -0,0 +1,5 @@
+rtl8187-objs            := dev.o rtl8225.o leds.o rfkill.o
+
+obj-$(CONFIG_RTL8187)   += rtl8187.o
+
+ccflags-y += -Idrivers/net/wireless/rtl818x
diff --git a/drivers/net/wireless/rtl818x/rtl8187_dev.c b/drivers/net/wireless/rtl818x/rtl8187/dev.c
index 38fa8244cc96..6b82cac37ee3 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_dev.c
+++ b/drivers/net/wireless/rtl818x/rtl8187/dev.c
@@ -29,11 +29,11 @@
 #include <net/mac80211.h>
 
 #include "rtl8187.h"
-#include "rtl8187_rtl8225.h"
+#include "rtl8225.h"
 #ifdef CONFIG_RTL8187_LEDS
-#include "rtl8187_leds.h"
+#include "leds.h"
 #endif
-#include "rtl8187_rfkill.h"
+#include "rfkill.h"
 
 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
 MODULE_AUTHOR("Andrea Merello <andreamrl@tiscali.it>");
@@ -553,6 +553,46 @@ static int rtl8187b_init_status_urb(struct ieee80211_hw *dev)
         return ret;
 }
 
+static void rtl8187_set_anaparam(struct rtl8187_priv *priv, bool rfon)
+{
+        u32 anaparam, anaparam2;
+        u8 anaparam3, reg;
+
+        if (!priv->is_rtl8187b) {
+                if (rfon) {
+                        anaparam = RTL8187_RTL8225_ANAPARAM_ON;
+                        anaparam2 = RTL8187_RTL8225_ANAPARAM2_ON;
+                } else {
+                        anaparam = RTL8187_RTL8225_ANAPARAM_OFF;
+                        anaparam2 = RTL8187_RTL8225_ANAPARAM2_OFF;
+                }
+        } else {
+                if (rfon) {
+                        anaparam = RTL8187B_RTL8225_ANAPARAM_ON;
+                        anaparam2 = RTL8187B_RTL8225_ANAPARAM2_ON;
+                        anaparam3 = RTL8187B_RTL8225_ANAPARAM3_ON;
+                } else {
+                        anaparam = RTL8187B_RTL8225_ANAPARAM_OFF;
+                        anaparam2 = RTL8187B_RTL8225_ANAPARAM2_OFF;
+                        anaparam3 = RTL8187B_RTL8225_ANAPARAM3_OFF;
+                }
+        }
+
+        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
+                         RTL818X_EEPROM_CMD_CONFIG);
+        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
+        reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
+        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
+        rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
+        rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
+        if (priv->is_rtl8187b)
+                rtl818x_iowrite8(priv, &priv->map->ANAPARAM3, anaparam3);
+        reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
+        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
+        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
+                         RTL818X_EEPROM_CMD_NORMAL);
+}
+
 static int rtl8187_cmd_reset(struct ieee80211_hw *dev)
 {
         struct rtl8187_priv *priv = dev->priv;
@@ -603,19 +643,7 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
         int res;
 
         /* reset */
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
-                         RTL818X_EEPROM_CMD_CONFIG);
-        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg |
-                         RTL818X_CONFIG3_ANAPARAM_WRITE);
-        rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
-                          RTL8187_RTL8225_ANAPARAM_ON);
-        rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
-                          RTL8187_RTL8225_ANAPARAM2_ON);
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg &
-                         ~RTL818X_CONFIG3_ANAPARAM_WRITE);
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
-                         RTL818X_EEPROM_CMD_NORMAL);
+        rtl8187_set_anaparam(priv, true);
 
         rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
 
@@ -629,17 +657,7 @@ static int rtl8187_init_hw(struct ieee80211_hw *dev)
         if (res)
                 return res;
 
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
-        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3,
-                        reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
-        rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
-                          RTL8187_RTL8225_ANAPARAM_ON);
-        rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
-                          RTL8187_RTL8225_ANAPARAM2_ON);
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3,
-                        reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
+        rtl8187_set_anaparam(priv, true);
 
         /* setup card */
         rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0);
@@ -712,10 +730,9 @@ static const u8 rtl8187b_reg_table[][3] = {
 
         {0x58, 0x4B, 1}, {0x59, 0x00, 1}, {0x5A, 0x4B, 1}, {0x5B, 0x00, 1},
         {0x60, 0x4B, 1}, {0x61, 0x09, 1}, {0x62, 0x4B, 1}, {0x63, 0x09, 1},
-        {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xE0, 0xFF, 1}, {0xE1, 0x0F, 1},
-        {0xE2, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1}, {0xF2, 0x02, 1},
-        {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1}, {0xF6, 0x06, 1},
-        {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
+        {0xCE, 0x0F, 1}, {0xCF, 0x00, 1}, {0xF0, 0x4E, 1}, {0xF1, 0x01, 1},
+        {0xF2, 0x02, 1}, {0xF3, 0x03, 1}, {0xF4, 0x04, 1}, {0xF5, 0x05, 1},
+        {0xF6, 0x06, 1}, {0xF7, 0x07, 1}, {0xF8, 0x08, 1},
 
         {0x4E, 0x00, 2}, {0x0C, 0x04, 2}, {0x21, 0x61, 2}, {0x22, 0x68, 2},
         {0x23, 0x6F, 2}, {0x24, 0x76, 2}, {0x25, 0x7D, 2}, {0x26, 0x84, 2},
@@ -723,14 +740,13 @@ static const u8 rtl8187b_reg_table[][3] = {
         {0x52, 0x04, 2}, {0x53, 0xA0, 2}, {0x54, 0x1F, 2}, {0x55, 0x23, 2},
         {0x56, 0x45, 2}, {0x57, 0x67, 2}, {0x58, 0x08, 2}, {0x59, 0x08, 2},
         {0x5A, 0x08, 2}, {0x5B, 0x08, 2}, {0x60, 0x08, 2}, {0x61, 0x08, 2},
-        {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2}, {0x72, 0x56, 2},
-        {0x73, 0x9A, 2},
+        {0x62, 0x08, 2}, {0x63, 0x08, 2}, {0x64, 0xCF, 2},
 
-        {0x34, 0xF0, 0}, {0x35, 0x0F, 0}, {0x5B, 0x40, 0}, {0x84, 0x88, 0},
-        {0x85, 0x24, 0}, {0x88, 0x54, 0}, {0x8B, 0xB8, 0}, {0x8C, 0x07, 0},
-        {0x8D, 0x00, 0}, {0x94, 0x1B, 0}, {0x95, 0x12, 0}, {0x96, 0x00, 0},
-        {0x97, 0x06, 0}, {0x9D, 0x1A, 0}, {0x9F, 0x10, 0}, {0xB4, 0x22, 0},
-        {0xBE, 0x80, 0}, {0xDB, 0x00, 0}, {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
+        {0x5B, 0x40, 0}, {0x84, 0x88, 0}, {0x85, 0x24, 0}, {0x88, 0x54, 0},
+        {0x8B, 0xB8, 0}, {0x8C, 0x07, 0}, {0x8D, 0x00, 0}, {0x94, 0x1B, 0},
+        {0x95, 0x12, 0}, {0x96, 0x00, 0}, {0x97, 0x06, 0}, {0x9D, 0x1A, 0},
+        {0x9F, 0x10, 0}, {0xB4, 0x22, 0}, {0xBE, 0x80, 0}, {0xDB, 0x00, 0},
+        {0xEE, 0x00, 0}, {0x4C, 0x00, 2},
 
         {0x9F, 0x00, 3}, {0x8C, 0x01, 0}, {0x8D, 0x10, 0}, {0x8E, 0x08, 0},
         {0x8F, 0x00, 0}
@@ -742,48 +758,34 @@ static int rtl8187b_init_hw(struct ieee80211_hw *dev)
         int res, i;
         u8 reg;
 
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
-                         RTL818X_EEPROM_CMD_CONFIG);
-
-        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
-        reg |= RTL818X_CONFIG3_ANAPARAM_WRITE | RTL818X_CONFIG3_GNT_SELECT;
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
-        rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
-                          RTL8187B_RTL8225_ANAPARAM2_ON);
-        rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
-                          RTL8187B_RTL8225_ANAPARAM_ON);
-        rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
-                         RTL8187B_RTL8225_ANAPARAM3_ON);
+        rtl8187_set_anaparam(priv, true);
 
+        /* Reset PLL sequence on 8187B. Realtek note: reduces power
+         * consumption about 30 mA */
         rtl818x_iowrite8(priv, (u8 *)0xFF61, 0x10);
         reg = rtl818x_ioread8(priv, (u8 *)0xFF62);
         rtl818x_iowrite8(priv, (u8 *)0xFF62, reg & ~(1 << 5));
         rtl818x_iowrite8(priv, (u8 *)0xFF62, reg | (1 << 5));
 
-        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
-        reg &= ~RTL818X_CONFIG3_ANAPARAM_WRITE;
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
-
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
-                         RTL818X_EEPROM_CMD_NORMAL);
-
         res = rtl8187_cmd_reset(dev);
         if (res)
                 return res;
 
-        rtl818x_iowrite16(priv, (__le16 *)0xFF2D, 0x0FFF);
+        rtl8187_set_anaparam(priv, true);
+
+        /* BRSR (Basic Rate Set Register) on 8187B looks to be the same as
+         * RESP_RATE on 8187L in Realtek sources: each bit should be each
+         * one of the 12 rates, all are enabled */
+        rtl818x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF);
+
         reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
         reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
         rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
-        reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
-        reg |= RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT |
-               RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
-        rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
 
+        /* Auto Rate Fallback Register (ARFR): 1M-54M setting */
         rtl818x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1);
+        rtl818x_iowrite8_idx(priv, (u8 *)0xFFE2, 0x00, 1);
 
-        rtl818x_iowrite16(priv, &priv->map->BEACON_INTERVAL, 100);
-        rtl818x_iowrite16(priv, &priv->map->ATIM_WND, 2);
         rtl818x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1);
 
         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
@@ -811,16 +813,9 @@ static int rtl8187b_init_hw(struct ieee80211_hw *dev)
 
         rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001);
 
+        /* RFSW_CTRL register */
         rtl818x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2);
 
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
-                         RTL818X_EEPROM_CMD_CONFIG);
-        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
-        reg |= RTL818X_CONFIG3_ANAPARAM_WRITE;
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
-                         RTL818X_EEPROM_CMD_NORMAL);
-
         rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
         rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
         rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF);
@@ -929,6 +924,12 @@ static int rtl8187_start(struct ieee80211_hw *dev)
                 priv->rx_conf = reg;
                 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
 
+                reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
+                reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
+                reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
+                reg &= ~RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
+                rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
+
                 rtl818x_iowrite32(priv, &priv->map->TX_CONF,
                                   RTL818X_TX_CONF_HW_SEQNUM |
                                   RTL818X_TX_CONF_DISREQQSIZE |
@@ -1002,6 +1003,7 @@ static void rtl8187_stop(struct ieee80211_hw *dev)
         rtl818x_iowrite8(priv, &priv->map->CMD, reg);
 
         priv->rf->stop(dev);
+        rtl8187_set_anaparam(priv, false);
 
         rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
         reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
diff --git a/drivers/net/wireless/rtl818x/rtl8187_leds.c b/drivers/net/wireless/rtl818x/rtl8187/leds.c
index 4637337d5ce6..2e0de2f5f0f9 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_leds.c
+++ b/drivers/net/wireless/rtl818x/rtl8187/leds.c
@@ -20,7 +20,7 @@
 #include <linux/eeprom_93cx6.h>
 
 #include "rtl8187.h"
-#include "rtl8187_leds.h"
+#include "leds.h"
 
 static void led_turn_on(struct work_struct *work)
 {
diff --git a/drivers/net/wireless/rtl818x/rtl8187_leds.h b/drivers/net/wireless/rtl818x/rtl8187/leds.h
index d743c96d4a20..d743c96d4a20 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_leds.h
+++ b/drivers/net/wireless/rtl818x/rtl8187/leds.h
diff --git a/drivers/net/wireless/rtl818x/rtl8187_rfkill.c b/drivers/net/wireless/rtl818x/rtl8187/rfkill.c
index 03555e1e0cab..34116719974a 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_rfkill.c
+++ b/drivers/net/wireless/rtl818x/rtl8187/rfkill.c
@@ -18,7 +18,7 @@
 #include <net/mac80211.h>
 
 #include "rtl8187.h"
-#include "rtl8187_rfkill.h"
+#include "rfkill.h"
 
 static bool rtl8187_is_radio_enabled(struct rtl8187_priv *priv)
 {
diff --git a/drivers/net/wireless/rtl818x/rtl8187_rfkill.h b/drivers/net/wireless/rtl818x/rtl8187/rfkill.h
index e12575e96d11..e12575e96d11 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_rfkill.h
+++ b/drivers/net/wireless/rtl818x/rtl8187/rfkill.h
diff --git a/drivers/net/wireless/rtl818x/rtl8187.h b/drivers/net/wireless/rtl818x/rtl8187/rtl8187.h
index 98878160a65a..0d7b1423f77b 100644
--- a/drivers/net/wireless/rtl818x/rtl8187.h
+++ b/drivers/net/wireless/rtl818x/rtl8187/rtl8187.h
@@ -16,7 +16,7 @@
 #define RTL8187_H
 
 #include "rtl818x.h"
-#include "rtl8187_leds.h"
+#include "leds.h"
 
 #define RTL8187_EEPROM_TXPWR_BASE       0x05
 #define RTL8187_EEPROM_MAC_ADDR         0x07
diff --git a/drivers/net/wireless/rtl818x/rtl8187_rtl8225.c b/drivers/net/wireless/rtl818x/rtl8187/rtl8225.c
index 97eebdcf7eb9..908903f721f5 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_rtl8225.c
+++ b/drivers/net/wireless/rtl818x/rtl8187/rtl8225.c
@@ -21,7 +21,7 @@
 #include <net/mac80211.h>
 
 #include "rtl8187.h"
-#include "rtl8187_rtl8225.h"
+#include "rtl8225.h"
 
 static void rtl8225_write_bitbang(struct ieee80211_hw *dev, u8 addr, u16 data)
 {
@@ -898,29 +898,7 @@ static void rtl8225z2_b_rf_init(struct ieee80211_hw *dev)
 
 static void rtl8225_rf_stop(struct ieee80211_hw *dev)
 {
-        u8 reg;
-        struct rtl8187_priv *priv = dev->priv;
-
         rtl8225_write(dev, 0x4, 0x1f);
-
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
-        reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
-        if (!priv->is_rtl8187b) {
-                rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
-                                  RTL8187_RTL8225_ANAPARAM2_OFF);
-                rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
-                                  RTL8187_RTL8225_ANAPARAM_OFF);
-        } else {
-                rtl818x_iowrite32(priv, &priv->map->ANAPARAM2,
-                                  RTL8187B_RTL8225_ANAPARAM2_OFF);
-                rtl818x_iowrite32(priv, &priv->map->ANAPARAM,
-                                  RTL8187B_RTL8225_ANAPARAM_OFF);
-                rtl818x_iowrite8(priv, &priv->map->ANAPARAM3,
-                                  RTL8187B_RTL8225_ANAPARAM3_OFF);
-        }
-        rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
-        rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
 }
 
 static void rtl8225_rf_set_channel(struct ieee80211_hw *dev,
diff --git a/drivers/net/wireless/rtl818x/rtl8187_rtl8225.h b/drivers/net/wireless/rtl818x/rtl8187/rtl8225.h
index 20c5b6ead0f6..20c5b6ead0f6 100644
--- a/drivers/net/wireless/rtl818x/rtl8187_rtl8225.h
+++ b/drivers/net/wireless/rtl818x/rtl8187/rtl8225.h
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
new file mode 100644
index 000000000000..7f6573f7f470
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -0,0 +1,15 @@
+config RTL8192CE
+        tristate "Realtek RTL8192CE/RTL8188SE Wireless Network Adapter"
+        depends on MAC80211 && EXPERIMENTAL
+        select FW_LOADER
+        select RTLWIFI
+        ---help---
+        This is the driver for Realtek RTL8192CE/RTL8188CE 802.11n PCIe
+        wireless network adapters.
+
+        If you choose to build it as a module, it will be called rtl8192ce
+
+config RTLWIFI
+        tristate
+        depends on RTL8192CE
+        default m
diff --git a/drivers/net/wireless/rtlwifi/Makefile b/drivers/net/wireless/rtlwifi/Makefile
new file mode 100644
index 000000000000..2a7a4384f8ee
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/Makefile
@@ -0,0 +1,13 @@
+obj-$(CONFIG_RTLWIFI)           += rtlwifi.o
+rtlwifi-objs    :=              \
+                base.o          \
+                cam.o           \
+                core.o          \
+                debug.o         \
+                efuse.o         \
+                pci.o           \
+                ps.o            \
+                rc.o            \
+                regd.o
+
+obj-$(CONFIG_RTL8192CE)         += rtl8192ce/
diff --git a/drivers/net/wireless/rtlwifi/base.c b/drivers/net/wireless/rtlwifi/base.c
new file mode 100644
index 000000000000..cf0b73e51fc2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/base.c
@@ -0,0 +1,956 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include <linux/ip.h>
+#include "wifi.h"
+#include "rc.h"
+#include "base.h"
+#include "efuse.h"
+#include "cam.h"
+#include "ps.h"
+#include "regd.h"
+
+/*
+ *NOTICE!!!: This file will be very big, we hsould
+ *keep it clear under follwing roles:
+ *
+ *This file include follwing part, so, if you add new
+ *functions into this file, please check which part it
+ *should includes. or check if you should add new part
+ *for this file:
+ *
+ *1) mac80211 init functions
+ *2) tx information functions
+ *3) functions called by core.c
+ *4) wq & timer callback functions
+ *5) frame process functions
+ *6) sysfs functions
+ *7) ...
+ */
+
+/*********************************************************
+ *
+ * mac80211 init functions
+ *
+ *********************************************************/
+static struct ieee80211_channel rtl_channeltable[] = {
+        {.center_freq = 2412, .hw_value = 1,},
+        {.center_freq = 2417, .hw_value = 2,},
+        {.center_freq = 2422, .hw_value = 3,},
+        {.center_freq = 2427, .hw_value = 4,},
+        {.center_freq = 2432, .hw_value = 5,},
+        {.center_freq = 2437, .hw_value = 6,},
+        {.center_freq = 2442, .hw_value = 7,},
+        {.center_freq = 2447, .hw_value = 8,},
+        {.center_freq = 2452, .hw_value = 9,},
+        {.center_freq = 2457, .hw_value = 10,},
+        {.center_freq = 2462, .hw_value = 11,},
+        {.center_freq = 2467, .hw_value = 12,},
+        {.center_freq = 2472, .hw_value = 13,},
+        {.center_freq = 2484, .hw_value = 14,},
+};
+
+static struct ieee80211_rate rtl_ratetable[] = {
+        {.bitrate = 10, .hw_value = 0x00,},
+        {.bitrate = 20, .hw_value = 0x01,},
+        {.bitrate = 55, .hw_value = 0x02,},
+        {.bitrate = 110, .hw_value = 0x03,},
+        {.bitrate = 60, .hw_value = 0x04,},
+        {.bitrate = 90, .hw_value = 0x05,},
+        {.bitrate = 120, .hw_value = 0x06,},
+        {.bitrate = 180, .hw_value = 0x07,},
+        {.bitrate = 240, .hw_value = 0x08,},
+        {.bitrate = 360, .hw_value = 0x09,},
+        {.bitrate = 480, .hw_value = 0x0a,},
+        {.bitrate = 540, .hw_value = 0x0b,},
+};
+
+static const struct ieee80211_supported_band rtl_band_2ghz = {
+        .band = IEEE80211_BAND_2GHZ,
+
+        .channels = rtl_channeltable,
+        .n_channels = ARRAY_SIZE(rtl_channeltable),
+
+        .bitrates = rtl_ratetable,
+        .n_bitrates = ARRAY_SIZE(rtl_ratetable),
+
+        .ht_cap = {0},
+};
+
+static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw,
+                                  struct ieee80211_sta_ht_cap *ht_cap)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        ht_cap->ht_supported = true;
+        ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
+            IEEE80211_HT_CAP_SGI_40 |
+            IEEE80211_HT_CAP_SGI_20 |
+            IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU;
+
+        /*
+         *Maximum length of AMPDU that the STA can receive.
+         *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets)
+         */
+        ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
+
+        /*Minimum MPDU start spacing , */
+        ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
+
+        ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
+
+        /*
+         *hw->wiphy->bands[IEEE80211_BAND_2GHZ]
+         *base on ant_num
+         *rx_mask: RX mask
+         *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7
+         *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15
+         *if rx_ant >=3 rx_mask[2]=0xff;
+         *if BW_40 rx_mask[4]=0x01;
+         *highest supported RX rate
+         */
+        if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_2T2R) {
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("1T2R or 2T2R\n"));
+
+                ht_cap->mcs.rx_mask[0] = 0xFF;
+                ht_cap->mcs.rx_mask[1] = 0xFF;
+                ht_cap->mcs.rx_mask[4] = 0x01;
+
+                ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15;
+        } else if (get_rf_type(rtlphy) == RF_1T1R) {
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("1T1R\n"));
+
+                ht_cap->mcs.rx_mask[0] = 0xFF;
+                ht_cap->mcs.rx_mask[1] = 0x00;
+                ht_cap->mcs.rx_mask[4] = 0x01;
+
+                ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7;
+        }
+}
+
+static void _rtl_init_mac80211(struct ieee80211_hw *hw)
+{
+        struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        struct ieee80211_supported_band *sband;
+
+        /* <1> use  mac->bands as mem for hw->wiphy->bands */
+        sband = &(rtlmac->bands[IEEE80211_BAND_2GHZ]);
+
+        /*
+         * <2> set hw->wiphy->bands[IEEE80211_BAND_2GHZ]
+         * to default value(1T1R)
+         */
+        memcpy(&(rtlmac->bands[IEEE80211_BAND_2GHZ]), &rtl_band_2ghz,
+               sizeof(struct ieee80211_supported_band));
+
+        /* <3> init ht cap base on ant_num */
+        _rtl_init_hw_ht_capab(hw, &sband->ht_cap);
+
+        /* <4> set mac->sband to wiphy->sband */
+        hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
+
+        /* <5> set hw caps */
+        hw->flags = IEEE80211_HW_SIGNAL_DBM |
+            IEEE80211_HW_RX_INCLUDES_FCS |
+            IEEE80211_HW_BEACON_FILTER | IEEE80211_HW_AMPDU_AGGREGATION | /*PS*/
+            /*IEEE80211_HW_SUPPORTS_PS | */
+            /*IEEE80211_HW_PS_NULLFUNC_STACK | */
+            /*IEEE80211_HW_SUPPORTS_DYNAMIC_PS | */
+            IEEE80211_HW_REPORTS_TX_ACK_STATUS | 0;
+
+        hw->wiphy->interface_modes =
+            BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC);
+
+        hw->wiphy->rts_threshold = 2347;
+
+        hw->queues = AC_MAX;
+        hw->extra_tx_headroom = RTL_TX_HEADER_SIZE;
+
+        /* TODO: Correct this value for our hw */
+        /* TODO: define these hard code value */
+        hw->channel_change_time = 100;
+        hw->max_listen_interval = 5;
+        hw->max_rate_tries = 4;
+        /* hw->max_rates = 1; */
+
+        /* <6> mac address */
+        if (is_valid_ether_addr(rtlefuse->dev_addr)) {
+                SET_IEEE80211_PERM_ADDR(hw, rtlefuse->dev_addr);
+        } else {
+                u8 rtlmac[] = { 0x00, 0xe0, 0x4c, 0x81, 0x92, 0x00 };
+                get_random_bytes((rtlmac + (ETH_ALEN - 1)), 1);
+                SET_IEEE80211_PERM_ADDR(hw, rtlmac);
+        }
+
+}
+
+static void _rtl_init_deferred_work(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        /* <1> timer */
+        init_timer(&rtlpriv->works.watchdog_timer);
+        setup_timer(&rtlpriv->works.watchdog_timer,
+                    rtl_watch_dog_timer_callback, (unsigned long)hw);
+
+        /* <2> work queue */
+        rtlpriv->works.hw = hw;
+        rtlpriv->works.rtl_wq = alloc_workqueue(rtlpriv->cfg->name, 0, 0);
+        INIT_DELAYED_WORK(&rtlpriv->works.watchdog_wq,
+                          (void *)rtl_watchdog_wq_callback);
+        INIT_DELAYED_WORK(&rtlpriv->works.ips_nic_off_wq,
+                          (void *)rtl_ips_nic_off_wq_callback);
+
+}
+
+void rtl_deinit_deferred_work(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        del_timer_sync(&rtlpriv->works.watchdog_timer);
+
+        cancel_delayed_work(&rtlpriv->works.watchdog_wq);
+        cancel_delayed_work(&rtlpriv->works.ips_nic_off_wq);
+}
+
+void rtl_init_rfkill(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        bool radio_state;
+        bool blocked;
+        u8 valid = 0;
+
+        radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
+
+        /*set init state to that of switch */
+        rtlpriv->rfkill.rfkill_state = radio_state;
+        printk(KERN_INFO "rtlwifi: wireless switch is %s\n",
+               rtlpriv->rfkill.rfkill_state ? "on" : "off");
+
+        if (valid) {
+                rtlpriv->rfkill.rfkill_state = radio_state;
+
+                blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1;
+                wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
+        }
+
+        wiphy_rfkill_start_polling(hw->wiphy);
+}
+
+void rtl_deinit_rfkill(struct ieee80211_hw *hw)
+{
+        wiphy_rfkill_stop_polling(hw->wiphy);
+}
+
+int rtl_init_core(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
+
+        /* <1> init mac80211 */
+        _rtl_init_mac80211(hw);
+        rtlmac->hw = hw;
+
+        /* <2> rate control register */
+        if (rtl_rate_control_register()) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("rtl: Unable to register rtl_rc,"
+                          "use default RC !!\n"));
+        } else {
+                hw->rate_control_algorithm = "rtl_rc";
+        }
+
+        /*
+         * <3> init CRDA must come after init
+         * mac80211 hw  in _rtl_init_mac80211.
+         */
+        if (rtl_regd_init(hw, rtl_reg_notifier)) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("REGD init failed\n"));
+                return 1;
+        } else {
+                /* CRDA regd hint must after init CRDA */
+                if (regulatory_hint(hw->wiphy, rtlpriv->regd.alpha2)) {
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                 ("regulatory_hint fail\n"));
+                }
+        }
+
+        /* <4> locks */
+        mutex_init(&rtlpriv->locks.conf_mutex);
+        spin_lock_init(&rtlpriv->locks.ips_lock);
+        spin_lock_init(&rtlpriv->locks.irq_th_lock);
+        spin_lock_init(&rtlpriv->locks.h2c_lock);
+        spin_lock_init(&rtlpriv->locks.rf_ps_lock);
+        spin_lock_init(&rtlpriv->locks.rf_lock);
+        spin_lock_init(&rtlpriv->locks.lps_lock);
+
+        rtlmac->link_state = MAC80211_NOLINK;
+
+        /* <5> init deferred work */
+        _rtl_init_deferred_work(hw);
+
+        return 0;
+}
+
+void rtl_deinit_core(struct ieee80211_hw *hw)
+{
+         /*RC*/
+        rtl_rate_control_unregister();
+}
+
+void rtl_init_rx_config(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *) (&mac->rx_conf));
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_MGT_FILTER,
+                                      (u8 *) (&mac->rx_mgt_filter));
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_CTRL_FILTER,
+                                      (u8 *) (&mac->rx_ctrl_filter));
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_DATA_FILTER,
+                                      (u8 *) (&mac->rx_data_filter));
+}
+
+/*********************************************************
+ *
+ * tx information functions
+ *
+ *********************************************************/
+static void _rtl_qurey_shortpreamble_mode(struct ieee80211_hw *hw,
+                                          struct rtl_tcb_desc *tcb_desc,
+                                          struct ieee80211_tx_info *info)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 rate_flag = info->control.rates[0].flags;
+
+        tcb_desc->use_shortpreamble = false;
+
+        /* 1M can only use Long Preamble. 11B spec */
+        if (tcb_desc->hw_rate == rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M])
+                return;
+        else if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
+                tcb_desc->use_shortpreamble = true;
+
+        return;
+}
+
+static void _rtl_query_shortgi(struct ieee80211_hw *hw,
+                               struct rtl_tcb_desc *tcb_desc,
+                               struct ieee80211_tx_info *info)
+{
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u8 rate_flag = info->control.rates[0].flags;
+
+        tcb_desc->use_shortgi = false;
+
+        if (!mac->ht_enable)
+                return;
+
+        if (!mac->sgi_40 && !mac->sgi_20)
+                return;
+
+        if ((mac->bw_40 == true) && mac->sgi_40)
+                tcb_desc->use_shortgi = true;
+        else if ((mac->bw_40 == false) && mac->sgi_20)
+                tcb_desc->use_shortgi = true;
+
+        if (!(rate_flag & IEEE80211_TX_RC_SHORT_GI))
+                tcb_desc->use_shortgi = false;
+
+}
+
+static void _rtl_query_protection_mode(struct ieee80211_hw *hw,
+                                       struct rtl_tcb_desc *tcb_desc,
+                                       struct ieee80211_tx_info *info)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 rate_flag = info->control.rates[0].flags;
+
+        /* Common Settings */
+        tcb_desc->b_rts_stbc = false;
+        tcb_desc->b_cts_enable = false;
+        tcb_desc->rts_sc = 0;
+        tcb_desc->b_rts_bw = false;
+        tcb_desc->b_rts_use_shortpreamble = false;
+        tcb_desc->b_rts_use_shortgi = false;
+
+        if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) {
+                /* Use CTS-to-SELF in protection mode. */
+                tcb_desc->b_rts_enable = true;
+                tcb_desc->b_cts_enable = true;
+                tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
+        } else if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
+                /* Use RTS-CTS in protection mode. */
+                tcb_desc->b_rts_enable = true;
+                tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
+        }
+
+}
+
+static void _rtl_txrate_selectmode(struct ieee80211_hw *hw,
+                                   struct rtl_tcb_desc *tcb_desc)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        if (!tcb_desc->disable_ratefallback || !tcb_desc->use_driver_rate) {
+                if (mac->opmode == NL80211_IFTYPE_STATION)
+                        tcb_desc->ratr_index = 0;
+                else if (mac->opmode == NL80211_IFTYPE_ADHOC) {
+                        if (tcb_desc->b_multicast || tcb_desc->b_broadcast) {
+                                tcb_desc->hw_rate =
+                                    rtlpriv->cfg->maps[RTL_RC_CCK_RATE2M];
+                                tcb_desc->use_driver_rate = 1;
+                        } else {
+                                /* TODO */
+                        }
+                }
+        }
+
+        if (rtlpriv->dm.b_useramask) {
+                /* TODO we will differentiate adhoc and station futrue  */
+                tcb_desc->mac_id = 0;
+
+                if ((mac->mode == WIRELESS_MODE_N_24G) ||
+                    (mac->mode == WIRELESS_MODE_N_5G)) {
+                        tcb_desc->ratr_index = RATR_INX_WIRELESS_NGB;
+                } else if (mac->mode & WIRELESS_MODE_G) {
+                        tcb_desc->ratr_index = RATR_INX_WIRELESS_GB;
+                } else if (mac->mode & WIRELESS_MODE_B) {
+                        tcb_desc->ratr_index = RATR_INX_WIRELESS_B;
+                }
+        }
+
+}
+
+static void _rtl_query_bandwidth_mode(struct ieee80211_hw *hw,
+                                      struct rtl_tcb_desc *tcb_desc)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        tcb_desc->b_packet_bw = false;
+
+        if (!mac->bw_40 || !mac->ht_enable)
+                return;
+
+        if (tcb_desc->b_multicast || tcb_desc->b_broadcast)
+                return;
+
+        /*use legency rate, shall use 20MHz */
+        if (tcb_desc->hw_rate <= rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M])
+                return;
+
+        tcb_desc->b_packet_bw = true;
+}
+
+static u8 _rtl_get_highest_n_rate(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        u8 hw_rate;
+
+        if (get_rf_type(rtlphy) == RF_2T2R)
+                hw_rate = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS15];
+        else
+                hw_rate = rtlpriv->cfg->maps[RTL_RC_HT_RATEMCS7];
+
+        return hw_rate;
+}
+
+void rtl_get_tcb_desc(struct ieee80211_hw *hw,
+                      struct ieee80211_tx_info *info,
+                      struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+        struct ieee80211_rate *txrate;
+        u16 fc = le16_to_cpu(hdr->frame_control);
+
+        memset(tcb_desc, 0, sizeof(struct rtl_tcb_desc));
+
+        if (ieee80211_is_data(fc)) {
+                txrate = ieee80211_get_tx_rate(hw, info);
+                tcb_desc->hw_rate = txrate->hw_value;
+
+                /*
+                 *we set data rate RTL_RC_CCK_RATE1M
+                 *in rtl_rc.c   if skb is special data or
+                 *mgt which need low data rate.
+                 */
+
+                /*
+                 *So tcb_desc->hw_rate is just used for
+                 *special data and mgt frames
+                 */
+                if (tcb_desc->hw_rate < rtlpriv->cfg->maps[RTL_RC_CCK_RATE11M]) {
+                        tcb_desc->use_driver_rate = true;
+                        tcb_desc->ratr_index = 7;
+
+                        tcb_desc->hw_rate =
+                            rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M];
+                        tcb_desc->disable_ratefallback = 1;
+                } else {
+                        /*
+                         *because hw will nerver use hw_rate
+                         *when tcb_desc->use_driver_rate = false
+                         *so we never set highest N rate here,
+                         *and N rate will all be controled by FW
+                         *when tcb_desc->use_driver_rate = false
+                         */
+                        if (rtlmac->ht_enable) {
+                                tcb_desc->hw_rate = _rtl_get_highest_n_rate(hw);
+                        } else {
+                                if (rtlmac->mode == WIRELESS_MODE_B) {
+                                        tcb_desc->hw_rate =
+                                           rtlpriv->cfg->maps[RTL_RC_CCK_RATE11M];
+                                } else {
+                                        tcb_desc->hw_rate =
+                                           rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M];
+                                }
+                        }
+                }
+
+                if (is_multicast_ether_addr(ieee80211_get_DA(hdr)))
+                        tcb_desc->b_multicast = 1;
+                else if (is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
+                        tcb_desc->b_broadcast = 1;
+
+                _rtl_txrate_selectmode(hw, tcb_desc);
+                _rtl_query_bandwidth_mode(hw, tcb_desc);
+                _rtl_qurey_shortpreamble_mode(hw, tcb_desc, info);
+                _rtl_query_shortgi(hw, tcb_desc, info);
+                _rtl_query_protection_mode(hw, tcb_desc, info);
+        } else {
+                tcb_desc->use_driver_rate = true;
+                tcb_desc->ratr_index = 7;
+                tcb_desc->disable_ratefallback = 1;
+                tcb_desc->mac_id = 0;
+
+                tcb_desc->hw_rate = rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M];
+        }
+}
+EXPORT_SYMBOL(rtl_get_tcb_desc);
+
+bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+        u16 fc = le16_to_cpu(hdr->frame_control);
+
+        if (ieee80211_is_auth(fc)) {
+                RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
+                rtl_ips_nic_on(hw);
+
+                mac->link_state = MAC80211_LINKING;
+        }
+
+        return true;
+}
+
+bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
+{
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u16 fc = le16_to_cpu(hdr->frame_control);
+        u8 *act = (u8 *) (((u8 *) skb->data + MAC80211_3ADDR_LEN));
+        u8 category;
+
+        if (!ieee80211_is_action(fc))
+                return true;
+
+        category = *act;
+        act++;
+        switch (category) {
+        case ACT_CAT_BA:
+                switch (*act) {
+                case ACT_ADDBAREQ:
+                        if (mac->act_scanning)
+                                return false;
+
+                        RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
+                                 ("%s ACT_ADDBAREQ From :" MAC_FMT "\n",
+                                  is_tx ? "Tx" : "Rx", MAC_ARG(hdr->addr2)));
+                        break;
+                case ACT_ADDBARSP:
+                        RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
+                                 ("%s ACT_ADDBARSP From :" MAC_FMT "\n",
+                                  is_tx ? "Tx" : "Rx", MAC_ARG(hdr->addr2)));
+                        break;
+                case ACT_DELBA:
+                        RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
+                                 ("ACT_ADDBADEL From :" MAC_FMT "\n",
+                                  MAC_ARG(hdr->addr2)));
+                        break;
+                }
+                break;
+        default:
+                break;
+        }
+
+        return true;
+}
+
+/*should call before software enc*/
+u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        u16 fc = le16_to_cpu(hdr->frame_control);
+        u16 ether_type;
+        u8 mac_hdr_len = ieee80211_get_hdrlen_from_skb(skb);
+        const struct iphdr *ip;
+
+        if (!ieee80211_is_data(fc))
+                goto end;
+
+        if (ieee80211_is_nullfunc(fc))
+                return true;
+
+        ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
+                              SNAP_SIZE + PROTOC_TYPE_SIZE);
+        ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
+        ether_type = ntohs(ether_type);
+
+        if (ETH_P_IP == ether_type) {
+                if (IPPROTO_UDP == ip->protocol) {
+                        struct udphdr *udp = (struct udphdr *)((u8 *) ip +
+                                                               (ip->ihl << 2));
+                        if (((((u8 *) udp)[1] == 68) &&
+                             (((u8 *) udp)[3] == 67)) ||
+                            ((((u8 *) udp)[1] == 67) &&
+                             (((u8 *) udp)[3] == 68))) {
+                                /*
+                                 * 68 : UDP BOOTP client
+                                 * 67 : UDP BOOTP server
+                                 */
+                                RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV),
+                                         DBG_DMESG, ("dhcp %s !!\n",
+                                                     (is_tx) ? "Tx" : "Rx"));
+
+                                if (is_tx) {
+                                        rtl_lps_leave(hw);
+                                        ppsc->last_delaylps_stamp_jiffies =
+                                            jiffies;
+                                }
+
+                                return true;
+                        }
+                }
+        } else if (ETH_P_ARP == ether_type) {
+                if (is_tx) {
+                        rtl_lps_leave(hw);
+                        ppsc->last_delaylps_stamp_jiffies = jiffies;
+                }
+
+                return true;
+        } else if (ETH_P_PAE == ether_type) {
+                RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG,
+                         ("802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx"));
+
+                if (is_tx) {
+                        rtl_lps_leave(hw);
+                        ppsc->last_delaylps_stamp_jiffies = jiffies;
+                }
+
+                return true;
+        } else if (0x86DD == ether_type) {
+                return true;
+        }
+
+end:
+        return false;
+}
+
+/*********************************************************
+ *
+ * functions called by core.c
+ *
+ *********************************************************/
+int rtl_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra, u16 tid, u16 *ssn)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_tid_data *tid_data;
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG,
+                 ("on ra = %pM tid = %d\n", ra, tid));
+
+        if (unlikely(tid >= MAX_TID_COUNT))
+                return -EINVAL;
+
+        if (mac->tids[tid].agg.agg_state != RTL_AGG_OFF) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Start AGG when state is not RTL_AGG_OFF !\n"));
+                return -ENXIO;
+        }
+
+        tid_data = &mac->tids[tid];
+        *ssn = SEQ_TO_SN(tid_data->seq_number);
+
+        RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG,
+                 ("HW queue is empty tid:%d\n", tid));
+        tid_data->agg.agg_state = RTL_AGG_ON;
+
+        ieee80211_start_tx_ba_cb_irqsafe(mac->vif, ra, tid);
+
+        return 0;
+}
+
+int rtl_tx_agg_stop(struct ieee80211_hw *hw, const u8 * ra, u16 tid)
+{
+        int ssn = -1;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_tid_data *tid_data;
+
+        if (!ra) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("ra = NULL\n"));
+                return -EINVAL;
+        }
+
+        if (unlikely(tid >= MAX_TID_COUNT))
+                return -EINVAL;
+
+        if (mac->tids[tid].agg.agg_state != RTL_AGG_ON)
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Stopping AGG while state not ON or starting\n"));
+
+        tid_data = &mac->tids[tid];
+        ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
+
+        mac->tids[tid].agg.agg_state = RTL_AGG_OFF;
+
+        ieee80211_stop_tx_ba_cb_irqsafe(mac->vif, ra, tid);
+
+        return 0;
+}
+
+/*********************************************************
+ *
+ * wq & timer callback functions
+ *
+ *********************************************************/
+void rtl_watchdog_wq_callback(void *data)
+{
+        struct rtl_works *rtlworks = container_of_dwork_rtl(data,
+                                                            struct rtl_works,
+                                                            watchdog_wq);
+        struct ieee80211_hw *hw = rtlworks->hw;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        bool b_busytraffic = false;
+        bool b_higher_busytraffic = false;
+        bool b_higher_busyrxtraffic = false;
+        bool b_higher_busytxtraffic = false;
+
+        u8 idx = 0;
+        u32 rx_cnt_inp4eriod = 0;
+        u32 tx_cnt_inp4eriod = 0;
+        u32 aver_rx_cnt_inperiod = 0;
+        u32 aver_tx_cnt_inperiod = 0;
+
+        bool benter_ps = false;
+
+        if (is_hal_stop(rtlhal))
+                return;
+
+        /* <1> Determine if action frame is allowed */
+        if (mac->link_state > MAC80211_NOLINK) {
+                if (mac->cnt_after_linked < 20)
+                        mac->cnt_after_linked++;
+        } else {
+                mac->cnt_after_linked = 0;
+        }
+
+        /* <2> DM */
+        rtlpriv->cfg->ops->dm_watchdog(hw);
+
+        /*
+         *<3> to check if traffic busy, if
+         * busytraffic we don't change channel
+         */
+        if (mac->link_state >= MAC80211_LINKED) {
+
+                /* (1) get aver_rx_cnt_inperiod & aver_tx_cnt_inperiod */
+                for (idx = 0; idx <= 2; idx++) {
+                        rtlpriv->link_info.num_rx_in4period[idx] =
+                            rtlpriv->link_info.num_rx_in4period[idx + 1];
+                        rtlpriv->link_info.num_tx_in4period[idx] =
+                            rtlpriv->link_info.num_tx_in4period[idx + 1];
+                }
+                rtlpriv->link_info.num_rx_in4period[3] =
+                    rtlpriv->link_info.num_rx_inperiod;
+                rtlpriv->link_info.num_tx_in4period[3] =
+                    rtlpriv->link_info.num_tx_inperiod;
+                for (idx = 0; idx <= 3; idx++) {
+                        rx_cnt_inp4eriod +=
+                            rtlpriv->link_info.num_rx_in4period[idx];
+                        tx_cnt_inp4eriod +=
+                            rtlpriv->link_info.num_tx_in4period[idx];
+                }
+                aver_rx_cnt_inperiod = rx_cnt_inp4eriod / 4;
+                aver_tx_cnt_inperiod = tx_cnt_inp4eriod / 4;
+
+                /* (2) check traffic busy */
+                if (aver_rx_cnt_inperiod > 100 || aver_tx_cnt_inperiod > 100)
+                        b_busytraffic = true;
+
+                /* Higher Tx/Rx data. */
+                if (aver_rx_cnt_inperiod > 4000 ||
+                    aver_tx_cnt_inperiod > 4000) {
+                        b_higher_busytraffic = true;
+
+                        /* Extremely high Rx data. */
+                        if (aver_rx_cnt_inperiod > 5000)
+                                b_higher_busyrxtraffic = true;
+                        else
+                                b_higher_busytxtraffic = false;
+                }
+
+                if (((rtlpriv->link_info.num_rx_inperiod +
+                      rtlpriv->link_info.num_tx_inperiod) > 8) ||
+                    (rtlpriv->link_info.num_rx_inperiod > 2))
+                        benter_ps = false;
+                else
+                        benter_ps = true;
+
+                /* LeisurePS only work in infra mode. */
+                if (benter_ps)
+                        rtl_lps_enter(hw);
+                else
+                        rtl_lps_leave(hw);
+        }
+
+        rtlpriv->link_info.num_rx_inperiod = 0;
+        rtlpriv->link_info.num_tx_inperiod = 0;
+
+        rtlpriv->link_info.b_busytraffic = b_busytraffic;
+        rtlpriv->link_info.b_higher_busytraffic = b_higher_busytraffic;
+        rtlpriv->link_info.b_higher_busyrxtraffic = b_higher_busyrxtraffic;
+
+}
+
+void rtl_watch_dog_timer_callback(unsigned long data)
+{
+        struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        queue_delayed_work(rtlpriv->works.rtl_wq,
+                           &rtlpriv->works.watchdog_wq, 0);
+
+        mod_timer(&rtlpriv->works.watchdog_timer,
+                  jiffies + MSECS(RTL_WATCH_DOG_TIME));
+}
+
+/*********************************************************
+ *
+ * sysfs functions
+ *
+ *********************************************************/
+static ssize_t rtl_show_debug_level(struct device *d,
+                                    struct device_attribute *attr, char *buf)
+{
+        struct ieee80211_hw *hw = dev_get_drvdata(d);
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        return sprintf(buf, "0x%08X\n", rtlpriv->dbg.global_debuglevel);
+}
+
+static ssize_t rtl_store_debug_level(struct device *d,
+                                     struct device_attribute *attr,
+                                     const char *buf, size_t count)
+{
+        struct ieee80211_hw *hw = dev_get_drvdata(d);
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        unsigned long val;
+        int ret;
+
+        ret = strict_strtoul(buf, 0, &val);
+        if (ret) {
+                printk(KERN_DEBUG "%s is not in hex or decimal form.\n", buf);
+        } else {
+                rtlpriv->dbg.global_debuglevel = val;
+                printk(KERN_DEBUG "debuglevel:%x\n",
+                       rtlpriv->dbg.global_debuglevel);
+        }
+
+        return strnlen(buf, count);
+}
+
+static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
+                   rtl_show_debug_level, rtl_store_debug_level);
+
+static struct attribute *rtl_sysfs_entries[] = {
+
+        &dev_attr_debug_level.attr,
+
+        NULL
+};
+
+/*
+ * "name" is folder name witch will be
+ * put in device directory like :
+ * sys/devices/pci0000:00/0000:00:1c.4/
+ * 0000:06:00.0/rtl_sysfs
+ */
+struct attribute_group rtl_attribute_group = {
+        .name = "rtlsysfs",
+        .attrs = rtl_sysfs_entries,
+};
+
+MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
+MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
+MODULE_AUTHOR("Larry Finger     <Larry.FInger@lwfinger.net>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
+
+static int __init rtl_core_module_init(void)
+{
+        return 0;
+}
+
+static void __exit rtl_core_module_exit(void)
+{
+}
+
+module_init(rtl_core_module_init);
+module_exit(rtl_core_module_exit);
diff --git a/drivers/net/wireless/rtlwifi/base.h b/drivers/net/wireless/rtlwifi/base.h
new file mode 100644
index 000000000000..3de5a14745f1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/base.h
@@ -0,0 +1,120 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *****************************************************************************/
+
+#ifndef __RTL_BASE_H__
+#define __RTL_BASE_H__
+
+#define RTL_DUMMY_OFFSET        0
+#define RTL_DUMMY_UNIT          8
+#define RTL_TX_DUMMY_SIZE       (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
+#define RTL_TX_DESC_SIZE        32
+#define RTL_TX_HEADER_SIZE      (RTL_TX_DESC_SIZE + RTL_TX_DUMMY_SIZE)
+
+#define HT_AMSDU_SIZE_4K        3839
+#define HT_AMSDU_SIZE_8K        7935
+
+#define MAX_BIT_RATE_40MHZ_MCS15        300     /* Mbps */
+#define MAX_BIT_RATE_40MHZ_MCS7         150     /* Mbps */
+
+#define RTL_RATE_COUNT_LEGACY           12
+#define RTL_CHANNEL_COUNT               14
+
+#define FRAME_OFFSET_FRAME_CONTROL      0
+#define FRAME_OFFSET_DURATION           2
+#define FRAME_OFFSET_ADDRESS1           4
+#define FRAME_OFFSET_ADDRESS2           10
+#define FRAME_OFFSET_ADDRESS3           16
+#define FRAME_OFFSET_SEQUENCE           22
+#define FRAME_OFFSET_ADDRESS4           24
+
+#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val)         \
+        WRITEEF2BYTE(_hdr, _val)
+#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val)      \
+        WRITEEF1BYTE(_hdr, _val)
+#define SET_80211_HDR_PWR_MGNT(_hdr, _val)              \
+        SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
+#define SET_80211_HDR_TO_DS(_hdr, _val)                 \
+        SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
+
+#define SET_80211_PS_POLL_AID(_hdr, _val)               \
+        WRITEEF2BYTE(((u8 *)(_hdr)) + 2, _val)
+#define SET_80211_PS_POLL_BSSID(_hdr, _val)             \
+        CP_MACADDR(((u8 *)(_hdr)) + 4, (u8 *)(_val))
+#define SET_80211_PS_POLL_TA(_hdr, _val)                \
+        CP_MACADDR(((u8 *)(_hdr)) + 10, (u8 *)(_val))
+
+#define SET_80211_HDR_DURATION(_hdr, _val)      \
+        WRITEEF2BYTE((u8 *)(_hdr)+FRAME_OFFSET_DURATION, _val)
+#define SET_80211_HDR_ADDRESS1(_hdr, _val)      \
+        CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8*)(_val))
+#define SET_80211_HDR_ADDRESS2(_hdr, _val)      \
+        CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS2, (u8 *)(_val))
+#define SET_80211_HDR_ADDRESS3(_hdr, _val)      \
+        CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS3, (u8 *)(_val))
+#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val)  \
+        WRITEEF2BYTE((u8 *)(_hdr)+FRAME_OFFSET_SEQUENCE, _val)
+
+#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val)      \
+        WRITEEF4BYTE(((u8 *)(__phdr)) + 24, __val)
+#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
+        WRITEEF4BYTE(((u8 *)(__phdr)) + 28, __val)
+#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
+        WRITEEF2BYTE(((u8 *)(__phdr)) + 32, __val)
+#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr)    \
+        READEF2BYTE(((u8 *)(__phdr)) + 34)
+#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
+        WRITEEF2BYTE(((u8 *)(__phdr)) + 34, __val)
+#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
+        SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
+        (GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
+
+int rtl_init_core(struct ieee80211_hw *hw);
+void rtl_deinit_core(struct ieee80211_hw *hw);
+void rtl_init_rx_config(struct ieee80211_hw *hw);
+void rtl_init_rfkill(struct ieee80211_hw *hw);
+void rtl_deinit_rfkill(struct ieee80211_hw *hw);
+
+void rtl_watch_dog_timer_callback(unsigned long data);
+void rtl_deinit_deferred_work(struct ieee80211_hw *hw);
+
+bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
+bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb);
+u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx);
+
+void rtl_watch_dog_timer_callback(unsigned long data);
+int rtl_tx_agg_start(struct ieee80211_hw *hw, const u8 *ra,
+                     u16 tid, u16 *ssn);
+int rtl_tx_agg_stop(struct ieee80211_hw *hw, const u8 *ra, u16 tid);
+void rtl_watchdog_wq_callback(void *data);
+
+void rtl_get_tcb_desc(struct ieee80211_hw *hw,
+                      struct ieee80211_tx_info *info,
+                      struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc);
+
+extern struct attribute_group rtl_attribute_group;
+#endif
diff --git a/drivers/net/wireless/rtlwifi/cam.c b/drivers/net/wireless/rtlwifi/cam.c
new file mode 100644
index 000000000000..52c9c1367cac
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/cam.c
@@ -0,0 +1,291 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ *****************************************************************************/
+
+#include "wifi.h"
+#include "cam.h"
+
+void rtl_cam_reset_sec_info(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->sec.use_defaultkey = false;
+        rtlpriv->sec.pairwise_enc_algorithm = NO_ENCRYPTION;
+        rtlpriv->sec.group_enc_algorithm = NO_ENCRYPTION;
+        memset(rtlpriv->sec.key_buf, 0, KEY_BUF_SIZE * MAX_KEY_LEN);
+        memset(rtlpriv->sec.key_len, 0, KEY_BUF_SIZE);
+        rtlpriv->sec.pairwise_key = NULL;
+}
+
+static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no,
+                           u8 *mac_addr, u8 *key_cont_128, u16 us_config)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        u32 target_command;
+        u32 target_content = 0;
+        u8 entry_i;
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("key_cont_128:\n %x:%x:%x:%x:%x:%x\n",
+                  key_cont_128[0], key_cont_128[1],
+                  key_cont_128[2], key_cont_128[3],
+                  key_cont_128[4], key_cont_128[5]));
+
+        for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
+                target_command = entry_i + CAM_CONTENT_COUNT * entry_no;
+                target_command = target_command | BIT(31) | BIT(16);
+
+                if (entry_i == 0) {
+                        target_content = (u32) (*(mac_addr + 0)) << 16 |
+                            (u32) (*(mac_addr + 1)) << 24 | (u32) us_config;
+
+                        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
+                                        target_content);
+                        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
+                                        target_command);
+
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("rtl_cam_program_entry(): "
+                                  "WRITE %x: %x\n",
+                                  rtlpriv->cfg->maps[WCAMI], target_content));
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("The Key ID is %d\n", entry_no));
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("rtl_cam_program_entry(): "
+                                  "WRITE %x: %x\n",
+                                  rtlpriv->cfg->maps[RWCAM], target_command));
+
+                } else if (entry_i == 1) {
+
+                        target_content = (u32) (*(mac_addr + 5)) << 24 |
+                            (u32) (*(mac_addr + 4)) << 16 |
+                            (u32) (*(mac_addr + 3)) << 8 |
+                            (u32) (*(mac_addr + 2));
+
+                        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
+                                        target_content);
+                        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
+                                        target_command);
+
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("rtl_cam_program_entry(): WRITE A4: %x\n",
+                                  target_content));
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("rtl_cam_program_entry(): WRITE A0: %x\n",
+                                  target_command));
+
+                } else {
+
+                        target_content =
+                            (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 3)) <<
+                            24 | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 2))
+                            << 16 |
+                            (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 1)) << 8
+                            | (u32) (*(key_cont_128 + (entry_i * 4 - 8) + 0));
+
+                        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI],
+                                        target_content);
+                        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM],
+                                        target_command);
+                        udelay(100);
+
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("rtl_cam_program_entry(): WRITE A4: %x\n",
+                                  target_content));
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("rtl_cam_program_entry(): WRITE A0: %x\n",
+                                  target_command));
+                }
+        }
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("after set key, usconfig:%x\n", us_config));
+}
+
+u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
+                         u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
+                         u32 ul_default_key, u8 *key_content)
+{
+        u32 us_config;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, "
+                  "ulUseDK=%x MacAddr" MAC_FMT "\n",
+                  ul_entry_idx, ul_key_id, ul_enc_alg,
+                  ul_default_key, MAC_ARG(mac_addr)));
+
+        if (ul_key_id == TOTAL_CAM_ENTRY) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("<=== ulKeyId exceed!\n"));
+                return 0;
+        }
+
+        if (ul_default_key == 1) {
+                us_config = CFG_VALID | ((u16) (ul_enc_alg) << 2);
+        } else {
+                us_config = CFG_VALID | ((ul_enc_alg) << 2) | ul_key_id;
+        }
+
+        rtl_cam_program_entry(hw, ul_entry_idx, mac_addr,
+                              (u8 *) key_content, us_config);
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("<===\n"));
+
+        return 1;
+
+}
+EXPORT_SYMBOL(rtl_cam_add_one_entry);
+
+int rtl_cam_delete_one_entry(struct ieee80211_hw *hw,
+                             u8 *mac_addr, u32 ul_key_id)
+{
+        u32 ul_command;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("key_idx:%d\n", ul_key_id));
+
+        ul_command = ul_key_id * CAM_CONTENT_COUNT;
+        ul_command = ul_command | BIT(31) | BIT(16);
+
+        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0);
+        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("rtl_cam_delete_one_entry(): WRITE A4: %x\n", 0));
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("rtl_cam_delete_one_entry(): WRITE A0: %x\n", ul_command));
+
+        return 0;
+
+}
+EXPORT_SYMBOL(rtl_cam_delete_one_entry);
+
+void rtl_cam_reset_all_entry(struct ieee80211_hw *hw)
+{
+        u32 ul_command;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        ul_command = BIT(31) | BIT(30);
+        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
+}
+EXPORT_SYMBOL(rtl_cam_reset_all_entry);
+
+void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        u32 ul_command;
+        u32 ul_content;
+        u32 ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
+
+        switch (rtlpriv->sec.pairwise_enc_algorithm) {
+        case WEP40_ENCRYPTION:
+                ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
+                break;
+        case WEP104_ENCRYPTION:
+                ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
+                break;
+        case TKIP_ENCRYPTION:
+                ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
+                break;
+        case AESCCMP_ENCRYPTION:
+                ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
+                break;
+        default:
+                ul_enc_algo = rtlpriv->cfg->maps[SEC_CAM_AES];
+        }
+
+        ul_content = (uc_index & 3) | ((u16) (ul_enc_algo) << 2);
+
+        ul_content |= BIT(15);
+        ul_command = CAM_CONTENT_COUNT * uc_index;
+        ul_command = ul_command | BIT(31) | BIT(16);
+
+        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
+        rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("rtl_cam_mark_invalid(): WRITE A4: %x\n", ul_content));
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("rtl_cam_mark_invalid(): WRITE A0: %x\n", ul_command));
+}
+EXPORT_SYMBOL(rtl_cam_mark_invalid);
+
+void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        u32 ul_command;
+        u32 ul_content;
+        u32 ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
+        u8 entry_i;
+
+        switch (rtlpriv->sec.pairwise_enc_algorithm) {
+        case WEP40_ENCRYPTION:
+                ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP40];
+                break;
+        case WEP104_ENCRYPTION:
+                ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_WEP104];
+                break;
+        case TKIP_ENCRYPTION:
+                ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_TKIP];
+                break;
+        case AESCCMP_ENCRYPTION:
+                ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
+                break;
+        default:
+                ul_encalgo = rtlpriv->cfg->maps[SEC_CAM_AES];
+        }
+
+        for (entry_i = 0; entry_i < CAM_CONTENT_COUNT; entry_i++) {
+
+                if (entry_i == 0) {
+                        ul_content =
+                            (uc_index & 0x03) | ((u16) (ul_encalgo) << 2);
+                        ul_content |= BIT(15);
+
+                } else {
+                        ul_content = 0;
+                }
+
+                ul_command = CAM_CONTENT_COUNT * uc_index + entry_i;
+                ul_command = ul_command | BIT(31) | BIT(16);
+
+                rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content);
+                rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command);
+
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
+                         ("rtl_cam_empty_entry(): WRITE A4: %x\n",
+                          ul_content));
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
+                         ("rtl_cam_empty_entry(): WRITE A0: %x\n",
+                          ul_command));
+        }
+
+}
+EXPORT_SYMBOL(rtl_cam_empty_entry);
diff --git a/drivers/net/wireless/rtlwifi/cam.h b/drivers/net/wireless/rtlwifi/cam.h
new file mode 100644
index 000000000000..dd82f057d53d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/cam.h
@@ -0,0 +1,53 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ *****************************************************************************/
+
+#ifndef __RTL_CAM_H_
+#define __RTL_CAM_H_
+
+#define TOTAL_CAM_ENTRY                                 32
+#define CAM_CONTENT_COUNT                               8
+
+#define CFG_DEFAULT_KEY                                 BIT(5)
+#define CFG_VALID                                       BIT(15)
+
+#define PAIRWISE_KEYIDX                                 0
+#define CAM_PAIRWISE_KEY_POSITION               4
+
+#define CAM_CONFIG_USEDK                                1
+#define CAM_CONFIG_NO_USEDK                             0
+
+extern void rtl_cam_reset_all_entry(struct ieee80211_hw *hw);
+extern u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
+                        u32 ul_key_id, u32 ul_entry_idx, u32 ul_enc_alg,
+                        u32 ul_default_key, u8 *key_content);
+int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u8 *mac_addr,
+                        u32 ul_key_id);
+void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index);
+void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index);
+void rtl_cam_reset_sec_info(struct ieee80211_hw *hw);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/core.c b/drivers/net/wireless/rtlwifi/core.c
new file mode 100644
index 000000000000..d6a924a05654
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/core.c
@@ -0,0 +1,1029 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *****************************************************************************/
+
+#include "wifi.h"
+#include "core.h"
+#include "cam.h"
+#include "base.h"
+#include "ps.h"
+
+/*mutex for start & stop is must here. */
+static int rtl_op_start(struct ieee80211_hw *hw)
+{
+        int err = 0;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (!is_hal_stop(rtlhal))
+                return 0;
+        if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
+                return 0;
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+        err = rtlpriv->intf_ops->adapter_start(hw);
+        if (err)
+                goto out;
+        rtl_watch_dog_timer_callback((unsigned long)hw);
+out:
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+        return err;
+}
+
+static void rtl_op_stop(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        if (is_hal_stop(rtlhal))
+                return;
+
+        if (unlikely(ppsc->rfpwr_state == ERFOFF)) {
+                rtl_ips_nic_on(hw);
+                mdelay(1);
+        }
+
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+
+        mac->link_state = MAC80211_NOLINK;
+        memset(mac->bssid, 0, 6);
+
+        /*reset sec info */
+        rtl_cam_reset_sec_info(hw);
+
+        rtl_deinit_deferred_work(hw);
+        rtlpriv->intf_ops->adapter_stop(hw);
+
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+}
+
+static int rtl_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        if (unlikely(is_hal_stop(rtlhal) || ppsc->rfpwr_state != ERFON))
+                goto err_free;
+
+        if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
+                goto err_free;
+
+
+        rtlpriv->intf_ops->adapter_tx(hw, skb);
+
+        return NETDEV_TX_OK;
+
+err_free:
+        dev_kfree_skb_any(skb);
+        return NETDEV_TX_OK;
+}
+
+static int rtl_op_add_interface(struct ieee80211_hw *hw,
+                struct ieee80211_vif *vif)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        int err = 0;
+
+        if (mac->vif) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("vif has been set!! mac->vif = 0x%p\n", mac->vif));
+                return -EOPNOTSUPP;
+        }
+
+        rtl_ips_nic_on(hw);
+
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+        switch (vif->type) {
+        case NL80211_IFTYPE_STATION:
+                if (mac->beacon_enabled == 1) {
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("NL80211_IFTYPE_STATION\n"));
+                        mac->beacon_enabled = 0;
+                        rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
+                                        rtlpriv->cfg->maps
+                                        [RTL_IBSS_INT_MASKS]);
+                }
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                         ("NL80211_IFTYPE_ADHOC\n"));
+
+                mac->link_state = MAC80211_LINKED;
+                rtlpriv->cfg->ops->set_bcn_reg(hw);
+                break;
+        case NL80211_IFTYPE_AP:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                         ("NL80211_IFTYPE_AP\n"));
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("operation mode %d is not support!\n", vif->type));
+                err = -EOPNOTSUPP;
+                goto out;
+        }
+
+        mac->vif = vif;
+        mac->opmode = vif->type;
+        rtlpriv->cfg->ops->set_network_type(hw, vif->type);
+        memcpy(mac->mac_addr, vif->addr, ETH_ALEN);
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
+
+out:
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+        return err;
+}
+
+static void rtl_op_remove_interface(struct ieee80211_hw *hw,
+                struct ieee80211_vif *vif)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+
+        /* Free beacon resources */
+        if ((mac->opmode == NL80211_IFTYPE_AP) ||
+            (mac->opmode == NL80211_IFTYPE_ADHOC) ||
+            (mac->opmode == NL80211_IFTYPE_MESH_POINT)) {
+                if (mac->beacon_enabled == 1) {
+                        mac->beacon_enabled = 0;
+                        rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
+                                        rtlpriv->cfg->maps
+                                        [RTL_IBSS_INT_MASKS]);
+                }
+        }
+
+        /*
+         *Note: We assume NL80211_IFTYPE_UNSPECIFIED as
+         *NO LINK for our hardware.
+         */
+        mac->vif = NULL;
+        mac->link_state = MAC80211_NOLINK;
+        memset(mac->bssid, 0, 6);
+        mac->opmode = NL80211_IFTYPE_UNSPECIFIED;
+        rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
+
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+}
+
+
+static int rtl_op_config(struct ieee80211_hw *hw, u32 changed)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct ieee80211_conf *conf = &hw->conf;
+
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+        if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {  /*BIT(2)*/
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                         ("IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n"));
+        }
+
+        /*For IPS */
+        if (changed & IEEE80211_CONF_CHANGE_IDLE) {
+                if (hw->conf.flags & IEEE80211_CONF_IDLE)
+                        rtl_ips_nic_off(hw);
+                else
+                        rtl_ips_nic_on(hw);
+        } else {
+                /*
+                 *although rfoff may not cause by ips, but we will
+                 *check the reason in set_rf_power_state function
+                 */
+                if (unlikely(ppsc->rfpwr_state == ERFOFF))
+                        rtl_ips_nic_on(hw);
+        }
+
+        /*For LPS */
+        if (changed & IEEE80211_CONF_CHANGE_PS) {
+                if (conf->flags & IEEE80211_CONF_PS)
+                        rtl_lps_enter(hw);
+                else
+                        rtl_lps_leave(hw);
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                         ("IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n",
+                          hw->conf.long_frame_max_tx_count));
+                mac->retry_long = hw->conf.long_frame_max_tx_count;
+                mac->retry_short = hw->conf.long_frame_max_tx_count;
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
+                                              (u8 *) (&hw->conf.
+                                                      long_frame_max_tx_count));
+        }
+
+        if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
+                struct ieee80211_channel *channel = hw->conf.channel;
+                u8 wide_chan = (u8) channel->hw_value;
+
+                /*
+                 *because we should back channel to
+                 *current_network.chan in in scanning,
+                 *So if set_chan == current_network.chan
+                 *we should set it.
+                 *because mac80211 tell us wrong bw40
+                 *info for cisco1253 bw20, so we modify
+                 *it here based on UPPER & LOWER
+                 */
+                switch (hw->conf.channel_type) {
+                case NL80211_CHAN_HT20:
+                case NL80211_CHAN_NO_HT:
+                        /* SC */
+                        mac->cur_40_prime_sc =
+                            PRIME_CHNL_OFFSET_DONT_CARE;
+                        rtlphy->current_chan_bw = HT_CHANNEL_WIDTH_20;
+                        mac->bw_40 = false;
+                        break;
+                case NL80211_CHAN_HT40MINUS:
+                        /* SC */
+                        mac->cur_40_prime_sc = PRIME_CHNL_OFFSET_UPPER;
+                        rtlphy->current_chan_bw =
+                            HT_CHANNEL_WIDTH_20_40;
+                        mac->bw_40 = true;
+
+                        /*wide channel */
+                        wide_chan -= 2;
+
+                        break;
+                case NL80211_CHAN_HT40PLUS:
+                        /* SC */
+                        mac->cur_40_prime_sc = PRIME_CHNL_OFFSET_LOWER;
+                        rtlphy->current_chan_bw =
+                            HT_CHANNEL_WIDTH_20_40;
+                        mac->bw_40 = true;
+
+                        /*wide channel */
+                        wide_chan += 2;
+
+                        break;
+                default:
+                        mac->bw_40 = false;
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("switch case not processed\n"));
+                        break;
+                }
+
+                if (wide_chan <= 0)
+                        wide_chan = 1;
+                rtlphy->current_channel = wide_chan;
+
+                rtlpriv->cfg->ops->set_channel_access(hw);
+                rtlpriv->cfg->ops->switch_channel(hw);
+                rtlpriv->cfg->ops->set_bw_mode(hw,
+                                               hw->conf.channel_type);
+        }
+
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+
+        return 0;
+}
+
+static void rtl_op_configure_filter(struct ieee80211_hw *hw,
+                             unsigned int changed_flags,
+                             unsigned int *new_flags, u64 multicast)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        *new_flags &= RTL_SUPPORTED_FILTERS;
+        if (!changed_flags)
+                return;
+
+        /*TODO: we disable broadcase now, so enable here */
+        if (changed_flags & FIF_ALLMULTI) {
+                if (*new_flags & FIF_ALLMULTI) {
+                        mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AM] |
+                            rtlpriv->cfg->maps[MAC_RCR_AB];
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Enable receive multicast frame.\n"));
+                } else {
+                        mac->rx_conf &= ~(rtlpriv->cfg->maps[MAC_RCR_AM] |
+                                          rtlpriv->cfg->maps[MAC_RCR_AB]);
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Disable receive multicast frame.\n"));
+                }
+        }
+
+        if (changed_flags & FIF_FCSFAIL) {
+                if (*new_flags & FIF_FCSFAIL) {
+                        mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACRC32];
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Enable receive FCS error frame.\n"));
+                } else {
+                        mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACRC32];
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Disable receive FCS error frame.\n"));
+                }
+        }
+
+        if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
+                /*
+                 *TODO: BIT(5) is probe response BIT(8) is beacon
+                 *TODO: Use define for BIT(5) and BIT(8)
+                 */
+                if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
+                        mac->rx_mgt_filter |= (BIT(5) | BIT(8));
+                else
+                        mac->rx_mgt_filter &= ~(BIT(5) | BIT(8));
+        }
+
+        if (changed_flags & FIF_CONTROL) {
+                if (*new_flags & FIF_CONTROL) {
+                        mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACF];
+                        mac->rx_ctrl_filter |= RTL_SUPPORTED_CTRL_FILTER;
+
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Enable receive control frame.\n"));
+                } else {
+                        mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACF];
+                        mac->rx_ctrl_filter &= ~RTL_SUPPORTED_CTRL_FILTER;
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Disable receive control frame.\n"));
+                }
+        }
+
+        if (changed_flags & FIF_OTHER_BSS) {
+                if (*new_flags & FIF_OTHER_BSS) {
+                        mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AAP];
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Enable receive other BSS's frame.\n"));
+                } else {
+                        mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_AAP];
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                 ("Disable receive other BSS's frame.\n"));
+                }
+        }
+
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *) (&mac->rx_conf));
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,
+                                      (u8 *) (&mac->rx_mgt_filter));
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,
+                                      (u8 *) (&mac->rx_ctrl_filter));
+}
+
+static int _rtl_get_hal_qnum(u16 queue)
+{
+        int qnum;
+
+        switch (queue) {
+        case 0:
+                qnum = AC3_VO;
+                break;
+        case 1:
+                qnum = AC2_VI;
+                break;
+        case 2:
+                qnum = AC0_BE;
+                break;
+        case 3:
+                qnum = AC1_BK;
+                break;
+        default:
+                qnum = AC0_BE;
+                break;
+        }
+        return qnum;
+}
+
+/*
+ *for mac80211 VO=0, VI=1, BE=2, BK=3
+ *for rtl819x  BE=0, BK=1, VI=2, VO=3
+ */
+static int rtl_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
+                   const struct ieee80211_tx_queue_params *param)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        int aci;
+
+        if (queue >= AC_MAX) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("queue number %d is incorrect!\n", queue));
+                return -EINVAL;
+        }
+
+        aci = _rtl_get_hal_qnum(queue);
+        mac->ac[aci].aifs = param->aifs;
+        mac->ac[aci].cw_min = param->cw_min;
+        mac->ac[aci].cw_max = param->cw_max;
+        mac->ac[aci].tx_op = param->txop;
+        memcpy(&mac->edca_param[aci], param, sizeof(*param));
+        rtlpriv->cfg->ops->set_qos(hw, aci);
+        return 0;
+}
+
+static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
+                             struct ieee80211_vif *vif,
+                             struct ieee80211_bss_conf *bss_conf, u32 changed)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+
+        if ((vif->type == NL80211_IFTYPE_ADHOC) ||
+            (vif->type == NL80211_IFTYPE_AP) ||
+            (vif->type == NL80211_IFTYPE_MESH_POINT)) {
+
+                if ((changed & BSS_CHANGED_BEACON) ||
+                    (changed & BSS_CHANGED_BEACON_ENABLED &&
+                     bss_conf->enable_beacon)) {
+
+                        if (mac->beacon_enabled == 0) {
+                                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
+                                         ("BSS_CHANGED_BEACON_ENABLED\n"));
+
+                                /*start hw beacon interrupt. */
+                                /*rtlpriv->cfg->ops->set_bcn_reg(hw); */
+                                mac->beacon_enabled = 1;
+                                rtlpriv->cfg->ops->update_interrupt_mask(hw,
+                                                rtlpriv->cfg->maps
+                                                [RTL_IBSS_INT_MASKS],
+                                                0);
+                        }
+                } else {
+                        if (mac->beacon_enabled == 1) {
+                                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
+                                         ("ADHOC DISABLE BEACON\n"));
+
+                                mac->beacon_enabled = 0;
+                                rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
+                                                rtlpriv->cfg->maps
+                                                [RTL_IBSS_INT_MASKS]);
+                        }
+                }
+
+                if (changed & BSS_CHANGED_BEACON_INT) {
+                        RT_TRACE(rtlpriv, COMP_BEACON, DBG_TRACE,
+                                 ("BSS_CHANGED_BEACON_INT\n"));
+                        mac->beacon_interval = bss_conf->beacon_int;
+                        rtlpriv->cfg->ops->set_bcn_intv(hw);
+                }
+        }
+
+        /*TODO: reference to enum ieee80211_bss_change */
+        if (changed & BSS_CHANGED_ASSOC) {
+                if (bss_conf->assoc) {
+                        mac->link_state = MAC80211_LINKED;
+                        mac->cnt_after_linked = 0;
+                        mac->assoc_id = bss_conf->aid;
+                        memcpy(mac->bssid, bss_conf->bssid, 6);
+
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
+                                 ("BSS_CHANGED_ASSOC\n"));
+                } else {
+                        if (mac->link_state == MAC80211_LINKED)
+                                rtl_lps_leave(hw);
+
+                        mac->link_state = MAC80211_NOLINK;
+                        memset(mac->bssid, 0, 6);
+
+                        /* reset sec info */
+                        rtl_cam_reset_sec_info(hw);
+
+                        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
+                                 ("BSS_CHANGED_UN_ASSOC\n"));
+                }
+        }
+
+        if (changed & BSS_CHANGED_ERP_CTS_PROT) {
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("BSS_CHANGED_ERP_CTS_PROT\n"));
+                mac->use_cts_protect = bss_conf->use_cts_prot;
+        }
+
+        if (changed & BSS_CHANGED_ERP_PREAMBLE) {
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                         ("BSS_CHANGED_ERP_PREAMBLE use short preamble:%x\n",
+                          bss_conf->use_short_preamble));
+
+                mac->short_preamble = bss_conf->use_short_preamble;
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACK_PREAMBLE,
+                                              (u8 *) (&mac->short_preamble));
+        }
+
+        if (changed & BSS_CHANGED_ERP_SLOT) {
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("BSS_CHANGED_ERP_SLOT\n"));
+
+                if (bss_conf->use_short_slot)
+                        mac->slot_time = RTL_SLOT_TIME_9;
+                else
+                        mac->slot_time = RTL_SLOT_TIME_20;
+
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
+                                              (u8 *) (&mac->slot_time));
+        }
+
+        if (changed & BSS_CHANGED_HT) {
+                struct ieee80211_sta *sta = NULL;
+
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("BSS_CHANGED_HT\n"));
+
+                sta = ieee80211_find_sta(mac->vif, mac->bssid);
+
+                if (sta) {
+                        if (sta->ht_cap.ampdu_density >
+                            mac->current_ampdu_density)
+                                mac->current_ampdu_density =
+                                    sta->ht_cap.ampdu_density;
+                        if (sta->ht_cap.ampdu_factor <
+                            mac->current_ampdu_factor)
+                                mac->current_ampdu_factor =
+                                    sta->ht_cap.ampdu_factor;
+                }
+
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SHORTGI_DENSITY,
+                                              (u8 *) (&mac->max_mss_density));
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AMPDU_FACTOR,
+                                              &mac->current_ampdu_factor);
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AMPDU_MIN_SPACE,
+                                              &mac->current_ampdu_density);
+        }
+
+        if (changed & BSS_CHANGED_BSSID) {
+                struct ieee80211_sta *sta = NULL;
+                u32 basic_rates;
+                u8 i;
+
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BSSID,
+                                              (u8 *) bss_conf->bssid);
+
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG,
+                         (MAC_FMT "\n", MAC_ARG(bss_conf->bssid)));
+
+                memcpy(mac->bssid, bss_conf->bssid, 6);
+                if (is_valid_ether_addr(bss_conf->bssid)) {
+                        switch (vif->type) {
+                        case NL80211_IFTYPE_UNSPECIFIED:
+                                break;
+                        case NL80211_IFTYPE_ADHOC:
+                                break;
+                        case NL80211_IFTYPE_STATION:
+                                break;
+                        case NL80211_IFTYPE_AP:
+                                break;
+                        default:
+                                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                         ("switch case not process\n"));
+                                break;
+                        }
+                        rtlpriv->cfg->ops->set_network_type(hw, vif->type);
+                } else
+                        rtlpriv->cfg->ops->set_network_type(hw,
+                                        NL80211_IFTYPE_UNSPECIFIED);
+
+                memset(mac->mcs, 0, 16);
+                mac->ht_enable = false;
+                mac->sgi_40 = false;
+                mac->sgi_20 = false;
+
+                if (!bss_conf->use_short_slot)
+                        mac->mode = WIRELESS_MODE_B;
+                else
+                        mac->mode = WIRELESS_MODE_G;
+
+                sta = ieee80211_find_sta(mac->vif, mac->bssid);
+
+                if (sta) {
+                        if (sta->ht_cap.ht_supported) {
+                                mac->mode = WIRELESS_MODE_N_24G;
+                                mac->ht_enable = true;
+                        }
+
+                        if (mac->ht_enable) {
+                                u16 ht_cap = sta->ht_cap.cap;
+                                memcpy(mac->mcs, (u8 *) (&sta->ht_cap.mcs), 16);
+
+                                for (i = 0; i < 16; i++)
+                                        RT_TRACE(rtlpriv, COMP_MAC80211,
+                                                 DBG_LOUD, ("%x ",
+                                                            mac->mcs[i]));
+                                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD,
+                                         ("\n"));
+
+                                if (ht_cap & IEEE80211_HT_CAP_SGI_40)
+                                        mac->sgi_40 = true;
+
+                                if (ht_cap & IEEE80211_HT_CAP_SGI_20)
+                                        mac->sgi_20 = true;
+
+                                /*
+                                 * for cisco 1252 bw20 it's wrong
+                                 * if (ht_cap &
+                                 *     IEEE80211_HT_CAP_SUP_WIDTH_20_40) {
+                                 *      mac->bw_40 = true;
+                                 * }
+                                 */
+                        }
+                }
+
+                /*mac80211 just give us CCK rates any time
+                 *So we add G rate in basic rates when
+                 not in B mode*/
+                if (changed & BSS_CHANGED_BASIC_RATES) {
+                        if (mac->mode == WIRELESS_MODE_B)
+                                basic_rates = bss_conf->basic_rates | 0x00f;
+                        else
+                                basic_rates = bss_conf->basic_rates | 0xff0;
+
+                        if (!vif)
+                                goto out;
+
+                        mac->basic_rates = basic_rates;
+                        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
+                                        (u8 *) (&basic_rates));
+
+                        if (rtlpriv->dm.b_useramask)
+                                rtlpriv->cfg->ops->update_rate_mask(hw, 0);
+                        else
+                                rtlpriv->cfg->ops->update_rate_table(hw);
+
+                }
+        }
+
+        /*
+         * For FW LPS:
+         * To tell firmware we have connected
+         * to an AP. For 92SE/CE power save v2.
+         */
+        if (changed & BSS_CHANGED_ASSOC) {
+                if (bss_conf->assoc) {
+                        if (ppsc->b_fwctrl_lps) {
+                                u8 mstatus = RT_MEDIA_CONNECT;
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                      HW_VAR_H2C_FW_JOINBSSRPT,
+                                                      (u8 *) (&mstatus));
+                                ppsc->report_linked = true;
+                        }
+                } else {
+                        if (ppsc->b_fwctrl_lps) {
+                                u8 mstatus = RT_MEDIA_DISCONNECT;
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                      HW_VAR_H2C_FW_JOINBSSRPT,
+                                                      (u8 *)(&mstatus));
+                                ppsc->report_linked = false;
+                        }
+                }
+        }
+
+out:
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+}
+
+static u64 rtl_op_get_tsf(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u64 tsf;
+
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_CORRECT_TSF, (u8 *) (&tsf));
+        return tsf;
+}
+
+static void rtl_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u8 bibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ? 1 : 0;;
+
+        mac->tsf = tsf;
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CORRECT_TSF, (u8 *) (&bibss));
+}
+
+static void rtl_op_reset_tsf(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 tmp = 0;
+
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DUAL_TSF_RST, (u8 *) (&tmp));
+}
+
+static void rtl_op_sta_notify(struct ieee80211_hw *hw,
+                              struct ieee80211_vif *vif,
+                              enum sta_notify_cmd cmd,
+                              struct ieee80211_sta *sta)
+{
+        switch (cmd) {
+        case STA_NOTIFY_SLEEP:
+                break;
+        case STA_NOTIFY_AWAKE:
+                break;
+        default:
+                break;
+        }
+}
+
+static int rtl_op_ampdu_action(struct ieee80211_hw *hw,
+                               struct ieee80211_vif *vif,
+                               enum ieee80211_ampdu_mlme_action action,
+                               struct ieee80211_sta *sta, u16 tid, u16 * ssn)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        switch (action) {
+        case IEEE80211_AMPDU_TX_START:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("IEEE80211_AMPDU_TX_START: TID:%d\n", tid));
+                return rtl_tx_agg_start(hw, sta->addr, tid, ssn);
+                break;
+        case IEEE80211_AMPDU_TX_STOP:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid));
+                return rtl_tx_agg_stop(hw, sta->addr, tid);
+                break;
+        case IEEE80211_AMPDU_TX_OPERATIONAL:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid));
+                break;
+        case IEEE80211_AMPDU_RX_START:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("IEEE80211_AMPDU_RX_START:TID:%d\n", tid));
+                break;
+        case IEEE80211_AMPDU_RX_STOP:
+                RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
+                         ("IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid));
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("IEEE80211_AMPDU_ERR!!!!:\n"));
+                return -EOPNOTSUPP;
+        }
+        return 0;
+}
+
+static void rtl_op_sw_scan_start(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        mac->act_scanning = true;
+
+        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, ("\n"));
+
+        if (mac->link_state == MAC80211_LINKED) {
+                rtl_lps_leave(hw);
+                mac->link_state = MAC80211_LINKED_SCANNING;
+        } else
+                rtl_ips_nic_on(hw);
+
+        rtlpriv->cfg->ops->led_control(hw, LED_CTL_SITE_SURVEY);
+        rtlpriv->cfg->ops->scan_operation_backup(hw, SCAN_OPT_BACKUP);
+}
+
+static void rtl_op_sw_scan_complete(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, ("\n"));
+
+        rtlpriv->cfg->ops->scan_operation_backup(hw, SCAN_OPT_RESTORE);
+        mac->act_scanning = false;
+        if (mac->link_state == MAC80211_LINKED_SCANNING) {
+                mac->link_state = MAC80211_LINKED;
+
+                /* fix fwlps issue */
+                rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
+
+                if (rtlpriv->dm.b_useramask)
+                        rtlpriv->cfg->ops->update_rate_mask(hw, 0);
+                else
+                        rtlpriv->cfg->ops->update_rate_table(hw);
+
+        }
+
+}
+
+static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+                          struct ieee80211_vif *vif, struct ieee80211_sta *sta,
+                          struct ieee80211_key_conf *key)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u8 key_type = NO_ENCRYPTION;
+        u8 key_idx;
+        bool group_key = false;
+        bool wep_only = false;
+        int err = 0;
+        u8 mac_addr[ETH_ALEN];
+        u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+        u8 zero_addr[ETH_ALEN] = { 0 };
+
+        if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("not open hw encryption\n"));
+                return -ENOSPC; /*User disabled HW-crypto */
+        }
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                 ("%s hardware based encryption for keyidx: %d, mac: %pM\n",
+                  cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
+                  sta ? sta->addr : bcast_addr));
+        rtlpriv->sec.being_setkey = true;
+        rtl_ips_nic_on(hw);
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+        /* <1> get encryption alg */
+        switch (key->cipher) {
+        case WLAN_CIPHER_SUITE_WEP40:
+                key_type = WEP40_ENCRYPTION;
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("alg:WEP40\n"));
+                rtlpriv->sec.use_defaultkey = true;
+                break;
+        case WLAN_CIPHER_SUITE_WEP104:
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                         ("alg:WEP104\n"));
+                key_type = WEP104_ENCRYPTION;
+                rtlpriv->sec.use_defaultkey = true;
+                break;
+        case WLAN_CIPHER_SUITE_TKIP:
+                key_type = TKIP_ENCRYPTION;
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("alg:TKIP\n"));
+                if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                        rtlpriv->sec.use_defaultkey = true;
+                break;
+        case WLAN_CIPHER_SUITE_CCMP:
+                key_type = AESCCMP_ENCRYPTION;
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("alg:CCMP\n"));
+                if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                        rtlpriv->sec.use_defaultkey = true;
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("alg_err:%x!!!!:\n", key->cipher));
+                goto out_unlock;
+        }
+        /* <2> get key_idx */
+        key_idx = (u8) (key->keyidx);
+        if (key_idx > 3)
+                goto out_unlock;
+        /* <3> if pairwise key enable_hw_sec */
+        group_key = !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE);
+        if ((!group_key) || (mac->opmode == NL80211_IFTYPE_ADHOC) ||
+            rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION) {
+                if (rtlpriv->sec.pairwise_enc_algorithm == NO_ENCRYPTION &&
+                    (key_type == WEP40_ENCRYPTION ||
+                     key_type == WEP104_ENCRYPTION))
+                        wep_only = true;
+                rtlpriv->sec.pairwise_enc_algorithm = key_type;
+                rtlpriv->cfg->ops->enable_hw_sec(hw);
+        }
+        /* <4> set key based on cmd */
+        switch (cmd) {
+        case SET_KEY:
+                if (wep_only) {
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("set WEP(group/pairwise) key\n"));
+                        /* Pairwise key with an assigned MAC address. */
+                        rtlpriv->sec.pairwise_enc_algorithm = key_type;
+                        rtlpriv->sec.group_enc_algorithm = key_type;
+                        /*set local buf about wep key. */
+                        memcpy(rtlpriv->sec.key_buf[key_idx],
+                               key->key, key->keylen);
+                        rtlpriv->sec.key_len[key_idx] = key->keylen;
+                        memcpy(mac_addr, zero_addr, ETH_ALEN);
+                } else if (group_key) { /* group key */
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("set group key\n"));
+                        /* group key */
+                        rtlpriv->sec.group_enc_algorithm = key_type;
+                        /*set local buf about group key. */
+                        memcpy(rtlpriv->sec.key_buf[key_idx],
+                               key->key, key->keylen);
+                        rtlpriv->sec.key_len[key_idx] = key->keylen;
+                        memcpy(mac_addr, bcast_addr, ETH_ALEN);
+                } else {        /* pairwise key */
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("set pairwise key\n"));
+                        if (!sta) {
+                                RT_ASSERT(false, ("pairwise key withnot"
+                                                  "mac_addr\n"));
+                                err = -EOPNOTSUPP;
+                                goto out_unlock;
+                        }
+                        /* Pairwise key with an assigned MAC address. */
+                        rtlpriv->sec.pairwise_enc_algorithm = key_type;
+                        /*set local buf about pairwise key. */
+                        memcpy(rtlpriv->sec.key_buf[PAIRWISE_KEYIDX],
+                               key->key, key->keylen);
+                        rtlpriv->sec.key_len[PAIRWISE_KEYIDX] = key->keylen;
+                        rtlpriv->sec.pairwise_key =
+                            rtlpriv->sec.key_buf[PAIRWISE_KEYIDX];
+                        memcpy(mac_addr, sta->addr, ETH_ALEN);
+                }
+                rtlpriv->cfg->ops->set_key(hw, key_idx, mac_addr,
+                                           group_key, key_type, wep_only,
+                                           false);
+                /* <5> tell mac80211 do something: */
+                /*must use sw generate IV, or can not work !!!!. */
+                key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
+                key->hw_key_idx = key_idx;
+                if (key_type == TKIP_ENCRYPTION)
+                        key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
+                break;
+        case DISABLE_KEY:
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                         ("disable key delete one entry\n"));
+                /*set local buf about wep key. */
+                memset(rtlpriv->sec.key_buf[key_idx], 0, key->keylen);
+                rtlpriv->sec.key_len[key_idx] = 0;
+                memcpy(mac_addr, zero_addr, ETH_ALEN);
+                /*
+                 *mac80211 will delete entrys one by one,
+                 *so don't use rtl_cam_reset_all_entry
+                 *or clear all entry here.
+                 */
+                rtl_cam_delete_one_entry(hw, mac_addr, key_idx);
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("cmd_err:%x!!!!:\n", cmd));
+        }
+out_unlock:
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+        rtlpriv->sec.being_setkey = false;
+        return err;
+}
+
+static void rtl_op_rfkill_poll(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        bool radio_state;
+        bool blocked;
+        u8 valid = 0;
+
+        if (!test_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status))
+                return;
+
+        mutex_lock(&rtlpriv->locks.conf_mutex);
+
+        /*if Radio On return true here */
+        radio_state = rtlpriv->cfg->ops->radio_onoff_checking(hw, &valid);
+
+        if (valid) {
+                if (unlikely(radio_state != rtlpriv->rfkill.rfkill_state)) {
+                        rtlpriv->rfkill.rfkill_state = radio_state;
+
+                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                 (KERN_INFO "wireless radio switch turned %s\n",
+                                  radio_state ? "on" : "off"));
+
+                        blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1;
+                        wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
+                }
+        }
+
+        mutex_unlock(&rtlpriv->locks.conf_mutex);
+}
+
+const struct ieee80211_ops rtl_ops = {
+        .start = rtl_op_start,
+        .stop = rtl_op_stop,
+        .tx = rtl_op_tx,
+        .add_interface = rtl_op_add_interface,
+        .remove_interface = rtl_op_remove_interface,
+        .config = rtl_op_config,
+        .configure_filter = rtl_op_configure_filter,
+        .set_key = rtl_op_set_key,
+        .conf_tx = rtl_op_conf_tx,
+        .bss_info_changed = rtl_op_bss_info_changed,
+        .get_tsf = rtl_op_get_tsf,
+        .set_tsf = rtl_op_set_tsf,
+        .reset_tsf = rtl_op_reset_tsf,
+        .sta_notify = rtl_op_sta_notify,
+        .ampdu_action = rtl_op_ampdu_action,
+        .sw_scan_start = rtl_op_sw_scan_start,
+        .sw_scan_complete = rtl_op_sw_scan_complete,
+        .rfkill_poll = rtl_op_rfkill_poll,
+};
diff --git a/drivers/net/wireless/rtlwifi/core.h b/drivers/net/wireless/rtlwifi/core.h
new file mode 100644
index 000000000000..0ef31c3c6196
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/core.h
@@ -0,0 +1,42 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * Tmis program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * Tmis program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * tmis program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * Tme full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *****************************************************************************/
+
+#ifndef __RTL_CORE_H__
+#define __RTL_CORE_H__
+
+#define RTL_SUPPORTED_FILTERS           \
+        (FIF_PROMISC_IN_BSS | \
+        FIF_ALLMULTI | FIF_CONTROL | \
+        FIF_OTHER_BSS | \
+        FIF_FCSFAIL | \
+        FIF_BCN_PRBRESP_PROMISC)
+
+#define RTL_SUPPORTED_CTRL_FILTER       0xFF
+
+extern const struct ieee80211_ops rtl_ops;
+#endif
diff --git a/drivers/net/wireless/rtlwifi/debug.c b/drivers/net/wireless/rtlwifi/debug.c
new file mode 100644
index 000000000000..5fa73852cb66
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/debug.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * Tmis program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * Tmis program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * tmis program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * Tme full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *****************************************************************************/
+
+#include "wifi.h"
+
+void rtl_dbgp_flag_init(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 i;
+
+        rtlpriv->dbg.global_debuglevel = DBG_EMERG;
+
+        rtlpriv->dbg.global_debugcomponents =
+            COMP_ERR | COMP_FW | COMP_INIT | COMP_RECV | COMP_SEND |
+            COMP_MLME | COMP_SCAN | COMP_INTR | COMP_LED | COMP_SEC |
+            COMP_BEACON | COMP_RATE | COMP_RXDESC | COMP_DIG | COMP_TXAGC |
+            COMP_POWER | COMP_POWER_TRACKING | COMP_BB_POWERSAVING | COMP_SWAS |
+            COMP_RF | COMP_TURBO | COMP_RATR | COMP_CMD |
+            COMP_EFUSE | COMP_QOS | COMP_MAC80211 | COMP_REGD | COMP_CHAN;
+
+        for (i = 0; i < DBGP_TYPE_MAX; i++)
+                rtlpriv->dbg.dbgp_type[i] = 0;
+
+        /*Init Debug flag enable condition */
+}
diff --git a/drivers/net/wireless/rtlwifi/debug.h b/drivers/net/wireless/rtlwifi/debug.h
new file mode 100644
index 000000000000..08bdec2ceda4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/debug.h
@@ -0,0 +1,212 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * Tmis program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * Tmis program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * tmis program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * Tme full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *****************************************************************************/
+
+#ifndef __RTL_DEBUG_H__
+#define __RTL_DEBUG_H__
+
+/*--------------------------------------------------------------
+                        Debug level
+--------------------------------------------------------------*/
+/*
+ *Fatal bug.
+ *For example, Tx/Rx/IO locked up,
+ *memory access violation,
+ *resource allocation failed,
+ *unexpected HW behavior, HW BUG
+ *and so on.
+ */
+#define DBG_EMERG                       0
+
+/*
+ *Abnormal, rare, or unexpeted cases.
+ *For example, Packet/IO Ctl canceled,
+ *device suprisely unremoved and so on.
+ */
+#define DBG_WARNING                     2
+
+/*
+ *Normal case driver developer should
+ *open, we can see link status like
+ *assoc/AddBA/DHCP/adapter start and
+ *so on basic and useful infromations.
+ */
+#define DBG_DMESG                       3
+
+/*
+ *Normal case with useful information
+ *about current SW or HW state.
+ *For example, Tx/Rx descriptor to fill,
+ *Tx/Rx descriptor completed status,
+ *SW protocol state change, dynamic
+ *mechanism state change and so on.
+ */
+#define DBG_LOUD                        4
+
+/*
+ *Normal case with detail execution
+ *flow or information.
+ */
+#define DBG_TRACE                       5
+
+/*--------------------------------------------------------------
+                Define the rt_trace components
+--------------------------------------------------------------*/
+#define COMP_ERR                        BIT(0)
+#define COMP_FW                         BIT(1)
+#define COMP_INIT                       BIT(2)  /*For init/deinit */
+#define COMP_RECV                       BIT(3)  /*For Rx. */
+#define COMP_SEND                       BIT(4)  /*For Tx. */
+#define COMP_MLME                       BIT(5)  /*For MLME. */
+#define COMP_SCAN                       BIT(6)  /*For Scan. */
+#define COMP_INTR                       BIT(7)  /*For interrupt Related. */
+#define COMP_LED                        BIT(8)  /*For LED. */
+#define COMP_SEC                        BIT(9)  /*For sec. */
+#define COMP_BEACON                     BIT(10) /*For beacon. */
+#define COMP_RATE                       BIT(11) /*For rate. */
+#define COMP_RXDESC                     BIT(12) /*For rx desc. */
+#define COMP_DIG                        BIT(13) /*For DIG */
+#define COMP_TXAGC                      BIT(14) /*For Tx power */
+#define COMP_HIPWR                      BIT(15) /*For High Power Mechanism */
+#define COMP_POWER                      BIT(16) /*For lps/ips/aspm. */
+#define COMP_POWER_TRACKING     BIT(17) /*For TX POWER TRACKING */
+#define COMP_BB_POWERSAVING     BIT(18)
+#define COMP_SWAS                       BIT(19) /*For SW Antenna Switch */
+#define COMP_RF                         BIT(20) /*For RF. */
+#define COMP_TURBO                      BIT(21) /*For EDCA TURBO. */
+#define COMP_RATR                       BIT(22)
+#define COMP_CMD                        BIT(23)
+#define COMP_EFUSE                      BIT(24)
+#define COMP_QOS                        BIT(25)
+#define COMP_MAC80211           BIT(26)
+#define COMP_REGD                       BIT(27)
+#define COMP_CHAN                       BIT(28)
+
+/*--------------------------------------------------------------
+                Define the rt_print components
+--------------------------------------------------------------*/
+/* Define EEPROM and EFUSE  check module bit*/
+#define EEPROM_W                        BIT(0)
+#define EFUSE_PG                        BIT(1)
+#define EFUSE_READ_ALL          BIT(2)
+
+/* Define init check for module bit*/
+#define INIT_EEPROM                     BIT(0)
+#define INIT_TxPower            BIT(1)
+#define INIT_IQK                        BIT(2)
+#define INIT_RF                         BIT(3)
+
+/* Define PHY-BB/RF/MAC check module bit */
+#define PHY_BBR                         BIT(0)
+#define PHY_BBW                         BIT(1)
+#define PHY_RFR                         BIT(2)
+#define PHY_RFW                         BIT(3)
+#define PHY_MACR                        BIT(4)
+#define PHY_MACW                        BIT(5)
+#define PHY_ALLR                        BIT(6)
+#define PHY_ALLW                        BIT(7)
+#define PHY_TXPWR                       BIT(8)
+#define PHY_PWRDIFF                     BIT(9)
+
+enum dbgp_flag_e {
+        FQOS = 0,
+        FTX = 1,
+        FRX = 2,
+        FSEC = 3,
+        FMGNT = 4,
+        FMLME = 5,
+        FRESOURCE = 6,
+        FBEACON = 7,
+        FISR = 8,
+        FPHY = 9,
+        FMP = 10,
+        FEEPROM = 11,
+        FPWR = 12,
+        FDM = 13,
+        FDBGCtrl = 14,
+        FC2H = 15,
+        FBT = 16,
+        FINIT = 17,
+        FIOCTL = 18,
+        DBGP_TYPE_MAX
+};
+
+#define RT_ASSERT(_exp, fmt)                            \
+        do {                                            \
+                if (!(_exp)) {                  \
+                        printk(KERN_DEBUG "%s:%s(): ", KBUILD_MODNAME, \
+                        __func__);                      \
+                        printk fmt;                     \
+                } \
+        } while (0);
+
+#define RT_TRACE(rtlpriv, comp, level, fmt)\
+        do { \
+                if (unlikely(((comp) & rtlpriv->dbg.global_debugcomponents) && \
+                        ((level) <= rtlpriv->dbg.global_debuglevel))) {\
+                        printk(KERN_DEBUG "%s:%s():<%lx-%x> ", KBUILD_MODNAME, \
+                        __func__, in_interrupt(), in_atomic()); \
+                        printk fmt;                             \
+                } \
+        } while (0);
+
+#define RTPRINT(rtlpriv, dbgtype, dbgflag, printstr)    \
+        do {                                            \
+                if (unlikely(rtlpriv->dbg.dbgp_type[dbgtype] & dbgflag)) { \
+                        printk(KERN_DEBUG "%s: ", KBUILD_MODNAME);      \
+                        printk printstr;                \
+                }                                       \
+        } while (0);
+
+#define RT_PRINT_DATA(rtlpriv, _comp, _level, _titlestring, _hexdata, \
+                _hexdatalen) \
+        do {\
+                if (unlikely(((_comp) & rtlpriv->dbg.global_debugcomponents) &&\
+                        (_level <= rtlpriv->dbg.global_debuglevel)))    { \
+                        int __i;                                        \
+                        u8*     ptr = (u8 *)_hexdata;                   \
+                        printk(KERN_DEBUG "%s: ", KBUILD_MODNAME);      \
+                        printk("In process \"%s\" (pid %i):", current->comm,\
+                                        current->pid); \
+                        printk(_titlestring);           \
+                        for (__i = 0; __i < (int)_hexdatalen; __i++) {  \
+                                printk("%02X%s", ptr[__i], (((__i + 1) % 4)\
+                                                        == 0) ? "  " : " ");\
+                                if (((__i + 1) % 16) == 0)              \
+                                        printk("\n");                   \
+                        }                               \
+                        printk(KERN_DEBUG "\n");                        \
+                } \
+        } while (0);
+
+#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
+#define MAC_ARG(x) \
+        ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2],\
+        ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5]
+
+void rtl_dbgp_flag_init(struct ieee80211_hw *hw);
+#endif
diff --git a/drivers/net/wireless/rtlwifi/efuse.c b/drivers/net/wireless/rtlwifi/efuse.c
new file mode 100644
index 000000000000..b8433f3a9bc2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/efuse.c
@@ -0,0 +1,1189 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * Tmis program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * Tmis program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * tmis program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * Tme full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "wifi.h"
+#include "efuse.h"
+
+static const u8 MAX_PGPKT_SIZE = 9;
+static const u8 PGPKT_DATA_SIZE = 8;
+static const int EFUSE_MAX_SIZE = 512;
+
+static const u8 EFUSE_OOB_PROTECT_BYTES = 15;
+
+static const struct efuse_map RTL8712_SDIO_EFUSE_TABLE[] = {
+        {0, 0, 0, 2},
+        {0, 1, 0, 2},
+        {0, 2, 0, 2},
+        {1, 0, 0, 1},
+        {1, 0, 1, 1},
+        {1, 1, 0, 1},
+        {1, 1, 1, 3},
+        {1, 3, 0, 17},
+        {3, 3, 1, 48},
+        {10, 0, 0, 6},
+        {10, 3, 0, 1},
+        {10, 3, 1, 1},
+        {11, 0, 0, 28}
+};
+
+static void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset,
+                                        u8 *pbuf);
+static void efuse_shadow_read_1byte(struct ieee80211_hw *hw, u16 offset,
+                                    u8 *value);
+static void efuse_shadow_read_2byte(struct ieee80211_hw *hw, u16 offset,
+                                    u16 *value);
+static void efuse_shadow_read_4byte(struct ieee80211_hw *hw, u16 offset,
+                                    u32 *value);
+static void efuse_shadow_write_1byte(struct ieee80211_hw *hw, u16 offset,
+                                     u8 value);
+static void efuse_shadow_write_2byte(struct ieee80211_hw *hw, u16 offset,
+                                     u16 value);
+static void efuse_shadow_write_4byte(struct ieee80211_hw *hw, u16 offset,
+                                     u32 value);
+static int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr,
+                                        u8 *data);
+static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr,
+                                        u8 data);
+static void efuse_read_all_map(struct ieee80211_hw *hw, u8 *efuse);
+static int efuse_pg_packet_read(struct ieee80211_hw *hw, u8 offset,
+                                        u8 *data);
+static int efuse_pg_packet_write(struct ieee80211_hw *hw, u8 offset,
+                                 u8 word_en, u8 *data);
+static void efuse_word_enable_data_read(u8 word_en, u8 *sourdata,
+                                        u8 *targetdata);
+static u8 efuse_word_enable_data_write(struct ieee80211_hw *hw,
+                                       u16 efuse_addr, u8 word_en, u8 *data);
+static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite,
+                                        u8 pwrstate);
+static u16 efuse_get_current_size(struct ieee80211_hw *hw);
+static u8 efuse_calculate_word_cnts(u8 word_en);
+
+void efuse_initialize(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 bytetemp;
+        u8 temp;
+
+        bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN] + 1);
+        temp = bytetemp | 0x20;
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN] + 1, temp);
+
+        bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[SYS_ISO_CTRL] + 1);
+        temp = bytetemp & 0xFE;
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[SYS_ISO_CTRL] + 1, temp);
+
+        bytetemp = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3);
+        temp = bytetemp | 0x80;
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST] + 3, temp);
+
+        rtl_write_byte(rtlpriv, 0x2F8, 0x3);
+
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0x72);
+
+}
+
+u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 data;
+        u8 bytetemp;
+        u8 temp;
+        u32 k = 0;
+
+        if (address < EFUSE_REAL_CONTENT_LEN) {
+                temp = address & 0xFF;
+                rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
+                               temp);
+                bytetemp = rtl_read_byte(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
+                temp = ((address >> 8) & 0x03) | (bytetemp & 0xFC);
+                rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
+                               temp);
+
+                bytetemp = rtl_read_byte(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
+                temp = bytetemp & 0x7F;
+                rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3,
+                               temp);
+
+                bytetemp = rtl_read_byte(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
+                while (!(bytetemp & 0x80)) {
+                        bytetemp = rtl_read_byte(rtlpriv,
+                                                 rtlpriv->cfg->
+                                                 maps[EFUSE_CTRL] + 3);
+                        k++;
+                        if (k == 1000) {
+                                k = 0;
+                                break;
+                        }
+                }
+                data = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
+                return data;
+        } else
+                return 0xFF;
+
+}
+EXPORT_SYMBOL(efuse_read_1byte);
+
+void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 bytetemp;
+        u8 temp;
+        u32 k = 0;
+
+        RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                 ("Addr=%x Data =%x\n", address, value));
+
+        if (address < EFUSE_REAL_CONTENT_LEN) {
+                rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], value);
+
+                temp = address & 0xFF;
+                rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
+                               temp);
+                bytetemp = rtl_read_byte(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
+
+                temp = ((address >> 8) & 0x03) | (bytetemp & 0xFC);
+                rtl_write_byte(rtlpriv,
+                               rtlpriv->cfg->maps[EFUSE_CTRL] + 2, temp);
+
+                bytetemp = rtl_read_byte(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
+                temp = bytetemp | 0x80;
+                rtl_write_byte(rtlpriv,
+                               rtlpriv->cfg->maps[EFUSE_CTRL] + 3, temp);
+
+                bytetemp = rtl_read_byte(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
+
+                while (bytetemp & 0x80) {
+                        bytetemp = rtl_read_byte(rtlpriv,
+                                                 rtlpriv->cfg->
+                                                 maps[EFUSE_CTRL] + 3);
+                        k++;
+                        if (k == 100) {
+                                k = 0;
+                                break;
+                        }
+                }
+        }
+
+}
+
+static void read_efuse_byte(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 value32;
+        u8 readbyte;
+        u16 retry;
+
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
+                       (_offset & 0xff));
+        readbyte = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2);
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
+                       ((_offset >> 8) & 0x03) | (readbyte & 0xfc));
+
+        readbyte = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3);
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3,
+                       (readbyte & 0x7f));
+
+        retry = 0;
+        value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
+        while (!(((value32 >> 24) & 0xff) & 0x80) && (retry < 10000)) {
+                value32 = rtl_read_dword(rtlpriv,
+                                         rtlpriv->cfg->maps[EFUSE_CTRL]);
+                retry++;
+        }
+
+        udelay(50);
+        value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
+
+        *pbuf = (u8) (value32 & 0xff);
+}
+
+void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 efuse_tbl[EFUSE_MAP_LEN];
+        u8 rtemp8[1];
+        u16 efuse_addr = 0;
+        u8 offset, wren;
+        u16 i;
+        u16 j;
+        u16 efuse_word[EFUSE_MAX_SECTION][EFUSE_MAX_WORD_UNIT];
+        u16 efuse_utilized = 0;
+        u8 efuse_usage;
+
+        if ((_offset + _size_byte) > EFUSE_MAP_LEN) {
+                RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                         ("read_efuse(): Invalid offset(%#x) with read "
+                          "bytes(%#x)!!\n", _offset, _size_byte));
+                return;
+        }
+
+        for (i = 0; i < EFUSE_MAX_SECTION; i++)
+                for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++)
+                        efuse_word[i][j] = 0xFFFF;
+
+        read_efuse_byte(hw, efuse_addr, rtemp8);
+        if (*rtemp8 != 0xFF) {
+                efuse_utilized++;
+                RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
+                        ("Addr=%d\n", efuse_addr));
+                efuse_addr++;
+        }
+
+        while ((*rtemp8 != 0xFF) && (efuse_addr < EFUSE_REAL_CONTENT_LEN)) {
+                offset = ((*rtemp8 >> 4) & 0x0f);
+
+                if (offset < EFUSE_MAX_SECTION) {
+                        wren = (*rtemp8 & 0x0f);
+                        RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
+                                ("offset-%d Worden=%x\n", offset, wren));
+
+                        for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
+                                if (!(wren & 0x01)) {
+                                        RTPRINT(rtlpriv, FEEPROM,
+                                                EFUSE_READ_ALL, ("Addr=%d\n",
+                                                                 efuse_addr));
+
+                                        read_efuse_byte(hw, efuse_addr, rtemp8);
+                                        efuse_addr++;
+                                        efuse_utilized++;
+                                        efuse_word[offset][i] = (*rtemp8 & 0xff);
+
+                                        if (efuse_addr >= EFUSE_REAL_CONTENT_LEN)
+                                                break;
+
+                                        RTPRINT(rtlpriv, FEEPROM,
+                                                EFUSE_READ_ALL, ("Addr=%d\n",
+                                                                 efuse_addr));
+
+                                        read_efuse_byte(hw, efuse_addr, rtemp8);
+                                        efuse_addr++;
+                                        efuse_utilized++;
+                                        efuse_word[offset][i] |=
+                                            (((u16)*rtemp8 << 8) & 0xff00);
+
+                                        if (efuse_addr >= EFUSE_REAL_CONTENT_LEN)
+                                                break;
+                                }
+
+                                wren >>= 1;
+                        }
+                }
+
+                RTPRINT(rtlpriv, FEEPROM, EFUSE_READ_ALL,
+                        ("Addr=%d\n", efuse_addr));
+                read_efuse_byte(hw, efuse_addr, rtemp8);
+                if (*rtemp8 != 0xFF && (efuse_addr < 512)) {
+                        efuse_utilized++;
+                        efuse_addr++;
+                }
+        }
+
+        for (i = 0; i < EFUSE_MAX_SECTION; i++) {
+                for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) {
+                        efuse_tbl[(i * 8) + (j * 2)] =
+                            (efuse_word[i][j] & 0xff);
+                        efuse_tbl[(i * 8) + ((j * 2) + 1)] =
+                            ((efuse_word[i][j] >> 8) & 0xff);
+                }
+        }
+
+        for (i = 0; i < _size_byte; i++)
+                pbuf[i] = efuse_tbl[_offset + i];
+
+        rtlefuse->efuse_usedbytes = efuse_utilized;
+        efuse_usage = (u8)((efuse_utilized * 100) / EFUSE_REAL_CONTENT_LEN);
+        rtlefuse->efuse_usedpercentage = efuse_usage;
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_EFUSE_BYTES,
+                                      (u8 *)&efuse_utilized);
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_EFUSE_USAGE,
+                                      (u8 *)&efuse_usage);
+}
+
+bool efuse_shadow_update_chk(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 section_idx, i, Base;
+        u16 words_need = 0, hdr_num = 0, totalbytes, efuse_used;
+        bool bwordchanged, bresult = true;
+
+        for (section_idx = 0; section_idx < 16; section_idx++) {
+                Base = section_idx * 8;
+                bwordchanged = false;
+
+                for (i = 0; i < 8; i = i + 2) {
+                        if ((rtlefuse->efuse_map[EFUSE_INIT_MAP][Base + i] !=
+                             rtlefuse->efuse_map[EFUSE_MODIFY_MAP][Base + i]) ||
+                            (rtlefuse->efuse_map[EFUSE_INIT_MAP][Base + i + 1] !=
+                             rtlefuse->efuse_map[EFUSE_MODIFY_MAP][Base + i +
+                                                                   1])) {
+                                words_need++;
+                                bwordchanged = true;
+                        }
+                }
+
+                if (bwordchanged == true)
+                        hdr_num++;
+        }
+
+        totalbytes = hdr_num + words_need * 2;
+        efuse_used = rtlefuse->efuse_usedbytes;
+
+        if ((totalbytes + efuse_used) >=
+            (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))
+                bresult = false;
+
+        RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                 ("efuse_shadow_update_chk(): totalbytes(%#x), "
+                  "hdr_num(%#x), words_need(%#x), efuse_used(%d)\n",
+                  totalbytes, hdr_num, words_need, efuse_used));
+
+        return bresult;
+}
+
+void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
+                       u16 offset, u32 *value)
+{
+        if (type == 1)
+                efuse_shadow_read_1byte(hw, offset, (u8 *) value);
+        else if (type == 2)
+                efuse_shadow_read_2byte(hw, offset, (u16 *) value);
+        else if (type == 4)
+                efuse_shadow_read_4byte(hw, offset, (u32 *) value);
+
+}
+
+void efuse_shadow_write(struct ieee80211_hw *hw, u8 type, u16 offset,
+                                u32 value)
+{
+        if (type == 1)
+                efuse_shadow_write_1byte(hw, offset, (u8) value);
+        else if (type == 2)
+                efuse_shadow_write_2byte(hw, offset, (u16) value);
+        else if (type == 4)
+                efuse_shadow_write_4byte(hw, offset, (u32) value);
+
+}
+
+bool efuse_shadow_update(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u16 i, offset, base;
+        u8 word_en = 0x0F;
+        u8 first_pg = false;
+
+        RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, ("--->\n"));
+
+        if (!efuse_shadow_update_chk(hw)) {
+                efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
+                memcpy((void *)&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
+                       (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
+                       rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
+
+                RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                         ("<---efuse out of capacity!!\n"));
+                return false;
+        }
+        efuse_power_switch(hw, true, true);
+
+        for (offset = 0; offset < 16; offset++) {
+
+                word_en = 0x0F;
+                base = offset * 8;
+
+                for (i = 0; i < 8; i++) {
+                        if (first_pg == true) {
+
+                                word_en &= ~(BIT(i / 2));
+
+                                rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] =
+                                    rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i];
+                        } else {
+
+                                if (rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] !=
+                                    rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i]) {
+                                        word_en &= ~(BIT(i / 2));
+
+                                        rtlefuse->efuse_map[EFUSE_INIT_MAP][base + i] =
+                                            rtlefuse->efuse_map[EFUSE_MODIFY_MAP][base + i];
+                                }
+                        }
+                }
+
+                if (word_en != 0x0F) {
+                        u8 tmpdata[8];
+                        memcpy((void *)tmpdata,
+                               (void *)(&rtlefuse->
+                                        efuse_map[EFUSE_MODIFY_MAP][base]), 8);
+                        RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD,
+                                      ("U-efuse\n"), tmpdata, 8);
+
+                        if (!efuse_pg_packet_write(hw, (u8) offset, word_en,
+                                                   tmpdata)) {
+                                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                         ("PG section(%#x) fail!!\n", offset));
+                                break;
+                        }
+                }
+
+        }
+
+        efuse_power_switch(hw, true, false);
+        efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
+
+        memcpy((void *)&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
+               (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
+               rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
+
+        RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, ("<---\n"));
+        return true;
+}
+
+void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        if (rtlefuse->autoload_failflag == true) {
+                memset((void *)(&rtlefuse->efuse_map[EFUSE_INIT_MAP][0]), 128,
+                       0xFF);
+        } else
+                efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]);
+
+        memcpy((void *)&rtlefuse->efuse_map[EFUSE_MODIFY_MAP][0],
+               (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
+               rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]);
+
+}
+EXPORT_SYMBOL(rtl_efuse_shadow_map_update);
+
+void efuse_force_write_vendor_Id(struct ieee80211_hw *hw)
+{
+        u8 tmpdata[8] = { 0xFF, 0xFF, 0xEC, 0x10, 0xFF, 0xFF, 0xFF, 0xFF };
+
+        efuse_power_switch(hw, true, true);
+
+        efuse_pg_packet_write(hw, 1, 0xD, tmpdata);
+
+        efuse_power_switch(hw, true, false);
+
+}
+
+void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx)
+{
+}
+
+static void efuse_shadow_read_1byte(struct ieee80211_hw *hw,
+                                    u16 offset, u8 *value)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
+}
+
+static void efuse_shadow_read_2byte(struct ieee80211_hw *hw,
+                                    u16 offset, u16 *value)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
+        *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] << 8;
+
+}
+
+static void efuse_shadow_read_4byte(struct ieee80211_hw *hw,
+                                    u16 offset, u32 *value)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        *value = rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset];
+        *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] << 8;
+        *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 2] << 16;
+        *value |= rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 3] << 24;
+}
+
+static void efuse_shadow_write_1byte(struct ieee80211_hw *hw,
+                                     u16 offset, u8 value)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] = value;
+}
+
+static void efuse_shadow_write_2byte(struct ieee80211_hw *hw,
+                                     u16 offset, u16 value)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] = value & 0x00FF;
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] = value >> 8;
+
+}
+
+static void efuse_shadow_write_4byte(struct ieee80211_hw *hw,
+                                     u16 offset, u32 value)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset] =
+            (u8) (value & 0x000000FF);
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 1] =
+            (u8) ((value >> 8) & 0x0000FF);
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 2] =
+            (u8) ((value >> 16) & 0x00FF);
+        rtlefuse->efuse_map[EFUSE_MODIFY_MAP][offset + 3] =
+            (u8) ((value >> 24) & 0xFF);
+
+}
+
+static int efuse_one_byte_read(struct ieee80211_hw *hw, u16 addr, u8 *data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 tmpidx = 0;
+        int bresult;
+
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1,
+                       (u8) (addr & 0xff));
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
+                       ((u8) ((addr >> 8) & 0x03)) |
+                       (rtl_read_byte(rtlpriv,
+                                      rtlpriv->cfg->maps[EFUSE_CTRL] + 2) &
+                        0xFC));
+
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0x72);
+
+        while (!(0x80 & rtl_read_byte(rtlpriv,
+                                      rtlpriv->cfg->maps[EFUSE_CTRL] + 3))
+               && (tmpidx < 100)) {
+                tmpidx++;
+        }
+
+        if (tmpidx < 100) {
+                *data = rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL]);
+                bresult = true;
+        } else {
+                *data = 0xff;
+                bresult = false;
+        }
+        return bresult;
+}
+
+static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr, u8 data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 tmpidx = 0;
+        bool bresult;
+
+        RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                 ("Addr = %x Data=%x\n", addr, data));
+
+        rtl_write_byte(rtlpriv,
+                       rtlpriv->cfg->maps[EFUSE_CTRL] + 1, (u8) (addr & 0xff));
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 2,
+                       (rtl_read_byte(rtlpriv,
+                         rtlpriv->cfg->maps[EFUSE_CTRL] +
+                         2) & 0xFC) | (u8) ((addr >> 8) & 0x03));
+
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], data);
+        rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 3, 0xF2);
+
+        while ((0x80 & rtl_read_byte(rtlpriv,
+                                     rtlpriv->cfg->maps[EFUSE_CTRL] + 3))
+               && (tmpidx < 100)) {
+                tmpidx++;
+        }
+
+        if (tmpidx < 100)
+                bresult = true;
+        else
+                bresult = false;
+
+        return bresult;
+}
+
+static void efuse_read_all_map(struct ieee80211_hw *hw, u8 * efuse)
+{
+        efuse_power_switch(hw, false, true);
+        read_efuse(hw, 0, 128, efuse);
+        efuse_power_switch(hw, false, false);
+}
+
+static void efuse_read_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
+                                u8 efuse_data, u8 offset, u8 *tmpdata,
+                                u8 *readstate)
+{
+        bool bdataempty = true;
+        u8 hoffset;
+        u8 tmpidx;
+        u8 hworden;
+        u8 word_cnts;
+
+        hoffset = (efuse_data >> 4) & 0x0F;
+        hworden = efuse_data & 0x0F;
+        word_cnts = efuse_calculate_word_cnts(hworden);
+
+        if (hoffset == offset) {
+                for (tmpidx = 0; tmpidx < word_cnts * 2; tmpidx++) {
+                        if (efuse_one_byte_read(hw, *efuse_addr + 1 + tmpidx,
+                            &efuse_data)) {
+                                tmpdata[tmpidx] = efuse_data;
+                                if (efuse_data != 0xff)
+                                        bdataempty = true;
+                        }
+                }
+
+                if (bdataempty == true)
+                        *readstate = PG_STATE_DATA;
+                else {
+                        *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
+                        *readstate = PG_STATE_HEADER;
+                }
+
+        } else {
+                *efuse_addr = *efuse_addr + (word_cnts * 2) + 1;
+                *readstate = PG_STATE_HEADER;
+        }
+}
+
+static int efuse_pg_packet_read(struct ieee80211_hw *hw, u8 offset, u8 *data)
+{
+        u8 readstate = PG_STATE_HEADER;
+
+        bool bcontinual = true;
+
+        u8 efuse_data, word_cnts = 0;
+        u16 efuse_addr = 0;
+        u8 hworden;
+        u8 tmpdata[8];
+
+        if (data == NULL)
+                return false;
+        if (offset > 15)
+                return false;
+
+        memset((void *)data, PGPKT_DATA_SIZE * sizeof(u8), 0xff);
+        memset((void *)tmpdata, PGPKT_DATA_SIZE * sizeof(u8), 0xff);
+
+        while (bcontinual && (efuse_addr < EFUSE_MAX_SIZE)) {
+                if (readstate & PG_STATE_HEADER) {
+                        if (efuse_one_byte_read(hw, efuse_addr, &efuse_data)
+                            && (efuse_data != 0xFF))
+                                efuse_read_data_case1(hw, &efuse_addr,
+                                                      efuse_data,
+                                                      offset, tmpdata,
+                                                      &readstate);
+                        else
+                                bcontinual = false;
+                } else if (readstate & PG_STATE_DATA) {
+                        efuse_word_enable_data_read(hworden, tmpdata, data);
+                        efuse_addr = efuse_addr + (word_cnts * 2) + 1;
+                        readstate = PG_STATE_HEADER;
+                }
+
+        }
+
+        if ((data[0] == 0xff) && (data[1] == 0xff) &&
+            (data[2] == 0xff) && (data[3] == 0xff) &&
+            (data[4] == 0xff) && (data[5] == 0xff) &&
+            (data[6] == 0xff) && (data[7] == 0xff))
+                return false;
+        else
+                return true;
+
+}
+
+static void efuse_write_data_case1(struct ieee80211_hw *hw, u16 *efuse_addr,
+                                u8 efuse_data, u8 offset, int *bcontinual,
+                                u8 *write_state, struct pgpkt_struct target_pkt,
+                                int *repeat_times, int *bresult, u8 word_en)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct pgpkt_struct tmp_pkt;
+        int bdataempty = true;
+        u8 originaldata[8 * sizeof(u8)];
+        u8 badworden = 0x0F;
+        u8 match_word_en, tmp_word_en;
+        u8 tmpindex;
+        u8 tmp_header = efuse_data;
+        u8 tmp_word_cnts;
+
+        tmp_pkt.offset = (tmp_header >> 4) & 0x0F;
+        tmp_pkt.word_en = tmp_header & 0x0F;
+        tmp_word_cnts = efuse_calculate_word_cnts(tmp_pkt.word_en);
+
+        if (tmp_pkt.offset != target_pkt.offset) {
+                efuse_addr = efuse_addr + (tmp_word_cnts * 2) + 1;
+                *write_state = PG_STATE_HEADER;
+        } else {
+                for (tmpindex = 0; tmpindex < (tmp_word_cnts * 2); tmpindex++) {
+                        u16 address = *efuse_addr + 1 + tmpindex;
+                        if (efuse_one_byte_read(hw, address,
+                             &efuse_data) && (efuse_data != 0xFF))
+                                bdataempty = false;
+                }
+
+                if (bdataempty == false) {
+                        efuse_addr = efuse_addr + (tmp_word_cnts * 2) + 1;
+                        *write_state = PG_STATE_HEADER;
+                } else {
+                        match_word_en = 0x0F;
+                        if (!((target_pkt.word_en & BIT(0)) |
+                             (tmp_pkt.word_en & BIT(0))))
+                                match_word_en &= (~BIT(0));
+
+                        if (!((target_pkt.word_en & BIT(1)) |
+                             (tmp_pkt.word_en & BIT(1))))
+                                match_word_en &= (~BIT(1));
+
+                        if (!((target_pkt.word_en & BIT(2)) |
+                             (tmp_pkt.word_en & BIT(2))))
+                                match_word_en &= (~BIT(2));
+
+                        if (!((target_pkt.word_en & BIT(3)) |
+                             (tmp_pkt.word_en & BIT(3))))
+                                match_word_en &= (~BIT(3));
+
+                        if ((match_word_en & 0x0F) != 0x0F) {
+                                badworden = efuse_word_enable_data_write(
+                                                            hw, *efuse_addr + 1,
+                                                            tmp_pkt.word_en,
+                                                            target_pkt.data);
+
+                                if (0x0F != (badworden & 0x0F)) {
+                                        u8 reorg_offset = offset;
+                                        u8 reorg_worden = badworden;
+                                        efuse_pg_packet_write(hw, reorg_offset,
+                                                               reorg_worden,
+                                                               originaldata);
+                                }
+
+                                tmp_word_en = 0x0F;
+                                if ((target_pkt.word_en & BIT(0)) ^
+                                    (match_word_en & BIT(0)))
+                                        tmp_word_en &= (~BIT(0));
+
+                                if ((target_pkt.word_en & BIT(1)) ^
+                                    (match_word_en & BIT(1)))
+                                        tmp_word_en &= (~BIT(1));
+
+                                if ((target_pkt.word_en & BIT(2)) ^
+                                        (match_word_en & BIT(2)))
+                                        tmp_word_en &= (~BIT(2));
+
+                                if ((target_pkt.word_en & BIT(3)) ^
+                                    (match_word_en & BIT(3)))
+                                        tmp_word_en &= (~BIT(3));
+
+                                if ((tmp_word_en & 0x0F) != 0x0F) {
+                                        *efuse_addr = efuse_get_current_size(hw);
+                                        target_pkt.offset = offset;
+                                        target_pkt.word_en = tmp_word_en;
+                                } else
+                                        *bcontinual = false;
+                                *write_state = PG_STATE_HEADER;
+                                *repeat_times += 1;
+                                if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
+                                        *bcontinual = false;
+                                        *bresult = false;
+                                }
+                        } else {
+                                *efuse_addr += (2 * tmp_word_cnts) + 1;
+                                target_pkt.offset = offset;
+                                target_pkt.word_en = word_en;
+                                *write_state = PG_STATE_HEADER;
+                        }
+                }
+        }
+        RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, ("efuse PG_STATE_HEADER-1\n"));
+}
+
+static void efuse_write_data_case2(struct ieee80211_hw *hw, u16 *efuse_addr,
+                                   int *bcontinual, u8 *write_state,
+                                   struct pgpkt_struct target_pkt,
+                                   int *repeat_times, int *bresult)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct pgpkt_struct tmp_pkt;
+        u8 pg_header;
+        u8 tmp_header;
+        u8 originaldata[8 * sizeof(u8)];
+        u8 tmp_word_cnts;
+        u8 badworden = 0x0F;
+
+        pg_header = ((target_pkt.offset << 4) & 0xf0) | target_pkt.word_en;
+        efuse_one_byte_write(hw, *efuse_addr, pg_header);
+        efuse_one_byte_read(hw, *efuse_addr, &tmp_header);
+
+        if (tmp_header == pg_header)
+                *write_state = PG_STATE_DATA;
+        else if (tmp_header == 0xFF) {
+                *write_state = PG_STATE_HEADER;
+                *repeat_times += 1;
+                if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
+                        *bcontinual = false;
+                        *bresult = false;
+                }
+        } else {
+                tmp_pkt.offset = (tmp_header >> 4) & 0x0F;
+                tmp_pkt.word_en = tmp_header & 0x0F;
+
+                tmp_word_cnts = efuse_calculate_word_cnts(tmp_pkt.word_en);
+
+                memset((void *)originaldata, 8 * sizeof(u8), 0xff);
+
+                if (efuse_pg_packet_read(hw, tmp_pkt.offset, originaldata)) {
+                        badworden = efuse_word_enable_data_write(hw,
+                                    *efuse_addr + 1, tmp_pkt.word_en,
+                                    originaldata);
+
+                        if (0x0F != (badworden & 0x0F)) {
+                                u8 reorg_offset = tmp_pkt.offset;
+                                u8 reorg_worden = badworden;
+                                efuse_pg_packet_write(hw, reorg_offset,
+                                                      reorg_worden,
+                                                      originaldata);
+                                *efuse_addr = efuse_get_current_size(hw);
+                         } else
+                                *efuse_addr = *efuse_addr + (tmp_word_cnts * 2)
+                                              + 1;
+                } else
+                        *efuse_addr = *efuse_addr + (tmp_word_cnts * 2) + 1;
+
+                *write_state = PG_STATE_HEADER;
+                *repeat_times += 1;
+                if (*repeat_times > EFUSE_REPEAT_THRESHOLD_) {
+                        *bcontinual = false;
+                        *bresult = false;
+                }
+
+                RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
+                        ("efuse PG_STATE_HEADER-2\n"));
+        }
+}
+
+static int efuse_pg_packet_write(struct ieee80211_hw *hw,
+                                 u8 offset, u8 word_en, u8 *data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct pgpkt_struct target_pkt;
+        u8 write_state = PG_STATE_HEADER;
+        int bcontinual = true, bdataempty = true, bresult = true;
+        u16 efuse_addr = 0;
+        u8 efuse_data;
+        u8 target_word_cnts = 0;
+        u8 badworden = 0x0F;
+        static int repeat_times;
+
+        if (efuse_get_current_size(hw) >=
+            (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES)) {
+                RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
+                        ("efuse_pg_packet_write error\n"));
+                return false;
+        }
+
+        target_pkt.offset = offset;
+        target_pkt.word_en = word_en;
+
+        memset((void *)target_pkt.data, 8 * sizeof(u8), 0xFF);
+
+        efuse_word_enable_data_read(word_en, data, target_pkt.data);
+        target_word_cnts = efuse_calculate_word_cnts(target_pkt.word_en);
+
+        RTPRINT(rtlpriv, FEEPROM, EFUSE_PG, ("efuse Power ON\n"));
+
+        while (bcontinual && (efuse_addr <
+               (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES))) {
+
+                if (write_state == PG_STATE_HEADER) {
+                        bdataempty = true;
+                        badworden = 0x0F;
+                        RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
+                                ("efuse PG_STATE_HEADER\n"));
+
+                        if (efuse_one_byte_read(hw, efuse_addr, &efuse_data) &&
+                            (efuse_data != 0xFF))
+                                efuse_write_data_case1(hw, &efuse_addr,
+                                                       efuse_data, offset,
+                                                       &bcontinual,
+                                                       &write_state, target_pkt,
+                                                       &repeat_times, &bresult,
+                                                       word_en);
+                        else
+                                efuse_write_data_case2(hw, &efuse_addr,
+                                                       &bcontinual,
+                                                       &write_state,
+                                                       target_pkt,
+                                                       &repeat_times,
+                                                       &bresult);
+
+                } else if (write_state == PG_STATE_DATA) {
+                        RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
+                                ("efuse PG_STATE_DATA\n"));
+                        badworden = 0x0f;
+                        badworden =
+                            efuse_word_enable_data_write(hw, efuse_addr + 1,
+                                                         target_pkt.word_en,
+                                                         target_pkt.data);
+
+                        if ((badworden & 0x0F) == 0x0F) {
+                                bcontinual = false;
+                        } else {
+                                efuse_addr =
+                                    efuse_addr + (2 * target_word_cnts) + 1;
+
+                                target_pkt.offset = offset;
+                                target_pkt.word_en = badworden;
+                                target_word_cnts =
+                                    efuse_calculate_word_cnts(target_pkt.
+                                                              word_en);
+                                write_state = PG_STATE_HEADER;
+                                repeat_times++;
+                                if (repeat_times > EFUSE_REPEAT_THRESHOLD_) {
+                                        bcontinual = false;
+                                        bresult = false;
+                                }
+                                RTPRINT(rtlpriv, FEEPROM, EFUSE_PG,
+                                        ("efuse PG_STATE_HEADER-3\n"));
+                        }
+                }
+        }
+
+        if (efuse_addr >= (EFUSE_MAX_SIZE - EFUSE_OOB_PROTECT_BYTES)) {
+                RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                         ("efuse_addr(%#x) Out of size!!\n", efuse_addr));
+        }
+
+        return true;
+}
+
+static void efuse_word_enable_data_read(u8 word_en,
+                                        u8 *sourdata, u8 *targetdata)
+{
+        if (!(word_en & BIT(0))) {
+                targetdata[0] = sourdata[0];
+                targetdata[1] = sourdata[1];
+        }
+
+        if (!(word_en & BIT(1))) {
+                targetdata[2] = sourdata[2];
+                targetdata[3] = sourdata[3];
+        }
+
+        if (!(word_en & BIT(2))) {
+                targetdata[4] = sourdata[4];
+                targetdata[5] = sourdata[5];
+        }
+
+        if (!(word_en & BIT(3))) {
+                targetdata[6] = sourdata[6];
+                targetdata[7] = sourdata[7];
+        }
+}
+
+static u8 efuse_word_enable_data_write(struct ieee80211_hw *hw,
+                                       u16 efuse_addr, u8 word_en, u8 *data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u16 tmpaddr;
+        u16 start_addr = efuse_addr;
+        u8 badworden = 0x0F;
+        u8 tmpdata[8];
+
+        memset((void *)tmpdata, PGPKT_DATA_SIZE, 0xff);
+        RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD,
+                 ("word_en = %x efuse_addr=%x\n", word_en, efuse_addr));
+
+        if (!(word_en & BIT(0))) {
+                tmpaddr = start_addr;
+                efuse_one_byte_write(hw, start_addr++, data[0]);
+                efuse_one_byte_write(hw, start_addr++, data[1]);
+
+                efuse_one_byte_read(hw, tmpaddr, &tmpdata[0]);
+                efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[1]);
+                if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
+                        badworden &= (~BIT(0));
+        }
+
+        if (!(word_en & BIT(1))) {
+                tmpaddr = start_addr;
+                efuse_one_byte_write(hw, start_addr++, data[2]);
+                efuse_one_byte_write(hw, start_addr++, data[3]);
+
+                efuse_one_byte_read(hw, tmpaddr, &tmpdata[2]);
+                efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[3]);
+                if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
+                        badworden &= (~BIT(1));
+        }
+
+        if (!(word_en & BIT(2))) {
+                tmpaddr = start_addr;
+                efuse_one_byte_write(hw, start_addr++, data[4]);
+                efuse_one_byte_write(hw, start_addr++, data[5]);
+
+                efuse_one_byte_read(hw, tmpaddr, &tmpdata[4]);
+                efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[5]);
+                if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
+                        badworden &= (~BIT(2));
+        }
+
+        if (!(word_en & BIT(3))) {
+                tmpaddr = start_addr;
+                efuse_one_byte_write(hw, start_addr++, data[6]);
+                efuse_one_byte_write(hw, start_addr++, data[7]);
+
+                efuse_one_byte_read(hw, tmpaddr, &tmpdata[6]);
+                efuse_one_byte_read(hw, tmpaddr + 1, &tmpdata[7]);
+                if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
+                        badworden &= (~BIT(3));
+        }
+
+        return badworden;
+}
+
+static void efuse_power_switch(struct ieee80211_hw *hw, u8 bwrite, u8 pwrstate)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 tempval;
+        u16 tmpV16;
+
+        if (pwrstate == true) {
+                tmpV16 = rtl_read_word(rtlpriv,
+                                       rtlpriv->cfg->maps[SYS_ISO_CTRL]);
+                if (!(tmpV16 & rtlpriv->cfg->maps[EFUSE_PWC_EV12V])) {
+                        tmpV16 |= rtlpriv->cfg->maps[EFUSE_PWC_EV12V];
+                        rtl_write_word(rtlpriv,
+                                       rtlpriv->cfg->maps[SYS_ISO_CTRL],
+                                       tmpV16);
+                }
+
+                tmpV16 = rtl_read_word(rtlpriv,
+                                       rtlpriv->cfg->maps[SYS_FUNC_EN]);
+                if (!(tmpV16 & rtlpriv->cfg->maps[EFUSE_FEN_ELDR])) {
+                        tmpV16 |= rtlpriv->cfg->maps[EFUSE_FEN_ELDR];
+                        rtl_write_word(rtlpriv,
+                                       rtlpriv->cfg->maps[SYS_FUNC_EN], tmpV16);
+                }
+
+                tmpV16 = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_CLK]);
+                if ((!(tmpV16 & rtlpriv->cfg->maps[EFUSE_LOADER_CLK_EN])) ||
+                    (!(tmpV16 & rtlpriv->cfg->maps[EFUSE_ANA8M]))) {
+                        tmpV16 |= (rtlpriv->cfg->maps[EFUSE_LOADER_CLK_EN] |
+                                   rtlpriv->cfg->maps[EFUSE_ANA8M]);
+                        rtl_write_word(rtlpriv,
+                                       rtlpriv->cfg->maps[SYS_CLK], tmpV16);
+                }
+        }
+
+        if (pwrstate == true) {
+                if (bwrite == true) {
+                        tempval = rtl_read_byte(rtlpriv,
+                                                rtlpriv->cfg->maps[EFUSE_TEST] +
+                                                3);
+                        tempval &= 0x0F;
+                        tempval |= (VOLTAGE_V25 << 4);
+                        rtl_write_byte(rtlpriv,
+                                       rtlpriv->cfg->maps[EFUSE_TEST] + 3,
+                                       (tempval | 0x80));
+                }
+
+        } else {
+                if (bwrite == true) {
+                        tempval = rtl_read_byte(rtlpriv,
+                                                rtlpriv->cfg->maps[EFUSE_TEST] +
+                                                3);
+                        rtl_write_byte(rtlpriv,
+                                       rtlpriv->cfg->maps[EFUSE_TEST] + 3,
+                                       (tempval & 0x7F));
+                }
+
+        }
+
+}
+
+static u16 efuse_get_current_size(struct ieee80211_hw *hw)
+{
+        int bcontinual = true;
+        u16 efuse_addr = 0;
+        u8 hoffset, hworden;
+        u8 efuse_data, word_cnts;
+
+        while (bcontinual && efuse_one_byte_read(hw, efuse_addr, &efuse_data)
+               && (efuse_addr < EFUSE_MAX_SIZE)) {
+                if (efuse_data != 0xFF) {
+                        hoffset = (efuse_data >> 4) & 0x0F;
+                        hworden = efuse_data & 0x0F;
+                        word_cnts = efuse_calculate_word_cnts(hworden);
+                        efuse_addr = efuse_addr + (word_cnts * 2) + 1;
+                } else {
+                        bcontinual = false;
+                }
+        }
+
+        return efuse_addr;
+}
+
+static u8 efuse_calculate_word_cnts(u8 word_en)
+{
+        u8 word_cnts = 0;
+        if (!(word_en & BIT(0)))
+                word_cnts++;
+        if (!(word_en & BIT(1)))
+                word_cnts++;
+        if (!(word_en & BIT(2)))
+                word_cnts++;
+        if (!(word_en & BIT(3)))
+                word_cnts++;
+        return word_cnts;
+}
+
+void efuse_reset_loader(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u16 tmp_u2b;
+
+        tmp_u2b = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN]);
+        rtl_write_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN],
+                       (tmp_u2b & ~(BIT(12))));
+        udelay(10000);
+        rtl_write_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN],
+                       (tmp_u2b | BIT(12)));
+        udelay(10000);
+}
+
+bool efuse_program_map(struct ieee80211_hw *hw, char *p_filename, u8 tabletype)
+{
+        return true;
+}
diff --git a/drivers/net/wireless/rtlwifi/efuse.h b/drivers/net/wireless/rtlwifi/efuse.h
new file mode 100644
index 000000000000..2d39a4df181b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/efuse.h
@@ -0,0 +1,124 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL_EFUSE_H_
+#define __RTL_EFUSE_H_
+
+#define EFUSE_REAL_CONTENT_LEN          512
+#define EFUSE_MAP_LEN                   128
+#define EFUSE_MAX_SECTION               16
+#define EFUSE_MAX_WORD_UNIT             4
+
+#define EFUSE_INIT_MAP                  0
+#define EFUSE_MODIFY_MAP                1
+
+#define PG_STATE_HEADER                 0x01
+#define PG_STATE_WORD_0                 0x02
+#define PG_STATE_WORD_1                 0x04
+#define PG_STATE_WORD_2                 0x08
+#define PG_STATE_WORD_3                 0x10
+#define PG_STATE_DATA                   0x20
+
+#define PG_SWBYTE_H                     0x01
+#define PG_SWBYTE_L                     0x02
+
+#define _POWERON_DELAY_
+#define _PRE_EXECUTE_READ_CMD_
+
+#define EFUSE_REPEAT_THRESHOLD_         3
+
+struct efuse_map {
+        u8 offset;
+        u8 word_start;
+        u8 byte_start;
+        u8 byte_cnts;
+};
+
+struct pgpkt_struct {
+        u8 offset;
+        u8 word_en;
+        u8 data[8];
+};
+
+enum efuse_data_item {
+        EFUSE_CHIP_ID = 0,
+        EFUSE_LDO_SETTING,
+        EFUSE_CLK_SETTING,
+        EFUSE_SDIO_SETTING,
+        EFUSE_CCCR,
+        EFUSE_SDIO_MODE,
+        EFUSE_OCR,
+        EFUSE_F0CIS,
+        EFUSE_F1CIS,
+        EFUSE_MAC_ADDR,
+        EFUSE_EEPROM_VER,
+        EFUSE_CHAN_PLAN,
+        EFUSE_TXPW_TAB
+};
+
+enum {
+        VOLTAGE_V25 = 0x03,
+        LDOE25_SHIFT = 28,
+};
+
+struct efuse_priv {
+        u8 id[2];
+        u8 ldo_setting[2];
+        u8 clk_setting[2];
+        u8 cccr;
+        u8 sdio_mode;
+        u8 ocr[3];
+        u8 cis0[17];
+        u8 cis1[48];
+        u8 mac_addr[6];
+        u8 eeprom_verno;
+        u8 channel_plan;
+        u8 tx_power_b[14];
+        u8 tx_power_g[14];
+};
+
+extern void efuse_initialize(struct ieee80211_hw *hw);
+extern u8 efuse_read_1byte(struct ieee80211_hw *hw, u16 address);
+extern void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value);
+extern void read_efuse(struct ieee80211_hw *hw, u16 _offset,
+                       u16 _size_byte, u8 *pbuf);
+extern void efuse_shadow_read(struct ieee80211_hw *hw, u8 type,
+                              u16 offset, u32 *value);
+extern void efuse_shadow_write(struct ieee80211_hw *hw, u8 type,
+                               u16 offset, u32 value);
+extern bool efuse_shadow_update(struct ieee80211_hw *hw);
+extern bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
+extern void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
+extern void efuse_force_write_vendor_Id(struct ieee80211_hw *hw);
+extern void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
+extern bool efuse_program_map(struct ieee80211_hw *hw,
+                              char *p_filename, u8 tabletype);
+extern void efuse_reset_loader(struct ieee80211_hw *hw);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
new file mode 100644
index 000000000000..0fa36aa6701a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -0,0 +1,1945 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "core.h"
+#include "wifi.h"
+#include "pci.h"
+#include "base.h"
+#include "ps.h"
+
+static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
+        INTEL_VENDOR_ID,
+        ATI_VENDOR_ID,
+        AMD_VENDOR_ID,
+        SIS_VENDOR_ID
+};
+
+/* Update PCI dependent default settings*/
+static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
+
+        ppsc->reg_rfps_level = 0;
+        ppsc->b_support_aspm = 0;
+
+        /*Update PCI ASPM setting */
+        ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
+        switch (rtlpci->const_pci_aspm) {
+        case 0:
+                /*No ASPM */
+                break;
+
+        case 1:
+                /*ASPM dynamically enabled/disable. */
+                ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
+                break;
+
+        case 2:
+                /*ASPM with Clock Req dynamically enabled/disable. */
+                ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
+                                         RT_RF_OFF_LEVL_CLK_REQ);
+                break;
+
+        case 3:
+                /*
+                 * Always enable ASPM and Clock Req
+                 * from initialization to halt.
+                 * */
+                ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
+                ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
+                                         RT_RF_OFF_LEVL_CLK_REQ);
+                break;
+
+        case 4:
+                /*
+                 * Always enable ASPM without Clock Req
+                 * from initialization to halt.
+                 * */
+                ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
+                                          RT_RF_OFF_LEVL_CLK_REQ);
+                ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
+                break;
+        }
+
+        ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
+
+        /*Update Radio OFF setting */
+        switch (rtlpci->const_hwsw_rfoff_d3) {
+        case 1:
+                if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
+                        ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
+                break;
+
+        case 2:
+                if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
+                        ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
+                ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
+                break;
+
+        case 3:
+                ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
+                break;
+        }
+
+        /*Set HW definition to determine if it supports ASPM. */
+        switch (rtlpci->const_support_pciaspm) {
+        case 0:{
+                        /*Not support ASPM. */
+                        bool b_support_aspm = false;
+                        ppsc->b_support_aspm = b_support_aspm;
+                        break;
+                }
+        case 1:{
+                        /*Support ASPM. */
+                        bool b_support_aspm = true;
+                        bool b_support_backdoor = true;
+                        ppsc->b_support_aspm = b_support_aspm;
+
+                        /*if(priv->oem_id == RT_CID_TOSHIBA &&
+                           !priv->ndis_adapter.amd_l1_patch)
+                           b_support_backdoor = false; */
+
+                        ppsc->b_support_backdoor = b_support_backdoor;
+
+                        break;
+                }
+        case 2:
+                /*ASPM value set by chipset. */
+                if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
+                        bool b_support_aspm = true;
+                        ppsc->b_support_aspm = b_support_aspm;
+                }
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+}
+
+static bool _rtl_pci_platform_switch_device_pci_aspm(
+                        struct ieee80211_hw *hw,
+                        u8 value)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        bool bresult = false;
+
+        value |= 0x40;
+
+        pci_write_config_byte(rtlpci->pdev, 0x80, value);
+
+        return bresult;
+}
+
+/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
+static bool _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u8 buffer;
+        bool bresult = false;
+
+        buffer = value;
+
+        pci_write_config_byte(rtlpci->pdev, 0x81, value);
+        bresult = true;
+
+        return bresult;
+}
+
+/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
+static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
+        u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
+        u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
+        /*Retrieve original configuration settings. */
+        u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
+        u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
+                                pcibridge_linkctrlreg;
+        u16 aspmlevel = 0;
+
+        if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
+                         ("PCI(Bridge) UNKNOWN.\n"));
+
+                return;
+        }
+
+        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
+                RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
+                _rtl_pci_switch_clk_req(hw, 0x0);
+        }
+
+        if (1) {
+                /*for promising device will in L0 state after an I/O. */
+                u8 tmp_u1b;
+                pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
+        }
+
+        /*Set corresponding value. */
+        aspmlevel |= BIT(0) | BIT(1);
+        linkctrl_reg &= ~aspmlevel;
+        pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
+
+        _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
+        udelay(50);
+
+        /*4 Disable Pci Bridge ASPM */
+        rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
+                                     pcicfg_addrport + (num4bytes << 2));
+        rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
+
+        udelay(50);
+
+}
+
+/*
+ *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
+ *power saving We should follow the sequence to enable
+ *RTL8192SE first then enable Pci Bridge ASPM
+ *or the system will show bluescreen.
+ */
+static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u8 pcibridge_busnum = pcipriv->ndis_adapter.pcibridge_busnum;
+        u8 pcibridge_devnum = pcipriv->ndis_adapter.pcibridge_devnum;
+        u8 pcibridge_funcnum = pcipriv->ndis_adapter.pcibridge_funcnum;
+        u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
+        u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
+        u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
+        u16 aspmlevel;
+        u8 u_pcibridge_aspmsetting;
+        u8 u_device_aspmsetting;
+
+        if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
+                         ("PCI(Bridge) UNKNOWN.\n"));
+                return;
+        }
+
+        /*4 Enable Pci Bridge ASPM */
+        rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
+                                     pcicfg_addrport + (num4bytes << 2));
+
+        u_pcibridge_aspmsetting =
+            pcipriv->ndis_adapter.pcibridge_linkctrlreg |
+            rtlpci->const_hostpci_aspm_setting;
+
+        if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
+                u_pcibridge_aspmsetting &= ~BIT(0);
+
+        rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
+                 ("PlatformEnableASPM():PciBridge busnumber[%x], "
+                  "DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
+                  pcibridge_busnum, pcibridge_devnum, pcibridge_funcnum,
+                  (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
+                  u_pcibridge_aspmsetting));
+
+        udelay(50);
+
+        /*Get ASPM level (with/without Clock Req) */
+        aspmlevel = rtlpci->const_devicepci_aspm_setting;
+        u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
+
+        /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
+        /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
+
+        u_device_aspmsetting |= aspmlevel;
+
+        _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
+
+        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
+                _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
+                                             RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
+                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
+        }
+        udelay(200);
+}
+
+static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
+{
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
+
+        bool status = false;
+        u8 offset_e0;
+        unsigned offset_e4;
+
+        rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
+                        pcicfg_addrport + 0xE0);
+        rtl_pci_raw_write_port_uchar(PCI_CONF_DATA, 0xA0);
+
+        rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
+                        pcicfg_addrport + 0xE0);
+        rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &offset_e0);
+
+        if (offset_e0 == 0xA0) {
+                rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
+                                             pcicfg_addrport + 0xE4);
+                rtl_pci_raw_read_port_ulong(PCI_CONF_DATA, &offset_e4);
+                if (offset_e4 & BIT(23))
+                        status = true;
+        }
+
+        return status;
+}
+
+static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
+{
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
+        u32 pcicfg_addrport = pcipriv->ndis_adapter.pcicfg_addrport;
+        u8 linkctrl_reg;
+        u8 num4bBytes;
+
+        num4bBytes = (capabilityoffset + 0x10) / 4;
+
+        /*Read  Link Control Register */
+        rtl_pci_raw_write_port_ulong(PCI_CONF_ADDRESS,
+                                     pcicfg_addrport + (num4bBytes << 2));
+        rtl_pci_raw_read_port_uchar(PCI_CONF_DATA, &linkctrl_reg);
+
+        pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
+}
+
+static void rtl_pci_parse_configuration(struct pci_dev *pdev,
+                struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+
+        u8 tmp;
+        int pos;
+        u8 linkctrl_reg;
+
+        /*Link Control Register */
+        pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
+        pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
+        pcipriv->ndis_adapter.linkctrl_reg = linkctrl_reg;
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                 ("Link Control Register =%x\n",
+                  pcipriv->ndis_adapter.linkctrl_reg));
+
+        pci_read_config_byte(pdev, 0x98, &tmp);
+        tmp |= BIT(4);
+        pci_write_config_byte(pdev, 0x98, tmp);
+
+        tmp = 0x17;
+        pci_write_config_byte(pdev, 0x70f, tmp);
+}
+
+static void _rtl_pci_initialize_adapter_common(struct ieee80211_hw *hw)
+{
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        _rtl_pci_update_default_setting(hw);
+
+        if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
+                /*Always enable ASPM & Clock Req. */
+                rtl_pci_enable_aspm(hw);
+                RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
+        }
+
+}
+
+static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        /*close ASPM for AMD defaultly */
+        rtlpci->const_amdpci_aspm = 0;
+
+        /*
+         * ASPM PS mode.
+         * 0 - Disable ASPM,
+         * 1 - Enable ASPM without Clock Req,
+         * 2 - Enable ASPM with Clock Req,
+         * 3 - Alwyas Enable ASPM with Clock Req,
+         * 4 - Always Enable ASPM without Clock Req.
+         * set defult to RTL8192CE:3 RTL8192E:2
+         * */
+        rtlpci->const_pci_aspm = 3;
+
+        /*Setting for PCI-E device */
+        rtlpci->const_devicepci_aspm_setting = 0x03;
+
+        /*Setting for PCI-E bridge */
+        rtlpci->const_hostpci_aspm_setting = 0x02;
+
+        /*
+         * In Hw/Sw Radio Off situation.
+         * 0 - Default,
+         * 1 - From ASPM setting without low Mac Pwr,
+         * 2 - From ASPM setting with low Mac Pwr,
+         * 3 - Bus D3
+         * set default to RTL8192CE:0 RTL8192SE:2
+         */
+        rtlpci->const_hwsw_rfoff_d3 = 0;
+
+        /*
+         * This setting works for those device with
+         * backdoor ASPM setting such as EPHY setting.
+         * 0 - Not support ASPM,
+         * 1 - Support ASPM,
+         * 2 - According to chipset.
+         */
+        rtlpci->const_support_pciaspm = 1;
+
+        _rtl_pci_initialize_adapter_common(hw);
+}
+
+static void _rtl_pci_io_handler_init(struct device *dev,
+                                     struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->io.dev = dev;
+
+        rtlpriv->io.write8_async = pci_write8_async;
+        rtlpriv->io.write16_async = pci_write16_async;
+        rtlpriv->io.write32_async = pci_write32_async;
+
+        rtlpriv->io.read8_sync = pci_read8_sync;
+        rtlpriv->io.read16_sync = pci_read16_sync;
+        rtlpriv->io.read32_sync = pci_read32_sync;
+
+}
+
+static void _rtl_pci_io_handler_release(struct ieee80211_hw *hw)
+{
+}
+
+static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
+
+        while (skb_queue_len(&ring->queue)) {
+                struct rtl_tx_desc *entry = &ring->desc[ring->idx];
+                struct sk_buff *skb;
+                struct ieee80211_tx_info *info;
+
+                u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
+                                                          HW_DESC_OWN);
+
+                /*
+                 *beacon packet will only use the first
+                 *descriptor defautly,and the own may not
+                 *be cleared by the hardware
+                 */
+                if (own)
+                        return;
+                ring->idx = (ring->idx + 1) % ring->entries;
+
+                skb = __skb_dequeue(&ring->queue);
+                pci_unmap_single(rtlpci->pdev,
+                                 le32_to_cpu(rtlpriv->cfg->ops->
+                                             get_desc((u8 *) entry, true,
+                                                      HW_DESC_TXBUFF_ADDR)),
+                                 skb->len, PCI_DMA_TODEVICE);
+
+                RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
+                         ("new ring->idx:%d, "
+                          "free: skb_queue_len:%d, free: seq:%x\n",
+                          ring->idx,
+                          skb_queue_len(&ring->queue),
+                          *(u16 *) (skb->data + 22)));
+
+                info = IEEE80211_SKB_CB(skb);
+                ieee80211_tx_info_clear_status(info);
+
+                info->flags |= IEEE80211_TX_STAT_ACK;
+                /*info->status.rates[0].count = 1; */
+
+                ieee80211_tx_status_irqsafe(hw, skb);
+
+                if ((ring->entries - skb_queue_len(&ring->queue))
+                                == 2) {
+
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
+                                        ("more desc left, wake"
+                                         "skb_queue@%d,ring->idx = %d,"
+                                         "skb_queue_len = 0x%d\n",
+                                         prio, ring->idx,
+                                         skb_queue_len(&ring->queue)));
+
+                        ieee80211_wake_queue(hw,
+                                        skb_get_queue_mapping
+                                        (skb));
+                }
+
+                skb = NULL;
+        }
+
+        if (((rtlpriv->link_info.num_rx_inperiod +
+                rtlpriv->link_info.num_tx_inperiod) > 8) ||
+                (rtlpriv->link_info.num_rx_inperiod > 2)) {
+                rtl_lps_leave(hw);
+        }
+}
+
+static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
+
+        struct ieee80211_rx_status rx_status = { 0 };
+        unsigned int count = rtlpci->rxringcount;
+        u8 own;
+        u8 tmp_one;
+        u32 bufferaddress;
+        bool unicast = false;
+
+        struct rtl_stats stats = {
+                .signal = 0,
+                .noise = -98,
+                .rate = 0,
+        };
+
+        /*RX NORMAL PKT */
+        while (count--) {
+                /*rx descriptor */
+                struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
+                                rtlpci->rx_ring[rx_queue_idx].idx];
+                /*rx pkt */
+                struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
+                                rtlpci->rx_ring[rx_queue_idx].idx];
+
+                own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
+                                                       false, HW_DESC_OWN);
+
+                if (own) {
+                        /*wait data to be filled by hardware */
+                        return;
+                } else {
+                        struct ieee80211_hdr *hdr;
+                        u16 fc;
+                        struct sk_buff *new_skb = NULL;
+
+                        rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
+                                                         &rx_status,
+                                                         (u8 *) pdesc, skb);
+
+                        pci_unmap_single(rtlpci->pdev,
+                                         *((dma_addr_t *) skb->cb),
+                                         rtlpci->rxbuffersize,
+                                         PCI_DMA_FROMDEVICE);
+
+                        skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
+                                                         false,
+                                                         HW_DESC_RXPKT_LEN));
+                        skb_reserve(skb,
+                                    stats.rx_drvinfo_size + stats.rx_bufshift);
+
+                        /*
+                         *NOTICE This can not be use for mac80211,
+                         *this is done in mac80211 code,
+                         *if you done here sec DHCP will fail
+                         *skb_trim(skb, skb->len - 4);
+                         */
+
+                        hdr = (struct ieee80211_hdr *)(skb->data);
+                        fc = le16_to_cpu(hdr->frame_control);
+
+                        if (!stats.b_crc) {
+                                memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
+                                       sizeof(rx_status));
+
+                                if (is_broadcast_ether_addr(hdr->addr1))
+                                        ;/*TODO*/
+                                else {
+                                        if (is_multicast_ether_addr(hdr->addr1))
+                                                ;/*TODO*/
+                                        else {
+                                                unicast = true;
+                                                rtlpriv->stats.rxbytesunicast +=
+                                                    skb->len;
+                                        }
+                                }
+
+                                rtl_is_special_data(hw, skb, false);
+
+                                if (ieee80211_is_data(fc)) {
+                                        rtlpriv->cfg->ops->led_control(hw,
+                                                               LED_CTL_RX);
+
+                                        if (unicast)
+                                                rtlpriv->link_info.
+                                                    num_rx_inperiod++;
+                                }
+
+                                if (unlikely(!rtl_action_proc(hw, skb,
+                                    false))) {
+                                        dev_kfree_skb_any(skb);
+                                } else {
+                                        struct sk_buff *uskb = NULL;
+                                        u8 *pdata;
+                                        uskb = dev_alloc_skb(skb->len + 128);
+                                        memcpy(IEEE80211_SKB_RXCB(uskb),
+                                                        &rx_status,
+                                                        sizeof(rx_status));
+                                        pdata = (u8 *)skb_put(uskb, skb->len);
+                                        memcpy(pdata, skb->data, skb->len);
+                                        dev_kfree_skb_any(skb);
+
+                                        ieee80211_rx_irqsafe(hw, uskb);
+                                }
+                        } else {
+                                dev_kfree_skb_any(skb);
+                        }
+
+                        if (((rtlpriv->link_info.num_rx_inperiod +
+                                rtlpriv->link_info.num_tx_inperiod) > 8) ||
+                                (rtlpriv->link_info.num_rx_inperiod > 2)) {
+                                rtl_lps_leave(hw);
+                        }
+
+                        new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
+                        if (unlikely(!new_skb)) {
+                                RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV),
+                                         DBG_DMESG,
+                                         ("can't alloc skb for rx\n"));
+                                goto done;
+                        }
+                        skb = new_skb;
+                        /*skb->dev = dev; */
+
+                        rtlpci->rx_ring[rx_queue_idx].rx_buf[rtlpci->
+                                                             rx_ring
+                                                             [rx_queue_idx].
+                                                             idx] = skb;
+                        *((dma_addr_t *) skb->cb) =
+                            pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
+                                           rtlpci->rxbuffersize,
+                                           PCI_DMA_FROMDEVICE);
+
+                }
+done:
+                bufferaddress = cpu_to_le32(*((dma_addr_t *) skb->cb));
+                tmp_one = 1;
+                rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
+                                            HW_DESC_RXBUFF_ADDR,
+                                            (u8 *)&bufferaddress);
+                rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
+                                            (u8 *)&tmp_one);
+                rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
+                                            HW_DESC_RXPKT_LEN,
+                                            (u8 *)&rtlpci->rxbuffersize);
+
+                if (rtlpci->rx_ring[rx_queue_idx].idx ==
+                    rtlpci->rxringcount - 1)
+                        rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
+                                                    HW_DESC_RXERO,
+                                                    (u8 *)&tmp_one);
+
+                rtlpci->rx_ring[rx_queue_idx].idx =
+                    (rtlpci->rx_ring[rx_queue_idx].idx + 1) %
+                    rtlpci->rxringcount;
+        }
+
+}
+
+void _rtl_pci_tx_interrupt(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        int prio;
+
+        for (prio = 0; prio < RTL_PCI_MAX_TX_QUEUE_COUNT; prio++) {
+                struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
+
+                while (skb_queue_len(&ring->queue)) {
+                        struct rtl_tx_desc *entry = &ring->desc[ring->idx];
+                        struct sk_buff *skb;
+                        struct ieee80211_tx_info *info;
+                        u8 own;
+
+                        /*
+                         *beacon packet will only use the first
+                         *descriptor defautly, and the own may not
+                         *be cleared by the hardware, and
+                         *beacon will free in prepare beacon
+                         */
+                        if (prio == BEACON_QUEUE || prio == TXCMD_QUEUE ||
+                            prio == HCCA_QUEUE)
+                                break;
+
+                        own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)entry,
+                                                               true,
+                                                               HW_DESC_OWN);
+
+                        if (own)
+                                break;
+
+                        skb = __skb_dequeue(&ring->queue);
+                        pci_unmap_single(rtlpci->pdev,
+                                         le32_to_cpu(rtlpriv->cfg->ops->
+                                                     get_desc((u8 *) entry,
+                                                     true,
+                                                     HW_DESC_TXBUFF_ADDR)),
+                                         skb->len, PCI_DMA_TODEVICE);
+
+                        ring->idx = (ring->idx + 1) % ring->entries;
+
+                        info = IEEE80211_SKB_CB(skb);
+                        ieee80211_tx_info_clear_status(info);
+
+                        info->flags |= IEEE80211_TX_STAT_ACK;
+                        /*info->status.rates[0].count = 1; */
+
+                        ieee80211_tx_status_irqsafe(hw, skb);
+
+                        if ((ring->entries - skb_queue_len(&ring->queue))
+                            == 2 && prio != BEACON_QUEUE) {
+                                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                         ("more desc left, wake "
+                                          "skb_queue@%d,ring->idx = %d,"
+                                          "skb_queue_len = 0x%d\n",
+                                          prio, ring->idx,
+                                          skb_queue_len(&ring->queue)));
+
+                                ieee80211_wake_queue(hw,
+                                                     skb_get_queue_mapping
+                                                     (skb));
+                        }
+
+                        skb = NULL;
+                }
+        }
+}
+
+static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
+{
+        struct ieee80211_hw *hw = dev_id;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        unsigned long flags;
+        u32 inta = 0;
+        u32 intb = 0;
+
+        if (rtlpci->irq_enabled == 0)
+                return IRQ_HANDLED;
+
+        spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
+
+        /*read ISR: 4/8bytes */
+        rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
+
+        /*Shared IRQ or HW disappared */
+        if (!inta || inta == 0xffff)
+                goto done;
+
+        /*<1> beacon related */
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("beacon ok interrupt!\n"));
+        }
+
+        if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("beacon err interrupt!\n"));
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("beacon interrupt!\n"));
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_BcnInt]) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("prepare beacon for interrupt!\n"));
+                tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
+        }
+
+        /*<3> Tx related */
+        if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("IMR_TXFOVW!\n"));
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("Manage ok interrupt!\n"));
+                _rtl_pci_tx_isr(hw, MGNT_QUEUE);
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("HIGH_QUEUE ok interrupt!\n"));
+                _rtl_pci_tx_isr(hw, HIGH_QUEUE);
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
+                rtlpriv->link_info.num_tx_inperiod++;
+
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("BK Tx OK interrupt!\n"));
+                _rtl_pci_tx_isr(hw, BK_QUEUE);
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
+                rtlpriv->link_info.num_tx_inperiod++;
+
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("BE TX OK interrupt!\n"));
+                _rtl_pci_tx_isr(hw, BE_QUEUE);
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
+                rtlpriv->link_info.num_tx_inperiod++;
+
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("VI TX OK interrupt!\n"));
+                _rtl_pci_tx_isr(hw, VI_QUEUE);
+        }
+
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
+                rtlpriv->link_info.num_tx_inperiod++;
+
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
+                         ("Vo TX OK interrupt!\n"));
+                _rtl_pci_tx_isr(hw, VO_QUEUE);
+        }
+
+        /*<2> Rx related */
+        if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
+                RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, ("Rx ok interrupt!\n"));
+                tasklet_schedule(&rtlpriv->works.irq_tasklet);
+        }
+
+        if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("rx descriptor unavailable!\n"));
+                tasklet_schedule(&rtlpriv->works.irq_tasklet);
+        }
+
+        if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("rx overflow !\n"));
+                tasklet_schedule(&rtlpriv->works.irq_tasklet);
+        }
+
+        spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+        return IRQ_HANDLED;
+
+done:
+        spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+        return IRQ_HANDLED;
+}
+
+static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
+{
+        _rtl_pci_rx_interrupt(hw);
+}
+
+static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
+        struct ieee80211_hdr *hdr = NULL;
+        struct ieee80211_tx_info *info = NULL;
+        struct sk_buff *pskb = NULL;
+        struct rtl_tx_desc *pdesc = NULL;
+        unsigned int queue_index;
+        u8 temp_one = 1;
+
+        ring = &rtlpci->tx_ring[BEACON_QUEUE];
+        pskb = __skb_dequeue(&ring->queue);
+        if (pskb)
+                kfree_skb(pskb);
+
+        /*NB: the beacon data buffer must be 32-bit aligned. */
+        pskb = ieee80211_beacon_get(hw, mac->vif);
+        if (pskb == NULL)
+                return;
+        hdr = (struct ieee80211_hdr *)(pskb->data);
+        info = IEEE80211_SKB_CB(pskb);
+
+        queue_index = BEACON_QUEUE;
+
+        pdesc = &ring->desc[0];
+        rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
+                                        info, pskb, queue_index);
+
+        __skb_queue_tail(&ring->queue, pskb);
+
+        rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
+                                    (u8 *)&temp_one);
+
+        return;
+}
+
+static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u8 i;
+
+        for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
+                rtlpci->txringcount[i] = RT_TXDESC_NUM;
+
+        /*
+         *we just alloc 2 desc for beacon queue,
+         *because we just need first desc in hw beacon.
+         */
+        rtlpci->txringcount[BEACON_QUEUE] = 2;
+
+        /*
+         *BE queue need more descriptor for performance
+         *consideration or, No more tx desc will happen,
+         *and may cause mac80211 mem leakage.
+         */
+        rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
+
+        rtlpci->rxbuffersize = 9100;    /*2048/1024; */
+        rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;     /*64; */
+}
+
+static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
+                struct pci_dev *pdev)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        rtlpci->up_first_time = true;
+        rtlpci->being_init_adapter = false;
+
+        rtlhal->hw = hw;
+        rtlpci->pdev = pdev;
+
+        ppsc->b_inactiveps = false;
+        ppsc->b_leisure_ps = true;
+        ppsc->b_fwctrl_lps = true;
+        ppsc->b_reg_fwctrl_lps = 3;
+        ppsc->reg_max_lps_awakeintvl = 5;
+
+        if (ppsc->b_reg_fwctrl_lps == 1)
+                ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
+        else if (ppsc->b_reg_fwctrl_lps == 2)
+                ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
+        else if (ppsc->b_reg_fwctrl_lps == 3)
+                ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
+
+        /*Tx/Rx related var */
+        _rtl_pci_init_trx_var(hw);
+
+         /*IBSS*/ mac->beacon_interval = 100;
+
+         /*AMPDU*/ mac->min_space_cfg = 0;
+        mac->max_mss_density = 0;
+        /*set sane AMPDU defaults */
+        mac->current_ampdu_density = 7;
+        mac->current_ampdu_factor = 3;
+
+         /*QOS*/ rtlpci->acm_method = eAcmWay2_SW;
+
+        /*task */
+        tasklet_init(&rtlpriv->works.irq_tasklet,
+                     (void (*)(unsigned long))_rtl_pci_irq_tasklet,
+                     (unsigned long)hw);
+        tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
+                     (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
+                     (unsigned long)hw);
+}
+
+static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
+                                 unsigned int prio, unsigned int entries)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_tx_desc *ring;
+        dma_addr_t dma;
+        u32 nextdescaddress;
+        int i;
+
+        ring = pci_alloc_consistent(rtlpci->pdev,
+                                    sizeof(*ring) * entries, &dma);
+
+        if (!ring || (unsigned long)ring & 0xFF) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Cannot allocate TX ring (prio = %d)\n", prio));
+                return -ENOMEM;
+        }
+
+        memset(ring, 0, sizeof(*ring) * entries);
+        rtlpci->tx_ring[prio].desc = ring;
+        rtlpci->tx_ring[prio].dma = dma;
+        rtlpci->tx_ring[prio].idx = 0;
+        rtlpci->tx_ring[prio].entries = entries;
+        skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
+                 ("queue:%d, ring_addr:%p\n", prio, ring));
+
+        for (i = 0; i < entries; i++) {
+                nextdescaddress = cpu_to_le32((u32) dma +
+                                              ((i + 1) % entries) *
+                                              sizeof(*ring));
+
+                rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
+                                            true, HW_DESC_TX_NEXTDESC_ADDR,
+                                            (u8 *)&nextdescaddress);
+        }
+
+        return 0;
+}
+
+static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_rx_desc *entry = NULL;
+        int i, rx_queue_idx;
+        u8 tmp_one = 1;
+
+        /*
+         *rx_queue_idx 0:RX_MPDU_QUEUE
+         *rx_queue_idx 1:RX_CMD_QUEUE
+         */
+        for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
+             rx_queue_idx++) {
+                rtlpci->rx_ring[rx_queue_idx].desc =
+                    pci_alloc_consistent(rtlpci->pdev,
+                                         sizeof(*rtlpci->rx_ring[rx_queue_idx].
+                                                desc) * rtlpci->rxringcount,
+                                         &rtlpci->rx_ring[rx_queue_idx].dma);
+
+                if (!rtlpci->rx_ring[rx_queue_idx].desc ||
+                    (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("Cannot allocate RX ring\n"));
+                        return -ENOMEM;
+                }
+
+                memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
+                       sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
+                       rtlpci->rxringcount);
+
+                rtlpci->rx_ring[rx_queue_idx].idx = 0;
+
+                for (i = 0; i < rtlpci->rxringcount; i++) {
+                        struct sk_buff *skb =
+                            dev_alloc_skb(rtlpci->rxbuffersize);
+                        u32 bufferaddress;
+                        entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
+                        if (!skb)
+                                return 0;
+
+                        /*skb->dev = dev; */
+
+                        rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
+
+                        /*
+                         *just set skb->cb to mapping addr
+                         *for pci_unmap_single use
+                         */
+                        *((dma_addr_t *) skb->cb) =
+                            pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
+                                           rtlpci->rxbuffersize,
+                                           PCI_DMA_FROMDEVICE);
+
+                        bufferaddress = cpu_to_le32(*((dma_addr_t *)skb->cb));
+                        rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
+                                                    HW_DESC_RXBUFF_ADDR,
+                                                    (u8 *)&bufferaddress);
+                        rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
+                                                    HW_DESC_RXPKT_LEN,
+                                                    (u8 *)&rtlpci->
+                                                    rxbuffersize);
+                        rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
+                                                    HW_DESC_RXOWN,
+                                                    (u8 *)&tmp_one);
+                }
+
+                rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
+                                            HW_DESC_RXERO, (u8 *)&tmp_one);
+        }
+        return 0;
+}
+
+static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
+                unsigned int prio)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
+
+        while (skb_queue_len(&ring->queue)) {
+                struct rtl_tx_desc *entry = &ring->desc[ring->idx];
+                struct sk_buff *skb = __skb_dequeue(&ring->queue);
+
+                pci_unmap_single(rtlpci->pdev,
+                                 le32_to_cpu(rtlpriv->cfg->
+                                             ops->get_desc((u8 *) entry, true,
+                                                   HW_DESC_TXBUFF_ADDR)),
+                                 skb->len, PCI_DMA_TODEVICE);
+                kfree_skb(skb);
+                ring->idx = (ring->idx + 1) % ring->entries;
+        }
+
+        pci_free_consistent(rtlpci->pdev,
+                            sizeof(*ring->desc) * ring->entries,
+                            ring->desc, ring->dma);
+        ring->desc = NULL;
+}
+
+static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
+{
+        int i, rx_queue_idx;
+
+        /*rx_queue_idx 0:RX_MPDU_QUEUE */
+        /*rx_queue_idx 1:RX_CMD_QUEUE */
+        for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
+             rx_queue_idx++) {
+                for (i = 0; i < rtlpci->rxringcount; i++) {
+                        struct sk_buff *skb =
+                            rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
+                        if (!skb)
+                                continue;
+
+                        pci_unmap_single(rtlpci->pdev,
+                                         *((dma_addr_t *) skb->cb),
+                                         rtlpci->rxbuffersize,
+                                         PCI_DMA_FROMDEVICE);
+                        kfree_skb(skb);
+                }
+
+                pci_free_consistent(rtlpci->pdev,
+                                    sizeof(*rtlpci->rx_ring[rx_queue_idx].
+                                           desc) * rtlpci->rxringcount,
+                                    rtlpci->rx_ring[rx_queue_idx].desc,
+                                    rtlpci->rx_ring[rx_queue_idx].dma);
+                rtlpci->rx_ring[rx_queue_idx].desc = NULL;
+        }
+}
+
+static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        int ret;
+        int i;
+
+        ret = _rtl_pci_init_rx_ring(hw);
+        if (ret)
+                return ret;
+
+        for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
+                ret = _rtl_pci_init_tx_ring(hw, i,
+                                 rtlpci->txringcount[i]);
+                if (ret)
+                        goto err_free_rings;
+        }
+
+        return 0;
+
+err_free_rings:
+        _rtl_pci_free_rx_ring(rtlpci);
+
+        for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
+                if (rtlpci->tx_ring[i].desc)
+                        _rtl_pci_free_tx_ring(hw, i);
+
+        return 1;
+}
+
+static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u32 i;
+
+        /*free rx rings */
+        _rtl_pci_free_rx_ring(rtlpci);
+
+        /*free tx rings */
+        for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
+                _rtl_pci_free_tx_ring(hw, i);
+
+        return 0;
+}
+
+int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        int i, rx_queue_idx;
+        unsigned long flags;
+        u8 tmp_one = 1;
+
+        /*rx_queue_idx 0:RX_MPDU_QUEUE */
+        /*rx_queue_idx 1:RX_CMD_QUEUE */
+        for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
+             rx_queue_idx++) {
+                /*
+                 *force the rx_ring[RX_MPDU_QUEUE/
+                 *RX_CMD_QUEUE].idx to the first one
+                 */
+                if (rtlpci->rx_ring[rx_queue_idx].desc) {
+                        struct rtl_rx_desc *entry = NULL;
+
+                        for (i = 0; i < rtlpci->rxringcount; i++) {
+                                entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
+                                rtlpriv->cfg->ops->set_desc((u8 *) entry,
+                                                            false,
+                                                            HW_DESC_RXOWN,
+                                                            (u8 *)&tmp_one);
+                        }
+                        rtlpci->rx_ring[rx_queue_idx].idx = 0;
+                }
+        }
+
+        /*
+         *after reset, release previous pending packet,
+         *and force the  tx idx to the first one
+         */
+        spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
+        for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
+                if (rtlpci->tx_ring[i].desc) {
+                        struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
+
+                        while (skb_queue_len(&ring->queue)) {
+                                struct rtl_tx_desc *entry =
+                                    &ring->desc[ring->idx];
+                                struct sk_buff *skb =
+                                    __skb_dequeue(&ring->queue);
+
+                                pci_unmap_single(rtlpci->pdev,
+                                                 le32_to_cpu(rtlpriv->cfg->ops->
+                                                         get_desc((u8 *)
+                                                         entry,
+                                                         true,
+                                                         HW_DESC_TXBUFF_ADDR)),
+                                                 skb->len, PCI_DMA_TODEVICE);
+                                kfree_skb(skb);
+                                ring->idx = (ring->idx + 1) % ring->entries;
+                        }
+                        ring->idx = 0;
+                }
+        }
+
+        spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+
+        return 0;
+}
+
+unsigned int _rtl_mac_to_hwqueue(u16 fc,
+                unsigned int mac80211_queue_index)
+{
+        unsigned int hw_queue_index;
+
+        if (unlikely(ieee80211_is_beacon(fc))) {
+                hw_queue_index = BEACON_QUEUE;
+                goto out;
+        }
+
+        if (ieee80211_is_mgmt(fc)) {
+                hw_queue_index = MGNT_QUEUE;
+                goto out;
+        }
+
+        switch (mac80211_queue_index) {
+        case 0:
+                hw_queue_index = VO_QUEUE;
+                break;
+        case 1:
+                hw_queue_index = VI_QUEUE;
+                break;
+        case 2:
+                hw_queue_index = BE_QUEUE;;
+                break;
+        case 3:
+                hw_queue_index = BK_QUEUE;
+                break;
+        default:
+                hw_queue_index = BE_QUEUE;
+                RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
+                                  mac80211_queue_index));
+                break;
+        }
+
+out:
+        return hw_queue_index;
+}
+
+int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
+        struct rtl8192_tx_ring *ring;
+        struct rtl_tx_desc *pdesc;
+        u8 idx;
+        unsigned int queue_index, hw_queue;
+        unsigned long flags;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+        u16 fc = le16_to_cpu(hdr->frame_control);
+        u8 *pda_addr = hdr->addr1;
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        /*ssn */
+        u8 *qc = NULL;
+        u8 tid = 0;
+        u16 seq_number = 0;
+        u8 own;
+        u8 temp_one = 1;
+
+        if (ieee80211_is_mgmt(fc))
+                rtl_tx_mgmt_proc(hw, skb);
+        rtl_action_proc(hw, skb, true);
+
+        queue_index = skb_get_queue_mapping(skb);
+        hw_queue = _rtl_mac_to_hwqueue(fc, queue_index);
+
+        if (is_multicast_ether_addr(pda_addr))
+                rtlpriv->stats.txbytesmulticast += skb->len;
+        else if (is_broadcast_ether_addr(pda_addr))
+                rtlpriv->stats.txbytesbroadcast += skb->len;
+        else
+                rtlpriv->stats.txbytesunicast += skb->len;
+
+        spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
+
+        ring = &rtlpci->tx_ring[hw_queue];
+        if (hw_queue != BEACON_QUEUE)
+                idx = (ring->idx + skb_queue_len(&ring->queue)) %
+                                ring->entries;
+        else
+                idx = 0;
+
+        pdesc = &ring->desc[idx];
+        own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
+                        true, HW_DESC_OWN);
+
+        if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("No more TX desc@%d, ring->idx = %d,"
+                          "idx = %d, skb_queue_len = 0x%d\n",
+                          hw_queue, ring->idx, idx,
+                          skb_queue_len(&ring->queue)));
+
+                spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+                return skb->len;
+        }
+
+        /*
+         *if(ieee80211_is_nullfunc(fc)) {
+         *      spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+         *      return 1;
+         *}
+         */
+
+        if (ieee80211_is_data_qos(fc)) {
+                qc = ieee80211_get_qos_ctl(hdr);
+                tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
+
+                seq_number = mac->tids[tid].seq_number;
+                seq_number &= IEEE80211_SCTL_SEQ;
+                /*
+                 *hdr->seq_ctrl = hdr->seq_ctrl &
+                 *cpu_to_le16(IEEE80211_SCTL_FRAG);
+                 *hdr->seq_ctrl |= cpu_to_le16(seq_number);
+                 */
+
+                seq_number += 1;
+        }
+
+        if (ieee80211_is_data(fc))
+                rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
+
+        rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
+                                        info, skb, hw_queue);
+
+        __skb_queue_tail(&ring->queue, skb);
+
+        rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true,
+                                    HW_DESC_OWN, (u8 *)&temp_one);
+
+        if (!ieee80211_has_morefrags(hdr->frame_control)) {
+                if (qc)
+                        mac->tids[tid].seq_number = seq_number;
+        }
+
+        if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
+            hw_queue != BEACON_QUEUE) {
+
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
+                         ("less desc left, stop skb_queue@%d, "
+                          "ring->idx = %d,"
+                          "idx = %d, skb_queue_len = 0x%d\n",
+                          hw_queue, ring->idx, idx,
+                          skb_queue_len(&ring->queue)));
+
+                ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
+        }
+
+        spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+
+        rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
+
+        return 0;
+}
+
+void rtl_pci_deinit(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        _rtl_pci_deinit_trx_ring(hw);
+
+        synchronize_irq(rtlpci->pdev->irq);
+        tasklet_kill(&rtlpriv->works.irq_tasklet);
+
+        flush_workqueue(rtlpriv->works.rtl_wq);
+        destroy_workqueue(rtlpriv->works.rtl_wq);
+
+}
+
+int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        int err;
+
+        _rtl_pci_init_struct(hw, pdev);
+
+        err = _rtl_pci_init_trx_ring(hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("tx ring initialization failed"));
+                return err;
+        }
+
+        return 1;
+}
+
+int rtl_pci_start(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        int err;
+
+        rtl_pci_reset_trx_ring(hw);
+
+        rtlpci->driver_is_goingto_unload = false;
+        err = rtlpriv->cfg->ops->hw_init(hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                         ("Failed to config hardware!\n"));
+                return err;
+        }
+
+        rtlpriv->cfg->ops->enable_interrupt(hw);
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("enable_interrupt OK\n"));
+
+        rtl_init_rx_config(hw);
+
+        /*should after adapter start and interrupt enable. */
+        set_hal_start(rtlhal);
+
+        RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
+
+        rtlpci->up_first_time = false;
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
+        return 0;
+}
+
+void rtl_pci_stop(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        unsigned long flags;
+        u8 RFInProgressTimeOut = 0;
+
+        /*
+         *should before disable interrrupt&adapter
+         *and will do it immediately.
+         */
+        set_hal_stop(rtlhal);
+
+        rtlpriv->cfg->ops->disable_interrupt(hw);
+
+        spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
+        while (ppsc->rfchange_inprogress) {
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
+                if (RFInProgressTimeOut > 100) {
+                        spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
+                        break;
+                }
+                mdelay(1);
+                RFInProgressTimeOut++;
+                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
+        }
+        ppsc->rfchange_inprogress = true;
+        spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
+
+        rtlpci->driver_is_goingto_unload = true;
+        rtlpriv->cfg->ops->hw_disable(hw);
+        rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
+
+        spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
+        ppsc->rfchange_inprogress = false;
+        spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
+
+        rtl_pci_enable_aspm(hw);
+}
+
+static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
+                struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct pci_dev *bridge_pdev = pdev->bus->self;
+        u16 venderid;
+        u16 deviceid;
+        u8 revisionid;
+        u16 irqline;
+        u8 tmp;
+
+        venderid = pdev->vendor;
+        deviceid = pdev->device;
+        pci_read_config_byte(pdev, 0x8, &revisionid);
+        pci_read_config_word(pdev, 0x3C, &irqline);
+
+        if (deviceid == RTL_PCI_8192_DID ||
+            deviceid == RTL_PCI_0044_DID ||
+            deviceid == RTL_PCI_0047_DID ||
+            deviceid == RTL_PCI_8192SE_DID ||
+            deviceid == RTL_PCI_8174_DID ||
+            deviceid == RTL_PCI_8173_DID ||
+            deviceid == RTL_PCI_8172_DID ||
+            deviceid == RTL_PCI_8171_DID) {
+                switch (revisionid) {
+                case RTL_PCI_REVISION_ID_8192PCIE:
+                        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                                 ("8192 PCI-E is found - "
+                                  "vid/did=%x/%x\n", venderid, deviceid));
+                        rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
+                        break;
+                case RTL_PCI_REVISION_ID_8192SE:
+                        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                                 ("8192SE is found - "
+                                  "vid/did=%x/%x\n", venderid, deviceid));
+                        rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                 ("Err: Unknown device - "
+                                  "vid/did=%x/%x\n", venderid, deviceid));
+                        rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
+                        break;
+
+                }
+        } else if (deviceid == RTL_PCI_8192CET_DID ||
+                   deviceid == RTL_PCI_8192CE_DID ||
+                   deviceid == RTL_PCI_8191CE_DID ||
+                   deviceid == RTL_PCI_8188CE_DID) {
+                rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                         ("8192C PCI-E is found - "
+                          "vid/did=%x/%x\n", venderid, deviceid));
+        } else {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Err: Unknown device -"
+                          " vid/did=%x/%x\n", venderid, deviceid));
+
+                rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
+        }
+
+        /*find bus info */
+        pcipriv->ndis_adapter.busnumber = pdev->bus->number;
+        pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
+        pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
+
+        /*find bridge info */
+        pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
+        for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
+                if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
+                        pcipriv->ndis_adapter.pcibridge_vendor = tmp;
+                        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                                 ("Pci Bridge Vendor is found index: %d\n",
+                                  tmp));
+                        break;
+                }
+        }
+
+        if (pcipriv->ndis_adapter.pcibridge_vendor !=
+                PCI_BRIDGE_VENDOR_UNKNOWN) {
+                pcipriv->ndis_adapter.pcibridge_busnum =
+                    bridge_pdev->bus->number;
+                pcipriv->ndis_adapter.pcibridge_devnum =
+                    PCI_SLOT(bridge_pdev->devfn);
+                pcipriv->ndis_adapter.pcibridge_funcnum =
+                    PCI_FUNC(bridge_pdev->devfn);
+                pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
+                    pci_pcie_cap(bridge_pdev);
+                pcipriv->ndis_adapter.pcicfg_addrport =
+                    (pcipriv->ndis_adapter.pcibridge_busnum << 16) |
+                    (pcipriv->ndis_adapter.pcibridge_devnum << 11) |
+                    (pcipriv->ndis_adapter.pcibridge_funcnum << 8) | (1 << 31);
+                pcipriv->ndis_adapter.num4bytes =
+                    (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
+
+                rtl_pci_get_linkcontrol_field(hw);
+
+                if (pcipriv->ndis_adapter.pcibridge_vendor ==
+                    PCI_BRIDGE_VENDOR_AMD) {
+                        pcipriv->ndis_adapter.amd_l1_patch =
+                            rtl_pci_get_amd_l1_patch(hw);
+                }
+        }
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                 ("pcidev busnumber:devnumber:funcnumber:"
+                  "vendor:link_ctl %d:%d:%d:%x:%x\n",
+                  pcipriv->ndis_adapter.busnumber,
+                  pcipriv->ndis_adapter.devnumber,
+                  pcipriv->ndis_adapter.funcnumber,
+                  pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg));
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                 ("pci_bridge busnumber:devnumber:funcnumber:vendor:"
+                  "pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
+                  pcipriv->ndis_adapter.pcibridge_busnum,
+                  pcipriv->ndis_adapter.pcibridge_devnum,
+                  pcipriv->ndis_adapter.pcibridge_funcnum,
+                  pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
+                  pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
+                  pcipriv->ndis_adapter.pcibridge_linkctrlreg,
+                  pcipriv->ndis_adapter.amd_l1_patch));
+
+        rtl_pci_parse_configuration(pdev, hw);
+
+        return true;
+}
+
+int __devinit rtl_pci_probe(struct pci_dev *pdev,
+                            const struct pci_device_id *id)
+{
+        struct ieee80211_hw *hw = NULL;
+
+        struct rtl_priv *rtlpriv = NULL;
+        struct rtl_pci_priv *pcipriv = NULL;
+        struct rtl_pci *rtlpci;
+        unsigned long pmem_start, pmem_len, pmem_flags;
+        int err;
+
+        err = pci_enable_device(pdev);
+        if (err) {
+                RT_ASSERT(false,
+                          ("%s : Cannot enable new PCI device\n",
+                           pci_name(pdev)));
+                return err;
+        }
+
+        if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
+                if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
+                        RT_ASSERT(false, ("Unable to obtain 32bit DMA "
+                                          "for consistent allocations\n"));
+                        pci_disable_device(pdev);
+                        return -ENOMEM;
+                }
+        }
+
+        pci_set_master(pdev);
+
+        hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
+                                sizeof(struct rtl_priv), &rtl_ops);
+        if (!hw) {
+                RT_ASSERT(false,
+                          ("%s : ieee80211 alloc failed\n", pci_name(pdev)));
+                err = -ENOMEM;
+                goto fail1;
+        }
+
+        SET_IEEE80211_DEV(hw, &pdev->dev);
+        pci_set_drvdata(pdev, hw);
+
+        rtlpriv = hw->priv;
+        pcipriv = (void *)rtlpriv->priv;
+        pcipriv->dev.pdev = pdev;
+
+        /*
+         *init dbgp flags before all
+         *other functions, because we will
+         *use it in other funtions like
+         *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
+         *you can not use these macro
+         *before this
+         */
+        rtl_dbgp_flag_init(hw);
+
+        /* MEM map */
+        err = pci_request_regions(pdev, KBUILD_MODNAME);
+        if (err) {
+                RT_ASSERT(false, ("Can't obtain PCI resources\n"));
+                return err;
+        }
+
+        pmem_start = pci_resource_start(pdev, 2);
+        pmem_len = pci_resource_len(pdev, 2);
+        pmem_flags = pci_resource_flags(pdev, 2);
+
+        /*shared mem start */
+        rtlpriv->io.pci_mem_start =
+                        (unsigned long)pci_iomap(pdev, 2, pmem_len);
+        if (rtlpriv->io.pci_mem_start == 0) {
+                RT_ASSERT(false, ("Can't map PCI mem\n"));
+                goto fail2;
+        }
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                 ("mem mapped space: start: 0x%08lx len:%08lx "
+                  "flags:%08lx, after map:0x%08lx\n",
+                  pmem_start, pmem_len, pmem_flags,
+                  rtlpriv->io.pci_mem_start));
+
+        /* Disable Clk Request */
+        pci_write_config_byte(pdev, 0x81, 0);
+        /* leave D3 mode */
+        pci_write_config_byte(pdev, 0x44, 0);
+        pci_write_config_byte(pdev, 0x04, 0x06);
+        pci_write_config_byte(pdev, 0x04, 0x07);
+
+        /* init cfg & intf_ops */
+        rtlpriv->rtlhal.interface = INTF_PCI;
+        rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
+        rtlpriv->intf_ops = &rtl_pci_ops;
+
+        /* find adapter */
+        _rtl_pci_find_adapter(pdev, hw);
+
+        /* Init IO handler */
+        _rtl_pci_io_handler_init(&pdev->dev, hw);
+
+        /*like read eeprom and so on */
+        rtlpriv->cfg->ops->read_eeprom_info(hw);
+
+        if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Can't init_sw_vars.\n"));
+                goto fail3;
+        }
+
+        rtlpriv->cfg->ops->init_sw_leds(hw);
+
+        /*aspm */
+        rtl_pci_init_aspm(hw);
+
+        /* Init mac80211 sw */
+        err = rtl_init_core(hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Can't allocate sw for mac80211.\n"));
+                goto fail3;
+        }
+
+        /* Init PCI sw */
+        err = !rtl_pci_init(hw, pdev);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Failed to init PCI.\n"));
+                goto fail3;
+        }
+
+        err = ieee80211_register_hw(hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Can't register mac80211 hw.\n"));
+                goto fail3;
+        } else {
+                rtlpriv->mac80211.mac80211_registered = 1;
+        }
+
+        err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("failed to create sysfs device attributes\n"));
+                goto fail3;
+        }
+
+        /*init rfkill */
+        rtl_init_rfkill(hw);
+
+        rtlpci = rtl_pcidev(pcipriv);
+        err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
+                          IRQF_SHARED, KBUILD_MODNAME, hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                         ("%s: failed to register IRQ handler\n",
+                          wiphy_name(hw->wiphy)));
+                goto fail3;
+        } else {
+                rtlpci->irq_alloc = 1;
+        }
+
+        set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
+        return 0;
+
+fail3:
+        pci_set_drvdata(pdev, NULL);
+        rtl_deinit_core(hw);
+        _rtl_pci_io_handler_release(hw);
+        ieee80211_free_hw(hw);
+
+        if (rtlpriv->io.pci_mem_start != 0)
+                pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
+
+fail2:
+        pci_release_regions(pdev);
+
+fail1:
+
+        pci_disable_device(pdev);
+
+        return -ENODEV;
+
+}
+EXPORT_SYMBOL(rtl_pci_probe);
+
+void rtl_pci_disconnect(struct pci_dev *pdev)
+{
+        struct ieee80211_hw *hw = pci_get_drvdata(pdev);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
+        struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
+
+        clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
+
+        sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
+
+        /*ieee80211_unregister_hw will call ops_stop */
+        if (rtlmac->mac80211_registered == 1) {
+                ieee80211_unregister_hw(hw);
+                rtlmac->mac80211_registered = 0;
+        } else {
+                rtl_deinit_deferred_work(hw);
+                rtlpriv->intf_ops->adapter_stop(hw);
+        }
+
+        /*deinit rfkill */
+        rtl_deinit_rfkill(hw);
+
+        rtl_pci_deinit(hw);
+        rtl_deinit_core(hw);
+        rtlpriv->cfg->ops->deinit_sw_leds(hw);
+        _rtl_pci_io_handler_release(hw);
+        rtlpriv->cfg->ops->deinit_sw_vars(hw);
+
+        if (rtlpci->irq_alloc) {
+                free_irq(rtlpci->pdev->irq, hw);
+                rtlpci->irq_alloc = 0;
+        }
+
+        if (rtlpriv->io.pci_mem_start != 0) {
+                pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start);
+                pci_release_regions(pdev);
+        }
+
+        pci_disable_device(pdev);
+        pci_set_drvdata(pdev, NULL);
+
+        ieee80211_free_hw(hw);
+}
+EXPORT_SYMBOL(rtl_pci_disconnect);
+
+/***************************************
+kernel pci power state define:
+PCI_D0         ((pci_power_t __force) 0)
+PCI_D1         ((pci_power_t __force) 1)
+PCI_D2         ((pci_power_t __force) 2)
+PCI_D3hot      ((pci_power_t __force) 3)
+PCI_D3cold     ((pci_power_t __force) 4)
+PCI_UNKNOWN    ((pci_power_t __force) 5)
+
+This function is called when system
+goes into suspend state mac80211 will
+call rtl_mac_stop() from the mac80211
+suspend function first, So there is
+no need to call hw_disable here.
+****************************************/
+int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+        pci_save_state(pdev);
+        pci_disable_device(pdev);
+        pci_set_power_state(pdev, PCI_D3hot);
+
+        return 0;
+}
+EXPORT_SYMBOL(rtl_pci_suspend);
+
+int rtl_pci_resume(struct pci_dev *pdev)
+{
+        int ret;
+
+        pci_set_power_state(pdev, PCI_D0);
+        ret = pci_enable_device(pdev);
+        if (ret) {
+                RT_ASSERT(false, ("ERR: <======\n"));
+                return ret;
+        }
+
+        pci_restore_state(pdev);
+
+        return 0;
+}
+EXPORT_SYMBOL(rtl_pci_resume);
+
+struct rtl_intf_ops rtl_pci_ops = {
+        .adapter_start = rtl_pci_start,
+        .adapter_stop = rtl_pci_stop,
+        .adapter_tx = rtl_pci_tx,
+        .reset_trx_ring = rtl_pci_reset_trx_ring,
+
+        .disable_aspm = rtl_pci_disable_aspm,
+        .enable_aspm = rtl_pci_enable_aspm,
+};
diff --git a/drivers/net/wireless/rtlwifi/pci.h b/drivers/net/wireless/rtlwifi/pci.h
new file mode 100644
index 000000000000..d36a66939958
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/pci.h
@@ -0,0 +1,302 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL_PCI_H__
+#define __RTL_PCI_H__
+
+#include <linux/pci.h>
+/*
+1: MSDU packet queue,
+2: Rx Command Queue
+*/
+#define RTL_PCI_RX_MPDU_QUEUE                   0
+#define RTL_PCI_RX_CMD_QUEUE                    1
+#define RTL_PCI_MAX_RX_QUEUE                    2
+
+#define RTL_PCI_MAX_RX_COUNT                    64
+#define RTL_PCI_MAX_TX_QUEUE_COUNT              9
+
+#define RT_TXDESC_NUM                           128
+#define RT_TXDESC_NUM_BE_QUEUE                  256
+
+#define BK_QUEUE                                0
+#define BE_QUEUE                                1
+#define VI_QUEUE                                2
+#define VO_QUEUE                                3
+#define BEACON_QUEUE                            4
+#define TXCMD_QUEUE                             5
+#define MGNT_QUEUE                              6
+#define HIGH_QUEUE                              7
+#define HCCA_QUEUE                              8
+
+#define RTL_PCI_DEVICE(vend, dev, cfg)  \
+        .vendor = (vend), \
+        .device = (dev), \
+        .subvendor = PCI_ANY_ID, \
+        .subdevice = PCI_ANY_ID,\
+        .driver_data = (kernel_ulong_t)&(cfg)
+
+#define INTEL_VENDOR_ID                         0x8086
+#define SIS_VENDOR_ID                           0x1039
+#define ATI_VENDOR_ID                           0x1002
+#define ATI_DEVICE_ID                           0x7914
+#define AMD_VENDOR_ID                           0x1022
+
+#define PCI_MAX_BRIDGE_NUMBER                   255
+#define PCI_MAX_DEVICES                         32
+#define PCI_MAX_FUNCTION                        8
+
+#define PCI_CONF_ADDRESS        0x0CF8  /*PCI Configuration Space Address */
+#define PCI_CONF_DATA           0x0CFC  /*PCI Configuration Space Data */
+
+#define PCI_CLASS_BRIDGE_DEV            0x06
+#define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
+#define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
+#define PCI_CAP_ID_EXP                  0x10
+
+#define U1DONTCARE                      0xFF
+#define U2DONTCARE                      0xFFFF
+#define U4DONTCARE                      0xFFFFFFFF
+
+#define RTL_PCI_8192_DID        0x8192  /*8192 PCI-E */
+#define RTL_PCI_8192SE_DID      0x8192  /*8192 SE */
+#define RTL_PCI_8174_DID        0x8174  /*8192 SE */
+#define RTL_PCI_8173_DID        0x8173  /*8191 SE Crab */
+#define RTL_PCI_8172_DID        0x8172  /*8191 SE RE */
+#define RTL_PCI_8171_DID        0x8171  /*8191 SE Unicron */
+#define RTL_PCI_0045_DID        0x0045  /*8190 PCI for Ceraga */
+#define RTL_PCI_0046_DID        0x0046  /*8190 Cardbus for Ceraga */
+#define RTL_PCI_0044_DID        0x0044  /*8192e PCIE for Ceraga */
+#define RTL_PCI_0047_DID        0x0047  /*8192e Express Card for Ceraga */
+#define RTL_PCI_700F_DID        0x700F
+#define RTL_PCI_701F_DID        0x701F
+#define RTL_PCI_DLINK_DID       0x3304
+#define RTL_PCI_8192CET_DID     0x8191  /*8192ce */
+#define RTL_PCI_8192CE_DID      0x8178  /*8192ce */
+#define RTL_PCI_8191CE_DID      0x8177  /*8192ce */
+#define RTL_PCI_8188CE_DID      0x8176  /*8192ce */
+#define RTL_PCI_8192CU_DID      0x8191  /*8192ce */
+#define RTL_PCI_8192DE_DID      0x092D  /*8192ce */
+#define RTL_PCI_8192DU_DID      0x092D  /*8192ce */
+
+/*8192 support 16 pages of IO registers*/
+#define RTL_MEM_MAPPED_IO_RANGE_8190PCI         0x1000
+#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE        0x4000
+#define RTL_MEM_MAPPED_IO_RANGE_8192SE          0x4000
+#define RTL_MEM_MAPPED_IO_RANGE_8192CE          0x4000
+#define RTL_MEM_MAPPED_IO_RANGE_8192DE          0x4000
+
+#define RTL_PCI_REVISION_ID_8190PCI             0x00
+#define RTL_PCI_REVISION_ID_8192PCIE            0x01
+#define RTL_PCI_REVISION_ID_8192SE              0x10
+#define RTL_PCI_REVISION_ID_8192CE              0x1
+#define RTL_PCI_REVISION_ID_8192DE              0x0
+
+#define RTL_DEFAULT_HARDWARE_TYPE       HARDWARE_TYPE_RTL8192CE
+
+enum pci_bridge_vendor {
+        PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
+        PCI_BRIDGE_VENDOR_ATI,          /*0b'0000,0010*/
+        PCI_BRIDGE_VENDOR_AMD,          /*0b'0000,0100*/
+        PCI_BRIDGE_VENDOR_SIS,          /*0b'0000,1000*/
+        PCI_BRIDGE_VENDOR_UNKNOWN,      /*0b'0100,0000*/
+        PCI_BRIDGE_VENDOR_MAX,
+};
+
+struct rtl_rx_desc {
+        u32 dword[8];
+} __packed;
+
+struct rtl_tx_desc {
+        u32 dword[16];
+} __packed;
+
+struct rtl_tx_cmd_desc {
+        u32 dword[16];
+} __packed;
+
+struct rtl8192_tx_ring {
+        struct rtl_tx_desc *desc;
+        dma_addr_t dma;
+        unsigned int idx;
+        unsigned int entries;
+        struct sk_buff_head queue;
+};
+
+struct rtl8192_rx_ring {
+        struct rtl_rx_desc *desc;
+        dma_addr_t dma;
+        unsigned int idx;
+        struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
+};
+
+struct rtl_pci {
+        struct pci_dev *pdev;
+
+        bool driver_is_goingto_unload;
+        bool up_first_time;
+        bool being_init_adapter;
+        bool irq_enabled;
+
+        /*Tx */
+        struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
+        int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
+        u32 transmit_config;
+
+        /*Rx */
+        struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
+        int rxringcount;
+        u16 rxbuffersize;
+        u32 receive_config;
+
+        /*irq */
+        u8 irq_alloc;
+        u32 irq_mask[2];
+
+        /*Bcn control register setting */
+        u32 reg_bcn_ctrl_val;
+
+         /*ASPM*/ u8 const_pci_aspm;
+        u8 const_amdpci_aspm;
+        u8 const_hwsw_rfoff_d3;
+        u8 const_support_pciaspm;
+        /*pci-e bridge */
+        u8 const_hostpci_aspm_setting;
+        /*pci-e device */
+        u8 const_devicepci_aspm_setting;
+        /*If it supports ASPM, Offset[560h] = 0x40,
+           otherwise Offset[560h] = 0x00. */
+        bool b_support_aspm;
+        bool b_support_backdoor;
+
+        /*QOS & EDCA */
+        enum acm_method acm_method;
+};
+
+struct mp_adapter {
+        u8 linkctrl_reg;
+
+        u8 busnumber;
+        u8 devnumber;
+        u8 funcnumber;
+
+        u8 pcibridge_busnum;
+        u8 pcibridge_devnum;
+        u8 pcibridge_funcnum;
+
+        u8 pcibridge_vendor;
+        u16 pcibridge_vendorid;
+        u16 pcibridge_deviceid;
+
+        u32 pcicfg_addrport;
+        u8 num4bytes;
+
+        u8 pcibridge_pciehdr_offset;
+        u8 pcibridge_linkctrlreg;
+
+        bool amd_l1_patch;
+};
+
+struct rtl_pci_priv {
+        struct rtl_pci dev;
+        struct mp_adapter ndis_adapter;
+        struct rtl_led_ctl ledctl;
+};
+
+#define rtl_pcipriv(hw)         (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
+#define rtl_pcidev(pcipriv)     (&((pcipriv)->dev))
+
+int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
+
+extern struct rtl_intf_ops rtl_pci_ops;
+
+int __devinit rtl_pci_probe(struct pci_dev *pdev,
+                            const struct pci_device_id *id);
+void rtl_pci_disconnect(struct pci_dev *pdev);
+int rtl_pci_suspend(struct pci_dev *pdev, pm_message_t state);
+int rtl_pci_resume(struct pci_dev *pdev);
+
+static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
+{
+        return 0xff & readb((u8 *) rtlpriv->io.pci_mem_start + addr);
+}
+
+static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
+{
+        return readw((u8 *) rtlpriv->io.pci_mem_start + addr);
+}
+
+static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
+{
+        return readl((u8 *) rtlpriv->io.pci_mem_start + addr);
+}
+
+static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
+{
+        writeb(val, (u8 *) rtlpriv->io.pci_mem_start + addr);
+}
+
+static inline void pci_write16_async(struct rtl_priv *rtlpriv,
+                                     u32 addr, u16 val)
+{
+        writew(val, (u8 *) rtlpriv->io.pci_mem_start + addr);
+}
+
+static inline void pci_write32_async(struct rtl_priv *rtlpriv,
+                                     u32 addr, u32 val)
+{
+        writel(val, (u8 *) rtlpriv->io.pci_mem_start + addr);
+}
+
+static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
+{
+        outl(val, port);
+}
+
+static inline void rtl_pci_raw_write_port_uchar(u32 port, u8 val)
+{
+        outb(val, port);
+}
+
+static inline void rtl_pci_raw_read_port_uchar(u32 port, u8 *pval)
+{
+        *pval = inb(port);
+}
+
+static inline void rtl_pci_raw_read_port_ushort(u32 port, u16 *pval)
+{
+        *pval = inw(port);
+}
+
+static inline void rtl_pci_raw_read_port_ulong(u32 port, u32 *pval)
+{
+        *pval = inl(port);
+}
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/ps.c b/drivers/net/wireless/rtlwifi/ps.c
new file mode 100644
index 000000000000..d2326c13449e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/ps.c
@@ -0,0 +1,493 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "wifi.h"
+#include "base.h"
+#include "ps.h"
+
+bool rtl_ps_enable_nic(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        bool init_status = true;
+
+        /*<1> reset trx ring */
+        if (rtlhal->interface == INTF_PCI)
+                rtlpriv->intf_ops->reset_trx_ring(hw);
+
+        if (is_hal_stop(rtlhal))
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Driver is already down!\n"));
+
+        /*<2> Enable Adapter */
+        rtlpriv->cfg->ops->hw_init(hw);
+        RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
+        /*init_status = false; */
+
+        /*<3> Enable Interrupt */
+        rtlpriv->cfg->ops->enable_interrupt(hw);
+
+        /*<enable timer> */
+        rtl_watch_dog_timer_callback((unsigned long)hw);
+
+        return init_status;
+}
+EXPORT_SYMBOL(rtl_ps_enable_nic);
+
+bool rtl_ps_disable_nic(struct ieee80211_hw *hw)
+{
+        bool status = true;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        /*<1> Stop all timer */
+        rtl_deinit_deferred_work(hw);
+
+        /*<2> Disable Interrupt */
+        rtlpriv->cfg->ops->disable_interrupt(hw);
+
+        /*<3> Disable Adapter */
+        rtlpriv->cfg->ops->hw_disable(hw);
+
+        return status;
+}
+EXPORT_SYMBOL(rtl_ps_disable_nic);
+
+bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
+                         enum rf_pwrstate state_toset,
+                         u32 changesource, bool protect_or_not)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        enum rf_pwrstate rtstate;
+        bool b_actionallowed = false;
+        u16 rfwait_cnt = 0;
+        unsigned long flag;
+
+        /*protect_or_not = true; */
+
+        if (protect_or_not)
+                goto no_protect;
+
+        /*
+         *Only one thread can change
+         *the RF state at one time, and others
+         *should wait to be executed.
+         */
+        while (true) {
+                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
+                if (ppsc->rfchange_inprogress) {
+                        spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock,
+                                               flag);
+
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                 ("RF Change in progress!"
+                                  "Wait to set..state_toset(%d).\n",
+                                  state_toset));
+
+                        /* Set RF after the previous action is done.  */
+                        while (ppsc->rfchange_inprogress) {
+                                rfwait_cnt++;
+                                mdelay(1);
+
+                                /*
+                                 *Wait too long, return false to avoid
+                                 *to be stuck here.
+                                 */
+                                if (rfwait_cnt > 100)
+                                        return false;
+                        }
+                } else {
+                        ppsc->rfchange_inprogress = true;
+                        spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock,
+                                               flag);
+                        break;
+                }
+        }
+
+no_protect:
+        rtstate = ppsc->rfpwr_state;
+
+        switch (state_toset) {
+        case ERFON:
+                ppsc->rfoff_reason &= (~changesource);
+
+                if ((changesource == RF_CHANGE_BY_HW) &&
+                    (ppsc->b_hwradiooff == true)) {
+                        ppsc->b_hwradiooff = false;
+                }
+
+                if (!ppsc->rfoff_reason) {
+                        ppsc->rfoff_reason = 0;
+                        b_actionallowed = true;
+                }
+
+                break;
+
+        case ERFOFF:
+
+                if ((changesource == RF_CHANGE_BY_HW)
+                    && (ppsc->b_hwradiooff == false)) {
+                        ppsc->b_hwradiooff = true;
+                }
+
+                ppsc->rfoff_reason |= changesource;
+                b_actionallowed = true;
+                break;
+
+        case ERFSLEEP:
+                ppsc->rfoff_reason |= changesource;
+                b_actionallowed = true;
+                break;
+
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+
+        if (b_actionallowed)
+                rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset);
+
+        if (!protect_or_not) {
+                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
+                ppsc->rfchange_inprogress = false;
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
+        }
+
+        return b_actionallowed;
+}
+EXPORT_SYMBOL(rtl_ps_set_rf_state);
+
+static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        ppsc->b_swrf_processing = true;
+
+        if (ppsc->inactive_pwrstate == ERFON && rtlhal->interface == INTF_PCI) {
+                if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
+                    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM) &&
+                    rtlhal->interface == INTF_PCI) {
+                        rtlpriv->intf_ops->disable_aspm(hw);
+                        RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
+                }
+        }
+
+        rtl_ps_set_rf_state(hw, ppsc->inactive_pwrstate,
+                            RF_CHANGE_BY_IPS, false);
+
+        if (ppsc->inactive_pwrstate == ERFOFF &&
+            rtlhal->interface == INTF_PCI) {
+                if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
+                        rtlpriv->intf_ops->enable_aspm(hw);
+                        RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
+                }
+        }
+
+        ppsc->b_swrf_processing = false;
+}
+
+void rtl_ips_nic_off_wq_callback(void *data)
+{
+        struct rtl_works *rtlworks =
+            container_of_dwork_rtl(data, struct rtl_works, ips_nic_off_wq);
+        struct ieee80211_hw *hw = rtlworks->hw;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        enum rf_pwrstate rtstate;
+
+        if (mac->opmode != NL80211_IFTYPE_STATION) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("not station return\n"));
+                return;
+        }
+
+        if (is_hal_stop(rtlhal))
+                return;
+
+        if (rtlpriv->sec.being_setkey)
+                return;
+
+        if (ppsc->b_inactiveps) {
+                rtstate = ppsc->rfpwr_state;
+
+                /*
+                 *Do not enter IPS in the following conditions:
+                 *(1) RF is already OFF or Sleep
+                 *(2) b_swrf_processing (indicates the IPS is still under going)
+                 *(3) Connectted (only disconnected can trigger IPS)
+                 *(4) IBSS (send Beacon)
+                 *(5) AP mode (send Beacon)
+                 *(6) monitor mode (rcv packet)
+                 */
+
+                if (rtstate == ERFON &&
+                    !ppsc->b_swrf_processing &&
+                    (mac->link_state == MAC80211_NOLINK) &&
+                    !mac->act_scanning) {
+                        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
+                                 ("IPSEnter(): Turn off RF.\n"));
+
+                        ppsc->inactive_pwrstate = ERFOFF;
+                        ppsc->b_in_powersavemode = true;
+
+                        /*rtl_pci_reset_trx_ring(hw); */
+                        _rtl_ps_inactive_ps(hw);
+                }
+        }
+}
+
+void rtl_ips_nic_off(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        /*
+         *because when link with ap, mac80211 will ask us
+         *to disable nic quickly after scan before linking,
+         *this will cause link failed, so we delay 100ms here
+         */
+        queue_delayed_work(rtlpriv->works.rtl_wq,
+                           &rtlpriv->works.ips_nic_off_wq, MSECS(100));
+}
+
+void rtl_ips_nic_on(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        enum rf_pwrstate rtstate;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtlpriv->locks.ips_lock, flags);
+
+        if (ppsc->b_inactiveps) {
+                rtstate = ppsc->rfpwr_state;
+
+                if (rtstate != ERFON &&
+                    !ppsc->b_swrf_processing &&
+                    ppsc->rfoff_reason <= RF_CHANGE_BY_IPS) {
+
+                        ppsc->inactive_pwrstate = ERFON;
+                        ppsc->b_in_powersavemode = false;
+
+                        _rtl_ps_inactive_ps(hw);
+                }
+        }
+
+        spin_unlock_irqrestore(&rtlpriv->locks.ips_lock, flags);
+}
+
+/*for FW LPS*/
+
+/*
+ *Determine if we can set Fw into PS mode
+ *in current condition.Return TRUE if it
+ *can enter PS mode.
+ */
+static bool rtl_get_fwlps_doze(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        u32 ps_timediff;
+
+        ps_timediff = jiffies_to_msecs(jiffies -
+                                       ppsc->last_delaylps_stamp_jiffies);
+
+        if (ps_timediff < 2000) {
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("Delay enter Fw LPS for DHCP, ARP,"
+                          " or EAPOL exchanging state.\n"));
+                return false;
+        }
+
+        if (mac->link_state != MAC80211_LINKED)
+                return false;
+
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                return false;
+
+        return true;
+}
+
+/* Change current and default preamble mode.*/
+static void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        u8 rpwm_val, fw_pwrmode;
+
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                return;
+
+        if (mac->link_state != MAC80211_LINKED)
+                return;
+
+        if (ppsc->dot11_psmode == rt_psmode)
+                return;
+
+        /* Update power save mode configured. */
+        ppsc->dot11_psmode = rt_psmode;
+
+        /*
+         *<FW control LPS>
+         *1. Enter PS mode
+         *   Set RPWM to Fw to turn RF off and send H2C fw_pwrmode
+         *   cmd to set Fw into PS mode.
+         *2. Leave PS mode
+         *   Send H2C fw_pwrmode cmd to Fw to set Fw into Active
+         *   mode and set RPWM to turn RF on.
+         */
+
+        if ((ppsc->b_fwctrl_lps) && (ppsc->b_leisure_ps) &&
+             ppsc->report_linked) {
+                bool b_fw_current_inps;
+                if (ppsc->dot11_psmode == EACTIVE) {
+                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                 ("FW LPS leave ps_mode:%x\n",
+                                  FW_PS_ACTIVE_MODE));
+
+                        rpwm_val = 0x0C;        /* RF on */
+                        fw_pwrmode = FW_PS_ACTIVE_MODE;
+                        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
+                                        (u8 *) (&rpwm_val));
+                        rtlpriv->cfg->ops->set_hw_reg(hw,
+                                        HW_VAR_H2C_FW_PWRMODE,
+                                        (u8 *) (&fw_pwrmode));
+                        b_fw_current_inps = false;
+
+                        rtlpriv->cfg->ops->set_hw_reg(hw,
+                                        HW_VAR_FW_PSMODE_STATUS,
+                                        (u8 *) (&b_fw_current_inps));
+
+                } else {
+                        if (rtl_get_fwlps_doze(hw)) {
+                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                                ("FW LPS enter ps_mode:%x\n",
+                                                 ppsc->fwctrl_psmode));
+
+                                rpwm_val = 0x02;        /* RF off */
+                                b_fw_current_inps = true;
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                HW_VAR_FW_PSMODE_STATUS,
+                                                (u8 *) (&b_fw_current_inps));
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                HW_VAR_H2C_FW_PWRMODE,
+                                                (u8 *) (&ppsc->fwctrl_psmode));
+
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                HW_VAR_SET_RPWM,
+                                                (u8 *) (&rpwm_val));
+                        } else {
+                                /* Reset the power save related parameters. */
+                                ppsc->dot11_psmode = EACTIVE;
+                        }
+                }
+        }
+}
+
+/*Enter the leisure power save mode.*/
+void rtl_lps_enter(struct ieee80211_hw *hw)
+{
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        unsigned long flag;
+
+        if (!(ppsc->b_fwctrl_lps && ppsc->b_leisure_ps))
+                return;
+
+        if (rtlpriv->sec.being_setkey)
+                return;
+
+        if (rtlpriv->link_info.b_busytraffic)
+                return;
+
+        /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
+        if (mac->cnt_after_linked < 5)
+                return;
+
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                return;
+
+        if (mac->link_state != MAC80211_LINKED)
+                return;
+
+        spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
+
+        if (ppsc->b_leisure_ps) {
+                /* Idle for a while if we connect to AP a while ago. */
+                if (mac->cnt_after_linked >= 2) {
+                        if (ppsc->dot11_psmode == EACTIVE) {
+                                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                                        ("Enter 802.11 power save mode...\n"));
+
+                                rtl_lps_set_psmode(hw, EAUTOPS);
+                        }
+                }
+        }
+        spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
+}
+
+/*Leave the leisure power save mode.*/
+void rtl_lps_leave(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        unsigned long flag;
+
+        spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
+
+        if (ppsc->b_fwctrl_lps && ppsc->b_leisure_ps) {
+                if (ppsc->dot11_psmode != EACTIVE) {
+
+                        /*FIX ME */
+                        rtlpriv->cfg->ops->enable_interrupt(hw);
+
+                        if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM &&
+                            RT_IN_PS_LEVEL(ppsc, RT_RF_LPS_LEVEL_ASPM) &&
+                            rtlhal->interface == INTF_PCI) {
+                                rtlpriv->intf_ops->disable_aspm(hw);
+                                RT_CLEAR_PS_LEVEL(ppsc, RT_RF_LPS_LEVEL_ASPM);
+                        }
+
+                        RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                                 ("Busy Traffic,Leave 802.11 power save..\n"));
+
+                        rtl_lps_set_psmode(hw, EACTIVE);
+                }
+        }
+        spin_unlock_irqrestore(&rtlpriv->locks.lps_lock, flag);
+}
diff --git a/drivers/net/wireless/rtlwifi/ps.h b/drivers/net/wireless/rtlwifi/ps.h
new file mode 100644
index 000000000000..ae56da801a23
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/ps.h
@@ -0,0 +1,43 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __REALTEK_RTL_PCI_PS_H__
+#define __REALTEK_RTL_PCI_PS_H__
+
+bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
+                         enum rf_pwrstate state_toset, u32 changesource,
+                         bool protect_or_not);
+bool rtl_ps_enable_nic(struct ieee80211_hw *hw);
+bool rtl_ps_disable_nic(struct ieee80211_hw *hw);
+void rtl_ips_nic_off(struct ieee80211_hw *hw);
+void rtl_ips_nic_on(struct ieee80211_hw *hw);
+void rtl_ips_nic_off_wq_callback(void *data);
+void rtl_lps_enter(struct ieee80211_hw *hw);
+void rtl_lps_leave(struct ieee80211_hw *hw);
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rc.c b/drivers/net/wireless/rtlwifi/rc.c
new file mode 100644
index 000000000000..91634107434a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rc.c
@@ -0,0 +1,329 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "wifi.h"
+#include "base.h"
+#include "rc.h"
+
+/*
+ *Finds the highest rate index we can use
+ *if skb is special data like DHCP/EAPOL, we set should
+ *it to lowest rate CCK_1M, otherwise we set rate to
+ *CCK11M or OFDM_54M based on wireless mode.
+ */
+static u8 _rtl_rc_get_highest_rix(struct rtl_priv *rtlpriv,
+                                  struct sk_buff *skb, bool not_data)
+{
+        struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
+
+        /*
+         *mgt use 1M, although we have check it
+         *before this function use rate_control_send_low,
+         *we still check it here
+         */
+        if (not_data)
+                return rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M];
+
+        /*
+         *this rate is no use for true rate, firmware
+         *will control rate at all it just used for
+         *1.show in iwconfig in B/G mode
+         *2.in rtl_get_tcb_desc when we check rate is
+         *      1M we will not use FW rate but user rate.
+         */
+        if (rtl_is_special_data(rtlpriv->mac80211.hw, skb, true)) {
+                return rtlpriv->cfg->maps[RTL_RC_CCK_RATE1M];
+        } else {
+                if (rtlmac->mode == WIRELESS_MODE_B)
+                        return rtlpriv->cfg->maps[RTL_RC_CCK_RATE11M];
+                else
+                        return rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M];
+        }
+}
+
+static void _rtl_rc_rate_set_series(struct rtl_priv *rtlpriv,
+                                    struct ieee80211_tx_rate *rate,
+                                    struct ieee80211_tx_rate_control *txrc,
+                                    u8 tries, u8 rix, int rtsctsenable,
+                                    bool not_data)
+{
+        struct rtl_mac *mac = rtl_mac(rtlpriv);
+
+        rate->count = tries;
+        rate->idx = (rix > 0x2) ? rix : 0x2;
+
+        if (!not_data) {
+                if (txrc->short_preamble)
+                        rate->flags |= IEEE80211_TX_RC_USE_SHORT_PREAMBLE;
+                if (mac->bw_40)
+                        rate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
+                if (mac->sgi_20 || mac->sgi_40)
+                        rate->flags |= IEEE80211_TX_RC_SHORT_GI;
+                if (mac->ht_enable)
+                        rate->flags |= IEEE80211_TX_RC_MCS;
+        }
+}
+
+static void rtl_get_rate(void *ppriv, struct ieee80211_sta *sta,
+                         void *priv_sta, struct ieee80211_tx_rate_control *txrc)
+{
+        struct rtl_priv *rtlpriv = ppriv;
+        struct sk_buff *skb = txrc->skb;
+        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
+        struct ieee80211_tx_rate *rates = tx_info->control.rates;
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
+        __le16 fc = hdr->frame_control;
+        u8 try_per_rate, i, rix;
+        bool not_data = !ieee80211_is_data(fc);
+
+        if (rate_control_send_low(sta, priv_sta, txrc))
+                return;
+
+        rix = _rtl_rc_get_highest_rix(rtlpriv, skb, not_data);
+
+        try_per_rate = 1;
+        _rtl_rc_rate_set_series(rtlpriv, &rates[0], txrc,
+                                try_per_rate, rix, 1, not_data);
+
+        if (!not_data) {
+                for (i = 1; i < 4; i++)
+                        _rtl_rc_rate_set_series(rtlpriv, &rates[i],
+                                                txrc, i, (rix - i), 1,
+                                                not_data);
+        }
+}
+
+static bool _rtl_tx_aggr_check(struct rtl_priv *rtlpriv, u16 tid)
+{
+        struct rtl_mac *mac = rtl_mac(rtlpriv);
+
+        if (mac->act_scanning)
+                return false;
+
+        if (mac->cnt_after_linked < 3)
+                return false;
+
+        if (mac->tids[tid].agg.agg_state == RTL_AGG_OFF)
+                return true;
+
+        return false;
+}
+
+/*mac80211 Rate Control callbacks*/
+static void rtl_tx_status(void *ppriv,
+                          struct ieee80211_supported_band *sband,
+                          struct ieee80211_sta *sta, void *priv_sta,
+                          struct sk_buff *skb)
+{
+        struct rtl_priv *rtlpriv = ppriv;
+        struct rtl_mac *mac = rtl_mac(rtlpriv);
+        struct ieee80211_hdr *hdr;
+        __le16 fc;
+
+        hdr = (struct ieee80211_hdr *)skb->data;
+        fc = hdr->frame_control;
+
+        if (!priv_sta || !ieee80211_is_data(fc))
+                return;
+
+        if (rtl_is_special_data(mac->hw, skb, true))
+                return;
+
+        if (is_multicast_ether_addr(ieee80211_get_DA(hdr))
+            || is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
+                return;
+
+        /* Check if aggregation has to be enabled for this tid */
+        if (conf_is_ht(&mac->hw->conf) &&
+            !(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
+                if (ieee80211_is_data_qos(fc)) {
+                        u8 *qc, tid;
+
+                        qc = ieee80211_get_qos_ctl(hdr);
+                        tid = qc[0] & 0xf;
+
+                        if (_rtl_tx_aggr_check(rtlpriv, tid))
+                                ieee80211_start_tx_ba_session(sta, tid, 5000);
+                }
+        }
+}
+
+static void rtl_rate_init(void *ppriv,
+                          struct ieee80211_supported_band *sband,
+                          struct ieee80211_sta *sta, void *priv_sta)
+{
+        struct rtl_priv *rtlpriv = ppriv;
+        struct rtl_mac *mac = rtl_mac(rtlpriv);
+        u8 is_ht = conf_is_ht(&mac->hw->conf);
+
+        if ((mac->opmode == NL80211_IFTYPE_STATION) ||
+            (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
+            (mac->opmode == NL80211_IFTYPE_ADHOC)) {
+
+                switch (sband->band) {
+                case IEEE80211_BAND_2GHZ:
+                        rtlpriv->rate_priv->cur_ratetab_idx =
+                            RATR_INX_WIRELESS_G;
+                        if (is_ht)
+                                rtlpriv->rate_priv->cur_ratetab_idx =
+                                    RATR_INX_WIRELESS_NGB;
+                        break;
+                case IEEE80211_BAND_5GHZ:
+                        rtlpriv->rate_priv->cur_ratetab_idx =
+                            RATR_INX_WIRELESS_A;
+                        if (is_ht)
+                                rtlpriv->rate_priv->cur_ratetab_idx =
+                                    RATR_INX_WIRELESS_NGB;
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                 ("Invalid band\n"));
+                        rtlpriv->rate_priv->cur_ratetab_idx =
+                            RATR_INX_WIRELESS_NGB;
+                        break;
+                }
+
+                RT_TRACE(rtlpriv, COMP_RATE, DBG_DMESG,
+                         ("Choosing rate table index: %d\n",
+                          rtlpriv->rate_priv->cur_ratetab_idx));
+
+        }
+
+}
+
+static void rtl_rate_update(void *ppriv,
+                            struct ieee80211_supported_band *sband,
+                            struct ieee80211_sta *sta, void *priv_sta,
+                            u32 changed,
+                            enum nl80211_channel_type oper_chan_type)
+{
+        struct rtl_priv *rtlpriv = ppriv;
+        struct rtl_mac *mac = rtl_mac(rtlpriv);
+        struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
+        bool oper_cw40 = false, oper_sgi40;
+        bool local_cw40 = mac->bw_40;
+        bool local_sgi40 = mac->sgi_40;
+        u8 is_ht = conf_is_ht(&mac->hw->conf);
+
+        if (changed & IEEE80211_RC_HT_CHANGED) {
+                if (mac->opmode != NL80211_IFTYPE_STATION)
+                        return;
+
+                if (rtlhal->hw->conf.channel_type == NL80211_CHAN_HT40MINUS ||
+                    rtlhal->hw->conf.channel_type == NL80211_CHAN_HT40PLUS)
+                        oper_cw40 = true;
+
+                oper_sgi40 = mac->sgi_40;
+
+                if ((local_cw40 != oper_cw40) || (local_sgi40 != oper_sgi40)) {
+                        switch (sband->band) {
+                        case IEEE80211_BAND_2GHZ:
+                                rtlpriv->rate_priv->cur_ratetab_idx =
+                                    RATR_INX_WIRELESS_G;
+                                if (is_ht)
+                                        rtlpriv->rate_priv->cur_ratetab_idx =
+                                            RATR_INX_WIRELESS_NGB;
+                                break;
+                        case IEEE80211_BAND_5GHZ:
+                                rtlpriv->rate_priv->cur_ratetab_idx =
+                                    RATR_INX_WIRELESS_A;
+                                if (is_ht)
+                                        rtlpriv->rate_priv->cur_ratetab_idx =
+                                            RATR_INX_WIRELESS_NGB;
+                                break;
+                        default:
+                                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                         ("Invalid band\n"));
+                                rtlpriv->rate_priv->cur_ratetab_idx =
+                                    RATR_INX_WIRELESS_NGB;
+                                break;
+                        }
+                }
+        }
+}
+
+static void *rtl_rate_alloc(struct ieee80211_hw *hw,
+                struct dentry *debugfsdir)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        return rtlpriv;
+}
+
+static void rtl_rate_free(void *rtlpriv)
+{
+        return;
+}
+
+static void *rtl_rate_alloc_sta(void *ppriv,
+                                struct ieee80211_sta *sta, gfp_t gfp)
+{
+        struct rtl_priv *rtlpriv = ppriv;
+        struct rtl_rate_priv *rate_priv;
+
+        rate_priv = kzalloc(sizeof(struct rtl_rate_priv), gfp);
+        if (!rate_priv) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Unable to allocate private rc structure\n"));
+                return NULL;
+        }
+
+        rtlpriv->rate_priv = rate_priv;
+
+        return rate_priv;
+}
+
+static void rtl_rate_free_sta(void *rtlpriv,
+                              struct ieee80211_sta *sta, void *priv_sta)
+{
+        struct rtl_rate_priv *rate_priv = priv_sta;
+        kfree(rate_priv);
+}
+
+static struct rate_control_ops rtl_rate_ops = {
+        .module = NULL,
+        .name = "rtl_rc",
+        .alloc = rtl_rate_alloc,
+        .free = rtl_rate_free,
+        .alloc_sta = rtl_rate_alloc_sta,
+        .free_sta = rtl_rate_free_sta,
+        .rate_init = rtl_rate_init,
+        .rate_update = rtl_rate_update,
+        .tx_status = rtl_tx_status,
+        .get_rate = rtl_get_rate,
+};
+
+int rtl_rate_control_register(void)
+{
+        return ieee80211_rate_control_register(&rtl_rate_ops);
+}
+
+void rtl_rate_control_unregister(void)
+{
+        ieee80211_rate_control_unregister(&rtl_rate_ops);
+}
diff --git a/drivers/net/wireless/rtlwifi/rc.h b/drivers/net/wireless/rtlwifi/rc.h
new file mode 100644
index 000000000000..b4667c035f0b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rc.h
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL_RC_H__
+#define __RTL_RC_H__
+
+struct rtl_rate_priv {
+        u8 cur_ratetab_idx;
+        u8 ht_cap;
+};
+
+int rtl_rate_control_register(void);
+void rtl_rate_control_unregister(void);
+#endif
diff --git a/drivers/net/wireless/rtlwifi/regd.c b/drivers/net/wireless/rtlwifi/regd.c
new file mode 100644
index 000000000000..3336ca999dfd
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/regd.c
@@ -0,0 +1,400 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "wifi.h"
+#include "regd.h"
+
+static struct country_code_to_enum_rd allCountries[] = {
+        {COUNTRY_CODE_FCC, "US"},
+        {COUNTRY_CODE_IC, "US"},
+        {COUNTRY_CODE_ETSI, "EC"},
+        {COUNTRY_CODE_SPAIN, "EC"},
+        {COUNTRY_CODE_FRANCE, "EC"},
+        {COUNTRY_CODE_MKK, "JP"},
+        {COUNTRY_CODE_MKK1, "JP"},
+        {COUNTRY_CODE_ISRAEL, "EC"},
+        {COUNTRY_CODE_TELEC, "JP"},
+        {COUNTRY_CODE_MIC, "JP"},
+        {COUNTRY_CODE_GLOBAL_DOMAIN, "JP"},
+        {COUNTRY_CODE_WORLD_WIDE_13, "EC"},
+        {COUNTRY_CODE_TELEC_NETGEAR, "EC"},
+};
+
+/*
+ *Only these channels all allow active
+ *scan on all world regulatory domains
+ */
+#define RTL819x_2GHZ_CH01_11    \
+        REG_RULE(2412-10, 2462+10, 40, 0, 20, 0)
+
+/*
+ *We enable active scan on these a case
+ *by case basis by regulatory domain
+ */
+#define RTL819x_2GHZ_CH12_13    \
+        REG_RULE(2467-10, 2472+10, 40, 0, 20,\
+        NL80211_RRF_PASSIVE_SCAN)
+
+#define RTL819x_2GHZ_CH14       \
+        REG_RULE(2484-10, 2484+10, 40, 0, 20, \
+        NL80211_RRF_PASSIVE_SCAN | \
+        NL80211_RRF_NO_OFDM)
+
+static const struct ieee80211_regdomain rtl_regdom_11 = {
+        .n_reg_rules = 1,
+        .alpha2 = "99",
+        .reg_rules = {
+                      RTL819x_2GHZ_CH01_11,
+        }
+};
+
+static const struct ieee80211_regdomain rtl_regdom_global = {
+        .n_reg_rules = 3,
+        .alpha2 = "99",
+        .reg_rules = {
+                      RTL819x_2GHZ_CH01_11,
+                      RTL819x_2GHZ_CH12_13,
+                      RTL819x_2GHZ_CH14,
+        }
+};
+
+static const struct ieee80211_regdomain rtl_regdom_world = {
+        .n_reg_rules = 2,
+        .alpha2 = "99",
+        .reg_rules = {
+                      RTL819x_2GHZ_CH01_11,
+                      RTL819x_2GHZ_CH12_13,
+        }
+};
+
+static bool _rtl_is_radar_freq(u16 center_freq)
+{
+        return (center_freq >= 5260 && center_freq <= 5700);
+}
+
+static void _rtl_reg_apply_beaconing_flags(struct wiphy *wiphy,
+                                           enum nl80211_reg_initiator initiator)
+{
+        enum ieee80211_band band;
+        struct ieee80211_supported_band *sband;
+        const struct ieee80211_reg_rule *reg_rule;
+        struct ieee80211_channel *ch;
+        unsigned int i;
+        u32 bandwidth = 0;
+        int r;
+
+        for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
+
+                if (!wiphy->bands[band])
+                        continue;
+
+                sband = wiphy->bands[band];
+
+                for (i = 0; i < sband->n_channels; i++) {
+                        ch = &sband->channels[i];
+                        if (_rtl_is_radar_freq(ch->center_freq) ||
+                            (ch->flags & IEEE80211_CHAN_RADAR))
+                                continue;
+                        if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) {
+                                r = freq_reg_info(wiphy, ch->center_freq,
+                                                  bandwidth, &reg_rule);
+                                if (r)
+                                        continue;
+
+                                /*
+                                 *If 11d had a rule for this channel ensure
+                                 *we enable adhoc/beaconing if it allows us to
+                                 *use it. Note that we would have disabled it
+                                 *by applying our static world regdomain by
+                                 *default during init, prior to calling our
+                                 *regulatory_hint().
+                                 */
+
+                                if (!(reg_rule->flags & NL80211_RRF_NO_IBSS))
+                                        ch->flags &= ~IEEE80211_CHAN_NO_IBSS;
+                                if (!(reg_rule->
+                                     flags & NL80211_RRF_PASSIVE_SCAN))
+                                        ch->flags &=
+                                            ~IEEE80211_CHAN_PASSIVE_SCAN;
+                        } else {
+                                if (ch->beacon_found)
+                                        ch->flags &= ~(IEEE80211_CHAN_NO_IBSS |
+                                                  IEEE80211_CHAN_PASSIVE_SCAN);
+                        }
+                }
+        }
+}
+
+/* Allows active scan scan on Ch 12 and 13 */
+static void _rtl_reg_apply_active_scan_flags(struct wiphy *wiphy,
+                                             enum nl80211_reg_initiator
+                                             initiator)
+{
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *ch;
+        const struct ieee80211_reg_rule *reg_rule;
+        u32 bandwidth = 0;
+        int r;
+
+        sband = wiphy->bands[IEEE80211_BAND_2GHZ];
+
+        /*
+         *If no country IE has been received always enable active scan
+         *on these channels. This is only done for specific regulatory SKUs
+         */
+        if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) {
+                ch = &sband->channels[11];      /* CH 12 */
+                if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+                        ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+                ch = &sband->channels[12];      /* CH 13 */
+                if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+                        ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+                return;
+        }
+
+        /*
+         *If a country IE has been recieved check its rule for this
+         *channel first before enabling active scan. The passive scan
+         *would have been enforced by the initial processing of our
+         *custom regulatory domain.
+         */
+
+        ch = &sband->channels[11];      /* CH 12 */
+        r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
+        if (!r) {
+                if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
+                        if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+                                ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+        }
+
+        ch = &sband->channels[12];      /* CH 13 */
+        r = freq_reg_info(wiphy, ch->center_freq, bandwidth, &reg_rule);
+        if (!r) {
+                if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN))
+                        if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN)
+                                ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN;
+        }
+}
+
+/*
+ *Always apply Radar/DFS rules on
+ *freq range 5260 MHz - 5700 MHz
+ */
+static void _rtl_reg_apply_radar_flags(struct wiphy *wiphy)
+{
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *ch;
+        unsigned int i;
+
+        if (!wiphy->bands[IEEE80211_BAND_5GHZ])
+                return;
+
+        sband = wiphy->bands[IEEE80211_BAND_5GHZ];
+
+        for (i = 0; i < sband->n_channels; i++) {
+                ch = &sband->channels[i];
+                if (!_rtl_is_radar_freq(ch->center_freq))
+                        continue;
+
+                /*
+                 *We always enable radar detection/DFS on this
+                 *frequency range. Additionally we also apply on
+                 *this frequency range:
+                 *- If STA mode does not yet have DFS supports disable
+                 * active scanning
+                 *- If adhoc mode does not support DFS yet then disable
+                 * adhoc in the frequency.
+                 *- If AP mode does not yet support radar detection/DFS
+                 *do not allow AP mode
+                 */
+                if (!(ch->flags & IEEE80211_CHAN_DISABLED))
+                        ch->flags |= IEEE80211_CHAN_RADAR |
+                            IEEE80211_CHAN_NO_IBSS |
+                            IEEE80211_CHAN_PASSIVE_SCAN;
+        }
+}
+
+static void _rtl_reg_apply_world_flags(struct wiphy *wiphy,
+                                       enum nl80211_reg_initiator initiator,
+                                       struct rtl_regulatory *reg)
+{
+        _rtl_reg_apply_beaconing_flags(wiphy, initiator);
+        _rtl_reg_apply_active_scan_flags(wiphy, initiator);
+        return;
+}
+
+static void _rtl_dump_channel_map(struct wiphy *wiphy)
+{
+        enum ieee80211_band band;
+        struct ieee80211_supported_band *sband;
+        struct ieee80211_channel *ch;
+        unsigned int i;
+
+        for (band = 0; band < IEEE80211_NUM_BANDS; band++) {
+                if (!wiphy->bands[band])
+                        continue;
+                sband = wiphy->bands[band];
+                for (i = 0; i < sband->n_channels; i++)
+                        ch = &sband->channels[i];
+        }
+}
+
+static int _rtl_reg_notifier_apply(struct wiphy *wiphy,
+                                   struct regulatory_request *request,
+                                   struct rtl_regulatory *reg)
+{
+        /* We always apply this */
+        _rtl_reg_apply_radar_flags(wiphy);
+
+        switch (request->initiator) {
+        case NL80211_REGDOM_SET_BY_DRIVER:
+        case NL80211_REGDOM_SET_BY_CORE:
+        case NL80211_REGDOM_SET_BY_USER:
+                break;
+        case NL80211_REGDOM_SET_BY_COUNTRY_IE:
+                _rtl_reg_apply_world_flags(wiphy, request->initiator, reg);
+                break;
+        }
+
+        _rtl_dump_channel_map(wiphy);
+
+        return 0;
+}
+
+static const struct ieee80211_regdomain *_rtl_regdomain_select(
+                                               struct rtl_regulatory *reg)
+{
+        switch (reg->country_code) {
+        case COUNTRY_CODE_FCC:
+        case COUNTRY_CODE_IC:
+                return &rtl_regdom_11;
+        case COUNTRY_CODE_ETSI:
+        case COUNTRY_CODE_SPAIN:
+        case COUNTRY_CODE_FRANCE:
+        case COUNTRY_CODE_ISRAEL:
+        case COUNTRY_CODE_TELEC_NETGEAR:
+                return &rtl_regdom_world;
+        case COUNTRY_CODE_MKK:
+        case COUNTRY_CODE_MKK1:
+        case COUNTRY_CODE_TELEC:
+        case COUNTRY_CODE_MIC:
+                return &rtl_regdom_global;
+        case COUNTRY_CODE_GLOBAL_DOMAIN:
+                return &rtl_regdom_global;
+        case COUNTRY_CODE_WORLD_WIDE_13:
+                return &rtl_regdom_world;
+        default:
+                return &rtl_regdom_world;
+        }
+}
+
+static int _rtl_regd_init_wiphy(struct rtl_regulatory *reg,
+                                struct wiphy *wiphy,
+                                int (*reg_notifier) (struct wiphy *wiphy,
+                                                     struct regulatory_request *
+                                                     request))
+{
+        const struct ieee80211_regdomain *regd;
+
+        wiphy->reg_notifier = reg_notifier;
+        wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY;
+        wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY;
+        wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS;
+        regd = _rtl_regdomain_select(reg);
+        wiphy_apply_custom_regulatory(wiphy, regd);
+        _rtl_reg_apply_radar_flags(wiphy);
+        _rtl_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg);
+        return 0;
+}
+
+static struct country_code_to_enum_rd *_rtl_regd_find_country(u16 countrycode)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(allCountries); i++) {
+                if (allCountries[i].countrycode == countrycode)
+                        return &allCountries[i];
+        }
+        return NULL;
+}
+
+int rtl_regd_init(struct ieee80211_hw *hw,
+                  int (*reg_notifier) (struct wiphy *wiphy,
+                                       struct regulatory_request *request))
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct wiphy *wiphy = hw->wiphy;
+        struct country_code_to_enum_rd *country = NULL;
+
+        if (wiphy == NULL || &rtlpriv->regd == NULL)
+                return -EINVAL;
+
+        /* force the channel plan to world wide 13 */
+        rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13;
+
+        RT_TRACE(rtlpriv, COMP_REGD, DBG_TRACE,
+                 (KERN_DEBUG "rtl: EEPROM regdomain: 0x%0x\n",
+                  rtlpriv->regd.country_code));
+
+        if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) {
+                RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG,
+                         (KERN_DEBUG "rtl: EEPROM indicates invalid contry code"
+                          "world wide 13 should be used\n"));
+
+                rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13;
+        }
+
+        country = _rtl_regd_find_country(rtlpriv->regd.country_code);
+
+        if (country) {
+                rtlpriv->regd.alpha2[0] = country->isoName[0];
+                rtlpriv->regd.alpha2[1] = country->isoName[1];
+        } else {
+                rtlpriv->regd.alpha2[0] = '0';
+                rtlpriv->regd.alpha2[1] = '0';
+        }
+
+        RT_TRACE(rtlpriv, COMP_REGD, DBG_TRACE,
+                 (KERN_DEBUG "rtl: Country alpha2 being used: %c%c\n",
+                  rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]));
+
+        _rtl_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier);
+
+        return 0;
+}
+
+int rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
+{
+        struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        RT_TRACE(rtlpriv, COMP_REGD, DBG_LOUD, ("\n"));
+
+        return _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd);
+}
diff --git a/drivers/net/wireless/rtlwifi/regd.h b/drivers/net/wireless/rtlwifi/regd.h
new file mode 100644
index 000000000000..4cdbc4ae76d4
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/regd.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL_REGD_H__
+#define __RTL_REGD_H__
+
+struct country_code_to_enum_rd {
+        u16 countrycode;
+        const char *isoName;
+};
+
+enum country_code_type_t {
+        COUNTRY_CODE_FCC = 0,
+        COUNTRY_CODE_IC = 1,
+        COUNTRY_CODE_ETSI = 2,
+        COUNTRY_CODE_SPAIN = 3,
+        COUNTRY_CODE_FRANCE = 4,
+        COUNTRY_CODE_MKK = 5,
+        COUNTRY_CODE_MKK1 = 6,
+        COUNTRY_CODE_ISRAEL = 7,
+        COUNTRY_CODE_TELEC = 8,
+        COUNTRY_CODE_MIC = 9,
+        COUNTRY_CODE_GLOBAL_DOMAIN = 10,
+        COUNTRY_CODE_WORLD_WIDE_13 = 11,
+        COUNTRY_CODE_TELEC_NETGEAR = 12,
+
+        /*add new channel plan above this line */
+        COUNTRY_CODE_MAX
+};
+
+int rtl_regd_init(struct ieee80211_hw *hw,
+                  int (*reg_notifier) (struct wiphy *wiphy,
+                                       struct regulatory_request *request));
+int rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile b/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
new file mode 100644
index 000000000000..0f0be7c763b8
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
@@ -0,0 +1,12 @@
+rtl8192ce-objs :=               \
+                dm.o            \
+                fw.o            \
+                hw.o            \
+                led.o           \
+                phy.o           \
+                rf.o            \
+                sw.o            \
+                table.o         \
+                trx.o
+
+obj-$(CONFIG_RTL8192CE) += rtl8192ce.o
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/def.h b/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
new file mode 100644
index 000000000000..83cd64895292
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
@@ -0,0 +1,257 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92C_DEF_H__
+#define __RTL92C_DEF_H__
+
+#define HAL_RETRY_LIMIT_INFRA                           48
+#define HAL_RETRY_LIMIT_AP_ADHOC                        7
+
+#define PHY_RSSI_SLID_WIN_MAX                           100
+#define PHY_LINKQUALITY_SLID_WIN_MAX                    20
+#define PHY_BEACON_RSSI_SLID_WIN_MAX                    10
+
+#define RESET_DELAY_8185                                20
+
+#define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
+#define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
+
+#define NUM_OF_FIRMWARE_QUEUE                           10
+#define NUM_OF_PAGES_IN_FW                              0x100
+#define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
+#define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
+#define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
+#define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
+#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA                    0x0
+#define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
+#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT                    0x02
+#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH                    0x02
+#define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
+#define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
+
+#define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM                  0x026
+#define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM                  0x048
+#define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM                  0x048
+#define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM                  0x026
+#define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM                 0x00
+
+#define MAX_LINES_HWCONFIG_TXT                          1000
+#define MAX_BYTES_LINE_HWCONFIG_TXT                     256
+
+#define SW_THREE_WIRE                                   0
+#define HW_THREE_WIRE                                   2
+
+#define BT_DEMO_BOARD                                   0
+#define BT_QA_BOARD                                     1
+#define BT_FPGA                                         2
+
+#define RX_SMOOTH_FACTOR                                20
+
+#define HAL_PRIME_CHNL_OFFSET_DONT_CARE                 0
+#define HAL_PRIME_CHNL_OFFSET_LOWER                     1
+#define HAL_PRIME_CHNL_OFFSET_UPPER                     2
+
+#define MAX_H2C_QUEUE_NUM                               10
+
+#define RX_MPDU_QUEUE                                   0
+#define RX_CMD_QUEUE                                    1
+#define RX_MAX_QUEUE                                    2
+#define AC2QUEUEID(_AC)                                 (_AC)
+
+#define C2H_RX_CMD_HDR_LEN                              8
+#define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
+        LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
+#define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
+        LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
+#define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
+        LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
+#define GET_C2H_CMD_CONTINUE(__prxhdr)          \
+        LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
+#define GET_C2H_CMD_CONTENT(__prxhdr)           \
+        ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
+
+#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
+        LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
+#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)       \
+        LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
+#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
+        LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
+#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
+        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
+#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)     \
+        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
+#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
+        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
+#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)       \
+        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
+#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)      \
+        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
+#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)       \
+        LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
+
+#define CHIP_VER_B                      BIT(4)
+#define CHIP_92C_BITMASK                BIT(0)
+#define CHIP_92C_1T2R                   0x03
+#define CHIP_92C                        0x01
+#define CHIP_88C                        0x00
+
+enum version_8192c {
+        VERSION_A_CHIP_92C = 0x01,
+        VERSION_A_CHIP_88C = 0x00,
+        VERSION_B_CHIP_92C = 0x11,
+        VERSION_B_CHIP_88C = 0x10,
+        VERSION_UNKNOWN = 0x88,
+};
+
+#define IS_CHIP_VER_B(version)  ((version & CHIP_VER_B) ? true : false)
+#define IS_92C_SERIAL(version)  ((version & CHIP_92C_BITMASK) ? true : false)
+
+enum rtl819x_loopback_e {
+        RTL819X_NO_LOOPBACK = 0,
+        RTL819X_MAC_LOOPBACK = 1,
+        RTL819X_DMA_LOOPBACK = 2,
+        RTL819X_CCK_LOOPBACK = 3,
+};
+
+enum rf_optype {
+        RF_OP_BY_SW_3WIRE = 0,
+        RF_OP_BY_FW,
+        RF_OP_MAX
+};
+
+enum rf_power_state {
+        RF_ON,
+        RF_OFF,
+        RF_SLEEP,
+        RF_SHUT_DOWN,
+};
+
+enum power_save_mode {
+        POWER_SAVE_MODE_ACTIVE,
+        POWER_SAVE_MODE_SAVE,
+};
+
+enum power_polocy_config {
+        POWERCFG_MAX_POWER_SAVINGS,
+        POWERCFG_GLOBAL_POWER_SAVINGS,
+        POWERCFG_LOCAL_POWER_SAVINGS,
+        POWERCFG_LENOVO,
+};
+
+enum interface_select_pci {
+        INTF_SEL1_MINICARD = 0,
+        INTF_SEL0_PCIE = 1,
+        INTF_SEL2_RSV = 2,
+        INTF_SEL3_RSV = 3,
+};
+
+enum hal_fw_c2h_cmd_id {
+        HAL_FW_C2H_CMD_Read_MACREG = 0,
+        HAL_FW_C2H_CMD_Read_BBREG = 1,
+        HAL_FW_C2H_CMD_Read_RFREG = 2,
+        HAL_FW_C2H_CMD_Read_EEPROM = 3,
+        HAL_FW_C2H_CMD_Read_EFUSE = 4,
+        HAL_FW_C2H_CMD_Read_CAM = 5,
+        HAL_FW_C2H_CMD_Get_BasicRate = 6,
+        HAL_FW_C2H_CMD_Get_DataRate = 7,
+        HAL_FW_C2H_CMD_Survey = 8,
+        HAL_FW_C2H_CMD_SurveyDone = 9,
+        HAL_FW_C2H_CMD_JoinBss = 10,
+        HAL_FW_C2H_CMD_AddSTA = 11,
+        HAL_FW_C2H_CMD_DelSTA = 12,
+        HAL_FW_C2H_CMD_AtimDone = 13,
+        HAL_FW_C2H_CMD_TX_Report = 14,
+        HAL_FW_C2H_CMD_CCX_Report = 15,
+        HAL_FW_C2H_CMD_DTM_Report = 16,
+        HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
+        HAL_FW_C2H_CMD_C2HLBK = 18,
+        HAL_FW_C2H_CMD_C2HDBG = 19,
+        HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
+        HAL_FW_C2H_CMD_MAX
+};
+
+enum rtl_desc_qsel {
+        QSLT_BK = 0x2,
+        QSLT_BE = 0x0,
+        QSLT_VI = 0x5,
+        QSLT_VO = 0x7,
+        QSLT_BEACON = 0x10,
+        QSLT_HIGH = 0x11,
+        QSLT_MGNT = 0x12,
+        QSLT_CMD = 0x13,
+};
+
+enum rtl_desc92c_rate {
+        DESC92C_RATE1M = 0x00,
+        DESC92C_RATE2M = 0x01,
+        DESC92C_RATE5_5M = 0x02,
+        DESC92C_RATE11M = 0x03,
+
+        DESC92C_RATE6M = 0x04,
+        DESC92C_RATE9M = 0x05,
+        DESC92C_RATE12M = 0x06,
+        DESC92C_RATE18M = 0x07,
+        DESC92C_RATE24M = 0x08,
+        DESC92C_RATE36M = 0x09,
+        DESC92C_RATE48M = 0x0a,
+        DESC92C_RATE54M = 0x0b,
+
+        DESC92C_RATEMCS0 = 0x0c,
+        DESC92C_RATEMCS1 = 0x0d,
+        DESC92C_RATEMCS2 = 0x0e,
+        DESC92C_RATEMCS3 = 0x0f,
+        DESC92C_RATEMCS4 = 0x10,
+        DESC92C_RATEMCS5 = 0x11,
+        DESC92C_RATEMCS6 = 0x12,
+        DESC92C_RATEMCS7 = 0x13,
+        DESC92C_RATEMCS8 = 0x14,
+        DESC92C_RATEMCS9 = 0x15,
+        DESC92C_RATEMCS10 = 0x16,
+        DESC92C_RATEMCS11 = 0x17,
+        DESC92C_RATEMCS12 = 0x18,
+        DESC92C_RATEMCS13 = 0x19,
+        DESC92C_RATEMCS14 = 0x1a,
+        DESC92C_RATEMCS15 = 0x1b,
+        DESC92C_RATEMCS15_SG = 0x1c,
+        DESC92C_RATEMCS32 = 0x20,
+};
+
+struct phy_sts_cck_8192s_t {
+        u8 adc_pwdb_X[4];
+        u8 sq_rpt;
+        u8 cck_agc_rpt;
+};
+
+struct h2c_cmd_8192c {
+        u8 element_id;
+        u32 cmd_len;
+        u8 *p_cmdbuffer;
+};
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
new file mode 100644
index 000000000000..62e7c64e087b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
@@ -0,0 +1,1473 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../wifi.h"
+#include "../base.h"
+#include "reg.h"
+#include "def.h"
+#include "phy.h"
+#include "dm.h"
+#include "fw.h"
+
+struct dig_t dm_digtable;
+static struct ps_t dm_pstable;
+
+static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
+        0x7f8001fe,
+        0x788001e2,
+        0x71c001c7,
+        0x6b8001ae,
+        0x65400195,
+        0x5fc0017f,
+        0x5a400169,
+        0x55400155,
+        0x50800142,
+        0x4c000130,
+        0x47c0011f,
+        0x43c0010f,
+        0x40000100,
+        0x3c8000f2,
+        0x390000e4,
+        0x35c000d7,
+        0x32c000cb,
+        0x300000c0,
+        0x2d4000b5,
+        0x2ac000ab,
+        0x288000a2,
+        0x26000098,
+        0x24000090,
+        0x22000088,
+        0x20000080,
+        0x1e400079,
+        0x1c800072,
+        0x1b00006c,
+        0x19800066,
+        0x18000060,
+        0x16c0005b,
+        0x15800056,
+        0x14400051,
+        0x1300004c,
+        0x12000048,
+        0x11000044,
+        0x10000040,
+};
+
+static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
+        {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
+        {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
+        {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
+        {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
+        {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
+        {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
+        {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
+        {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
+        {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
+        {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
+        {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
+        {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
+        {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
+        {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
+        {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
+        {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
+        {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
+        {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
+        {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
+        {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
+        {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
+        {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
+        {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
+        {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
+        {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
+        {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
+        {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
+        {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
+        {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
+        {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
+        {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
+        {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
+        {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
+};
+
+static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
+        {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
+        {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
+        {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
+        {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
+        {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
+        {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
+        {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
+        {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
+        {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
+        {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
+        {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
+        {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
+        {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
+        {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
+        {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
+        {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
+        {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
+        {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
+        {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
+        {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
+        {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
+        {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
+        {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
+        {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
+        {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
+        {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
+        {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
+        {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
+        {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
+        {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
+        {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
+        {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
+        {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
+};
+
+static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
+{
+        dm_digtable.dig_enable_flag = true;
+        dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
+        dm_digtable.cur_igvalue = 0x20;
+        dm_digtable.pre_igvalue = 0x0;
+        dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
+        dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
+        dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
+        dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
+        dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
+        dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
+        dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
+        dm_digtable.rx_gain_range_max = DM_DIG_MAX;
+        dm_digtable.rx_gain_range_min = DM_DIG_MIN;
+        dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
+        dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
+        dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
+        dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
+        dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
+}
+
+static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        long rssi_val_min = 0;
+
+        if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
+            (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
+                if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
+                        rssi_val_min =
+                            (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
+                             rtlpriv->dm.undecorated_smoothed_pwdb) ?
+                            rtlpriv->dm.undecorated_smoothed_pwdb :
+                            rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+                else
+                        rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
+        } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
+                   dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
+                rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
+        } else if (dm_digtable.curmultista_connectstate ==
+                   DIG_MULTISTA_CONNECT) {
+                rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+        }
+
+        return (u8) rssi_val_min;
+}
+
+static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
+{
+        u32 ret_value;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
+
+        ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
+        falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
+
+        ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
+        falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
+        falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
+
+        ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
+        falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
+        falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
+            falsealm_cnt->cnt_rate_illegal +
+            falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
+
+        rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
+        ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
+        falsealm_cnt->cnt_cck_fail = ret_value;
+
+        ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
+        falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
+        falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
+                                 falsealm_cnt->cnt_rate_illegal +
+                                 falsealm_cnt->cnt_crc8_fail +
+                                 falsealm_cnt->cnt_mcs_fail +
+                                 falsealm_cnt->cnt_cck_fail);
+
+        rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
+        rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
+        rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
+        rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
+                  "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
+                  falsealm_cnt->cnt_parity_fail,
+                  falsealm_cnt->cnt_rate_illegal,
+                  falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
+                  falsealm_cnt->cnt_ofdm_fail,
+                  falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
+}
+
+static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 value_igi = dm_digtable.cur_igvalue;
+
+        if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
+                value_igi--;
+        else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
+                value_igi += 0;
+        else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
+                value_igi++;
+        else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
+                value_igi += 2;
+        if (value_igi > DM_DIG_FA_UPPER)
+                value_igi = DM_DIG_FA_UPPER;
+        else if (value_igi < DM_DIG_FA_LOWER)
+                value_igi = DM_DIG_FA_LOWER;
+        if (rtlpriv->falsealm_cnt.cnt_all > 10000)
+                value_igi = 0x32;
+
+        dm_digtable.cur_igvalue = value_igi;
+        rtl92c_dm_write_dig(hw);
+}
+
+static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
+                if ((dm_digtable.backoff_val - 2) <
+                    dm_digtable.backoff_val_range_min)
+                        dm_digtable.backoff_val =
+                            dm_digtable.backoff_val_range_min;
+                else
+                        dm_digtable.backoff_val -= 2;
+        } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
+                if ((dm_digtable.backoff_val + 2) >
+                    dm_digtable.backoff_val_range_max)
+                        dm_digtable.backoff_val =
+                            dm_digtable.backoff_val_range_max;
+                else
+                        dm_digtable.backoff_val += 2;
+        }
+
+        if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
+            dm_digtable.rx_gain_range_max)
+                dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
+        else if ((dm_digtable.rssi_val_min + 10 -
+                  dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
+                dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
+        else
+                dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
+                    dm_digtable.backoff_val;
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("rssi_val_min = %x backoff_val %x\n",
+                  dm_digtable.rssi_val_min, dm_digtable.backoff_val));
+
+        rtl92c_dm_write_dig(hw);
+}
+
+static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
+{
+        static u8 binitialized; /* initialized to false */
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+        bool b_multi_sta = false;
+
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                b_multi_sta = true;
+
+        if ((b_multi_sta == false) || (dm_digtable.cursta_connectctate !=
+                                       DIG_STA_DISCONNECT)) {
+                binitialized = false;
+                dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
+                return;
+        } else if (binitialized == false) {
+                binitialized = true;
+                dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
+                dm_digtable.cur_igvalue = 0x20;
+                rtl92c_dm_write_dig(hw);
+        }
+
+        if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
+                if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
+                    (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
+
+                        if (dm_digtable.dig_ext_port_stage ==
+                            DIG_EXT_PORT_STAGE_2) {
+                                dm_digtable.cur_igvalue = 0x20;
+                                rtl92c_dm_write_dig(hw);
+                        }
+
+                        dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
+                } else if (rssi_strength > dm_digtable.rssi_highthresh) {
+                        dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
+                        rtl92c_dm_ctrl_initgain_by_fa(hw);
+                }
+        } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
+                dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
+                dm_digtable.cur_igvalue = 0x20;
+                rtl92c_dm_write_dig(hw);
+        }
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("curmultista_connectstate = "
+                  "%x dig_ext_port_stage %x\n",
+                  dm_digtable.curmultista_connectstate,
+                  dm_digtable.dig_ext_port_stage));
+}
+
+static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("presta_connectstate = %x,"
+                  " cursta_connectctate = %x\n",
+                  dm_digtable.presta_connectstate,
+                  dm_digtable.cursta_connectctate));
+
+        if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
+            || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
+            || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
+
+                if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
+                        dm_digtable.rssi_val_min =
+                            rtl92c_dm_initial_gain_min_pwdb(hw);
+                        rtl92c_dm_ctrl_initgain_by_rssi(hw);
+                }
+        } else {
+                dm_digtable.rssi_val_min = 0;
+                dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
+                dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
+                dm_digtable.cur_igvalue = 0x20;
+                dm_digtable.pre_igvalue = 0;
+                rtl92c_dm_write_dig(hw);
+        }
+}
+
+static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
+                dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
+
+                if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
+                        if (dm_digtable.rssi_val_min <= 25)
+                                dm_digtable.cur_cck_pd_state =
+                                    CCK_PD_STAGE_LowRssi;
+                        else
+                                dm_digtable.cur_cck_pd_state =
+                                    CCK_PD_STAGE_HighRssi;
+                } else {
+                        if (dm_digtable.rssi_val_min <= 20)
+                                dm_digtable.cur_cck_pd_state =
+                                    CCK_PD_STAGE_LowRssi;
+                        else
+                                dm_digtable.cur_cck_pd_state =
+                                    CCK_PD_STAGE_HighRssi;
+                }
+        } else {
+                dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
+        }
+
+        if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
+                if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
+                        if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
+                                dm_digtable.cur_cck_fa_state =
+                                    CCK_FA_STAGE_High;
+                        else
+                                dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
+
+                        if (dm_digtable.pre_cck_fa_state !=
+                            dm_digtable.cur_cck_fa_state) {
+                                if (dm_digtable.cur_cck_fa_state ==
+                                    CCK_FA_STAGE_Low)
+                                        rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
+                                                      0x83);
+                                else
+                                        rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
+                                                      0xcd);
+
+                                dm_digtable.pre_cck_fa_state =
+                                    dm_digtable.cur_cck_fa_state;
+                        }
+
+                        rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
+
+                        if (IS_92C_SERIAL(rtlhal->version))
+                                rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
+                                              MASKBYTE2, 0xd7);
+                } else {
+                        rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
+                        rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
+
+                        if (IS_92C_SERIAL(rtlhal->version))
+                                rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
+                                              MASKBYTE2, 0xd3);
+                }
+                dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
+        }
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
+                 ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
+}
+
+static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
+{
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        if (mac->act_scanning == true)
+                return;
+
+        if ((mac->link_state > MAC80211_NOLINK) &&
+            (mac->link_state < MAC80211_LINKED))
+                dm_digtable.cursta_connectctate = DIG_STA_BEFORE_CONNECT;
+        else if (mac->link_state >= MAC80211_LINKED)
+                dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
+        else
+                dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
+
+        rtl92c_dm_initial_gain_sta(hw);
+        rtl92c_dm_initial_gain_multi_sta(hw);
+        rtl92c_dm_cck_packet_detection_thresh(hw);
+
+        dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
+
+}
+
+static void rtl92c_dm_dig(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->dm.b_dm_initialgain_enable == false)
+                return;
+        if (dm_digtable.dig_enable_flag == false)
+                return;
+
+        rtl92c_dm_ctrl_initgain_by_twoport(hw);
+
+}
+
+static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->dm.bdynamic_txpower_enable = false;
+
+        rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
+        rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
+}
+
+static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        long undecorated_smoothed_pwdb;
+
+        if (!rtlpriv->dm.bdynamic_txpower_enable)
+                return;
+
+        if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
+                rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
+                return;
+        }
+
+        if ((mac->link_state < MAC80211_LINKED) &&
+            (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
+                         ("Not connected to any\n"));
+
+                rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
+
+                rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
+                return;
+        }
+
+        if (mac->link_state >= MAC80211_LINKED) {
+                if (mac->opmode == NL80211_IFTYPE_ADHOC) {
+                        undecorated_smoothed_pwdb =
+                            rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+                        RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                                 ("AP Client PWDB = 0x%lx\n",
+                                  undecorated_smoothed_pwdb));
+                } else {
+                        undecorated_smoothed_pwdb =
+                            rtlpriv->dm.undecorated_smoothed_pwdb;
+                        RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                                 ("STA Default Port PWDB = 0x%lx\n",
+                                  undecorated_smoothed_pwdb));
+                }
+        } else {
+                undecorated_smoothed_pwdb =
+                    rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("AP Ext Port PWDB = 0x%lx\n",
+                          undecorated_smoothed_pwdb));
+        }
+
+        if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
+                rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
+        } else if ((undecorated_smoothed_pwdb <
+                    (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
+                   (undecorated_smoothed_pwdb >=
+                    TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
+
+                rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
+        } else if (undecorated_smoothed_pwdb <
+                   (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
+                rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("TXHIGHPWRLEVEL_NORMAL\n"));
+        }
+
+        if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
+                          rtlphy->current_channel));
+                rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
+        }
+
+        rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
+}
+
+void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
+                 ("cur_igvalue = 0x%x, "
+                  "pre_igvalue = 0x%x, backoff_val = %d\n",
+                  dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
+                  dm_digtable.backoff_val));
+
+        if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
+                rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
+                              dm_digtable.cur_igvalue);
+                rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
+                              dm_digtable.cur_igvalue);
+
+                dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
+        }
+}
+
+static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
+
+        u8 h2c_parameter[3] = { 0 };
+
+        return;
+
+        if (tmpentry_max_pwdb != 0) {
+                rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
+                    tmpentry_max_pwdb;
+        } else {
+                rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
+        }
+
+        if (tmpentry_min_pwdb != 0xff) {
+                rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
+                    tmpentry_min_pwdb;
+        } else {
+                rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
+        }
+
+        h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
+        h2c_parameter[0] = 0;
+
+        rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
+}
+
+void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        rtlpriv->dm.bcurrent_turbo_edca = false;
+        rtlpriv->dm.bis_any_nonbepkts = false;
+        rtlpriv->dm.bis_cur_rdlstate = false;
+}
+
+static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        static u64 last_txok_cnt;
+        static u64 last_rxok_cnt;
+        u64 cur_txok_cnt;
+        u64 cur_rxok_cnt;
+        u32 edca_be_ul = 0x5ea42b;
+        u32 edca_be_dl = 0x5ea42b;
+
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                goto dm_checkedcaturbo_exit;
+
+        if (mac->link_state != MAC80211_LINKED) {
+                rtlpriv->dm.bcurrent_turbo_edca = false;
+                return;
+        }
+
+        if (!mac->ht_enable) {  /*FIX MERGE */
+                if (!(edca_be_ul & 0xffff0000))
+                        edca_be_ul |= 0x005e0000;
+
+                if (!(edca_be_dl & 0xffff0000))
+                        edca_be_dl |= 0x005e0000;
+        }
+
+        if ((!rtlpriv->dm.bis_any_nonbepkts) &&
+            (!rtlpriv->dm.b_disable_framebursting)) {
+                cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
+                cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
+                if (cur_rxok_cnt > 4 * cur_txok_cnt) {
+                        if (!rtlpriv->dm.bis_cur_rdlstate ||
+                            !rtlpriv->dm.bcurrent_turbo_edca) {
+                                rtl_write_dword(rtlpriv,
+                                                REG_EDCA_BE_PARAM,
+                                                edca_be_dl);
+                                rtlpriv->dm.bis_cur_rdlstate = true;
+                        }
+                } else {
+                        if (rtlpriv->dm.bis_cur_rdlstate ||
+                            !rtlpriv->dm.bcurrent_turbo_edca) {
+                                rtl_write_dword(rtlpriv,
+                                                REG_EDCA_BE_PARAM,
+                                                edca_be_ul);
+                                rtlpriv->dm.bis_cur_rdlstate = false;
+                        }
+                }
+                rtlpriv->dm.bcurrent_turbo_edca = true;
+        } else {
+                if (rtlpriv->dm.bcurrent_turbo_edca) {
+                        u8 tmp = AC0_BE;
+                        rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                      HW_VAR_AC_PARAM,
+                                                      (u8 *) (&tmp));
+                        rtlpriv->dm.bcurrent_turbo_edca = false;
+                }
+        }
+
+dm_checkedcaturbo_exit:
+        rtlpriv->dm.bis_any_nonbepkts = false;
+        last_txok_cnt = rtlpriv->stats.txbytesunicast;
+        last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
+}
+
+static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
+                                                             *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 thermalvalue, delta, delta_lck, delta_iqk;
+        long ele_a, ele_d, temp_cck, val_x, value32;
+        long val_y, ele_c;
+        u8 ofdm_index[2], cck_index, ofdm_index_old[2], cck_index_old;
+        int i;
+        bool is2t = IS_92C_SERIAL(rtlhal->version);
+        u8 txpwr_level[2] = {0, 0};
+        u8 ofdm_min_index = 6, rf;
+
+        rtlpriv->dm.btxpower_trackingInit = true;
+        RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                 ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
+
+        thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
+
+        RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
+                  "eeprom_thermalmeter 0x%x\n",
+                  thermalvalue, rtlpriv->dm.thermalvalue,
+                  rtlefuse->eeprom_thermalmeter));
+
+        rtl92c_phy_ap_calibrate(hw, (thermalvalue -
+                                     rtlefuse->eeprom_thermalmeter));
+        if (is2t)
+                rf = 2;
+        else
+                rf = 1;
+
+        if (thermalvalue) {
+                ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
+                                      MASKDWORD) & MASKOFDM_D;
+
+                for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
+                        if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
+                                ofdm_index_old[0] = (u8) i;
+
+                                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                                        ("Initial pathA ele_d reg0x%x = 0x%lx, "
+                                         "ofdm_index=0x%x\n",
+                                         ROFDM0_XATXIQIMBALANCE,
+                                         ele_d, ofdm_index_old[0]));
+                                break;
+                        }
+                }
+
+                if (is2t) {
+                        ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
+                                              MASKDWORD) & MASKOFDM_D;
+
+                        for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
+                                if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
+                                        ofdm_index_old[1] = (u8) i;
+
+                                        RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
+                                           DBG_LOUD,
+                                           ("Initial pathB ele_d reg0x%x = "
+                                           "0x%lx, ofdm_index=0x%x\n",
+                                           ROFDM0_XBTXIQIMBALANCE, ele_d,
+                                           ofdm_index_old[1]));
+                                        break;
+                                }
+                        }
+                }
+
+                temp_cck =
+                    rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
+
+                for (i = 0; i < CCK_TABLE_LENGTH; i++) {
+                        if (rtlpriv->dm.b_cck_inch14) {
+                                if (memcmp((void *)&temp_cck,
+                                           (void *)&cckswing_table_ch14[i][2],
+                                           4) == 0) {
+                                        cck_index_old = (u8) i;
+
+                                        RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
+                                                 DBG_LOUD,
+                                                 ("Initial reg0x%x = 0x%lx, "
+                                                  "cck_index=0x%x, ch 14 %d\n",
+                                                  RCCK0_TXFILTER2, temp_cck,
+                                                  cck_index_old,
+                                                  rtlpriv->dm.b_cck_inch14));
+                                        break;
+                                }
+                        } else {
+                                if (memcmp((void *)&temp_cck,
+                                           (void *)
+                                           &cckswing_table_ch1ch13[i][2],
+                                           4) == 0) {
+                                        cck_index_old = (u8) i;
+
+                                        RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
+                                                 DBG_LOUD,
+                                                 ("Initial reg0x%x = 0x%lx, "
+                                                  "cck_index=0x%x, ch14 %d\n",
+                                                  RCCK0_TXFILTER2, temp_cck,
+                                                  cck_index_old,
+                                                  rtlpriv->dm.b_cck_inch14));
+                                        break;
+                                }
+                        }
+                }
+
+                if (!rtlpriv->dm.thermalvalue) {
+                        rtlpriv->dm.thermalvalue =
+                            rtlefuse->eeprom_thermalmeter;
+                        rtlpriv->dm.thermalvalue_lck = thermalvalue;
+                        rtlpriv->dm.thermalvalue_iqk = thermalvalue;
+                        for (i = 0; i < rf; i++)
+                                rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
+                        rtlpriv->dm.cck_index = cck_index_old;
+                }
+
+                delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
+                    (thermalvalue - rtlpriv->dm.thermalvalue) :
+                    (rtlpriv->dm.thermalvalue - thermalvalue);
+
+                delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
+                    (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
+                    (rtlpriv->dm.thermalvalue_lck - thermalvalue);
+
+                delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
+                    (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
+                    (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
+
+                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                        ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
+                         "eeprom_thermalmeter 0x%x delta 0x%x "
+                         "delta_lck 0x%x delta_iqk 0x%x\n",
+                         thermalvalue, rtlpriv->dm.thermalvalue,
+                         rtlefuse->eeprom_thermalmeter, delta, delta_lck,
+                         delta_iqk));
+
+                if (delta_lck > 1) {
+                        rtlpriv->dm.thermalvalue_lck = thermalvalue;
+                        rtl92c_phy_lc_calibrate(hw);
+                }
+
+                if (delta > 0 && rtlpriv->dm.txpower_track_control) {
+                        if (thermalvalue > rtlpriv->dm.thermalvalue) {
+                                for (i = 0; i < rf; i++)
+                                        rtlpriv->dm.ofdm_index[i] -= delta;
+                                rtlpriv->dm.cck_index -= delta;
+                        } else {
+                                for (i = 0; i < rf; i++)
+                                        rtlpriv->dm.ofdm_index[i] += delta;
+                                rtlpriv->dm.cck_index += delta;
+                        }
+
+                        if (is2t) {
+                                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                                         ("temp OFDM_A_index=0x%x, "
+                                          "OFDM_B_index=0x%x,"
+                                          "cck_index=0x%x\n",
+                                          rtlpriv->dm.ofdm_index[0],
+                                          rtlpriv->dm.ofdm_index[1],
+                                          rtlpriv->dm.cck_index));
+                        } else {
+                                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                                         ("temp OFDM_A_index=0x%x,"
+                                          "cck_index=0x%x\n",
+                                          rtlpriv->dm.ofdm_index[0],
+                                          rtlpriv->dm.cck_index));
+                        }
+
+                        if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
+                                for (i = 0; i < rf; i++)
+                                        ofdm_index[i] =
+                                            rtlpriv->dm.ofdm_index[i]
+                                            + 1;
+                                cck_index = rtlpriv->dm.cck_index + 1;
+                        } else {
+                                for (i = 0; i < rf; i++)
+                                        ofdm_index[i] =
+                                            rtlpriv->dm.ofdm_index[i];
+                                cck_index = rtlpriv->dm.cck_index;
+                        }
+
+                        for (i = 0; i < rf; i++) {
+                                if (txpwr_level[i] >= 0 &&
+                                    txpwr_level[i] <= 26) {
+                                        if (thermalvalue >
+                                            rtlefuse->eeprom_thermalmeter) {
+                                                if (delta < 5)
+                                                        ofdm_index[i] -= 1;
+
+                                                else
+                                                        ofdm_index[i] -= 2;
+                                        } else if (delta > 5 && thermalvalue <
+                                                   rtlefuse->
+                                                   eeprom_thermalmeter) {
+                                                ofdm_index[i] += 1;
+                                        }
+                                } else if (txpwr_level[i] >= 27 &&
+                                           txpwr_level[i] <= 32
+                                           && thermalvalue >
+                                           rtlefuse->eeprom_thermalmeter) {
+                                        if (delta < 5)
+                                                ofdm_index[i] -= 1;
+
+                                        else
+                                                ofdm_index[i] -= 2;
+                                } else if (txpwr_level[i] >= 32 &&
+                                           txpwr_level[i] <= 38 &&
+                                           thermalvalue >
+                                           rtlefuse->eeprom_thermalmeter
+                                           && delta > 5) {
+                                        ofdm_index[i] -= 1;
+                                }
+                        }
+
+                        if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
+                                if (thermalvalue >
+                                    rtlefuse->eeprom_thermalmeter) {
+                                        if (delta < 5)
+                                                cck_index -= 1;
+
+                                        else
+                                                cck_index -= 2;
+                                } else if (delta > 5 && thermalvalue <
+                                           rtlefuse->eeprom_thermalmeter) {
+                                        cck_index += 1;
+                                }
+                        } else if (txpwr_level[i] >= 27 &&
+                                   txpwr_level[i] <= 32 &&
+                                   thermalvalue >
+                                   rtlefuse->eeprom_thermalmeter) {
+                                if (delta < 5)
+                                        cck_index -= 1;
+
+                                else
+                                        cck_index -= 2;
+                        } else if (txpwr_level[i] >= 32 &&
+                                   txpwr_level[i] <= 38 &&
+                                   thermalvalue > rtlefuse->eeprom_thermalmeter
+                                   && delta > 5) {
+                                cck_index -= 1;
+                        }
+
+                        for (i = 0; i < rf; i++) {
+                                if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
+                                        ofdm_index[i] = OFDM_TABLE_SIZE - 1;
+
+                                else if (ofdm_index[i] < ofdm_min_index)
+                                        ofdm_index[i] = ofdm_min_index;
+                        }
+
+                        if (cck_index > CCK_TABLE_SIZE - 1)
+                                cck_index = CCK_TABLE_SIZE - 1;
+                        else if (cck_index < 0)
+                                cck_index = 0;
+
+                        if (is2t) {
+                                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                                         ("new OFDM_A_index=0x%x, "
+                                          "OFDM_B_index=0x%x,"
+                                          "cck_index=0x%x\n",
+                                          ofdm_index[0], ofdm_index[1],
+                                          cck_index));
+                        } else {
+                                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                                         ("new OFDM_A_index=0x%x,"
+                                          "cck_index=0x%x\n",
+                                          ofdm_index[0], cck_index));
+                        }
+                }
+
+                if (rtlpriv->dm.txpower_track_control && delta != 0) {
+                        ele_d =
+                            (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
+                        val_x = rtlphy->reg_e94;
+                        val_y = rtlphy->reg_e9c;
+
+                        if (val_x != 0) {
+                                if ((val_x & 0x00000200) != 0)
+                                        val_x = val_x | 0xFFFFFC00;
+                                ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
+
+                                if ((val_y & 0x00000200) != 0)
+                                        val_y = val_y | 0xFFFFFC00;
+                                ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
+
+                                value32 = (ele_d << 22) |
+                                    ((ele_c & 0x3F) << 16) | ele_a;
+
+                                rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
+                                              MASKDWORD, value32);
+
+                                value32 = (ele_c & 0x000003C0) >> 6;
+                                rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
+                                              value32);
+
+                                value32 = ((val_x * ele_d) >> 7) & 0x01;
+                                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
+                                              BIT(31), value32);
+
+                                value32 = ((val_y * ele_d) >> 7) & 0x01;
+                                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
+                                              BIT(29), value32);
+                        } else {
+                                rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
+                                              MASKDWORD,
+                                              ofdmswing_table[ofdm_index[0]]);
+
+                                rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
+                                              0x00);
+                                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
+                                              BIT(31) | BIT(29), 0x00);
+                        }
+
+                        if (!rtlpriv->dm.b_cck_inch14) {
+                                rtl_write_byte(rtlpriv, 0xa22,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [0]);
+                                rtl_write_byte(rtlpriv, 0xa23,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [1]);
+                                rtl_write_byte(rtlpriv, 0xa24,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [2]);
+                                rtl_write_byte(rtlpriv, 0xa25,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [3]);
+                                rtl_write_byte(rtlpriv, 0xa26,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [4]);
+                                rtl_write_byte(rtlpriv, 0xa27,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [5]);
+                                rtl_write_byte(rtlpriv, 0xa28,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [6]);
+                                rtl_write_byte(rtlpriv, 0xa29,
+                                               cckswing_table_ch1ch13[cck_index]
+                                               [7]);
+                        } else {
+                                rtl_write_byte(rtlpriv, 0xa22,
+                                               cckswing_table_ch14[cck_index]
+                                               [0]);
+                                rtl_write_byte(rtlpriv, 0xa23,
+                                               cckswing_table_ch14[cck_index]
+                                               [1]);
+                                rtl_write_byte(rtlpriv, 0xa24,
+                                               cckswing_table_ch14[cck_index]
+                                               [2]);
+                                rtl_write_byte(rtlpriv, 0xa25,
+                                               cckswing_table_ch14[cck_index]
+                                               [3]);
+                                rtl_write_byte(rtlpriv, 0xa26,
+                                               cckswing_table_ch14[cck_index]
+                                               [4]);
+                                rtl_write_byte(rtlpriv, 0xa27,
+                                               cckswing_table_ch14[cck_index]
+                                               [5]);
+                                rtl_write_byte(rtlpriv, 0xa28,
+                                               cckswing_table_ch14[cck_index]
+                                               [6]);
+                                rtl_write_byte(rtlpriv, 0xa29,
+                                               cckswing_table_ch14[cck_index]
+                                               [7]);
+                        }
+
+                        if (is2t) {
+                                ele_d = (ofdmswing_table[ofdm_index[1]] &
+                                         0xFFC00000) >> 22;
+
+                                val_x = rtlphy->reg_eb4;
+                                val_y = rtlphy->reg_ebc;
+
+                                if (val_x != 0) {
+                                        if ((val_x & 0x00000200) != 0)
+                                                val_x = val_x | 0xFFFFFC00;
+                                        ele_a = ((val_x * ele_d) >> 8) &
+                                            0x000003FF;
+
+                                        if ((val_y & 0x00000200) != 0)
+                                                val_y = val_y | 0xFFFFFC00;
+                                        ele_c = ((val_y * ele_d) >> 8) &
+                                            0x00003FF;
+
+                                        value32 = (ele_d << 22) |
+                                            ((ele_c & 0x3F) << 16) | ele_a;
+                                        rtl_set_bbreg(hw,
+                                                      ROFDM0_XBTXIQIMBALANCE,
+                                                      MASKDWORD, value32);
+
+                                        value32 = (ele_c & 0x000003C0) >> 6;
+                                        rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
+                                                      MASKH4BITS, value32);
+
+                                        value32 = ((val_x * ele_d) >> 7) & 0x01;
+                                        rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
+                                                      BIT(27), value32);
+
+                                        value32 = ((val_y * ele_d) >> 7) & 0x01;
+                                        rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
+                                                      BIT(25), value32);
+                                } else {
+                                        rtl_set_bbreg(hw,
+                                                      ROFDM0_XBTXIQIMBALANCE,
+                                                      MASKDWORD,
+                                                      ofdmswing_table[ofdm_index
+                                                                      [1]]);
+                                        rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
+                                                      MASKH4BITS, 0x00);
+                                        rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
+                                                      BIT(27) | BIT(25), 0x00);
+                                }
+
+                        }
+                }
+
+                if (delta_iqk > 3) {
+                        rtlpriv->dm.thermalvalue_iqk = thermalvalue;
+                        rtl92c_phy_iq_calibrate(hw, false);
+                }
+
+                if (rtlpriv->dm.txpower_track_control)
+                        rtlpriv->dm.thermalvalue = thermalvalue;
+        }
+
+        RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
+
+}
+
+static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
+                                                struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->dm.btxpower_tracking = true;
+        rtlpriv->dm.btxpower_trackingInit = false;
+
+        RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                 ("pMgntInfo->btxpower_tracking = %d\n",
+                  rtlpriv->dm.btxpower_tracking));
+}
+
+static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
+{
+        rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
+}
+
+static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
+{
+        rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
+}
+
+static void rtl92c_dm_check_txpower_tracking_thermal_meter(
+                                                struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        static u8 tm_trigger;
+
+        if (!rtlpriv->dm.btxpower_tracking)
+                return;
+
+        if (!tm_trigger) {
+                rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
+                              0x60);
+                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                         ("Trigger 92S Thermal Meter!!\n"));
+                tm_trigger = 1;
+                return;
+        } else {
+                RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
+                         ("Schedule TxPowerTracking direct call!!\n"));
+                rtl92c_dm_txpower_tracking_directcall(hw);
+                tm_trigger = 0;
+        }
+}
+
+void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
+{
+        rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
+}
+
+void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rate_adaptive *p_ra = &(rtlpriv->ra);
+
+        p_ra->ratr_state = DM_RATR_STA_INIT;
+        p_ra->pre_ratr_state = DM_RATR_STA_INIT;
+
+        if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
+                rtlpriv->dm.b_useramask = true;
+        else
+                rtlpriv->dm.b_useramask = false;
+
+}
+
+static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rate_adaptive *p_ra = &(rtlpriv->ra);
+        u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
+
+        if (is_hal_stop(rtlhal)) {
+                RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
+                         ("<---- driver is going to unload\n"));
+                return;
+        }
+
+        if (!rtlpriv->dm.b_useramask) {
+                RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
+                        ("<---- driver does not control rate adaptive mask\n"));
+                return;
+        }
+
+        if (mac->link_state == MAC80211_LINKED) {
+
+                switch (p_ra->pre_ratr_state) {
+                case DM_RATR_STA_HIGH:
+                        high_rssithresh_for_ra = 50;
+                        low_rssithresh_for_ra = 20;
+                        break;
+                case DM_RATR_STA_MIDDLE:
+                        high_rssithresh_for_ra = 55;
+                        low_rssithresh_for_ra = 20;
+                        break;
+                case DM_RATR_STA_LOW:
+                        high_rssithresh_for_ra = 50;
+                        low_rssithresh_for_ra = 25;
+                        break;
+                default:
+                        high_rssithresh_for_ra = 50;
+                        low_rssithresh_for_ra = 20;
+                        break;
+                }
+
+                if (rtlpriv->dm.undecorated_smoothed_pwdb >
+                    (long)high_rssithresh_for_ra)
+                        p_ra->ratr_state = DM_RATR_STA_HIGH;
+                else if (rtlpriv->dm.undecorated_smoothed_pwdb >
+                         (long)low_rssithresh_for_ra)
+                        p_ra->ratr_state = DM_RATR_STA_MIDDLE;
+                else
+                        p_ra->ratr_state = DM_RATR_STA_LOW;
+
+                if (p_ra->pre_ratr_state != p_ra->ratr_state) {
+                        RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
+                                 ("RSSI = %ld\n",
+                                  rtlpriv->dm.undecorated_smoothed_pwdb));
+                        RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
+                                 ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
+                        RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
+                                 ("PreState = %d, CurState = %d\n",
+                                  p_ra->pre_ratr_state, p_ra->ratr_state));
+
+                        rtlpriv->cfg->ops->update_rate_mask(hw,
+                                        p_ra->ratr_state);
+
+                        p_ra->pre_ratr_state = p_ra->ratr_state;
+                }
+        }
+}
+
+static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
+{
+        dm_pstable.pre_ccastate = CCA_MAX;
+        dm_pstable.cur_ccasate = CCA_MAX;
+        dm_pstable.pre_rfstate = RF_MAX;
+        dm_pstable.cur_rfstate = RF_MAX;
+        dm_pstable.rssi_val_min = 0;
+}
+
+static void rtl92c_dm_1r_cca(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        if (dm_pstable.rssi_val_min != 0) {
+                if (dm_pstable.pre_ccastate == CCA_2R) {
+                        if (dm_pstable.rssi_val_min >= 35)
+                                dm_pstable.cur_ccasate = CCA_1R;
+                        else
+                                dm_pstable.cur_ccasate = CCA_2R;
+                } else {
+                        if (dm_pstable.rssi_val_min <= 30)
+                                dm_pstable.cur_ccasate = CCA_2R;
+                        else
+                                dm_pstable.cur_ccasate = CCA_1R;
+                }
+        } else {
+                dm_pstable.cur_ccasate = CCA_MAX;
+        }
+
+        if (dm_pstable.pre_ccastate != dm_pstable.cur_ccasate) {
+                if (dm_pstable.cur_ccasate == CCA_1R) {
+                        if (get_rf_type(rtlphy) == RF_2T2R) {
+                                rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
+                                              MASKBYTE0, 0x13);
+                                rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x20);
+                        } else {
+                                rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
+                                              MASKBYTE0, 0x23);
+                                rtl_set_bbreg(hw, 0xe70, 0x7fc00000, 0x10c);
+                        }
+                } else {
+                        rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0,
+                                      0x33);
+                        rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x63);
+                }
+                dm_pstable.pre_ccastate = dm_pstable.cur_ccasate;
+        }
+
+        RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, ("CCAStage = %s\n",
+                                               (dm_pstable.cur_ccasate ==
+                                                0) ? "1RCCA" : "2RCCA"));
+}
+
+void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
+{
+        static u8 initialize;
+        static u32 reg_874, reg_c70, reg_85c, reg_a74;
+
+        if (initialize == 0) {
+                reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
+                                         MASKDWORD) & 0x1CC000) >> 14;
+
+                reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
+                                         MASKDWORD) & BIT(3)) >> 3;
+
+                reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
+                                         MASKDWORD) & 0xFF000000) >> 24;
+
+                reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
+
+                initialize = 1;
+        }
+
+        if (!bforce_in_normal) {
+                if (dm_pstable.rssi_val_min != 0) {
+                        if (dm_pstable.pre_rfstate == RF_NORMAL) {
+                                if (dm_pstable.rssi_val_min >= 30)
+                                        dm_pstable.cur_rfstate = RF_SAVE;
+                                else
+                                        dm_pstable.cur_rfstate = RF_NORMAL;
+                        } else {
+                                if (dm_pstable.rssi_val_min <= 25)
+                                        dm_pstable.cur_rfstate = RF_NORMAL;
+                                else
+                                        dm_pstable.cur_rfstate = RF_SAVE;
+                        }
+                } else {
+                        dm_pstable.cur_rfstate = RF_MAX;
+                }
+        } else {
+                dm_pstable.cur_rfstate = RF_NORMAL;
+        }
+
+        if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
+                if (dm_pstable.cur_rfstate == RF_SAVE) {
+                        rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
+                                      0x1C0000, 0x2);
+                        rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
+                        rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
+                                      0xFF000000, 0x63);
+                        rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
+                                      0xC000, 0x2);
+                        rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
+                        rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
+                        rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
+                } else {
+                        rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
+                                      0x1CC000, reg_874);
+                        rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
+                                      reg_c70);
+                        rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
+                                      reg_85c);
+                        rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
+                        rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
+                }
+
+                dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
+        }
+}
+
+static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (((mac->link_state == MAC80211_NOLINK)) &&
+            (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
+                dm_pstable.rssi_val_min = 0;
+                RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
+                         ("Not connected to any\n"));
+        }
+
+        if (mac->link_state == MAC80211_LINKED) {
+                if (mac->opmode == NL80211_IFTYPE_ADHOC) {
+                        dm_pstable.rssi_val_min =
+                            rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+                        RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
+                                 ("AP Client PWDB = 0x%lx\n",
+                                  dm_pstable.rssi_val_min));
+                } else {
+                        dm_pstable.rssi_val_min =
+                            rtlpriv->dm.undecorated_smoothed_pwdb;
+                        RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
+                                 ("STA Default Port PWDB = 0x%lx\n",
+                                  dm_pstable.rssi_val_min));
+                }
+        } else {
+                dm_pstable.rssi_val_min =
+                    rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
+
+                RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
+                         ("AP Ext Port PWDB = 0x%lx\n",
+                          dm_pstable.rssi_val_min));
+        }
+
+        if (IS_92C_SERIAL(rtlhal->version))
+                rtl92c_dm_1r_cca(hw);
+}
+
+void rtl92c_dm_init(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
+        rtl92c_dm_diginit(hw);
+        rtl92c_dm_init_dynamic_txpower(hw);
+        rtl92c_dm_init_edca_turbo(hw);
+        rtl92c_dm_init_rate_adaptive_mask(hw);
+        rtl92c_dm_initialize_txpower_tracking(hw);
+        rtl92c_dm_init_dynamic_bb_powersaving(hw);
+}
+
+void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        bool b_fw_current_inpsmode = false;
+        bool b_fw_ps_awake = true;
+
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
+                                      (u8 *) (&b_fw_current_inpsmode));
+        rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
+                                      (u8 *) (&b_fw_ps_awake));
+
+        if ((ppsc->rfpwr_state == ERFON) && ((!b_fw_current_inpsmode) &&
+                                             b_fw_ps_awake)
+            && (!ppsc->rfchange_inprogress)) {
+                rtl92c_dm_pwdb_monitor(hw);
+                rtl92c_dm_dig(hw);
+                rtl92c_dm_false_alarm_counter_statistics(hw);
+                rtl92c_dm_dynamic_bb_powersaving(hw);
+                rtl92c_dm_dynamic_txpower(hw);
+                rtl92c_dm_check_txpower_tracking(hw);
+                rtl92c_dm_refresh_rate_adaptive_mask(hw);
+                rtl92c_dm_check_edca_turbo(hw);
+        }
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
new file mode 100644
index 000000000000..463439e4074c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
@@ -0,0 +1,196 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92C_DM_H__
+#define __RTL92C_DM_H__
+
+#define HAL_DM_DIG_DISABLE                      BIT(0)
+#define HAL_DM_HIPWR_DISABLE                    BIT(1)
+
+#define OFDM_TABLE_LENGTH                       37
+#define CCK_TABLE_LENGTH                        33
+
+#define OFDM_TABLE_SIZE                         37
+#define CCK_TABLE_SIZE                          33
+
+#define BW_AUTO_SWITCH_HIGH_LOW                 25
+#define BW_AUTO_SWITCH_LOW_HIGH                 30
+
+#define DM_DIG_THRESH_HIGH                      40
+#define DM_DIG_THRESH_LOW                       35
+
+#define DM_FALSEALARM_THRESH_LOW                400
+#define DM_FALSEALARM_THRESH_HIGH               1000
+
+#define DM_DIG_MAX                              0x3e
+#define DM_DIG_MIN                              0x1e
+
+#define DM_DIG_FA_UPPER                         0x32
+#define DM_DIG_FA_LOWER                         0x20
+#define DM_DIG_FA_TH0                           0x20
+#define DM_DIG_FA_TH1                           0x100
+#define DM_DIG_FA_TH2                           0x200
+
+#define DM_DIG_BACKOFF_MAX                      12
+#define DM_DIG_BACKOFF_MIN                      -4
+#define DM_DIG_BACKOFF_DEFAULT                  10
+
+#define RXPATHSELECTION_SS_TH_lOW               30
+#define RXPATHSELECTION_DIFF_TH                 18
+
+#define DM_RATR_STA_INIT                        0
+#define DM_RATR_STA_HIGH                        1
+#define DM_RATR_STA_MIDDLE                      2
+#define DM_RATR_STA_LOW                         3
+
+#define CTS2SELF_THVAL                          30
+#define REGC38_TH                               20
+
+#define WAIOTTHVal                              25
+
+#define TXHIGHPWRLEVEL_NORMAL                   0
+#define TXHIGHPWRLEVEL_LEVEL1                   1
+#define TXHIGHPWRLEVEL_LEVEL2                   2
+#define TXHIGHPWRLEVEL_BT1                      3
+#define TXHIGHPWRLEVEL_BT2                      4
+
+#define DM_TYPE_BYFW                            0
+#define DM_TYPE_BYDRIVER                        1
+
+#define TX_POWER_NEAR_FIELD_THRESH_LVL2         74
+#define TX_POWER_NEAR_FIELD_THRESH_LVL1         67
+
+struct ps_t {
+        u8 pre_ccastate;
+        u8 cur_ccasate;
+        u8 pre_rfstate;
+        u8 cur_rfstate;
+        long rssi_val_min;
+};
+
+struct dig_t {
+        u8 dig_enable_flag;
+        u8 dig_ext_port_stage;
+        u32 rssi_lowthresh;
+        u32 rssi_highthresh;
+        u32 fa_lowthresh;
+        u32 fa_highthresh;
+        u8 cursta_connectctate;
+        u8 presta_connectstate;
+        u8 curmultista_connectstate;
+        u8 pre_igvalue;
+        u8 cur_igvalue;
+        char backoff_val;
+        char backoff_val_range_max;
+        char backoff_val_range_min;
+        u8 rx_gain_range_max;
+        u8 rx_gain_range_min;
+        u8 rssi_val_min;
+        u8 pre_cck_pd_state;
+        u8 cur_cck_pd_state;
+        u8 pre_cck_fa_state;
+        u8 cur_cck_fa_state;
+        u8 pre_ccastate;
+        u8 cur_ccasate;
+};
+
+struct swat_t {
+        u8 failure_cnt;
+        u8 try_flag;
+        u8 stop_trying;
+        long pre_rssi;
+        long trying_threshold;
+        u8 cur_antenna;
+        u8 pre_antenna;
+};
+
+enum tag_dynamic_init_gain_operation_type_definition {
+        DIG_TYPE_THRESH_HIGH = 0,
+        DIG_TYPE_THRESH_LOW = 1,
+        DIG_TYPE_BACKOFF = 2,
+        DIG_TYPE_RX_GAIN_MIN = 3,
+        DIG_TYPE_RX_GAIN_MAX = 4,
+        DIG_TYPE_ENABLE = 5,
+        DIG_TYPE_DISABLE = 6,
+        DIG_OP_TYPE_MAX
+};
+
+enum tag_cck_packet_detection_threshold_type_definition {
+        CCK_PD_STAGE_LowRssi = 0,
+        CCK_PD_STAGE_HighRssi = 1,
+        CCK_FA_STAGE_Low = 2,
+        CCK_FA_STAGE_High = 3,
+        CCK_PD_STAGE_MAX = 4,
+};
+
+enum dm_1r_cca_e {
+        CCA_1R = 0,
+        CCA_2R = 1,
+        CCA_MAX = 2,
+};
+
+enum dm_rf_e {
+        RF_SAVE = 0,
+        RF_NORMAL = 1,
+        RF_MAX = 2,
+};
+
+enum dm_sw_ant_switch_e {
+        ANS_ANTENNA_B = 1,
+        ANS_ANTENNA_A = 2,
+        ANS_ANTENNA_MAX = 3,
+};
+
+enum dm_dig_ext_port_alg_e {
+        DIG_EXT_PORT_STAGE_0 = 0,
+        DIG_EXT_PORT_STAGE_1 = 1,
+        DIG_EXT_PORT_STAGE_2 = 2,
+        DIG_EXT_PORT_STAGE_3 = 3,
+        DIG_EXT_PORT_STAGE_MAX = 4,
+};
+
+enum dm_dig_connect_e {
+        DIG_STA_DISCONNECT = 0,
+        DIG_STA_CONNECT = 1,
+        DIG_STA_BEFORE_CONNECT = 2,
+        DIG_MULTISTA_DISCONNECT = 3,
+        DIG_MULTISTA_CONNECT = 4,
+        DIG_CONNECT_MAX
+};
+
+extern struct dig_t dm_digtable;
+void rtl92c_dm_init(struct ieee80211_hw *hw);
+void rtl92c_dm_watchdog(struct ieee80211_hw *hw);
+void rtl92c_dm_write_dig(struct ieee80211_hw *hw);
+void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw);
+void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw);
+void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
+void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/fw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/fw.c
new file mode 100644
index 000000000000..11dd22b987e7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/fw.c
@@ -0,0 +1,804 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include <linux/firmware.h>
+#include "../wifi.h"
+#include "../pci.h"
+#include "../base.h"
+#include "reg.h"
+#include "def.h"
+#include "fw.h"
+#include "table.h"
+
+static void _rtl92c_enable_fw_download(struct ieee80211_hw *hw, bool enable)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU) {
+                u32 value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
+                if (enable)
+                        value32 |= MCUFWDL_EN;
+                else
+                        value32 &= ~MCUFWDL_EN;
+                rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
+        } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) {
+                u8 tmp;
+                if (enable) {
+
+                        tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
+                        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1,
+                                       tmp | 0x04);
+
+                        tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
+                        rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp | 0x01);
+
+                        tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
+                        rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
+                } else {
+
+                        tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
+                        rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
+
+                        rtl_write_byte(rtlpriv, REG_MCUFWDL + 1, 0x00);
+                }
+        }
+}
+
+static void _rtl92c_fw_block_write(struct ieee80211_hw *hw,
+                                   const u8 *buffer, u32 size)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 blockSize = sizeof(u32);
+        u8 *bufferPtr = (u8 *) buffer;
+        u32 *pu4BytePtr = (u32 *) buffer;
+        u32 i, offset, blockCount, remainSize;
+
+        blockCount = size / blockSize;
+        remainSize = size % blockSize;
+
+        for (i = 0; i < blockCount; i++) {
+                offset = i * blockSize;
+                rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
+                                *(pu4BytePtr + i));
+        }
+
+        if (remainSize) {
+                offset = blockCount * blockSize;
+                bufferPtr += offset;
+                for (i = 0; i < remainSize; i++) {
+                        rtl_write_byte(rtlpriv, (FW_8192C_START_ADDRESS +
+                                                 offset + i), *(bufferPtr + i));
+                }
+        }
+}
+
+static void _rtl92c_fw_page_write(struct ieee80211_hw *hw,
+                                  u32 page, const u8 *buffer, u32 size)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 value8;
+        u8 u8page = (u8) (page & 0x07);
+
+        value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
+
+        rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
+        _rtl92c_fw_block_write(hw, buffer, size);
+}
+
+static void _rtl92c_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
+{
+        u32 fwlen = *pfwlen;
+        u8 remain = (u8) (fwlen % 4);
+
+        remain = (remain == 0) ? 0 : (4 - remain);
+
+        while (remain > 0) {
+                pfwbuf[fwlen] = 0;
+                fwlen++;
+                remain--;
+        }
+
+        *pfwlen = fwlen;
+}
+
+static void _rtl92c_write_fw(struct ieee80211_hw *hw,
+                             enum version_8192c version, u8 *buffer, u32 size)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        bool is_version_b;
+        u8 *bufferPtr = (u8 *) buffer;
+
+        RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size));
+
+        is_version_b = IS_CHIP_VER_B(version);
+        if (is_version_b) {
+                u32 pageNums, remainSize;
+                u32 page, offset;
+
+                if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
+                        _rtl92c_fill_dummy(bufferPtr, &size);
+
+                pageNums = size / FW_8192C_PAGE_SIZE;
+                remainSize = size % FW_8192C_PAGE_SIZE;
+
+                if (pageNums > 4) {
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("Page numbers should not greater then 4\n"));
+                }
+
+                for (page = 0; page < pageNums; page++) {
+                        offset = page * FW_8192C_PAGE_SIZE;
+                        _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
+                                              FW_8192C_PAGE_SIZE);
+                }
+
+                if (remainSize) {
+                        offset = pageNums * FW_8192C_PAGE_SIZE;
+                        page = pageNums;
+                        _rtl92c_fw_page_write(hw, page, (bufferPtr + offset),
+                                              remainSize);
+                }
+        } else {
+                _rtl92c_fw_block_write(hw, buffer, size);
+        }
+}
+
+static int _rtl92c_fw_free_to_go(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        int err = -EIO;
+        u32 counter = 0;
+        u32 value32;
+
+        do {
+                value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
+        } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
+                 (!(value32 & FWDL_ChkSum_rpt)));
+
+        if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("chksum report faill ! REG_MCUFWDL:0x%08x .\n",
+                          value32));
+                goto exit;
+        }
+
+        RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
+                 ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32));
+
+        value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
+        value32 |= MCUFWDL_RDY;
+        value32 &= ~WINTINI_RDY;
+        rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
+
+        counter = 0;
+
+        do {
+                value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
+                if (value32 & WINTINI_RDY) {
+                        RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
+                                 ("Polling FW ready success!!"
+                                 " REG_MCUFWDL:0x%08x .\n",
+                                 value32));
+                        err = 0;
+                        goto exit;
+                }
+
+                mdelay(FW_8192C_POLLING_DELAY);
+
+        } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
+
+        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                 ("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", value32));
+
+exit:
+        return err;
+}
+
+int rtl92c_download_fw(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl92c_firmware_header *pfwheader;
+        u8 *pfwdata;
+        u32 fwsize;
+        int err;
+        enum version_8192c version = rtlhal->version;
+
+        const struct firmware *firmware = NULL;
+
+        err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
+                               rtlpriv->io.dev);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Failed to request firmware!\n"));
+                return 1;
+        }
+
+        if (firmware->size > 0x4000) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Firmware is too big!\n"));
+                release_firmware(firmware);
+                return 1;
+        }
+
+        memcpy(rtlhal->pfirmware, firmware->data, firmware->size);
+        fwsize = firmware->size;
+        release_firmware(firmware);
+
+        pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
+        pfwdata = (u8 *) rtlhal->pfirmware;
+
+        if (IS_FW_HEADER_EXIST(pfwheader)) {
+                RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
+                         ("Firmware Version(%d), Signature(%#x),Size(%d)\n",
+                          pfwheader->version, pfwheader->signature,
+                          (uint)sizeof(struct rtl92c_firmware_header)));
+
+                pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
+                fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
+        }
+
+        _rtl92c_enable_fw_download(hw, true);
+        _rtl92c_write_fw(hw, version, pfwdata, fwsize);
+        _rtl92c_enable_fw_download(hw, false);
+
+        err = _rtl92c_fw_free_to_go(hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Firmware is not ready to run!\n"));
+        } else {
+                RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
+                         ("Firmware is ready to run!\n"));
+        }
+
+        return 0;
+}
+
+static bool _rtl92c_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 val_hmetfr, val_mcutst_1;
+        bool result = false;
+
+        val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
+        val_mcutst_1 = rtl_read_byte(rtlpriv, (REG_MCUTST_1 + boxnum));
+
+        if (((val_hmetfr >> boxnum) & BIT(0)) == 0 && val_mcutst_1 == 0)
+                result = true;
+        return result;
+}
+
+static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
+                              u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u8 boxnum;
+        u16 box_reg, box_extreg;
+        u8 u1b_tmp;
+        bool isfw_read = false;
+        u8 buf_index;
+        bool bwrite_sucess = false;
+        u8 wait_h2c_limmit = 100;
+        u8 wait_writeh2c_limmit = 100;
+        u8 boxcontent[4], boxextcontent[2];
+        u32 h2c_waitcounter = 0;
+        unsigned long flag;
+        u8 idx;
+
+        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("come in\n"));
+
+        while (true) {
+                spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
+                if (rtlhal->b_h2c_setinprogress) {
+                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                                 ("H2C set in progress! Wait to set.."
+                                  "element_id(%d).\n", element_id));
+
+                        while (rtlhal->b_h2c_setinprogress) {
+                                spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
+                                                       flag);
+                                h2c_waitcounter++;
+                                RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                                         ("Wait 100 us (%d times)...\n",
+                                          h2c_waitcounter));
+                                udelay(100);
+
+                                if (h2c_waitcounter > 1000)
+                                        return;
+                                spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
+                                                  flag);
+                        }
+                        spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
+                } else {
+                        rtlhal->b_h2c_setinprogress = true;
+                        spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
+                        break;
+                }
+        }
+
+        while (!bwrite_sucess) {
+                wait_writeh2c_limmit--;
+                if (wait_writeh2c_limmit == 0) {
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("Write H2C fail because no trigger "
+                                  "for FW INT!\n"));
+                        break;
+                }
+
+                boxnum = rtlhal->last_hmeboxnum;
+                switch (boxnum) {
+                case 0:
+                        box_reg = REG_HMEBOX_0;
+                        box_extreg = REG_HMEBOX_EXT_0;
+                        break;
+                case 1:
+                        box_reg = REG_HMEBOX_1;
+                        box_extreg = REG_HMEBOX_EXT_1;
+                        break;
+                case 2:
+                        box_reg = REG_HMEBOX_2;
+                        box_extreg = REG_HMEBOX_EXT_2;
+                        break;
+                case 3:
+                        box_reg = REG_HMEBOX_3;
+                        box_extreg = REG_HMEBOX_EXT_3;
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("switch case not process\n"));
+                        break;
+                }
+
+                isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
+                while (!isfw_read) {
+
+                        wait_h2c_limmit--;
+                        if (wait_h2c_limmit == 0) {
+                                RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                                         ("Wating too long for FW read "
+                                          "clear HMEBox(%d)!\n", boxnum));
+                                break;
+                        }
+
+                        udelay(10);
+
+                        isfw_read = _rtl92c_check_fw_read_last_h2c(hw, boxnum);
+                        u1b_tmp = rtl_read_byte(rtlpriv, 0x1BF);
+                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                                 ("Wating for FW read clear HMEBox(%d)!!! "
+                                  "0x1BF = %2x\n", boxnum, u1b_tmp));
+                }
+
+                if (!isfw_read) {
+                        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                                 ("Write H2C register BOX[%d] fail!!!!! "
+                                  "Fw do not read.\n", boxnum));
+                        break;
+                }
+
+                memset(boxcontent, 0, sizeof(boxcontent));
+                memset(boxextcontent, 0, sizeof(boxextcontent));
+                boxcontent[0] = element_id;
+                RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                         ("Write element_id box_reg(%4x) = %2x\n",
+                          box_reg, element_id));
+
+                switch (cmd_len) {
+                case 1:
+                        boxcontent[0] &= ~(BIT(7));
+                        memcpy((u8 *) (boxcontent) + 1,
+                               p_cmdbuffer + buf_index, 1);
+
+                        for (idx = 0; idx < 4; idx++) {
+                                rtl_write_byte(rtlpriv, box_reg + idx,
+                                               boxcontent[idx]);
+                        }
+                        break;
+                case 2:
+                        boxcontent[0] &= ~(BIT(7));
+                        memcpy((u8 *) (boxcontent) + 1,
+                               p_cmdbuffer + buf_index, 2);
+
+                        for (idx = 0; idx < 4; idx++) {
+                                rtl_write_byte(rtlpriv, box_reg + idx,
+                                               boxcontent[idx]);
+                        }
+                        break;
+                case 3:
+                        boxcontent[0] &= ~(BIT(7));
+                        memcpy((u8 *) (boxcontent) + 1,
+                               p_cmdbuffer + buf_index, 3);
+
+                        for (idx = 0; idx < 4; idx++) {
+                                rtl_write_byte(rtlpriv, box_reg + idx,
+                                               boxcontent[idx]);
+                        }
+                        break;
+                case 4:
+                        boxcontent[0] |= (BIT(7));
+                        memcpy((u8 *) (boxextcontent),
+                               p_cmdbuffer + buf_index, 2);
+                        memcpy((u8 *) (boxcontent) + 1,
+                               p_cmdbuffer + buf_index + 2, 2);
+
+                        for (idx = 0; idx < 2; idx++) {
+                                rtl_write_byte(rtlpriv, box_extreg + idx,
+                                               boxextcontent[idx]);
+                        }
+
+                        for (idx = 0; idx < 4; idx++) {
+                                rtl_write_byte(rtlpriv, box_reg + idx,
+                                               boxcontent[idx]);
+                        }
+                        break;
+                case 5:
+                        boxcontent[0] |= (BIT(7));
+                        memcpy((u8 *) (boxextcontent),
+                               p_cmdbuffer + buf_index, 2);
+                        memcpy((u8 *) (boxcontent) + 1,
+                               p_cmdbuffer + buf_index + 2, 3);
+
+                        for (idx = 0; idx < 2; idx++) {
+                                rtl_write_byte(rtlpriv, box_extreg + idx,
+                                               boxextcontent[idx]);
+                        }
+
+                        for (idx = 0; idx < 4; idx++) {
+                                rtl_write_byte(rtlpriv, box_reg + idx,
+                                               boxcontent[idx]);
+                        }
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("switch case not process\n"));
+                        break;
+                }
+
+                bwrite_sucess = true;
+
+                rtlhal->last_hmeboxnum = boxnum + 1;
+                if (rtlhal->last_hmeboxnum == 4)
+                        rtlhal->last_hmeboxnum = 0;
+
+                RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
+                         ("pHalData->last_hmeboxnum  = %d\n",
+                          rtlhal->last_hmeboxnum));
+        }
+
+        spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
+        rtlhal->b_h2c_setinprogress = false;
+        spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
+
+        RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n"));
+}
+
+void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
+                         u8 element_id, u32 cmd_len, u8 *p_cmdbuffer)
+{
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u32 tmp_cmdbuf[2];
+
+        if (rtlhal->bfw_ready == false) {
+                RT_ASSERT(false, ("return H2C cmd because of Fw "
+                                  "download fail!!!\n"));
+                return;
+        }
+
+        memset(tmp_cmdbuf, 0, 8);
+        memcpy(tmp_cmdbuf, p_cmdbuffer, cmd_len);
+        _rtl92c_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
+
+        return;
+}
+
+void rtl92c_firmware_selfreset(struct ieee80211_hw *hw)
+{
+        u8 u1b_tmp;
+        u8 delay = 100;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtl_write_byte(rtlpriv, REG_HMETFR + 3, 0x20);
+        u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
+
+        while (u1b_tmp & BIT(2)) {
+                delay--;
+                if (delay == 0) {
+                        RT_ASSERT(false, ("8051 reset fail.\n"));
+                        break;
+                }
+                udelay(50);
+                u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
+        }
+}
+
+void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 u1_h2c_set_pwrmode[3] = {0};
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("FW LPS mode = %d\n", mode));
+
+        SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, mode);
+        SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode, 1);
+        SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1_h2c_set_pwrmode,
+                                              ppsc->reg_max_lps_awakeintvl);
+
+        RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
+                      "rtl92c_set_fw_rsvdpagepkt(): u1_h2c_set_pwrmode\n",
+                      u1_h2c_set_pwrmode, 3);
+        rtl92c_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
+
+}
+
+static bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
+                                    struct sk_buff *skb)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl8192_tx_ring *ring;
+        struct rtl_tx_desc *pdesc;
+        u8 own;
+        unsigned long flags;
+        struct sk_buff *pskb = NULL;
+
+        ring = &rtlpci->tx_ring[BEACON_QUEUE];
+
+        pskb = __skb_dequeue(&ring->queue);
+        if (pskb)
+                kfree_skb(pskb);
+
+        spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
+
+        pdesc = &ring->desc[0];
+        own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
+
+        rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
+
+        __skb_queue_tail(&ring->queue, skb);
+
+        spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
+
+        rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
+
+        return true;
+}
+
+#define BEACON_PG               0 /*->1*/
+#define PSPOLL_PG               2
+#define NULL_PG                 3
+#define PROBERSP_PG             4 /*->5*/
+
+#define TOTAL_RESERVED_PKT_LEN  768
+
+static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
+        /* page 0 beacon */
+        0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
+        0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
+        0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x50, 0x08,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
+        0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
+        0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
+        0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
+        0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
+        0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
+        0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
+        0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+        /* page 1 beacon */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x10, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x10, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+        /* page 2  ps-poll */
+        0xA4, 0x10, 0x01, 0xC0, 0x00, 0x40, 0x10, 0x10,
+        0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x18, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+        0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+        /* page 3  null */
+        0x48, 0x01, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
+        0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
+        0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x72, 0x00, 0x20, 0x8C, 0x00, 0x12, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
+        0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+        /* page 4  probe_resp */
+        0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
+        0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
+        0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
+        0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
+        0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
+        0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
+        0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
+        0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
+        0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
+        0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
+        0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
+        0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+        /* page 5  probe_resp */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct sk_buff *skb = NULL;
+
+        u32 totalpacketlen;
+        bool rtstatus;
+        u8 u1RsvdPageLoc[3] = {0};
+        bool b_dlok = false;
+
+        u8 *beacon;
+        u8 *p_pspoll;
+        u8 *nullfunc;
+        u8 *p_probersp;
+        /*---------------------------------------------------------
+                                (1) beacon
+        ---------------------------------------------------------*/
+        beacon = &reserved_page_packet[BEACON_PG * 128];
+        SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
+        SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
+
+        /*-------------------------------------------------------
+                                (2) ps-poll
+        --------------------------------------------------------*/
+        p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
+        SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
+        SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
+        SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
+
+        SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1RsvdPageLoc, PSPOLL_PG);
+
+        /*--------------------------------------------------------
+                                (3) null data
+        ---------------------------------------------------------*/
+        nullfunc = &reserved_page_packet[NULL_PG * 128];
+        SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
+        SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
+        SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
+
+        SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1RsvdPageLoc, NULL_PG);
+
+        /*---------------------------------------------------------
+                                (4) probe response
+        ----------------------------------------------------------*/
+        p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
+        SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
+        SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
+        SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
+
+        SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1RsvdPageLoc, PROBERSP_PG);
+
+        totalpacketlen = TOTAL_RESERVED_PKT_LEN;
+
+        RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
+                      "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
+                      &reserved_page_packet[0], totalpacketlen);
+        RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
+                      "rtl92c_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
+                      u1RsvdPageLoc, 3);
+
+
+        skb = dev_alloc_skb(totalpacketlen);
+        memcpy((u8 *) skb_put(skb, totalpacketlen),
+               &reserved_page_packet, totalpacketlen);
+
+        rtstatus = _rtl92c_cmd_send_packet(hw, skb);
+
+        if (rtstatus)
+                b_dlok = true;
+
+        if (b_dlok) {
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
+                         ("Set RSVD page location to Fw.\n"));
+                RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
+                                "H2C_RSVDPAGE:\n",
+                                u1RsvdPageLoc, 3);
+                rtl92c_fill_h2c_cmd(hw, H2C_RSVDPAGE,
+                                    sizeof(u1RsvdPageLoc), u1RsvdPageLoc);
+        } else
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
+}
+
+void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
+{
+        u8 u1_joinbssrpt_parm[1] = {0};
+
+        SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1_joinbssrpt_parm, mstatus);
+
+        rtl92c_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/fw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/fw.h
new file mode 100644
index 000000000000..3db33bd14666
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/fw.h
@@ -0,0 +1,98 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92C__FW__H__
+#define __RTL92C__FW__H__
+
+#define FW_8192C_SIZE                           0x3000
+#define FW_8192C_START_ADDRESS                  0x1000
+#define FW_8192C_END_ADDRESS                    0x3FFF
+#define FW_8192C_PAGE_SIZE                      4096
+#define FW_8192C_POLLING_DELAY                  5
+#define FW_8192C_POLLING_TIMEOUT_COUNT          100
+
+#define IS_FW_HEADER_EXIST(_pfwhdr)     \
+        ((_pfwhdr->signature&0xFFF0) == 0x92C0 ||\
+        (_pfwhdr->signature&0xFFF0) == 0x88C0)
+
+struct rtl92c_firmware_header {
+        u16 signature;
+        u8 category;
+        u8 function;
+        u16 version;
+        u8 subversion;
+        u8 rsvd1;
+        u8 month;
+        u8 date;
+        u8 hour;
+        u8 minute;
+        u16 ramcodeSize;
+        u16 rsvd2;
+        u32 svnindex;
+        u32 rsvd3;
+        u32 rsvd4;
+        u32 rsvd5;
+};
+
+enum rtl8192c_h2c_cmd {
+        H2C_AP_OFFLOAD = 0,
+        H2C_SETPWRMODE = 1,
+        H2C_JOINBSSRPT = 2,
+        H2C_RSVDPAGE = 3,
+        H2C_RSSI_REPORT = 5,
+        H2C_RA_MASK = 6,
+        MAX_H2CCMD
+};
+
+#define pagenum_128(_len)       (u32)(((_len)>>7) + ((_len)&0x7F ? 1 : 0))
+
+#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val)                  \
+        SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
+#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val)              \
+        SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
+#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \
+        SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
+#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val)             \
+        SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
+#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val)             \
+        SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
+#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val)                \
+        SET_BITS_TO_LE_1BYTE((__ph2ccmd)+1, 0, 8, __val)
+#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val)             \
+        SET_BITS_TO_LE_1BYTE((__ph2ccmd)+2, 0, 8, __val)
+
+int rtl92c_download_fw(struct ieee80211_hw *hw);
+void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
+                         u32 cmd_len, u8 *p_cmdbuffer);
+void rtl92c_firmware_selfreset(struct ieee80211_hw *hw);
+void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
+void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
+void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
new file mode 100644
index 000000000000..1c41a0c93506
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
@@ -0,0 +1,2162 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../wifi.h"
+#include "../efuse.h"
+#include "../base.h"
+#include "../cam.h"
+#include "../ps.h"
+#include "../pci.h"
+#include "reg.h"
+#include "def.h"
+#include "phy.h"
+#include "dm.h"
+#include "fw.h"
+#include "led.h"
+#include "hw.h"
+
+#define LLT_CONFIG      5
+
+static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
+                                      u8 set_bits, u8 clear_bits)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpci->reg_bcn_ctrl_val |= set_bits;
+        rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
+
+        rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
+}
+
+static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 tmp1byte;
+
+        tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
+        rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
+        rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
+        tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
+        tmp1byte &= ~(BIT(0));
+        rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
+}
+
+static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 tmp1byte;
+
+        tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
+        rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
+        rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
+        tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
+        tmp1byte |= BIT(0);
+        rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
+}
+
+static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
+{
+        _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
+}
+
+static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
+{
+        _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
+}
+
+void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        switch (variable) {
+        case HW_VAR_RCR:
+                *((u32 *) (val)) = rtlpci->receive_config;
+                break;
+        case HW_VAR_RF_STATE:
+                *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
+                break;
+        case HW_VAR_FWLPS_RF_ON:{
+                        enum rf_pwrstate rfState;
+                        u32 val_rcr;
+
+                        rtlpriv->cfg->ops->get_hw_reg(hw,
+                                                      HW_VAR_RF_STATE,
+                                                      (u8 *) (&rfState));
+                        if (rfState == ERFOFF) {
+                                *((bool *) (val)) = true;
+                        } else {
+                                val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
+                                val_rcr &= 0x00070000;
+                                if (val_rcr)
+                                        *((bool *) (val)) = false;
+                                else
+                                        *((bool *) (val)) = true;
+                        }
+                        break;
+                }
+        case HW_VAR_FW_PSMODE_STATUS:
+                *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
+                break;
+        case HW_VAR_CORRECT_TSF:{
+                u64 tsf;
+                u32 *ptsf_low = (u32 *)&tsf;
+                u32 *ptsf_high = ((u32 *)&tsf) + 1;
+
+                *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
+                *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
+
+                *((u64 *) (val)) = tsf;
+
+                break;
+                }
+        case HW_VAR_MGT_FILTER:
+                *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
+                break;
+        case HW_VAR_CTRL_FILTER:
+                *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
+                break;
+        case HW_VAR_DATA_FILTER:
+                *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+}
+
+void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        u8 idx;
+
+        switch (variable) {
+        case HW_VAR_ETHER_ADDR:{
+                        for (idx = 0; idx < ETH_ALEN; idx++) {
+                                rtl_write_byte(rtlpriv, (REG_MACID + idx),
+                                               val[idx]);
+                        }
+                        break;
+                }
+        case HW_VAR_BASIC_RATE:{
+                        u16 b_rate_cfg = ((u16 *) val)[0];
+                        u8 rate_index = 0;
+                        b_rate_cfg = b_rate_cfg & 0x15f;
+                        b_rate_cfg |= 0x01;
+                        rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
+                        rtl_write_byte(rtlpriv, REG_RRSR + 1,
+                                       (b_rate_cfg >> 8)&0xff);
+                        while (b_rate_cfg > 0x1) {
+                                b_rate_cfg = (b_rate_cfg >> 1);
+                                rate_index++;
+                        }
+                        rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
+                                       rate_index);
+                        break;
+                }
+        case HW_VAR_BSSID:{
+                        for (idx = 0; idx < ETH_ALEN; idx++) {
+                                rtl_write_byte(rtlpriv, (REG_BSSID + idx),
+                                               val[idx]);
+                        }
+                        break;
+                }
+        case HW_VAR_SIFS:{
+                        rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
+                        rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
+
+                        rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
+                        rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
+
+                        if (!mac->ht_enable)
+                                rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
+                                               0x0e0e);
+                        else
+                                rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
+                                               *((u16 *) val));
+                        break;
+                }
+        case HW_VAR_SLOT_TIME:{
+                        u8 e_aci;
+
+                        RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
+                                 ("HW_VAR_SLOT_TIME %x\n", val[0]));
+
+                        rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
+
+                        for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                              HW_VAR_AC_PARAM,
+                                                              (u8 *) (&e_aci));
+                        }
+                        break;
+                }
+        case HW_VAR_ACK_PREAMBLE:{
+                        u8 reg_tmp;
+                        u8 short_preamble = (bool) (*(u8 *) val);
+                        reg_tmp = (mac->cur_40_prime_sc) << 5;
+                        if (short_preamble)
+                                reg_tmp |= 0x80;
+
+                        rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
+                        break;
+                }
+        case HW_VAR_AMPDU_MIN_SPACE:{
+                        u8 min_spacing_to_set;
+                        u8 sec_min_space;
+
+                        min_spacing_to_set = *((u8 *) val);
+                        if (min_spacing_to_set <= 7) {
+                                sec_min_space = 0;
+
+                                if (min_spacing_to_set < sec_min_space)
+                                        min_spacing_to_set = sec_min_space;
+
+                                mac->min_space_cfg = ((mac->min_space_cfg &
+                                                       0xf8) |
+                                                      min_spacing_to_set);
+
+                                *val = min_spacing_to_set;
+
+                                RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
+                                         ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
+                                          mac->min_space_cfg));
+
+                                rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
+                                               mac->min_space_cfg);
+                        }
+                        break;
+                }
+        case HW_VAR_SHORTGI_DENSITY:{
+                        u8 density_to_set;
+
+                        density_to_set = *((u8 *) val);
+                        mac->min_space_cfg |= (density_to_set << 3);
+
+                        RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
+                                 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
+                                  mac->min_space_cfg));
+
+                        rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
+                                       mac->min_space_cfg);
+
+                        break;
+                }
+        case HW_VAR_AMPDU_FACTOR:{
+                        u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
+
+                        u8 factor_toset;
+                        u8 *p_regtoset = NULL;
+                        u8 index = 0;
+
+                        p_regtoset = regtoset_normal;
+
+                        factor_toset = *((u8 *) val);
+                        if (factor_toset <= 3) {
+                                factor_toset = (1 << (factor_toset + 2));
+                                if (factor_toset > 0xf)
+                                        factor_toset = 0xf;
+
+                                for (index = 0; index < 4; index++) {
+                                        if ((p_regtoset[index] & 0xf0) >
+                                            (factor_toset << 4))
+                                                p_regtoset[index] =
+                                                    (p_regtoset[index] & 0x0f) |
+                                                    (factor_toset << 4);
+
+                                        if ((p_regtoset[index] & 0x0f) >
+                                            factor_toset)
+                                                p_regtoset[index] =
+                                                    (p_regtoset[index] & 0xf0) |
+                                                    (factor_toset);
+
+                                        rtl_write_byte(rtlpriv,
+                                                       (REG_AGGLEN_LMT + index),
+                                                       p_regtoset[index]);
+
+                                }
+
+                                RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
+                                         ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
+                                          factor_toset));
+                        }
+                        break;
+                }
+        case HW_VAR_AC_PARAM:{
+                        u8 e_aci = *((u8 *) val);
+                        u32 u4b_ac_param = 0;
+
+                        u4b_ac_param |= (u32) mac->ac[e_aci].aifs;
+                        u4b_ac_param |= ((u32) mac->ac[e_aci].cw_min
+                                         & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
+                        u4b_ac_param |= ((u32) mac->ac[e_aci].cw_max &
+                                         0xF) << AC_PARAM_ECW_MAX_OFFSET;
+                        u4b_ac_param |= (u32) mac->ac[e_aci].tx_op
+                            << AC_PARAM_TXOP_LIMIT_OFFSET;
+
+                        RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
+                                 ("queue:%x, ac_param:%x\n", e_aci,
+                                  u4b_ac_param));
+
+                        switch (e_aci) {
+                        case AC1_BK:
+                                rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
+                                                u4b_ac_param);
+                                break;
+                        case AC0_BE:
+                                rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
+                                                u4b_ac_param);
+                                break;
+                        case AC2_VI:
+                                rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
+                                                u4b_ac_param);
+                                break;
+                        case AC3_VO:
+                                rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
+                                                u4b_ac_param);
+                                break;
+                        default:
+                                RT_ASSERT(false,
+                                  ("SetHwReg8185(): invalid aci: %d !\n",
+                                   e_aci));
+                                break;
+                        }
+
+                        if (rtlpci->acm_method != eAcmWay2_SW)
+                                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                              HW_VAR_ACM_CTRL,
+                                                              (u8 *) (&e_aci));
+                        break;
+                }
+        case HW_VAR_ACM_CTRL:{
+                        u8 e_aci = *((u8 *) val);
+                        union aci_aifsn *p_aci_aifsn =
+                            (union aci_aifsn *)(&(mac->ac[0].aifs));
+                        u8 acm = p_aci_aifsn->f.acm;
+                        u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
+
+                        acm_ctrl =
+                            acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
+
+                        if (acm) {
+                                switch (e_aci) {
+                                case AC0_BE:
+                                        acm_ctrl |= AcmHw_BeqEn;
+                                        break;
+                                case AC2_VI:
+                                        acm_ctrl |= AcmHw_ViqEn;
+                                        break;
+                                case AC3_VO:
+                                        acm_ctrl |= AcmHw_VoqEn;
+                                        break;
+                                default:
+                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                                 ("HW_VAR_ACM_CTRL acm set "
+                                                  "failed: eACI is %d\n", acm));
+                                        break;
+                                }
+                        } else {
+                                switch (e_aci) {
+                                case AC0_BE:
+                                        acm_ctrl &= (~AcmHw_BeqEn);
+                                        break;
+                                case AC2_VI:
+                                        acm_ctrl &= (~AcmHw_ViqEn);
+                                        break;
+                                case AC3_VO:
+                                        acm_ctrl &= (~AcmHw_BeqEn);
+                                        break;
+                                default:
+                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                                 ("switch case not process\n"));
+                                        break;
+                                }
+                        }
+
+                        RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
+                                 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
+                                  "Write 0x%X\n", acm_ctrl));
+                        rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
+                        break;
+                }
+        case HW_VAR_RCR:{
+                        rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
+                        rtlpci->receive_config = ((u32 *) (val))[0];
+                        break;
+                }
+        case HW_VAR_RETRY_LIMIT:{
+                        u8 retry_limit = ((u8 *) (val))[0];
+
+                        rtl_write_word(rtlpriv, REG_RL,
+                                       retry_limit << RETRY_LIMIT_SHORT_SHIFT |
+                                       retry_limit << RETRY_LIMIT_LONG_SHIFT);
+                        break;
+                }
+        case HW_VAR_DUAL_TSF_RST:
+                rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
+                break;
+        case HW_VAR_EFUSE_BYTES:
+                rtlefuse->efuse_usedbytes = *((u16 *) val);
+                break;
+        case HW_VAR_EFUSE_USAGE:
+                rtlefuse->efuse_usedpercentage = *((u8 *) val);
+                break;
+        case HW_VAR_IO_CMD:
+                rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
+                break;
+        case HW_VAR_WPA_CONFIG:
+                rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
+                break;
+        case HW_VAR_SET_RPWM:{
+                        u8 rpwm_val;
+
+                        rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
+                        udelay(1);
+
+                        if (rpwm_val & BIT(7)) {
+                                rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
+                                               (*(u8 *) val));
+                        } else {
+                                rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
+                                               ((*(u8 *) val) | BIT(7)));
+                        }
+
+                        break;
+                }
+        case HW_VAR_H2C_FW_PWRMODE:{
+                        u8 psmode = (*(u8 *) val);
+
+                        if ((psmode != FW_PS_ACTIVE_MODE) &&
+                            (!IS_92C_SERIAL(rtlhal->version))) {
+                                rtl92c_dm_rf_saving(hw, true);
+                        }
+
+                        rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
+                        break;
+                }
+        case HW_VAR_FW_PSMODE_STATUS:
+                ppsc->b_fw_current_inpsmode = *((bool *) val);
+                break;
+        case HW_VAR_H2C_FW_JOINBSSRPT:{
+                        u8 mstatus = (*(u8 *) val);
+                        u8 tmp_regcr, tmp_reg422;
+                        bool b_recover = false;
+
+                        if (mstatus == RT_MEDIA_CONNECT) {
+                                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
+                                                              NULL);
+
+                                tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
+                                rtl_write_byte(rtlpriv, REG_CR + 1,
+                                               (tmp_regcr | BIT(0)));
+
+                                _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
+                                _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
+
+                                tmp_reg422 =
+                                    rtl_read_byte(rtlpriv,
+                                                  REG_FWHW_TXQ_CTRL + 2);
+                                if (tmp_reg422 & BIT(6))
+                                        b_recover = true;
+                                rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
+                                               tmp_reg422 & (~BIT(6)));
+
+                                rtl92c_set_fw_rsvdpagepkt(hw, 0);
+
+                                _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
+                                _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
+
+                                if (b_recover) {
+                                        rtl_write_byte(rtlpriv,
+                                                       REG_FWHW_TXQ_CTRL + 2,
+                                                       tmp_reg422);
+                                }
+
+                                rtl_write_byte(rtlpriv, REG_CR + 1,
+                                               (tmp_regcr & ~(BIT(0))));
+                        }
+                        rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
+
+                        break;
+                }
+        case HW_VAR_AID:{
+                        u16 u2btmp;
+                        u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
+                        u2btmp &= 0xC000;
+                        rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
+                                                mac->assoc_id));
+
+                        break;
+                }
+        case HW_VAR_CORRECT_TSF:{
+                        u8 btype_ibss = ((u8 *) (val))[0];
+
+                        /*btype_ibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ?
+                                        1 : 0;*/
+
+                        if (btype_ibss == true)
+                                _rtl92ce_stop_tx_beacon(hw);
+
+                        _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
+
+                        rtl_write_dword(rtlpriv, REG_TSFTR,
+                                        (u32) (mac->tsf & 0xffffffff));
+                        rtl_write_dword(rtlpriv, REG_TSFTR + 4,
+                                        (u32) ((mac->tsf >> 32)&0xffffffff));
+
+                        _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
+
+                        if (btype_ibss == true)
+                                _rtl92ce_resume_tx_beacon(hw);
+
+                        break;
+
+                }
+        case HW_VAR_MGT_FILTER:
+                rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *) val);
+                break;
+        case HW_VAR_CTRL_FILTER:
+                rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *) val);
+                break;
+        case HW_VAR_DATA_FILTER:
+                rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *) val);
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
+                                                        "not process\n"));
+                break;
+        }
+}
+
+static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        bool status = true;
+        long count = 0;
+        u32 value = _LLT_INIT_ADDR(address) |
+            _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
+
+        rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
+
+        do {
+                value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
+                if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
+                        break;
+
+                if (count > POLLING_LLT_THRESHOLD) {
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("Failed to polling write LLT done at "
+                                  "address %d!\n", address));
+                        status = false;
+                        break;
+                }
+        } while (++count);
+
+        return status;
+}
+
+static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        unsigned short i;
+        u8 txpktbuf_bndy;
+        u8 maxPage;
+        bool status;
+
+#if LLT_CONFIG == 1
+        maxPage = 255;
+        txpktbuf_bndy = 252;
+#elif LLT_CONFIG == 2
+        maxPage = 127;
+        txpktbuf_bndy = 124;
+#elif LLT_CONFIG == 3
+        maxPage = 255;
+        txpktbuf_bndy = 174;
+#elif LLT_CONFIG == 4
+        maxPage = 255;
+        txpktbuf_bndy = 246;
+#elif LLT_CONFIG == 5
+        maxPage = 255;
+        txpktbuf_bndy = 246;
+#endif
+
+#if LLT_CONFIG == 1
+        rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
+        rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
+#elif LLT_CONFIG == 2
+        rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
+#elif LLT_CONFIG == 3
+        rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
+#elif LLT_CONFIG == 4
+        rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
+#elif LLT_CONFIG == 5
+        rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
+
+        rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
+#endif
+
+        rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
+        rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
+
+        rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
+        rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
+
+        rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
+        rtl_write_byte(rtlpriv, REG_PBP, 0x11);
+        rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
+
+        for (i = 0; i < (txpktbuf_bndy - 1); i++) {
+                status = _rtl92ce_llt_write(hw, i, i + 1);
+                if (true != status)
+                        return status;
+        }
+
+        status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
+        if (true != status)
+                return status;
+
+        for (i = txpktbuf_bndy; i < maxPage; i++) {
+                status = _rtl92ce_llt_write(hw, i, (i + 1));
+                if (true != status)
+                        return status;
+        }
+
+        status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
+        if (true != status)
+                return status;
+
+        return true;
+}
+
+static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
+{
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
+
+        if (rtlpci->up_first_time)
+                return;
+
+        if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
+                rtl92ce_sw_led_on(hw, pLed0);
+        else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
+                rtl92ce_sw_led_on(hw, pLed0);
+        else
+                rtl92ce_sw_led_off(hw, pLed0);
+
+}
+
+static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        unsigned char bytetmp;
+        unsigned short wordtmp;
+        u16 retry;
+
+        rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
+        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
+        rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
+
+        bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
+        udelay(2);
+
+        rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
+        udelay(2);
+
+        bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
+        udelay(2);
+
+        retry = 0;
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
+                                                rtl_read_dword(rtlpriv, 0xEC),
+                                                bytetmp));
+
+        while ((bytetmp & BIT(0)) && retry < 1000) {
+                retry++;
+                udelay(50);
+                bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
+                                                        rtl_read_dword(rtlpriv,
+                                                                       0xEC),
+                                                        bytetmp));
+                udelay(50);
+        }
+
+        rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
+
+        rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
+        udelay(2);
+
+        rtl_write_word(rtlpriv, REG_CR, 0x2ff);
+
+        if (_rtl92ce_llt_table_init(hw) == false)
+                return false;;
+
+        rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
+        rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
+
+        rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
+
+        wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
+        wordtmp &= 0xf;
+        wordtmp |= 0xF771;
+        rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
+
+        rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
+        rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
+        rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
+
+        rtl_write_byte(rtlpriv, 0x4d0, 0x0);
+
+        rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
+                        ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
+                        DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_MGQ_DESA,
+                        (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
+                        DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_VOQ_DESA,
+                        (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_VIQ_DESA,
+                        (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_BEQ_DESA,
+                        (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_BKQ_DESA,
+                        (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_HQ_DESA,
+                        (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
+                        DMA_BIT_MASK(32));
+        rtl_write_dword(rtlpriv, REG_RX_DESA,
+                        (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
+                        DMA_BIT_MASK(32));
+
+        if (IS_92C_SERIAL(rtlhal->version))
+                rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
+        else
+                rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
+
+        rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
+
+        bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
+        rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
+        do {
+                retry++;
+                bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
+        } while ((retry < 200) && (bytetmp & BIT(7)));
+
+        _rtl92ce_gen_refresh_led_state(hw);
+
+        rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
+
+        return true;;
+}
+
+static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
+{
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 reg_bw_opmode;
+        u32 reg_ratr, reg_prsr;
+
+        reg_bw_opmode = BW_OPMODE_20MHZ;
+        reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
+            RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
+        reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
+
+        rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
+
+        rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
+
+        rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
+
+        rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
+
+        rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
+
+        rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
+
+        rtl_write_word(rtlpriv, REG_RL, 0x0707);
+
+        rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
+
+        rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
+
+        rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
+        rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
+        rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
+        rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
+
+        rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
+
+        rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
+
+        rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
+
+        rtlpci->reg_bcn_ctrl_val = 0x1f;
+        rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
+
+        rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
+
+        rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
+
+        rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
+        rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
+
+        rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
+
+        rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
+
+        rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
+
+        rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
+
+        rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
+        rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
+
+        rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
+
+        rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
+
+        rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
+        rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
+
+}
+
+static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        rtl_write_byte(rtlpriv, 0x34b, 0x93);
+        rtl_write_word(rtlpriv, 0x350, 0x870c);
+        rtl_write_byte(rtlpriv, 0x352, 0x1);
+
+        if (ppsc->b_support_backdoor)
+                rtl_write_byte(rtlpriv, 0x349, 0x1b);
+        else
+                rtl_write_byte(rtlpriv, 0x349, 0x03);
+
+        rtl_write_word(rtlpriv, 0x350, 0x2718);
+        rtl_write_byte(rtlpriv, 0x352, 0x1);
+}
+
+void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 sec_reg_value;
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
+                 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
+                  rtlpriv->sec.pairwise_enc_algorithm,
+                  rtlpriv->sec.group_enc_algorithm));
+
+        if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
+                                                        "hw encryption\n"));
+                return;
+        }
+
+        sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
+
+        if (rtlpriv->sec.use_defaultkey) {
+                sec_reg_value |= SCR_TxUseDK;
+                sec_reg_value |= SCR_RxUseDK;
+        }
+
+        sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
+
+        rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
+
+        RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
+                 ("The SECR-value %x\n", sec_reg_value));
+
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
+
+}
+
+int rtl92ce_hw_init(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        static bool iqk_initialized; /* initialized to false */
+        bool rtstatus = true;
+        bool is92c;
+        int err;
+        u8 tmp_u1b;
+
+        rtlpci->being_init_adapter = true;
+        rtlpriv->intf_ops->disable_aspm(hw);
+        rtstatus = _rtl92ce_init_mac(hw);
+        if (rtstatus != true) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
+                err = 1;
+                return err;
+        }
+
+        err = rtl92c_download_fw(hw);
+        if (err) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Failed to download FW. Init HW "
+                          "without FW now..\n"));
+                err = 1;
+                rtlhal->bfw_ready = false;
+                return err;
+        } else {
+                rtlhal->bfw_ready = true;
+        }
+
+        rtlhal->last_hmeboxnum = 0;
+        rtl92c_phy_mac_config(hw);
+        rtl92c_phy_bb_config(hw);
+        rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
+        rtl92c_phy_rf_config(hw);
+        rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
+                                                 RF_CHNLBW, RFREG_OFFSET_MASK);
+        rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
+                                                 RF_CHNLBW, RFREG_OFFSET_MASK);
+        rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
+        rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
+        rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
+        _rtl92ce_hw_configure(hw);
+        rtl_cam_reset_all_entry(hw);
+        rtl92ce_enable_hw_security_config(hw);
+        ppsc->rfpwr_state = ERFON;
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
+        _rtl92ce_enable_aspm_back_door(hw);
+        rtlpriv->intf_ops->enable_aspm(hw);
+        if (ppsc->rfpwr_state == ERFON) {
+                rtl92c_phy_set_rfpath_switch(hw, 1);
+                if (iqk_initialized)
+                        rtl92c_phy_iq_calibrate(hw, true);
+                else {
+                        rtl92c_phy_iq_calibrate(hw, false);
+                        iqk_initialized = true;
+                }
+
+                rtl92c_dm_check_txpower_tracking(hw);
+                rtl92c_phy_lc_calibrate(hw);
+        }
+
+        is92c = IS_92C_SERIAL(rtlhal->version);
+        tmp_u1b = efuse_read_1byte(hw, 0x1FA);
+        if (!(tmp_u1b & BIT(0))) {
+                rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
+        }
+
+        if (!(tmp_u1b & BIT(1)) && is92c) {
+                rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
+        }
+
+        if (!(tmp_u1b & BIT(4))) {
+                tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
+                tmp_u1b &= 0x0F;
+                rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
+                udelay(10);
+                rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
+        }
+        rtl92c_dm_init(hw);
+        rtlpci->being_init_adapter = false;
+        return err;
+}
+
+static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        enum version_8192c version = VERSION_UNKNOWN;
+        u32 value32;
+
+        value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
+        if (value32 & TRP_VAUX_EN) {
+                version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
+                           VERSION_A_CHIP_88C;
+        } else {
+                version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
+                           VERSION_B_CHIP_88C;
+        }
+
+        switch (version) {
+        case VERSION_B_CHIP_92C:
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
+                break;
+        case VERSION_B_CHIP_88C:
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
+                break;
+        case VERSION_A_CHIP_92C:
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
+                break;
+        case VERSION_A_CHIP_88C:
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Chip Version ID: Unknown. Bug?\n"));
+                break;
+        }
+
+        switch (version & 0x3) {
+        case CHIP_88C:
+                rtlphy->rf_type = RF_1T1R;
+                break;
+        case CHIP_92C:
+                rtlphy->rf_type = RF_2T2R;
+                break;
+        case CHIP_92C_1T2R:
+                rtlphy->rf_type = RF_1T2R;
+                break;
+        default:
+                rtlphy->rf_type = RF_1T1R;
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("ERROR RF_Type is set!!"));
+                break;
+        }
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
+                 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
+                  "RF_2T2R" : "RF_1T1R"));
+
+        return version;
+}
+
+static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
+                                     enum nl80211_iftype type)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
+        enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
+        bt_msr &= 0xfc;
+
+        if (type == NL80211_IFTYPE_UNSPECIFIED ||
+            type == NL80211_IFTYPE_STATION) {
+                _rtl92ce_stop_tx_beacon(hw);
+                _rtl92ce_enable_bcn_sub_func(hw);
+        } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
+                _rtl92ce_resume_tx_beacon(hw);
+                _rtl92ce_disable_bcn_sub_func(hw);
+        } else {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("Set HW_VAR_MEDIA_STATUS: "
+                          "No such media status(%x).\n", type));
+        }
+
+        switch (type) {
+        case NL80211_IFTYPE_UNSPECIFIED:
+                bt_msr |= MSR_NOLINK;
+                ledaction = LED_CTL_LINK;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Set Network type to NO LINK!\n"));
+                break;
+        case NL80211_IFTYPE_ADHOC:
+                bt_msr |= MSR_ADHOC;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Set Network type to Ad Hoc!\n"));
+                break;
+        case NL80211_IFTYPE_STATION:
+                bt_msr |= MSR_INFRA;
+                ledaction = LED_CTL_LINK;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Set Network type to STA!\n"));
+                break;
+        case NL80211_IFTYPE_AP:
+                bt_msr |= MSR_AP;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Set Network type to AP!\n"));
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Network type %d not support!\n", type));
+                return 1;
+                break;
+
+        }
+
+        rtl_write_byte(rtlpriv, (MSR), bt_msr);
+        rtlpriv->cfg->ops->led_control(hw, ledaction);
+        if ((bt_msr & 0xfc) == MSR_AP)
+                rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
+        else
+                rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
+        return 0;
+}
+
+static void _rtl92ce_set_check_bssid(struct ieee80211_hw *hw,
+                                     enum nl80211_iftype type)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
+        u8 filterout_non_associated_bssid = false;
+
+        switch (type) {
+        case NL80211_IFTYPE_ADHOC:
+        case NL80211_IFTYPE_STATION:
+                filterout_non_associated_bssid = true;
+                break;
+        case NL80211_IFTYPE_UNSPECIFIED:
+        case NL80211_IFTYPE_AP:
+        default:
+                break;
+        }
+
+        if (filterout_non_associated_bssid == true) {
+                reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
+                rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
+                                              (u8 *) (&reg_rcr));
+                _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
+        } else if (filterout_non_associated_bssid == false) {
+                reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
+                _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
+                rtlpriv->cfg->ops->set_hw_reg(hw,
+                                              HW_VAR_RCR, (u8 *) (&reg_rcr));
+        }
+}
+
+int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
+{
+        if (_rtl92ce_set_media_status(hw, type))
+                return -EOPNOTSUPP;
+        _rtl92ce_set_check_bssid(hw, type);
+        return 0;
+}
+
+void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        u32 u4b_ac_param;
+
+        rtl92c_dm_init_edca_turbo(hw);
+
+        u4b_ac_param = (u32) mac->ac[aci].aifs;
+        u4b_ac_param |=
+            ((u32) mac->ac[aci].cw_min & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
+        u4b_ac_param |=
+            ((u32) mac->ac[aci].cw_max & 0xF) << AC_PARAM_ECW_MAX_OFFSET;
+        u4b_ac_param |= (u32) mac->ac[aci].tx_op << AC_PARAM_TXOP_LIMIT_OFFSET;
+        RT_TRACE(rtlpriv, COMP_QOS, DBG_DMESG,
+                 ("queue:%x, ac_param:%x aifs:%x cwmin:%x cwmax:%x txop:%x\n",
+                  aci, u4b_ac_param, mac->ac[aci].aifs, mac->ac[aci].cw_min,
+                  mac->ac[aci].cw_max, mac->ac[aci].tx_op));
+        switch (aci) {
+        case AC1_BK:
+                rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
+                break;
+        case AC0_BE:
+                rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
+                break;
+        case AC2_VI:
+                rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
+                break;
+        case AC3_VO:
+                rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
+                break;
+        default:
+                RT_ASSERT(false, ("invalid aci: %d !\n", aci));
+                break;
+        }
+}
+
+void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
+        rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
+        rtlpci->irq_enabled = true;
+}
+
+void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
+        rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
+        rtlpci->irq_enabled = false;
+}
+
+static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u8 u1b_tmp;
+
+        rtlpriv->intf_ops->enable_aspm(hw);
+        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
+        rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
+        rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
+        rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
+        if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->bfw_ready)
+                rtl92c_firmware_selfreset(hw);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
+        rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
+        rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
+        u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
+        rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
+                        (u1b_tmp << 8));
+        rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
+        rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
+        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
+        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
+        rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
+        rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
+        rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
+}
+
+void rtl92ce_card_disable(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        enum nl80211_iftype opmode;
+
+        mac->link_state = MAC80211_NOLINK;
+        opmode = NL80211_IFTYPE_UNSPECIFIED;
+        _rtl92ce_set_media_status(hw, opmode);
+        if (rtlpci->driver_is_goingto_unload ||
+            ppsc->rfoff_reason > RF_CHANGE_BY_PS)
+                rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
+        RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
+        _rtl92ce_poweroff_adapter(hw);
+}
+
+void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
+                                  u32 *p_inta, u32 *p_intb)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
+        rtl_write_dword(rtlpriv, ISR, *p_inta);
+
+        /*
+         * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
+         * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
+         */
+}
+
+void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
+{
+
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u16 bcn_interval, atim_window;
+
+        bcn_interval = mac->beacon_interval;
+        atim_window = 2;        /*FIX MERGE */
+        rtl92ce_disable_interrupt(hw);
+        rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
+        rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
+        rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
+        rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
+        rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
+        rtl_write_byte(rtlpriv, 0x606, 0x30);
+        rtl92ce_enable_interrupt(hw);
+}
+
+void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u16 bcn_interval = mac->beacon_interval;
+
+        RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
+                 ("beacon_interval:%d\n", bcn_interval));
+        rtl92ce_disable_interrupt(hw);
+        rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
+        rtl92ce_enable_interrupt(hw);
+}
+
+void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
+                                   u32 add_msr, u32 rm_msr)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
+                 ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
+        if (add_msr)
+                rtlpci->irq_mask[0] |= add_msr;
+        if (rm_msr)
+                rtlpci->irq_mask[0] &= (~rm_msr);
+        rtl92ce_disable_interrupt(hw);
+        rtl92ce_enable_interrupt(hw);
+}
+
+static u8 _rtl92c_get_chnl_group(u8 chnl)
+{
+        u8 group;
+
+        if (chnl < 3)
+                group = 0;
+        else if (chnl < 9)
+                group = 1;
+        else
+                group = 2;
+        return group;
+}
+
+static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
+                                                 bool autoload_fail,
+                                                 u8 *hwinfo)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 rf_path, index, tempval;
+        u16 i;
+
+        for (rf_path = 0; rf_path < 2; rf_path++) {
+                for (i = 0; i < 3; i++) {
+                        if (!autoload_fail) {
+                                rtlefuse->
+                                    eeprom_chnlarea_txpwr_cck[rf_path][i] =
+                                    hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
+                                rtlefuse->
+                                    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
+                                    hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
+                                           i];
+                        } else {
+                                rtlefuse->
+                                    eeprom_chnlarea_txpwr_cck[rf_path][i] =
+                                    EEPROM_DEFAULT_TXPOWERLEVEL;
+                                rtlefuse->
+                                    eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
+                                    EEPROM_DEFAULT_TXPOWERLEVEL;
+                        }
+                }
+        }
+
+        for (i = 0; i < 3; i++) {
+                if (!autoload_fail)
+                        tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
+                else
+                        tempval = EEPROM_DEFAULT_HT40_2SDIFF;
+                rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
+                    (tempval & 0xf);
+                rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
+                    ((tempval & 0xf0) >> 4);
+        }
+
+        for (rf_path = 0; rf_path < 2; rf_path++)
+                for (i = 0; i < 3; i++)
+                        RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
+                                ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
+                                 i,
+                                 rtlefuse->
+                                 eeprom_chnlarea_txpwr_cck[rf_path][i]));
+        for (rf_path = 0; rf_path < 2; rf_path++)
+                for (i = 0; i < 3; i++)
+                        RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
+                                ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
+                                 rf_path, i,
+                                 rtlefuse->
+                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
+        for (rf_path = 0; rf_path < 2; rf_path++)
+                for (i = 0; i < 3; i++)
+                        RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
+                                ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
+                                 rf_path, i,
+                                 rtlefuse->
+                                 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
+                                 [i]));
+
+        for (rf_path = 0; rf_path < 2; rf_path++) {
+                for (i = 0; i < 14; i++) {
+                        index = _rtl92c_get_chnl_group((u8) i);
+
+                        rtlefuse->txpwrlevel_cck[rf_path][i] =
+                            rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
+                        rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
+                            rtlefuse->
+                            eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
+
+                        if ((rtlefuse->
+                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
+                             rtlefuse->
+                             eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
+                            > 0) {
+                                rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
+                                    rtlefuse->
+                                    eeprom_chnlarea_txpwr_ht40_1s[rf_path]
+                                    [index] -
+                                    rtlefuse->
+                                    eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
+                                    [index];
+                        } else {
+                                rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
+                        }
+                }
+
+                for (i = 0; i < 14; i++) {
+                        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                                ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
+                                 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
+                                 rtlefuse->txpwrlevel_cck[rf_path][i],
+                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
+                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
+                }
+        }
+
+        for (i = 0; i < 3; i++) {
+                if (!autoload_fail) {
+                        rtlefuse->eeprom_pwrlimit_ht40[i] =
+                            hwinfo[EEPROM_TXPWR_GROUP + i];
+                        rtlefuse->eeprom_pwrlimit_ht20[i] =
+                            hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
+                } else {
+                        rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
+                        rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
+                }
+        }
+
+        for (rf_path = 0; rf_path < 2; rf_path++) {
+                for (i = 0; i < 14; i++) {
+                        index = _rtl92c_get_chnl_group((u8) i);
+
+                        if (rf_path == RF90_PATH_A) {
+                                rtlefuse->pwrgroup_ht20[rf_path][i] =
+                                    (rtlefuse->eeprom_pwrlimit_ht20[index]
+                                     & 0xf);
+                                rtlefuse->pwrgroup_ht40[rf_path][i] =
+                                    (rtlefuse->eeprom_pwrlimit_ht40[index]
+                                     & 0xf);
+                        } else if (rf_path == RF90_PATH_B) {
+                                rtlefuse->pwrgroup_ht20[rf_path][i] =
+                                    ((rtlefuse->eeprom_pwrlimit_ht20[index]
+                                      & 0xf0) >> 4);
+                                rtlefuse->pwrgroup_ht40[rf_path][i] =
+                                    ((rtlefuse->eeprom_pwrlimit_ht40[index]
+                                      & 0xf0) >> 4);
+                        }
+
+                        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                                ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
+                                 rf_path, i,
+                                 rtlefuse->pwrgroup_ht20[rf_path][i]));
+                        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                                ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
+                                 rf_path, i,
+                                 rtlefuse->pwrgroup_ht40[rf_path][i]));
+                }
+        }
+
+        for (i = 0; i < 14; i++) {
+                index = _rtl92c_get_chnl_group((u8) i);
+
+                if (!autoload_fail)
+                        tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
+                else
+                        tempval = EEPROM_DEFAULT_HT20_DIFF;
+
+                rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
+                rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
+                    ((tempval >> 4) & 0xF);
+
+                if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
+                        rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
+
+                if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
+                        rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
+
+                index = _rtl92c_get_chnl_group((u8) i);
+
+                if (!autoload_fail)
+                        tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
+                else
+                        tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
+
+                rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
+                rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
+                    ((tempval >> 4) & 0xF);
+        }
+
+        rtlefuse->legacy_ht_txpowerdiff =
+            rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
+
+        for (i = 0; i < 14; i++)
+                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                        ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
+                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
+        for (i = 0; i < 14; i++)
+                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                        ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
+                         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
+        for (i = 0; i < 14; i++)
+                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                        ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
+                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
+        for (i = 0; i < 14; i++)
+                RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                        ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
+                         rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
+
+        if (!autoload_fail)
+                rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
+        else
+                rtlefuse->eeprom_regulatory = 0;
+        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
+
+        if (!autoload_fail) {
+                rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
+                rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
+        } else {
+                rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
+                rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
+        }
+        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
+                 rtlefuse->eeprom_tssi[RF90_PATH_A],
+                 rtlefuse->eeprom_tssi[RF90_PATH_B]));
+
+        if (!autoload_fail)
+                tempval = hwinfo[EEPROM_THERMAL_METER];
+        else
+                tempval = EEPROM_DEFAULT_THERMALMETER;
+        rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
+
+        if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
+                rtlefuse->b_apk_thermalmeterignore = true;
+
+        rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
+        RTPRINT(rtlpriv, FINIT, INIT_TxPower,
+                ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
+}
+
+static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u16 i, usvalue;
+        u8 hwinfo[HWSET_MAX_SIZE];
+        u16 eeprom_id;
+
+        if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
+                rtl_efuse_shadow_map_update(hw);
+
+                memcpy((void *)hwinfo,
+                       (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
+                       HWSET_MAX_SIZE);
+        } else if (rtlefuse->epromtype == EEPROM_93C46) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("RTL819X Not boot from eeprom, check it !!"));
+        }
+
+        RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
+                      hwinfo, HWSET_MAX_SIZE);
+
+        eeprom_id = *((u16 *)&hwinfo[0]);
+        if (eeprom_id != RTL8190_EEPROM_ID) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
+                rtlefuse->autoload_failflag = true;
+        } else {
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
+                rtlefuse->autoload_failflag = false;
+        }
+
+        if (rtlefuse->autoload_failflag == true)
+                return;
+
+        for (i = 0; i < 6; i += 2) {
+                usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
+                *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
+        }
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                 (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
+
+        _rtl92ce_read_txpower_info_from_hwpg(hw,
+                                             rtlefuse->autoload_failflag,
+                                             hwinfo);
+
+        rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
+        rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
+        rtlefuse->b_txpwr_fromeprom = true;
+        rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
+                 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
+
+        if (rtlhal->oem_id == RT_CID_DEFAULT) {
+                switch (rtlefuse->eeprom_oemid) {
+                case EEPROM_CID_DEFAULT:
+                        if (rtlefuse->eeprom_did == 0x8176) {
+                                if ((rtlefuse->eeprom_svid == 0x103C &&
+                                     rtlefuse->eeprom_smid == 0x1629))
+                                        rtlhal->oem_id = RT_CID_819x_HP;
+                                else
+                                        rtlhal->oem_id = RT_CID_DEFAULT;
+                        } else {
+                                rtlhal->oem_id = RT_CID_DEFAULT;
+                        }
+                        break;
+                case EEPROM_CID_TOSHIBA:
+                        rtlhal->oem_id = RT_CID_TOSHIBA;
+                        break;
+                case EEPROM_CID_QMI:
+                        rtlhal->oem_id = RT_CID_819x_QMI;
+                        break;
+                case EEPROM_CID_WHQL:
+                default:
+                        rtlhal->oem_id = RT_CID_DEFAULT;
+                        break;
+
+                }
+        }
+
+}
+
+static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        switch (rtlhal->oem_id) {
+        case RT_CID_819x_HP:
+                pcipriv->ledctl.bled_opendrain = true;
+                break;
+        case RT_CID_819x_Lenovo:
+        case RT_CID_DEFAULT:
+        case RT_CID_TOSHIBA:
+        case RT_CID_CCX:
+        case RT_CID_819x_Acer:
+        case RT_CID_WHQL:
+        default:
+                break;
+        }
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
+                 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
+}
+
+void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u8 tmp_u1b;
+
+        rtlhal->version = _rtl92ce_read_chip_version(hw);
+        if (get_rf_type(rtlphy) == RF_1T1R)
+                rtlpriv->dm.brfpath_rxenable[0] = true;
+        else
+                rtlpriv->dm.brfpath_rxenable[0] =
+                    rtlpriv->dm.brfpath_rxenable[1] = true;
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
+                                                rtlhal->version));
+        tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
+        if (tmp_u1b & BIT(4)) {
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
+                rtlefuse->epromtype = EEPROM_93C46;
+        } else {
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
+                rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
+        }
+        if (tmp_u1b & BIT(5)) {
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
+                rtlefuse->autoload_failflag = false;
+                _rtl92ce_read_adapter_info(hw);
+        } else {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
+        }
+
+        _rtl92ce_hal_customized_behavior(hw);
+}
+
+void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+
+        u32 ratr_value = (u32) mac->basic_rates;
+        u8 *p_mcsrate = mac->mcs;
+        u8 ratr_index = 0;
+        u8 b_nmode = mac->ht_enable;
+        u8 mimo_ps = 1;
+        u16 shortgi_rate;
+        u32 tmp_ratr_value;
+        u8 b_curtxbw_40mhz = mac->bw_40;
+        u8 b_curshortgi_40mhz = mac->sgi_40;
+        u8 b_curshortgi_20mhz = mac->sgi_20;
+        enum wireless_mode wirelessmode = mac->mode;
+
+        ratr_value |= EF2BYTE((*(u16 *) (p_mcsrate))) << 12;
+
+        switch (wirelessmode) {
+        case WIRELESS_MODE_B:
+                if (ratr_value & 0x0000000c)
+                        ratr_value &= 0x0000000d;
+                else
+                        ratr_value &= 0x0000000f;
+                break;
+        case WIRELESS_MODE_G:
+                ratr_value &= 0x00000FF5;
+                break;
+        case WIRELESS_MODE_N_24G:
+        case WIRELESS_MODE_N_5G:
+                b_nmode = 1;
+                if (mimo_ps == 0) {
+                        ratr_value &= 0x0007F005;
+                } else {
+                        u32 ratr_mask;
+
+                        if (get_rf_type(rtlphy) == RF_1T2R ||
+                            get_rf_type(rtlphy) == RF_1T1R)
+                                ratr_mask = 0x000ff005;
+                        else
+                                ratr_mask = 0x0f0ff005;
+
+                        ratr_value &= ratr_mask;
+                }
+                break;
+        default:
+                if (rtlphy->rf_type == RF_1T2R)
+                        ratr_value &= 0x000ff0ff;
+                else
+                        ratr_value &= 0x0f0ff0ff;
+
+                break;
+        }
+
+        ratr_value &= 0x0FFFFFFF;
+
+        if (b_nmode && ((b_curtxbw_40mhz &&
+                         b_curshortgi_40mhz) || (!b_curtxbw_40mhz &&
+                                                 b_curshortgi_20mhz))) {
+
+                ratr_value |= 0x10000000;
+                tmp_ratr_value = (ratr_value >> 12);
+
+                for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
+                        if ((1 << shortgi_rate) & tmp_ratr_value)
+                                break;
+                }
+
+                shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
+                    (shortgi_rate << 4) | (shortgi_rate);
+        }
+
+        rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
+                 ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
+}
+
+void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u32 ratr_bitmap = (u32) mac->basic_rates;
+        u8 *p_mcsrate = mac->mcs;
+        u8 ratr_index;
+        u8 b_curtxbw_40mhz = mac->bw_40;
+        u8 b_curshortgi_40mhz = mac->sgi_40;
+        u8 b_curshortgi_20mhz = mac->sgi_20;
+        enum wireless_mode wirelessmode = mac->mode;
+        bool b_shortgi = false;
+        u8 rate_mask[5];
+        u8 macid = 0;
+        u8 mimops = 1;
+
+        ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
+        switch (wirelessmode) {
+        case WIRELESS_MODE_B:
+                ratr_index = RATR_INX_WIRELESS_B;
+                if (ratr_bitmap & 0x0000000c)
+                        ratr_bitmap &= 0x0000000d;
+                else
+                        ratr_bitmap &= 0x0000000f;
+                break;
+        case WIRELESS_MODE_G:
+                ratr_index = RATR_INX_WIRELESS_GB;
+
+                if (rssi_level == 1)
+                        ratr_bitmap &= 0x00000f00;
+                else if (rssi_level == 2)
+                        ratr_bitmap &= 0x00000ff0;
+                else
+                        ratr_bitmap &= 0x00000ff5;
+                break;
+        case WIRELESS_MODE_A:
+                ratr_index = RATR_INX_WIRELESS_A;
+                ratr_bitmap &= 0x00000ff0;
+                break;
+        case WIRELESS_MODE_N_24G:
+        case WIRELESS_MODE_N_5G:
+                ratr_index = RATR_INX_WIRELESS_NGB;
+
+                if (mimops == 0) {
+                        if (rssi_level == 1)
+                                ratr_bitmap &= 0x00070000;
+                        else if (rssi_level == 2)
+                                ratr_bitmap &= 0x0007f000;
+                        else
+                                ratr_bitmap &= 0x0007f005;
+                } else {
+                        if (rtlphy->rf_type == RF_1T2R ||
+                            rtlphy->rf_type == RF_1T1R) {
+                                if (b_curtxbw_40mhz) {
+                                        if (rssi_level == 1)
+                                                ratr_bitmap &= 0x000f0000;
+                                        else if (rssi_level == 2)
+                                                ratr_bitmap &= 0x000ff000;
+                                        else
+                                                ratr_bitmap &= 0x000ff015;
+                                } else {
+                                        if (rssi_level == 1)
+                                                ratr_bitmap &= 0x000f0000;
+                                        else if (rssi_level == 2)
+                                                ratr_bitmap &= 0x000ff000;
+                                        else
+                                                ratr_bitmap &= 0x000ff005;
+                                }
+                        } else {
+                                if (b_curtxbw_40mhz) {
+                                        if (rssi_level == 1)
+                                                ratr_bitmap &= 0x0f0f0000;
+                                        else if (rssi_level == 2)
+                                                ratr_bitmap &= 0x0f0ff000;
+                                        else
+                                                ratr_bitmap &= 0x0f0ff015;
+                                } else {
+                                        if (rssi_level == 1)
+                                                ratr_bitmap &= 0x0f0f0000;
+                                        else if (rssi_level == 2)
+                                                ratr_bitmap &= 0x0f0ff000;
+                                        else
+                                                ratr_bitmap &= 0x0f0ff005;
+                                }
+                        }
+                }
+
+                if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
+                    (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
+
+                        if (macid == 0)
+                                b_shortgi = true;
+                        else if (macid == 1)
+                                b_shortgi = false;
+                }
+                break;
+        default:
+                ratr_index = RATR_INX_WIRELESS_NGB;
+
+                if (rtlphy->rf_type == RF_1T2R)
+                        ratr_bitmap &= 0x000ff0ff;
+                else
+                        ratr_bitmap &= 0x0f0ff0ff;
+                break;
+        }
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
+                 ("ratr_bitmap :%x\n", ratr_bitmap));
+        *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
+                                       (ratr_index << 28));
+        rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
+                                                 "ratr_val:%x, %x:%x:%x:%x:%x\n",
+                                                 ratr_index, ratr_bitmap,
+                                                 rate_mask[0], rate_mask[1],
+                                                 rate_mask[2], rate_mask[3],
+                                                 rate_mask[4]));
+        rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
+}
+
+void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u16 sifs_timer;
+
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
+                                      (u8 *)&mac->slot_time);
+        if (!mac->ht_enable)
+                sifs_timer = 0x0a0a;
+        else
+                sifs_timer = 0x1010;
+        rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
+}
+
+bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
+        u8 u1tmp;
+        bool b_actuallyset = false;
+        unsigned long flag;
+
+        if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
+                return false;
+
+        if (ppsc->b_swrf_processing)
+                return false;
+
+        spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
+        if (ppsc->rfchange_inprogress) {
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
+                return false;
+        } else {
+                ppsc->rfchange_inprogress = true;
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
+        }
+
+        cur_rfstate = ppsc->rfpwr_state;
+
+        if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
+            RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
+                rtlpriv->intf_ops->disable_aspm(hw);
+                RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
+        }
+
+        rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
+                       REG_MAC_PINMUX_CFG)&~(BIT(3)));
+
+        u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
+        e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
+
+        if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
+                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                         ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
+
+                e_rfpowerstate_toset = ERFON;
+                ppsc->b_hwradiooff = false;
+                b_actuallyset = true;
+        } else if ((ppsc->b_hwradiooff == false)
+                   && (e_rfpowerstate_toset == ERFOFF)) {
+                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                         ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
+
+                e_rfpowerstate_toset = ERFOFF;
+                ppsc->b_hwradiooff = true;
+                b_actuallyset = true;
+        }
+
+        if (b_actuallyset) {
+                if (e_rfpowerstate_toset == ERFON) {
+                        if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
+                            RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
+                                rtlpriv->intf_ops->disable_aspm(hw);
+                                RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
+                        }
+                }
+
+                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
+                ppsc->rfchange_inprogress = false;
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
+
+                if (e_rfpowerstate_toset == ERFOFF) {
+                        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
+                                rtlpriv->intf_ops->enable_aspm(hw);
+                                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
+                        }
+                }
+
+        } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
+                if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
+                        RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
+
+                if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
+                        rtlpriv->intf_ops->enable_aspm(hw);
+                        RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
+                }
+
+                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
+                ppsc->rfchange_inprogress = false;
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
+        } else {
+                spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
+                ppsc->rfchange_inprogress = false;
+                spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
+        }
+
+        *valid = 1;
+        return !ppsc->b_hwradiooff;
+
+}
+
+void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
+                     u8 *p_macaddr, bool is_group, u8 enc_algo,
+                     bool is_wepkey, bool clear_all)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 *macaddr = p_macaddr;
+        u32 entry_id = 0;
+        bool is_pairwise = false;
+
+        static u8 cam_const_addr[4][6] = {
+                {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+                {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
+                {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
+                {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
+        };
+        static u8 cam_const_broad[] = {
+                0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+        };
+
+        if (clear_all) {
+                u8 idx = 0;
+                u8 cam_offset = 0;
+                u8 clear_number = 5;
+
+                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
+
+                for (idx = 0; idx < clear_number; idx++) {
+                        rtl_cam_mark_invalid(hw, cam_offset + idx);
+                        rtl_cam_empty_entry(hw, cam_offset + idx);
+
+                        if (idx < 5) {
+                                memset(rtlpriv->sec.key_buf[idx], 0,
+                                       MAX_KEY_LEN);
+                                rtlpriv->sec.key_len[idx] = 0;
+                        }
+                }
+
+        } else {
+                switch (enc_algo) {
+                case WEP40_ENCRYPTION:
+                        enc_algo = CAM_WEP40;
+                        break;
+                case WEP104_ENCRYPTION:
+                        enc_algo = CAM_WEP104;
+                        break;
+                case TKIP_ENCRYPTION:
+                        enc_algo = CAM_TKIP;
+                        break;
+                case AESCCMP_ENCRYPTION:
+                        enc_algo = CAM_AES;
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
+                                        "not process\n"));
+                        enc_algo = CAM_TKIP;
+                        break;
+                }
+
+                if (is_wepkey || rtlpriv->sec.use_defaultkey) {
+                        macaddr = cam_const_addr[key_index];
+                        entry_id = key_index;
+                } else {
+                        if (is_group) {
+                                macaddr = cam_const_broad;
+                                entry_id = key_index;
+                        } else {
+                                key_index = PAIRWISE_KEYIDX;
+                                entry_id = CAM_PAIRWISE_KEY_POSITION;
+                                is_pairwise = true;
+                        }
+                }
+
+                if (rtlpriv->sec.key_len[key_index] == 0) {
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("delete one entry\n"));
+                        rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
+                } else {
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
+                                 ("The insert KEY length is %d\n",
+                                  rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
+                                 ("The insert KEY  is %x %x\n",
+                                  rtlpriv->sec.key_buf[0][0],
+                                  rtlpriv->sec.key_buf[0][1]));
+
+                        RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                 ("add one entry\n"));
+                        if (is_pairwise) {
+                                RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
+                                              "Pairwiase Key content :",
+                                              rtlpriv->sec.pairwise_key,
+                                              rtlpriv->sec.
+                                              key_len[PAIRWISE_KEYIDX]);
+
+                                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                         ("set Pairwiase key\n"));
+
+                                rtl_cam_add_one_entry(hw, macaddr, key_index,
+                                                      entry_id, enc_algo,
+                                                      CAM_CONFIG_NO_USEDK,
+                                                      rtlpriv->sec.
+                                                      key_buf[key_index]);
+                        } else {
+                                RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
+                                         ("set group key\n"));
+
+                                if (mac->opmode == NL80211_IFTYPE_ADHOC) {
+                                        rtl_cam_add_one_entry(hw,
+                                                rtlefuse->dev_addr,
+                                                PAIRWISE_KEYIDX,
+                                                CAM_PAIRWISE_KEY_POSITION,
+                                                enc_algo,
+                                                CAM_CONFIG_NO_USEDK,
+                                                rtlpriv->sec.key_buf
+                                                [entry_id]);
+                                }
+
+                                rtl_cam_add_one_entry(hw, macaddr, key_index,
+                                                entry_id, enc_algo,
+                                                CAM_CONFIG_NO_USEDK,
+                                                rtlpriv->sec.key_buf[entry_id]);
+                        }
+
+                }
+        }
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
new file mode 100644
index 000000000000..305c819c8c78
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
@@ -0,0 +1,57 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92CE_HW_H__
+#define __RTL92CE_HW_H__
+
+void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
+void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw);
+void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
+                                  u32 *p_inta, u32 *p_intb);
+int rtl92ce_hw_init(struct ieee80211_hw *hw);
+void rtl92ce_card_disable(struct ieee80211_hw *hw);
+void rtl92ce_enable_interrupt(struct ieee80211_hw *hw);
+void rtl92ce_disable_interrupt(struct ieee80211_hw *hw);
+int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
+void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci);
+void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw);
+void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw);
+void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
+                                   u32 add_msr, u32 rm_msr);
+void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
+void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw);
+void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
+void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw);
+bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid);
+void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw);
+void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
+                     u8 *p_macaddr, bool is_group, u8 enc_algo,
+                     bool is_wepkey, bool clear_all);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/led.c b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
new file mode 100644
index 000000000000..78a0569208ea
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
@@ -0,0 +1,144 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../wifi.h"
+#include "../pci.h"
+#include "reg.h"
+#include "led.h"
+
+void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
+{
+        u8 ledcfg;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
+                 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
+
+        ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
+
+        switch (pled->ledpin) {
+        case LED_PIN_GPIO0:
+                break;
+        case LED_PIN_LED0:
+                rtl_write_byte(rtlpriv,
+                               REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6));
+                break;
+        case LED_PIN_LED1:
+                rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+        pled->b_ledon = true;
+}
+
+void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        u8 ledcfg;
+
+        RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
+                 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
+
+        ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
+
+        switch (pled->ledpin) {
+        case LED_PIN_GPIO0:
+                break;
+        case LED_PIN_LED0:
+                ledcfg &= 0xf0;
+                if (pcipriv->ledctl.bled_opendrain == true)
+                        rtl_write_byte(rtlpriv, REG_LEDCFG2,
+                                       (ledcfg | BIT(1) | BIT(5) | BIT(6)));
+                else
+                        rtl_write_byte(rtlpriv, REG_LEDCFG2,
+                                       (ledcfg | BIT(3) | BIT(5) | BIT(6)));
+                break;
+        case LED_PIN_LED1:
+                ledcfg &= 0x0f;
+                rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+        pled->b_ledon = false;
+}
+
+void rtl92ce_init_sw_leds(struct ieee80211_hw *hw)
+{
+}
+
+void rtl92ce_deinit_sw_leds(struct ieee80211_hw *hw)
+{
+}
+
+void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
+                                    enum led_ctl_mode ledaction)
+{
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
+        switch (ledaction) {
+        case LED_CTL_POWER_ON:
+        case LED_CTL_LINK:
+        case LED_CTL_NO_LINK:
+                rtl92ce_sw_led_on(hw, pLed0);
+                break;
+        case LED_CTL_POWER_OFF:
+                rtl92ce_sw_led_off(hw, pLed0);
+                break;
+        default:
+                break;
+        }
+}
+
+void rtl92ce_led_control(struct ieee80211_hw *hw,
+                        enum led_ctl_mode ledaction)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+
+        if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
+            (ledaction == LED_CTL_TX ||
+             ledaction == LED_CTL_RX ||
+             ledaction == LED_CTL_SITE_SURVEY ||
+             ledaction == LED_CTL_LINK ||
+             ledaction == LED_CTL_NO_LINK ||
+             ledaction == LED_CTL_START_TO_LINK ||
+             ledaction == LED_CTL_POWER_ON)) {
+                return;
+        }
+        RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, ("ledaction %d,\n",
+                                ledaction));
+        _rtl92ce_sw_led_control(hw, ledaction);
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/led.h b/drivers/net/wireless/rtlwifi/rtl8192ce/led.h
new file mode 100644
index 000000000000..10da3018f4b7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/led.h
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92CE_LED_H__
+#define __RTL92CE_LED_H__
+
+void rtl92ce_init_sw_leds(struct ieee80211_hw *hw);
+void rtl92ce_deinit_sw_leds(struct ieee80211_hw *hw);
+void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
+void rtl92ce_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
+void _rtl92ce_sw_led_control(struct ieee80211_hw *hw,
+                                    enum led_ctl_mode ledaction);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
new file mode 100644
index 000000000000..45044117139a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
@@ -0,0 +1,2676 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../wifi.h"
+#include "../pci.h"
+#include "../ps.h"
+#include "reg.h"
+#include "def.h"
+#include "phy.h"
+#include "rf.h"
+#include "dm.h"
+#include "table.h"
+
+static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
+                                         enum radio_path rfpath, u32 offset);
+static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
+                                           enum radio_path rfpath, u32 offset,
+                                           u32 data);
+static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
+                                      enum radio_path rfpath, u32 offset);
+static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
+                                        enum radio_path rfpath, u32 offset,
+                                        u32 data);
+static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
+static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
+static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
+static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
+                                                  u8 configtype);
+static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
+                                                    u8 configtype);
+static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
+static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
+                                             u32 cmdtableidx, u32 cmdtablesz,
+                                             enum swchnlcmd_id cmdid, u32 para1,
+                                             u32 para2, u32 msdelay);
+static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
+                                             u8 channel, u8 *stage, u8 *step,
+                                             u32 *delay);
+static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
+                                       enum wireless_mode wirelessmode,
+                                       long power_indbm);
+static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
+                                              enum radio_path rfpath);
+static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
+                                         enum wireless_mode wirelessmode,
+                                         u8 txpwridx);
+u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 returnvalue, originalvalue, bitshift;
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
+                                               "bitmask(%#x)\n", regaddr,
+                                               bitmask));
+        originalvalue = rtl_read_dword(rtlpriv, regaddr);
+        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
+        returnvalue = (originalvalue & bitmask) >> bitshift;
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
+                                               "Addr[0x%x]=0x%x\n", bitmask,
+                                               regaddr, originalvalue));
+
+        return returnvalue;
+
+}
+
+void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
+                           u32 regaddr, u32 bitmask, u32 data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 originalvalue, bitshift;
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
+                                               " data(%#x)\n", regaddr, bitmask,
+                                               data));
+
+        if (bitmask != MASKDWORD) {
+                originalvalue = rtl_read_dword(rtlpriv, regaddr);
+                bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
+                data = ((originalvalue & (~bitmask)) | (data << bitshift));
+        }
+
+        rtl_write_dword(rtlpriv, regaddr, data);
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
+                                               " data(%#x)\n", regaddr, bitmask,
+                                               data));
+
+}
+
+u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
+                            enum radio_path rfpath, u32 regaddr, u32 bitmask)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 original_value, readback_value, bitshift;
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        unsigned long flags;
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
+                                               "rfpath(%#x), bitmask(%#x)\n",
+                                               regaddr, rfpath, bitmask));
+
+        spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
+
+        if (rtlphy->rf_mode != RF_OP_BY_FW) {
+                original_value = _rtl92c_phy_rf_serial_read(hw,
+                                                            rfpath, regaddr);
+        } else {
+                original_value = _rtl92c_phy_fw_rf_serial_read(hw,
+                                                               rfpath, regaddr);
+        }
+
+        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
+        readback_value = (original_value & bitmask) >> bitshift;
+
+        spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
+                 ("regaddr(%#x), rfpath(%#x), "
+                  "bitmask(%#x), original_value(%#x)\n",
+                  regaddr, rfpath, bitmask, original_value));
+
+        return readback_value;
+}
+
+void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
+                           enum radio_path rfpath,
+                           u32 regaddr, u32 bitmask, u32 data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        u32 original_value, bitshift;
+        unsigned long flags;
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
+                 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
+                  regaddr, bitmask, data, rfpath));
+
+        spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
+
+        if (rtlphy->rf_mode != RF_OP_BY_FW) {
+                if (bitmask != RFREG_OFFSET_MASK) {
+                        original_value = _rtl92c_phy_rf_serial_read(hw,
+                                                                    rfpath,
+                                                                    regaddr);
+                        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
+                        data =
+                            ((original_value & (~bitmask)) |
+                             (data << bitshift));
+                }
+
+                _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
+        } else {
+                if (bitmask != RFREG_OFFSET_MASK) {
+                        original_value = _rtl92c_phy_fw_rf_serial_read(hw,
+                                                                       rfpath,
+                                                                       regaddr);
+                        bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
+                        data =
+                            ((original_value & (~bitmask)) |
+                             (data << bitshift));
+                }
+                _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
+        }
+
+        spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
+
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
+                                               "bitmask(%#x), data(%#x), "
+                                               "rfpath(%#x)\n", regaddr,
+                                               bitmask, data, rfpath));
+}
+
+static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
+                                         enum radio_path rfpath, u32 offset)
+{
+        RT_ASSERT(false, ("deprecated!\n"));
+        return 0;
+}
+
+static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
+                                           enum radio_path rfpath, u32 offset,
+                                           u32 data)
+{
+        RT_ASSERT(false, ("deprecated!\n"));
+}
+
+static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
+                                      enum radio_path rfpath, u32 offset)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
+        u32 newoffset;
+        u32 tmplong, tmplong2;
+        u8 rfpi_enable = 0;
+        u32 retvalue;
+
+        offset &= 0x3f;
+        newoffset = offset;
+        if (RT_CANNOT_IO(hw)) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
+                return 0xFFFFFFFF;
+        }
+        tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
+        if (rfpath == RF90_PATH_A)
+                tmplong2 = tmplong;
+        else
+                tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
+        tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
+            (newoffset << 23) | BLSSIREADEDGE;
+        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
+                      tmplong & (~BLSSIREADEDGE));
+        mdelay(1);
+        rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
+        mdelay(1);
+        rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
+                      tmplong | BLSSIREADEDGE);
+        mdelay(1);
+        if (rfpath == RF90_PATH_A)
+                rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
+                                                 BIT(8));
+        else if (rfpath == RF90_PATH_B)
+                rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
+                                                 BIT(8));
+        if (rfpi_enable)
+                retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
+                                         BLSSIREADBACKDATA);
+        else
+                retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
+                                         BLSSIREADBACKDATA);
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
+                                               rfpath, pphyreg->rflssi_readback,
+                                               retvalue));
+        return retvalue;
+}
+
+static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
+                                        enum radio_path rfpath, u32 offset,
+                                        u32 data)
+{
+        u32 data_and_addr;
+        u32 newoffset;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
+
+        if (RT_CANNOT_IO(hw)) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
+                return;
+        }
+        offset &= 0x3f;
+        newoffset = offset;
+        data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
+        rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
+        RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
+                                               rfpath, pphyreg->rf3wire_offset,
+                                               data_and_addr));
+}
+
+static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
+{
+        u32 i;
+
+        for (i = 0; i <= 31; i++) {
+                if (((bitmask >> i) & 0x1) == 1)
+                        break;
+        }
+        return i;
+}
+
+static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
+{
+        rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
+        rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
+        rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
+        rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
+        rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
+        rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
+        rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
+        rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
+        rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
+        rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
+}
+
+bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        bool is92c = IS_92C_SERIAL(rtlhal->version);
+        bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
+
+        if (is92c)
+                rtl_write_byte(rtlpriv, 0x14, 0x71);
+        return rtstatus;
+}
+
+bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
+{
+        bool rtstatus = true;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u16 regval;
+        u32 regvaldw;
+        u8 b_reg_hwparafile = 1;
+
+        _rtl92c_phy_init_bb_rf_register_definition(hw);
+        regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
+        rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
+                       regval | BIT(13) | BIT(0) | BIT(1));
+        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
+        rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
+        rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
+                       FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
+                       FEN_BB_GLB_RSTn | FEN_BBRSTB);
+        rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
+        regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
+        rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
+        if (b_reg_hwparafile == 1)
+                rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
+        return rtstatus;
+}
+
+bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
+{
+        return rtl92c_phy_rf6052_config(hw);
+}
+
+static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        bool rtstatus;
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
+        rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
+                                                 BASEBAND_CONFIG_PHY_REG);
+        if (rtstatus != true) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
+                return false;
+        }
+        if (rtlphy->rf_type == RF_1T2R) {
+                _rtl92c_phy_bb_config_1t(hw);
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
+        }
+        if (rtlefuse->autoload_failflag == false) {
+                rtlphy->pwrgroup_cnt = 0;
+                rtstatus = _rtl92c_phy_config_bb_with_pgheaderfile(hw,
+                                                   BASEBAND_CONFIG_PHY_REG);
+        }
+        if (rtstatus != true) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
+                return false;
+        }
+        rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
+                                                 BASEBAND_CONFIG_AGC_TAB);
+        if (rtstatus != true) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
+                return false;
+        }
+        rtlphy->bcck_high_power = (bool) (rtl_get_bbreg(hw,
+                                                RFPGA0_XA_HSSIPARAMETER2,
+                                                0x200));
+        return true;
+}
+
+static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 i;
+        u32 arraylength;
+        u32 *ptrarray;
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
+        arraylength = MAC_2T_ARRAYLENGTH;
+        ptrarray = RTL8192CEMAC_2T_ARRAY;
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
+        for (i = 0; i < arraylength; i = i + 2)
+                rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
+        return true;
+}
+
+void rtl92c_phy_config_bb_external_pa(struct ieee80211_hw *hw)
+{
+}
+
+static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
+                                                  u8 configtype)
+{
+        int i;
+        u32 *phy_regarray_table;
+        u32 *agctab_array_table;
+        u16 phy_reg_arraylen, agctab_arraylen;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (IS_92C_SERIAL(rtlhal->version)) {
+                agctab_arraylen = AGCTAB_2TARRAYLENGTH;
+                agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
+                phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
+                phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
+        } else {
+                agctab_arraylen = AGCTAB_1TARRAYLENGTH;
+                agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
+                phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
+                phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
+        }
+        if (configtype == BASEBAND_CONFIG_PHY_REG) {
+                for (i = 0; i < phy_reg_arraylen; i = i + 2) {
+                        if (phy_regarray_table[i] == 0xfe)
+                                mdelay(50);
+                        else if (phy_regarray_table[i] == 0xfd)
+                                mdelay(5);
+                        else if (phy_regarray_table[i] == 0xfc)
+                                mdelay(1);
+                        else if (phy_regarray_table[i] == 0xfb)
+                                udelay(50);
+                        else if (phy_regarray_table[i] == 0xfa)
+                                udelay(5);
+                        else if (phy_regarray_table[i] == 0xf9)
+                                udelay(1);
+                        rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
+                                      phy_regarray_table[i + 1]);
+                        udelay(1);
+                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                                 ("The phy_regarray_table[0] is %x"
+                                  " Rtl819XPHY_REGArray[1] is %x\n",
+                                  phy_regarray_table[i],
+                                  phy_regarray_table[i + 1]));
+                }
+                rtl92c_phy_config_bb_external_pa(hw);
+        } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
+                for (i = 0; i < agctab_arraylen; i = i + 2) {
+                        rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
+                                      agctab_array_table[i + 1]);
+                        udelay(1);
+                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                                 ("The agctab_array_table[0] is "
+                                  "%x Rtl819XPHY_REGArray[1] is %x\n",
+                                  agctab_array_table[i],
+                                  agctab_array_table[i + 1]));
+                }
+        }
+        return true;
+}
+
+static void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
+                                                   u32 regaddr, u32 bitmask,
+                                                   u32 data)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        if (regaddr == RTXAGC_A_RATE18_06) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][0]));
+        }
+        if (regaddr == RTXAGC_A_RATE54_24) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][1]));
+        }
+        if (regaddr == RTXAGC_A_CCK1_MCS32) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][6]));
+        }
+        if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][7]));
+        }
+        if (regaddr == RTXAGC_A_MCS03_MCS00) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][2]));
+        }
+        if (regaddr == RTXAGC_A_MCS07_MCS04) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][3]));
+        }
+        if (regaddr == RTXAGC_A_MCS11_MCS08) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][4]));
+        }
+        if (regaddr == RTXAGC_A_MCS15_MCS12) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][5]));
+        }
+        if (regaddr == RTXAGC_B_RATE18_06) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
+                    data;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][8]));
+        }
+        if (regaddr == RTXAGC_B_RATE54_24) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][9]));
+        }
+
+        if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][14]));
+        }
+
+        if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][15]));
+        }
+
+        if (regaddr == RTXAGC_B_MCS03_MCS00) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][10]));
+        }
+
+        if (regaddr == RTXAGC_B_MCS07_MCS04) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][11]));
+        }
+
+        if (regaddr == RTXAGC_B_MCS11_MCS08) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][12]));
+        }
+
+        if (regaddr == RTXAGC_B_MCS15_MCS12) {
+                rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
+                    data;
+
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
+                          rtlphy->pwrgroup_cnt,
+                          rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
+                                                            pwrgroup_cnt][13]));
+
+                rtlphy->pwrgroup_cnt++;
+        }
+}
+
+static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
+                                                    u8 configtype)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        int i;
+        u32 *phy_regarray_table_pg;
+        u16 phy_regarray_pg_len;
+
+        phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
+        phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
+
+        if (configtype == BASEBAND_CONFIG_PHY_REG) {
+                for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
+                        if (phy_regarray_table_pg[i] == 0xfe)
+                                mdelay(50);
+                        else if (phy_regarray_table_pg[i] == 0xfd)
+                                mdelay(5);
+                        else if (phy_regarray_table_pg[i] == 0xfc)
+                                mdelay(1);
+                        else if (phy_regarray_table_pg[i] == 0xfb)
+                                udelay(50);
+                        else if (phy_regarray_table_pg[i] == 0xfa)
+                                udelay(5);
+                        else if (phy_regarray_table_pg[i] == 0xf9)
+                                udelay(1);
+
+                        _rtl92c_store_pwrIndex_diffrate_offset(hw,
+                                               phy_regarray_table_pg[i],
+                                               phy_regarray_table_pg[i + 1],
+                                               phy_regarray_table_pg[i + 2]);
+                }
+        } else {
+
+                RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
+                         ("configtype != BaseBand_Config_PHY_REG\n"));
+        }
+        return true;
+}
+
+static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
+                                              enum radio_path rfpath)
+{
+        return true;
+}
+
+bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
+                                          enum radio_path rfpath)
+{
+
+        int i;
+        bool rtstatus = true;
+        u32 *radioa_array_table;
+        u32 *radiob_array_table;
+        u16 radioa_arraylen, radiob_arraylen;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (IS_92C_SERIAL(rtlhal->version)) {
+                radioa_arraylen = RADIOA_2TARRAYLENGTH;
+                radioa_array_table = RTL8192CERADIOA_2TARRAY;
+                radiob_arraylen = RADIOB_2TARRAYLENGTH;
+                radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
+        } else {
+                radioa_arraylen = RADIOA_1TARRAYLENGTH;
+                radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
+                radiob_arraylen = RADIOB_1TARRAYLENGTH;
+                radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
+                RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                         ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
+        }
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
+        rtstatus = true;
+        switch (rfpath) {
+        case RF90_PATH_A:
+                for (i = 0; i < radioa_arraylen; i = i + 2) {
+                        if (radioa_array_table[i] == 0xfe)
+                                mdelay(50);
+                        else if (radioa_array_table[i] == 0xfd)
+                                mdelay(5);
+                        else if (radioa_array_table[i] == 0xfc)
+                                mdelay(1);
+                        else if (radioa_array_table[i] == 0xfb)
+                                udelay(50);
+                        else if (radioa_array_table[i] == 0xfa)
+                                udelay(5);
+                        else if (radioa_array_table[i] == 0xf9)
+                                udelay(1);
+                        else {
+                                rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
+                                              RFREG_OFFSET_MASK,
+                                              radioa_array_table[i + 1]);
+                                udelay(1);
+                        }
+                }
+                _rtl92c_phy_config_rf_external_pa(hw, rfpath);
+                break;
+        case RF90_PATH_B:
+                for (i = 0; i < radiob_arraylen; i = i + 2) {
+                        if (radiob_array_table[i] == 0xfe) {
+                                mdelay(50);
+                        } else if (radiob_array_table[i] == 0xfd)
+                                mdelay(5);
+                        else if (radiob_array_table[i] == 0xfc)
+                                mdelay(1);
+                        else if (radiob_array_table[i] == 0xfb)
+                                udelay(50);
+                        else if (radiob_array_table[i] == 0xfa)
+                                udelay(5);
+                        else if (radiob_array_table[i] == 0xf9)
+                                udelay(1);
+                        else {
+                                rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
+                                              RFREG_OFFSET_MASK,
+                                              radiob_array_table[i + 1]);
+                                udelay(1);
+                        }
+                }
+                break;
+        case RF90_PATH_C:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        case RF90_PATH_D:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+        return true;
+}
+
+void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        rtlphy->default_initialgain[0] =
+            (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
+        rtlphy->default_initialgain[1] =
+            (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
+        rtlphy->default_initialgain[2] =
+            (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
+        rtlphy->default_initialgain[3] =
+            (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                 ("Default initial gain (c50=0x%x, "
+                  "c58=0x%x, c60=0x%x, c68=0x%x\n",
+                  rtlphy->default_initialgain[0],
+                  rtlphy->default_initialgain[1],
+                  rtlphy->default_initialgain[2],
+                  rtlphy->default_initialgain[3]));
+
+        rtlphy->framesync = (u8) rtl_get_bbreg(hw,
+                                               ROFDM0_RXDETECTOR3, MASKBYTE0);
+        rtlphy->framesync_c34 = rtl_get_bbreg(hw,
+                                              ROFDM0_RXDETECTOR2, MASKDWORD);
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                 ("Default framesync (0x%x) = 0x%x\n",
+                  ROFDM0_RXDETECTOR3, rtlphy->framesync));
+}
+
+static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
+        rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
+        rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
+        rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
+        rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
+        rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
+        rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
+        rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
+        rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
+            RFPGA0_XA_LSSIPARAMETER;
+        rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
+            RFPGA0_XB_LSSIPARAMETER;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
+        rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
+        rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
+        rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
+        rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
+        rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
+        rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
+        rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
+        rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
+            RFPGA0_XAB_SWITCHCONTROL;
+        rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
+            RFPGA0_XAB_SWITCHCONTROL;
+        rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
+            RFPGA0_XCD_SWITCHCONTROL;
+        rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
+            RFPGA0_XCD_SWITCHCONTROL;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
+        rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
+        rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
+        rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
+        rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
+        rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
+        rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
+            ROFDM0_XARXIQIMBALANCE;
+        rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
+            ROFDM0_XBRXIQIMBALANCE;
+        rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
+            ROFDM0_XCRXIQIMBANLANCE;
+        rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
+            ROFDM0_XDRXIQIMBALANCE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
+        rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
+        rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
+        rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
+            ROFDM0_XATXIQIMBALANCE;
+        rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
+            ROFDM0_XBTXIQIMBALANCE;
+        rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
+            ROFDM0_XCTXIQIMBALANCE;
+        rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
+            ROFDM0_XDTXIQIMBALANCE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
+        rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
+        rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
+        rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
+            RFPGA0_XA_LSSIREADBACK;
+        rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
+            RFPGA0_XB_LSSIREADBACK;
+        rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
+            RFPGA0_XC_LSSIREADBACK;
+        rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
+            RFPGA0_XD_LSSIREADBACK;
+
+        rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
+            TRANSCEIVEA_HSPI_READBACK;
+        rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
+            TRANSCEIVEB_HSPI_READBACK;
+
+}
+
+void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 txpwr_level;
+        long txpwr_dbm;
+
+        txpwr_level = rtlphy->cur_cck_txpwridx;
+        txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
+                                                 WIRELESS_MODE_B, txpwr_level);
+        txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
+            rtlefuse->legacy_ht_txpowerdiff;
+        if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
+                                         WIRELESS_MODE_G,
+                                         txpwr_level) > txpwr_dbm)
+                txpwr_dbm =
+                    _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
+                                                 txpwr_level);
+        txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
+        if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
+                                         WIRELESS_MODE_N_24G,
+                                         txpwr_level) > txpwr_dbm)
+                txpwr_dbm =
+                    _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
+                                                 txpwr_level);
+        *powerlevel = txpwr_dbm;
+}
+
+static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
+                                      u8 *cckpowerlevel, u8 *ofdmpowerlevel)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 index = (channel - 1);
+
+        cckpowerlevel[RF90_PATH_A] =
+            rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
+        cckpowerlevel[RF90_PATH_B] =
+            rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
+        if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
+                ofdmpowerlevel[RF90_PATH_A] =
+                    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
+                ofdmpowerlevel[RF90_PATH_B] =
+                    rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
+        } else if (get_rf_type(rtlphy) == RF_2T2R) {
+                ofdmpowerlevel[RF90_PATH_A] =
+                    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
+                ofdmpowerlevel[RF90_PATH_B] =
+                    rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
+        }
+}
+
+static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
+                                         u8 channel, u8 *cckpowerlevel,
+                                         u8 *ofdmpowerlevel)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
+        rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
+}
+
+void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
+{
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 cckpowerlevel[2], ofdmpowerlevel[2];
+
+        if (rtlefuse->b_txpwr_fromeprom == false)
+                return;
+        _rtl92c_get_txpower_index(hw, channel,
+                                  &cckpowerlevel[0], &ofdmpowerlevel[0]);
+        _rtl92c_ccxpower_index_check(hw,
+                                     channel, &cckpowerlevel[0],
+                                     &ofdmpowerlevel[0]);
+        rtl92c_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
+        rtl92c_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
+}
+
+bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 idx;
+        u8 rf_path;
+
+        u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
+                                                      WIRELESS_MODE_B,
+                                                      power_indbm);
+        u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
+                                                       WIRELESS_MODE_N_24G,
+                                                       power_indbm);
+        if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
+                ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
+        else
+                ofdmtxpwridx = 0;
+        RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
+                 ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
+                  power_indbm, ccktxpwridx, ofdmtxpwridx));
+        for (idx = 0; idx < 14; idx++) {
+                for (rf_path = 0; rf_path < 2; rf_path++) {
+                        rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
+                        rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
+                            ofdmtxpwridx;
+                        rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
+                            ofdmtxpwridx;
+                }
+        }
+        rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
+        return true;
+}
+
+void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval)
+{
+}
+
+static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
+                                       enum wireless_mode wirelessmode,
+                                       long power_indbm)
+{
+        u8 txpwridx;
+        long offset;
+
+        switch (wirelessmode) {
+        case WIRELESS_MODE_B:
+                offset = -7;
+                break;
+        case WIRELESS_MODE_G:
+        case WIRELESS_MODE_N_24G:
+                offset = -8;
+                break;
+        default:
+                offset = -8;
+                break;
+        }
+
+        if ((power_indbm - offset) > 0)
+                txpwridx = (u8) ((power_indbm - offset) * 2);
+        else
+                txpwridx = 0;
+
+        if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
+                txpwridx = MAX_TXPWR_IDX_NMODE_92S;
+
+        return txpwridx;
+}
+
+static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
+                                         enum wireless_mode wirelessmode,
+                                         u8 txpwridx)
+{
+        long offset;
+        long pwrout_dbm;
+
+        switch (wirelessmode) {
+        case WIRELESS_MODE_B:
+                offset = -7;
+                break;
+        case WIRELESS_MODE_G:
+        case WIRELESS_MODE_N_24G:
+                offset = -8;
+                break;
+        default:
+                offset = -8;
+                break;
+        }
+        pwrout_dbm = txpwridx / 2 + offset;
+        return pwrout_dbm;
+}
+
+void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        enum io_type iotype;
+
+        if (!is_hal_stop(rtlhal)) {
+                switch (operation) {
+                case SCAN_OPT_BACKUP:
+                        iotype = IO_CMD_PAUSE_DM_BY_SCAN;
+                        rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                      HW_VAR_IO_CMD,
+                                                      (u8 *)&iotype);
+
+                        break;
+                case SCAN_OPT_RESTORE:
+                        iotype = IO_CMD_RESUME_DM_BY_SCAN;
+                        rtlpriv->cfg->ops->set_hw_reg(hw,
+                                                      HW_VAR_IO_CMD,
+                                                      (u8 *)&iotype);
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("Unknown Scan Backup operation.\n"));
+                        break;
+                }
+        }
+}
+
+void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        u8 reg_bw_opmode;
+        u8 reg_prsr_rsc;
+
+        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
+                 ("Switch to %s bandwidth\n",
+                  rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
+                  "20MHz" : "40MHz"))
+
+            if (is_hal_stop(rtlhal))
+                return;
+
+        reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
+        reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
+
+        switch (rtlphy->current_chan_bw) {
+        case HT_CHANNEL_WIDTH_20:
+                reg_bw_opmode |= BW_OPMODE_20MHZ;
+                rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
+                break;
+
+        case HT_CHANNEL_WIDTH_20_40:
+                reg_bw_opmode &= ~BW_OPMODE_20MHZ;
+                rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
+
+                reg_prsr_rsc =
+                    (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
+                rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
+                break;
+
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
+                break;
+        }
+
+        switch (rtlphy->current_chan_bw) {
+        case HT_CHANNEL_WIDTH_20:
+                rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
+                rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
+                rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
+                break;
+        case HT_CHANNEL_WIDTH_20_40:
+                rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
+                rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
+                rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
+                              (mac->cur_40_prime_sc >> 1));
+                rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
+                rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
+                rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
+                              (mac->cur_40_prime_sc ==
+                               HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
+                break;
+        }
+        rtl92c_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
+        rtlphy->set_bwmode_inprogress = false;
+        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
+}
+
+void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
+                            enum nl80211_channel_type ch_type)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u8 tmp_bw = rtlphy->current_chan_bw;
+
+        if (rtlphy->set_bwmode_inprogress)
+                return;
+        rtlphy->set_bwmode_inprogress = true;
+        if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
+                rtl92c_phy_set_bw_mode_callback(hw);
+        else {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                         ("FALSE driver sleep or unload\n"));
+                rtlphy->set_bwmode_inprogress = false;
+                rtlphy->current_chan_bw = tmp_bw;
+        }
+}
+
+void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        u32 delay;
+
+        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
+                 ("switch to channel%d\n", rtlphy->current_channel));
+        if (is_hal_stop(rtlhal))
+                return;
+        do {
+                if (!rtlphy->sw_chnl_inprogress)
+                        break;
+                if (!_rtl92c_phy_sw_chnl_step_by_step
+                    (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
+                     &rtlphy->sw_chnl_step, &delay)) {
+                        if (delay > 0)
+                                mdelay(delay);
+                        else
+                                continue;
+                } else
+                        rtlphy->sw_chnl_inprogress = false;
+                break;
+        } while (true);
+        RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
+}
+
+u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (rtlphy->sw_chnl_inprogress)
+                return 0;
+        if (rtlphy->set_bwmode_inprogress)
+                return 0;
+        RT_ASSERT((rtlphy->current_channel <= 14),
+                  ("WIRELESS_MODE_G but channel>14"));
+        rtlphy->sw_chnl_inprogress = true;
+        rtlphy->sw_chnl_stage = 0;
+        rtlphy->sw_chnl_step = 0;
+        if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
+                rtl92c_phy_sw_chnl_callback(hw);
+                RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
+                         ("sw_chnl_inprogress false schdule workitem\n"));
+                rtlphy->sw_chnl_inprogress = false;
+        } else {
+                RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
+                         ("sw_chnl_inprogress false driver sleep or"
+                          " unload\n"));
+                rtlphy->sw_chnl_inprogress = false;
+        }
+        return 1;
+}
+
+static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
+                                             u8 channel, u8 *stage, u8 *step,
+                                             u32 *delay)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
+        u32 precommoncmdcnt;
+        struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
+        u32 postcommoncmdcnt;
+        struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
+        u32 rfdependcmdcnt;
+        struct swchnlcmd *currentcmd = NULL;
+        u8 rfpath;
+        u8 num_total_rfpath = rtlphy->num_total_rfpath;
+
+        precommoncmdcnt = 0;
+        _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
+                                         MAX_PRECMD_CNT,
+                                         CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
+        _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
+                                         MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
+
+        postcommoncmdcnt = 0;
+
+        _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
+                                         MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
+
+        rfdependcmdcnt = 0;
+
+        RT_ASSERT((channel >= 1 && channel <= 14),
+                  ("illegal channel for Zebra: %d\n", channel));
+
+        _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
+                                         MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
+                                         RF_CHNLBW, channel, 10);
+
+        _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
+                                         MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
+                                         0);
+
+        do {
+                switch (*stage) {
+                case 0:
+                        currentcmd = &precommoncmd[*step];
+                        break;
+                case 1:
+                        currentcmd = &rfdependcmd[*step];
+                        break;
+                case 2:
+                        currentcmd = &postcommoncmd[*step];
+                        break;
+                }
+
+                if (currentcmd->cmdid == CMDID_END) {
+                        if ((*stage) == 2) {
+                                return true;
+                        } else {
+                                (*stage)++;
+                                (*step) = 0;
+                                continue;
+                        }
+                }
+
+                switch (currentcmd->cmdid) {
+                case CMDID_SET_TXPOWEROWER_LEVEL:
+                        rtl92c_phy_set_txpower_level(hw, channel);
+                        break;
+                case CMDID_WRITEPORT_ULONG:
+                        rtl_write_dword(rtlpriv, currentcmd->para1,
+                                        currentcmd->para2);
+                        break;
+                case CMDID_WRITEPORT_USHORT:
+                        rtl_write_word(rtlpriv, currentcmd->para1,
+                                       (u16) currentcmd->para2);
+                        break;
+                case CMDID_WRITEPORT_UCHAR:
+                        rtl_write_byte(rtlpriv, currentcmd->para1,
+                                       (u8) currentcmd->para2);
+                        break;
+                case CMDID_RF_WRITEREG:
+                        for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
+                                rtlphy->rfreg_chnlval[rfpath] =
+                                    ((rtlphy->rfreg_chnlval[rfpath] &
+                                      0xfffffc00) | currentcmd->para2);
+
+                                rtl_set_rfreg(hw, (enum radio_path)rfpath,
+                                              currentcmd->para1,
+                                              RFREG_OFFSET_MASK,
+                                              rtlphy->rfreg_chnlval[rfpath]);
+                        }
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("switch case not process\n"));
+                        break;
+                }
+
+                break;
+        } while (true);
+
+        (*delay) = currentcmd->msdelay;
+        (*step)++;
+        return false;
+}
+
+static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
+                                             u32 cmdtableidx, u32 cmdtablesz,
+                                             enum swchnlcmd_id cmdid,
+                                             u32 para1, u32 para2, u32 msdelay)
+{
+        struct swchnlcmd *pcmd;
+
+        if (cmdtable == NULL) {
+                RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
+                return false;
+        }
+
+        if (cmdtableidx >= cmdtablesz)
+                return false;
+
+        pcmd = cmdtable + cmdtableidx;
+        pcmd->cmdid = cmdid;
+        pcmd->para1 = para1;
+        pcmd->para2 = para2;
+        pcmd->msdelay = msdelay;
+        return true;
+}
+
+bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
+{
+        return true;
+}
+
+static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
+{
+        u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
+        u8 result = 0x00;
+
+        rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
+        rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
+        rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
+        rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
+                      config_pathb ? 0x28160202 : 0x28160502);
+
+        if (config_pathb) {
+                rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
+                rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
+                rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
+                rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
+        }
+
+        rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
+        rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
+        rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
+
+        mdelay(IQK_DELAY_TIME);
+
+        reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
+        reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
+        reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
+        reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
+
+        if (!(reg_eac & BIT(28)) &&
+            (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
+            (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
+                result |= 0x01;
+        else
+                return result;
+
+        if (!(reg_eac & BIT(27)) &&
+            (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
+            (((reg_eac & 0x03FF0000) >> 16) != 0x36))
+                result |= 0x02;
+        return result;
+}
+
+static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
+{
+        u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
+        u8 result = 0x00;
+
+        rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
+        rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
+        mdelay(IQK_DELAY_TIME);
+        reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
+        reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
+        reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
+        reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
+        reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
+        if (!(reg_eac & BIT(31)) &&
+            (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
+            (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
+                result |= 0x01;
+        else
+                return result;
+
+        if (!(reg_eac & BIT(30)) &&
+            (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
+            (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
+                result |= 0x02;
+        return result;
+}
+
+static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
+                                               bool b_iqk_ok, long result[][8],
+                                               u8 final_candidate, bool btxonly)
+{
+        u32 oldval_0, x, tx0_a, reg;
+        long y, tx0_c;
+
+        if (final_candidate == 0xFF)
+                return;
+        else if (b_iqk_ok) {
+                oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
+                                          MASKDWORD) >> 22) & 0x3FF;
+                x = result[final_candidate][0];
+                if ((x & 0x00000200) != 0)
+                        x = x | 0xFFFFFC00;
+                tx0_a = (x * oldval_0) >> 8;
+                rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
+                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
+                              ((x * oldval_0 >> 7) & 0x1));
+                y = result[final_candidate][1];
+                if ((y & 0x00000200) != 0)
+                        y = y | 0xFFFFFC00;
+                tx0_c = (y * oldval_0) >> 8;
+                rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
+                              ((tx0_c & 0x3C0) >> 6));
+                rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
+                              (tx0_c & 0x3F));
+                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
+                              ((y * oldval_0 >> 7) & 0x1));
+                if (btxonly)
+                        return;
+                reg = result[final_candidate][2];
+                rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
+                reg = result[final_candidate][3] & 0x3F;
+                rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
+                reg = (result[final_candidate][3] >> 6) & 0xF;
+                rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
+        }
+}
+
+static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
+                                               bool b_iqk_ok, long result[][8],
+                                               u8 final_candidate, bool btxonly)
+{
+        u32 oldval_1, x, tx1_a, reg;
+        long y, tx1_c;
+
+        if (final_candidate == 0xFF)
+                return;
+        else if (b_iqk_ok) {
+                oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
+                                          MASKDWORD) >> 22) & 0x3FF;
+                x = result[final_candidate][4];
+                if ((x & 0x00000200) != 0)
+                        x = x | 0xFFFFFC00;
+                tx1_a = (x * oldval_1) >> 8;
+                rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
+                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
+                              ((x * oldval_1 >> 7) & 0x1));
+                y = result[final_candidate][5];
+                if ((y & 0x00000200) != 0)
+                        y = y | 0xFFFFFC00;
+                tx1_c = (y * oldval_1) >> 8;
+                rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
+                              ((tx1_c & 0x3C0) >> 6));
+                rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
+                              (tx1_c & 0x3F));
+                rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
+                              ((y * oldval_1 >> 7) & 0x1));
+                if (btxonly)
+                        return;
+                reg = result[final_candidate][6];
+                rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
+                reg = result[final_candidate][7] & 0x3F;
+                rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
+                reg = (result[final_candidate][7] >> 6) & 0xF;
+                rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
+        }
+}
+
+static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
+                                            u32 *addareg, u32 *addabackup,
+                                            u32 registernum)
+{
+        u32 i;
+
+        for (i = 0; i < registernum; i++)
+                addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
+}
+
+static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
+                                           u32 *macreg, u32 *macbackup)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 i;
+
+        for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
+                macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
+        macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
+}
+
+static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
+                                              u32 *addareg, u32 *addabackup,
+                                              u32 regiesternum)
+{
+        u32 i;
+
+        for (i = 0; i < regiesternum; i++)
+                rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
+}
+
+static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
+                                             u32 *macreg, u32 *macbackup)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 i;
+
+        for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
+                rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
+        rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
+}
+
+static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
+                                     u32 *addareg, bool is_patha_on, bool is2t)
+{
+        u32 pathOn;
+        u32 i;
+
+        pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
+        if (false == is2t) {
+                pathOn = 0x0bdb25a0;
+                rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
+        } else {
+                rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
+        }
+
+        for (i = 1; i < IQK_ADDA_REG_NUM; i++)
+                rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
+}
+
+static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
+                                                u32 *macreg, u32 *macbackup)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 i;
+
+        rtl_write_byte(rtlpriv, macreg[0], 0x3F);
+
+        for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
+                rtl_write_byte(rtlpriv, macreg[i],
+                               (u8) (macbackup[i] & (~BIT(3))));
+        rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
+}
+
+static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
+{
+        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
+        rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
+        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
+}
+
+static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
+{
+        u32 mode;
+
+        mode = pi_mode ? 0x01000100 : 0x01000000;
+        rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
+        rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
+}
+
+static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
+                                           long result[][8], u8 c1, u8 c2)
+{
+        u32 i, j, diff, simularity_bitmap, bound;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        u8 final_candidate[2] = { 0xFF, 0xFF };
+        bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
+
+        if (is2t)
+                bound = 8;
+        else
+                bound = 4;
+
+        simularity_bitmap = 0;
+
+        for (i = 0; i < bound; i++) {
+                diff = (result[c1][i] > result[c2][i]) ?
+                    (result[c1][i] - result[c2][i]) :
+                    (result[c2][i] - result[c1][i]);
+
+                if (diff > MAX_TOLERANCE) {
+                        if ((i == 2 || i == 6) && !simularity_bitmap) {
+                                if (result[c1][i] + result[c1][i + 1] == 0)
+                                        final_candidate[(i / 4)] = c2;
+                                else if (result[c2][i] + result[c2][i + 1] == 0)
+                                        final_candidate[(i / 4)] = c1;
+                                else
+                                        simularity_bitmap = simularity_bitmap |
+                                            (1 << i);
+                        } else
+                                simularity_bitmap =
+                                    simularity_bitmap | (1 << i);
+                }
+        }
+
+        if (simularity_bitmap == 0) {
+                for (i = 0; i < (bound / 4); i++) {
+                        if (final_candidate[i] != 0xFF) {
+                                for (j = i * 4; j < (i + 1) * 4 - 2; j++)
+                                        result[3][j] =
+                                            result[final_candidate[i]][j];
+                                bresult = false;
+                        }
+                }
+                return bresult;
+        } else if (!(simularity_bitmap & 0x0F)) {
+                for (i = 0; i < 4; i++)
+                        result[3][i] = result[c1][i];
+                return false;
+        } else if (!(simularity_bitmap & 0xF0) && is2t) {
+                for (i = 4; i < 8; i++)
+                        result[3][i] = result[c1][i];
+                return false;
+        } else {
+                return false;
+        }
+
+}
+
+static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
+                                     long result[][8], u8 t, bool is2t)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        u32 i;
+        u8 patha_ok, pathb_ok;
+        u32 adda_reg[IQK_ADDA_REG_NUM] = {
+                0x85c, 0xe6c, 0xe70, 0xe74,
+                0xe78, 0xe7c, 0xe80, 0xe84,
+                0xe88, 0xe8c, 0xed0, 0xed4,
+                0xed8, 0xedc, 0xee0, 0xeec
+        };
+
+        u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
+                0x522, 0x550, 0x551, 0x040
+        };
+
+        const u32 retrycount = 2;
+
+        u32 bbvalue;
+
+        if (t == 0) {
+                bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
+
+                _rtl92c_phy_save_adda_registers(hw, adda_reg,
+                                                rtlphy->adda_backup, 16);
+                _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
+                                               rtlphy->iqk_mac_backup);
+        }
+        _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
+        if (t == 0) {
+                rtlphy->b_rfpi_enable = (u8) rtl_get_bbreg(hw,
+                                                   RFPGA0_XA_HSSIPARAMETER1,
+                                                   BIT(8));
+        }
+        if (!rtlphy->b_rfpi_enable)
+                _rtl92c_phy_pi_mode_switch(hw, true);
+        if (t == 0) {
+                rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
+                rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
+                rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
+        }
+        rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
+        rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
+        rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
+        if (is2t) {
+                rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
+                rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
+        }
+        _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
+                                            rtlphy->iqk_mac_backup);
+        rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
+        if (is2t)
+                rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
+        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
+        rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
+        rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
+        for (i = 0; i < retrycount; i++) {
+                patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
+                if (patha_ok == 0x03) {
+                        result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
+                                        0x3FF0000) >> 16;
+                        result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
+                                        0x3FF0000) >> 16;
+                        result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
+                                        0x3FF0000) >> 16;
+                        result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
+                                        0x3FF0000) >> 16;
+                        break;
+                } else if (i == (retrycount - 1) && patha_ok == 0x01)
+                        result[t][0] = (rtl_get_bbreg(hw, 0xe94,
+                                                      MASKDWORD) & 0x3FF0000) >>
+                                                      16;
+                result[t][1] =
+                    (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
+
+        }
+
+        if (is2t) {
+                _rtl92c_phy_path_a_standby(hw);
+                _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
+                for (i = 0; i < retrycount; i++) {
+                        pathb_ok = _rtl92c_phy_path_b_iqk(hw);
+                        if (pathb_ok == 0x03) {
+                                result[t][4] = (rtl_get_bbreg(hw,
+                                                      0xeb4,
+                                                      MASKDWORD) &
+                                                0x3FF0000) >> 16;
+                                result[t][5] =
+                                    (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
+                                     0x3FF0000) >> 16;
+                                result[t][6] =
+                                    (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
+                                     0x3FF0000) >> 16;
+                                result[t][7] =
+                                    (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
+                                     0x3FF0000) >> 16;
+                                break;
+                        } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
+                                result[t][4] = (rtl_get_bbreg(hw,
+                                                      0xeb4,
+                                                      MASKDWORD) &
+                                                0x3FF0000) >> 16;
+                        }
+                        result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
+                                        0x3FF0000) >> 16;
+                }
+        }
+        rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
+        rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
+        rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
+        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
+        rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
+        if (is2t)
+                rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
+        if (t != 0) {
+                if (!rtlphy->b_rfpi_enable)
+                        _rtl92c_phy_pi_mode_switch(hw, false);
+                _rtl92c_phy_reload_adda_registers(hw, adda_reg,
+                                                  rtlphy->adda_backup, 16);
+                _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
+                                                 rtlphy->iqk_mac_backup);
+        }
+}
+
+static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
+{
+        u8 tmpreg;
+        u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        tmpreg = rtl_read_byte(rtlpriv, 0xd03);
+
+        if ((tmpreg & 0x70) != 0)
+                rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
+        else
+                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
+
+        if ((tmpreg & 0x70) != 0) {
+                rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
+
+                if (is2t)
+                        rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
+                                                  MASK12BITS);
+
+                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
+                              (rf_a_mode & 0x8FFFF) | 0x10000);
+
+                if (is2t)
+                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
+                                      (rf_b_mode & 0x8FFFF) | 0x10000);
+        }
+        lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
+
+        rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
+
+        mdelay(100);
+
+        if ((tmpreg & 0x70) != 0) {
+                rtl_write_byte(rtlpriv, 0xd03, tmpreg);
+                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
+
+                if (is2t)
+                        rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
+                                      rf_b_mode);
+        } else {
+                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
+        }
+}
+
+static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
+                                     char delta, bool is2t)
+{
+        /* This routine is deliberately dummied out for later fixes */
+#if 0
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        u32 reg_d[PATH_NUM];
+        u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
+
+        u32 bb_backup[APK_BB_REG_NUM];
+        u32 bb_reg[APK_BB_REG_NUM] = {
+                0x904, 0xc04, 0x800, 0xc08, 0x874
+        };
+        u32 bb_ap_mode[APK_BB_REG_NUM] = {
+                0x00000020, 0x00a05430, 0x02040000,
+                0x000800e4, 0x00204000
+        };
+        u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
+                0x00000020, 0x00a05430, 0x02040000,
+                0x000800e4, 0x22204000
+        };
+
+        u32 afe_backup[APK_AFE_REG_NUM];
+        u32 afe_reg[APK_AFE_REG_NUM] = {
+                0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
+                0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
+                0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
+                0xeec
+        };
+
+        u32 mac_backup[IQK_MAC_REG_NUM];
+        u32 mac_reg[IQK_MAC_REG_NUM] = {
+                0x522, 0x550, 0x551, 0x040
+        };
+
+        u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
+                {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
+                {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
+        };
+
+        u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
+                {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
+                {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
+        };
+
+        u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
+                {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
+                {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
+        };
+
+        u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
+                {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
+                {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
+        };
+
+        u32 afe_on_off[PATH_NUM] = {
+                0x04db25a4, 0x0b1b25a4
+        };
+
+        u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
+
+        u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
+
+        u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
+
+        u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
+
+        const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
+                {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+                {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+                {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+                {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
+                {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
+        };
+
+        const u32 apk_normal_setting_value_1[13] = {
+                0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
+                0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
+                0x12680000, 0x00880000, 0x00880000
+        };
+
+        const u32 apk_normal_setting_value_2[16] = {
+                0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
+                0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
+                0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
+                0x00050006
+        };
+
+        const u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
+
+        long bb_offset, delta_v, delta_offset;
+
+        if (!is2t)
+                pathbound = 1;
+
+        for (index = 0; index < PATH_NUM; index++) {
+                apk_offset[index] = apk_normal_offset[index];
+                apk_value[index] = apk_normal_value[index];
+                afe_on_off[index] = 0x6fdb25a4;
+        }
+
+        for (index = 0; index < APK_BB_REG_NUM; index++) {
+                for (path = 0; path < pathbound; path++) {
+                        apk_rf_init_value[path][index] =
+                            apk_normal_rf_init_value[path][index];
+                        apk_rf_value_0[path][index] =
+                            apk_normal_rf_value_0[path][index];
+                }
+                bb_ap_mode[index] = bb_normal_ap_mode[index];
+
+                apkbound = 6;
+        }
+
+        for (index = 0; index < APK_BB_REG_NUM; index++) {
+                if (index == 0)
+                        continue;
+                bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
+        }
+
+        _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
+
+        _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
+
+        for (path = 0; path < pathbound; path++) {
+                if (path == RF90_PATH_A) {
+                        offset = 0xb00;
+                        for (index = 0; index < 11; index++) {
+                                rtl_set_bbreg(hw, offset, MASKDWORD,
+                                              apk_normal_setting_value_1
+                                              [index]);
+
+                                offset += 0x04;
+                        }
+
+                        rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
+
+                        offset = 0xb68;
+                        for (; index < 13; index++) {
+                                rtl_set_bbreg(hw, offset, MASKDWORD,
+                                              apk_normal_setting_value_1
+                                              [index]);
+
+                                offset += 0x04;
+                        }
+
+                        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
+
+                        offset = 0xb00;
+                        for (index = 0; index < 16; index++) {
+                                rtl_set_bbreg(hw, offset, MASKDWORD,
+                                              apk_normal_setting_value_2
+                                              [index]);
+
+                                offset += 0x04;
+                        }
+                        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
+                } else if (path == RF90_PATH_B) {
+                        offset = 0xb70;
+                        for (index = 0; index < 10; index++) {
+                                rtl_set_bbreg(hw, offset, MASKDWORD,
+                                              apk_normal_setting_value_1
+                                              [index]);
+
+                                offset += 0x04;
+                        }
+                        rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
+                        rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
+
+                        offset = 0xb68;
+                        index = 11;
+                        for (; index < 13; index++) {
+                                rtl_set_bbreg(hw, offset, MASKDWORD,
+                                              apk_normal_setting_value_1
+                                              [index]);
+
+                                offset += 0x04;
+                        }
+
+                        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
+
+                        offset = 0xb60;
+                        for (index = 0; index < 16; index++) {
+                                rtl_set_bbreg(hw, offset, MASKDWORD,
+                                              apk_normal_setting_value_2
+                                              [index]);
+
+                                offset += 0x04;
+                        }
+                        rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
+                }
+
+                reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
+                                            0xd, MASKDWORD);
+
+                for (index = 0; index < APK_AFE_REG_NUM; index++)
+                        rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
+                                      afe_on_off[path]);
+
+                if (path == RF90_PATH_A) {
+                        for (index = 0; index < APK_BB_REG_NUM; index++) {
+                                if (index == 0)
+                                        continue;
+                                rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
+                                              bb_ap_mode[index]);
+                        }
+                }
+
+                _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
+
+                if (path == 0) {
+                        rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
+                } else {
+                        rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
+                                      0x10000);
+                        rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
+                                      0x1000f);
+                        rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
+                                      0x20103);
+                }
+
+                delta_offset = ((delta + 14) / 2);
+                if (delta_offset < 0)
+                        delta_offset = 0;
+                else if (delta_offset > 12)
+                        delta_offset = 12;
+
+                for (index = 0; index < APK_BB_REG_NUM; index++) {
+                        if (index != 1)
+                                continue;
+
+                        tmpreg = apk_rf_init_value[path][index];
+
+                        if (!rtlefuse->b_apk_thermalmeterignore) {
+                                bb_offset = (tmpreg & 0xF0000) >> 16;
+
+                                if (!(tmpreg & BIT(15)))
+                                        bb_offset = -bb_offset;
+
+                                delta_v =
+                                    apk_delta_mapping[index][delta_offset];
+
+                                bb_offset += delta_v;
+
+                                if (bb_offset < 0) {
+                                        tmpreg = tmpreg & (~BIT(15));
+                                        bb_offset = -bb_offset;
+                                } else {
+                                        tmpreg = tmpreg | BIT(15);
+                                }
+
+                                tmpreg =
+                                    (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
+                        }
+
+                        rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
+                                      MASKDWORD, 0x8992e);
+                        rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
+                                      MASKDWORD, apk_rf_value_0[path][index]);
+                        rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
+                                      MASKDWORD, tmpreg);
+
+                        i = 0;
+                        do {
+                                rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
+                                rtl_set_bbreg(hw, apk_offset[path],
+                                              MASKDWORD, apk_value[0]);
+                                RTPRINT(rtlpriv, FINIT, INIT_IQK,
+                                        ("PHY_APCalibrate() offset 0x%x "
+                                         "value 0x%x\n",
+                                         apk_offset[path],
+                                         rtl_get_bbreg(hw, apk_offset[path],
+                                                       MASKDWORD)));
+
+                                mdelay(3);
+
+                                rtl_set_bbreg(hw, apk_offset[path],
+                                              MASKDWORD, apk_value[1]);
+                                RTPRINT(rtlpriv, FINIT, INIT_IQK,
+                                        ("PHY_APCalibrate() offset 0x%x "
+                                         "value 0x%x\n",
+                                         apk_offset[path],
+                                         rtl_get_bbreg(hw, apk_offset[path],
+                                                       MASKDWORD)));
+
+                                mdelay(20);
+
+                                rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
+
+                                if (path == RF90_PATH_A)
+                                        tmpreg = rtl_get_bbreg(hw, 0xbd8,
+                                                               0x03E00000);
+                                else
+                                        tmpreg = rtl_get_bbreg(hw, 0xbd8,
+                                                               0xF8000000);
+
+                                RTPRINT(rtlpriv, FINIT, INIT_IQK,
+                                        ("PHY_APCalibrate() offset "
+                                         "0xbd8[25:21] %x\n", tmpreg));
+
+                                i++;
+
+                        } while (tmpreg > apkbound && i < 4);
+
+                        apk_result[path][index] = tmpreg;
+                }
+        }
+
+        _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
+
+        for (index = 0; index < APK_BB_REG_NUM; index++) {
+                if (index == 0)
+                        continue;
+                rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
+        }
+
+        _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
+
+        for (path = 0; path < pathbound; path++) {
+                rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
+                              MASKDWORD, reg_d[path]);
+
+                if (path == RF90_PATH_B) {
+                        rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
+                                      0x1000f);
+                        rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
+                                      0x20101);
+                }
+
+                if (apk_result[path][1] > 6)
+                        apk_result[path][1] = 6;
+        }
+
+        for (path = 0; path < pathbound; path++) {
+                rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
+                              ((apk_result[path][1] << 15) |
+                               (apk_result[path][1] << 10) |
+                               (apk_result[path][1] << 5) |
+                               apk_result[path][1]));
+
+                if (path == RF90_PATH_A)
+                        rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
+                                      ((apk_result[path][1] << 15) |
+                                       (apk_result[path][1] << 10) |
+                                       (0x00 << 5) | 0x05));
+                else
+                        rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
+                                      ((apk_result[path][1] << 15) |
+                                       (apk_result[path][1] << 10) |
+                                       (0x02 << 5) | 0x05));
+
+                rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
+                              ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
+                               0x08));
+
+        }
+
+        rtlphy->b_apk_done = true;
+#endif
+}
+
+static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
+                                          bool bmain, bool is2t)
+{
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (is_hal_stop(rtlhal)) {
+                rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
+                rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
+        }
+        if (is2t) {
+                if (bmain)
+                        rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
+                                      BIT(5) | BIT(6), 0x1);
+                else
+                        rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
+                                      BIT(5) | BIT(6), 0x2);
+        } else {
+                if (bmain)
+                        rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
+                else
+                        rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
+
+        }
+}
+
+#undef IQK_ADDA_REG_NUM
+#undef IQK_DELAY_TIME
+
+void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        long result[4][8];
+        u8 i, final_candidate;
+        bool b_patha_ok, b_pathb_ok;
+        long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
+            reg_ecc, reg_tmp = 0;
+        bool is12simular, is13simular, is23simular;
+        bool b_start_conttx = false, b_singletone = false;
+        u32 iqk_bb_reg[10] = {
+                ROFDM0_XARXIQIMBALANCE,
+                ROFDM0_XBRXIQIMBALANCE,
+                ROFDM0_ECCATHRESHOLD,
+                ROFDM0_AGCRSSITABLE,
+                ROFDM0_XATXIQIMBALANCE,
+                ROFDM0_XBTXIQIMBALANCE,
+                ROFDM0_XCTXIQIMBALANCE,
+                ROFDM0_XCTXAFE,
+                ROFDM0_XDTXAFE,
+                ROFDM0_RXIQEXTANTA
+        };
+
+        if (b_recovery) {
+                _rtl92c_phy_reload_adda_registers(hw,
+                                                  iqk_bb_reg,
+                                                  rtlphy->iqk_bb_backup, 10);
+                return;
+        }
+        if (b_start_conttx || b_singletone)
+                return;
+        for (i = 0; i < 8; i++) {
+                result[0][i] = 0;
+                result[1][i] = 0;
+                result[2][i] = 0;
+                result[3][i] = 0;
+        }
+        final_candidate = 0xff;
+        b_patha_ok = false;
+        b_pathb_ok = false;
+        is12simular = false;
+        is23simular = false;
+        is13simular = false;
+        for (i = 0; i < 3; i++) {
+                if (IS_92C_SERIAL(rtlhal->version))
+                        _rtl92c_phy_iq_calibrate(hw, result, i, true);
+                else
+                        _rtl92c_phy_iq_calibrate(hw, result, i, false);
+                if (i == 1) {
+                        is12simular = _rtl92c_phy_simularity_compare(hw,
+                                                                     result, 0,
+                                                                     1);
+                        if (is12simular) {
+                                final_candidate = 0;
+                                break;
+                        }
+                }
+                if (i == 2) {
+                        is13simular = _rtl92c_phy_simularity_compare(hw,
+                                                                     result, 0,
+                                                                     2);
+                        if (is13simular) {
+                                final_candidate = 0;
+                                break;
+                        }
+                        is23simular = _rtl92c_phy_simularity_compare(hw,
+                                                                     result, 1,
+                                                                     2);
+                        if (is23simular)
+                                final_candidate = 1;
+                        else {
+                                for (i = 0; i < 8; i++)
+                                        reg_tmp += result[3][i];
+
+                                if (reg_tmp != 0)
+                                        final_candidate = 3;
+                                else
+                                        final_candidate = 0xFF;
+                        }
+                }
+        }
+        for (i = 0; i < 4; i++) {
+                reg_e94 = result[i][0];
+                reg_e9c = result[i][1];
+                reg_ea4 = result[i][2];
+                reg_eac = result[i][3];
+                reg_eb4 = result[i][4];
+                reg_ebc = result[i][5];
+                reg_ec4 = result[i][6];
+                reg_ecc = result[i][7];
+        }
+        if (final_candidate != 0xff) {
+                rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
+                rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
+                reg_ea4 = result[final_candidate][2];
+                reg_eac = result[final_candidate][3];
+                rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
+                rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
+                reg_ec4 = result[final_candidate][6];
+                reg_ecc = result[final_candidate][7];
+                b_patha_ok = b_pathb_ok = true;
+        } else {
+                rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
+                rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
+        }
+        if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
+                _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
+                                                   final_candidate,
+                                                   (reg_ea4 == 0));
+        if (IS_92C_SERIAL(rtlhal->version)) {
+                if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
+                        _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
+                                                           result,
+                                                           final_candidate,
+                                                           (reg_ec4 == 0));
+        }
+        _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
+                                        rtlphy->iqk_bb_backup, 10);
+}
+
+void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
+{
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        bool b_start_conttx = false, b_singletone = false;
+
+        if (b_start_conttx || b_singletone)
+                return;
+        if (IS_92C_SERIAL(rtlhal->version))
+                _rtl92c_phy_lc_calibrate(hw, true);
+        else
+                _rtl92c_phy_lc_calibrate(hw, false);
+}
+
+void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (rtlphy->b_apk_done)
+                return;
+        if (IS_92C_SERIAL(rtlhal->version))
+                _rtl92c_phy_ap_calibrate(hw, delta, true);
+        else
+                _rtl92c_phy_ap_calibrate(hw, delta, false);
+}
+
+void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
+{
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+
+        if (IS_92C_SERIAL(rtlhal->version))
+                _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
+        else
+                _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
+}
+
+bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        bool b_postprocessing = false;
+
+        RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
+                 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
+                  iotype, rtlphy->set_io_inprogress));
+        do {
+                switch (iotype) {
+                case IO_CMD_RESUME_DM_BY_SCAN:
+                        RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
+                                 ("[IO CMD] Resume DM after scan.\n"));
+                        b_postprocessing = true;
+                        break;
+                case IO_CMD_PAUSE_DM_BY_SCAN:
+                        RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
+                                 ("[IO CMD] Pause DM before scan.\n"));
+                        b_postprocessing = true;
+                        break;
+                default:
+                        RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                                 ("switch case not process\n"));
+                        break;
+                }
+        } while (false);
+        if (b_postprocessing && !rtlphy->set_io_inprogress) {
+                rtlphy->set_io_inprogress = true;
+                rtlphy->current_io_type = iotype;
+        } else {
+                return false;
+        }
+        rtl92c_phy_set_io(hw);
+        RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
+        return true;
+}
+
+void rtl92c_phy_set_io(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
+                 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
+                  rtlphy->current_io_type, rtlphy->set_io_inprogress));
+        switch (rtlphy->current_io_type) {
+        case IO_CMD_RESUME_DM_BY_SCAN:
+                dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
+                rtl92c_dm_write_dig(hw);
+                rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
+                break;
+        case IO_CMD_PAUSE_DM_BY_SCAN:
+                rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
+                dm_digtable.cur_igvalue = 0x17;
+                rtl92c_dm_write_dig(hw);
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                break;
+        }
+        rtlphy->set_io_inprogress = false;
+        RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
+                 ("<---(%#x)\n", rtlphy->current_io_type));
+}
+
+void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
+        rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
+        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
+}
+
+static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
+{
+        u32 u4b_tmp;
+        u8 delay = 5;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
+        rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
+        rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
+        u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
+        while (u4b_tmp != 0 && delay > 0) {
+                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
+                rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
+                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
+                u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
+                delay--;
+        }
+        if (delay == 0) {
+                rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
+                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
+                rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
+                rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
+                RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
+                         ("Switch RF timeout !!!.\n"));
+                return;
+        }
+        rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
+        rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
+}
+
+static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
+                                            enum rf_pwrstate rfpwr_state)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        bool bresult = true;
+        u8 i, queue_id;
+        struct rtl8192_tx_ring *ring = NULL;
+
+        ppsc->set_rfpowerstate_inprogress = true;
+        switch (rfpwr_state) {
+        case ERFON:{
+                        if ((ppsc->rfpwr_state == ERFOFF) &&
+                            RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
+                                bool rtstatus;
+                                u32 InitializeCount = 0;
+                                do {
+                                        InitializeCount++;
+                                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                                 ("IPS Set eRf nic enable\n"));
+                                        rtstatus = rtl_ps_enable_nic(hw);
+                                } while ((rtstatus != true)
+                                         && (InitializeCount < 10));
+                                RT_CLEAR_PS_LEVEL(ppsc,
+                                                  RT_RF_OFF_LEVL_HALT_NIC);
+                        } else {
+                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                         ("Set ERFON sleeped:%d ms\n",
+                                          jiffies_to_msecs(jiffies -
+                                                   ppsc->
+                                                   last_sleep_jiffies)));
+                                ppsc->last_awake_jiffies = jiffies;
+                                rtl92ce_phy_set_rf_on(hw);
+                        }
+                        if (mac->link_state == MAC80211_LINKED) {
+                                rtlpriv->cfg->ops->led_control(hw,
+                                                               LED_CTL_LINK);
+                        } else {
+                                rtlpriv->cfg->ops->led_control(hw,
+                                                               LED_CTL_NO_LINK);
+                        }
+                        break;
+                }
+        case ERFOFF:{
+                        for (queue_id = 0, i = 0;
+                             queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
+                                ring = &pcipriv->dev.tx_ring[queue_id];
+                                if (skb_queue_len(&ring->queue) == 0 ||
+                                    queue_id == BEACON_QUEUE) {
+                                        queue_id++;
+                                        continue;
+                                } else {
+                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                                 ("eRf Off/Sleep: %d times "
+                                                  "TcbBusyQueue[%d] "
+                                                  "=%d before doze!\n", (i + 1),
+                                                  queue_id,
+                                                  skb_queue_len(&ring->queue)));
+                                        udelay(10);
+                                        i++;
+                                }
+                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
+                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                                 ("\nERFOFF: %d times "
+                                                  "TcbBusyQueue[%d] = %d !\n",
+                                                  MAX_DOZE_WAITING_TIMES_9x,
+                                                  queue_id,
+                                                  skb_queue_len(&ring->queue)));
+                                        break;
+                                }
+                        }
+                        if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
+                                RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                         ("IPS Set eRf nic disable\n"));
+                                rtl_ps_disable_nic(hw);
+                                RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
+                        } else {
+                                if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
+                                        rtlpriv->cfg->ops->led_control(hw,
+                                                               LED_CTL_NO_LINK);
+                                } else {
+                                        rtlpriv->cfg->ops->led_control(hw,
+                                                             LED_CTL_POWER_OFF);
+                                }
+                        }
+                        break;
+                }
+        case ERFSLEEP:{
+                        if (ppsc->rfpwr_state == ERFOFF)
+                                break;
+                        for (queue_id = 0, i = 0;
+                             queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
+                                ring = &pcipriv->dev.tx_ring[queue_id];
+                                if (skb_queue_len(&ring->queue) == 0) {
+                                        queue_id++;
+                                        continue;
+                                } else {
+                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                                 ("eRf Off/Sleep: %d times "
+                                                  "TcbBusyQueue[%d] =%d before "
+                                                  "doze!\n", (i + 1), queue_id,
+                                                  skb_queue_len(&ring->queue)));
+                                        udelay(10);
+                                        i++;
+                                }
+                                if (i >= MAX_DOZE_WAITING_TIMES_9x) {
+                                        RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
+                                                 ("\n ERFSLEEP: %d times "
+                                                  "TcbBusyQueue[%d] = %d !\n",
+                                                  MAX_DOZE_WAITING_TIMES_9x,
+                                                  queue_id,
+                                                  skb_queue_len(&ring->queue)));
+                                        break;
+                                }
+                        }
+                        RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
+                                 ("Set ERFSLEEP awaked:%d ms\n",
+                                  jiffies_to_msecs(jiffies -
+                                                   ppsc->last_awake_jiffies)));
+                        ppsc->last_sleep_jiffies = jiffies;
+                        _rtl92ce_phy_set_rf_sleep(hw);
+                        break;
+                }
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("switch case not process\n"));
+                bresult = false;
+                break;
+        }
+        if (bresult)
+                ppsc->rfpwr_state = rfpwr_state;
+        ppsc->set_rfpowerstate_inprogress = false;
+        return bresult;
+}
+
+bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
+                                   enum rf_pwrstate rfpwr_state)
+{
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        bool bresult = false;
+
+        if (rfpwr_state == ppsc->rfpwr_state)
+                return bresult;
+        bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
+        return bresult;
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
new file mode 100644
index 000000000000..ca4daee6e9a8
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
@@ -0,0 +1,237 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92C_PHY_H__
+#define __RTL92C_PHY_H__
+
+#define MAX_PRECMD_CNT                  16
+#define MAX_RFDEPENDCMD_CNT             16
+#define MAX_POSTCMD_CNT                 16
+
+#define MAX_DOZE_WAITING_TIMES_9x       64
+
+#define RT_CANNOT_IO(hw)                false
+#define HIGHPOWER_RADIOA_ARRAYLEN       22
+
+#define MAX_TOLERANCE                   5
+#define IQK_DELAY_TIME                  1
+
+#define APK_BB_REG_NUM                  5
+#define APK_AFE_REG_NUM                 16
+#define APK_CURVE_REG_NUM               4
+#define PATH_NUM                        2
+
+#define LOOP_LIMIT                      5
+#define MAX_STALL_TIME                  50
+#define AntennaDiversityValue           0x80
+#define MAX_TXPWR_IDX_NMODE_92S         63
+#define Reset_Cnt_Limit                 3
+
+#define IQK_ADDA_REG_NUM                16
+#define IQK_MAC_REG_NUM                 4
+
+#define RF90_PATH_MAX                   2
+#define CHANNEL_MAX_NUMBER              14
+#define CHANNEL_GROUP_MAX               3
+
+#define CT_OFFSET_MAC_ADDR              0X16
+
+#define CT_OFFSET_CCK_TX_PWR_IDX        0x5A
+#define CT_OFFSET_HT401S_TX_PWR_IDX     0x60
+#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
+#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF  0x69
+#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF  0x6C
+
+#define CT_OFFSET_HT40_MAX_PWR_OFFSET   0x6F
+#define CT_OFFSET_HT20_MAX_PWR_OFFSET   0x72
+
+#define CT_OFFSET_CHANNEL_PLAH          0x75
+#define CT_OFFSET_THERMAL_METER         0x78
+#define CT_OFFSET_RF_OPTION             0x79
+#define CT_OFFSET_VERSION               0x7E
+#define CT_OFFSET_CUSTOMER_ID           0x7F
+
+#define RTL92C_MAX_PATH_NUM             2
+#define CHANNEL_MAX_NUMBER              14
+#define CHANNEL_GROUP_MAX               3
+
+enum swchnlcmd_id {
+        CMDID_END,
+        CMDID_SET_TXPOWEROWER_LEVEL,
+        CMDID_BBREGWRITE10,
+        CMDID_WRITEPORT_ULONG,
+        CMDID_WRITEPORT_USHORT,
+        CMDID_WRITEPORT_UCHAR,
+        CMDID_RF_WRITEREG,
+};
+
+struct swchnlcmd {
+        enum swchnlcmd_id cmdid;
+        u32 para1;
+        u32 para2;
+        u32 msdelay;
+};
+
+enum hw90_block_e {
+        HW90_BLOCK_MAC = 0,
+        HW90_BLOCK_PHY0 = 1,
+        HW90_BLOCK_PHY1 = 2,
+        HW90_BLOCK_RF = 3,
+        HW90_BLOCK_MAXIMUM = 4,
+};
+
+enum baseband_config_type {
+        BASEBAND_CONFIG_PHY_REG = 0,
+        BASEBAND_CONFIG_AGC_TAB = 1,
+};
+
+enum ra_offset_area {
+        RA_OFFSET_LEGACY_OFDM1,
+        RA_OFFSET_LEGACY_OFDM2,
+        RA_OFFSET_HT_OFDM1,
+        RA_OFFSET_HT_OFDM2,
+        RA_OFFSET_HT_OFDM3,
+        RA_OFFSET_HT_OFDM4,
+        RA_OFFSET_HT_CCK,
+};
+
+enum antenna_path {
+        ANTENNA_NONE,
+        ANTENNA_D,
+        ANTENNA_C,
+        ANTENNA_CD,
+        ANTENNA_B,
+        ANTENNA_BD,
+        ANTENNA_BC,
+        ANTENNA_BCD,
+        ANTENNA_A,
+        ANTENNA_AD,
+        ANTENNA_AC,
+        ANTENNA_ACD,
+        ANTENNA_AB,
+        ANTENNA_ABD,
+        ANTENNA_ABC,
+        ANTENNA_ABCD
+};
+
+struct r_antenna_select_ofdm {
+        u32 r_tx_antenna:4;
+        u32 r_ant_l:4;
+        u32 r_ant_non_ht:4;
+        u32 r_ant_ht1:4;
+        u32 r_ant_ht2:4;
+        u32 r_ant_ht_s1:4;
+        u32 r_ant_non_ht_s1:4;
+        u32 ofdm_txsc:2;
+        u32 reserved:2;
+};
+
+struct r_antenna_select_cck {
+        u8 r_cckrx_enable_2:2;
+        u8 r_cckrx_enable:2;
+        u8 r_ccktx_enable:4;
+};
+
+struct efuse_contents {
+        u8 mac_addr[ETH_ALEN];
+        u8 cck_tx_power_idx[6];
+        u8 ht40_1s_tx_power_idx[6];
+        u8 ht40_2s_tx_power_idx_diff[3];
+        u8 ht20_tx_power_idx_diff[3];
+        u8 ofdm_tx_power_idx_diff[3];
+        u8 ht40_max_power_offset[3];
+        u8 ht20_max_power_offset[3];
+        u8 channel_plan;
+        u8 thermal_meter;
+        u8 rf_option[5];
+        u8 version;
+        u8 oem_id;
+        u8 regulatory;
+};
+
+struct tx_power_struct {
+        u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 legacy_ht_txpowerdiff;
+        u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
+        u8 pwrgroup_cnt;
+        u32 mcs_original_offset[4][16];
+};
+
+extern u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
+                                   u32 regaddr, u32 bitmask);
+extern void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
+                                  u32 regaddr, u32 bitmask, u32 data);
+extern u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
+                                   enum radio_path rfpath, u32 regaddr,
+                                   u32 bitmask);
+extern void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
+                                  enum radio_path rfpath, u32 regaddr,
+                                  u32 bitmask, u32 data);
+extern bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
+extern bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
+extern bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
+extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
+                                                 enum radio_path rfpath);
+extern void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
+extern void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
+                                         long *powerlevel);
+extern void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
+extern bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
+                                          long power_indbm);
+extern void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
+                                             u8 operation);
+extern void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
+extern void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
+                                   enum nl80211_channel_type ch_type);
+extern void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
+extern u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
+extern void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
+extern void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
+                                         u16 beaconinterval);
+void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
+void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
+void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
+bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
+                                          enum radio_path rfpath);
+extern bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
+                                              u32 rfpath);
+bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
+extern bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
+                                          enum rf_pwrstate rfpwr_state);
+void rtl92c_phy_config_bb_external_pa(struct ieee80211_hw *hw);
+void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
+bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
+void rtl92c_phy_set_io(struct ieee80211_hw *hw);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
new file mode 100644
index 000000000000..875d51465225
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -0,0 +1,2065 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92C_REG_H__
+#define __RTL92C_REG_H__
+
+#define REG_SYS_ISO_CTRL                        0x0000
+#define REG_SYS_FUNC_EN                         0x0002
+#define REG_APS_FSMCO                           0x0004
+#define REG_SYS_CLKR                            0x0008
+#define REG_9346CR                              0x000A
+#define REG_EE_VPD                              0x000C
+#define REG_AFE_MISC                            0x0010
+#define REG_SPS0_CTRL                           0x0011
+#define REG_SPS_OCP_CFG                         0x0018
+#define REG_RSV_CTRL                            0x001C
+#define REG_RF_CTRL                             0x001F
+#define REG_LDOA15_CTRL                         0x0020
+#define REG_LDOV12D_CTRL                        0x0021
+#define REG_LDOHCI12_CTRL                       0x0022
+#define REG_LPLDO_CTRL                          0x0023
+#define REG_AFE_XTAL_CTRL                       0x0024
+#define REG_AFE_PLL_CTRL                        0x0028
+#define REG_EFUSE_CTRL                          0x0030
+#define REG_EFUSE_TEST                          0x0034
+#define REG_PWR_DATA                            0x0038
+#define REG_CAL_TIMER                           0x003C
+#define REG_ACLK_MON                            0x003E
+#define REG_GPIO_MUXCFG                         0x0040
+#define REG_GPIO_IO_SEL                         0x0042
+#define REG_MAC_PINMUX_CFG                      0x0043
+#define REG_GPIO_PIN_CTRL                       0x0044
+#define REG_GPIO_INTM                           0x0048
+#define REG_LEDCFG0                             0x004C
+#define REG_LEDCFG1                             0x004D
+#define REG_LEDCFG2                             0x004E
+#define REG_LEDCFG3                             0x004F
+#define REG_FSIMR                               0x0050
+#define REG_FSISR                               0x0054
+
+#define REG_MCUFWDL                             0x0080
+
+#define REG_HMEBOX_EXT_0                        0x0088
+#define REG_HMEBOX_EXT_1                        0x008A
+#define REG_HMEBOX_EXT_2                        0x008C
+#define REG_HMEBOX_EXT_3                        0x008E
+
+#define REG_BIST_SCAN                           0x00D0
+#define REG_BIST_RPT                            0x00D4
+#define REG_BIST_ROM_RPT                        0x00D8
+#define REG_USB_SIE_INTF                        0x00E0
+#define REG_PCIE_MIO_INTF                       0x00E4
+#define REG_PCIE_MIO_INTD                       0x00E8
+#define REG_HPON_FSM                            0x00EC
+#define REG_SYS_CFG                             0x00F0
+
+#define REG_CR                                  0x0100
+#define REG_PBP                                 0x0104
+#define REG_TRXDMA_CTRL                         0x010C
+#define REG_TRXFF_BNDY                          0x0114
+#define REG_TRXFF_STATUS                        0x0118
+#define REG_RXFF_PTR                            0x011C
+#define REG_HIMR                                0x0120
+#define REG_HISR                                0x0124
+#define REG_HIMRE                               0x0128
+#define REG_HISRE                               0x012C
+#define REG_CPWM                                0x012F
+#define REG_FWIMR                               0x0130
+#define REG_FWISR                               0x0134
+#define REG_PKTBUF_DBG_CTRL                     0x0140
+#define REG_PKTBUF_DBG_DATA_L                   0x0144
+#define REG_PKTBUF_DBG_DATA_H                   0x0148
+
+#define REG_TC0_CTRL                            0x0150
+#define REG_TC1_CTRL                            0x0154
+#define REG_TC2_CTRL                            0x0158
+#define REG_TC3_CTRL                            0x015C
+#define REG_TC4_CTRL                            0x0160
+#define REG_TCUNIT_BASE                         0x0164
+#define REG_MBIST_START                         0x0174
+#define REG_MBIST_DONE                          0x0178
+#define REG_MBIST_FAIL                          0x017C
+#define REG_C2HEVT_MSG_NORMAL                   0x01A0
+#define REG_C2HEVT_MSG_TEST                     0x01B8
+#define REG_C2HEVT_CLEAR                        0x01BF
+#define REG_MCUTST_1                            0x01c0
+#define REG_FMETHR                              0x01C8
+#define REG_HMETFR                              0x01CC
+#define REG_HMEBOX_0                            0x01D0
+#define REG_HMEBOX_1                            0x01D4
+#define REG_HMEBOX_2                            0x01D8
+#define REG_HMEBOX_3                            0x01DC
+
+#define REG_LLT_INIT                            0x01E0
+#define REG_BB_ACCEESS_CTRL                     0x01E8
+#define REG_BB_ACCESS_DATA                      0x01EC
+
+#define REG_RQPN                                0x0200
+#define REG_FIFOPAGE                            0x0204
+#define REG_TDECTRL                             0x0208
+#define REG_TXDMA_OFFSET_CHK                    0x020C
+#define REG_TXDMA_STATUS                        0x0210
+#define REG_RQPN_NPQ                            0x0214
+
+#define REG_RXDMA_AGG_PG_TH                     0x0280
+#define REG_RXPKT_NUM                           0x0284
+#define REG_RXDMA_STATUS                        0x0288
+
+#define REG_PCIE_CTRL_REG                       0x0300
+#define REG_INT_MIG                             0x0304
+#define REG_BCNQ_DESA                           0x0308
+#define REG_HQ_DESA                             0x0310
+#define REG_MGQ_DESA                            0x0318
+#define REG_VOQ_DESA                            0x0320
+#define REG_VIQ_DESA                            0x0328
+#define REG_BEQ_DESA                            0x0330
+#define REG_BKQ_DESA                            0x0338
+#define REG_RX_DESA                             0x0340
+#define REG_DBI                                 0x0348
+#define REG_MDIO                                0x0354
+#define REG_DBG_SEL                             0x0360
+#define REG_PCIE_HRPWM                          0x0361
+#define REG_PCIE_HCPWM                          0x0363
+#define REG_UART_CTRL                           0x0364
+#define REG_UART_TX_DESA                        0x0370
+#define REG_UART_RX_DESA                        0x0378
+
+#define REG_HDAQ_DESA_NODEF                     0x0000
+#define REG_CMDQ_DESA_NODEF                     0x0000
+
+#define REG_VOQ_INFORMATION                     0x0400
+#define REG_VIQ_INFORMATION                     0x0404
+#define REG_BEQ_INFORMATION                     0x0408
+#define REG_BKQ_INFORMATION                     0x040C
+#define REG_MGQ_INFORMATION                     0x0410
+#define REG_HGQ_INFORMATION                     0x0414
+#define REG_BCNQ_INFORMATION                    0x0418
+
+#define REG_CPU_MGQ_INFORMATION                 0x041C
+#define REG_FWHW_TXQ_CTRL                       0x0420
+#define REG_HWSEQ_CTRL                          0x0423
+#define REG_TXPKTBUF_BCNQ_BDNY                  0x0424
+#define REG_TXPKTBUF_MGQ_BDNY                   0x0425
+#define REG_MULTI_BCNQ_EN                       0x0426
+#define REG_MULTI_BCNQ_OFFSET                   0x0427
+#define REG_SPEC_SIFS                           0x0428
+#define REG_RL                                  0x042A
+#define REG_DARFRC                              0x0430
+#define REG_RARFRC                              0x0438
+#define REG_RRSR                                0x0440
+#define REG_ARFR0                               0x0444
+#define REG_ARFR1                               0x0448
+#define REG_ARFR2                               0x044C
+#define REG_ARFR3                               0x0450
+#define REG_AGGLEN_LMT                          0x0458
+#define REG_AMPDU_MIN_SPACE                     0x045C
+#define REG_TXPKTBUF_WMAC_LBK_BF_HD             0x045D
+#define REG_FAST_EDCA_CTRL                      0x0460
+#define REG_RD_RESP_PKT_TH                      0x0463
+#define REG_INIRTS_RATE_SEL                     0x0480
+#define REG_INIDATA_RATE_SEL                    0x0484
+#define REG_POWER_STATUS                        0x04A4
+#define REG_POWER_STAGE1                        0x04B4
+#define REG_POWER_STAGE2                        0x04B8
+#define REG_PKT_LIFE_TIME                       0x04C0
+#define REG_STBC_SETTING                        0x04C4
+#define REG_PROT_MODE_CTRL                      0x04C8
+#define REG_BAR_MODE_CTRL                       0x04CC
+#define REG_RA_TRY_RATE_AGG_LMT                 0x04CF
+#define REG_NQOS_SEQ                            0x04DC
+#define REG_QOS_SEQ                             0x04DE
+#define REG_NEED_CPU_HANDLE                     0x04E0
+#define REG_PKT_LOSE_RPT                        0x04E1
+#define REG_PTCL_ERR_STATUS                     0x04E2
+#define REG_DUMMY                               0x04FC
+
+#define REG_EDCA_VO_PARAM                       0x0500
+#define REG_EDCA_VI_PARAM                       0x0504
+#define REG_EDCA_BE_PARAM                       0x0508
+#define REG_EDCA_BK_PARAM                       0x050C
+#define REG_BCNTCFG                             0x0510
+#define REG_PIFS                                0x0512
+#define REG_RDG_PIFS                            0x0513
+#define REG_SIFS_CTX                            0x0514
+#define REG_SIFS_TRX                            0x0516
+#define REG_AGGR_BREAK_TIME                     0x051A
+#define REG_SLOT                                0x051B
+#define REG_TX_PTCL_CTRL                        0x0520
+#define REG_TXPAUSE                             0x0522
+#define REG_DIS_TXREQ_CLR                       0x0523
+#define REG_RD_CTRL                             0x0524
+#define REG_TBTT_PROHIBIT                       0x0540
+#define REG_RD_NAV_NXT                          0x0544
+#define REG_NAV_PROT_LEN                        0x0546
+#define REG_BCN_CTRL                            0x0550
+#define REG_USTIME_TSF                          0x0551
+#define REG_MBID_NUM                            0x0552
+#define REG_DUAL_TSF_RST                        0x0553
+#define REG_BCN_INTERVAL                        0x0554
+#define REG_MBSSID_BCN_SPACE                    0x0554
+#define REG_DRVERLYINT                          0x0558
+#define REG_BCNDMATIM                           0x0559
+#define REG_ATIMWND                             0x055A
+#define REG_BCN_MAX_ERR                         0x055D
+#define REG_RXTSF_OFFSET_CCK                    0x055E
+#define REG_RXTSF_OFFSET_OFDM                   0x055F
+#define REG_TSFTR                               0x0560
+#define REG_INIT_TSFTR                          0x0564
+#define REG_PSTIMER                             0x0580
+#define REG_TIMER0                              0x0584
+#define REG_TIMER1                              0x0588
+#define REG_ACMHWCTRL                           0x05C0
+#define REG_ACMRSTCTRL                          0x05C1
+#define REG_ACMAVG                              0x05C2
+#define REG_VO_ADMTIME                          0x05C4
+#define REG_VI_ADMTIME                          0x05C6
+#define REG_BE_ADMTIME                          0x05C8
+#define REG_EDCA_RANDOM_GEN                     0x05CC
+#define REG_SCH_TXCMD                           0x05D0
+
+#define REG_APSD_CTRL                           0x0600
+#define REG_BWOPMODE                            0x0603
+#define REG_TCR                                 0x0604
+#define REG_RCR                                 0x0608
+#define REG_RX_PKT_LIMIT                        0x060C
+#define REG_RX_DLK_TIME                         0x060D
+#define REG_RX_DRVINFO_SZ                       0x060F
+
+#define REG_MACID                               0x0610
+#define REG_BSSID                               0x0618
+#define REG_MAR                                 0x0620
+#define REG_MBIDCAMCFG                          0x0628
+
+#define REG_USTIME_EDCA                         0x0638
+#define REG_MAC_SPEC_SIFS                       0x063A
+#define REG_RESP_SIFS_CCK                       0x063C
+#define REG_RESP_SIFS_OFDM                      0x063E
+#define REG_ACKTO                               0x0640
+#define REG_CTS2TO                              0x0641
+#define REG_EIFS                                0x0642
+
+#define REG_NAV_CTRL                            0x0650
+#define REG_BACAMCMD                            0x0654
+#define REG_BACAMCONTENT                        0x0658
+#define REG_LBDLY                               0x0660
+#define REG_FWDLY                               0x0661
+#define REG_RXERR_RPT                           0x0664
+#define REG_WMAC_TRXPTCL_CTL                    0x0668
+
+#define REG_CAMCMD                              0x0670
+#define REG_CAMWRITE                            0x0674
+#define REG_CAMREAD                             0x0678
+#define REG_CAMDBG                              0x067C
+#define REG_SECCFG                              0x0680
+
+#define REG_WOW_CTRL                            0x0690
+#define REG_PSSTATUS                            0x0691
+#define REG_PS_RX_INFO                          0x0692
+#define REG_LPNAV_CTRL                          0x0694
+#define REG_WKFMCAM_CMD                         0x0698
+#define REG_WKFMCAM_RWD                         0x069C
+#define REG_RXFLTMAP0                           0x06A0
+#define REG_RXFLTMAP1                           0x06A2
+#define REG_RXFLTMAP2                           0x06A4
+#define REG_BCN_PSR_RPT                         0x06A8
+#define REG_CALB32K_CTRL                        0x06AC
+#define REG_PKT_MON_CTRL                        0x06B4
+#define REG_BT_COEX_TABLE                       0x06C0
+#define REG_WMAC_RESP_TXINFO                    0x06D8
+
+#define REG_USB_INFO                            0xFE17
+#define REG_USB_SPECIAL_OPTION                  0xFE55
+#define REG_USB_DMA_AGG_TO                      0xFE5B
+#define REG_USB_AGG_TO                          0xFE5C
+#define REG_USB_AGG_TH                          0xFE5D
+
+#define REG_TEST_USB_TXQS                       0xFE48
+#define REG_TEST_SIE_VID                        0xFE60
+#define REG_TEST_SIE_PID                        0xFE62
+#define REG_TEST_SIE_OPTIONAL                   0xFE64
+#define REG_TEST_SIE_CHIRP_K                    0xFE65
+#define REG_TEST_SIE_PHY                        0xFE66
+#define REG_TEST_SIE_MAC_ADDR                   0xFE70
+#define REG_TEST_SIE_STRING                     0xFE80
+
+#define REG_NORMAL_SIE_VID                      0xFE60
+#define REG_NORMAL_SIE_PID                      0xFE62
+#define REG_NORMAL_SIE_OPTIONAL                 0xFE64
+#define REG_NORMAL_SIE_EP                       0xFE65
+#define REG_NORMAL_SIE_PHY                      0xFE68
+#define REG_NORMAL_SIE_MAC_ADDR                 0xFE70
+#define REG_NORMAL_SIE_STRING                   0xFE80
+
+#define CR9346                                  REG_9346CR
+#define MSR                                     (REG_CR + 2)
+#define ISR                                     REG_HISR
+#define TSFR                                    REG_TSFTR
+
+#define MACIDR0                                 REG_MACID
+#define MACIDR4                                 (REG_MACID + 4)
+
+#define PBP                                     REG_PBP
+
+#define IDR0                                    MACIDR0
+#define IDR4                                    MACIDR4
+
+#define UNUSED_REGISTER                         0x1BF
+#define DCAM                                    UNUSED_REGISTER
+#define PSR                                     UNUSED_REGISTER
+#define BBADDR                                  UNUSED_REGISTER
+#define PHYDATAR                                UNUSED_REGISTER
+
+#define INVALID_BBRF_VALUE                      0x12345678
+
+#define MAX_MSS_DENSITY_2T                      0x13
+#define MAX_MSS_DENSITY_1T                      0x0A
+
+#define CMDEEPROM_EN                            BIT(5)
+#define CMDEEPROM_SEL                           BIT(4)
+#define CMD9346CR_9356SEL                       BIT(4)
+#define AUTOLOAD_EEPROM                         (CMDEEPROM_EN|CMDEEPROM_SEL)
+#define AUTOLOAD_EFUSE                          CMDEEPROM_EN
+
+#define GPIOSEL_GPIO                            0
+#define GPIOSEL_ENBT                            BIT(5)
+
+#define GPIO_IN                                 REG_GPIO_PIN_CTRL
+#define GPIO_OUT                                (REG_GPIO_PIN_CTRL+1)
+#define GPIO_IO_SEL                             (REG_GPIO_PIN_CTRL+2)
+#define GPIO_MOD                                (REG_GPIO_PIN_CTRL+3)
+
+#define MSR_NOLINK                              0x00
+#define MSR_ADHOC                               0x01
+#define MSR_INFRA                               0x02
+#define MSR_AP                                  0x03
+
+#define RRSR_RSC_OFFSET                         21
+#define RRSR_SHORT_OFFSET                       23
+#define RRSR_RSC_BW_40M                         0x600000
+#define RRSR_RSC_UPSUBCHNL                      0x400000
+#define RRSR_RSC_LOWSUBCHNL                     0x200000
+#define RRSR_SHORT                              0x800000
+#define RRSR_1M                                 BIT(0)
+#define RRSR_2M                                 BIT(1)
+#define RRSR_5_5M                               BIT(2)
+#define RRSR_11M                                BIT(3)
+#define RRSR_6M                                 BIT(4)
+#define RRSR_9M                                 BIT(5)
+#define RRSR_12M                                BIT(6)
+#define RRSR_18M                                BIT(7)
+#define RRSR_24M                                BIT(8)
+#define RRSR_36M                                BIT(9)
+#define RRSR_48M                                BIT(10)
+#define RRSR_54M                                BIT(11)
+#define RRSR_MCS0                               BIT(12)
+#define RRSR_MCS1                               BIT(13)
+#define RRSR_MCS2                               BIT(14)
+#define RRSR_MCS3                               BIT(15)
+#define RRSR_MCS4                               BIT(16)
+#define RRSR_MCS5                               BIT(17)
+#define RRSR_MCS6                               BIT(18)
+#define RRSR_MCS7                               BIT(19)
+#define BRSR_ACKSHORTPMB                        BIT(23)
+
+#define RATR_1M                                 0x00000001
+#define RATR_2M                                 0x00000002
+#define RATR_55M                                0x00000004
+#define RATR_11M                                0x00000008
+#define RATR_6M                                 0x00000010
+#define RATR_9M                                 0x00000020
+#define RATR_12M                                0x00000040
+#define RATR_18M                                0x00000080
+#define RATR_24M                                0x00000100
+#define RATR_36M                                0x00000200
+#define RATR_48M                                0x00000400
+#define RATR_54M                                0x00000800
+#define RATR_MCS0                               0x00001000
+#define RATR_MCS1                               0x00002000
+#define RATR_MCS2                               0x00004000
+#define RATR_MCS3                               0x00008000
+#define RATR_MCS4                               0x00010000
+#define RATR_MCS5                               0x00020000
+#define RATR_MCS6                               0x00040000
+#define RATR_MCS7                               0x00080000
+#define RATR_MCS8                               0x00100000
+#define RATR_MCS9                               0x00200000
+#define RATR_MCS10                              0x00400000
+#define RATR_MCS11                              0x00800000
+#define RATR_MCS12                              0x01000000
+#define RATR_MCS13                              0x02000000
+#define RATR_MCS14                              0x04000000
+#define RATR_MCS15                              0x08000000
+
+#define RATE_1M                                 BIT(0)
+#define RATE_2M                                 BIT(1)
+#define RATE_5_5M                               BIT(2)
+#define RATE_11M                                BIT(3)
+#define RATE_6M                                 BIT(4)
+#define RATE_9M                                 BIT(5)
+#define RATE_12M                                BIT(6)
+#define RATE_18M                                BIT(7)
+#define RATE_24M                                BIT(8)
+#define RATE_36M                                BIT(9)
+#define RATE_48M                                BIT(10)
+#define RATE_54M                                BIT(11)
+#define RATE_MCS0                               BIT(12)
+#define RATE_MCS1                               BIT(13)
+#define RATE_MCS2                               BIT(14)
+#define RATE_MCS3                               BIT(15)
+#define RATE_MCS4                               BIT(16)
+#define RATE_MCS5                               BIT(17)
+#define RATE_MCS6                               BIT(18)
+#define RATE_MCS7                               BIT(19)
+#define RATE_MCS8                               BIT(20)
+#define RATE_MCS9                               BIT(21)
+#define RATE_MCS10                              BIT(22)
+#define RATE_MCS11                              BIT(23)
+#define RATE_MCS12                              BIT(24)
+#define RATE_MCS13                              BIT(25)
+#define RATE_MCS14                              BIT(26)
+#define RATE_MCS15                              BIT(27)
+
+#define RATE_ALL_CCK            (RATR_1M | RATR_2M | RATR_55M | RATR_11M)
+#define RATE_ALL_OFDM_AG        (RATR_6M | RATR_9M | RATR_12M | RATR_18M \
+                                | RATR_24M | RATR_36M | RATR_48M | RATR_54M)
+#define RATE_ALL_OFDM_1SS       (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \
+                                RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \
+                                RATR_MCS6 | RATR_MCS7)
+#define RATE_ALL_OFDM_2SS       (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \
+                                RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \
+                                RATR_MCS14 | RATR_MCS15)
+
+#define BW_OPMODE_20MHZ                         BIT(2)
+#define BW_OPMODE_5G                            BIT(1)
+#define BW_OPMODE_11J                           BIT(0)
+
+#define CAM_VALID                               BIT(15)
+#define CAM_NOTVALID                            0x0000
+#define CAM_USEDK                               BIT(5)
+
+#define CAM_NONE                                0x0
+#define CAM_WEP40                               0x01
+#define CAM_TKIP                                0x02
+#define CAM_AES                                 0x04
+#define CAM_WEP104                              0x05
+
+#define TOTAL_CAM_ENTRY                         32
+#define HALF_CAM_ENTRY                          16
+
+#define CAM_WRITE                               BIT(16)
+#define CAM_READ                                0x00000000
+#define CAM_POLLINIG                            BIT(31)
+
+#define SCR_USEDK                               0x01
+#define SCR_TXSEC_ENABLE                        0x02
+#define SCR_RXSEC_ENABLE                        0x04
+
+#define WOW_PMEN                                BIT(0)
+#define WOW_WOMEN                               BIT(1)
+#define WOW_MAGIC                               BIT(2)
+#define WOW_UWF                                 BIT(3)
+
+#define IMR8190_DISABLED                        0x0
+#define IMR_BCNDMAINT6                          BIT(31)
+#define IMR_BCNDMAINT5                          BIT(30)
+#define IMR_BCNDMAINT4                          BIT(29)
+#define IMR_BCNDMAINT3                          BIT(28)
+#define IMR_BCNDMAINT2                          BIT(27)
+#define IMR_BCNDMAINT1                          BIT(26)
+#define IMR_BCNDOK8                             BIT(25)
+#define IMR_BCNDOK7                             BIT(24)
+#define IMR_BCNDOK6                             BIT(23)
+#define IMR_BCNDOK5                             BIT(22)
+#define IMR_BCNDOK4                             BIT(21)
+#define IMR_BCNDOK3                             BIT(20)
+#define IMR_BCNDOK2                             BIT(19)
+#define IMR_BCNDOK1                             BIT(18)
+#define IMR_TIMEOUT2                            BIT(17)
+#define IMR_TIMEOUT1                            BIT(16)
+#define IMR_TXFOVW                              BIT(15)
+#define IMR_PSTIMEOUT                           BIT(14)
+#define IMR_BCNINT                              BIT(13)
+#define IMR_RXFOVW                              BIT(12)
+#define IMR_RDU                                 BIT(11)
+#define IMR_ATIMEND                             BIT(10)
+#define IMR_BDOK                                BIT(9)
+#define IMR_HIGHDOK                             BIT(8)
+#define IMR_TBDOK                               BIT(7)
+#define IMR_MGNTDOK                             BIT(6)
+#define IMR_TBDER                               BIT(5)
+#define IMR_BKDOK                               BIT(4)
+#define IMR_BEDOK                               BIT(3)
+#define IMR_VIDOK                               BIT(2)
+#define IMR_VODOK                               BIT(1)
+#define IMR_ROK                                 BIT(0)
+
+#define IMR_TXERR                               BIT(11)
+#define IMR_RXERR                               BIT(10)
+#define IMR_C2HCMD                              BIT(9)
+#define IMR_CPWM                                BIT(8)
+#define IMR_OCPINT                              BIT(1)
+#define IMR_WLANOFF                             BIT(0)
+
+#define HWSET_MAX_SIZE                          128
+
+#define EEPROM_DEFAULT_TSSI                     0x0
+#define EEPROM_DEFAULT_TXPOWERDIFF              0x0
+#define EEPROM_DEFAULT_CRYSTALCAP               0x5
+#define EEPROM_DEFAULT_BOARDTYPE                0x02
+#define EEPROM_DEFAULT_TXPOWER                  0x1010
+#define EEPROM_DEFAULT_HT2T_TXPWR               0x10
+
+#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF      0x3
+#define EEPROM_DEFAULT_THERMALMETER             0x12
+#define EEPROM_DEFAULT_ANTTXPOWERDIFF           0x0
+#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP      0x5
+#define EEPROM_DEFAULT_TXPOWERLEVEL             0x22
+#define EEPROM_DEFAULT_HT40_2SDIFF              0x0
+#define EEPROM_DEFAULT_HT20_DIFF                2
+#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF      0x3
+#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET        0
+#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET        0
+
+#define RF_OPTION1                              0x79
+#define RF_OPTION2                              0x7A
+#define RF_OPTION3                              0x7B
+#define RF_OPTION4                              0x7C
+
+#define EEPROM_DEFAULT_PID                      0x1234
+#define EEPROM_DEFAULT_VID                      0x5678
+#define EEPROM_DEFAULT_CUSTOMERID               0xAB
+#define EEPROM_DEFAULT_SUBCUSTOMERID            0xCD
+#define EEPROM_DEFAULT_VERSION                  0
+
+#define EEPROM_CHANNEL_PLAN_FCC                 0x0
+#define EEPROM_CHANNEL_PLAN_IC                  0x1
+#define EEPROM_CHANNEL_PLAN_ETSI                0x2
+#define EEPROM_CHANNEL_PLAN_SPAIN               0x3
+#define EEPROM_CHANNEL_PLAN_FRANCE              0x4
+#define EEPROM_CHANNEL_PLAN_MKK                 0x5
+#define EEPROM_CHANNEL_PLAN_MKK1                0x6
+#define EEPROM_CHANNEL_PLAN_ISRAEL              0x7
+#define EEPROM_CHANNEL_PLAN_TELEC               0x8
+#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN       0x9
+#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13       0xA
+#define EEPROM_CHANNEL_PLAN_NCC                 0xB
+#define EEPROM_CHANNEL_PLAN_BY_HW_MASK          0x80
+
+#define EEPROM_CID_DEFAULT                      0x0
+#define EEPROM_CID_TOSHIBA                      0x4
+#define EEPROM_CID_CCX                          0x10
+#define EEPROM_CID_QMI                          0x0D
+#define EEPROM_CID_WHQL                         0xFE
+
+#define RTL8192_EEPROM_ID                       0x8129
+
+#define RTL8190_EEPROM_ID                       0x8129
+#define EEPROM_HPON                             0x02
+#define EEPROM_CLK                              0x06
+#define EEPROM_TESTR                            0x08
+
+#define EEPROM_VID                              0x0A
+#define EEPROM_DID                              0x0C
+#define EEPROM_SVID                             0x0E
+#define EEPROM_SMID                             0x10
+
+#define EEPROM_MAC_ADDR                         0x16
+
+#define EEPROM_CCK_TX_PWR_INX                   0x5A
+#define EEPROM_HT40_1S_TX_PWR_INX               0x60
+#define EEPROM_HT40_2S_TX_PWR_INX_DIFF          0x66
+#define EEPROM_HT20_TX_PWR_INX_DIFF             0x69
+#define EEPROM_OFDM_TX_PWR_INX_DIFF             0x6C
+#define EEPROM_HT40_MAX_PWR_OFFSET              0x6F
+#define EEPROM_HT20_MAX_PWR_OFFSET              0x72
+
+#define EEPROM_TSSI_A                           0x76
+#define EEPROM_TSSI_B                           0x77
+#define EEPROM_THERMAL_METER                    0x78
+#define EEPROM_XTAL_K                           0x78
+#define EEPROM_RF_OPT1                          0x79
+#define EEPROM_RF_OPT2                          0x7A
+#define EEPROM_RF_OPT3                          0x7B
+#define EEPROM_RF_OPT4                          0x7C
+#define EEPROM_CHANNEL_PLAN                     0x7D
+#define EEPROM_VERSION                          0x7E
+#define EEPROM_CUSTOMER_ID                      0x7F
+
+#define EEPROM_PWRDIFF                          0x54
+
+#define EEPROM_TXPOWERCCK                       0x5A
+#define EEPROM_TXPOWERHT40_1S                   0x60
+#define EEPROM_TXPOWERHT40_2SDIFF               0x66
+#define EEPROM_TXPOWERHT20DIFF                  0x69
+#define EEPROM_TXPOWER_OFDMDIFF                 0x6C
+
+#define EEPROM_TXPWR_GROUP                      0x6F
+
+#define EEPROM_TSSI_A                           0x76
+#define EEPROM_TSSI_B                           0x77
+#define EEPROM_THERMAL_METER                    0x78
+
+#define EEPROM_CHANNELPLAN                      0x75
+
+#define RF_OPTION1                              0x79
+#define RF_OPTION2                              0x7A
+#define RF_OPTION3                              0x7B
+#define RF_OPTION4                              0x7C
+
+#define STOPBECON                               BIT(6)
+#define STOPHIGHT                               BIT(5)
+#define STOPMGT                                 BIT(4)
+#define STOPVO                                  BIT(3)
+#define STOPVI                                  BIT(2)
+#define STOPBE                                  BIT(1)
+#define STOPBK                                  BIT(0)
+
+#define RCR_APPFCS                              BIT(31)
+#define RCR_APP_MIC                             BIT(30)
+#define RCR_APP_ICV                             BIT(29)
+#define RCR_APP_PHYST_RXFF                      BIT(28)
+#define RCR_APP_BA_SSN                          BIT(27)
+#define RCR_ENMBID                              BIT(24)
+#define RCR_LSIGEN                              BIT(23)
+#define RCR_MFBEN                               BIT(22)
+#define RCR_HTC_LOC_CTRL                        BIT(14)
+#define RCR_AMF                                 BIT(13)
+#define RCR_ACF                                 BIT(12)
+#define RCR_ADF                                 BIT(11)
+#define RCR_AICV                                BIT(9)
+#define RCR_ACRC32                              BIT(8)
+#define RCR_CBSSID_BCN                          BIT(7)
+#define RCR_CBSSID_DATA                         BIT(6)
+#define RCR_CBSSID                              RCR_CBSSID_DATA
+#define RCR_APWRMGT                             BIT(5)
+#define RCR_ADD3                                BIT(4)
+#define RCR_AB                                  BIT(3)
+#define RCR_AM                                  BIT(2)
+#define RCR_APM                                 BIT(1)
+#define RCR_AAP                                 BIT(0)
+#define RCR_MXDMA_OFFSET                        8
+#define RCR_FIFO_OFFSET                         13
+
+#define RSV_CTRL                                0x001C
+#define RD_CTRL                                 0x0524
+
+#define REG_USB_INFO                            0xFE17
+#define REG_USB_SPECIAL_OPTION                  0xFE55
+#define REG_USB_DMA_AGG_TO                      0xFE5B
+#define REG_USB_AGG_TO                          0xFE5C
+#define REG_USB_AGG_TH                          0xFE5D
+
+#define REG_USB_VID                             0xFE60
+#define REG_USB_PID                             0xFE62
+#define REG_USB_OPTIONAL                        0xFE64
+#define REG_USB_CHIRP_K                         0xFE65
+#define REG_USB_PHY                             0xFE66
+#define REG_USB_MAC_ADDR                        0xFE70
+#define REG_USB_HRPWM                           0xFE58
+#define REG_USB_HCPWM                           0xFE57
+
+#define SW18_FPWM                               BIT(3)
+
+#define ISO_MD2PP                               BIT(0)
+#define ISO_UA2USB                              BIT(1)
+#define ISO_UD2CORE                             BIT(2)
+#define ISO_PA2PCIE                             BIT(3)
+#define ISO_PD2CORE                             BIT(4)
+#define ISO_IP2MAC                              BIT(5)
+#define ISO_DIOP                                BIT(6)
+#define ISO_DIOE                                BIT(7)
+#define ISO_EB2CORE                             BIT(8)
+#define ISO_DIOR                                BIT(9)
+
+#define PWC_EV25V                               BIT(14)
+#define PWC_EV12V                               BIT(15)
+
+#define FEN_BBRSTB                              BIT(0)
+#define FEN_BB_GLB_RSTn                         BIT(1)
+#define FEN_USBA                                BIT(2)
+#define FEN_UPLL                                BIT(3)
+#define FEN_USBD                                BIT(4)
+#define FEN_DIO_PCIE                            BIT(5)
+#define FEN_PCIEA                               BIT(6)
+#define FEN_PPLL                                BIT(7)
+#define FEN_PCIED                               BIT(8)
+#define FEN_DIOE                                BIT(9)
+#define FEN_CPUEN                               BIT(10)
+#define FEN_DCORE                               BIT(11)
+#define FEN_ELDR                                BIT(12)
+#define FEN_DIO_RF                              BIT(13)
+#define FEN_HWPDN                               BIT(14)
+#define FEN_MREGEN                              BIT(15)
+
+#define PFM_LDALL                               BIT(0)
+#define PFM_ALDN                                BIT(1)
+#define PFM_LDKP                                BIT(2)
+#define PFM_WOWL                                BIT(3)
+#define EnPDN                                   BIT(4)
+#define PDN_PL                                  BIT(5)
+#define APFM_ONMAC                              BIT(8)
+#define APFM_OFF                                BIT(9)
+#define APFM_RSM                                BIT(10)
+#define AFSM_HSUS                               BIT(11)
+#define AFSM_PCIE                               BIT(12)
+#define APDM_MAC                                BIT(13)
+#define APDM_HOST                               BIT(14)
+#define APDM_HPDN                               BIT(15)
+#define RDY_MACON                               BIT(16)
+#define SUS_HOST                                BIT(17)
+#define ROP_ALD                                 BIT(20)
+#define ROP_PWR                                 BIT(21)
+#define ROP_SPS                                 BIT(22)
+#define SOP_MRST                                BIT(25)
+#define SOP_FUSE                                BIT(26)
+#define SOP_ABG                                 BIT(27)
+#define SOP_AMB                                 BIT(28)
+#define SOP_RCK                                 BIT(29)
+#define SOP_A8M                                 BIT(30)
+#define XOP_BTCK                                BIT(31)
+
+#define ANAD16V_EN                              BIT(0)
+#define ANA8M                                   BIT(1)
+#define MACSLP                                  BIT(4)
+#define LOADER_CLK_EN                           BIT(5)
+#define _80M_SSC_DIS                            BIT(7)
+#define _80M_SSC_EN_HO                          BIT(8)
+#define PHY_SSC_RSTB                            BIT(9)
+#define SEC_CLK_EN                              BIT(10)
+#define MAC_CLK_EN                              BIT(11)
+#define SYS_CLK_EN                              BIT(12)
+#define RING_CLK_EN                             BIT(13)
+
+#define BOOT_FROM_EEPROM                        BIT(4)
+#define EEPROM_EN                               BIT(5)
+
+#define AFE_BGEN                                BIT(0)
+#define AFE_MBEN                                BIT(1)
+#define MAC_ID_EN                               BIT(7)
+
+#define WLOCK_ALL                               BIT(0)
+#define WLOCK_00                                BIT(1)
+#define WLOCK_04                                BIT(2)
+#define WLOCK_08                                BIT(3)
+#define WLOCK_40                                BIT(4)
+#define R_DIS_PRST_0                            BIT(5)
+#define R_DIS_PRST_1                            BIT(6)
+#define LOCK_ALL_EN                             BIT(7)
+
+#define RF_EN                                   BIT(0)
+#define RF_RSTB                                 BIT(1)
+#define RF_SDMRSTB                              BIT(2)
+
+#define LDA15_EN                                BIT(0)
+#define LDA15_STBY                              BIT(1)
+#define LDA15_OBUF                              BIT(2)
+#define LDA15_REG_VOS                           BIT(3)
+#define _LDA15_VOADJ(x)                         (((x) & 0x7) << 4)
+
+#define LDV12_EN                                BIT(0)
+#define LDV12_SDBY                              BIT(1)
+#define LPLDO_HSM                               BIT(2)
+#define LPLDO_LSM_DIS                           BIT(3)
+#define _LDV12_VADJ(x)                          (((x) & 0xF) << 4)
+
+#define XTAL_EN                                 BIT(0)
+#define XTAL_BSEL                               BIT(1)
+#define _XTAL_BOSC(x)                           (((x) & 0x3) << 2)
+#define _XTAL_CADJ(x)                           (((x) & 0xF) << 4)
+#define XTAL_GATE_USB                           BIT(8)
+#define _XTAL_USB_DRV(x)                        (((x) & 0x3) << 9)
+#define XTAL_GATE_AFE                           BIT(11)
+#define _XTAL_AFE_DRV(x)                        (((x) & 0x3) << 12)
+#define XTAL_RF_GATE                            BIT(14)
+#define _XTAL_RF_DRV(x)                         (((x) & 0x3) << 15)
+#define XTAL_GATE_DIG                           BIT(17)
+#define _XTAL_DIG_DRV(x)                        (((x) & 0x3) << 18)
+#define XTAL_BT_GATE                            BIT(20)
+#define _XTAL_BT_DRV(x)                         (((x) & 0x3) << 21)
+#define _XTAL_GPIO(x)                           (((x) & 0x7) << 23)
+
+#define CKDLY_AFE                               BIT(26)
+#define CKDLY_USB                               BIT(27)
+#define CKDLY_DIG                               BIT(28)
+#define CKDLY_BT                                BIT(29)
+
+#define APLL_EN                                 BIT(0)
+#define APLL_320_EN                             BIT(1)
+#define APLL_FREF_SEL                           BIT(2)
+#define APLL_EDGE_SEL                           BIT(3)
+#define APLL_WDOGB                              BIT(4)
+#define APLL_LPFEN                              BIT(5)
+
+#define APLL_REF_CLK_13MHZ                      0x1
+#define APLL_REF_CLK_19_2MHZ                    0x2
+#define APLL_REF_CLK_20MHZ                      0x3
+#define APLL_REF_CLK_25MHZ                      0x4
+#define APLL_REF_CLK_26MHZ                      0x5
+#define APLL_REF_CLK_38_4MHZ                    0x6
+#define APLL_REF_CLK_40MHZ                      0x7
+
+#define APLL_320EN                              BIT(14)
+#define APLL_80EN                               BIT(15)
+#define APLL_1MEN                               BIT(24)
+
+#define ALD_EN                                  BIT(18)
+#define EF_PD                                   BIT(19)
+#define EF_FLAG                                 BIT(31)
+
+#define EF_TRPT                                 BIT(7)
+#define LDOE25_EN                               BIT(31)
+
+#define RSM_EN                                  BIT(0)
+#define Timer_EN                                BIT(4)
+
+#define TRSW0EN                                 BIT(2)
+#define TRSW1EN                                 BIT(3)
+#define EROM_EN                                 BIT(4)
+#define EnBT                                    BIT(5)
+#define EnUart                                  BIT(8)
+#define Uart_910                                BIT(9)
+#define EnPMAC                                  BIT(10)
+#define SIC_SWRST                               BIT(11)
+#define EnSIC                                   BIT(12)
+#define SIC_23                                  BIT(13)
+#define EnHDP                                   BIT(14)
+#define SIC_LBK                                 BIT(15)
+
+#define LED0PL                                  BIT(4)
+#define LED1PL                                  BIT(12)
+#define LED0DIS                                 BIT(7)
+
+#define MCUFWDL_EN                              BIT(0)
+#define MCUFWDL_RDY                             BIT(1)
+#define FWDL_ChkSum_rpt                         BIT(2)
+#define MACINI_RDY                              BIT(3)
+#define BBINI_RDY                               BIT(4)
+#define RFINI_RDY                               BIT(5)
+#define WINTINI_RDY                             BIT(6)
+#define CPRST                                   BIT(23)
+
+#define XCLK_VLD                                BIT(0)
+#define ACLK_VLD                                BIT(1)
+#define UCLK_VLD                                BIT(2)
+#define PCLK_VLD                                BIT(3)
+#define PCIRSTB                                 BIT(4)
+#define V15_VLD                                 BIT(5)
+#define TRP_B15V_EN                             BIT(7)
+#define SIC_IDLE                                BIT(8)
+#define BD_MAC2                                 BIT(9)
+#define BD_MAC1                                 BIT(10)
+#define IC_MACPHY_MODE                          BIT(11)
+#define PAD_HWPD_IDN                            BIT(22)
+#define TRP_VAUX_EN                             BIT(23)
+#define TRP_BT_EN                               BIT(24)
+#define BD_PKG_SEL                              BIT(25)
+#define BD_HCI_SEL                              BIT(26)
+#define TYPE_ID                                 BIT(27)
+
+#define CHIP_VER_RTL_MASK                       0xF000
+#define CHIP_VER_RTL_SHIFT                      12
+
+#define REG_LBMODE                              (REG_CR + 3)
+
+#define HCI_TXDMA_EN                            BIT(0)
+#define HCI_RXDMA_EN                            BIT(1)
+#define TXDMA_EN                                BIT(2)
+#define RXDMA_EN                                BIT(3)
+#define PROTOCOL_EN                             BIT(4)
+#define SCHEDULE_EN                             BIT(5)
+#define MACTXEN                                 BIT(6)
+#define MACRXEN                                 BIT(7)
+#define ENSWBCN                                 BIT(8)
+#define ENSEC                                   BIT(9)
+
+#define _NETTYPE(x)                             (((x) & 0x3) << 16)
+#define MASK_NETTYPE                            0x30000
+#define NT_NO_LINK                              0x0
+#define NT_LINK_AD_HOC                          0x1
+#define NT_LINK_AP                              0x2
+#define NT_AS_AP                                0x3
+
+#define _LBMODE(x)                              (((x) & 0xF) << 24)
+#define MASK_LBMODE                             0xF000000
+#define LOOPBACK_NORMAL                         0x0
+#define LOOPBACK_IMMEDIATELY                    0xB
+#define LOOPBACK_MAC_DELAY                      0x3
+#define LOOPBACK_PHY                            0x1
+#define LOOPBACK_DMA                            0x7
+
+#define GET_RX_PAGE_SIZE(value)         ((value) & 0xF)
+#define GET_TX_PAGE_SIZE(value)         (((value) & 0xF0) >> 4)
+#define _PSRX_MASK                              0xF
+#define _PSTX_MASK                              0xF0
+#define _PSRX(x)                                (x)
+#define _PSTX(x)                                ((x) << 4)
+
+#define PBP_64                                  0x0
+#define PBP_128                                 0x1
+#define PBP_256                                 0x2
+#define PBP_512                                 0x3
+#define PBP_1024                                0x4
+
+#define RXDMA_ARBBW_EN                          BIT(0)
+#define RXSHFT_EN                               BIT(1)
+#define RXDMA_AGG_EN                            BIT(2)
+#define QS_VO_QUEUE                             BIT(8)
+#define QS_VI_QUEUE                             BIT(9)
+#define QS_BE_QUEUE                             BIT(10)
+#define QS_BK_QUEUE                             BIT(11)
+#define QS_MANAGER_QUEUE                        BIT(12)
+#define QS_HIGH_QUEUE                           BIT(13)
+
+#define HQSEL_VOQ                               BIT(0)
+#define HQSEL_VIQ                               BIT(1)
+#define HQSEL_BEQ                               BIT(2)
+#define HQSEL_BKQ                               BIT(3)
+#define HQSEL_MGTQ                              BIT(4)
+#define HQSEL_HIQ                               BIT(5)
+
+#define _TXDMA_HIQ_MAP(x)                       (((x)&0x3) << 14)
+#define _TXDMA_MGQ_MAP(x)                       (((x)&0x3) << 12)
+#define _TXDMA_BKQ_MAP(x)                       (((x)&0x3) << 10)
+#define _TXDMA_BEQ_MAP(x)                       (((x)&0x3) <<  8)
+#define _TXDMA_VIQ_MAP(x)                       (((x)&0x3) <<  6)
+#define _TXDMA_VOQ_MAP(x)                       (((x)&0x3) <<  4)
+
+#define QUEUE_LOW                               1
+#define QUEUE_NORMAL                            2
+#define QUEUE_HIGH                              3
+
+#define _LLT_NO_ACTIVE                          0x0
+#define _LLT_WRITE_ACCESS                       0x1
+#define _LLT_READ_ACCESS                        0x2
+
+#define _LLT_INIT_DATA(x)                       ((x) & 0xFF)
+#define _LLT_INIT_ADDR(x)                       (((x) & 0xFF) << 8)
+#define _LLT_OP(x)                              (((x) & 0x3) << 30)
+#define _LLT_OP_VALUE(x)                        (((x) >> 30) & 0x3)
+
+#define BB_WRITE_READ_MASK                      (BIT(31) | BIT(30))
+#define BB_WRITE_EN                             BIT(30)
+#define BB_READ_EN                              BIT(31)
+
+#define _HPQ(x)                                 ((x) & 0xFF)
+#define _LPQ(x)                                 (((x) & 0xFF) << 8)
+#define _PUBQ(x)                                (((x) & 0xFF) << 16)
+#define _NPQ(x)                                 ((x) & 0xFF)
+
+#define HPQ_PUBLIC_DIS                          BIT(24)
+#define LPQ_PUBLIC_DIS                          BIT(25)
+#define LD_RQPN                                 BIT(31)
+
+#define BCN_VALID                               BIT(16)
+#define BCN_HEAD(x)                             (((x) & 0xFF) << 8)
+#define BCN_HEAD_MASK                           0xFF00
+
+#define BLK_DESC_NUM_SHIFT                      4
+#define BLK_DESC_NUM_MASK                       0xF
+
+#define DROP_DATA_EN                            BIT(9)
+
+#define EN_AMPDU_RTY_NEW                        BIT(7)
+
+#define _INIRTSMCS_SEL(x)                       ((x) & 0x3F)
+
+#define _SPEC_SIFS_CCK(x)                       ((x) & 0xFF)
+#define _SPEC_SIFS_OFDM(x)                      (((x) & 0xFF) << 8)
+
+#define RATE_REG_BITMAP_ALL                     0xFFFFF
+
+#define _RRSC_BITMAP(x)                         ((x) & 0xFFFFF)
+
+#define _RRSR_RSC(x)                            (((x) & 0x3) << 21)
+#define RRSR_RSC_RESERVED                       0x0
+#define RRSR_RSC_UPPER_SUBCHANNEL               0x1
+#define RRSR_RSC_LOWER_SUBCHANNEL               0x2
+#define RRSR_RSC_DUPLICATE_MODE                 0x3
+
+#define USE_SHORT_G1                            BIT(20)
+
+#define _AGGLMT_MCS0(x)                         ((x) & 0xF)
+#define _AGGLMT_MCS1(x)                         (((x) & 0xF) << 4)
+#define _AGGLMT_MCS2(x)                         (((x) & 0xF) << 8)
+#define _AGGLMT_MCS3(x)                         (((x) & 0xF) << 12)
+#define _AGGLMT_MCS4(x)                         (((x) & 0xF) << 16)
+#define _AGGLMT_MCS5(x)                         (((x) & 0xF) << 20)
+#define _AGGLMT_MCS6(x)                         (((x) & 0xF) << 24)
+#define _AGGLMT_MCS7(x)                         (((x) & 0xF) << 28)
+
+#define RETRY_LIMIT_SHORT_SHIFT                 8
+#define RETRY_LIMIT_LONG_SHIFT                  0
+
+#define _DARF_RC1(x)                            ((x) & 0x1F)
+#define _DARF_RC2(x)                            (((x) & 0x1F) << 8)
+#define _DARF_RC3(x)                            (((x) & 0x1F) << 16)
+#define _DARF_RC4(x)                            (((x) & 0x1F) << 24)
+#define _DARF_RC5(x)                            ((x) & 0x1F)
+#define _DARF_RC6(x)                            (((x) & 0x1F) << 8)
+#define _DARF_RC7(x)                            (((x) & 0x1F) << 16)
+#define _DARF_RC8(x)                            (((x) & 0x1F) << 24)
+
+#define _RARF_RC1(x)                            ((x) & 0x1F)
+#define _RARF_RC2(x)                            (((x) & 0x1F) << 8)
+#define _RARF_RC3(x)                            (((x) & 0x1F) << 16)
+#define _RARF_RC4(x)                            (((x) & 0x1F) << 24)
+#define _RARF_RC5(x)                            ((x) & 0x1F)
+#define _RARF_RC6(x)                            (((x) & 0x1F) << 8)
+#define _RARF_RC7(x)                            (((x) & 0x1F) << 16)
+#define _RARF_RC8(x)                            (((x) & 0x1F) << 24)
+
+#define AC_PARAM_TXOP_LIMIT_OFFSET              16
+#define AC_PARAM_ECW_MAX_OFFSET                 12
+#define AC_PARAM_ECW_MIN_OFFSET                 8
+#define AC_PARAM_AIFS_OFFSET                    0
+
+#define _AIFS(x)                                (x)
+#define _ECW_MAX_MIN(x)                         ((x) << 8)
+#define _TXOP_LIMIT(x)                          ((x) << 16)
+
+#define _BCNIFS(x)                              ((x) & 0xFF)
+#define _BCNECW(x)                              ((((x) & 0xF)) << 8)
+
+#define _LRL(x)                                 ((x) & 0x3F)
+#define _SRL(x)                                 (((x) & 0x3F) << 8)
+
+#define _SIFS_CCK_CTX(x)                        ((x) & 0xFF)
+#define _SIFS_CCK_TRX(x)                        (((x) & 0xFF) << 8);
+
+#define _SIFS_OFDM_CTX(x)                       ((x) & 0xFF)
+#define _SIFS_OFDM_TRX(x)                       (((x) & 0xFF) << 8);
+
+#define _TBTT_PROHIBIT_HOLD(x)                  (((x) & 0xFF) << 8)
+
+#define DIS_EDCA_CNT_DWN                        BIT(11)
+
+#define EN_MBSSID                               BIT(1)
+#define EN_TXBCN_RPT                            BIT(2)
+#define EN_BCN_FUNCTION                         BIT(3)
+
+#define TSFTR_RST                               BIT(0)
+#define TSFTR1_RST                              BIT(1)
+
+#define STOP_BCNQ                               BIT(6)
+
+#define DIS_TSF_UDT0_NORMAL_CHIP                BIT(4)
+#define DIS_TSF_UDT0_TEST_CHIP                  BIT(5)
+
+#define AcmHw_HwEn                              BIT(0)
+#define AcmHw_BeqEn                             BIT(1)
+#define AcmHw_ViqEn                             BIT(2)
+#define AcmHw_VoqEn                             BIT(3)
+#define AcmHw_BeqStatus                         BIT(4)
+#define AcmHw_ViqStatus                         BIT(5)
+#define AcmHw_VoqStatus                         BIT(6)
+
+#define APSDOFF                                 BIT(6)
+#define APSDOFF_STATUS                          BIT(7)
+
+#define BW_20MHZ                                BIT(2)
+
+#define RATE_BITMAP_ALL                         0xFFFFF
+
+#define RATE_RRSR_CCK_ONLY_1M                   0xFFFF1
+
+#define TSFRST                                  BIT(0)
+#define DIS_GCLK                                BIT(1)
+#define PAD_SEL                                 BIT(2)
+#define PWR_ST                                  BIT(6)
+#define PWRBIT_OW_EN                            BIT(7)
+#define ACRC                                    BIT(8)
+#define CFENDFORM                               BIT(9)
+#define ICV                                     BIT(10)
+
+#define AAP                                     BIT(0)
+#define APM                                     BIT(1)
+#define AM                                      BIT(2)
+#define AB                                      BIT(3)
+#define ADD3                                    BIT(4)
+#define APWRMGT                                 BIT(5)
+#define CBSSID                                  BIT(6)
+#define CBSSID_DATA                             BIT(6)
+#define CBSSID_BCN                              BIT(7)
+#define ACRC32                                  BIT(8)
+#define AICV                                    BIT(9)
+#define ADF                                     BIT(11)
+#define ACF                                     BIT(12)
+#define AMF                                     BIT(13)
+#define HTC_LOC_CTRL                            BIT(14)
+#define UC_DATA_EN                              BIT(16)
+#define BM_DATA_EN                              BIT(17)
+#define MFBEN                                   BIT(22)
+#define LSIGEN                                  BIT(23)
+#define EnMBID                                  BIT(24)
+#define APP_BASSN                               BIT(27)
+#define APP_PHYSTS                              BIT(28)
+#define APP_ICV                                 BIT(29)
+#define APP_MIC                                 BIT(30)
+#define APP_FCS                                 BIT(31)
+
+#define _MIN_SPACE(x)                           ((x) & 0x7)
+#define _SHORT_GI_PADDING(x)                    (((x) & 0x1F) << 3)
+
+#define RXERR_TYPE_OFDM_PPDU                    0
+#define RXERR_TYPE_OFDM_FALSE_ALARM             1
+#define RXERR_TYPE_OFDM_MPDU_OK                 2
+#define RXERR_TYPE_OFDM_MPDU_FAIL               3
+#define RXERR_TYPE_CCK_PPDU                     4
+#define RXERR_TYPE_CCK_FALSE_ALARM              5
+#define RXERR_TYPE_CCK_MPDU_OK                  6
+#define RXERR_TYPE_CCK_MPDU_FAIL                7
+#define RXERR_TYPE_HT_PPDU                      8
+#define RXERR_TYPE_HT_FALSE_ALARM               9
+#define RXERR_TYPE_HT_MPDU_TOTAL                10
+#define RXERR_TYPE_HT_MPDU_OK                   11
+#define RXERR_TYPE_HT_MPDU_FAIL                 12
+#define RXERR_TYPE_RX_FULL_DROP                 15
+
+#define RXERR_COUNTER_MASK                      0xFFFFF
+#define RXERR_RPT_RST                           BIT(27)
+#define _RXERR_RPT_SEL(type)                    ((type) << 28)
+
+#define SCR_TxUseDK                             BIT(0)
+#define SCR_RxUseDK                             BIT(1)
+#define SCR_TxEncEnable                         BIT(2)
+#define SCR_RxDecEnable                         BIT(3)
+#define SCR_SKByA2                              BIT(4)
+#define SCR_NoSKMC                              BIT(5)
+#define SCR_TXBCUSEDK                           BIT(6)
+#define SCR_RXBCUSEDK                           BIT(7)
+
+#define USB_IS_HIGH_SPEED                       0
+#define USB_IS_FULL_SPEED                       1
+#define USB_SPEED_MASK                          BIT(5)
+
+#define USB_NORMAL_SIE_EP_MASK                  0xF
+#define USB_NORMAL_SIE_EP_SHIFT                 4
+
+#define USB_TEST_EP_MASK                        0x30
+#define USB_TEST_EP_SHIFT                       4
+
+#define USB_AGG_EN                              BIT(3)
+
+#define MAC_ADDR_LEN                            6
+#define LAST_ENTRY_OF_TX_PKT_BUFFER             255
+
+#define POLLING_LLT_THRESHOLD                   20
+#define POLLING_READY_TIMEOUT_COUNT             1000
+
+#define MAX_MSS_DENSITY_2T                      0x13
+#define MAX_MSS_DENSITY_1T                      0x0A
+
+#define EPROM_CMD_OPERATING_MODE_MASK   ((1<<7)|(1<<6))
+#define EPROM_CMD_CONFIG                        0x3
+#define EPROM_CMD_LOAD                          1
+
+#define HWSET_MAX_SIZE_92S              HWSET_MAX_SIZE
+
+#define HAL_8192C_HW_GPIO_WPS_BIT               BIT(2)
+
+#define RPMAC_RESET                             0x100
+#define RPMAC_TXSTART                           0x104
+#define RPMAC_TXLEGACYSIG                       0x108
+#define RPMAC_TXHTSIG1                          0x10c
+#define RPMAC_TXHTSIG2                          0x110
+#define RPMAC_PHYDEBUG                          0x114
+#define RPMAC_TXPACKETNUM                       0x118
+#define RPMAC_TXIDLE                            0x11c
+#define RPMAC_TXMACHEADER0                      0x120
+#define RPMAC_TXMACHEADER1                      0x124
+#define RPMAC_TXMACHEADER2                      0x128
+#define RPMAC_TXMACHEADER3                      0x12c
+#define RPMAC_TXMACHEADER4                      0x130
+#define RPMAC_TXMACHEADER5                      0x134
+#define RPMAC_TXDADATYPE                        0x138
+#define RPMAC_TXRANDOMSEED                      0x13c
+#define RPMAC_CCKPLCPPREAMBLE                   0x140
+#define RPMAC_CCKPLCPHEADER                     0x144
+#define RPMAC_CCKCRC16                          0x148
+#define RPMAC_OFDMRXCRC32OK                     0x170
+#define RPMAC_OFDMRXCRC32Er                     0x174
+#define RPMAC_OFDMRXPARITYER                    0x178
+#define RPMAC_OFDMRXCRC8ER                      0x17c
+#define RPMAC_CCKCRXRC16ER                      0x180
+#define RPMAC_CCKCRXRC32ER                      0x184
+#define RPMAC_CCKCRXRC32OK                      0x188
+#define RPMAC_TXSTATUS                          0x18c
+
+#define RFPGA0_RFMOD                            0x800
+
+#define RFPGA0_TXINFO                           0x804
+#define RFPGA0_PSDFUNCTION                      0x808
+
+#define RFPGA0_TXGAINSTAGE                      0x80c
+
+#define RFPGA0_RFTIMING1                        0x810
+#define RFPGA0_RFTIMING2                        0x814
+
+#define RFPGA0_XA_HSSIPARAMETER1                0x820
+#define RFPGA0_XA_HSSIPARAMETER2                0x824
+#define RFPGA0_XB_HSSIPARAMETER1                0x828
+#define RFPGA0_XB_HSSIPARAMETER2                0x82c
+
+#define RFPGA0_XA_LSSIPARAMETER                 0x840
+#define RFPGA0_XB_LSSIPARAMETER                 0x844
+
+#define RFPGA0_RFWAKEUPPARAMETER                0x850
+#define RFPGA0_RFSLEEPUPPARAMETER               0x854
+
+#define RFPGA0_XAB_SWITCHCONTROL                0x858
+#define RFPGA0_XCD_SWITCHCONTROL                0x85c
+
+#define RFPGA0_XA_RFINTERFACEOE                 0x860
+#define RFPGA0_XB_RFINTERFACEOE                 0x864
+
+#define RFPGA0_XAB_RFINTERFACESW                0x870
+#define RFPGA0_XCD_RFINTERFACESW                0x874
+
+#define rFPGA0_XAB_RFPARAMETER                  0x878
+#define rFPGA0_XCD_RFPARAMETER                  0x87c
+
+#define RFPGA0_ANALOGPARAMETER1                 0x880
+#define RFPGA0_ANALOGPARAMETER2                 0x884
+#define RFPGA0_ANALOGPARAMETER3                 0x888
+#define RFPGA0_ANALOGPARAMETER4                 0x88c
+
+#define RFPGA0_XA_LSSIREADBACK                  0x8a0
+#define RFPGA0_XB_LSSIREADBACK                  0x8a4
+#define RFPGA0_XC_LSSIREADBACK                  0x8a8
+#define RFPGA0_XD_LSSIREADBACK                  0x8ac
+
+#define RFPGA0_PSDREPORT                        0x8b4
+#define TRANSCEIVEA_HSPI_READBACK               0x8b8
+#define TRANSCEIVEB_HSPI_READBACK               0x8bc
+#define RFPGA0_XAB_RFINTERFACERB                0x8e0
+#define RFPGA0_XCD_RFINTERFACERB                0x8e4
+
+#define RFPGA1_RFMOD                            0x900
+
+#define RFPGA1_TXBLOCK                          0x904
+#define RFPGA1_DEBUGSELECT                      0x908
+#define RFPGA1_TXINFO                           0x90c
+
+#define RCCK0_SYSTEM                            0xa00
+
+#define RCCK0_AFESETTING                        0xa04
+#define RCCK0_CCA                               0xa08
+
+#define RCCK0_RXAGC1                            0xa0c
+#define RCCK0_RXAGC2                            0xa10
+
+#define RCCK0_RXHP                              0xa14
+
+#define RCCK0_DSPPARAMETER1                     0xa18
+#define RCCK0_DSPPARAMETER2                     0xa1c
+
+#define RCCK0_TXFILTER1                         0xa20
+#define RCCK0_TXFILTER2                         0xa24
+#define RCCK0_DEBUGPORT                         0xa28
+#define RCCK0_FALSEALARMREPORT                  0xa2c
+#define RCCK0_TRSSIREPORT                       0xa50
+#define RCCK0_RXREPORT                          0xa54
+#define RCCK0_FACOUNTERLOWER                    0xa5c
+#define RCCK0_FACOUNTERUPPER                    0xa58
+
+#define ROFDM0_LSTF                             0xc00
+
+#define ROFDM0_TRXPATHENABLE                    0xc04
+#define ROFDM0_TRMUXPAR                         0xc08
+#define ROFDM0_TRSWISOLATION                    0xc0c
+
+#define ROFDM0_XARXAFE                          0xc10
+#define ROFDM0_XARXIQIMBALANCE                  0xc14
+#define ROFDM0_XBRXAFE                          0xc18
+#define ROFDM0_XBRXIQIMBALANCE                  0xc1c
+#define ROFDM0_XCRXAFE                          0xc20
+#define ROFDM0_XCRXIQIMBANLANCE                 0xc24
+#define ROFDM0_XDRXAFE                          0xc28
+#define ROFDM0_XDRXIQIMBALANCE                  0xc2c
+
+#define ROFDM0_RXDETECTOR1                      0xc30
+#define ROFDM0_RXDETECTOR2                      0xc34
+#define ROFDM0_RXDETECTOR3                      0xc38
+#define ROFDM0_RXDETECTOR4                      0xc3c
+
+#define ROFDM0_RXDSP                            0xc40
+#define ROFDM0_CFOANDDAGC                       0xc44
+#define ROFDM0_CCADROPTHRESHOLD                 0xc48
+#define ROFDM0_ECCATHRESHOLD                    0xc4c
+
+#define ROFDM0_XAAGCCORE1                       0xc50
+#define ROFDM0_XAAGCCORE2                       0xc54
+#define ROFDM0_XBAGCCORE1                       0xc58
+#define ROFDM0_XBAGCCORE2                       0xc5c
+#define ROFDM0_XCAGCCORE1                       0xc60
+#define ROFDM0_XCAGCCORE2                       0xc64
+#define ROFDM0_XDAGCCORE1                       0xc68
+#define ROFDM0_XDAGCCORE2                       0xc6c
+
+#define ROFDM0_AGCPARAMETER1                    0xc70
+#define ROFDM0_AGCPARAMETER2                    0xc74
+#define ROFDM0_AGCRSSITABLE                     0xc78
+#define ROFDM0_HTSTFAGC                         0xc7c
+
+#define ROFDM0_XATXIQIMBALANCE                  0xc80
+#define ROFDM0_XATXAFE                          0xc84
+#define ROFDM0_XBTXIQIMBALANCE                  0xc88
+#define ROFDM0_XBTXAFE                          0xc8c
+#define ROFDM0_XCTXIQIMBALANCE                  0xc90
+#define ROFDM0_XCTXAFE                          0xc94
+#define ROFDM0_XDTXIQIMBALANCE                  0xc98
+#define ROFDM0_XDTXAFE                          0xc9c
+
+#define ROFDM0_RXIQEXTANTA                      0xca0
+
+#define ROFDM0_RXHPPARAMETER                    0xce0
+#define ROFDM0_TXPSEUDONOISEWGT                 0xce4
+#define ROFDM0_FRAMESYNC                        0xcf0
+#define ROFDM0_DFSREPORT                        0xcf4
+#define ROFDM0_TXCOEFF1                         0xca4
+#define ROFDM0_TXCOEFF2                         0xca8
+#define ROFDM0_TXCOEFF3                         0xcac
+#define ROFDM0_TXCOEFF4                         0xcb0
+#define ROFDM0_TXCOEFF5                         0xcb4
+#define ROFDM0_TXCOEFF6                         0xcb8
+
+#define ROFDM1_LSTF                             0xd00
+#define ROFDM1_TRXPATHENABLE                    0xd04
+
+#define ROFDM1_CF0                              0xd08
+#define ROFDM1_CSI1                             0xd10
+#define ROFDM1_SBD                              0xd14
+#define ROFDM1_CSI2                             0xd18
+#define ROFDM1_CFOTRACKING                      0xd2c
+#define ROFDM1_TRXMESAURE1                      0xd34
+#define ROFDM1_INTFDET                          0xd3c
+#define ROFDM1_PSEUDONOISESTATEAB               0xd50
+#define ROFDM1_PSEUDONOISESTATECD               0xd54
+#define ROFDM1_RXPSEUDONOISEWGT                 0xd58
+
+#define ROFDM_PHYCOUNTER1                       0xda0
+#define ROFDM_PHYCOUNTER2                       0xda4
+#define ROFDM_PHYCOUNTER3                       0xda8
+
+#define ROFDM_SHORTCFOAB                        0xdac
+#define ROFDM_SHORTCFOCD                        0xdb0
+#define ROFDM_LONGCFOAB                         0xdb4
+#define ROFDM_LONGCFOCD                         0xdb8
+#define ROFDM_TAILCF0AB                         0xdbc
+#define ROFDM_TAILCF0CD                         0xdc0
+#define ROFDM_PWMEASURE1                        0xdc4
+#define ROFDM_PWMEASURE2                        0xdc8
+#define ROFDM_BWREPORT                          0xdcc
+#define ROFDM_AGCREPORT                         0xdd0
+#define ROFDM_RXSNR                             0xdd4
+#define ROFDM_RXEVMCSI                          0xdd8
+#define ROFDM_SIGREPORT                         0xddc
+
+#define RTXAGC_A_RATE18_06                      0xe00
+#define RTXAGC_A_RATE54_24                      0xe04
+#define RTXAGC_A_CCK1_MCS32                     0xe08
+#define RTXAGC_A_MCS03_MCS00                    0xe10
+#define RTXAGC_A_MCS07_MCS04                    0xe14
+#define RTXAGC_A_MCS11_MCS08                    0xe18
+#define RTXAGC_A_MCS15_MCS12                    0xe1c
+
+#define RTXAGC_B_RATE18_06                      0x830
+#define RTXAGC_B_RATE54_24                      0x834
+#define RTXAGC_B_CCK1_55_MCS32                  0x838
+#define RTXAGC_B_MCS03_MCS00                    0x83c
+#define RTXAGC_B_MCS07_MCS04                    0x848
+#define RTXAGC_B_MCS11_MCS08                    0x84c
+#define RTXAGC_B_MCS15_MCS12                    0x868
+#define RTXAGC_B_CCK11_A_CCK2_11                0x86c
+
+#define RZEBRA1_HSSIENABLE                      0x0
+#define RZEBRA1_TRXENABLE1                      0x1
+#define RZEBRA1_TRXENABLE2                      0x2
+#define RZEBRA1_AGC                             0x4
+#define RZEBRA1_CHARGEPUMP                      0x5
+#define RZEBRA1_CHANNEL                         0x7
+
+#define RZEBRA1_TXGAIN                          0x8
+#define RZEBRA1_TXLPF                           0x9
+#define RZEBRA1_RXLPF                           0xb
+#define RZEBRA1_RXHPFCORNER                     0xc
+
+#define RGLOBALCTRL                             0
+#define RRTL8256_TXLPF                          19
+#define RRTL8256_RXLPF                          11
+#define RRTL8258_TXLPF                          0x11
+#define RRTL8258_RXLPF                          0x13
+#define RRTL8258_RSSILPF                        0xa
+
+#define RF_AC                                   0x00
+
+#define RF_IQADJ_G1                             0x01
+#define RF_IQADJ_G2                             0x02
+#define RF_POW_TRSW                             0x05
+
+#define RF_GAIN_RX                              0x06
+#define RF_GAIN_TX                              0x07
+
+#define RF_TXM_IDAC                             0x08
+#define RF_BS_IQGEN                             0x0F
+
+#define RF_MODE1                                0x10
+#define RF_MODE2                                0x11
+
+#define RF_RX_AGC_HP                            0x12
+#define RF_TX_AGC                               0x13
+#define RF_BIAS                                 0x14
+#define RF_IPA                                  0x15
+#define RF_POW_ABILITY                          0x17
+#define RF_MODE_AG                              0x18
+#define RRFCHANNEL                              0x18
+#define RF_CHNLBW                               0x18
+#define RF_TOP                                  0x19
+
+#define RF_RX_G1                                0x1A
+#define RF_RX_G2                                0x1B
+
+#define RF_RX_BB2                               0x1C
+#define RF_RX_BB1                               0x1D
+
+#define RF_RCK1                                 0x1E
+#define RF_RCK2                                 0x1F
+
+#define RF_TX_G1                                0x20
+#define RF_TX_G2                                0x21
+#define RF_TX_G3                                0x22
+
+#define RF_TX_BB1                               0x23
+#define RF_T_METER                              0x24
+
+#define RF_SYN_G1                               0x25
+#define RF_SYN_G2                               0x26
+#define RF_SYN_G3                               0x27
+#define RF_SYN_G4                               0x28
+#define RF_SYN_G5                               0x29
+#define RF_SYN_G6                               0x2A
+#define RF_SYN_G7                               0x2B
+#define RF_SYN_G8                               0x2C
+
+#define RF_RCK_OS                               0x30
+#define RF_TXPA_G1                              0x31
+#define RF_TXPA_G2                              0x32
+#define RF_TXPA_G3                              0x33
+
+#define BBBRESETB                               0x100
+#define BGLOBALRESETB                           0x200
+#define BOFDMTXSTART                            0x4
+#define BCCKTXSTART                             0x8
+#define BCRC32DEBUG                             0x100
+#define BPMACLOOPBACK                           0x10
+#define BTXLSIG                                 0xffffff
+#define BOFDMTXRATE                             0xf
+#define BOFDMTXRESERVED                         0x10
+#define BOFDMTXLENGTH                           0x1ffe0
+#define BOFDMTXPARITY                           0x20000
+#define BTXHTSIG1                               0xffffff
+#define BTXHTMCSRATE                            0x7f
+#define BTXHTBW                                 0x80
+#define BTXHTLENGTH                             0xffff00
+#define BTXHTSIG2                               0xffffff
+#define BTXHTSMOOTHING                          0x1
+#define BTXHTSOUNDING                           0x2
+#define BTXHTRESERVED                           0x4
+#define BTXHTAGGREATION                         0x8
+#define BTXHTSTBC                               0x30
+#define BTXHTADVANCECODING                      0x40
+#define BTXHTSHORTGI                            0x80
+#define BTXHTNUMBERHT_LT        F               0x300
+#define BTXHTCRC8                               0x3fc00
+#define BCOUNTERRESET                           0x10000
+#define BNUMOFOFDMTX                            0xffff
+#define BNUMOFCCKTX                             0xffff0000
+#define BTXIDLEINTERVAL                         0xffff
+#define BOFDMSERVICE                            0xffff0000
+#define BTXMACHEADER                            0xffffffff
+#define BTXDATAINIT                             0xff
+#define BTXHTMODE                               0x100
+#define BTXDATATYPE                             0x30000
+#define BTXRANDOMSEED                           0xffffffff
+#define BCCKTXPREAMBLE                          0x1
+#define BCCKTXSFD                               0xffff0000
+#define BCCKTXSIG                               0xff
+#define BCCKTXSERVICE                           0xff00
+#define BCCKLENGTHEXT                           0x8000
+#define BCCKTXLENGHT                            0xffff0000
+#define BCCKTXCRC16                             0xffff
+#define BCCKTXSTATUS                            0x1
+#define BOFDMTXSTATUS                           0x2
+#define IS_BB_REG_OFFSET_92S(_Offset)           \
+        ((_Offset >= 0x800) && (_Offset <= 0xfff))
+
+#define BRFMOD                                  0x1
+#define BJAPANMODE                              0x2
+#define BCCKTXSC                                0x30
+#define BCCKEN                                  0x1000000
+#define BOFDMEN                                 0x2000000
+
+#define BOFDMRXADCPHASE                         0x10000
+#define BOFDMTXDACPHASE                         0x40000
+#define BXATXAGC                                0x3f
+
+#define BXBTXAGC                                0xf00
+#define BXCTXAGC                                0xf000
+#define BXDTXAGC                                0xf0000
+
+#define BPASTART                                0xf0000000
+#define BTRSTART                                0x00f00000
+#define BRFSTART                                0x0000f000
+#define BBBSTART                                0x000000f0
+#define BBBCCKSTART                             0x0000000f
+#define BPAEND                                  0xf
+#define BTREND                                  0x0f000000
+#define BRFEND                                  0x000f0000
+#define BCCAMASK                                0x000000f0
+#define BR2RCCAMASK                             0x00000f00
+#define BHSSI_R2TDELAY                          0xf8000000
+#define BHSSI_T2RDELAY                          0xf80000
+#define BCONTXHSSI                              0x400
+#define BIGFROMCCK                              0x200
+#define BAGCADDRESS                             0x3f
+#define BRXHPTX                                 0x7000
+#define BRXHP2RX                                0x38000
+#define BRXHPCCKINI                             0xc0000
+#define BAGCTXCODE                              0xc00000
+#define BAGCRXCODE                              0x300000
+
+#define B3WIREDATALENGTH                        0x800
+#define B3WIREADDREAALENGTH                     0x400
+
+#define B3WIRERFPOWERDOWN                       0x1
+#define B5GPAPEPOLARITY                         0x40000000
+#define B2GPAPEPOLARITY                         0x80000000
+#define BRFSW_TXDEFAULTANT                      0x3
+#define BRFSW_TXOPTIONANT                       0x30
+#define BRFSW_RXDEFAULTANT                      0x300
+#define BRFSW_RXOPTIONANT                       0x3000
+#define BRFSI_3WIREDATA                         0x1
+#define BRFSI_3WIRECLOCK                        0x2
+#define BRFSI_3WIRELOAD                         0x4
+#define BRFSI_3WIRERW                           0x8
+#define BRFSI_3WIRE                             0xf
+
+#define BRFSI_RFENV                             0x10
+
+#define BRFSI_TRSW                              0x20
+#define BRFSI_TRSWB                             0x40
+#define BRFSI_ANTSW                             0x100
+#define BRFSI_ANTSWB                            0x200
+#define BRFSI_PAPE                              0x400
+#define BRFSI_PAPE5G                            0x800
+#define BBANDSELECT                             0x1
+#define BHTSIG2_GI                              0x80
+#define BHTSIG2_SMOOTHING                       0x01
+#define BHTSIG2_SOUNDING                        0x02
+#define BHTSIG2_AGGREATON                       0x08
+#define BHTSIG2_STBC                            0x30
+#define BHTSIG2_ADVCODING                       0x40
+#define BHTSIG2_NUMOFHTLTF                      0x300
+#define BHTSIG2_CRC8                            0x3fc
+#define BHTSIG1_MCS                             0x7f
+#define BHTSIG1_BANDWIDTH                       0x80
+#define BHTSIG1_HTLENGTH                        0xffff
+#define BLSIG_RATE                              0xf
+#define BLSIG_RESERVED                          0x10
+#define BLSIG_LENGTH                            0x1fffe
+#define BLSIG_PARITY                            0x20
+#define BCCKRXPHASE                             0x4
+
+#define BLSSIREADADDRESS                        0x7f800000
+#define BLSSIREADEDGE                           0x80000000
+
+#define BLSSIREADBACKDATA                       0xfffff
+
+#define BLSSIREADOKFLAG                         0x1000
+#define BCCKSAMPLERATE                          0x8
+#define BREGULATOR0STANDBY                      0x1
+#define BREGULATORPLLSTANDBY                    0x2
+#define BREGULATOR1STANDBY                      0x4
+#define BPLLPOWERUP                             0x8
+#define BDPLLPOWERUP                            0x10
+#define BDA10POWERUP                            0x20
+#define BAD7POWERUP                             0x200
+#define BDA6POWERUP                             0x2000
+#define BXTALPOWERUP                            0x4000
+#define B40MDCLKPOWERUP                         0x8000
+#define BDA6DEBUGMODE                           0x20000
+#define BDA6SWING                               0x380000
+
+#define BADCLKPHASE                             0x4000000
+#define B80MCLKDELAY                            0x18000000
+#define BAFEWATCHDOGENABLE                      0x20000000
+
+#define BXTALCAP01                              0xc0000000
+#define BXTALCAP23                              0x3
+#define BXTALCAP92X                             0x0f000000
+#define BXTALCAP                                0x0f000000
+
+#define BINTDIFCLKENABLE                        0x400
+#define BEXTSIGCLKENABLE                        0x800
+#define BBANDGAP_MBIAS_POWERUP                  0x10000
+#define BAD11SH_GAIN                            0xc0000
+#define BAD11NPUT_RANGE                         0x700000
+#define BAD110P_CURRENT                         0x3800000
+#define BLPATH_LOOPBACK                         0x4000000
+#define BQPATH_LOOPBACK                         0x8000000
+#define BAFE_LOOPBACK                           0x10000000
+#define BDA10_SWING                             0x7e0
+#define BDA10_REVERSE                           0x800
+#define BDA_CLK_SOURCE                          0x1000
+#define BDA7INPUT_RANGE                         0x6000
+#define BDA7_GAIN                               0x38000
+#define BDA7OUTPUT_CM_MODE                      0x40000
+#define BDA7INPUT_CM_MODE                       0x380000
+#define BDA7CURRENT                             0xc00000
+#define BREGULATOR_ADJUST                       0x7000000
+#define BAD11POWERUP_ATTX                       0x1
+#define BDA10PS_ATTX                            0x10
+#define BAD11POWERUP_ATRX                       0x100
+#define BDA10PS_ATRX                            0x1000
+#define BCCKRX_AGC_FORMAT                       0x200
+#define BPSDFFT_SAMPLE_POINT                    0xc000
+#define BPSD_AVERAGE_NUM                        0x3000
+#define BIQPATH_CONTROL                         0xc00
+#define BPSD_FREQ                               0x3ff
+#define BPSD_ANTENNA_PATH                       0x30
+#define BPSD_IQ_SWITCH                          0x40
+#define BPSD_RX_TRIGGER                         0x400000
+#define BPSD_TX_TRIGGER                         0x80000000
+#define BPSD_SINE_TONE_SCALE                    0x7f000000
+#define BPSD_REPORT                             0xffff
+
+#define BOFDM_TXSC                              0x30000000
+#define BCCK_TXON                               0x1
+#define BOFDM_TXON                              0x2
+#define BDEBUG_PAGE                             0xfff
+#define BDEBUG_ITEM                             0xff
+#define BANTL                                   0x10
+#define BANT_NONHT                              0x100
+#define BANT_HT1                                0x1000
+#define BANT_HT2                                0x10000
+#define BANT_HT1S1                              0x100000
+#define BANT_NONHTS1                            0x1000000
+
+#define BCCK_BBMODE                             0x3
+#define BCCK_TXPOWERSAVING                      0x80
+#define BCCK_RXPOWERSAVING                      0x40
+
+#define BCCK_SIDEBAND                           0x10
+
+#define BCCK_SCRAMBLE                           0x8
+#define BCCK_ANTDIVERSITY                       0x8000
+#define BCCK_CARRIER_RECOVERY                   0x4000
+#define BCCK_TXRATE                             0x3000
+#define BCCK_DCCANCEL                           0x0800
+#define BCCK_ISICANCEL                          0x0400
+#define BCCK_MATCH_FILTER                       0x0200
+#define BCCK_EQUALIZER                          0x0100
+#define BCCK_PREAMBLE_DETECT                    0x800000
+#define BCCK_FAST_FALSECCA                      0x400000
+#define BCCK_CH_ESTSTART                        0x300000
+#define BCCK_CCA_COUNT                          0x080000
+#define BCCK_CS_LIM                             0x070000
+#define BCCK_BIST_MODE                          0x80000000
+#define BCCK_CCAMASK                            0x40000000
+#define BCCK_TX_DAC_PHASE                       0x4
+#define BCCK_RX_ADC_PHASE                       0x20000000
+#define BCCKR_CP_MODE                           0x0100
+#define BCCK_TXDC_OFFSET                        0xf0
+#define BCCK_RXDC_OFFSET                        0xf
+#define BCCK_CCA_MODE                           0xc000
+#define BCCK_FALSECS_LIM                        0x3f00
+#define BCCK_CS_RATIO                           0xc00000
+#define BCCK_CORGBIT_SEL                        0x300000
+#define BCCK_PD_LIM                             0x0f0000
+#define BCCK_NEWCCA                             0x80000000
+#define BCCK_RXHP_OF_IG                         0x8000
+#define BCCK_RXIG                               0x7f00
+#define BCCK_LNA_POLARITY                       0x800000
+#define BCCK_RX1ST_BAIN                         0x7f0000
+#define BCCK_RF_EXTEND                          0x20000000
+#define BCCK_RXAGC_SATLEVEL                     0x1f000000
+#define BCCK_RXAGC_SATCOUNT                     0xe0
+#define bCCKRxRFSettle                          0x1f
+#define BCCK_FIXED_RXAGC                        0x8000
+#define BCCK_ANTENNA_POLARITY                   0x2000
+#define BCCK_TXFILTER_TYPE                      0x0c00
+#define BCCK_RXAGC_REPORTTYPE                   0x0300
+#define BCCK_RXDAGC_EN                          0x80000000
+#define BCCK_RXDAGC_PERIOD                      0x20000000
+#define BCCK_RXDAGC_SATLEVEL                    0x1f000000
+#define BCCK_TIMING_RECOVERY                    0x800000
+#define BCCK_TXC0                               0x3f0000
+#define BCCK_TXC1                               0x3f000000
+#define BCCK_TXC2                               0x3f
+#define BCCK_TXC3                               0x3f00
+#define BCCK_TXC4                               0x3f0000
+#define BCCK_TXC5                               0x3f000000
+#define BCCK_TXC6                               0x3f
+#define BCCK_TXC7                               0x3f00
+#define BCCK_DEBUGPORT                          0xff0000
+#define BCCK_DAC_DEBUG                          0x0f000000
+#define BCCK_FALSEALARM_ENABLE                  0x8000
+#define BCCK_FALSEALARM_READ                    0x4000
+#define BCCK_TRSSI                              0x7f
+#define BCCK_RXAGC_REPORT                       0xfe
+#define BCCK_RXREPORT_ANTSEL                    0x80000000
+#define BCCK_RXREPORT_MFOFF                     0x40000000
+#define BCCK_RXREPORT_SQLOSS                    0x20000000
+#define BCCK_RXREPORT_PKTLOSS                   0x10000000
+#define BCCK_RXREPORT_LOCKEDBIT                 0x08000000
+#define BCCK_RXREPORT_RATEERROR                 0x04000000
+#define BCCK_RXREPORT_RXRATE                    0x03000000
+#define BCCK_RXFA_COUNTER_LOWER                 0xff
+#define BCCK_RXFA_COUNTER_UPPER                 0xff000000
+#define BCCK_RXHPAGC_START                      0xe000
+#define BCCK_RXHPAGC_FINAL                      0x1c00
+#define BCCK_RXFALSEALARM_ENABLE                0x8000
+#define BCCK_FACOUNTER_FREEZE                   0x4000
+#define BCCK_TXPATH_SEL                         0x10000000
+#define BCCK_DEFAULT_RXPATH                     0xc000000
+#define BCCK_OPTION_RXPATH                      0x3000000
+
+#define BNUM_OFSTF                              0x3
+#define BSHIFT_L                                0xc0
+#define BGI_TH                                  0xc
+#define BRXPATH_A                               0x1
+#define BRXPATH_B                               0x2
+#define BRXPATH_C                               0x4
+#define BRXPATH_D                               0x8
+#define BTXPATH_A                               0x1
+#define BTXPATH_B                               0x2
+#define BTXPATH_C                               0x4
+#define BTXPATH_D                               0x8
+#define BTRSSI_FREQ                             0x200
+#define BADC_BACKOFF                            0x3000
+#define BDFIR_BACKOFF                           0xc000
+#define BTRSSI_LATCH_PHASE                      0x10000
+#define BRX_LDC_OFFSET                          0xff
+#define BRX_QDC_OFFSET                          0xff00
+#define BRX_DFIR_MODE                           0x1800000
+#define BRX_DCNF_TYPE                           0xe000000
+#define BRXIQIMB_A                              0x3ff
+#define BRXIQIMB_B                              0xfc00
+#define BRXIQIMB_C                              0x3f0000
+#define BRXIQIMB_D                              0xffc00000
+#define BDC_DC_NOTCH                            0x60000
+#define BRXNB_NOTCH                             0x1f000000
+#define BPD_TH                                  0xf
+#define BPD_TH_OPT2                             0xc000
+#define BPWED_TH                                0x700
+#define BIFMF_WIN_L                             0x800
+#define BPD_OPTION                              0x1000
+#define BMF_WIN_L                               0xe000
+#define BBW_SEARCH_L                            0x30000
+#define BWIN_ENH_L                              0xc0000
+#define BBW_TH                                  0x700000
+#define BED_TH2                                 0x3800000
+#define BBW_OPTION                              0x4000000
+#define BRADIO_TH                               0x18000000
+#define BWINDOW_L                               0xe0000000
+#define BSBD_OPTION                             0x1
+#define BFRAME_TH                               0x1c
+#define BFS_OPTION                              0x60
+#define BDC_SLOPE_CHECK                         0x80
+#define BFGUARD_COUNTER_DC_L                    0xe00
+#define BFRAME_WEIGHT_SHORT                     0x7000
+#define BSUB_TUNE                               0xe00000
+#define BFRAME_DC_LENGTH                        0xe000000
+#define BSBD_START_OFFSET                       0x30000000
+#define BFRAME_TH_2                             0x7
+#define BFRAME_GI2_TH                           0x38
+#define BGI2_SYNC_EN                            0x40
+#define BSARCH_SHORT_EARLY                      0x300
+#define BSARCH_SHORT_LATE                       0xc00
+#define BSARCH_GI2_LATE                         0x70000
+#define BCFOANTSUM                              0x1
+#define BCFOACC                                 0x2
+#define BCFOSTARTOFFSET                         0xc
+#define BCFOLOOPBACK                            0x70
+#define BCFOSUMWEIGHT                           0x80
+#define BDAGCENABLE                             0x10000
+#define BTXIQIMB_A                              0x3ff
+#define BTXIQIMB_b                              0xfc00
+#define BTXIQIMB_C                              0x3f0000
+#define BTXIQIMB_D                              0xffc00000
+#define BTXIDCOFFSET                            0xff
+#define BTXIQDCOFFSET                           0xff00
+#define BTXDFIRMODE                             0x10000
+#define BTXPESUDO_NOISEON                       0x4000000
+#define BTXPESUDO_NOISE_A                       0xff
+#define BTXPESUDO_NOISE_B                       0xff00
+#define BTXPESUDO_NOISE_C                       0xff0000
+#define BTXPESUDO_NOISE_D                       0xff000000
+#define BCCA_DROPOPTION                         0x20000
+#define BCCA_DROPTHRES                          0xfff00000
+#define BEDCCA_H                                0xf
+#define BEDCCA_L                                0xf0
+#define BLAMBDA_ED                              0x300
+#define BRX_INITIALGAIN                         0x7f
+#define BRX_ANTDIV_EN                           0x80
+#define BRX_AGC_ADDRESS_FOR_LNA                 0x7f00
+#define BRX_HIGHPOWER_FLOW                      0x8000
+#define BRX_AGC_FREEZE_THRES                    0xc0000
+#define BRX_FREEZESTEP_AGC1                     0x300000
+#define BRX_FREEZESTEP_AGC2                     0xc00000
+#define BRX_FREEZESTEP_AGC3                     0x3000000
+#define BRX_FREEZESTEP_AGC0                     0xc000000
+#define BRXRSSI_CMP_EN                          0x10000000
+#define BRXQUICK_AGCEN                          0x20000000
+#define BRXAGC_FREEZE_THRES_MODE                0x40000000
+#define BRX_OVERFLOW_CHECKTYPE                  0x80000000
+#define BRX_AGCSHIFT                            0x7f
+#define BTRSW_TRI_ONLY                          0x80
+#define BPOWER_THRES                            0x300
+#define BRXAGC_EN                               0x1
+#define BRXAGC_TOGETHER_EN                      0x2
+#define BRXAGC_MIN                              0x4
+#define BRXHP_INI                               0x7
+#define BRXHP_TRLNA                             0x70
+#define BRXHP_RSSI                              0x700
+#define BRXHP_BBP1                              0x7000
+#define BRXHP_BBP2                              0x70000
+#define BRXHP_BBP3                              0x700000
+#define BRSSI_H                                 0x7f0000
+#define BRSSI_GEN                               0x7f000000
+#define BRXSETTLE_TRSW                          0x7
+#define BRXSETTLE_LNA                           0x38
+#define BRXSETTLE_RSSI                          0x1c0
+#define BRXSETTLE_BBP                           0xe00
+#define BRXSETTLE_RXHP                          0x7000
+#define BRXSETTLE_ANTSW_RSSI                    0x38000
+#define BRXSETTLE_ANTSW                         0xc0000
+#define BRXPROCESS_TIME_DAGC                    0x300000
+#define BRXSETTLE_HSSI                          0x400000
+#define BRXPROCESS_TIME_BBPPW                   0x800000
+#define BRXANTENNA_POWER_SHIFT                  0x3000000
+#define BRSSI_TABLE_SELECT                      0xc000000
+#define BRXHP_FINAL                             0x7000000
+#define BRXHPSETTLE_BBP                         0x7
+#define BRXHTSETTLE_HSSI                        0x8
+#define BRXHTSETTLE_RXHP                        0x70
+#define BRXHTSETTLE_BBPPW                       0x80
+#define BRXHTSETTLE_IDLE                        0x300
+#define BRXHTSETTLE_RESERVED                    0x1c00
+#define BRXHT_RXHP_EN                           0x8000
+#define BRXAGC_FREEZE_THRES                     0x30000
+#define BRXAGC_TOGETHEREN                       0x40000
+#define BRXHTAGC_MIN                            0x80000
+#define BRXHTAGC_EN                             0x100000
+#define BRXHTDAGC_EN                            0x200000
+#define BRXHT_RXHP_BBP                          0x1c00000
+#define BRXHT_RXHP_FINAL                        0xe0000000
+#define BRXPW_RADIO_TH                          0x3
+#define BRXPW_RADIO_EN                          0x4
+#define BRXMF_HOLD                              0x3800
+#define BRXPD_DELAY_TH1                         0x38
+#define BRXPD_DELAY_TH2                         0x1c0
+#define BRXPD_DC_COUNT_MAX                      0x600
+#define BRXPD_DELAY_TH                          0x8000
+#define BRXPROCESS_DELAY                        0xf0000
+#define BRXSEARCHRANGE_GI2_EARLY                0x700000
+#define BRXFRAME_FUARD_COUNTER_L                0x3800000
+#define BRXSGI_GUARD_L                          0xc000000
+#define BRXSGI_SEARCH_L                         0x30000000
+#define BRXSGI_TH                               0xc0000000
+#define BDFSCNT0                                0xff
+#define BDFSCNT1                                0xff00
+#define BDFSFLAG                                0xf0000
+#define BMF_WEIGHT_SUM                          0x300000
+#define BMINIDX_TH                              0x7f000000
+#define BDAFORMAT                               0x40000
+#define BTXCH_EMU_ENABLE                        0x01000000
+#define BTRSW_ISOLATION_A                       0x7f
+#define BTRSW_ISOLATION_B                       0x7f00
+#define BTRSW_ISOLATION_C                       0x7f0000
+#define BTRSW_ISOLATION_D                       0x7f000000
+#define BEXT_LNA_GAIN                           0x7c00
+
+#define BSTBC_EN                                0x4
+#define BANTENNA_MAPPING                        0x10
+#define BNSS                                    0x20
+#define BCFO_ANTSUM_ID                          0x200
+#define BPHY_COUNTER_RESET                      0x8000000
+#define BCFO_REPORT_GET                         0x4000000
+#define BOFDM_CONTINUE_TX                       0x10000000
+#define BOFDM_SINGLE_CARRIER                    0x20000000
+#define BOFDM_SINGLE_TONE                       0x40000000
+#define BHT_DETECT                              0x100
+#define BCFOEN                                  0x10000
+#define BCFOVALUE                               0xfff00000
+#define BSIGTONE_RE                             0x3f
+#define BSIGTONE_IM                             0x7f00
+#define BCOUNTER_CCA                            0xffff
+#define BCOUNTER_PARITYFAIL                     0xffff0000
+#define BCOUNTER_RATEILLEGAL                    0xffff
+#define BCOUNTER_CRC8FAIL                       0xffff0000
+#define BCOUNTER_MCSNOSUPPORT                   0xffff
+#define BCOUNTER_FASTSYNC                       0xffff
+#define BSHORTCFO                               0xfff
+#define BSHORTCFOT_LENGTH                       12
+#define BSHORTCFOF_LENGTH                       11
+#define BLONGCFO                                0x7ff
+#define BLONGCFOT_LENGTH                        11
+#define BLONGCFOF_LENGTH                        11
+#define BTAILCFO                                0x1fff
+#define BTAILCFOT_LENGTH                        13
+#define BTAILCFOF_LENGTH                        12
+#define BNOISE_EN_PWDB                          0xffff
+#define BCC_POWER_DB                            0xffff0000
+#define BMOISE_PWDB                             0xffff
+#define BPOWERMEAST_LENGTH                      10
+#define BPOWERMEASF_LENGTH                      3
+#define BRX_HT_BW                               0x1
+#define BRXSC                                   0x6
+#define BRX_HT                                  0x8
+#define BNB_INTF_DET_ON                         0x1
+#define BINTF_WIN_LEN_CFG                       0x30
+#define BNB_INTF_TH_CFG                         0x1c0
+#define BRFGAIN                                 0x3f
+#define BTABLESEL                               0x40
+#define BTRSW                                   0x80
+#define BRXSNR_A                                0xff
+#define BRXSNR_B                                0xff00
+#define BRXSNR_C                                0xff0000
+#define BRXSNR_D                                0xff000000
+#define BSNR_EVMT_LENGTH                        8
+#define BSNR_EVMF_LENGTH                        1
+#define BCSI1ST                                 0xff
+#define BCSI2ND                                 0xff00
+#define BRXEVM1ST                               0xff0000
+#define BRXEVM2ND                               0xff000000
+#define BSIGEVM                                 0xff
+#define BPWDB                                   0xff00
+#define BSGIEN                                  0x10000
+
+#define BSFACTOR_QMA1                           0xf
+#define BSFACTOR_QMA2                           0xf0
+#define BSFACTOR_QMA3                           0xf00
+#define BSFACTOR_QMA4                           0xf000
+#define BSFACTOR_QMA5                           0xf0000
+#define BSFACTOR_QMA6                           0xf0000
+#define BSFACTOR_QMA7                           0xf00000
+#define BSFACTOR_QMA8                           0xf000000
+#define BSFACTOR_QMA9                           0xf0000000
+#define BCSI_SCHEME                             0x100000
+
+#define BNOISE_LVL_TOP_SET                      0x3
+#define BCHSMOOTH                               0x4
+#define BCHSMOOTH_CFG1                          0x38
+#define BCHSMOOTH_CFG2                          0x1c0
+#define BCHSMOOTH_CFG3                          0xe00
+#define BCHSMOOTH_CFG4                          0x7000
+#define BMRCMODE                                0x800000
+#define BTHEVMCFG                               0x7000000
+
+#define BLOOP_FIT_TYPE                          0x1
+#define BUPD_CFO                                0x40
+#define BUPD_CFO_OFFDATA                        0x80
+#define BADV_UPD_CFO                            0x100
+#define BADV_TIME_CTRL                          0x800
+#define BUPD_CLKO                               0x1000
+#define BFC                                     0x6000
+#define BTRACKING_MODE                          0x8000
+#define BPHCMP_ENABLE                           0x10000
+#define BUPD_CLKO_LTF                           0x20000
+#define BCOM_CH_CFO                             0x40000
+#define BCSI_ESTI_MODE                          0x80000
+#define BADV_UPD_EQZ                            0x100000
+#define BUCHCFG                                 0x7000000
+#define BUPDEQZ                                 0x8000000
+
+#define BRX_PESUDO_NOISE_ON                     0x20000000
+#define BRX_PESUDO_NOISE_A                      0xff
+#define BRX_PESUDO_NOISE_B                      0xff00
+#define BRX_PESUDO_NOISE_C                      0xff0000
+#define BRX_PESUDO_NOISE_D                      0xff000000
+#define BRX_PESUDO_NOISESTATE_A                 0xffff
+#define BRX_PESUDO_NOISESTATE_B                 0xffff0000
+#define BRX_PESUDO_NOISESTATE_C                 0xffff
+#define BRX_PESUDO_NOISESTATE_D                 0xffff0000
+
+#define BZEBRA1_HSSIENABLE                      0x8
+#define BZEBRA1_TRXCONTROL                      0xc00
+#define BZEBRA1_TRXGAINSETTING                  0x07f
+#define BZEBRA1_RXCOUNTER                       0xc00
+#define BZEBRA1_TXCHANGEPUMP                    0x38
+#define BZEBRA1_RXCHANGEPUMP                    0x7
+#define BZEBRA1_CHANNEL_NUM                     0xf80
+#define BZEBRA1_TXLPFBW                         0x400
+#define BZEBRA1_RXLPFBW                         0x600
+
+#define BRTL8256REG_MODE_CTRL1                  0x100
+#define BRTL8256REG_MODE_CTRL0                  0x40
+#define BRTL8256REG_TXLPFBW                     0x18
+#define BRTL8256REG_RXLPFBW                     0x600
+
+#define BRTL8258_TXLPFBW                        0xc
+#define BRTL8258_RXLPFBW                        0xc00
+#define BRTL8258_RSSILPFBW                      0xc0
+
+#define BBYTE0                                  0x1
+#define BBYTE1                                  0x2
+#define BBYTE2                                  0x4
+#define BBYTE3                                  0x8
+#define BWORD0                                  0x3
+#define BWORD1                                  0xc
+#define BWORD                                   0xf
+
+#define MASKBYTE0                               0xff
+#define MASKBYTE1                               0xff00
+#define MASKBYTE2                               0xff0000
+#define MASKBYTE3                               0xff000000
+#define MASKHWORD                               0xffff0000
+#define MASKLWORD                               0x0000ffff
+#define MASKDWORD                               0xffffffff
+#define MASK12BITS                              0xfff
+#define MASKH4BITS                              0xf0000000
+#define MASKOFDM_D                              0xffc00000
+#define MASKCCK                                 0x3f3f3f3f
+
+#define MASK4BITS                               0x0f
+#define MASK20BITS                              0xfffff
+#define RFREG_OFFSET_MASK                       0xfffff
+
+#define BENABLE                                 0x1
+#define BDISABLE                                0x0
+
+#define LEFT_ANTENNA                            0x0
+#define RIGHT_ANTENNA                           0x1
+
+#define TCHECK_TXSTATUS                         500
+#define TUPDATE_RXCOUNTER                       100
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
new file mode 100644
index 000000000000..ffd8e04c4028
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
@@ -0,0 +1,523 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../wifi.h"
+#include "reg.h"
+#include "def.h"
+#include "phy.h"
+#include "rf.h"
+#include "dm.h"
+
+static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
+
+void rtl92c_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        switch (bandwidth) {
+        case HT_CHANNEL_WIDTH_20:
+                rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
+                                             0xfffff3ff) | 0x0400);
+                rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
+                              rtlphy->rfreg_chnlval[0]);
+                break;
+        case HT_CHANNEL_WIDTH_20_40:
+                rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
+                                             0xfffff3ff));
+                rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
+                              rtlphy->rfreg_chnlval[0]);
+                break;
+        default:
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("unknown bandwidth: %#X\n", bandwidth));
+                break;
+        }
+}
+
+void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
+                                       u8 *ppowerlevel)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u32 tx_agc[2] = {0, 0}, tmpval;
+        bool turbo_scanoff = false;
+        u8 idx1, idx2;
+        u8 *ptr;
+
+        if (rtlefuse->eeprom_regulatory != 0)
+                turbo_scanoff = true;
+
+        if (mac->act_scanning == true) {
+                tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
+                tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
+
+                if (turbo_scanoff) {
+                        for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
+                                tx_agc[idx1] = ppowerlevel[idx1] |
+                                    (ppowerlevel[idx1] << 8) |
+                                    (ppowerlevel[idx1] << 16) |
+                                    (ppowerlevel[idx1] << 24);
+                        }
+                }
+        } else {
+                for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
+                        tx_agc[idx1] = ppowerlevel[idx1] |
+                            (ppowerlevel[idx1] << 8) |
+                            (ppowerlevel[idx1] << 16) |
+                            (ppowerlevel[idx1] << 24);
+                }
+
+                if (rtlefuse->eeprom_regulatory == 0) {
+                        tmpval =
+                            (rtlphy->mcs_txpwrlevel_origoffset[0][6]) +
+                            (rtlphy->mcs_txpwrlevel_origoffset[0][7] <<
+                             8);
+                        tx_agc[RF90_PATH_A] += tmpval;
+
+                        tmpval = (rtlphy->mcs_txpwrlevel_origoffset[0][14]) +
+                                 (rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
+                                 24);
+                        tx_agc[RF90_PATH_B] += tmpval;
+                }
+        }
+
+        for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
+                ptr = (u8 *) (&(tx_agc[idx1]));
+                for (idx2 = 0; idx2 < 4; idx2++) {
+                        if (*ptr > RF6052_MAX_TX_PWR)
+                                *ptr = RF6052_MAX_TX_PWR;
+                        ptr++;
+                }
+        }
+
+        tmpval = tx_agc[RF90_PATH_A] & 0xff;
+        rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
+
+        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
+                 RTXAGC_A_CCK1_MCS32));
+
+        tmpval = tx_agc[RF90_PATH_A] >> 8;
+
+        if (mac->mode == WIRELESS_MODE_B)
+                tmpval = tmpval & 0xff00ffff;
+
+        rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
+
+        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
+                 RTXAGC_B_CCK11_A_CCK2_11));
+
+        tmpval = tx_agc[RF90_PATH_B] >> 24;
+        rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
+
+        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
+                 RTXAGC_B_CCK11_A_CCK2_11));
+
+        tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
+        rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
+
+        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
+                 RTXAGC_B_CCK1_55_MCS32));
+}
+
+static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
+                                      u8 *ppowerlevel, u8 channel,
+                                      u32 *ofdmbase, u32 *mcsbase)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u32 powerBase0, powerBase1;
+        u8 legacy_pwrdiff, ht20_pwrdiff;
+        u8 i, powerlevel[2];
+
+        for (i = 0; i < 2; i++) {
+                powerlevel[i] = ppowerlevel[i];
+                legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
+                powerBase0 = powerlevel[i] + legacy_pwrdiff;
+
+                powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
+                    (powerBase0 << 8) | powerBase0;
+                *(ofdmbase + i) = powerBase0;
+                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                        (" [OFDM power base index rf(%c) = 0x%x]\n",
+                         ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
+        }
+
+        for (i = 0; i < 2; i++) {
+                if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
+                        ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
+                        powerlevel[i] += ht20_pwrdiff;
+                }
+                powerBase1 = powerlevel[i];
+                powerBase1 = (powerBase1 << 24) |
+                    (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
+
+                *(mcsbase + i) = powerBase1;
+
+                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                        (" [MCS power base index rf(%c) = 0x%x]\n",
+                         ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
+        }
+}
+
+static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
+                                                       u8 channel, u8 index,
+                                                       u32 *powerBase0,
+                                                       u32 *powerBase1,
+                                                       u32 *p_outwriteval)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+        u8 i, chnlgroup, pwr_diff_limit[4];
+        u32 writeVal, customer_limit, rf;
+
+        for (rf = 0; rf < 2; rf++) {
+                switch (rtlefuse->eeprom_regulatory) {
+                case 0:
+                        chnlgroup = 0;
+
+                        writeVal =
+                            rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
+                            (rf ? 8 : 0)]
+                            + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
+
+                        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                ("RTK better performance, "
+                                 "writeVal(%c) = 0x%x\n",
+                                 ((rf == 0) ? 'A' : 'B'), writeVal));
+                        break;
+                case 1:
+                        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
+                                writeVal = ((index < 2) ? powerBase0[rf] :
+                                            powerBase1[rf]);
+
+                                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                        ("Realtek regulatory, 40MHz, "
+                                         "writeVal(%c) = 0x%x\n",
+                                         ((rf == 0) ? 'A' : 'B'), writeVal));
+                        } else {
+                                if (rtlphy->pwrgroup_cnt == 1)
+                                        chnlgroup = 0;
+                                if (rtlphy->pwrgroup_cnt >= 3) {
+                                        if (channel <= 3)
+                                                chnlgroup = 0;
+                                        else if (channel >= 4 && channel <= 9)
+                                                chnlgroup = 1;
+                                        else if (channel > 9)
+                                                chnlgroup = 2;
+                                        if (rtlphy->pwrgroup_cnt == 4)
+                                                chnlgroup++;
+                                }
+
+                                writeVal =
+                                    rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
+                                    [index + (rf ? 8 : 0)] + ((index < 2) ?
+                                                              powerBase0[rf] :
+                                                              powerBase1[rf]);
+
+                                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                        ("Realtek regulatory, 20MHz, "
+                                         "writeVal(%c) = 0x%x\n",
+                                         ((rf == 0) ? 'A' : 'B'), writeVal));
+                        }
+                        break;
+                case 2:
+                        writeVal =
+                            ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
+
+                        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                ("Better regulatory, "
+                                 "writeVal(%c) = 0x%x\n",
+                                 ((rf == 0) ? 'A' : 'B'), writeVal));
+                        break;
+                case 3:
+                        chnlgroup = 0;
+
+                        if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
+                                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                        ("customer's limit, 40MHz "
+                                         "rf(%c) = 0x%x\n",
+                                         ((rf == 0) ? 'A' : 'B'),
+                                         rtlefuse->pwrgroup_ht40[rf][channel -
+                                                                     1]));
+                        } else {
+                                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                        ("customer's limit, 20MHz "
+                                         "rf(%c) = 0x%x\n",
+                                         ((rf == 0) ? 'A' : 'B'),
+                                         rtlefuse->pwrgroup_ht20[rf][channel -
+                                                                     1]));
+                        }
+                        for (i = 0; i < 4; i++) {
+                                pwr_diff_limit[i] =
+                                    (u8) ((rtlphy->mcs_txpwrlevel_origoffset
+                                          [chnlgroup][index +
+                                          (rf ? 8 : 0)] & (0x7f << (i * 8))) >>
+                                          (i * 8));
+
+                                if (rtlphy->current_chan_bw ==
+                                    HT_CHANNEL_WIDTH_20_40) {
+                                        if (pwr_diff_limit[i] >
+                                            rtlefuse->
+                                            pwrgroup_ht40[rf][channel - 1])
+                                                pwr_diff_limit[i] =
+                                                    rtlefuse->pwrgroup_ht40[rf]
+                                                    [channel - 1];
+                                } else {
+                                        if (pwr_diff_limit[i] >
+                                            rtlefuse->
+                                            pwrgroup_ht20[rf][channel - 1])
+                                                pwr_diff_limit[i] =
+                                                    rtlefuse->pwrgroup_ht20[rf]
+                                                    [channel - 1];
+                                }
+                        }
+
+                        customer_limit = (pwr_diff_limit[3] << 24) |
+                            (pwr_diff_limit[2] << 16) |
+                            (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
+
+                        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                ("Customer's limit rf(%c) = 0x%x\n",
+                                 ((rf == 0) ? 'A' : 'B'), customer_limit));
+
+                        writeVal = customer_limit +
+                            ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
+
+                        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                ("Customer, writeVal rf(%c)= 0x%x\n",
+                                 ((rf == 0) ? 'A' : 'B'), writeVal));
+                        break;
+                default:
+                        chnlgroup = 0;
+                        writeVal =
+                            rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
+                            [index + (rf ? 8 : 0)]
+                            + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
+
+                        RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                                ("RTK better performance, writeVal "
+                                 "rf(%c) = 0x%x\n",
+                                 ((rf == 0) ? 'A' : 'B'), writeVal));
+                        break;
+                }
+
+                if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
+                        writeVal = writeVal - 0x06060606;
+                else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
+                         TXHIGHPWRLEVEL_BT2)
+                        writeVal = writeVal - 0x0c0c0c0c;
+                *(p_outwriteval + rf) = writeVal;
+        }
+}
+
+static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
+                                         u8 index, u32 *pValue)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        u16 regoffset_a[6] = {
+                RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
+                RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
+                RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
+        };
+        u16 regoffset_b[6] = {
+                RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
+                RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
+                RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
+        };
+        u8 i, rf, pwr_val[4];
+        u32 writeVal;
+        u16 regoffset;
+
+        for (rf = 0; rf < 2; rf++) {
+                writeVal = pValue[rf];
+                for (i = 0; i < 4; i++) {
+                        pwr_val[i] = (u8) ((writeVal & (0x7f <<
+                                                        (i * 8))) >> (i * 8));
+
+                        if (pwr_val[i] > RF6052_MAX_TX_PWR)
+                                pwr_val[i] = RF6052_MAX_TX_PWR;
+                }
+                writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
+                    (pwr_val[1] << 8) | pwr_val[0];
+
+                if (rf == 0)
+                        regoffset = regoffset_a[index];
+                else
+                        regoffset = regoffset_b[index];
+                rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
+
+                RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
+                        ("Set 0x%x = %08x\n", regoffset, writeVal));
+
+                if (((get_rf_type(rtlphy) == RF_2T2R) &&
+                     (regoffset == RTXAGC_A_MCS15_MCS12 ||
+                      regoffset == RTXAGC_B_MCS15_MCS12)) ||
+                    ((get_rf_type(rtlphy) != RF_2T2R) &&
+                     (regoffset == RTXAGC_A_MCS07_MCS04 ||
+                      regoffset == RTXAGC_B_MCS07_MCS04))) {
+
+                        writeVal = pwr_val[3];
+                        if (regoffset == RTXAGC_A_MCS15_MCS12 ||
+                            regoffset == RTXAGC_A_MCS07_MCS04)
+                                regoffset = 0xc90;
+                        if (regoffset == RTXAGC_B_MCS15_MCS12 ||
+                            regoffset == RTXAGC_B_MCS07_MCS04)
+                                regoffset = 0xc98;
+
+                        for (i = 0; i < 3; i++) {
+                                writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
+                                rtl_write_byte(rtlpriv, (u32) (regoffset + i),
+                                               (u8) writeVal);
+                        }
+                }
+        }
+}
+
+void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
+                                        u8 *ppowerlevel, u8 channel)
+{
+        u32 writeVal[2], powerBase0[2], powerBase1[2];
+        u8 index;
+
+        rtl92c_phy_get_power_base(hw, ppowerlevel,
+                                  channel, &powerBase0[0], &powerBase1[0]);
+
+        for (index = 0; index < 6; index++) {
+                _rtl92c_get_txpower_writeval_by_regulatory(hw,
+                                                           channel, index,
+                                                           &powerBase0[0],
+                                                           &powerBase1[0],
+                                                           &writeVal[0]);
+
+                _rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
+        }
+}
+
+bool rtl92c_phy_rf6052_config(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+
+        if (rtlphy->rf_type == RF_1T1R)
+                rtlphy->num_total_rfpath = 1;
+        else
+                rtlphy->num_total_rfpath = 2;
+
+        return _rtl92c_phy_rf6052_config_parafile(hw);
+}
+
+static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        u32 u4_regvalue;
+        u8 rfpath;
+        bool rtstatus;
+        struct bb_reg_def *pphyreg;
+
+        for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
+
+                pphyreg = &rtlphy->phyreg_def[rfpath];
+
+                switch (rfpath) {
+                case RF90_PATH_A:
+                case RF90_PATH_C:
+                        u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
+                                                    BRFSI_RFENV);
+                        break;
+                case RF90_PATH_B:
+                case RF90_PATH_D:
+                        u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
+                                                    BRFSI_RFENV << 16);
+                        break;
+                }
+
+                rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
+                udelay(1);
+
+                rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
+                udelay(1);
+
+                rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
+                              B3WIREADDREAALENGTH, 0x0);
+                udelay(1);
+
+                rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
+                udelay(1);
+
+                switch (rfpath) {
+                case RF90_PATH_A:
+                        rtstatus = rtl92c_phy_config_rf_with_headerfile(hw,
+                                        (enum radio_path) rfpath);
+                        break;
+                case RF90_PATH_B:
+                        rtstatus = rtl92c_phy_config_rf_with_headerfile(hw,
+                                        (enum radio_path) rfpath);
+                        break;
+                case RF90_PATH_C:
+                        break;
+                case RF90_PATH_D:
+                        break;
+                }
+
+                switch (rfpath) {
+                case RF90_PATH_A:
+                case RF90_PATH_C:
+                        rtl_set_bbreg(hw, pphyreg->rfintfs,
+                                      BRFSI_RFENV, u4_regvalue);
+                        break;
+                case RF90_PATH_B:
+                case RF90_PATH_D:
+                        rtl_set_bbreg(hw, pphyreg->rfintfs,
+                                      BRFSI_RFENV << 16, u4_regvalue);
+                        break;
+                }
+
+                if (rtstatus != true) {
+                        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
+                                 ("Radio[%d] Fail!!", rfpath));
+                        return false;
+                }
+
+        }
+
+        RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
+        return rtstatus;
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
new file mode 100644
index 000000000000..d3014f99bb7b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92C_RF_H__
+#define __RTL92C_RF_H__
+
+#define RF6052_MAX_TX_PWR               0x3F
+#define RF6052_MAX_REG                  0x3F
+#define RF6052_MAX_PATH                 2
+
+extern void rtl92c_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
+                                            u8 bandwidth);
+extern void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
+                                              u8 *ppowerlevel);
+extern void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
+                                               u8 *ppowerlevel, u8 channel);
+extern bool rtl92c_phy_rf6052_config(struct ieee80211_hw *hw);
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
new file mode 100644
index 000000000000..b366e8862929
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
@@ -0,0 +1,282 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include <linux/vmalloc.h>
+
+#include "../wifi.h"
+#include "../core.h"
+#include "../pci.h"
+#include "reg.h"
+#include "def.h"
+#include "phy.h"
+#include "dm.h"
+#include "hw.h"
+#include "sw.h"
+#include "trx.h"
+#include "led.h"
+
+int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+
+        rtlpriv->dm.b_dm_initialgain_enable = 1;
+        rtlpriv->dm.dm_flag = 0;
+        rtlpriv->dm.b_disable_framebursting = 0;;
+        rtlpriv->dm.thermalvalue = 0;
+        rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
+
+        rtlpci->receive_config = (RCR_APPFCS |
+                                  RCR_AMF |
+                                  RCR_ADF |
+                                  RCR_APP_MIC |
+                                  RCR_APP_ICV |
+                                  RCR_AICV |
+                                  RCR_ACRC32 |
+                                  RCR_AB |
+                                  RCR_AM |
+                                  RCR_APM |
+                                  RCR_APP_PHYST_RXFF | RCR_HTC_LOC_CTRL | 0);
+
+        rtlpci->irq_mask[0] =
+            (u32) (IMR_ROK |
+                   IMR_VODOK |
+                   IMR_VIDOK |
+                   IMR_BEDOK |
+                   IMR_BKDOK |
+                   IMR_MGNTDOK |
+                   IMR_HIGHDOK | IMR_BDOK | IMR_RDU | IMR_RXFOVW | 0);
+
+        rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD | 0);
+
+        rtlpriv->rtlhal.pfirmware = (u8 *) vmalloc(0x4000);
+        if (!rtlpriv->rtlhal.pfirmware) {
+                RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
+                         ("Can't alloc buffer for fw.\n"));
+                return 1;
+        }
+
+        return 0;
+}
+
+void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->rtlhal.pfirmware) {
+                vfree(rtlpriv->rtlhal.pfirmware);
+                rtlpriv->rtlhal.pfirmware = NULL;
+        }
+}
+
+static struct rtl_hal_ops rtl8192ce_hal_ops = {
+        .init_sw_vars = rtl92c_init_sw_vars,
+        .deinit_sw_vars = rtl92c_deinit_sw_vars,
+        .read_eeprom_info = rtl92ce_read_eeprom_info,
+        .interrupt_recognized = rtl92ce_interrupt_recognized,
+        .hw_init = rtl92ce_hw_init,
+        .hw_disable = rtl92ce_card_disable,
+        .enable_interrupt = rtl92ce_enable_interrupt,
+        .disable_interrupt = rtl92ce_disable_interrupt,
+        .set_network_type = rtl92ce_set_network_type,
+        .set_qos = rtl92ce_set_qos,
+        .set_bcn_reg = rtl92ce_set_beacon_related_registers,
+        .set_bcn_intv = rtl92ce_set_beacon_interval,
+        .update_interrupt_mask = rtl92ce_update_interrupt_mask,
+        .get_hw_reg = rtl92ce_get_hw_reg,
+        .set_hw_reg = rtl92ce_set_hw_reg,
+        .update_rate_table = rtl92ce_update_hal_rate_table,
+        .update_rate_mask = rtl92ce_update_hal_rate_mask,
+        .fill_tx_desc = rtl92ce_tx_fill_desc,
+        .fill_tx_cmddesc = rtl92ce_tx_fill_cmddesc,
+        .query_rx_desc = rtl92ce_rx_query_desc,
+        .set_channel_access = rtl92ce_update_channel_access_setting,
+        .radio_onoff_checking = rtl92ce_gpio_radio_on_off_checking,
+        .set_bw_mode = rtl92c_phy_set_bw_mode,
+        .switch_channel = rtl92c_phy_sw_chnl,
+        .dm_watchdog = rtl92c_dm_watchdog,
+        .scan_operation_backup = rtl92c_phy_scan_operation_backup,
+        .set_rf_power_state = rtl92c_phy_set_rf_power_state,
+        .led_control = rtl92ce_led_control,
+        .set_desc = rtl92ce_set_desc,
+        .get_desc = rtl92ce_get_desc,
+        .tx_polling = rtl92ce_tx_polling,
+        .enable_hw_sec = rtl92ce_enable_hw_security_config,
+        .set_key = rtl92ce_set_key,
+        .init_sw_leds = rtl92ce_init_sw_leds,
+        .deinit_sw_leds = rtl92ce_deinit_sw_leds,
+        .get_bbreg = rtl92c_phy_query_bb_reg,
+        .set_bbreg = rtl92c_phy_set_bb_reg,
+        .get_rfreg = rtl92c_phy_query_rf_reg,
+        .set_rfreg = rtl92c_phy_set_rf_reg,
+};
+
+static struct rtl_mod_params rtl92ce_mod_params = {
+        .sw_crypto = 0,
+};
+
+static struct rtl_hal_cfg rtl92ce_hal_cfg = {
+        .name = "rtl92c_pci",
+        .fw_name = "rtlwifi/rtl8192cfw.bin",
+        .ops = &rtl8192ce_hal_ops,
+        .mod_params = &rtl92ce_mod_params,
+
+        .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
+        .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
+        .maps[SYS_CLK] = REG_SYS_CLKR,
+        .maps[MAC_RCR_AM] = AM,
+        .maps[MAC_RCR_AB] = AB,
+        .maps[MAC_RCR_ACRC32] = ACRC32,
+        .maps[MAC_RCR_ACF] = ACF,
+        .maps[MAC_RCR_AAP] = AAP,
+
+        .maps[EFUSE_TEST] = REG_EFUSE_TEST,
+        .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
+        .maps[EFUSE_CLK] = 0,
+        .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
+        .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
+        .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
+        .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
+        .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
+        .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
+
+        .maps[RWCAM] = REG_CAMCMD,
+        .maps[WCAMI] = REG_CAMWRITE,
+        .maps[RCAMO] = REG_CAMREAD,
+        .maps[CAMDBG] = REG_CAMDBG,
+        .maps[SECR] = REG_SECCFG,
+        .maps[SEC_CAM_NONE] = CAM_NONE,
+        .maps[SEC_CAM_WEP40] = CAM_WEP40,
+        .maps[SEC_CAM_TKIP] = CAM_TKIP,
+        .maps[SEC_CAM_AES] = CAM_AES,
+        .maps[SEC_CAM_WEP104] = CAM_WEP104,
+
+        .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
+        .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
+        .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
+        .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
+        .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
+        .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
+        .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
+        .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
+        .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
+        .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
+        .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
+        .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
+        .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
+        .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
+        .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
+        .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
+
+        .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
+        .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
+        .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
+        .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
+        .maps[RTL_IMR_RDU] = IMR_RDU,
+        .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
+        .maps[RTL_IMR_BDOK] = IMR_BDOK,
+        .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
+        .maps[RTL_IMR_TBDER] = IMR_TBDER,
+        .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
+        .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
+        .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
+        .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
+        .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
+        .maps[RTL_IMR_VODOK] = IMR_VODOK,
+        .maps[RTL_IMR_ROK] = IMR_ROK,
+        .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
+
+        .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
+        .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
+        .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
+        .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
+        .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
+        .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
+        .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
+        .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
+        .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
+        .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
+        .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
+        .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
+
+        .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
+        .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
+};
+
+static struct pci_device_id rtl92ce_pci_ids[] __devinitdata = {
+        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8191, rtl92ce_hal_cfg)},
+        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8178, rtl92ce_hal_cfg)},
+        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8177, rtl92ce_hal_cfg)},
+        {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8176, rtl92ce_hal_cfg)},
+        {},
+};
+
+MODULE_DEVICE_TABLE(pci, rtl92ce_pci_ids);
+
+MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
+MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
+MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
+MODULE_FIRMWARE("rtlwifi/rtl8192cfw.bin");
+
+module_param_named(swenc, rtl92ce_mod_params.sw_crypto, bool, 0444);
+MODULE_PARM_DESC(swenc, "using hardware crypto (default 0 [hardware])\n");
+
+static struct pci_driver rtl92ce_driver = {
+        .name = KBUILD_MODNAME,
+        .id_table = rtl92ce_pci_ids,
+        .probe = rtl_pci_probe,
+        .remove = rtl_pci_disconnect,
+
+#ifdef CONFIG_PM
+        .suspend = rtl_pci_suspend,
+        .resume = rtl_pci_resume,
+#endif
+
+};
+
+static int __init rtl92ce_module_init(void)
+{
+        int ret;
+
+        ret = pci_register_driver(&rtl92ce_driver);
+        if (ret)
+                RT_ASSERT(false, (": No device found\n"));
+
+        return ret;
+}
+
+static void __exit rtl92ce_module_exit(void)
+{
+        pci_unregister_driver(&rtl92ce_driver);
+}
+
+module_init(rtl92ce_module_init);
+module_exit(rtl92ce_module_exit);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
new file mode 100644
index 000000000000..de1198c38d4e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
@@ -0,0 +1,37 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92CE_SW_H__
+#define __RTL92CE_SW_H__
+
+int rtl92c_init_sw_vars(struct ieee80211_hw *hw);
+void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw);
+void rtl92c_init_var_map(struct ieee80211_hw *hw);
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/table.c b/drivers/net/wireless/rtlwifi/rtl8192ce/table.c
new file mode 100644
index 000000000000..ba938b91aa6f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/table.c
@@ -0,0 +1,1224 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Created on  2010/ 5/18,  1:41
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "table.h"
+
+
+u32 RTL8192CEPHY_REG_2TARRAY[PHY_REG_2TARRAY_LENGTH] = {
+        0x024, 0x0011800f,
+        0x028, 0x00ffdb83,
+        0x800, 0x80040002,
+        0x804, 0x00000003,
+        0x808, 0x0000fc00,
+        0x80c, 0x0000000a,
+        0x810, 0x10005388,
+        0x814, 0x020c3d10,
+        0x818, 0x02200385,
+        0x81c, 0x00000000,
+        0x820, 0x01000100,
+        0x824, 0x00390004,
+        0x828, 0x01000100,
+        0x82c, 0x00390004,
+        0x830, 0x27272727,
+        0x834, 0x27272727,
+        0x838, 0x27272727,
+        0x83c, 0x27272727,
+        0x840, 0x00010000,
+        0x844, 0x00010000,
+        0x848, 0x27272727,
+        0x84c, 0x27272727,
+        0x850, 0x00000000,
+        0x854, 0x00000000,
+        0x858, 0x569a569a,
+        0x85c, 0x0c1b25a4,
+        0x860, 0x66e60230,
+        0x864, 0x061f0130,
+        0x868, 0x27272727,
+        0x86c, 0x2b2b2b27,
+        0x870, 0x07000700,
+        0x874, 0x22184000,
+        0x878, 0x08080808,
+        0x87c, 0x00000000,
+        0x880, 0xc0083070,
+        0x884, 0x000004d5,
+        0x888, 0x00000000,
+        0x88c, 0xcc0000c0,
+        0x890, 0x00000800,
+        0x894, 0xfffffffe,
+        0x898, 0x40302010,
+        0x89c, 0x00706050,
+        0x900, 0x00000000,
+        0x904, 0x00000023,
+        0x908, 0x00000000,
+        0x90c, 0x81121313,
+        0xa00, 0x00d047c8,
+        0xa04, 0x80ff000c,
+        0xa08, 0x8c838300,
+        0xa0c, 0x2e68120f,
+        0xa10, 0x9500bb78,
+        0xa14, 0x11144028,
+        0xa18, 0x00881117,
+        0xa1c, 0x89140f00,
+        0xa20, 0x1a1b0000,
+        0xa24, 0x090e1317,
+        0xa28, 0x00000204,
+        0xa2c, 0x00d30000,
+        0xa70, 0x101fbf00,
+        0xa74, 0x00000007,
+        0xc00, 0x48071d40,
+        0xc04, 0x03a05633,
+        0xc08, 0x000000e4,
+        0xc0c, 0x6c6c6c6c,
+        0xc10, 0x08800000,
+        0xc14, 0x40000100,
+        0xc18, 0x08800000,
+        0xc1c, 0x40000100,
+        0xc20, 0x00000000,
+        0xc24, 0x00000000,
+        0xc28, 0x00000000,
+        0xc2c, 0x00000000,
+        0xc30, 0x69e9ac44,
+        0xc34, 0x469652cf,
+        0xc38, 0x49795994,
+        0xc3c, 0x0a97971c,
+        0xc40, 0x1f7c403f,
+        0xc44, 0x000100b7,
+        0xc48, 0xec020107,
+        0xc4c, 0x007f037f,
+        0xc50, 0x69543420,
+        0xc54, 0x43bc0094,
+        0xc58, 0x69543420,
+        0xc5c, 0x433c0094,
+        0xc60, 0x00000000,
+        0xc64, 0x5116848b,
+        0xc68, 0x47c00bff,
+        0xc6c, 0x00000036,
+        0xc70, 0x2c7f000d,
+        0xc74, 0x018610db,
+        0xc78, 0x0000001f,
+        0xc7c, 0x00b91612,
+        0xc80, 0x40000100,
+        0xc84, 0x20f60000,
+        0xc88, 0x40000100,
+        0xc8c, 0x20200000,
+        0xc90, 0x00121820,
+        0xc94, 0x00000000,
+        0xc98, 0x00121820,
+        0xc9c, 0x00007f7f,
+        0xca0, 0x00000000,
+        0xca4, 0x00000080,
+        0xca8, 0x00000000,
+        0xcac, 0x00000000,
+        0xcb0, 0x00000000,
+        0xcb4, 0x00000000,
+        0xcb8, 0x00000000,
+        0xcbc, 0x28000000,
+        0xcc0, 0x00000000,
+        0xcc4, 0x00000000,
+        0xcc8, 0x00000000,
+        0xccc, 0x00000000,
+        0xcd0, 0x00000000,
+        0xcd4, 0x00000000,
+        0xcd8, 0x64b22427,
+        0xcdc, 0x00766932,
+        0xce0, 0x00222222,
+        0xce4, 0x00000000,
+        0xce8, 0x37644302,
+        0xcec, 0x2f97d40c,
+        0xd00, 0x00080740,
+        0xd04, 0x00020403,
+        0xd08, 0x0000907f,
+        0xd0c, 0x20010201,
+        0xd10, 0xa0633333,
+        0xd14, 0x3333bc43,
+        0xd18, 0x7a8f5b6b,
+        0xd2c, 0xcc979975,
+        0xd30, 0x00000000,
+        0xd34, 0x80608000,
+        0xd38, 0x00000000,
+        0xd3c, 0x00027293,
+        0xd40, 0x00000000,
+        0xd44, 0x00000000,
+        0xd48, 0x00000000,
+        0xd4c, 0x00000000,
+        0xd50, 0x6437140a,
+        0xd54, 0x00000000,
+        0xd58, 0x00000000,
+        0xd5c, 0x30032064,
+        0xd60, 0x4653de68,
+        0xd64, 0x04518a3c,
+        0xd68, 0x00002101,
+        0xd6c, 0x2a201c16,
+        0xd70, 0x1812362e,
+        0xd74, 0x322c2220,
+        0xd78, 0x000e3c24,
+        0xe00, 0x2a2a2a2a,
+        0xe04, 0x2a2a2a2a,
+        0xe08, 0x03902a2a,
+        0xe10, 0x2a2a2a2a,
+        0xe14, 0x2a2a2a2a,
+        0xe18, 0x2a2a2a2a,
+        0xe1c, 0x2a2a2a2a,
+        0xe28, 0x00000000,
+        0xe30, 0x1000dc1f,
+        0xe34, 0x10008c1f,
+        0xe38, 0x02140102,
+        0xe3c, 0x681604c2,
+        0xe40, 0x01007c00,
+        0xe44, 0x01004800,
+        0xe48, 0xfb000000,
+        0xe4c, 0x000028d1,
+        0xe50, 0x1000dc1f,
+        0xe54, 0x10008c1f,
+        0xe58, 0x02140102,
+        0xe5c, 0x28160d05,
+        0xe60, 0x00000010,
+        0xe68, 0x001b25a4,
+        0xe6c, 0x63db25a4,
+        0xe70, 0x63db25a4,
+        0xe74, 0x0c1b25a4,
+        0xe78, 0x0c1b25a4,
+        0xe7c, 0x0c1b25a4,
+        0xe80, 0x0c1b25a4,
+        0xe84, 0x63db25a4,
+        0xe88, 0x0c1b25a4,
+        0xe8c, 0x63db25a4,
+        0xed0, 0x63db25a4,
+        0xed4, 0x63db25a4,
+        0xed8, 0x63db25a4,
+        0xedc, 0x001b25a4,
+        0xee0, 0x001b25a4,
+        0xeec, 0x6fdb25a4,
+        0xf14, 0x00000003,
+        0xf4c, 0x00000000,
+        0xf00, 0x00000300,
+};
+
+u32 RTL8192CEPHY_REG_1TARRAY[PHY_REG_1TARRAY_LENGTH] = {
+        0x024, 0x0011800f,
+        0x028, 0x00ffdb83,
+        0x800, 0x80040000,
+        0x804, 0x00000001,
+        0x808, 0x0000fc00,
+        0x80c, 0x0000000a,
+        0x810, 0x10005388,
+        0x814, 0x020c3d10,
+        0x818, 0x02200385,
+        0x81c, 0x00000000,
+        0x820, 0x01000100,
+        0x824, 0x00390004,
+        0x828, 0x00000000,
+        0x82c, 0x00000000,
+        0x830, 0x00000000,
+        0x834, 0x00000000,
+        0x838, 0x00000000,
+        0x83c, 0x00000000,
+        0x840, 0x00010000,
+        0x844, 0x00000000,
+        0x848, 0x00000000,
+        0x84c, 0x00000000,
+        0x850, 0x00000000,
+        0x854, 0x00000000,
+        0x858, 0x569a569a,
+        0x85c, 0x001b25a4,
+        0x860, 0x66e60230,
+        0x864, 0x061f0130,
+        0x868, 0x00000000,
+        0x86c, 0x32323200,
+        0x870, 0x07000700,
+        0x874, 0x22004000,
+        0x878, 0x00000808,
+        0x87c, 0x00000000,
+        0x880, 0xc0083070,
+        0x884, 0x000004d5,
+        0x888, 0x00000000,
+        0x88c, 0xccc000c0,
+        0x890, 0x00000800,
+        0x894, 0xfffffffe,
+        0x898, 0x40302010,
+        0x89c, 0x00706050,
+        0x900, 0x00000000,
+        0x904, 0x00000023,
+        0x908, 0x00000000,
+        0x90c, 0x81121111,
+        0xa00, 0x00d047c8,
+        0xa04, 0x80ff000c,
+        0xa08, 0x8c838300,
+        0xa0c, 0x2e68120f,
+        0xa10, 0x9500bb78,
+        0xa14, 0x11144028,
+        0xa18, 0x00881117,
+        0xa1c, 0x89140f00,
+        0xa20, 0x1a1b0000,
+        0xa24, 0x090e1317,
+        0xa28, 0x00000204,
+        0xa2c, 0x00d30000,
+        0xa70, 0x101fbf00,
+        0xa74, 0x00000007,
+        0xc00, 0x48071d40,
+        0xc04, 0x03a05611,
+        0xc08, 0x000000e4,
+        0xc0c, 0x6c6c6c6c,
+        0xc10, 0x08800000,
+        0xc14, 0x40000100,
+        0xc18, 0x08800000,
+        0xc1c, 0x40000100,
+        0xc20, 0x00000000,
+        0xc24, 0x00000000,
+        0xc28, 0x00000000,
+        0xc2c, 0x00000000,
+        0xc30, 0x69e9ac44,
+        0xc34, 0x469652cf,
+        0xc38, 0x49795994,
+        0xc3c, 0x0a97971c,
+        0xc40, 0x1f7c403f,
+        0xc44, 0x000100b7,
+        0xc48, 0xec020107,
+        0xc4c, 0x007f037f,
+        0xc50, 0x69543420,
+        0xc54, 0x43bc0094,
+        0xc58, 0x69543420,
+        0xc5c, 0x433c0094,
+        0xc60, 0x00000000,
+        0xc64, 0x5116848b,
+        0xc68, 0x47c00bff,
+        0xc6c, 0x00000036,
+        0xc70, 0x2c7f000d,
+        0xc74, 0x018610db,
+        0xc78, 0x0000001f,
+        0xc7c, 0x00b91612,
+        0xc80, 0x40000100,
+        0xc84, 0x20f60000,
+        0xc88, 0x40000100,
+        0xc8c, 0x20200000,
+        0xc90, 0x00121820,
+        0xc94, 0x00000000,
+        0xc98, 0x00121820,
+        0xc9c, 0x00007f7f,
+        0xca0, 0x00000000,
+        0xca4, 0x00000080,
+        0xca8, 0x00000000,
+        0xcac, 0x00000000,
+        0xcb0, 0x00000000,
+        0xcb4, 0x00000000,
+        0xcb8, 0x00000000,
+        0xcbc, 0x28000000,
+        0xcc0, 0x00000000,
+        0xcc4, 0x00000000,
+        0xcc8, 0x00000000,
+        0xccc, 0x00000000,
+        0xcd0, 0x00000000,
+        0xcd4, 0x00000000,
+        0xcd8, 0x64b22427,
+        0xcdc, 0x00766932,
+        0xce0, 0x00222222,
+        0xce4, 0x00000000,
+        0xce8, 0x37644302,
+        0xcec, 0x2f97d40c,
+        0xd00, 0x00080740,
+        0xd04, 0x00020401,
+        0xd08, 0x0000907f,
+        0xd0c, 0x20010201,
+        0xd10, 0xa0633333,
+        0xd14, 0x3333bc43,
+        0xd18, 0x7a8f5b6b,
+        0xd2c, 0xcc979975,
+        0xd30, 0x00000000,
+        0xd34, 0x80608000,
+        0xd38, 0x00000000,
+        0xd3c, 0x00027293,
+        0xd40, 0x00000000,
+        0xd44, 0x00000000,
+        0xd48, 0x00000000,
+        0xd4c, 0x00000000,
+        0xd50, 0x6437140a,
+        0xd54, 0x00000000,
+        0xd58, 0x00000000,
+        0xd5c, 0x30032064,
+        0xd60, 0x4653de68,
+        0xd64, 0x04518a3c,
+        0xd68, 0x00002101,
+        0xd6c, 0x2a201c16,
+        0xd70, 0x1812362e,
+        0xd74, 0x322c2220,
+        0xd78, 0x000e3c24,
+        0xe00, 0x2a2a2a2a,
+        0xe04, 0x2a2a2a2a,
+        0xe08, 0x03902a2a,
+        0xe10, 0x2a2a2a2a,
+        0xe14, 0x2a2a2a2a,
+        0xe18, 0x2a2a2a2a,
+        0xe1c, 0x2a2a2a2a,
+        0xe28, 0x00000000,
+        0xe30, 0x1000dc1f,
+        0xe34, 0x10008c1f,
+        0xe38, 0x02140102,
+        0xe3c, 0x681604c2,
+        0xe40, 0x01007c00,
+        0xe44, 0x01004800,
+        0xe48, 0xfb000000,
+        0xe4c, 0x000028d1,
+        0xe50, 0x1000dc1f,
+        0xe54, 0x10008c1f,
+        0xe58, 0x02140102,
+        0xe5c, 0x28160d05,
+        0xe60, 0x00000010,
+        0xe68, 0x001b25a4,
+        0xe6c, 0x631b25a0,
+        0xe70, 0x631b25a0,
+        0xe74, 0x081b25a0,
+        0xe78, 0x081b25a0,
+        0xe7c, 0x081b25a0,
+        0xe80, 0x081b25a0,
+        0xe84, 0x631b25a0,
+        0xe88, 0x081b25a0,
+        0xe8c, 0x631b25a0,
+        0xed0, 0x631b25a0,
+        0xed4, 0x631b25a0,
+        0xed8, 0x631b25a0,
+        0xedc, 0x001b25a0,
+        0xee0, 0x001b25a0,
+        0xeec, 0x6b1b25a0,
+        0xf14, 0x00000003,
+        0xf4c, 0x00000000,
+        0xf00, 0x00000300,
+};
+
+u32 RTL8192CEPHY_REG_ARRAY_PG[PHY_REG_ARRAY_PGLENGTH] = {
+        0xe00, 0xffffffff, 0x0a0c0c0c,
+        0xe04, 0xffffffff, 0x02040608,
+        0xe08, 0x0000ff00, 0x00000000,
+        0x86c, 0xffffff00, 0x00000000,
+        0xe10, 0xffffffff, 0x0a0c0d0e,
+        0xe14, 0xffffffff, 0x02040608,
+        0xe18, 0xffffffff, 0x0a0c0d0e,
+        0xe1c, 0xffffffff, 0x02040608,
+        0x830, 0xffffffff, 0x0a0c0c0c,
+        0x834, 0xffffffff, 0x02040608,
+        0x838, 0xffffff00, 0x00000000,
+        0x86c, 0x000000ff, 0x00000000,
+        0x83c, 0xffffffff, 0x0a0c0d0e,
+        0x848, 0xffffffff, 0x02040608,
+        0x84c, 0xffffffff, 0x0a0c0d0e,
+        0x868, 0xffffffff, 0x02040608,
+        0xe00, 0xffffffff, 0x00000000,
+        0xe04, 0xffffffff, 0x00000000,
+        0xe08, 0x0000ff00, 0x00000000,
+        0x86c, 0xffffff00, 0x00000000,
+        0xe10, 0xffffffff, 0x00000000,
+        0xe14, 0xffffffff, 0x00000000,
+        0xe18, 0xffffffff, 0x00000000,
+        0xe1c, 0xffffffff, 0x00000000,
+        0x830, 0xffffffff, 0x00000000,
+        0x834, 0xffffffff, 0x00000000,
+        0x838, 0xffffff00, 0x00000000,
+        0x86c, 0x000000ff, 0x00000000,
+        0x83c, 0xffffffff, 0x00000000,
+        0x848, 0xffffffff, 0x00000000,
+        0x84c, 0xffffffff, 0x00000000,
+        0x868, 0xffffffff, 0x00000000,
+        0xe00, 0xffffffff, 0x04040404,
+        0xe04, 0xffffffff, 0x00020204,
+        0xe08, 0x0000ff00, 0x00000000,
+        0x86c, 0xffffff00, 0x00000000,
+        0xe10, 0xffffffff, 0x06060606,
+        0xe14, 0xffffffff, 0x00020406,
+        0xe18, 0xffffffff, 0x06060606,
+        0xe1c, 0xffffffff, 0x00020406,
+        0x830, 0xffffffff, 0x04040404,
+        0x834, 0xffffffff, 0x00020204,
+        0x838, 0xffffff00, 0x00000000,
+        0x86c, 0x000000ff, 0x00000000,
+        0x83c, 0xffffffff, 0x06060606,
+        0x848, 0xffffffff, 0x00020406,
+        0x84c, 0xffffffff, 0x06060606,
+        0x868, 0xffffffff, 0x00020406,
+        0xe00, 0xffffffff, 0x00000000,
+        0xe04, 0xffffffff, 0x00000000,
+        0xe08, 0x0000ff00, 0x00000000,
+        0x86c, 0xffffff00, 0x00000000,
+        0xe10, 0xffffffff, 0x00000000,
+        0xe14, 0xffffffff, 0x00000000,
+        0xe18, 0xffffffff, 0x00000000,
+        0xe1c, 0xffffffff, 0x00000000,
+        0x830, 0xffffffff, 0x00000000,
+        0x834, 0xffffffff, 0x00000000,
+        0x838, 0xffffff00, 0x00000000,
+        0x86c, 0x000000ff, 0x00000000,
+        0x83c, 0xffffffff, 0x00000000,
+        0x848, 0xffffffff, 0x00000000,
+        0x84c, 0xffffffff, 0x00000000,
+        0x868, 0xffffffff, 0x00000000,
+};
+
+u32 RTL8192CERADIOA_2TARRAY[RADIOA_2TARRAYLENGTH] = {
+        0x000, 0x00030159,
+        0x001, 0x00031284,
+        0x002, 0x00098000,
+        0x003, 0x00018c63,
+        0x004, 0x000210e7,
+        0x009, 0x0002044f,
+        0x00a, 0x0001adb0,
+        0x00b, 0x00054867,
+        0x00c, 0x0008992e,
+        0x00d, 0x0000e52c,
+        0x00e, 0x00039ce7,
+        0x00f, 0x00000451,
+        0x019, 0x00000000,
+        0x01a, 0x00010255,
+        0x01b, 0x00060a00,
+        0x01c, 0x000fc378,
+        0x01d, 0x000a1250,
+        0x01e, 0x0004445f,
+        0x01f, 0x00080001,
+        0x020, 0x0000b614,
+        0x021, 0x0006c000,
+        0x022, 0x00000000,
+        0x023, 0x00001558,
+        0x024, 0x00000060,
+        0x025, 0x00000483,
+        0x026, 0x0004f000,
+        0x027, 0x000ec7d9,
+        0x028, 0x000977c0,
+        0x029, 0x00004783,
+        0x02a, 0x00000001,
+        0x02b, 0x00021334,
+        0x02a, 0x00000000,
+        0x02b, 0x00000054,
+        0x02a, 0x00000001,
+        0x02b, 0x00000808,
+        0x02b, 0x00053333,
+        0x02c, 0x0000000c,
+        0x02a, 0x00000002,
+        0x02b, 0x00000808,
+        0x02b, 0x0005b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000003,
+        0x02b, 0x00000808,
+        0x02b, 0x00063333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000004,
+        0x02b, 0x00000808,
+        0x02b, 0x0006b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000005,
+        0x02b, 0x00000808,
+        0x02b, 0x00073333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000006,
+        0x02b, 0x00000709,
+        0x02b, 0x0005b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000007,
+        0x02b, 0x00000709,
+        0x02b, 0x00063333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000008,
+        0x02b, 0x0000060a,
+        0x02b, 0x0004b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000009,
+        0x02b, 0x0000060a,
+        0x02b, 0x00053333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000a,
+        0x02b, 0x0000060a,
+        0x02b, 0x0005b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000b,
+        0x02b, 0x0000060a,
+        0x02b, 0x00063333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000c,
+        0x02b, 0x0000060a,
+        0x02b, 0x0006b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000d,
+        0x02b, 0x0000060a,
+        0x02b, 0x00073333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000e,
+        0x02b, 0x0000050b,
+        0x02b, 0x00066666,
+        0x02c, 0x0000001a,
+        0x02a, 0x000e0000,
+        0x010, 0x0004000f,
+        0x011, 0x000e31fc,
+        0x010, 0x0006000f,
+        0x011, 0x000ff9f8,
+        0x010, 0x0002000f,
+        0x011, 0x000203f9,
+        0x010, 0x0003000f,
+        0x011, 0x000ff500,
+        0x010, 0x00000000,
+        0x011, 0x00000000,
+        0x010, 0x0008000f,
+        0x011, 0x0003f100,
+        0x010, 0x0009000f,
+        0x011, 0x00023100,
+        0x012, 0x00032000,
+        0x012, 0x00071000,
+        0x012, 0x000b0000,
+        0x012, 0x000fc000,
+        0x013, 0x000287af,
+        0x013, 0x000244b7,
+        0x013, 0x000204ab,
+        0x013, 0x0001c49f,
+        0x013, 0x00018493,
+        0x013, 0x00014297,
+        0x013, 0x00010295,
+        0x013, 0x0000c298,
+        0x013, 0x0000819c,
+        0x013, 0x000040a8,
+        0x013, 0x0000001c,
+        0x014, 0x0001944c,
+        0x014, 0x00059444,
+        0x014, 0x0009944c,
+        0x014, 0x000d9444,
+        0x015, 0x0000f424,
+        0x015, 0x0004f424,
+        0x015, 0x0008f424,
+        0x015, 0x000cf424,
+        0x016, 0x000e0330,
+        0x016, 0x000a0330,
+        0x016, 0x00060330,
+        0x016, 0x00020330,
+        0x000, 0x00010159,
+        0x018, 0x0000f401,
+        0x0fe, 0x00000000,
+        0x0fe, 0x00000000,
+        0x01f, 0x00080003,
+        0x0fe, 0x00000000,
+        0x0fe, 0x00000000,
+        0x01e, 0x00044457,
+        0x01f, 0x00080000,
+        0x000, 0x00030159,
+};
+
+u32 RTL8192CE_RADIOB_2TARRAY[RADIOB_2TARRAYLENGTH] = {
+        0x000, 0x00030159,
+        0x001, 0x00031284,
+        0x002, 0x00098000,
+        0x003, 0x00018c63,
+        0x004, 0x000210e7,
+        0x009, 0x0002044f,
+        0x00a, 0x0001adb0,
+        0x00b, 0x00054867,
+        0x00c, 0x0008992e,
+        0x00d, 0x0000e52c,
+        0x00e, 0x00039ce7,
+        0x00f, 0x00000451,
+        0x012, 0x00032000,
+        0x012, 0x00071000,
+        0x012, 0x000b0000,
+        0x012, 0x000fc000,
+        0x013, 0x000287af,
+        0x013, 0x000244b7,
+        0x013, 0x000204ab,
+        0x013, 0x0001c49f,
+        0x013, 0x00018493,
+        0x013, 0x00014297,
+        0x013, 0x00010295,
+        0x013, 0x0000c298,
+        0x013, 0x0000819c,
+        0x013, 0x000040a8,
+        0x013, 0x0000001c,
+        0x014, 0x0001944c,
+        0x014, 0x00059444,
+        0x014, 0x0009944c,
+        0x014, 0x000d9444,
+        0x015, 0x0000f424,
+        0x015, 0x0004f424,
+        0x015, 0x0008f424,
+        0x015, 0x000cf424,
+        0x016, 0x000e0330,
+        0x016, 0x000a0330,
+        0x016, 0x00060330,
+        0x016, 0x00020330,
+};
+
+u32 RTL8192CE_RADIOA_1TARRAY[RADIOA_1TARRAYLENGTH] = {
+        0x000, 0x00030159,
+        0x001, 0x00031284,
+        0x002, 0x00098000,
+        0x003, 0x00018c63,
+        0x004, 0x000210e7,
+        0x009, 0x0002044f,
+        0x00a, 0x0001adb0,
+        0x00b, 0x00054867,
+        0x00c, 0x0008992e,
+        0x00d, 0x0000e52c,
+        0x00e, 0x00039ce7,
+        0x00f, 0x00000451,
+        0x019, 0x00000000,
+        0x01a, 0x00010255,
+        0x01b, 0x00060a00,
+        0x01c, 0x000fc378,
+        0x01d, 0x000a1250,
+        0x01e, 0x0004445f,
+        0x01f, 0x00080001,
+        0x020, 0x0000b614,
+        0x021, 0x0006c000,
+        0x022, 0x00000000,
+        0x023, 0x00001558,
+        0x024, 0x00000060,
+        0x025, 0x00000483,
+        0x026, 0x0004f000,
+        0x027, 0x000ec7d9,
+        0x028, 0x000977c0,
+        0x029, 0x00004783,
+        0x02a, 0x00000001,
+        0x02b, 0x00021334,
+        0x02a, 0x00000000,
+        0x02b, 0x00000054,
+        0x02a, 0x00000001,
+        0x02b, 0x00000808,
+        0x02b, 0x00053333,
+        0x02c, 0x0000000c,
+        0x02a, 0x00000002,
+        0x02b, 0x00000808,
+        0x02b, 0x0005b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000003,
+        0x02b, 0x00000808,
+        0x02b, 0x00063333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000004,
+        0x02b, 0x00000808,
+        0x02b, 0x0006b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000005,
+        0x02b, 0x00000808,
+        0x02b, 0x00073333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000006,
+        0x02b, 0x00000709,
+        0x02b, 0x0005b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000007,
+        0x02b, 0x00000709,
+        0x02b, 0x00063333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000008,
+        0x02b, 0x0000060a,
+        0x02b, 0x0004b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x00000009,
+        0x02b, 0x0000060a,
+        0x02b, 0x00053333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000a,
+        0x02b, 0x0000060a,
+        0x02b, 0x0005b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000b,
+        0x02b, 0x0000060a,
+        0x02b, 0x00063333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000c,
+        0x02b, 0x0000060a,
+        0x02b, 0x0006b333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000d,
+        0x02b, 0x0000060a,
+        0x02b, 0x00073333,
+        0x02c, 0x0000000d,
+        0x02a, 0x0000000e,
+        0x02b, 0x0000050b,
+        0x02b, 0x00066666,
+        0x02c, 0x0000001a,
+        0x02a, 0x000e0000,
+        0x010, 0x0004000f,
+        0x011, 0x000e31fc,
+        0x010, 0x0006000f,
+        0x011, 0x000ff9f8,
+        0x010, 0x0002000f,
+        0x011, 0x000203f9,
+        0x010, 0x0003000f,
+        0x011, 0x000ff500,
+        0x010, 0x00000000,
+        0x011, 0x00000000,
+        0x010, 0x0008000f,
+        0x011, 0x0003f100,
+        0x010, 0x0009000f,
+        0x011, 0x00023100,
+        0x012, 0x00032000,
+        0x012, 0x00071000,
+        0x012, 0x000b0000,
+        0x012, 0x000fc000,
+        0x013, 0x000287af,
+        0x013, 0x000244b7,
+        0x013, 0x000204ab,
+        0x013, 0x0001c49f,
+        0x013, 0x00018493,
+        0x013, 0x00014297,
+        0x013, 0x00010295,
+        0x013, 0x0000c298,
+        0x013, 0x0000819c,
+        0x013, 0x000040a8,
+        0x013, 0x0000001c,
+        0x014, 0x0001944c,
+        0x014, 0x00059444,
+        0x014, 0x0009944c,
+        0x014, 0x000d9444,
+        0x015, 0x0000f424,
+        0x015, 0x0004f424,
+        0x015, 0x0008f424,
+        0x015, 0x000cf424,
+        0x016, 0x000e0330,
+        0x016, 0x000a0330,
+        0x016, 0x00060330,
+        0x016, 0x00020330,
+        0x000, 0x00010159,
+        0x018, 0x0000f401,
+        0x0fe, 0x00000000,
+        0x0fe, 0x00000000,
+        0x01f, 0x00080003,
+        0x0fe, 0x00000000,
+        0x0fe, 0x00000000,
+        0x01e, 0x00044457,
+        0x01f, 0x00080000,
+        0x000, 0x00030159,
+};
+
+u32 RTL8192CE_RADIOB_1TARRAY[RADIOB_1TARRAYLENGTH] = {
+        0x0,
+};
+
+u32 RTL8192CEMAC_2T_ARRAY[MAC_2T_ARRAYLENGTH] = {
+        0x420, 0x00000080,
+        0x423, 0x00000000,
+        0x430, 0x00000000,
+        0x431, 0x00000000,
+        0x432, 0x00000000,
+        0x433, 0x00000001,
+        0x434, 0x00000004,
+        0x435, 0x00000005,
+        0x436, 0x00000006,
+        0x437, 0x00000007,
+        0x438, 0x00000000,
+        0x439, 0x00000000,
+        0x43a, 0x00000000,
+        0x43b, 0x00000001,
+        0x43c, 0x00000004,
+        0x43d, 0x00000005,
+        0x43e, 0x00000006,
+        0x43f, 0x00000007,
+        0x440, 0x0000005d,
+        0x441, 0x00000001,
+        0x442, 0x00000000,
+        0x444, 0x00000015,
+        0x445, 0x000000f0,
+        0x446, 0x0000000f,
+        0x447, 0x00000000,
+        0x458, 0x00000041,
+        0x459, 0x000000a8,
+        0x45a, 0x00000072,
+        0x45b, 0x000000b9,
+        0x460, 0x00000088,
+        0x461, 0x00000088,
+        0x462, 0x00000006,
+        0x463, 0x00000003,
+        0x4c8, 0x00000004,
+        0x4c9, 0x00000008,
+        0x4cc, 0x00000002,
+        0x4cd, 0x00000028,
+        0x4ce, 0x00000001,
+        0x500, 0x00000026,
+        0x501, 0x000000a2,
+        0x502, 0x0000002f,
+        0x503, 0x00000000,
+        0x504, 0x00000028,
+        0x505, 0x000000a3,
+        0x506, 0x0000005e,
+        0x507, 0x00000000,
+        0x508, 0x0000002b,
+        0x509, 0x000000a4,
+        0x50a, 0x0000005e,
+        0x50b, 0x00000000,
+        0x50c, 0x0000004f,
+        0x50d, 0x000000a4,
+        0x50e, 0x00000000,
+        0x50f, 0x00000000,
+        0x512, 0x0000001c,
+        0x514, 0x0000000a,
+        0x515, 0x00000010,
+        0x516, 0x0000000a,
+        0x517, 0x00000010,
+        0x51a, 0x00000016,
+        0x524, 0x0000000f,
+        0x525, 0x0000004f,
+        0x546, 0x00000020,
+        0x547, 0x00000000,
+        0x559, 0x00000002,
+        0x55a, 0x00000002,
+        0x55d, 0x000000ff,
+        0x605, 0x00000030,
+        0x608, 0x0000000e,
+        0x609, 0x0000002a,
+        0x652, 0x00000020,
+        0x63c, 0x0000000a,
+        0x63d, 0x0000000a,
+        0x700, 0x00000021,
+        0x701, 0x00000043,
+        0x702, 0x00000065,
+        0x703, 0x00000087,
+        0x708, 0x00000021,
+        0x709, 0x00000043,
+        0x70a, 0x00000065,
+        0x70b, 0x00000087,
+};
+
+u32 RTL8192CEAGCTAB_2TARRAY[AGCTAB_2TARRAYLENGTH] = {
+        0xc78, 0x7b000001,
+        0xc78, 0x7b010001,
+        0xc78, 0x7b020001,
+        0xc78, 0x7b030001,
+        0xc78, 0x7b040001,
+        0xc78, 0x7b050001,
+        0xc78, 0x7a060001,
+        0xc78, 0x79070001,
+        0xc78, 0x78080001,
+        0xc78, 0x77090001,
+        0xc78, 0x760a0001,
+        0xc78, 0x750b0001,
+        0xc78, 0x740c0001,
+        0xc78, 0x730d0001,
+        0xc78, 0x720e0001,
+        0xc78, 0x710f0001,
+        0xc78, 0x70100001,
+        0xc78, 0x6f110001,
+        0xc78, 0x6e120001,
+        0xc78, 0x6d130001,
+        0xc78, 0x6c140001,
+        0xc78, 0x6b150001,
+        0xc78, 0x6a160001,
+        0xc78, 0x69170001,
+        0xc78, 0x68180001,
+        0xc78, 0x67190001,
+        0xc78, 0x661a0001,
+        0xc78, 0x651b0001,
+        0xc78, 0x641c0001,
+        0xc78, 0x631d0001,
+        0xc78, 0x621e0001,
+        0xc78, 0x611f0001,
+        0xc78, 0x60200001,
+        0xc78, 0x49210001,
+        0xc78, 0x48220001,
+        0xc78, 0x47230001,
+        0xc78, 0x46240001,
+        0xc78, 0x45250001,
+        0xc78, 0x44260001,
+        0xc78, 0x43270001,
+        0xc78, 0x42280001,
+        0xc78, 0x41290001,
+        0xc78, 0x402a0001,
+        0xc78, 0x262b0001,
+        0xc78, 0x252c0001,
+        0xc78, 0x242d0001,
+        0xc78, 0x232e0001,
+        0xc78, 0x222f0001,
+        0xc78, 0x21300001,
+        0xc78, 0x20310001,
+        0xc78, 0x06320001,
+        0xc78, 0x05330001,
+        0xc78, 0x04340001,
+        0xc78, 0x03350001,
+        0xc78, 0x02360001,
+        0xc78, 0x01370001,
+        0xc78, 0x00380001,
+        0xc78, 0x00390001,
+        0xc78, 0x003a0001,
+        0xc78, 0x003b0001,
+        0xc78, 0x003c0001,
+        0xc78, 0x003d0001,
+        0xc78, 0x003e0001,
+        0xc78, 0x003f0001,
+        0xc78, 0x7b400001,
+        0xc78, 0x7b410001,
+        0xc78, 0x7b420001,
+        0xc78, 0x7b430001,
+        0xc78, 0x7b440001,
+        0xc78, 0x7b450001,
+        0xc78, 0x7a460001,
+        0xc78, 0x79470001,
+        0xc78, 0x78480001,
+        0xc78, 0x77490001,
+        0xc78, 0x764a0001,
+        0xc78, 0x754b0001,
+        0xc78, 0x744c0001,
+        0xc78, 0x734d0001,
+        0xc78, 0x724e0001,
+        0xc78, 0x714f0001,
+        0xc78, 0x70500001,
+        0xc78, 0x6f510001,
+        0xc78, 0x6e520001,
+        0xc78, 0x6d530001,
+        0xc78, 0x6c540001,
+        0xc78, 0x6b550001,
+        0xc78, 0x6a560001,
+        0xc78, 0x69570001,
+        0xc78, 0x68580001,
+        0xc78, 0x67590001,
+        0xc78, 0x665a0001,
+        0xc78, 0x655b0001,
+        0xc78, 0x645c0001,
+        0xc78, 0x635d0001,
+        0xc78, 0x625e0001,
+        0xc78, 0x615f0001,
+        0xc78, 0x60600001,
+        0xc78, 0x49610001,
+        0xc78, 0x48620001,
+        0xc78, 0x47630001,
+        0xc78, 0x46640001,
+        0xc78, 0x45650001,
+        0xc78, 0x44660001,
+        0xc78, 0x43670001,
+        0xc78, 0x42680001,
+        0xc78, 0x41690001,
+        0xc78, 0x406a0001,
+        0xc78, 0x266b0001,
+        0xc78, 0x256c0001,
+        0xc78, 0x246d0001,
+        0xc78, 0x236e0001,
+        0xc78, 0x226f0001,
+        0xc78, 0x21700001,
+        0xc78, 0x20710001,
+        0xc78, 0x06720001,
+        0xc78, 0x05730001,
+        0xc78, 0x04740001,
+        0xc78, 0x03750001,
+        0xc78, 0x02760001,
+        0xc78, 0x01770001,
+        0xc78, 0x00780001,
+        0xc78, 0x00790001,
+        0xc78, 0x007a0001,
+        0xc78, 0x007b0001,
+        0xc78, 0x007c0001,
+        0xc78, 0x007d0001,
+        0xc78, 0x007e0001,
+        0xc78, 0x007f0001,
+        0xc78, 0x3800001e,
+        0xc78, 0x3801001e,
+        0xc78, 0x3802001e,
+        0xc78, 0x3803001e,
+        0xc78, 0x3804001e,
+        0xc78, 0x3805001e,
+        0xc78, 0x3806001e,
+        0xc78, 0x3807001e,
+        0xc78, 0x3808001e,
+        0xc78, 0x3c09001e,
+        0xc78, 0x3e0a001e,
+        0xc78, 0x400b001e,
+        0xc78, 0x440c001e,
+        0xc78, 0x480d001e,
+        0xc78, 0x4c0e001e,
+        0xc78, 0x500f001e,
+        0xc78, 0x5210001e,
+        0xc78, 0x5611001e,
+        0xc78, 0x5a12001e,
+        0xc78, 0x5e13001e,
+        0xc78, 0x6014001e,
+        0xc78, 0x6015001e,
+        0xc78, 0x6016001e,
+        0xc78, 0x6217001e,
+        0xc78, 0x6218001e,
+        0xc78, 0x6219001e,
+        0xc78, 0x621a001e,
+        0xc78, 0x621b001e,
+        0xc78, 0x621c001e,
+        0xc78, 0x621d001e,
+        0xc78, 0x621e001e,
+        0xc78, 0x621f001e,
+};
+
+u32 RTL8192CEAGCTAB_1TARRAY[AGCTAB_1TARRAYLENGTH] = {
+        0xc78, 0x7b000001,
+        0xc78, 0x7b010001,
+        0xc78, 0x7b020001,
+        0xc78, 0x7b030001,
+        0xc78, 0x7b040001,
+        0xc78, 0x7b050001,
+        0xc78, 0x7a060001,
+        0xc78, 0x79070001,
+        0xc78, 0x78080001,
+        0xc78, 0x77090001,
+        0xc78, 0x760a0001,
+        0xc78, 0x750b0001,
+        0xc78, 0x740c0001,
+        0xc78, 0x730d0001,
+        0xc78, 0x720e0001,
+        0xc78, 0x710f0001,
+        0xc78, 0x70100001,
+        0xc78, 0x6f110001,
+        0xc78, 0x6e120001,
+        0xc78, 0x6d130001,
+        0xc78, 0x6c140001,
+        0xc78, 0x6b150001,
+        0xc78, 0x6a160001,
+        0xc78, 0x69170001,
+        0xc78, 0x68180001,
+        0xc78, 0x67190001,
+        0xc78, 0x661a0001,
+        0xc78, 0x651b0001,
+        0xc78, 0x641c0001,
+        0xc78, 0x631d0001,
+        0xc78, 0x621e0001,
+        0xc78, 0x611f0001,
+        0xc78, 0x60200001,
+        0xc78, 0x49210001,
+        0xc78, 0x48220001,
+        0xc78, 0x47230001,
+        0xc78, 0x46240001,
+        0xc78, 0x45250001,
+        0xc78, 0x44260001,
+        0xc78, 0x43270001,
+        0xc78, 0x42280001,
+        0xc78, 0x41290001,
+        0xc78, 0x402a0001,
+        0xc78, 0x262b0001,
+        0xc78, 0x252c0001,
+        0xc78, 0x242d0001,
+        0xc78, 0x232e0001,
+        0xc78, 0x222f0001,
+        0xc78, 0x21300001,
+        0xc78, 0x20310001,
+        0xc78, 0x06320001,
+        0xc78, 0x05330001,
+        0xc78, 0x04340001,
+        0xc78, 0x03350001,
+        0xc78, 0x02360001,
+        0xc78, 0x01370001,
+        0xc78, 0x00380001,
+        0xc78, 0x00390001,
+        0xc78, 0x003a0001,
+        0xc78, 0x003b0001,
+        0xc78, 0x003c0001,
+        0xc78, 0x003d0001,
+        0xc78, 0x003e0001,
+        0xc78, 0x003f0001,
+        0xc78, 0x7b400001,
+        0xc78, 0x7b410001,
+        0xc78, 0x7b420001,
+        0xc78, 0x7b430001,
+        0xc78, 0x7b440001,
+        0xc78, 0x7b450001,
+        0xc78, 0x7a460001,
+        0xc78, 0x79470001,
+        0xc78, 0x78480001,
+        0xc78, 0x77490001,
+        0xc78, 0x764a0001,
+        0xc78, 0x754b0001,
+        0xc78, 0x744c0001,
+        0xc78, 0x734d0001,
+        0xc78, 0x724e0001,
+        0xc78, 0x714f0001,
+        0xc78, 0x70500001,
+        0xc78, 0x6f510001,
+        0xc78, 0x6e520001,
+        0xc78, 0x6d530001,
+        0xc78, 0x6c540001,
+        0xc78, 0x6b550001,
+        0xc78, 0x6a560001,
+        0xc78, 0x69570001,
+        0xc78, 0x68580001,
+        0xc78, 0x67590001,
+        0xc78, 0x665a0001,
+        0xc78, 0x655b0001,
+        0xc78, 0x645c0001,
+        0xc78, 0x635d0001,
+        0xc78, 0x625e0001,
+        0xc78, 0x615f0001,
+        0xc78, 0x60600001,
+        0xc78, 0x49610001,
+        0xc78, 0x48620001,
+        0xc78, 0x47630001,
+        0xc78, 0x46640001,
+        0xc78, 0x45650001,
+        0xc78, 0x44660001,
+        0xc78, 0x43670001,
+        0xc78, 0x42680001,
+        0xc78, 0x41690001,
+        0xc78, 0x406a0001,
+        0xc78, 0x266b0001,
+        0xc78, 0x256c0001,
+        0xc78, 0x246d0001,
+        0xc78, 0x236e0001,
+        0xc78, 0x226f0001,
+        0xc78, 0x21700001,
+        0xc78, 0x20710001,
+        0xc78, 0x06720001,
+        0xc78, 0x05730001,
+        0xc78, 0x04740001,
+        0xc78, 0x03750001,
+        0xc78, 0x02760001,
+        0xc78, 0x01770001,
+        0xc78, 0x00780001,
+        0xc78, 0x00790001,
+        0xc78, 0x007a0001,
+        0xc78, 0x007b0001,
+        0xc78, 0x007c0001,
+        0xc78, 0x007d0001,
+        0xc78, 0x007e0001,
+        0xc78, 0x007f0001,
+        0xc78, 0x3800001e,
+        0xc78, 0x3801001e,
+        0xc78, 0x3802001e,
+        0xc78, 0x3803001e,
+        0xc78, 0x3804001e,
+        0xc78, 0x3805001e,
+        0xc78, 0x3806001e,
+        0xc78, 0x3807001e,
+        0xc78, 0x3808001e,
+        0xc78, 0x3c09001e,
+        0xc78, 0x3e0a001e,
+        0xc78, 0x400b001e,
+        0xc78, 0x440c001e,
+        0xc78, 0x480d001e,
+        0xc78, 0x4c0e001e,
+        0xc78, 0x500f001e,
+        0xc78, 0x5210001e,
+        0xc78, 0x5611001e,
+        0xc78, 0x5a12001e,
+        0xc78, 0x5e13001e,
+        0xc78, 0x6014001e,
+        0xc78, 0x6015001e,
+        0xc78, 0x6016001e,
+        0xc78, 0x6217001e,
+        0xc78, 0x6218001e,
+        0xc78, 0x6219001e,
+        0xc78, 0x621a001e,
+        0xc78, 0x621b001e,
+        0xc78, 0x621c001e,
+        0xc78, 0x621d001e,
+        0xc78, 0x621e001e,
+        0xc78, 0x621f001e,
+};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/table.h b/drivers/net/wireless/rtlwifi/rtl8192ce/table.h
new file mode 100644
index 000000000000..3a6e8b6aeee0
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/table.h
@@ -0,0 +1,58 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Created on  2010/ 5/18,  1:41
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92CE_TABLE__H_
+#define __RTL92CE_TABLE__H_
+
+#include <linux/types.h>
+
+#define PHY_REG_2TARRAY_LENGTH  374
+extern u32 RTL8192CEPHY_REG_2TARRAY[PHY_REG_2TARRAY_LENGTH];
+#define PHY_REG_1TARRAY_LENGTH  374
+extern u32 RTL8192CEPHY_REG_1TARRAY[PHY_REG_1TARRAY_LENGTH];
+#define PHY_REG_ARRAY_PGLENGTH  192
+extern u32 RTL8192CEPHY_REG_ARRAY_PG[PHY_REG_ARRAY_PGLENGTH];
+#define RADIOA_2TARRAYLENGTH    282
+extern u32 RTL8192CERADIOA_2TARRAY[RADIOA_2TARRAYLENGTH];
+#define RADIOB_2TARRAYLENGTH    78
+extern u32 RTL8192CE_RADIOB_2TARRAY[RADIOB_2TARRAYLENGTH];
+#define RADIOA_1TARRAYLENGTH    282
+extern u32 RTL8192CE_RADIOA_1TARRAY[RADIOA_1TARRAYLENGTH];
+#define RADIOB_1TARRAYLENGTH    1
+extern u32 RTL8192CE_RADIOB_1TARRAY[RADIOB_1TARRAYLENGTH];
+#define MAC_2T_ARRAYLENGTH      162
+extern u32 RTL8192CEMAC_2T_ARRAY[MAC_2T_ARRAYLENGTH];
+#define AGCTAB_2TARRAYLENGTH    320
+extern u32 RTL8192CEAGCTAB_2TARRAY[AGCTAB_2TARRAYLENGTH];
+#define AGCTAB_1TARRAYLENGTH    320
+extern u32 RTL8192CEAGCTAB_1TARRAY[AGCTAB_1TARRAYLENGTH];
+
+#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
new file mode 100644
index 000000000000..bf5852f2d634
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
@@ -0,0 +1,1031 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#include "../wifi.h"
+#include "../pci.h"
+#include "../base.h"
+#include "reg.h"
+#include "def.h"
+#include "phy.h"
+#include "trx.h"
+#include "led.h"
+
+static enum rtl_desc_qsel _rtl92ce_map_hwqueue_to_fwqueue(u16 fc,
+                                                          unsigned int
+                                                          skb_queue)
+{
+        enum rtl_desc_qsel qsel;
+
+        if (unlikely(ieee80211_is_beacon(fc))) {
+                qsel = QSLT_BEACON;
+                return qsel;
+        }
+
+        if (ieee80211_is_mgmt(fc)) {
+                qsel = QSLT_MGNT;
+                return qsel;
+        }
+
+        switch (skb_queue) {
+        case VO_QUEUE:
+                qsel = QSLT_VO;
+                break;
+        case VI_QUEUE:
+                qsel = QSLT_VI;
+                break;
+        case BE_QUEUE:
+                qsel = QSLT_BE;
+                break;
+        case BK_QUEUE:
+                qsel = QSLT_BK;
+                break;
+        default:
+                qsel = QSLT_BE;
+                RT_ASSERT(false, ("BE queue, skb_queue:%d,"
+                                  " set qsel = 0x%X\n", skb_queue, QSLT_BE));
+                break;
+        }
+        return qsel;
+}
+
+static int _rtl92ce_rate_mapping(bool isht, u8 desc_rate, bool first_ampdu)
+{
+        int rate_idx;
+
+        if (first_ampdu) {
+                if (false == isht) {
+                        switch (desc_rate) {
+                        case DESC92C_RATE1M:
+                                rate_idx = 0;
+                                break;
+                        case DESC92C_RATE2M:
+                                rate_idx = 1;
+                                break;
+                        case DESC92C_RATE5_5M:
+                                rate_idx = 2;
+                                break;
+                        case DESC92C_RATE11M:
+                                rate_idx = 3;
+                                break;
+                        case DESC92C_RATE6M:
+                                rate_idx = 4;
+                                break;
+                        case DESC92C_RATE9M:
+                                rate_idx = 5;
+                                break;
+                        case DESC92C_RATE12M:
+                                rate_idx = 6;
+                                break;
+                        case DESC92C_RATE18M:
+                                rate_idx = 7;
+                                break;
+                        case DESC92C_RATE24M:
+                                rate_idx = 8;
+                                break;
+                        case DESC92C_RATE36M:
+                                rate_idx = 9;
+                                break;
+                        case DESC92C_RATE48M:
+                                rate_idx = 10;
+                                break;
+                        case DESC92C_RATE54M:
+                                rate_idx = 11;
+                                break;
+                        default:
+                                rate_idx = 0;
+                                break;
+                        }
+                } else {
+                        rate_idx = 11;
+                }
+
+                return rate_idx;
+        }
+
+        switch (desc_rate) {
+        case DESC92C_RATE1M:
+                rate_idx = 0;
+                break;
+        case DESC92C_RATE2M:
+                rate_idx = 1;
+                break;
+        case DESC92C_RATE5_5M:
+                rate_idx = 2;
+                break;
+        case DESC92C_RATE11M:
+                rate_idx = 3;
+                break;
+        case DESC92C_RATE6M:
+                rate_idx = 4;
+                break;
+        case DESC92C_RATE9M:
+                rate_idx = 5;
+                break;
+        case DESC92C_RATE12M:
+                rate_idx = 6;
+                break;
+        case DESC92C_RATE18M:
+                rate_idx = 7;
+                break;
+        case DESC92C_RATE24M:
+                rate_idx = 8;
+                break;
+        case DESC92C_RATE36M:
+                rate_idx = 9;
+                break;
+        case DESC92C_RATE48M:
+                rate_idx = 10;
+                break;
+        case DESC92C_RATE54M:
+                rate_idx = 11;
+                break;
+        default:
+                rate_idx = 11;
+                break;
+        }
+        return rate_idx;
+}
+
+static u8 _rtl92c_query_rxpwrpercentage(char antpower)
+{
+        if ((antpower <= -100) || (antpower >= 20))
+                return 0;
+        else if (antpower >= 0)
+                return 100;
+        else
+                return 100 + antpower;
+}
+
+static u8 _rtl92c_evm_db_to_percentage(char value)
+{
+        char ret_val;
+        ret_val = value;
+
+        if (ret_val >= 0)
+                ret_val = 0;
+
+        if (ret_val <= -33)
+                ret_val = -33;
+
+        ret_val = 0 - ret_val;
+        ret_val *= 3;
+
+        if (ret_val == 99)
+                ret_val = 100;
+
+        return ret_val;
+}
+
+static long _rtl92ce_translate_todbm(struct ieee80211_hw *hw,
+                                     u8 signal_strength_index)
+{
+        long signal_power;
+
+        signal_power = (long)((signal_strength_index + 1) >> 1);
+        signal_power -= 95;
+        return signal_power;
+}
+
+static long _rtl92ce_signal_scale_mapping(struct ieee80211_hw *hw,
+                long currsig)
+{
+        long retsig;
+
+        if (currsig >= 61 && currsig <= 100)
+                retsig = 90 + ((currsig - 60) / 4);
+        else if (currsig >= 41 && currsig <= 60)
+                retsig = 78 + ((currsig - 40) / 2);
+        else if (currsig >= 31 && currsig <= 40)
+                retsig = 66 + (currsig - 30);
+        else if (currsig >= 21 && currsig <= 30)
+                retsig = 54 + (currsig - 20);
+        else if (currsig >= 5 && currsig <= 20)
+                retsig = 42 + (((currsig - 5) * 2) / 3);
+        else if (currsig == 4)
+                retsig = 36;
+        else if (currsig == 3)
+                retsig = 27;
+        else if (currsig == 2)
+                retsig = 18;
+        else if (currsig == 1)
+                retsig = 9;
+        else
+                retsig = currsig;
+
+        return retsig;
+}
+
+static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
+                                       struct rtl_stats *pstats,
+                                       struct rx_desc_92c *pdesc,
+                                       struct rx_fwinfo_92c *p_drvinfo,
+                                       bool bpacket_match_bssid,
+                                       bool bpacket_toself,
+                                       bool b_packet_beacon)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct phy_sts_cck_8192s_t *cck_buf;
+        s8 rx_pwr_all, rx_pwr[4];
+        u8 rf_rx_num, evm, pwdb_all;
+        u8 i, max_spatial_stream;
+        u32 rssi, total_rssi;
+        bool is_cck_rate;
+
+        is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
+        pstats->b_packet_matchbssid = bpacket_match_bssid;
+        pstats->b_packet_toself = bpacket_toself;
+        pstats->b_is_cck = is_cck_rate;
+        pstats->b_packet_beacon = b_packet_beacon;
+        pstats->b_is_cck = is_cck_rate;
+        pstats->rx_mimo_signalquality[0] = -1;
+        pstats->rx_mimo_signalquality[1] = -1;
+
+        if (is_cck_rate) {
+                u8 report, cck_highpwr;
+                cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
+
+                cck_highpwr = (u8) rtl_get_bbreg(hw,
+                                         RFPGA0_XA_HSSIPARAMETER2,
+                                         BIT(9));
+                if (!cck_highpwr) {
+                        u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
+                        report = cck_buf->cck_agc_rpt & 0xc0;
+                        report = report >> 6;
+                        switch (report) {
+                        case 0x3:
+                                rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
+                                break;
+                        case 0x2:
+                                rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
+                                break;
+                        case 0x1:
+                                rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
+                                break;
+                        case 0x0:
+                                rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
+                                break;
+                        }
+                } else {
+                        u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
+                        report = p_drvinfo->cfosho[0] & 0x60;
+                        report = report >> 5;
+                        switch (report) {
+                        case 0x3:
+                                rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
+                                break;
+                        case 0x2:
+                                rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
+                                break;
+                        case 0x1:
+                                rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
+                                break;
+                        case 0x0:
+                                rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
+                                break;
+                        }
+                }
+
+                pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
+                pstats->rx_pwdb_all = pwdb_all;
+                pstats->recvsignalpower = rx_pwr_all;
+
+                if (bpacket_match_bssid) {
+                        u8 sq;
+                        if (pstats->rx_pwdb_all > 40)
+                                sq = 100;
+                        else {
+                                sq = cck_buf->sq_rpt;
+                                if (sq > 64)
+                                        sq = 0;
+                                else if (sq < 20)
+                                        sq = 100;
+                                else
+                                        sq = ((64 - sq) * 100) / 44;
+                        }
+
+                        pstats->signalquality = sq;
+                        pstats->rx_mimo_signalquality[0] = sq;
+                        pstats->rx_mimo_signalquality[1] = -1;
+                }
+        } else {
+                rtlpriv->dm.brfpath_rxenable[0] =
+                    rtlpriv->dm.brfpath_rxenable[1] = true;
+                for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
+                        if (rtlpriv->dm.brfpath_rxenable[i])
+                                rf_rx_num++;
+
+                        rx_pwr[i] =
+                            ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
+                        rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
+                        total_rssi += rssi;
+                        rtlpriv->stats.rx_snr_db[i] =
+                            (long)(p_drvinfo->rxsnr[i] / 2);
+
+                        if (bpacket_match_bssid)
+                                pstats->rx_mimo_signalstrength[i] = (u8) rssi;
+                }
+
+                rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
+                pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
+                pstats->rx_pwdb_all = pwdb_all;
+                pstats->rxpower = rx_pwr_all;
+                pstats->recvsignalpower = rx_pwr_all;
+
+                if (pdesc->rxht && pdesc->rxmcs >= DESC92C_RATEMCS8 &&
+                    pdesc->rxmcs <= DESC92C_RATEMCS15)
+                        max_spatial_stream = 2;
+                else
+                        max_spatial_stream = 1;
+
+                for (i = 0; i < max_spatial_stream; i++) {
+                        evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
+
+                        if (bpacket_match_bssid) {
+                                if (i == 0)
+                                        pstats->signalquality =
+                                            (u8) (evm & 0xff);
+                                pstats->rx_mimo_signalquality[i] =
+                                    (u8) (evm & 0xff);
+                        }
+                }
+        }
+
+        if (is_cck_rate)
+                pstats->signalstrength =
+                    (u8) (_rtl92ce_signal_scale_mapping(hw, pwdb_all));
+        else if (rf_rx_num != 0)
+                pstats->signalstrength =
+                    (u8) (_rtl92ce_signal_scale_mapping
+                          (hw, total_rssi /= rf_rx_num));
+}
+
+static void _rtl92ce_process_ui_rssi(struct ieee80211_hw *hw,
+                struct rtl_stats *pstats)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_phy *rtlphy = &(rtlpriv->phy);
+        u8 rfpath;
+        u32 last_rssi, tmpval;
+
+        if (pstats->b_packet_toself || pstats->b_packet_beacon) {
+                rtlpriv->stats.rssi_calculate_cnt++;
+
+                if (rtlpriv->stats.ui_rssi.total_num++ >=
+                    PHY_RSSI_SLID_WIN_MAX) {
+                        rtlpriv->stats.ui_rssi.total_num =
+                            PHY_RSSI_SLID_WIN_MAX;
+                        last_rssi =
+                            rtlpriv->stats.ui_rssi.elements[rtlpriv->
+                                                    stats.ui_rssi.index];
+                        rtlpriv->stats.ui_rssi.total_val -= last_rssi;
+                }
+
+                rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
+                rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.
+                                                index++] =
+                    pstats->signalstrength;
+
+                if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
+                        rtlpriv->stats.ui_rssi.index = 0;
+
+                tmpval = rtlpriv->stats.ui_rssi.total_val /
+                    rtlpriv->stats.ui_rssi.total_num;
+                rtlpriv->stats.signal_strength =
+                    _rtl92ce_translate_todbm(hw, (u8) tmpval);
+                pstats->rssi = rtlpriv->stats.signal_strength;
+        }
+
+        if (!pstats->b_is_cck && pstats->b_packet_toself) {
+                for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
+                     rfpath++) {
+
+                        if (!rtl8192_phy_check_is_legal_rfpath(hw, rfpath))
+                                continue;
+
+                        if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
+                                rtlpriv->stats.rx_rssi_percentage[rfpath] =
+                                    pstats->rx_mimo_signalstrength[rfpath];
+
+                        }
+
+                        if (pstats->rx_mimo_signalstrength[rfpath] >
+                            rtlpriv->stats.rx_rssi_percentage[rfpath]) {
+                                rtlpriv->stats.rx_rssi_percentage[rfpath] =
+                                    ((rtlpriv->stats.
+                                      rx_rssi_percentage[rfpath] *
+                                      (RX_SMOOTH_FACTOR - 1)) +
+                                     (pstats->rx_mimo_signalstrength[rfpath])) /
+                                    (RX_SMOOTH_FACTOR);
+
+                                rtlpriv->stats.rx_rssi_percentage[rfpath] =
+                                    rtlpriv->stats.rx_rssi_percentage[rfpath] +
+                                    1;
+                        } else {
+                                rtlpriv->stats.rx_rssi_percentage[rfpath] =
+                                    ((rtlpriv->stats.
+                                      rx_rssi_percentage[rfpath] *
+                                      (RX_SMOOTH_FACTOR - 1)) +
+                                     (pstats->rx_mimo_signalstrength[rfpath])) /
+                                    (RX_SMOOTH_FACTOR);
+                        }
+
+                }
+        }
+}
+
+static void _rtl92ce_update_rxsignalstatistics(struct ieee80211_hw *hw,
+                                               struct rtl_stats *pstats)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        int weighting;
+
+        if (rtlpriv->stats.recv_signal_power == 0)
+                rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
+
+        if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
+                weighting = 5;
+
+        else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
+                weighting = (-5);
+
+        rtlpriv->stats.recv_signal_power =
+            (rtlpriv->stats.recv_signal_power * 5 +
+             pstats->recvsignalpower + weighting) / 6;
+}
+
+static void _rtl92ce_process_pwdb(struct ieee80211_hw *hw,
+                struct rtl_stats *pstats)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        long undecorated_smoothed_pwdb;
+
+        if (mac->opmode == NL80211_IFTYPE_ADHOC) {
+                return;
+        } else {
+                undecorated_smoothed_pwdb =
+                    rtlpriv->dm.undecorated_smoothed_pwdb;
+        }
+
+        if (pstats->b_packet_toself || pstats->b_packet_beacon) {
+                if (undecorated_smoothed_pwdb < 0)
+                        undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
+
+                if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
+                        undecorated_smoothed_pwdb =
+                            (((undecorated_smoothed_pwdb) *
+                              (RX_SMOOTH_FACTOR - 1)) +
+                             (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
+
+                        undecorated_smoothed_pwdb = undecorated_smoothed_pwdb
+                            + 1;
+                } else {
+                        undecorated_smoothed_pwdb =
+                            (((undecorated_smoothed_pwdb) *
+                              (RX_SMOOTH_FACTOR - 1)) +
+                             (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
+                }
+
+                rtlpriv->dm.undecorated_smoothed_pwdb =
+                    undecorated_smoothed_pwdb;
+                _rtl92ce_update_rxsignalstatistics(hw, pstats);
+        }
+}
+
+static void _rtl92ce_process_ui_link_quality(struct ieee80211_hw *hw,
+                                             struct rtl_stats *pstats)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        u32 last_evm, n_spatialstream, tmpval;
+
+        if (pstats->signalquality != 0) {
+                if (pstats->b_packet_toself || pstats->b_packet_beacon) {
+
+                        if (rtlpriv->stats.ui_link_quality.total_num++ >=
+                            PHY_LINKQUALITY_SLID_WIN_MAX) {
+                                rtlpriv->stats.ui_link_quality.total_num =
+                                    PHY_LINKQUALITY_SLID_WIN_MAX;
+                                last_evm =
+                                    rtlpriv->stats.
+                                    ui_link_quality.elements[rtlpriv->
+                                                          stats.ui_link_quality.
+                                                          index];
+                                rtlpriv->stats.ui_link_quality.total_val -=
+                                    last_evm;
+                        }
+
+                        rtlpriv->stats.ui_link_quality.total_val +=
+                            pstats->signalquality;
+                        rtlpriv->stats.ui_link_quality.elements[rtlpriv->stats.
+                                                                ui_link_quality.
+                                                                index++] =
+                            pstats->signalquality;
+
+                        if (rtlpriv->stats.ui_link_quality.index >=
+                            PHY_LINKQUALITY_SLID_WIN_MAX)
+                                rtlpriv->stats.ui_link_quality.index = 0;
+
+                        tmpval = rtlpriv->stats.ui_link_quality.total_val /
+                            rtlpriv->stats.ui_link_quality.total_num;
+                        rtlpriv->stats.signal_quality = tmpval;
+
+                        rtlpriv->stats.last_sigstrength_inpercent = tmpval;
+
+                        for (n_spatialstream = 0; n_spatialstream < 2;
+                             n_spatialstream++) {
+                                if (pstats->
+                                    rx_mimo_signalquality[n_spatialstream] !=
+                                    -1) {
+                                        if (rtlpriv->stats.
+                                            rx_evm_percentage[n_spatialstream]
+                                            == 0) {
+                                                rtlpriv->stats.
+                                                   rx_evm_percentage
+                                                   [n_spatialstream] =
+                                                   pstats->rx_mimo_signalquality
+                                                   [n_spatialstream];
+                                        }
+
+                                        rtlpriv->stats.
+                                            rx_evm_percentage[n_spatialstream] =
+                                            ((rtlpriv->
+                                              stats.rx_evm_percentage
+                                              [n_spatialstream] *
+                                              (RX_SMOOTH_FACTOR - 1)) +
+                                             (pstats->
+                                              rx_mimo_signalquality
+                                              [n_spatialstream] * 1)) /
+                                            (RX_SMOOTH_FACTOR);
+                                }
+                        }
+                }
+        } else {
+                ;
+        }
+}
+
+static void _rtl92ce_process_phyinfo(struct ieee80211_hw *hw,
+                                     u8 *buffer,
+                                     struct rtl_stats *pcurrent_stats)
+{
+
+        if (!pcurrent_stats->b_packet_matchbssid &&
+            !pcurrent_stats->b_packet_beacon)
+                return;
+
+        _rtl92ce_process_ui_rssi(hw, pcurrent_stats);
+        _rtl92ce_process_pwdb(hw, pcurrent_stats);
+        _rtl92ce_process_ui_link_quality(hw, pcurrent_stats);
+}
+
+static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
+                                               struct sk_buff *skb,
+                                               struct rtl_stats *pstats,
+                                               struct rx_desc_92c *pdesc,
+                                               struct rx_fwinfo_92c *p_drvinfo)
+{
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
+
+        struct ieee80211_hdr *hdr;
+        u8 *tmp_buf;
+        u8 *praddr;
+        u8 *psaddr;
+        u16 fc, type;
+        bool b_packet_matchbssid, b_packet_toself, b_packet_beacon;
+
+        tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
+
+        hdr = (struct ieee80211_hdr *)tmp_buf;
+        fc = le16_to_cpu(hdr->frame_control);
+        type = WLAN_FC_GET_TYPE(fc);
+        praddr = hdr->addr1;
+        psaddr = hdr->addr2;
+
+        b_packet_matchbssid =
+            ((IEEE80211_FTYPE_CTL != type) &&
+             (!compare_ether_addr(mac->bssid,
+                                  (fc & IEEE80211_FCTL_TODS) ?
+                                  hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ?
+                                  hdr->addr2 : hdr->addr3)) &&
+             (!pstats->b_hwerror) && (!pstats->b_crc) && (!pstats->b_icv));
+
+        b_packet_toself = b_packet_matchbssid &&
+            (!compare_ether_addr(praddr, rtlefuse->dev_addr));
+
+        if (ieee80211_is_beacon(fc))
+                b_packet_beacon = true;
+
+        _rtl92ce_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
+                                   b_packet_matchbssid, b_packet_toself,
+                                   b_packet_beacon);
+
+        _rtl92ce_process_phyinfo(hw, tmp_buf, pstats);
+}
+
+bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
+                           struct rtl_stats *stats,
+                           struct ieee80211_rx_status *rx_status,
+                           u8 *p_desc, struct sk_buff *skb)
+{
+        struct rx_fwinfo_92c *p_drvinfo;
+        struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
+
+        u32 phystatus = GET_RX_DESC_PHYST(pdesc);
+        stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
+        stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
+            RX_DRV_INFO_SIZE_UNIT;
+        stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
+        stats->b_icv = (u16) GET_RX_DESC_ICV(pdesc);
+        stats->b_crc = (u16) GET_RX_DESC_CRC32(pdesc);
+        stats->b_hwerror = (stats->b_crc | stats->b_icv);
+        stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
+        stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
+        stats->b_shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
+        stats->b_isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
+        stats->b_isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
+                                   && (GET_RX_DESC_FAGGR(pdesc) == 1));
+        stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
+        stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
+
+        rx_status->freq = hw->conf.channel->center_freq;
+        rx_status->band = hw->conf.channel->band;
+
+        if (GET_RX_DESC_CRC32(pdesc))
+                rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
+
+        if (!GET_RX_DESC_SWDEC(pdesc))
+                rx_status->flag |= RX_FLAG_DECRYPTED;
+
+        if (GET_RX_DESC_BW(pdesc))
+                rx_status->flag |= RX_FLAG_40MHZ;
+
+        if (GET_RX_DESC_RXHT(pdesc))
+                rx_status->flag |= RX_FLAG_HT;
+
+        rx_status->flag |= RX_FLAG_TSFT;
+
+        if (stats->decrypted)
+                rx_status->flag |= RX_FLAG_DECRYPTED;
+
+        rx_status->rate_idx = _rtl92ce_rate_mapping((bool)
+                                                    GET_RX_DESC_RXHT(pdesc),
+                                                    (u8)
+                                                    GET_RX_DESC_RXMCS(pdesc),
+                                                    (bool)
+                                                    GET_RX_DESC_PAGGR(pdesc));
+
+        rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
+        if (phystatus == true) {
+                p_drvinfo = (struct rx_fwinfo_92c *)(skb->data +
+                                                     stats->rx_bufshift);
+
+                _rtl92ce_translate_rx_signal_stuff(hw,
+                                                   skb, stats, pdesc,
+                                                   p_drvinfo);
+        }
+
+        /*rx_status->qual = stats->signal; */
+        rx_status->signal = stats->rssi + 10;
+        /*rx_status->noise = -stats->noise; */
+
+        return true;
+}
+
+void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
+                          struct ieee80211_hdr *hdr, u8 *pdesc_tx,
+                          struct ieee80211_tx_info *info, struct sk_buff *skb,
+                          unsigned int queue_index)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
+        bool b_defaultadapter = true;
+
+        struct ieee80211_sta *sta = ieee80211_find_sta(mac->vif, mac->bssid);
+
+        u8 *pdesc = (u8 *) pdesc_tx;
+        struct rtl_tcb_desc tcb_desc;
+        u8 *qc = ieee80211_get_qos_ctl(hdr);
+        u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
+        u16 seq_number;
+        u16 fc = le16_to_cpu(hdr->frame_control);
+        u8 rate_flag = info->control.rates[0].flags;
+
+        enum rtl_desc_qsel fw_qsel =
+            _rtl92ce_map_hwqueue_to_fwqueue(le16_to_cpu(hdr->frame_control),
+                                            queue_index);
+
+        bool b_firstseg = ((hdr->seq_ctrl &
+                            cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
+
+        bool b_lastseg = ((hdr->frame_control &
+                           cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
+
+        dma_addr_t mapping = pci_map_single(rtlpci->pdev,
+                                            skb->data, skb->len,
+                                            PCI_DMA_TODEVICE);
+
+        seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
+
+        rtl_get_tcb_desc(hw, info, skb, &tcb_desc);
+
+        CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92c));
+
+        if (b_firstseg) {
+                SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
+
+                SET_TX_DESC_TX_RATE(pdesc, tcb_desc.hw_rate);
+
+                if (tcb_desc.use_shortgi || tcb_desc.use_shortpreamble)
+                        SET_TX_DESC_DATA_SHORTGI(pdesc, 1);
+
+                if (mac->tids[tid].agg.agg_state == RTL_AGG_ON &&
+                    info->flags & IEEE80211_TX_CTL_AMPDU) {
+                        SET_TX_DESC_AGG_BREAK(pdesc, 1);
+                        SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
+                }
+                SET_TX_DESC_SEQ(pdesc, seq_number);
+
+                SET_TX_DESC_RTS_ENABLE(pdesc, ((tcb_desc.b_rts_enable &&
+                                                !tcb_desc.
+                                                b_cts_enable) ? 1 : 0));
+                SET_TX_DESC_HW_RTS_ENABLE(pdesc,
+                                          ((tcb_desc.b_rts_enable
+                                            || tcb_desc.b_cts_enable) ? 1 : 0));
+                SET_TX_DESC_CTS2SELF(pdesc, ((tcb_desc.b_cts_enable) ? 1 : 0));
+                SET_TX_DESC_RTS_STBC(pdesc, ((tcb_desc.b_rts_stbc) ? 1 : 0));
+
+                SET_TX_DESC_RTS_RATE(pdesc, tcb_desc.rts_rate);
+                SET_TX_DESC_RTS_BW(pdesc, 0);
+                SET_TX_DESC_RTS_SC(pdesc, tcb_desc.rts_sc);
+                SET_TX_DESC_RTS_SHORT(pdesc,
+                                      ((tcb_desc.rts_rate <= DESC92C_RATE54M) ?
+                                      (tcb_desc.b_rts_use_shortpreamble ? 1 : 0)
+                                      : (tcb_desc.b_rts_use_shortgi ? 1 : 0)));
+
+                if (mac->bw_40) {
+                        if (tcb_desc.b_packet_bw) {
+                                SET_TX_DESC_DATA_BW(pdesc, 1);
+                                SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
+                        } else {
+                                SET_TX_DESC_DATA_BW(pdesc, 0);
+
+                                if (rate_flag & IEEE80211_TX_RC_DUP_DATA) {
+                                        SET_TX_DESC_TX_SUB_CARRIER(pdesc,
+                                                        mac->cur_40_prime_sc);
+                                }
+                        }
+                } else {
+                        SET_TX_DESC_DATA_BW(pdesc, 0);
+                        SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
+                }
+
+                SET_TX_DESC_LINIP(pdesc, 0);
+                SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb->len);
+
+                if (sta) {
+                        u8 ampdu_density = sta->ht_cap.ampdu_density;
+                        SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
+                }
+
+                if (info->control.hw_key) {
+                        struct ieee80211_key_conf *keyconf =
+                            info->control.hw_key;
+
+                        switch (keyconf->cipher) {
+                        case WLAN_CIPHER_SUITE_WEP40:
+                        case WLAN_CIPHER_SUITE_WEP104:
+                        case WLAN_CIPHER_SUITE_TKIP:
+                                SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
+                                break;
+                        case WLAN_CIPHER_SUITE_CCMP:
+                                SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
+                                break;
+                        default:
+                                SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
+                                break;
+
+                        }
+                }
+
+                SET_TX_DESC_PKT_ID(pdesc, 0);
+                SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
+
+                SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
+                SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
+                SET_TX_DESC_DISABLE_FB(pdesc, 0);
+                SET_TX_DESC_USE_RATE(pdesc, tcb_desc.use_driver_rate ? 1 : 0);
+
+                if (ieee80211_is_data_qos(fc)) {
+                        if (mac->rdg_en) {
+                                RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
+                                         ("Enable RDG function.\n"));
+                                SET_TX_DESC_RDG_ENABLE(pdesc, 1);
+                                SET_TX_DESC_HTC(pdesc, 1);
+                        }
+                }
+        }
+
+        SET_TX_DESC_FIRST_SEG(pdesc, (b_firstseg ? 1 : 0));
+        SET_TX_DESC_LAST_SEG(pdesc, (b_lastseg ? 1 : 0));
+
+        SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) skb->len);
+
+        SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
+
+        if (rtlpriv->dm.b_useramask) {
+                SET_TX_DESC_RATE_ID(pdesc, tcb_desc.ratr_index);
+                SET_TX_DESC_MACID(pdesc, tcb_desc.mac_id);
+        } else {
+                SET_TX_DESC_RATE_ID(pdesc, 0xC + tcb_desc.ratr_index);
+                SET_TX_DESC_MACID(pdesc, tcb_desc.ratr_index);
+        }
+
+        if ((!ieee80211_is_data_qos(fc)) && ppsc->b_leisure_ps &&
+            ppsc->b_fwctrl_lps) {
+                SET_TX_DESC_HWSEQ_EN(pdesc, 1);
+                SET_TX_DESC_PKT_ID(pdesc, 8);
+
+                if (!b_defaultadapter)
+                        SET_TX_DESC_QOS(pdesc, 1);
+        }
+
+        SET_TX_DESC_MORE_FRAG(pdesc, (b_lastseg ? 0 : 1));
+
+        if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
+            is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
+                SET_TX_DESC_BMC(pdesc, 1);
+        }
+
+        RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, ("\n"));
+}
+
+void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
+                             u8 *pdesc, bool b_firstseg,
+                             bool b_lastseg, struct sk_buff *skb)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
+        u8 fw_queue = QSLT_BEACON;
+
+        dma_addr_t mapping = pci_map_single(rtlpci->pdev,
+                                            skb->data, skb->len,
+                                            PCI_DMA_TODEVICE);
+
+        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
+        u16 fc = le16_to_cpu(hdr->frame_control);
+
+        CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
+
+        if (b_firstseg)
+                SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
+
+        SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
+
+        SET_TX_DESC_SEQ(pdesc, 0);
+
+        SET_TX_DESC_LINIP(pdesc, 0);
+
+        SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
+
+        SET_TX_DESC_FIRST_SEG(pdesc, 1);
+        SET_TX_DESC_LAST_SEG(pdesc, 1);
+
+        SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) (skb->len));
+
+        SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
+
+        SET_TX_DESC_RATE_ID(pdesc, 7);
+        SET_TX_DESC_MACID(pdesc, 0);
+
+        SET_TX_DESC_OWN(pdesc, 1);
+
+        SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
+
+        SET_TX_DESC_FIRST_SEG(pdesc, 1);
+        SET_TX_DESC_LAST_SEG(pdesc, 1);
+
+        SET_TX_DESC_OFFSET(pdesc, 0x20);
+
+        SET_TX_DESC_USE_RATE(pdesc, 1);
+
+        if (!ieee80211_is_data_qos(fc)) {
+                SET_TX_DESC_HWSEQ_EN(pdesc, 1);
+                SET_TX_DESC_PKT_ID(pdesc, 8);
+        }
+
+        RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
+                      "H2C Tx Cmd Content\n",
+                      pdesc, TX_DESC_SIZE);
+}
+
+void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val)
+{
+        if (istx == true) {
+                switch (desc_name) {
+                case HW_DESC_OWN:
+                        SET_TX_DESC_OWN(pdesc, 1);
+                        break;
+                case HW_DESC_TX_NEXTDESC_ADDR:
+                        SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *) val);
+                        break;
+                default:
+                        RT_ASSERT(false, ("ERR txdesc :%d"
+                                          " not process\n", desc_name));
+                        break;
+                }
+        } else {
+                switch (desc_name) {
+                case HW_DESC_RXOWN:
+                        SET_RX_DESC_OWN(pdesc, 1);
+                        break;
+                case HW_DESC_RXBUFF_ADDR:
+                        SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *) val);
+                        break;
+                case HW_DESC_RXPKT_LEN:
+                        SET_RX_DESC_PKT_LEN(pdesc, *(u32 *) val);
+                        break;
+                case HW_DESC_RXERO:
+                        SET_RX_DESC_EOR(pdesc, 1);
+                        break;
+                default:
+                        RT_ASSERT(false, ("ERR rxdesc :%d "
+                                          "not process\n", desc_name));
+                        break;
+                }
+        }
+}
+
+u32 rtl92ce_get_desc(u8 *p_desc, bool istx, u8 desc_name)
+{
+        u32 ret = 0;
+
+        if (istx == true) {
+                switch (desc_name) {
+                case HW_DESC_OWN:
+                        ret = GET_TX_DESC_OWN(p_desc);
+                        break;
+                case HW_DESC_TXBUFF_ADDR:
+                        ret = GET_TX_DESC_TX_BUFFER_ADDRESS(p_desc);
+                        break;
+                default:
+                        RT_ASSERT(false, ("ERR txdesc :%d "
+                                          "not process\n", desc_name));
+                        break;
+                }
+        } else {
+                struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
+                switch (desc_name) {
+                case HW_DESC_OWN:
+                        ret = GET_RX_DESC_OWN(pdesc);
+                        break;
+                case HW_DESC_RXPKT_LEN:
+                        ret = GET_RX_DESC_PKT_LEN(pdesc);
+                        break;
+                default:
+                        RT_ASSERT(false, ("ERR rxdesc :%d "
+                                          "not process\n", desc_name));
+                        break;
+                }
+        }
+        return ret;
+}
+
+void rtl92ce_tx_polling(struct ieee80211_hw *hw, unsigned int hw_queue)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+        if (hw_queue == BEACON_QUEUE) {
+                rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, BIT(4));
+        } else {
+                rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG,
+                               BIT(0) << (hw_queue));
+        }
+}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
new file mode 100644
index 000000000000..53d0e0a5af5c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
@@ -0,0 +1,714 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL92CE_TRX_H__
+#define __RTL92CE_TRX_H__
+
+#define TX_DESC_SIZE                            64
+#define TX_DESC_AGGR_SUBFRAME_SIZE              32
+
+#define RX_DESC_SIZE                            32
+#define RX_DRV_INFO_SIZE_UNIT                   8
+
+#define TX_DESC_NEXT_DESC_OFFSET                40
+#define USB_HWDESC_HEADER_LEN                   32
+#define CRCLENGTH                               4
+
+#define SET_TX_DESC_PKT_SIZE(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val)
+#define SET_TX_DESC_OFFSET(__pdesc, __val)              \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val)
+#define SET_TX_DESC_BMC(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val)
+#define SET_TX_DESC_HTC(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val)
+#define SET_TX_DESC_LAST_SEG(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val)
+#define SET_TX_DESC_FIRST_SEG(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val)
+#define SET_TX_DESC_LINIP(__pdesc, __val)               \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val)
+#define SET_TX_DESC_NO_ACM(__pdesc, __val)              \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val)
+#define SET_TX_DESC_GF(__pdesc, __val)                  \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
+#define SET_TX_DESC_OWN(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
+
+#define GET_TX_DESC_PKT_SIZE(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc, 0, 16)
+#define GET_TX_DESC_OFFSET(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc, 16, 8)
+#define GET_TX_DESC_BMC(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 24, 1)
+#define GET_TX_DESC_HTC(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 25, 1)
+#define GET_TX_DESC_LAST_SEG(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc, 26, 1)
+#define GET_TX_DESC_FIRST_SEG(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc, 27, 1)
+#define GET_TX_DESC_LINIP(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc, 28, 1)
+#define GET_TX_DESC_NO_ACM(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc, 29, 1)
+#define GET_TX_DESC_GF(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc, 30, 1)
+#define GET_TX_DESC_OWN(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 31, 1)
+
+#define SET_TX_DESC_MACID(__pdesc, __val)               \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 5, __val)
+#define SET_TX_DESC_AGG_BREAK(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 5, 1, __val)
+#define SET_TX_DESC_BK(__pdesc, __val)                  \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 6, 1, __val)
+#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 7, 1, __val)
+#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val)
+#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val)
+#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val)        \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val)
+#define SET_TX_DESC_PIFS(__pdesc, __val)                \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val)
+#define SET_TX_DESC_RATE_ID(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 4, __val)
+#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 20, 1, __val)
+#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val)
+#define SET_TX_DESC_SEC_TYPE(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val)
+#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 8, __val)
+
+#define GET_TX_DESC_MACID(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
+#define GET_TX_DESC_AGG_ENABLE(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+4, 5, 1)
+#define GET_TX_DESC_AGG_BREAK(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+4, 6, 1)
+#define GET_TX_DESC_RDG_ENABLE(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+4, 7, 1)
+#define GET_TX_DESC_QUEUE_SEL(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+4, 8, 5)
+#define GET_TX_DESC_RDG_NAV_EXT(__pdesc)                \
+        LE_BITS_TO_4BYTE(__pdesc+4, 13, 1)
+#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc)               \
+        LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
+#define GET_TX_DESC_PIFS(__pdesc)                       \
+        LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
+#define GET_TX_DESC_RATE_ID(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
+#define GET_TX_DESC_NAV_USE_HDR(__pdesc)                \
+        LE_BITS_TO_4BYTE(__pdesc+4, 20, 1)
+#define GET_TX_DESC_EN_DESC_ID(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+4, 21, 1)
+#define GET_TX_DESC_SEC_TYPE(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+4, 22, 2)
+#define GET_TX_DESC_PKT_OFFSET(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+4, 24, 8)
+
+#define SET_TX_DESC_RTS_RC(__pdesc, __val)              \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 6, __val)
+#define SET_TX_DESC_DATA_RC(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 6, 6, __val)
+#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val)
+#define SET_TX_DESC_MORE_FRAG(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val)
+#define SET_TX_DESC_RAW(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val)
+#define SET_TX_DESC_CCX(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val)
+#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val)
+#define SET_TX_DESC_ANTSEL_A(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 1, __val)
+#define SET_TX_DESC_ANTSEL_B(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 25, 1, __val)
+#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 26, 2, __val)
+#define SET_TX_DESC_TX_ANTL(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 28, 2, __val)
+#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+8, 30, 2, __val)
+
+#define GET_TX_DESC_RTS_RC(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+8, 0, 6)
+#define GET_TX_DESC_DATA_RC(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+8, 6, 6)
+#define GET_TX_DESC_BAR_RTY_TH(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+8, 14, 2)
+#define GET_TX_DESC_MORE_FRAG(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+8, 17, 1)
+#define GET_TX_DESC_RAW(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+8, 18, 1)
+#define GET_TX_DESC_CCX(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+8, 19, 1)
+#define GET_TX_DESC_AMPDU_DENSITY(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+8, 20, 3)
+#define GET_TX_DESC_ANTSEL_A(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+8, 24, 1)
+#define GET_TX_DESC_ANTSEL_B(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+8, 25, 1)
+#define GET_TX_DESC_TX_ANT_CCK(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+8, 26, 2)
+#define GET_TX_DESC_TX_ANTL(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+8, 28, 2)
+#define GET_TX_DESC_TX_ANT_HT(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+8, 30, 2)
+
+#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val)      \
+        SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 8, __val)
+#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 8, __val)
+#define SET_TX_DESC_SEQ(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 12, __val)
+#define SET_TX_DESC_PKT_ID(__pdesc, __val)              \
+        SET_BITS_TO_LE_4BYTE(__pdesc+12, 28, 4, __val)
+
+#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc)             \
+        LE_BITS_TO_4BYTE(__pdesc+12, 0, 8)
+#define GET_TX_DESC_TAIL_PAGE(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+12, 8, 8)
+#define GET_TX_DESC_SEQ(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+12, 16, 12)
+#define GET_TX_DESC_PKT_ID(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+12, 28, 4)
+
+#define SET_TX_DESC_RTS_RATE(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val)
+#define SET_TX_DESC_AP_DCFE(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 5, 1, __val)
+#define SET_TX_DESC_QOS(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 6, 1, __val)
+#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val)
+#define SET_TX_DESC_USE_RATE(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 1, __val)
+#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val)      \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 9, 1, __val)
+#define SET_TX_DESC_DISABLE_FB(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 10, 1, __val)
+#define SET_TX_DESC_CTS2SELF(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 11, 1, __val)
+#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 12, 1, __val)
+#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 1, __val)
+#define SET_TX_DESC_PORT_ID(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 14, 1, __val)
+#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 1, __val)
+#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 19, 1, __val)
+#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val)      \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 20, 2, __val)
+#define SET_TX_DESC_TX_STBC(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 22, 2, __val)
+#define SET_TX_DESC_DATA_SHORT(__pdesc, __val)          \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 1, __val)
+#define SET_TX_DESC_DATA_BW(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 25, 1, __val)
+#define SET_TX_DESC_RTS_SHORT(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 26, 1, __val)
+#define SET_TX_DESC_RTS_BW(__pdesc, __val)              \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 27, 1, __val)
+#define SET_TX_DESC_RTS_SC(__pdesc, __val)              \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 28, 2, __val)
+#define SET_TX_DESC_RTS_STBC(__pdesc, __val)            \
+        SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val)
+
+#define GET_TX_DESC_RTS_RATE(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+16, 0, 5)
+#define GET_TX_DESC_AP_DCFE(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+16, 5, 1)
+#define GET_TX_DESC_QOS(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+16, 6, 1)
+#define GET_TX_DESC_HWSEQ_EN(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+16, 7, 1)
+#define GET_TX_DESC_USE_RATE(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+16, 8, 1)
+#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc)             \
+        LE_BITS_TO_4BYTE(__pdesc+16, 9, 1)
+#define GET_TX_DESC_DISABLE_FB(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+16, 10, 1)
+#define GET_TX_DESC_CTS2SELF(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+16, 11, 1)
+#define GET_TX_DESC_RTS_ENABLE(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+16, 12, 1)
+#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+16, 13, 1)
+#define GET_TX_DESC_PORT_ID(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+16, 14, 1)
+#define GET_TX_DESC_WAIT_DCTS(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+16, 18, 1)
+#define GET_TX_DESC_CTS2AP_EN(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+16, 19, 1)
+#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc)             \
+        LE_BITS_TO_4BYTE(__pdesc+16, 20, 2)
+#define GET_TX_DESC_TX_STBC(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+16, 22, 2)
+#define GET_TX_DESC_DATA_SHORT(__pdesc)                 \
+        LE_BITS_TO_4BYTE(__pdesc+16, 24, 1)
+#define GET_TX_DESC_DATA_BW(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+16, 25, 1)
+#define GET_TX_DESC_RTS_SHORT(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+16, 26, 1)
+#define GET_TX_DESC_RTS_BW(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+16, 27, 1)
+#define GET_TX_DESC_RTS_SC(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+16, 28, 2)
+#define GET_TX_DESC_RTS_STBC(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+16, 30, 2)
+
+#define SET_TX_DESC_TX_RATE(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 6, __val)
+#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val)        \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 6, 1, __val)
+#define SET_TX_DESC_CCX_TAG(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val)
+#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val)  \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 5, __val)
+#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val)   \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val)
+#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val)  \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 17, 1, __val)
+#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val)    \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 18, 6, __val)
+#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 8, __val)
+
+#define GET_TX_DESC_TX_RATE(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+20, 0, 6)
+#define GET_TX_DESC_DATA_SHORTGI(__pdesc)               \
+        LE_BITS_TO_4BYTE(__pdesc+20, 6, 1)
+#define GET_TX_DESC_CCX_TAG(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+20, 7, 1)
+#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc)         \
+        LE_BITS_TO_4BYTE(__pdesc+20, 8, 5)
+#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc)          \
+        LE_BITS_TO_4BYTE(__pdesc+20, 13, 4)
+#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc)         \
+        LE_BITS_TO_4BYTE(__pdesc+20, 17, 1)
+#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc)           \
+        LE_BITS_TO_4BYTE(__pdesc+20, 18, 6)
+#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+20, 24, 8)
+
+#define SET_TX_DESC_TXAGC_A(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 5, __val)
+#define SET_TX_DESC_TXAGC_B(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 5, 5, __val)
+#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val)         \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 10, 1, __val)
+#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val)         \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 11, 5, __val)
+#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 4, __val)
+#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 20, 4, __val)
+#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 24, 4, __val)
+#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val)    \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 28, 4, __val)
+
+#define GET_TX_DESC_TXAGC_A(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+24, 0, 5)
+#define GET_TX_DESC_TXAGC_B(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc+24, 5, 5)
+#define GET_TX_DESC_USE_MAX_LEN(__pdesc)                \
+        LE_BITS_TO_4BYTE(__pdesc+24, 10, 1)
+#define GET_TX_DESC_MAX_AGG_NUM(__pdesc)                \
+        LE_BITS_TO_4BYTE(__pdesc+24, 11, 5)
+#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+24, 16, 4)
+#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+24, 20, 4)
+#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+24, 24, 4)
+#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc)           \
+        LE_BITS_TO_4BYTE(__pdesc+24, 28, 4)
+
+#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val)      \
+        SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val)
+#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+28, 16, 4, __val)
+#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+28, 20, 4, __val)
+#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val)       \
+        SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 4, __val)
+#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val)   \
+        SET_BITS_TO_LE_4BYTE(__pdesc+28, 28, 4, __val)
+
+#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc)             \
+        LE_BITS_TO_4BYTE(__pdesc+28, 0, 16)
+#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+28, 16, 4)
+#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+28, 20, 4)
+#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc+28, 24, 4)
+#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc)          \
+        LE_BITS_TO_4BYTE(__pdesc+28, 28, 4)
+
+#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val)   \
+        SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 32, __val)
+#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
+        SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val)
+
+#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc)          \
+        LE_BITS_TO_4BYTE(__pdesc+32, 0, 32)
+#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc)        \
+        LE_BITS_TO_4BYTE(__pdesc+36, 0, 32)
+
+#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val)   \
+        SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val)
+#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
+        SET_BITS_TO_LE_4BYTE(__pdesc+44, 0, 32, __val)
+
+#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc)          \
+        LE_BITS_TO_4BYTE(__pdesc+40, 0, 32)
+#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc)        \
+        LE_BITS_TO_4BYTE(__pdesc+44, 0, 32)
+
+#define GET_RX_DESC_PKT_LEN(__pdesc)                    \
+        LE_BITS_TO_4BYTE(__pdesc, 0, 14)
+#define GET_RX_DESC_CRC32(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc, 14, 1)
+#define GET_RX_DESC_ICV(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 15, 1)
+#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc)              \
+        LE_BITS_TO_4BYTE(__pdesc, 16, 4)
+#define GET_RX_DESC_SECURITY(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc, 20, 3)
+#define GET_RX_DESC_QOS(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 23, 1)
+#define GET_RX_DESC_SHIFT(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc, 24, 2)
+#define GET_RX_DESC_PHYST(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc, 26, 1)
+#define GET_RX_DESC_SWDEC(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc, 27, 1)
+#define GET_RX_DESC_LS(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc, 28, 1)
+#define GET_RX_DESC_FS(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc, 29, 1)
+#define GET_RX_DESC_EOR(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 30, 1)
+#define GET_RX_DESC_OWN(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc, 31, 1)
+
+#define SET_RX_DESC_PKT_LEN(__pdesc, __val)             \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val)
+#define SET_RX_DESC_EOR(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val)
+#define SET_RX_DESC_OWN(__pdesc, __val)                 \
+        SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val)
+
+#define GET_RX_DESC_MACID(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc+4, 0, 5)
+#define GET_RX_DESC_TID(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+4, 5, 4)
+#define GET_RX_DESC_HWRSVD(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+4, 9, 5)
+#define GET_RX_DESC_PAGGR(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc+4, 14, 1)
+#define GET_RX_DESC_FAGGR(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc+4, 15, 1)
+#define GET_RX_DESC_A1_FIT(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+4, 16, 4)
+#define GET_RX_DESC_A2_FIT(__pdesc)                     \
+        LE_BITS_TO_4BYTE(__pdesc+4, 20, 4)
+#define GET_RX_DESC_PAM(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+4, 24, 1)
+#define GET_RX_DESC_PWR(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+4, 25, 1)
+#define GET_RX_DESC_MD(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc+4, 26, 1)
+#define GET_RX_DESC_MF(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc+4, 27, 1)
+#define GET_RX_DESC_TYPE(__pdesc)                       \
+        LE_BITS_TO_4BYTE(__pdesc+4, 28, 2)
+#define GET_RX_DESC_MC(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc+4, 30, 1)
+#define GET_RX_DESC_BC(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc+4, 31, 1)
+#define GET_RX_DESC_SEQ(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+8, 0, 12)
+#define GET_RX_DESC_FRAG(__pdesc)                       \
+        LE_BITS_TO_4BYTE(__pdesc+8, 12, 4)
+#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc)               \
+        LE_BITS_TO_4BYTE(__pdesc+8, 16, 14)
+#define GET_RX_DESC_NEXT_IND(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+8, 30, 1)
+#define GET_RX_DESC_RSVD(__pdesc)                       \
+        LE_BITS_TO_4BYTE(__pdesc+8, 31, 1)
+
+#define GET_RX_DESC_RXMCS(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc+12, 0, 6)
+#define GET_RX_DESC_RXHT(__pdesc)                       \
+        LE_BITS_TO_4BYTE(__pdesc+12, 6, 1)
+#define GET_RX_DESC_SPLCP(__pdesc)                      \
+        LE_BITS_TO_4BYTE(__pdesc+12, 8, 1)
+#define GET_RX_DESC_BW(__pdesc)                         \
+        LE_BITS_TO_4BYTE(__pdesc+12, 9, 1)
+#define GET_RX_DESC_HTC(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+12, 10, 1)
+#define GET_RX_DESC_HWPC_ERR(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+12, 14, 1)
+#define GET_RX_DESC_HWPC_IND(__pdesc)                   \
+        LE_BITS_TO_4BYTE(__pdesc+12, 15, 1)
+#define GET_RX_DESC_IV0(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+12, 16, 16)
+
+#define GET_RX_DESC_IV1(__pdesc)                        \
+        LE_BITS_TO_4BYTE(__pdesc+16, 0, 32)
+#define GET_RX_DESC_TSFL(__pdesc)                       \
+        LE_BITS_TO_4BYTE(__pdesc+20, 0, 32)
+
+#define GET_RX_DESC_BUFF_ADDR(__pdesc)                  \
+        LE_BITS_TO_4BYTE(__pdesc+24, 0, 32)
+#define GET_RX_DESC_BUFF_ADDR64(__pdesc)                \
+        LE_BITS_TO_4BYTE(__pdesc+28, 0, 32)
+
+#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val)           \
+        SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val)
+#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val)         \
+        SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val)
+
+#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)       \
+do {                                                    \
+        if (_size > TX_DESC_NEXT_DESC_OFFSET)           \
+                memset((void *)__pdesc, 0, TX_DESC_NEXT_DESC_OFFSET);   \
+        else                                            \
+                memset((void *)__pdesc, 0, _size);      \
+} while (0);
+
+#define RX_HAL_IS_CCK_RATE(_pdesc)\
+        (_pdesc->rxmcs == DESC92C_RATE1M ||             \
+         _pdesc->rxmcs == DESC92C_RATE2M ||             \
+         _pdesc->rxmcs == DESC92C_RATE5_5M ||           \
+         _pdesc->rxmcs == DESC92C_RATE11M)
+
+struct rx_fwinfo_92c {
+        u8 gain_trsw[4];
+        u8 pwdb_all;
+        u8 cfosho[4];
+        u8 cfotail[4];
+        char rxevm[2];
+        char rxsnr[4];
+        u8 pdsnr[2];
+        u8 csi_current[2];
+        u8 csi_target[2];
+        u8 sigevm;
+        u8 max_ex_pwr;
+        u8 ex_intf_flag:1;
+        u8 sgi_en:1;
+        u8 rxsc:2;
+        u8 reserve:4;
+} __packed;
+
+struct tx_desc_92c {
+        u32 pktsize:16;
+        u32 offset:8;
+        u32 bmc:1;
+        u32 htc:1;
+        u32 lastseg:1;
+        u32 firstseg:1;
+        u32 linip:1;
+        u32 noacm:1;
+        u32 gf:1;
+        u32 own:1;
+
+        u32 macid:5;
+        u32 agg_en:1;
+        u32 bk:1;
+        u32 rdg_en:1;
+        u32 queuesel:5;
+        u32 rd_nav_ext:1;
+        u32 lsig_txop_en:1;
+        u32 pifs:1;
+        u32 rateid:4;
+        u32 nav_usehdr:1;
+        u32 en_descid:1;
+        u32 sectype:2;
+        u32 pktoffset:8;
+
+        u32 rts_rc:6;
+        u32 data_rc:6;
+        u32 rsvd0:2;
+        u32 bar_retryht:2;
+        u32 rsvd1:1;
+        u32 morefrag:1;
+        u32 raw:1;
+        u32 ccx:1;
+        u32 ampdudensity:3;
+        u32 rsvd2:1;
+        u32 ant_sela:1;
+        u32 ant_selb:1;
+        u32 txant_cck:2;
+        u32 txant_l:2;
+        u32 txant_ht:2;
+
+        u32 nextheadpage:8;
+        u32 tailpage:8;
+        u32 seq:12;
+        u32 pktid:4;
+
+        u32 rtsrate:5;
+        u32 apdcfe:1;
+        u32 qos:1;
+        u32 hwseq_enable:1;
+        u32 userrate:1;
+        u32 dis_rtsfb:1;
+        u32 dis_datafb:1;
+        u32 cts2self:1;
+        u32 rts_en:1;
+        u32 hwrts_en:1;
+        u32 portid:1;
+        u32 rsvd3:3;
+        u32 waitdcts:1;
+        u32 cts2ap_en:1;
+        u32 txsc:2;
+        u32 stbc:2;
+        u32 txshort:1;
+        u32 txbw:1;
+        u32 rtsshort:1;
+        u32 rtsbw:1;
+        u32 rtssc:2;
+        u32 rtsstbc:2;
+
+        u32 txrate:6;
+        u32 shortgi:1;
+        u32 ccxt:1;
+        u32 txrate_fb_lmt:5;
+        u32 rtsrate_fb_lmt:4;
+        u32 retrylmt_en:1;
+        u32 txretrylmt:6;
+        u32 usb_txaggnum:8;
+
+        u32 txagca:5;
+        u32 txagcb:5;
+        u32 usemaxlen:1;
+        u32 maxaggnum:5;
+        u32 mcsg1maxlen:4;
+        u32 mcsg2maxlen:4;
+        u32 mcsg3maxlen:4;
+        u32 mcs7sgimaxlen:4;
+
+        u32 txbuffersize:16;
+        u32 mcsg4maxlen:4;
+        u32 mcsg5maxlen:4;
+        u32 mcsg6maxlen:4;
+        u32 mcsg15sgimaxlen:4;
+
+        u32 txbuffaddr;
+        u32 txbufferaddr64;
+        u32 nextdescaddress;
+        u32 nextdescaddress64;
+
+        u32 reserve_pass_pcie_mm_limit[4];
+} __packed;
+
+struct rx_desc_92c {
+        u32 length:14;
+        u32 crc32:1;
+        u32 icverror:1;
+        u32 drv_infosize:4;
+        u32 security:3;
+        u32 qos:1;
+        u32 shift:2;
+        u32 phystatus:1;
+        u32 swdec:1;
+        u32 lastseg:1;
+        u32 firstseg:1;
+        u32 eor:1;
+        u32 own:1;
+
+        u32 macid:5;
+        u32 tid:4;
+        u32 hwrsvd:5;
+        u32 paggr:1;
+        u32 faggr:1;
+        u32 a1_fit:4;
+        u32 a2_fit:4;
+        u32 pam:1;
+        u32 pwr:1;
+        u32 moredata:1;
+        u32 morefrag:1;
+        u32 type:2;
+        u32 mc:1;
+        u32 bc:1;
+
+        u32 seq:12;
+        u32 frag:4;
+        u32 nextpktlen:14;
+        u32 nextind:1;
+        u32 rsvd:1;
+
+        u32 rxmcs:6;
+        u32 rxht:1;
+        u32 amsdu:1;
+        u32 splcp:1;
+        u32 bandwidth:1;
+        u32 htc:1;
+        u32 tcpchk_rpt:1;
+        u32 ipcchk_rpt:1;
+        u32 tcpchk_valid:1;
+        u32 hwpcerr:1;
+        u32 hwpcind:1;
+        u32 iv0:16;
+
+        u32 iv1;
+
+        u32 tsfl;
+
+        u32 bufferaddress;
+        u32 bufferaddress64;
+
+} __packed;
+
+void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
+                          struct ieee80211_hdr *hdr,
+                          u8 *pdesc, struct ieee80211_tx_info *info,
+                          struct sk_buff *skb, unsigned int qsel);
+bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
+                           struct rtl_stats *stats,
+                           struct ieee80211_rx_status *rx_status,
+                           u8 *pdesc, struct sk_buff *skb);
+void rtl92ce_set_desc(u8 *pdesc, bool istx, u8 desc_name, u8 *val);
+u32 rtl92ce_get_desc(u8 *pdesc, bool istx, u8 desc_name);
+void rtl92ce_tx_polling(struct ieee80211_hw *hw, unsigned int hw_queue);
+void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
+                             bool b_firstseg, bool b_lastseg,
+                             struct sk_buff *skb);
+#endif
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
new file mode 100644
index 000000000000..d44d79613d2d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -0,0 +1,1532 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2009-2010  Realtek Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called LICENSE.
+ *
+ * Contact Information:
+ * wlanfae <wlanfae@realtek.com>
+ * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
+ * Hsinchu 300, Taiwan.
+ *
+ * Larry Finger <Larry.Finger@lwfinger.net>
+ *
+ *****************************************************************************/
+
+#ifndef __RTL_WIFI_H__
+#define __RTL_WIFI_H__
+
+#include <linux/sched.h>
+#include <linux/firmware.h>
+#include <linux/version.h>
+#include <linux/etherdevice.h>
+#include <net/mac80211.h>
+#include "debug.h"
+
+#define RF_CHANGE_BY_INIT                       0
+#define RF_CHANGE_BY_IPS                        BIT(28)
+#define RF_CHANGE_BY_PS                         BIT(29)
+#define RF_CHANGE_BY_HW                         BIT(30)
+#define RF_CHANGE_BY_SW                         BIT(31)
+
+#define IQK_ADDA_REG_NUM                        16
+#define IQK_MAC_REG_NUM                         4
+
+#define MAX_KEY_LEN                             61
+#define KEY_BUF_SIZE                            5
+
+/* QoS related. */
+/*aci: 0x00     Best Effort*/
+/*aci: 0x01     Background*/
+/*aci: 0x10     Video*/
+/*aci: 0x11     Voice*/
+/*Max: define total number.*/
+#define AC0_BE                                  0
+#define AC1_BK                                  1
+#define AC2_VI                                  2
+#define AC3_VO                                  3
+#define AC_MAX                                  4
+#define QOS_QUEUE_NUM                           4
+#define RTL_MAC80211_NUM_QUEUE                  5
+
+#define QBSS_LOAD_SIZE                          5
+#define MAX_WMMELE_LENGTH                       64
+
+/*slot time for 11g. */
+#define RTL_SLOT_TIME_9                         9
+#define RTL_SLOT_TIME_20                        20
+
+/*related with tcp/ip. */
+/*if_ehther.h*/
+#define ETH_P_PAE               0x888E  /*Port Access Entity (IEEE 802.1X) */
+#define ETH_P_IP                0x0800  /*Internet Protocol packet */
+#define ETH_P_ARP               0x0806  /*Address Resolution packet */
+#define SNAP_SIZE               6
+#define PROTOC_TYPE_SIZE        2
+
+/*related with 802.11 frame*/
+#define MAC80211_3ADDR_LEN                      24
+#define MAC80211_4ADDR_LEN                      30
+
+enum intf_type {
+        INTF_PCI = 0,
+        INTF_USB = 1,
+};
+
+enum radio_path {
+        RF90_PATH_A = 0,
+        RF90_PATH_B = 1,
+        RF90_PATH_C = 2,
+        RF90_PATH_D = 3,
+};
+
+enum rt_eeprom_type {
+        EEPROM_93C46,
+        EEPROM_93C56,
+        EEPROM_BOOT_EFUSE,
+};
+
+enum rtl_status {
+        RTL_STATUS_INTERFACE_START = 0,
+};
+
+enum hardware_type {
+        HARDWARE_TYPE_RTL8192E,
+        HARDWARE_TYPE_RTL8192U,
+        HARDWARE_TYPE_RTL8192SE,
+        HARDWARE_TYPE_RTL8192SU,
+        HARDWARE_TYPE_RTL8192CE,
+        HARDWARE_TYPE_RTL8192CU,
+        HARDWARE_TYPE_RTL8192DE,
+        HARDWARE_TYPE_RTL8192DU,
+
+        /*keep it last*/
+        HARDWARE_TYPE_NUM
+};
+
+enum scan_operation_backup_opt {
+        SCAN_OPT_BACKUP = 0,
+        SCAN_OPT_RESTORE,
+        SCAN_OPT_MAX
+};
+
+/*RF state.*/
+enum rf_pwrstate {
+        ERFON,
+        ERFSLEEP,
+        ERFOFF
+};
+
+struct bb_reg_def {
+        u32 rfintfs;
+        u32 rfintfi;
+        u32 rfintfo;
+        u32 rfintfe;
+        u32 rf3wire_offset;
+        u32 rflssi_select;
+        u32 rftxgain_stage;
+        u32 rfhssi_para1;
+        u32 rfhssi_para2;
+        u32 rfswitch_control;
+        u32 rfagc_control1;
+        u32 rfagc_control2;
+        u32 rfrxiq_imbalance;
+        u32 rfrx_afe;
+        u32 rftxiq_imbalance;
+        u32 rftx_afe;
+        u32 rflssi_readback;
+        u32 rflssi_readbackpi;
+};
+
+enum io_type {
+        IO_CMD_PAUSE_DM_BY_SCAN = 0,
+        IO_CMD_RESUME_DM_BY_SCAN = 1,
+};
+
+enum hw_variables {
+        HW_VAR_ETHER_ADDR,
+        HW_VAR_MULTICAST_REG,
+        HW_VAR_BASIC_RATE,
+        HW_VAR_BSSID,
+        HW_VAR_MEDIA_STATUS,
+        HW_VAR_SECURITY_CONF,
+        HW_VAR_BEACON_INTERVAL,
+        HW_VAR_ATIM_WINDOW,
+        HW_VAR_LISTEN_INTERVAL,
+        HW_VAR_CS_COUNTER,
+        HW_VAR_DEFAULTKEY0,
+        HW_VAR_DEFAULTKEY1,
+        HW_VAR_DEFAULTKEY2,
+        HW_VAR_DEFAULTKEY3,
+        HW_VAR_SIFS,
+        HW_VAR_DIFS,
+        HW_VAR_EIFS,
+        HW_VAR_SLOT_TIME,
+        HW_VAR_ACK_PREAMBLE,
+        HW_VAR_CW_CONFIG,
+        HW_VAR_CW_VALUES,
+        HW_VAR_RATE_FALLBACK_CONTROL,
+        HW_VAR_CONTENTION_WINDOW,
+        HW_VAR_RETRY_COUNT,
+        HW_VAR_TR_SWITCH,
+        HW_VAR_COMMAND,
+        HW_VAR_WPA_CONFIG,
+        HW_VAR_AMPDU_MIN_SPACE,
+        HW_VAR_SHORTGI_DENSITY,
+        HW_VAR_AMPDU_FACTOR,
+        HW_VAR_MCS_RATE_AVAILABLE,
+        HW_VAR_AC_PARAM,
+        HW_VAR_ACM_CTRL,
+        HW_VAR_DIS_Req_Qsize,
+        HW_VAR_CCX_CHNL_LOAD,
+        HW_VAR_CCX_NOISE_HISTOGRAM,
+        HW_VAR_CCX_CLM_NHM,
+        HW_VAR_TxOPLimit,
+        HW_VAR_TURBO_MODE,
+        HW_VAR_RF_STATE,
+        HW_VAR_RF_OFF_BY_HW,
+        HW_VAR_BUS_SPEED,
+        HW_VAR_SET_DEV_POWER,
+
+        HW_VAR_RCR,
+        HW_VAR_RATR_0,
+        HW_VAR_RRSR,
+        HW_VAR_CPU_RST,
+        HW_VAR_CECHK_BSSID,
+        HW_VAR_LBK_MODE,
+        HW_VAR_AES_11N_FIX,
+        HW_VAR_USB_RX_AGGR,
+        HW_VAR_USER_CONTROL_TURBO_MODE,
+        HW_VAR_RETRY_LIMIT,
+        HW_VAR_INIT_TX_RATE,
+        HW_VAR_TX_RATE_REG,
+        HW_VAR_EFUSE_USAGE,
+        HW_VAR_EFUSE_BYTES,
+        HW_VAR_AUTOLOAD_STATUS,
+        HW_VAR_RF_2R_DISABLE,
+        HW_VAR_SET_RPWM,
+        HW_VAR_H2C_FW_PWRMODE,
+        HW_VAR_H2C_FW_JOINBSSRPT,
+        HW_VAR_FW_PSMODE_STATUS,
+        HW_VAR_1X1_RECV_COMBINE,
+        HW_VAR_STOP_SEND_BEACON,
+        HW_VAR_TSF_TIMER,
+        HW_VAR_IO_CMD,
+
+        HW_VAR_RF_RECOVERY,
+        HW_VAR_H2C_FW_UPDATE_GTK,
+        HW_VAR_WF_MASK,
+        HW_VAR_WF_CRC,
+        HW_VAR_WF_IS_MAC_ADDR,
+        HW_VAR_H2C_FW_OFFLOAD,
+        HW_VAR_RESET_WFCRC,
+
+        HW_VAR_HANDLE_FW_C2H,
+        HW_VAR_DL_FW_RSVD_PAGE,
+        HW_VAR_AID,
+        HW_VAR_HW_SEQ_ENABLE,
+        HW_VAR_CORRECT_TSF,
+        HW_VAR_BCN_VALID,
+        HW_VAR_FWLPS_RF_ON,
+        HW_VAR_DUAL_TSF_RST,
+        HW_VAR_SWITCH_EPHY_WoWLAN,
+        HW_VAR_INT_MIGRATION,
+        HW_VAR_INT_AC,
+        HW_VAR_RF_TIMING,
+
+        HW_VAR_MRC,
+
+        HW_VAR_MGT_FILTER,
+        HW_VAR_CTRL_FILTER,
+        HW_VAR_DATA_FILTER,
+};
+
+enum _RT_MEDIA_STATUS {
+        RT_MEDIA_DISCONNECT = 0,
+        RT_MEDIA_CONNECT = 1
+};
+
+enum rt_oem_id {
+        RT_CID_DEFAULT = 0,
+        RT_CID_8187_ALPHA0 = 1,
+        RT_CID_8187_SERCOMM_PS = 2,
+        RT_CID_8187_HW_LED = 3,
+        RT_CID_8187_NETGEAR = 4,
+        RT_CID_WHQL = 5,
+        RT_CID_819x_CAMEO = 6,
+        RT_CID_819x_RUNTOP = 7,
+        RT_CID_819x_Senao = 8,
+        RT_CID_TOSHIBA = 9,
+        RT_CID_819x_Netcore = 10,
+        RT_CID_Nettronix = 11,
+        RT_CID_DLINK = 12,
+        RT_CID_PRONET = 13,
+        RT_CID_COREGA = 14,
+        RT_CID_819x_ALPHA = 15,
+        RT_CID_819x_Sitecom = 16,
+        RT_CID_CCX = 17,
+        RT_CID_819x_Lenovo = 18,
+        RT_CID_819x_QMI = 19,
+        RT_CID_819x_Edimax_Belkin = 20,
+        RT_CID_819x_Sercomm_Belkin = 21,
+        RT_CID_819x_CAMEO1 = 22,
+        RT_CID_819x_MSI = 23,
+        RT_CID_819x_Acer = 24,
+        RT_CID_819x_HP = 27,
+        RT_CID_819x_CLEVO = 28,
+        RT_CID_819x_Arcadyan_Belkin = 29,
+        RT_CID_819x_SAMSUNG = 30,
+        RT_CID_819x_WNC_COREGA = 31,
+        RT_CID_819x_Foxcoon = 32,
+        RT_CID_819x_DELL = 33,
+};
+
+enum hw_descs {
+        HW_DESC_OWN,
+        HW_DESC_RXOWN,
+        HW_DESC_TX_NEXTDESC_ADDR,
+        HW_DESC_TXBUFF_ADDR,
+        HW_DESC_RXBUFF_ADDR,
+        HW_DESC_RXPKT_LEN,
+        HW_DESC_RXERO,
+};
+
+enum prime_sc {
+        PRIME_CHNL_OFFSET_DONT_CARE = 0,
+        PRIME_CHNL_OFFSET_LOWER = 1,
+        PRIME_CHNL_OFFSET_UPPER = 2,
+};
+
+enum rf_type {
+        RF_1T1R = 0,
+        RF_1T2R = 1,
+        RF_2T2R = 2,
+};
+
+enum ht_channel_width {
+        HT_CHANNEL_WIDTH_20 = 0,
+        HT_CHANNEL_WIDTH_20_40 = 1,
+};
+
+/* Ref: 802.11i sepc D10.0 7.3.2.25.1
+Cipher Suites Encryption Algorithms */
+enum rt_enc_alg {
+        NO_ENCRYPTION = 0,
+        WEP40_ENCRYPTION = 1,
+        TKIP_ENCRYPTION = 2,
+        RSERVED_ENCRYPTION = 3,
+        AESCCMP_ENCRYPTION = 4,
+        WEP104_ENCRYPTION = 5,
+};
+
+enum rtl_hal_state {
+        _HAL_STATE_STOP = 0,
+        _HAL_STATE_START = 1,
+};
+
+enum rtl_var_map {
+        /*reg map */
+        SYS_ISO_CTRL = 0,
+        SYS_FUNC_EN,
+        SYS_CLK,
+        MAC_RCR_AM,
+        MAC_RCR_AB,
+        MAC_RCR_ACRC32,
+        MAC_RCR_ACF,
+        MAC_RCR_AAP,
+
+        /*efuse map */
+        EFUSE_TEST,
+        EFUSE_CTRL,
+        EFUSE_CLK,
+        EFUSE_CLK_CTRL,
+        EFUSE_PWC_EV12V,
+        EFUSE_FEN_ELDR,
+        EFUSE_LOADER_CLK_EN,
+        EFUSE_ANA8M,
+        EFUSE_HWSET_MAX_SIZE,
+
+        /*CAM map */
+        RWCAM,
+        WCAMI,
+        RCAMO,
+        CAMDBG,
+        SECR,
+        SEC_CAM_NONE,
+        SEC_CAM_WEP40,
+        SEC_CAM_TKIP,
+        SEC_CAM_AES,
+        SEC_CAM_WEP104,
+
+        /*IMR map */
+        RTL_IMR_BCNDMAINT6,     /*Beacon DMA Interrupt 6 */
+        RTL_IMR_BCNDMAINT5,     /*Beacon DMA Interrupt 5 */
+        RTL_IMR_BCNDMAINT4,     /*Beacon DMA Interrupt 4 */
+        RTL_IMR_BCNDMAINT3,     /*Beacon DMA Interrupt 3 */
+        RTL_IMR_BCNDMAINT2,     /*Beacon DMA Interrupt 2 */
+        RTL_IMR_BCNDMAINT1,     /*Beacon DMA Interrupt 1 */
+        RTL_IMR_BCNDOK8,        /*Beacon Queue DMA OK Interrup 8 */
+        RTL_IMR_BCNDOK7,        /*Beacon Queue DMA OK Interrup 7 */
+        RTL_IMR_BCNDOK6,        /*Beacon Queue DMA OK Interrup 6 */
+        RTL_IMR_BCNDOK5,        /*Beacon Queue DMA OK Interrup 5 */
+        RTL_IMR_BCNDOK4,        /*Beacon Queue DMA OK Interrup 4 */
+        RTL_IMR_BCNDOK3,        /*Beacon Queue DMA OK Interrup 3 */
+        RTL_IMR_BCNDOK2,        /*Beacon Queue DMA OK Interrup 2 */
+        RTL_IMR_BCNDOK1,        /*Beacon Queue DMA OK Interrup 1 */
+        RTL_IMR_TIMEOUT2,       /*Timeout interrupt 2 */
+        RTL_IMR_TIMEOUT1,       /*Timeout interrupt 1 */
+        RTL_IMR_TXFOVW,         /*Transmit FIFO Overflow */
+        RTL_IMR_PSTIMEOUT,      /*Power save time out interrupt */
+        RTL_IMR_BcnInt,         /*Beacon DMA Interrupt 0 */
+        RTL_IMR_RXFOVW,         /*Receive FIFO Overflow */
+        RTL_IMR_RDU,            /*Receive Descriptor Unavailable */
+        RTL_IMR_ATIMEND,        /*For 92C,ATIM Window End Interrupt */
+        RTL_IMR_BDOK,           /*Beacon Queue DMA OK Interrup */
+        RTL_IMR_HIGHDOK,        /*High Queue DMA OK Interrupt */
+        RTL_IMR_TBDOK,          /*Transmit Beacon OK interrup */
+        RTL_IMR_MGNTDOK,        /*Management Queue DMA OK Interrupt */
+        RTL_IMR_TBDER,          /*For 92C,Transmit Beacon Error Interrupt */
+        RTL_IMR_BKDOK,          /*AC_BK DMA OK Interrupt */
+        RTL_IMR_BEDOK,          /*AC_BE DMA OK Interrupt */
+        RTL_IMR_VIDOK,          /*AC_VI DMA OK Interrupt */
+        RTL_IMR_VODOK,          /*AC_VO DMA Interrupt */
+        RTL_IMR_ROK,            /*Receive DMA OK Interrupt */
+        RTL_IBSS_INT_MASKS,     /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/
+
+        /*CCK Rates, TxHT = 0 */
+        RTL_RC_CCK_RATE1M,
+        RTL_RC_CCK_RATE2M,
+        RTL_RC_CCK_RATE5_5M,
+        RTL_RC_CCK_RATE11M,
+
+        /*OFDM Rates, TxHT = 0 */
+        RTL_RC_OFDM_RATE6M,
+        RTL_RC_OFDM_RATE9M,
+        RTL_RC_OFDM_RATE12M,
+        RTL_RC_OFDM_RATE18M,
+        RTL_RC_OFDM_RATE24M,
+        RTL_RC_OFDM_RATE36M,
+        RTL_RC_OFDM_RATE48M,
+        RTL_RC_OFDM_RATE54M,
+
+        RTL_RC_HT_RATEMCS7,
+        RTL_RC_HT_RATEMCS15,
+
+        /*keep it last */
+        RTL_VAR_MAP_MAX,
+};
+
+/*Firmware PS mode for control LPS.*/
+enum _fw_ps_mode {
+        FW_PS_ACTIVE_MODE = 0,
+        FW_PS_MIN_MODE = 1,
+        FW_PS_MAX_MODE = 2,
+        FW_PS_DTIM_MODE = 3,
+        FW_PS_VOIP_MODE = 4,
+        FW_PS_UAPSD_WMM_MODE = 5,
+        FW_PS_UAPSD_MODE = 6,
+        FW_PS_IBSS_MODE = 7,
+        FW_PS_WWLAN_MODE = 8,
+        FW_PS_PM_Radio_Off = 9,
+        FW_PS_PM_Card_Disable = 10,
+};
+
+enum rt_psmode {
+        EACTIVE,                /*Active/Continuous access. */
+        EMAXPS,                 /*Max power save mode. */
+        EFASTPS,                /*Fast power save mode. */
+        EAUTOPS,                /*Auto power save mode. */
+};
+
+/*LED related.*/
+enum led_ctl_mode {
+        LED_CTL_POWER_ON = 1,
+        LED_CTL_LINK = 2,
+        LED_CTL_NO_LINK = 3,
+        LED_CTL_TX = 4,
+        LED_CTL_RX = 5,
+        LED_CTL_SITE_SURVEY = 6,
+        LED_CTL_POWER_OFF = 7,
+        LED_CTL_START_TO_LINK = 8,
+        LED_CTL_START_WPS = 9,
+        LED_CTL_STOP_WPS = 10,
+};
+
+enum rtl_led_pin {
+        LED_PIN_GPIO0,
+        LED_PIN_LED0,
+        LED_PIN_LED1,
+        LED_PIN_LED2
+};
+
+/*QoS related.*/
+/*acm implementation method.*/
+enum acm_method {
+        eAcmWay0_SwAndHw = 0,
+        eAcmWay1_HW = 1,
+        eAcmWay2_SW = 2,
+};
+
+/*aci/aifsn Field.
+Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
+union aci_aifsn {
+        u8 char_data;
+
+        struct {
+                u8 aifsn:4;
+                u8 acm:1;
+                u8 aci:2;
+                u8 reserved:1;
+        } f;                    /* Field */
+};
+
+/*mlme related.*/
+enum wireless_mode {
+        WIRELESS_MODE_UNKNOWN = 0x00,
+        WIRELESS_MODE_A = 0x01,
+        WIRELESS_MODE_B = 0x02,
+        WIRELESS_MODE_G = 0x04,
+        WIRELESS_MODE_AUTO = 0x08,
+        WIRELESS_MODE_N_24G = 0x10,
+        WIRELESS_MODE_N_5G = 0x20
+};
+
+enum ratr_table_mode {
+        RATR_INX_WIRELESS_NGB = 0,
+        RATR_INX_WIRELESS_NG = 1,
+        RATR_INX_WIRELESS_NB = 2,
+        RATR_INX_WIRELESS_N = 3,
+        RATR_INX_WIRELESS_GB = 4,
+        RATR_INX_WIRELESS_G = 5,
+        RATR_INX_WIRELESS_B = 6,
+        RATR_INX_WIRELESS_MC = 7,
+        RATR_INX_WIRELESS_A = 8,
+};
+
+enum rtl_link_state {
+        MAC80211_NOLINK = 0,
+        MAC80211_LINKING = 1,
+        MAC80211_LINKED = 2,
+        MAC80211_LINKED_SCANNING = 3,
+};
+
+enum act_category {
+        ACT_CAT_QOS = 1,
+        ACT_CAT_DLS = 2,
+        ACT_CAT_BA = 3,
+        ACT_CAT_HT = 7,
+        ACT_CAT_WMM = 17,
+};
+
+enum ba_action {
+        ACT_ADDBAREQ = 0,
+        ACT_ADDBARSP = 1,
+        ACT_DELBA = 2,
+};
+
+struct octet_string {
+        u8 *octet;
+        u16 length;
+};
+
+struct rtl_hdr_3addr {
+        __le16 frame_ctl;
+        __le16 duration_id;
+        u8 addr1[ETH_ALEN];
+        u8 addr2[ETH_ALEN];
+        u8 addr3[ETH_ALEN];
+        __le16 seq_ctl;
+        u8 payload[0];
+} __packed;
+
+struct rtl_info_element {
+        u8 id;
+        u8 len;
+        u8 data[0];
+} __packed;
+
+struct rtl_probe_rsp {
+        struct rtl_hdr_3addr header;
+        u32 time_stamp[2];
+        __le16 beacon_interval;
+        __le16 capability;
+        /*SSID, supported rates, FH params, DS params,
+           CF params, IBSS params, TIM (if beacon), RSN */
+        struct rtl_info_element info_element[0];
+} __packed;
+
+/*LED related.*/
+/*ledpin Identify how to implement this SW led.*/
+struct rtl_led {
+        void *hw;
+        enum rtl_led_pin ledpin;
+        bool b_ledon;
+};
+
+struct rtl_led_ctl {
+        bool bled_opendrain;
+        struct rtl_led sw_led0;
+        struct rtl_led sw_led1;
+};
+
+struct rtl_qos_parameters {
+        __le16 cw_min;
+        __le16 cw_max;
+        u8 aifs;
+        u8 flag;
+        __le16 tx_op;
+} __packed;
+
+struct rt_smooth_data {
+        u32 elements[100];      /*array to store values */
+        u32 index;              /*index to current array to store */
+        u32 total_num;          /*num of valid elements */
+        u32 total_val;          /*sum of valid elements */
+};
+
+struct false_alarm_statistics {
+        u32 cnt_parity_fail;
+        u32 cnt_rate_illegal;
+        u32 cnt_crc8_fail;
+        u32 cnt_mcs_fail;
+        u32 cnt_ofdm_fail;
+        u32 cnt_cck_fail;
+        u32 cnt_all;
+};
+
+struct init_gain {
+        u8 xaagccore1;
+        u8 xbagccore1;
+        u8 xcagccore1;
+        u8 xdagccore1;
+        u8 cca;
+
+};
+
+struct wireless_stats {
+        unsigned long txbytesunicast;
+        unsigned long txbytesmulticast;
+        unsigned long txbytesbroadcast;
+        unsigned long rxbytesunicast;
+
+        long rx_snr_db[4];
+        /*Correct smoothed ss in Dbm, only used
+           in driver to report real power now. */
+        long recv_signal_power;
+        long signal_quality;
+        long last_sigstrength_inpercent;
+
+        u32 rssi_calculate_cnt;
+
+        /*Transformed, in dbm. Beautified signal
+           strength for UI, not correct. */
+        long signal_strength;
+
+        u8 rx_rssi_percentage[4];
+        u8 rx_evm_percentage[2];
+
+        struct rt_smooth_data ui_rssi;
+        struct rt_smooth_data ui_link_quality;
+};
+
+struct rate_adaptive {
+        u8 rate_adaptive_disabled;
+        u8 ratr_state;
+        u16 reserve;
+
+        u32 high_rssi_thresh_for_ra;
+        u32 high2low_rssi_thresh_for_ra;
+        u8 low2high_rssi_thresh_for_ra40m;
+        u32 low_rssi_thresh_for_ra40M;
+        u8 low2high_rssi_thresh_for_ra20m;
+        u32 low_rssi_thresh_for_ra20M;
+        u32 upper_rssi_threshold_ratr;
+        u32 middleupper_rssi_threshold_ratr;
+        u32 middle_rssi_threshold_ratr;
+        u32 middlelow_rssi_threshold_ratr;
+        u32 low_rssi_threshold_ratr;
+        u32 ultralow_rssi_threshold_ratr;
+        u32 low_rssi_threshold_ratr_40m;
+        u32 low_rssi_threshold_ratr_20m;
+        u8 ping_rssi_enable;
+        u32 ping_rssi_ratr;
+        u32 ping_rssi_thresh_for_ra;
+        u32 last_ratr;
+        u8 pre_ratr_state;
+};
+
+struct regd_pair_mapping {
+        u16 reg_dmnenum;
+        u16 reg_5ghz_ctl;
+        u16 reg_2ghz_ctl;
+};
+
+struct rtl_regulatory {
+        char alpha2[2];
+        u16 country_code;
+        u16 max_power_level;
+        u32 tp_scale;
+        u16 current_rd;
+        u16 current_rd_ext;
+        int16_t power_limit;
+        struct regd_pair_mapping *regpair;
+};
+
+struct rtl_rfkill {
+        bool rfkill_state;      /*0 is off, 1 is on */
+};
+
+struct rtl_phy {
+        struct bb_reg_def phyreg_def[4];        /*Radio A/B/C/D */
+        struct init_gain initgain_backup;
+        enum io_type current_io_type;
+
+        u8 rf_mode;
+        u8 rf_type;
+        u8 current_chan_bw;
+        u8 set_bwmode_inprogress;
+        u8 sw_chnl_inprogress;
+        u8 sw_chnl_stage;
+        u8 sw_chnl_step;
+        u8 current_channel;
+        u8 h2c_box_num;
+        u8 set_io_inprogress;
+
+        /*record for power tracking*/
+        s32 reg_e94;
+        s32 reg_e9c;
+        s32 reg_ea4;
+        s32 reg_eac;
+        s32 reg_eb4;
+        s32 reg_ebc;
+        s32 reg_ec4;
+        s32 reg_ecc;
+        u8 rfpienable;
+        u8 reserve_0;
+        u16 reserve_1;
+        u32 reg_c04, reg_c08, reg_874;
+        u32 adda_backup[16];
+        u32 iqk_mac_backup[IQK_MAC_REG_NUM];
+        u32 iqk_bb_backup[10];
+
+        bool b_rfpi_enable;
+
+        u8 pwrgroup_cnt;
+        u8 bcck_high_power;
+        /* 3 groups of pwr diff by rates*/
+        u32 mcs_txpwrlevel_origoffset[4][16];
+        u8 default_initialgain[4];
+
+        /*the current Tx power level*/
+        u8 cur_cck_txpwridx;
+        u8 cur_ofdm24g_txpwridx;
+
+        u32 rfreg_chnlval[2];
+        bool b_apk_done;
+
+        /*fsync*/
+        u8 framesync;
+        u32 framesync_c34;
+
+        u8 num_total_rfpath;
+};
+
+#define MAX_TID_COUNT                           9
+#define RTL_AGG_OFF                             0
+#define RTL_AGG_ON                              1
+#define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA         2
+#define RTL_AGG_EMPTYING_HW_QUEUE_DELBA         3
+
+struct rtl_ht_agg {
+        u16 txq_id;
+        u16 wait_for_ba;
+        u16 start_idx;
+        u64 bitmap;
+        u32 rate_n_flags;
+        u8 agg_state;
+};
+
+struct rtl_tid_data {
+        u16 seq_number;
+        struct rtl_ht_agg agg;
+};
+
+struct rtl_priv;
+struct rtl_io {
+        struct device *dev;
+
+        /*PCI MEM map */
+        unsigned long pci_mem_end;      /*shared mem end        */
+        unsigned long pci_mem_start;    /*shared mem start */
+
+        /*PCI IO map */
+        unsigned long pci_base_addr;    /*device I/O address */
+
+        void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
+        void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
+        void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
+
+         u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
+         u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
+         u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
+
+};
+
+struct rtl_mac {
+        u8 mac_addr[ETH_ALEN];
+        u8 mac80211_registered;
+        u8 beacon_enabled;
+
+        u32 tx_ss_num;
+        u32 rx_ss_num;
+
+        struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
+        struct ieee80211_hw *hw;
+        struct ieee80211_vif *vif;
+        enum nl80211_iftype opmode;
+
+        /*Probe Beacon management */
+        struct rtl_tid_data tids[MAX_TID_COUNT];
+        enum rtl_link_state link_state;
+
+        int n_channels;
+        int n_bitrates;
+
+        /*filters */
+        u32 rx_conf;
+        u16 rx_mgt_filter;
+        u16 rx_ctrl_filter;
+        u16 rx_data_filter;
+
+        bool act_scanning;
+        u8 cnt_after_linked;
+
+         /*RDG*/ bool rdg_en;
+
+         /*AP*/ u8 bssid[6];
+        u8 mcs[16];     /*16 bytes mcs for HT rates.*/
+        u32 basic_rates; /*b/g rates*/
+        u8 ht_enable;
+        u8 sgi_40;
+        u8 sgi_20;
+        u8 bw_40;
+        u8 mode;                /*wireless mode*/
+        u8 slot_time;
+        u8 short_preamble;
+        u8 use_cts_protect;
+        u8 cur_40_prime_sc;
+        u8 cur_40_prime_sc_bk;
+        u64 tsf;
+        u8 retry_short;
+        u8 retry_long;
+        u16 assoc_id;
+
+         /*IBSS*/ int beacon_interval;
+
+         /*AMPDU*/ u8 min_space_cfg;    /*For Min spacing configurations */
+        u8 max_mss_density;
+        u8 current_ampdu_factor;
+        u8 current_ampdu_density;
+
+        /*QOS & EDCA */
+        struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
+        struct rtl_qos_parameters ac[AC_MAX];
+};
+
+struct rtl_hal {
+        struct ieee80211_hw *hw;
+
+        enum intf_type interface;
+        u16 hw_type;            /*92c or 92d or 92s and so on */
+        u8 oem_id;
+        u8 version;             /*version of chip */
+        u8 state;               /*stop 0, start 1 */
+
+        /*firmware */
+        u8 *pfirmware;
+        bool b_h2c_setinprogress;
+        u8 last_hmeboxnum;
+        bool bfw_ready;
+        /*Reserve page start offset except beacon in TxQ. */
+        u8 fw_rsvdpage_startoffset;
+};
+
+struct rtl_security {
+        /*default 0 */
+        bool use_sw_sec;
+
+        bool being_setkey;
+        bool use_defaultkey;
+        /*Encryption Algorithm for Unicast Packet */
+        enum rt_enc_alg pairwise_enc_algorithm;
+        /*Encryption Algorithm for Brocast/Multicast */
+        enum rt_enc_alg group_enc_algorithm;
+
+        /*local Key buffer, indx 0 is for
+           pairwise key 1-4 is for agoup key. */
+        u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
+        u8 key_len[KEY_BUF_SIZE];
+
+        /*The pointer of Pairwise Key,
+           it always points to KeyBuf[4] */
+        u8 *pairwise_key;
+};
+
+struct rtl_dm {
+        /*PHY status for DM */
+        long entry_min_undecoratedsmoothed_pwdb;
+        long undecorated_smoothed_pwdb; /*out dm */
+        long entry_max_undecoratedsmoothed_pwdb;
+        bool b_dm_initialgain_enable;
+        bool bdynamic_txpower_enable;
+        bool bcurrent_turbo_edca;
+        bool bis_any_nonbepkts; /*out dm */
+        bool bis_cur_rdlstate;
+        bool btxpower_trackingInit;
+        bool b_disable_framebursting;
+        bool b_cck_inch14;
+        bool btxpower_tracking;
+        bool b_useramask;
+        bool brfpath_rxenable[4];
+
+        u8 thermalvalue_iqk;
+        u8 thermalvalue_lck;
+        u8 thermalvalue;
+        u8 last_dtp_lvl;
+        u8 dynamic_txhighpower_lvl;     /*Tx high power level */
+        u8 dm_flag;     /*Indicate if each dynamic mechanism's status. */
+        u8 dm_type;
+        u8 txpower_track_control;
+
+        char ofdm_index[2];
+        char cck_index;
+};
+
+#define EFUSE_MAX_LOGICAL_SIZE                   128
+
+struct rtl_efuse {
+        bool bautoLoad_ok;
+        bool bootfromefuse;
+        u16 max_physical_size;
+        u8 contents[EFUSE_MAX_LOGICAL_SIZE];
+
+        u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
+        u16 efuse_usedbytes;
+        u8 efuse_usedpercentage;
+
+        u8 autoload_failflag;
+
+        short epromtype;
+        u16 eeprom_vid;
+        u16 eeprom_did;
+        u16 eeprom_svid;
+        u16 eeprom_smid;
+        u8 eeprom_oemid;
+        u16 eeprom_channelplan;
+        u8 eeprom_version;
+
+        u8 dev_addr[6];
+
+        bool b_txpwr_fromeprom;
+        u8 eeprom_tssi[2];
+        u8 eeprom_pwrlimit_ht20[3];
+        u8 eeprom_pwrlimit_ht40[3];
+        u8 eeprom_chnlarea_txpwr_cck[2][3];
+        u8 eeprom_chnlarea_txpwr_ht40_1s[2][3];
+        u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3];
+        u8 txpwrlevel_cck[2][14];
+        u8 txpwrlevel_ht40_1s[2][14];   /*For HT 40MHZ pwr */
+        u8 txpwrlevel_ht40_2s[2][14];   /*For HT 40MHZ pwr */
+
+        /*For power group */
+        u8 pwrgroup_ht20[2][14];
+        u8 pwrgroup_ht40[2][14];
+
+        char txpwr_ht20diff[2][14];     /*HT 20<->40 Pwr diff */
+        u8 txpwr_legacyhtdiff[2][14];   /*For HT<->legacy pwr diff */
+
+        u8 eeprom_regulatory;
+        u8 eeprom_thermalmeter;
+        /*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
+        u8 thermalmeter[2];
+
+        u8 legacy_ht_txpowerdiff;       /*Legacy to HT rate power diff */
+        bool b_apk_thermalmeterignore;
+};
+
+struct rtl_ps_ctl {
+        bool set_rfpowerstate_inprogress;
+        bool b_in_powersavemode;
+        bool rfchange_inprogress;
+        bool b_swrf_processing;
+        bool b_hwradiooff;
+
+        u32 last_sleep_jiffies;
+        u32 last_awake_jiffies;
+        u32 last_delaylps_stamp_jiffies;
+
+        /*
+         * just for PCIE ASPM
+         * If it supports ASPM, Offset[560h] = 0x40,
+         * otherwise Offset[560h] = 0x00.
+         * */
+        bool b_support_aspm;
+        bool b_support_backdoor;
+
+        /*for LPS */
+        enum rt_psmode dot11_psmode;    /*Power save mode configured. */
+        bool b_leisure_ps;
+        bool b_fwctrl_lps;
+        u8 fwctrl_psmode;
+        /*For Fw control LPS mode */
+        u8 b_reg_fwctrl_lps;
+        /*Record Fw PS mode status. */
+        bool b_fw_current_inpsmode;
+        u8 reg_max_lps_awakeintvl;
+        bool report_linked;
+
+        /*for IPS */
+        bool b_inactiveps;
+
+        u32 rfoff_reason;
+
+        /*RF OFF Level */
+        u32 cur_ps_level;
+        u32 reg_rfps_level;
+
+        /*just for PCIE ASPM */
+        u8 const_amdpci_aspm;
+
+        enum rf_pwrstate inactive_pwrstate;
+        enum rf_pwrstate rfpwr_state;   /*cur power state */
+};
+
+struct rtl_stats {
+        u32 mac_time[2];
+        s8 rssi;
+        u8 signal;
+        u8 noise;
+        u16 rate;               /*in 100 kbps */
+        u8 received_channel;
+        u8 control;
+        u8 mask;
+        u8 freq;
+        u16 len;
+        u64 tsf;
+        u32 beacon_time;
+        u8 nic_type;
+        u16 length;
+        u8 signalquality;       /*in 0-100 index. */
+        /*
+         * Real power in dBm for this packet,
+         * no beautification and aggregation.
+         * */
+        s32 recvsignalpower;
+        s8 rxpower;             /*in dBm Translate from PWdB */
+        u8 signalstrength;      /*in 0-100 index. */
+        u16 b_hwerror:1;
+        u16 b_crc:1;
+        u16 b_icv:1;
+        u16 b_shortpreamble:1;
+        u16 antenna:1;
+        u16 decrypted:1;
+        u16 wakeup:1;
+        u32 timestamp_low;
+        u32 timestamp_high;
+
+        u8 rx_drvinfo_size;
+        u8 rx_bufshift;
+        bool b_isampdu;
+        bool rx_is40Mhzpacket;
+        u32 rx_pwdb_all;
+        u8 rx_mimo_signalstrength[4];   /*in 0~100 index */
+        s8 rx_mimo_signalquality[2];
+        bool b_packet_matchbssid;
+        bool b_is_cck;
+        bool b_packet_toself;
+        bool b_packet_beacon;   /*for rssi */
+        char cck_adc_pwdb[4];   /*for rx path selection */
+};
+
+struct rt_link_detect {
+        u32 num_tx_in4period[4];
+        u32 num_rx_in4period[4];
+
+        u32 num_tx_inperiod;
+        u32 num_rx_inperiod;
+
+        bool b_busytraffic;
+        bool b_higher_busytraffic;
+        bool b_higher_busyrxtraffic;
+};
+
+struct rtl_tcb_desc {
+        u8 b_packet_bw:1;
+        u8 b_multicast:1;
+        u8 b_broadcast:1;
+
+        u8 b_rts_stbc:1;
+        u8 b_rts_enable:1;
+        u8 b_cts_enable:1;
+        u8 b_rts_use_shortpreamble:1;
+        u8 b_rts_use_shortgi:1;
+        u8 rts_sc:1;
+        u8 b_rts_bw:1;
+        u8 rts_rate;
+
+        u8 use_shortgi:1;
+        u8 use_shortpreamble:1;
+        u8 use_driver_rate:1;
+        u8 disable_ratefallback:1;
+
+        u8 ratr_index;
+        u8 mac_id;
+        u8 hw_rate;
+};
+
+struct rtl_hal_ops {
+        int (*init_sw_vars) (struct ieee80211_hw *hw);
+        void (*deinit_sw_vars) (struct ieee80211_hw *hw);
+        void (*read_eeprom_info) (struct ieee80211_hw *hw);
+        void (*interrupt_recognized) (struct ieee80211_hw *hw,
+                                      u32 *p_inta, u32 *p_intb);
+        int (*hw_init) (struct ieee80211_hw *hw);
+        void (*hw_disable) (struct ieee80211_hw *hw);
+        void (*enable_interrupt) (struct ieee80211_hw *hw);
+        void (*disable_interrupt) (struct ieee80211_hw *hw);
+        int (*set_network_type) (struct ieee80211_hw *hw,
+                                 enum nl80211_iftype type);
+        void (*set_bw_mode) (struct ieee80211_hw *hw,
+                             enum nl80211_channel_type ch_type);
+         u8(*switch_channel) (struct ieee80211_hw *hw);
+        void (*set_qos) (struct ieee80211_hw *hw, int aci);
+        void (*set_bcn_reg) (struct ieee80211_hw *hw);
+        void (*set_bcn_intv) (struct ieee80211_hw *hw);
+        void (*update_interrupt_mask) (struct ieee80211_hw *hw,
+                                       u32 add_msr, u32 rm_msr);
+        void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
+        void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
+        void (*update_rate_table) (struct ieee80211_hw *hw);
+        void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
+        void (*fill_tx_desc) (struct ieee80211_hw *hw,
+                              struct ieee80211_hdr *hdr, u8 *pdesc_tx,
+                              struct ieee80211_tx_info *info,
+                              struct sk_buff *skb, unsigned int queue_index);
+        void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
+                                 bool b_firstseg, bool b_lastseg,
+                                 struct sk_buff *skb);
+         bool(*query_rx_desc) (struct ieee80211_hw *hw,
+                               struct rtl_stats *stats,
+                               struct ieee80211_rx_status *rx_status,
+                               u8 *pdesc, struct sk_buff *skb);
+        void (*set_channel_access) (struct ieee80211_hw *hw);
+         bool(*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
+        void (*dm_watchdog) (struct ieee80211_hw *hw);
+        void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
+         bool(*set_rf_power_state) (struct ieee80211_hw *hw,
+                                    enum rf_pwrstate rfpwr_state);
+        void (*led_control) (struct ieee80211_hw *hw,
+                             enum led_ctl_mode ledaction);
+        void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
+         u32(*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
+        void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
+        void (*enable_hw_sec) (struct ieee80211_hw *hw);
+        void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
+                         u8 *p_macaddr, bool is_group, u8 enc_algo,
+                         bool is_wepkey, bool clear_all);
+        void (*init_sw_leds) (struct ieee80211_hw *hw);
+        void (*deinit_sw_leds) (struct ieee80211_hw *hw);
+         u32(*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
+        void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
+                           u32 data);
+         u32(*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
+                          u32 regaddr, u32 bitmask);
+        void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
+                           u32 regaddr, u32 bitmask, u32 data);
+};
+
+struct rtl_intf_ops {
+        /*com */
+        int (*adapter_start) (struct ieee80211_hw *hw);
+        void (*adapter_stop) (struct ieee80211_hw *hw);
+
+        int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
+        int (*reset_trx_ring) (struct ieee80211_hw *hw);
+
+        /*pci */
+        void (*disable_aspm) (struct ieee80211_hw *hw);
+        void (*enable_aspm) (struct ieee80211_hw *hw);
+
+        /*usb */
+};
+
+struct rtl_mod_params {
+        /* default: 0 = using hardware encryption */
+        int sw_crypto;
+};
+
+struct rtl_hal_cfg {
+        char *name;
+        char *fw_name;
+        struct rtl_hal_ops *ops;
+        struct rtl_mod_params *mod_params;
+
+        /*this map used for some registers or vars
+           defined int HAL but used in MAIN */
+        u32 maps[RTL_VAR_MAP_MAX];
+
+};
+
+struct rtl_locks {
+        /* mutex */
+        struct mutex conf_mutex;
+
+        /*spin lock */
+        spinlock_t ips_lock;
+        spinlock_t irq_th_lock;
+        spinlock_t h2c_lock;
+        spinlock_t rf_ps_lock;
+        spinlock_t rf_lock;
+        spinlock_t lps_lock;
+};
+
+struct rtl_works {
+        struct ieee80211_hw *hw;
+
+        /*timer */
+        struct timer_list watchdog_timer;
+
+        /*task */
+        struct tasklet_struct irq_tasklet;
+        struct tasklet_struct irq_prepare_bcn_tasklet;
+
+        /*work queue */
+        struct workqueue_struct *rtl_wq;
+        struct delayed_work watchdog_wq;
+        struct delayed_work ips_nic_off_wq;
+};
+
+struct rtl_debug {
+        u32 dbgp_type[DBGP_TYPE_MAX];
+        u32 global_debuglevel;
+        u64 global_debugcomponents;
+};
+
+struct rtl_priv {
+        struct rtl_locks locks;
+        struct rtl_works works;
+        struct rtl_mac mac80211;
+        struct rtl_hal rtlhal;
+        struct rtl_regulatory regd;
+        struct rtl_rfkill rfkill;
+        struct rtl_io io;
+        struct rtl_phy phy;
+        struct rtl_dm dm;
+        struct rtl_security sec;
+        struct rtl_efuse efuse;
+
+        struct rtl_ps_ctl psc;
+        struct rate_adaptive ra;
+        struct wireless_stats stats;
+        struct rt_link_detect link_info;
+        struct false_alarm_statistics falsealm_cnt;
+
+        struct rtl_rate_priv *rate_priv;
+
+        struct rtl_debug dbg;
+
+        /*
+         *hal_cfg : for diff cards
+         *intf_ops : for diff interrface usb/pcie
+         */
+        struct rtl_hal_cfg *cfg;
+        struct rtl_intf_ops *intf_ops;
+
+        /*this var will be set by set_bit,
+           and was used to indicate status of
+           interface or hardware */
+        unsigned long status;
+
+        /*This must be the last item so
+           that it points to the data allocated
+           beyond  this structure like:
+           rtl_pci_priv or rtl_usb_priv */
+        u8 priv[0];
+};
+
+#define rtl_priv(hw)            (((struct rtl_priv *)(hw)->priv))
+#define rtl_mac(rtlpriv)        (&((rtlpriv)->mac80211))
+#define rtl_hal(rtlpriv)        (&((rtlpriv)->rtlhal))
+#define rtl_efuse(rtlpriv)      (&((rtlpriv)->efuse))
+#define rtl_psc(rtlpriv)        (&((rtlpriv)->psc))
+
+/****************************************
+        mem access macro define start
+        Call endian free function when
+        1. Read/write packet content.
+        2. Before write integer to IO.
+        3. After read integer from IO.
+****************************************/
+/* Convert little data endian to host */
+#define EF1BYTE(_val)           \
+        ((u8)(_val))
+#define EF2BYTE(_val)           \
+        (le16_to_cpu(_val))
+#define EF4BYTE(_val)           \
+        (le32_to_cpu(_val))
+
+/* Read data from memory */
+#define READEF1BYTE(_ptr)       \
+        EF1BYTE(*((u8 *)(_ptr)))
+#define READEF2BYTE(_ptr)       \
+        EF2BYTE(*((u16 *)(_ptr)))
+#define READEF4BYTE(_ptr)       \
+        EF4BYTE(*((u32 *)(_ptr)))
+
+/* Write data to memory */
+#define WRITEEF1BYTE(_ptr, _val)        \
+        (*((u8 *)(_ptr))) = EF1BYTE(_val)
+#define WRITEEF2BYTE(_ptr, _val)        \
+        (*((u16 *)(_ptr))) = EF2BYTE(_val)
+#define WRITEEF4BYTE(_ptr, _val)        \
+        (*((u32 *)(_ptr))) = EF4BYTE(_val)
+
+/*Example:
+BIT_LEN_MASK_32(0) => 0x00000000
+BIT_LEN_MASK_32(1) => 0x00000001
+BIT_LEN_MASK_32(2) => 0x00000003
+BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
+#define BIT_LEN_MASK_32(__bitlen)        \
+        (0xFFFFFFFF >> (32 - (__bitlen)))
+#define BIT_LEN_MASK_16(__bitlen)        \
+        (0xFFFF >> (16 - (__bitlen)))
+#define BIT_LEN_MASK_8(__bitlen) \
+        (0xFF >> (8 - (__bitlen)))
+
+/*Example:
+BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
+BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
+#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
+        (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
+#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
+        (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
+#define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
+        (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
+
+/*Description:
+Return 4-byte value in host byte ordering from
+4-byte pointer in little-endian system.*/
+#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
+        (EF4BYTE(*((u32 *)(__pstart))))
+#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
+        (EF2BYTE(*((u16 *)(__pstart))))
+#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
+        (EF1BYTE(*((u8 *)(__pstart))))
+
+/*Description:
+Translate subfield (continuous bits in little-endian) of 4-byte
+value to host byte ordering.*/
+#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
+        ( \
+                (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset))  & \
+                BIT_LEN_MASK_32(__bitlen) \
+        )
+#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
+        ( \
+                (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
+                BIT_LEN_MASK_16(__bitlen) \
+        )
+#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
+        ( \
+                (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
+                BIT_LEN_MASK_8(__bitlen) \
+        )
+
+/*Description:
+Mask subfield (continuous bits in little-endian) of 4-byte value
+and return the result in 4-byte value in host byte ordering.*/
+#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
+        ( \
+                LE_P4BYTE_TO_HOST_4BYTE(__pstart)  & \
+                (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
+        )
+#define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
+        ( \
+                LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
+                (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
+        )
+#define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
+        ( \
+                LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
+                (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
+        )
+
+/*Description:
+Set subfield of little-endian 4-byte value to specified value.  */
+#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
+        *((u32 *)(__pstart)) = EF4BYTE \
+        ( \
+                LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
+                ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
+        );
+#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
+        *((u16 *)(__pstart)) = EF2BYTE \
+        ( \
+                LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
+                ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
+        );
+#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
+        *((u8 *)(__pstart)) = EF1BYTE \
+        ( \
+                LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
+                ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
+        );
+
+/****************************************
+        mem access macro define end
+****************************************/
+
+#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
+#define RTL_WATCH_DOG_TIME      2000
+#define MSECS(t)                msecs_to_jiffies(t)
+#define WLAN_FC_GET_VERS(fc)    ((fc) & IEEE80211_FCTL_VERS)
+#define WLAN_FC_GET_TYPE(fc)    ((fc) & IEEE80211_FCTL_FTYPE)
+#define WLAN_FC_GET_STYPE(fc)   ((fc) & IEEE80211_FCTL_STYPE)
+#define WLAN_FC_MORE_DATA(fc)   ((fc) & IEEE80211_FCTL_MOREDATA)
+#define SEQ_TO_SN(seq)          (((seq) & IEEE80211_SCTL_SEQ) >> 4)
+#define SN_TO_SEQ(ssn)          (((ssn) << 4) & IEEE80211_SCTL_SEQ)
+#define MAX_SN                  ((IEEE80211_SCTL_SEQ) >> 4)
+
+#define RT_RF_OFF_LEVL_ASPM             BIT(0)  /*PCI ASPM */
+#define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /*PCI clock request */
+#define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /*PCI D3 mode */
+/*NIC halt, re-initialize hw parameters*/
+#define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)
+#define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /*FW free, re-download the FW */
+#define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /*FW in 32k */
+/*Always enable ASPM and Clock Req in initialization.*/
+#define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)
+/*When LPS is on, disable 2R if no packet is received or transmittd.*/
+#define RT_RF_LPS_DISALBE_2R            BIT(30)
+#define RT_RF_LPS_LEVEL_ASPM            BIT(31) /*LPS with ASPM */
+#define RT_IN_PS_LEVEL(ppsc, _ps_flg)           \
+        ((ppsc->cur_ps_level & _ps_flg) ? true : false)
+#define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg)        \
+        (ppsc->cur_ps_level &= (~(_ps_flg)))
+#define RT_SET_PS_LEVEL(ppsc, _ps_flg)          \
+        (ppsc->cur_ps_level |= _ps_flg)
+
+#define container_of_dwork_rtl(x, y, z) \
+        container_of(container_of(x, struct delayed_work, work), y, z)
+
+#define FILL_OCTET_STRING(_os, _octet, _len)    \
+                (_os).octet = (u8 *)(_octet);           \
+                (_os).length = (_len);
+
+#define CP_MACADDR(des, src)    \
+        ((des)[0] = (src)[0], (des)[1] = (src)[1],\
+        (des)[2] = (src)[2], (des)[3] = (src)[3],\
+        (des)[4] = (src)[4], (des)[5] = (src)[5])
+
+static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
+{
+        return rtlpriv->io.read8_sync(rtlpriv, addr);
+}
+
+static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
+{
+        return rtlpriv->io.read16_sync(rtlpriv, addr);
+}
+
+static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
+{
+        return rtlpriv->io.read32_sync(rtlpriv, addr);
+}
+
+static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
+{
+        rtlpriv->io.write8_async(rtlpriv, addr, val8);
+}
+
+static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
+{
+        rtlpriv->io.write16_async(rtlpriv, addr, val16);
+}
+
+static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
+                                   u32 addr, u32 val32)
+{
+        rtlpriv->io.write32_async(rtlpriv, addr, val32);
+}
+
+static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
+                                u32 regaddr, u32 bitmask)
+{
+        return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_bbreg(hw,
+                                                                    regaddr,
+                                                                    bitmask);
+}
+
+static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
+                                 u32 bitmask, u32 data)
+{
+        ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_bbreg(hw,
+                                                             regaddr, bitmask,
+                                                             data);
+
+}
+
+static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
+                                enum radio_path rfpath, u32 regaddr,
+                                u32 bitmask)
+{
+        return ((struct rtl_priv *)(hw)->priv)->cfg->ops->get_rfreg(hw,
+                                                                    rfpath,
+                                                                    regaddr,
+                                                                    bitmask);
+}
+
+static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
+                                 enum radio_path rfpath, u32 regaddr,
+                                 u32 bitmask, u32 data)
+{
+        ((struct rtl_priv *)(hw)->priv)->cfg->ops->set_rfreg(hw,
+                                                             rfpath, regaddr,
+                                                             bitmask, data);
+}
+
+static inline bool is_hal_stop(struct rtl_hal *rtlhal)
+{
+        return (_HAL_STATE_STOP == rtlhal->state);
+}
+
+static inline void set_hal_start(struct rtl_hal *rtlhal)
+{
+        rtlhal->state = _HAL_STATE_START;
+}
+
+static inline void set_hal_stop(struct rtl_hal *rtlhal)
+{
+        rtlhal->state = _HAL_STATE_STOP;
+}
+
+static inline u8 get_rf_type(struct rtl_phy *rtlphy)
+{
+        return rtlphy->rf_type;
+}
+
+#endif
diff --git a/drivers/net/wireless/wl1251/boot.c b/drivers/net/wireless/wl1251/boot.c
index 61572dfa1f60..d729daf8e841 100644
--- a/drivers/net/wireless/wl1251/boot.c
+++ b/drivers/net/wireless/wl1251/boot.c
@@ -19,7 +19,6 @@
  *
  */
 
-#include <linux/gpio.h>
 #include <linux/slab.h>
 
 #include "reg.h"
diff --git a/drivers/net/wireless/wl1251/main.c b/drivers/net/wireless/wl1251/main.c
index 7a8762553cdc..012e1a4016fe 100644
--- a/drivers/net/wireless/wl1251/main.c
+++ b/drivers/net/wireless/wl1251/main.c
@@ -52,14 +52,14 @@ void wl1251_disable_interrupts(struct wl1251 *wl)
         wl->if_ops->disable_irq(wl);
 }
 
-static void wl1251_power_off(struct wl1251 *wl)
+static int wl1251_power_off(struct wl1251 *wl)
 {
-        wl->set_power(false);
+        return wl->if_ops->power(wl, false);
 }
 
-static void wl1251_power_on(struct wl1251 *wl)
+static int wl1251_power_on(struct wl1251 *wl)
 {
-        wl->set_power(true);
+        return wl->if_ops->power(wl, true);
 }
 
 static int wl1251_fetch_firmware(struct wl1251 *wl)
@@ -152,9 +152,12 @@ static void wl1251_fw_wakeup(struct wl1251 *wl)
 
 static int wl1251_chip_wakeup(struct wl1251 *wl)
 {
-        int ret = 0;
+        int ret;
+
+        ret = wl1251_power_on(wl);
+        if (ret < 0)
+                return ret;
 
-        wl1251_power_on(wl);
         msleep(WL1251_POWER_ON_SLEEP);
         wl->if_ops->reset(wl);
 
diff --git a/drivers/net/wireless/wl1251/sdio.c b/drivers/net/wireless/wl1251/sdio.c
index 74ba9ced5393..d550b5e68d3c 100644
--- a/drivers/net/wireless/wl1251/sdio.c
+++ b/drivers/net/wireless/wl1251/sdio.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/wl12xx.h>
 #include <linux/irq.h>
+#include <linux/pm_runtime.h>
 
 #include "wl1251.h"
 
@@ -42,8 +43,6 @@ struct wl1251_sdio {
         u32 elp_val;
 };
 
-static struct wl12xx_platform_data *wl12xx_board_data;
-
 static struct sdio_func *wl_to_func(struct wl1251 *wl)
 {
         struct wl1251_sdio *wl_sdio = wl->if_priv;
@@ -171,8 +170,42 @@ static void wl1251_disable_line_irq(struct wl1251 *wl)
         return disable_irq(wl->irq);
 }
 
-static void wl1251_sdio_set_power(bool enable)
+static int wl1251_sdio_set_power(struct wl1251 *wl, bool enable)
 {
+        struct sdio_func *func = wl_to_func(wl);
+        int ret;
+
+        if (enable) {
+                /*
+                 * Power is controlled by runtime PM, but we still call board
+                 * callback in case it wants to do any additional setup,
+                 * for example enabling clock buffer for the module.
+                 */
+                if (wl->set_power)
+                        wl->set_power(true);
+
+                ret = pm_runtime_get_sync(&func->dev);
+                if (ret < 0)
+                        goto out;
+
+                sdio_claim_host(func);
+                sdio_enable_func(func);
+                sdio_release_host(func);
+        } else {
+                sdio_claim_host(func);
+                sdio_disable_func(func);
+                sdio_release_host(func);
+
+                ret = pm_runtime_put_sync(&func->dev);
+                if (ret < 0)
+                        goto out;
+
+                if (wl->set_power)
+                        wl->set_power(false);
+        }
+
+out:
+        return ret;
 }
 
 static struct wl1251_if_operations wl1251_sdio_ops = {
@@ -181,30 +214,7 @@ static struct wl1251_if_operations wl1251_sdio_ops = {
         .write_elp = wl1251_sdio_write_elp,
         .read_elp = wl1251_sdio_read_elp,
         .reset = wl1251_sdio_reset,
-};
-
-static int wl1251_platform_probe(struct platform_device *pdev)
-{
-        if (pdev->id != -1) {
-                wl1251_error("can only handle single device");
-                return -ENODEV;
-        }
-
-        wl12xx_board_data = pdev->dev.platform_data;
-        return 0;
-}
-
-/*
- * Dummy platform_driver for passing platform_data to this driver,
- * until we have a way to pass this through SDIO subsystem or
- * some other way.
- */
-static struct platform_driver wl1251_platform_driver = {
-        .driver = {
-                .name   = "wl1251_data",
-                .owner  = THIS_MODULE,
-        },
-        .probe  = wl1251_platform_probe,
+        .power = wl1251_sdio_set_power,
 };
 
 static int wl1251_sdio_probe(struct sdio_func *func,
@@ -214,6 +224,7 @@ static int wl1251_sdio_probe(struct sdio_func *func,
         struct wl1251 *wl;
         struct ieee80211_hw *hw;
         struct wl1251_sdio *wl_sdio;
+        const struct wl12xx_platform_data *wl12xx_board_data;
 
         hw = wl1251_alloc_hw();
         if (IS_ERR(hw))
@@ -239,9 +250,9 @@ static int wl1251_sdio_probe(struct sdio_func *func,
         wl_sdio->func = func;
         wl->if_priv = wl_sdio;
         wl->if_ops = &wl1251_sdio_ops;
-        wl->set_power = wl1251_sdio_set_power;
 
-        if (wl12xx_board_data != NULL) {
+        wl12xx_board_data = wl12xx_get_platform_data();
+        if (!IS_ERR(wl12xx_board_data)) {
                 wl->set_power = wl12xx_board_data->set_power;
                 wl->irq = wl12xx_board_data->irq;
                 wl->use_eeprom = wl12xx_board_data->use_eeprom;
@@ -273,6 +284,10 @@ static int wl1251_sdio_probe(struct sdio_func *func,
                 goto out_free_irq;
 
         sdio_set_drvdata(func, wl);
+
+        /* Tell PM core that we don't need the card to be powered now */
+        pm_runtime_put_noidle(&func->dev);
+
         return ret;
 
 out_free_irq:
@@ -294,6 +309,9 @@ static void __devexit wl1251_sdio_remove(struct sdio_func *func)
         struct wl1251 *wl = sdio_get_drvdata(func);
         struct wl1251_sdio *wl_sdio = wl->if_priv;
 
+        /* Undo decrement done above in wl1251_probe */
+        pm_runtime_get_noresume(&func->dev);
+
         if (wl->irq)
                 free_irq(wl->irq, wl);
         kfree(wl_sdio);
@@ -305,23 +323,37 @@ static void __devexit wl1251_sdio_remove(struct sdio_func *func)
         sdio_release_host(func);
 }
 
+static int wl1251_suspend(struct device *dev)
+{
+        /*
+         * Tell MMC/SDIO core it's OK to power down the card
+         * (if it isn't already), but not to remove it completely.
+         */
+        return 0;
+}
+
+static int wl1251_resume(struct device *dev)
+{
+        return 0;
+}
+
+static const struct dev_pm_ops wl1251_sdio_pm_ops = {
+        .suspend        = wl1251_suspend,
+        .resume         = wl1251_resume,
+};
+
 static struct sdio_driver wl1251_sdio_driver = {
         .name           = "wl1251_sdio",
         .id_table       = wl1251_devices,
         .probe          = wl1251_sdio_probe,
         .remove         = __devexit_p(wl1251_sdio_remove),
+        .drv.pm         = &wl1251_sdio_pm_ops,
 };
 
 static int __init wl1251_sdio_init(void)
 {
         int err;
 
-        err = platform_driver_register(&wl1251_platform_driver);
-        if (err) {
-                wl1251_error("failed to register platform driver: %d", err);
-                return err;
-        }
-
         err = sdio_register_driver(&wl1251_sdio_driver);
         if (err)
                 wl1251_error("failed to register sdio driver: %d", err);
@@ -331,7 +363,6 @@ static int __init wl1251_sdio_init(void)
 static void __exit wl1251_sdio_exit(void)
 {
         sdio_unregister_driver(&wl1251_sdio_driver);
-        platform_driver_unregister(&wl1251_platform_driver);
         wl1251_notice("unloaded");
 }
 
diff --git a/drivers/net/wireless/wl1251/spi.c b/drivers/net/wireless/wl1251/spi.c
index 88fa8e69d0d1..ac872b38960f 100644
--- a/drivers/net/wireless/wl1251/spi.c
+++ b/drivers/net/wireless/wl1251/spi.c
@@ -215,12 +215,21 @@ static void wl1251_spi_disable_irq(struct wl1251 *wl)
         return disable_irq(wl->irq);
 }
 
+static int wl1251_spi_set_power(struct wl1251 *wl, bool enable)
+{
+        if (wl->set_power)
+                wl->set_power(enable);
+
+        return 0;
+}
+
 static const struct wl1251_if_operations wl1251_spi_ops = {
         .read = wl1251_spi_read,
         .write = wl1251_spi_write,
         .reset = wl1251_spi_reset_wake,
         .enable_irq = wl1251_spi_enable_irq,
         .disable_irq = wl1251_spi_disable_irq,
+        .power = wl1251_spi_set_power,
 };
 
 static int __devinit wl1251_spi_probe(struct spi_device *spi)
diff --git a/drivers/net/wireless/wl1251/wl1251.h b/drivers/net/wireless/wl1251/wl1251.h
index 47d2653baccd..c0ce2c8b43b8 100644
--- a/drivers/net/wireless/wl1251/wl1251.h
+++ b/drivers/net/wireless/wl1251/wl1251.h
@@ -256,6 +256,7 @@ struct wl1251_if_operations {
         void (*write)(struct wl1251 *wl, int addr, void *buf, size_t len);
         void (*read_elp)(struct wl1251 *wl, int addr, u32 *val);
         void (*write_elp)(struct wl1251 *wl, int addr, u32 val);
+        int  (*power)(struct wl1251 *wl, bool enable);
         void (*reset)(struct wl1251 *wl);
         void (*enable_irq)(struct wl1251 *wl);
         void (*disable_irq)(struct wl1251 *wl);
diff --git a/drivers/net/wireless/wl12xx/Kconfig b/drivers/net/wireless/wl12xx/Kconfig
index b447559f1db5..0e65bce457d6 100644
--- a/drivers/net/wireless/wl12xx/Kconfig
+++ b/drivers/net/wireless/wl12xx/Kconfig
@@ -1,46 +1,68 @@
-menuconfig WL12XX
+menuconfig WL12XX_MENU
         tristate "TI wl12xx driver support"
         depends on MAC80211 && EXPERIMENTAL
         ---help---
-          This will enable TI wl12xx driver support. The drivers make
-          use of the mac80211 stack.
+          This will enable TI wl12xx driver support for the following chips:
+          wl1271 and wl1273.
+          The drivers make use of the mac80211 stack.
 
-config WL1271
-        tristate "TI wl1271 support"
-        depends on WL12XX && GENERIC_HARDIRQS
+config WL12XX
+        tristate "TI wl12xx support"
+        depends on WL12XX_MENU && GENERIC_HARDIRQS
         depends on INET
         select FW_LOADER
         select CRC7
         ---help---
-          This module adds support for wireless adapters based on the
-          TI wl1271 chipset.
+          This module adds support for wireless adapters based on TI wl1271 and
+          TI wl1273 chipsets. This module does *not* include support for wl1251.
+          For wl1251 support, use the separate homonymous driver instead.
 
-          If you choose to build a module, it'll be called wl1271. Say N if
+          If you choose to build a module, it will be called wl12xx. Say N if
           unsure.
 
-config WL1271_SPI
-        tristate "TI wl1271 SPI support"
-        depends on WL1271 && SPI_MASTER
+config WL12XX_HT
+        bool "TI wl12xx 802.11 HT support (EXPERIMENTAL)"
+        depends on WL12XX && EXPERIMENTAL
+        default n
+        ---help---
+          This will enable 802.11 HT support in the wl12xx module.
+
+          That configuration is temporary due to the code incomplete and
+          still in testing process.
+
+config WL12XX_SPI
+        tristate "TI wl12xx SPI support"
+        depends on WL12XX && SPI_MASTER
         ---help---
           This module adds support for the SPI interface of adapters using
-          TI wl1271 chipset.  Select this if your platform is using
+          TI wl12xx chipsets.  Select this if your platform is using
           the SPI bus.
 
-          If you choose to build a module, it'll be called wl1251_spi.
+          If you choose to build a module, it'll be called wl12xx_spi.
           Say N if unsure.
 
-config WL1271_SDIO
-        tristate "TI wl1271 SDIO support"
-        depends on WL1271 && MMC
+config WL12XX_SDIO
+        tristate "TI wl12xx SDIO support"
+        depends on WL12XX && MMC
         ---help---
           This module adds support for the SDIO interface of adapters using
-          TI wl1271 chipset.  Select this if your platform is using
+          TI wl12xx chipsets.  Select this if your platform is using
           the SDIO bus.
 
-          If you choose to build a module, it'll be called
-          wl1271_sdio. Say N if unsure.
+          If you choose to build a module, it'll be called wl12xx_sdio.
+          Say N if unsure.
+
+config WL12XX_SDIO_TEST
+        tristate "TI wl12xx SDIO testing support"
+        depends on WL12XX && MMC
+        default n
+        ---help---
+          This module adds support for the SDIO bus testing with the
+          TI wl12xx chipsets.  You probably don't want this unless you are
+          testing a new hardware platform.  Select this if you want to test the
+          SDIO bus which is connected to the wl12xx chip.
 
 config WL12XX_PLATFORM_DATA
         bool
-        depends on WL1271_SDIO != n
+        depends on WL12XX_SDIO != n || WL1251_SDIO != n
         default y
diff --git a/drivers/net/wireless/wl12xx/Makefile b/drivers/net/wireless/wl12xx/Makefile
index 3a807444b2af..521c0414e52e 100644
--- a/drivers/net/wireless/wl12xx/Makefile
+++ b/drivers/net/wireless/wl12xx/Makefile
@@ -1,12 +1,16 @@
-wl1271-objs             = wl1271_main.o  wl1271_cmd.o wl1271_io.o \
-                          wl1271_event.o wl1271_tx.o  wl1271_rx.o   \
-                          wl1271_ps.o    wl1271_acx.o wl1271_boot.o \
-                          wl1271_init.o  wl1271_debugfs.o wl1271_scan.o
-
-wl1271-$(CONFIG_NL80211_TESTMODE)       += wl1271_testmode.o
-obj-$(CONFIG_WL1271)    += wl1271.o
-obj-$(CONFIG_WL1271_SPI)        += wl1271_spi.o
-obj-$(CONFIG_WL1271_SDIO)       += wl1271_sdio.o
+wl12xx-objs             = main.o cmd.o io.o event.o tx.o rx.o ps.o acx.o \
+                          boot.o init.o debugfs.o scan.o
+
+wl12xx_spi-objs = spi.o
+wl12xx_sdio-objs        = sdio.o
+wl12xx_sdio_test-objs = sdio_test.o
+
+wl12xx-$(CONFIG_NL80211_TESTMODE)       += testmode.o
+obj-$(CONFIG_WL12XX)                    += wl12xx.o
+obj-$(CONFIG_WL12XX_SPI)                += wl12xx_spi.o
+obj-$(CONFIG_WL12XX_SDIO)               += wl12xx_sdio.o
+
+obj-$(CONFIG_WL12XX_SDIO_TEST)  += wl12xx_sdio_test.o
 
 # small builtin driver bit
 obj-$(CONFIG_WL12XX_PLATFORM_DATA)      += wl12xx_platform_data.o
diff --git a/drivers/net/wireless/wl12xx/wl1271_acx.c b/drivers/net/wireless/wl12xx/acx.c
index 618993405262..cc4068d2b4a8 100644
--- a/drivers/net/wireless/wl12xx/wl1271_acx.c
+++ b/drivers/net/wireless/wl12xx/acx.c
@@ -21,7 +21,7 @@
  *
  */
 
-#include "wl1271_acx.h"
+#include "acx.h"
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -29,10 +29,10 @@
 #include <linux/spi/spi.h>
 #include <linux/slab.h>
 
-#include "wl1271.h"
+#include "wl12xx.h"
 #include "wl12xx_80211.h"
-#include "wl1271_reg.h"
-#include "wl1271_ps.h"
+#include "reg.h"
+#include "ps.h"
 
 int wl1271_acx_wake_up_conditions(struct wl1271 *wl)
 {
@@ -862,7 +862,7 @@ out:
         return ret;
 }
 
-int wl1271_acx_frag_threshold(struct wl1271 *wl)
+int wl1271_acx_frag_threshold(struct wl1271 *wl, u16 frag_threshold)
 {
         struct acx_frag_threshold *acx;
         int ret = 0;
@@ -876,7 +876,7 @@ int wl1271_acx_frag_threshold(struct wl1271 *wl)
                 goto out;
         }
 
-        acx->frag_threshold = cpu_to_le16(wl->conf.tx.frag_threshold);
+        acx->frag_threshold = cpu_to_le16(frag_threshold);
         ret = wl1271_cmd_configure(wl, ACX_FRAG_CFG, acx, sizeof(*acx));
         if (ret < 0) {
                 wl1271_warning("Setting of frag threshold failed: %d", ret);
@@ -1041,7 +1041,7 @@ out:
         return ret;
 }
 
-int wl1271_acx_arp_ip_filter(struct wl1271 *wl, bool enable, __be32 address)
+int wl1271_acx_arp_ip_filter(struct wl1271 *wl, u8 enable, __be32 address)
 {
         struct wl1271_acx_arp_filter *acx;
         int ret;
@@ -1057,7 +1057,7 @@ int wl1271_acx_arp_ip_filter(struct wl1271 *wl, bool enable, __be32 address)
         acx->version = ACX_IPV4_VERSION;
         acx->enable = enable;
 
-        if (enable == true)
+        if (enable)
                 memcpy(acx->address, &address, ACX_IPV4_ADDR_SIZE);
 
         ret = wl1271_cmd_configure(wl, ACX_ARP_IP_FILTER,
@@ -1226,6 +1226,89 @@ out:
         return ret;
 }
 
+int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
+                                    struct ieee80211_sta_ht_cap *ht_cap,
+                                    bool allow_ht_operation)
+{
+        struct wl1271_acx_ht_capabilities *acx;
+        u8 mac_address[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+        int ret = 0;
+
+        wl1271_debug(DEBUG_ACX, "acx ht capabilities setting");
+
+        acx = kzalloc(sizeof(*acx), GFP_KERNEL);
+        if (!acx) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        /* Allow HT Operation ? */
+        if (allow_ht_operation) {
+                acx->ht_capabilites =
+                        WL1271_ACX_FW_CAP_HT_OPERATION;
+                if (ht_cap->cap & IEEE80211_HT_CAP_GRN_FLD)
+                        acx->ht_capabilites |=
+                                WL1271_ACX_FW_CAP_GREENFIELD_FRAME_FORMAT;
+                if (ht_cap->cap & IEEE80211_HT_CAP_SGI_20)
+                        acx->ht_capabilites |=
+                                WL1271_ACX_FW_CAP_SHORT_GI_FOR_20MHZ_PACKETS;
+                if (ht_cap->cap & IEEE80211_HT_CAP_LSIG_TXOP_PROT)
+                        acx->ht_capabilites |=
+                                WL1271_ACX_FW_CAP_LSIG_TXOP_PROTECTION;
+
+                /* get data from A-MPDU parameters field */
+                acx->ampdu_max_length = ht_cap->ampdu_factor;
+                acx->ampdu_min_spacing = ht_cap->ampdu_density;
+
+                memcpy(acx->mac_address, mac_address, ETH_ALEN);
+        } else { /* HT operations are not allowed */
+                acx->ht_capabilites = 0;
+        }
+
+        ret = wl1271_cmd_configure(wl, ACX_PEER_HT_CAP, acx, sizeof(*acx));
+        if (ret < 0) {
+                wl1271_warning("acx ht capabilities setting failed: %d", ret);
+                goto out;
+        }
+
+out:
+        kfree(acx);
+        return ret;
+}
+
+int wl1271_acx_set_ht_information(struct wl1271 *wl,
+                                   u16 ht_operation_mode)
+{
+        struct wl1271_acx_ht_information *acx;
+        int ret = 0;
+
+        wl1271_debug(DEBUG_ACX, "acx ht information setting");
+
+        acx = kzalloc(sizeof(*acx), GFP_KERNEL);
+        if (!acx) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        acx->ht_protection =
+                (u8)(ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION);
+        acx->rifs_mode = 0;
+        acx->gf_protection = 0;
+        acx->ht_tx_burst_limit = 0;
+        acx->dual_cts_protection = 0;
+
+        ret = wl1271_cmd_configure(wl, ACX_HT_BSS_OPERATION, acx, sizeof(*acx));
+
+        if (ret < 0) {
+                wl1271_warning("acx ht information setting failed: %d", ret);
+                goto out;
+        }
+
+out:
+        kfree(acx);
+        return ret;
+}
+
 int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime)
 {
         struct wl1271_acx_fw_tsf_information *tsf_info;
diff --git a/drivers/net/wireless/wl12xx/wl1271_acx.h b/drivers/net/wireless/wl12xx/acx.h
index 0ce845fb6629..7bd8e4db4a71 100644
--- a/drivers/net/wireless/wl12xx/wl1271_acx.h
+++ b/drivers/net/wireless/wl12xx/acx.h
@@ -22,11 +22,11 @@
  *
  */
 
-#ifndef __WL1271_ACX_H__
-#define __WL1271_ACX_H__
+#ifndef __ACX_H__
+#define __ACX_H__
 
-#include "wl1271.h"
-#include "wl1271_cmd.h"
+#include "wl12xx.h"
+#include "cmd.h"
 
 /*************************************************************************
 
@@ -61,7 +61,8 @@
                                             WL1271_ACX_INTR_HW_AVAILABLE  | \
                                             WL1271_ACX_INTR_DATA)
 
-#define WL1271_INTR_MASK                   (WL1271_ACX_INTR_EVENT_A      | \
+#define WL1271_INTR_MASK                   (WL1271_ACX_INTR_WATCHDOG     | \
+                                            WL1271_ACX_INTR_EVENT_A      | \
                                             WL1271_ACX_INTR_EVENT_B      | \
                                             WL1271_ACX_INTR_HW_AVAILABLE | \
                                             WL1271_ACX_INTR_DATA)
@@ -867,10 +868,15 @@ struct wl1271_acx_bet_enable {
 #define ACX_IPV4_VERSION 4
 #define ACX_IPV6_VERSION 6
 #define ACX_IPV4_ADDR_SIZE 4
+
+/* bitmap of enabled arp_filter features */
+#define ACX_ARP_FILTER_ARP_FILTERING    BIT(0)
+#define ACX_ARP_FILTER_AUTO_ARP         BIT(1)
+
 struct wl1271_acx_arp_filter {
         struct acx_header header;
         u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
-        u8 enable;          /* 1 to enable ARP filtering, 0 to disable */
+        u8 enable;          /* bitmap of enabled ARP filtering features */
         u8 padding[2];
         u8 address[16];     /* The configured device IP address - all ARP
                                requests directed to this IP address will pass
@@ -964,6 +970,87 @@ struct wl1271_acx_rssi_snr_avg_weights {
         u8 snr_data;
 };
 
+/*
+ * ACX_PEER_HT_CAP
+ * Configure HT capabilities - declare the capabilities of the peer
+ * we are connected to.
+ */
+struct wl1271_acx_ht_capabilities {
+        struct acx_header header;
+
+        /*
+         * bit 0 - Allow HT Operation
+         * bit 1 - Allow Greenfield format in TX
+         * bit 2 - Allow Short GI in TX
+         * bit 3 - Allow L-SIG TXOP Protection in TX
+         * bit 4 - Allow HT Control fields in TX.
+         *         Note, driver will still leave space for HT control in packets
+         *         regardless of the value of this field. FW will be responsible
+         *         to drop the HT field from any frame when this Bit set to 0.
+         * bit 5 - Allow RD initiation in TXOP. FW is allowed to initate RD.
+         *         Exact policy setting for this feature is TBD.
+         *         Note, this bit can only be set to 1 if bit 3 is set to 1.
+         */
+        __le32 ht_capabilites;
+
+        /*
+         * Indicates to which peer these capabilities apply.
+         * For infrastructure use ff:ff:ff:ff:ff:ff that indicates relevance
+         * for all peers.
+         * Only valid for IBSS/DLS operation.
+         */
+        u8 mac_address[ETH_ALEN];
+
+        /*
+         * This the maximum A-MPDU length supported by the AP. The FW may not
+         * exceed this length when sending A-MPDUs
+         */
+        u8 ampdu_max_length;
+
+        /* This is the minimal spacing required when sending A-MPDUs to the AP*/
+        u8 ampdu_min_spacing;
+} __packed;
+
+/* HT Capabilites Fw Bit Mask Mapping */
+#define WL1271_ACX_FW_CAP_HT_OPERATION                 BIT(0)
+#define WL1271_ACX_FW_CAP_GREENFIELD_FRAME_FORMAT      BIT(1)
+#define WL1271_ACX_FW_CAP_SHORT_GI_FOR_20MHZ_PACKETS   BIT(2)
+#define WL1271_ACX_FW_CAP_LSIG_TXOP_PROTECTION         BIT(3)
+#define WL1271_ACX_FW_CAP_HT_CONTROL_FIELDS            BIT(4)
+#define WL1271_ACX_FW_CAP_RD_INITIATION                BIT(5)
+
+
+/*
+ * ACX_HT_BSS_OPERATION
+ * Configure HT capabilities - AP rules for behavior in the BSS.
+ */
+struct wl1271_acx_ht_information {
+        struct acx_header header;
+
+        /* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
+        u8 rifs_mode;
+
+        /* Values: 0 - 3 like in spec */
+        u8 ht_protection;
+
+        /* Values: 0 - GF protection not required, 1 - GF protection required */
+        u8 gf_protection;
+
+        /*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
+        u8 ht_tx_burst_limit;
+
+        /*
+         * Values: 0 - Dual CTS protection not required,
+         *         1 - Dual CTS Protection required
+         * Note: When this value is set to 1 FW will protect all TXOP with RTS
+         * frame and will not use CTS-to-self regardless of the value of the
+         * ACX_CTS_PROTECTION information element
+         */
+        u8 dual_cts_protection;
+
+        u8 padding[3];
+} __packed;
+
 struct wl1271_acx_fw_tsf_information {
         struct acx_header header;
 
@@ -1079,20 +1166,25 @@ int wl1271_acx_ac_cfg(struct wl1271 *wl, u8 ac, u8 cw_min, u16 cw_max,
 int wl1271_acx_tid_cfg(struct wl1271 *wl, u8 queue_id, u8 channel_type,
                        u8 tsid, u8 ps_scheme, u8 ack_policy,
                        u32 apsd_conf0, u32 apsd_conf1);
-int wl1271_acx_frag_threshold(struct wl1271 *wl);
+int wl1271_acx_frag_threshold(struct wl1271 *wl, u16 frag_threshold);
 int wl1271_acx_tx_config_options(struct wl1271 *wl);
 int wl1271_acx_mem_cfg(struct wl1271 *wl);
 int wl1271_acx_init_mem_config(struct wl1271 *wl);
 int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
 int wl1271_acx_smart_reflex(struct wl1271 *wl);
 int wl1271_acx_bet_enable(struct wl1271 *wl, bool enable);
-int wl1271_acx_arp_ip_filter(struct wl1271 *wl, bool enable, __be32 address);
+int wl1271_acx_arp_ip_filter(struct wl1271 *wl, u8 enable, __be32 address);
 int wl1271_acx_pm_config(struct wl1271 *wl);
 int wl1271_acx_keep_alive_mode(struct wl1271 *wl, bool enable);
 int wl1271_acx_keep_alive_config(struct wl1271 *wl, u8 index, u8 tpl_valid);
 int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, bool enable,
                                 s16 thold, u8 hyst);
 int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl);
+int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
+                                    struct ieee80211_sta_ht_cap *ht_cap,
+                                    bool allow_ht_operation);
+int wl1271_acx_set_ht_information(struct wl1271 *wl,
+                                   u16 ht_operation_mode);
 int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
 
 #endif /* __WL1271_ACX_H__ */
diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.c b/drivers/net/wireless/wl12xx/boot.c
index b91021242098..4df04f84d7f1 100644
--- a/drivers/net/wireless/wl12xx/wl1271_boot.c
+++ b/drivers/net/wireless/wl12xx/boot.c
@@ -21,14 +21,13 @@
  *
  */
 
-#include <linux/gpio.h>
 #include <linux/slab.h>
 
-#include "wl1271_acx.h"
-#include "wl1271_reg.h"
-#include "wl1271_boot.h"
-#include "wl1271_io.h"
-#include "wl1271_event.h"
+#include "acx.h"
+#include "reg.h"
+#include "boot.h"
+#include "io.h"
+#include "event.h"
 
 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
         [PART_DOWN] = {
@@ -467,24 +466,24 @@ static void wl1271_boot_hw_version(struct wl1271 *wl)
         wl->hw_pg_ver = (s8)fuse;
 }
 
-int wl1271_boot(struct wl1271 *wl)
+/* uploads NVS and firmware */
+int wl1271_load_firmware(struct wl1271 *wl)
 {
         int ret = 0;
         u32 tmp, clk, pause;
-        int ref_clock = wl->ref_clock;
 
         wl1271_boot_hw_version(wl);
 
-        if (ref_clock == 0 || ref_clock == 2 || ref_clock == 4)
+        if (wl->ref_clock == 0 || wl->ref_clock == 2 || wl->ref_clock == 4)
                 /* ref clk: 19.2/38.4/38.4-XTAL */
                 clk = 0x3;
-        else if (ref_clock == 1 || ref_clock == 3)
+        else if (wl->ref_clock == 1 || wl->ref_clock == 3)
                 /* ref clk: 26/52 */
                 clk = 0x5;
         else
                 return -EINVAL;
 
-        if (ref_clock != 0) {
+        if (wl->ref_clock != 0) {
                 u16 val;
                 /* Set clock type (open drain) */
                 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
@@ -529,8 +528,7 @@ int wl1271_boot(struct wl1271 *wl)
 
         wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
 
-        /* 2 */
-        clk |= (ref_clock << 1) << 4;
+        clk |= (wl->ref_clock << 1) << 4;
         wl1271_write32(wl, DRPW_SCRATCH_START, clk);
 
         wl1271_set_partition(wl, &part_table[PART_WORK]);
@@ -574,6 +572,20 @@ int wl1271_boot(struct wl1271 *wl)
         if (ret < 0)
                 goto out;
 
+out:
+        return ret;
+}
+EXPORT_SYMBOL_GPL(wl1271_load_firmware);
+
+int wl1271_boot(struct wl1271 *wl)
+{
+        int ret;
+
+        /* upload NVS and firmware */
+        ret = wl1271_load_firmware(wl);
+        if (ret)
+                return ret;
+
         /* 10.5 start firmware */
         ret = wl1271_boot_run_firmware(wl);
         if (ret < 0)
diff --git a/drivers/net/wireless/wl12xx/wl1271_boot.h b/drivers/net/wireless/wl12xx/boot.h
index f73b0b15a280..d67dcffa31eb 100644
--- a/drivers/net/wireless/wl12xx/wl1271_boot.h
+++ b/drivers/net/wireless/wl12xx/boot.h
@@ -24,9 +24,10 @@
 #ifndef __BOOT_H__
 #define __BOOT_H__
 
-#include "wl1271.h"
+#include "wl12xx.h"
 
 int wl1271_boot(struct wl1271 *wl);
+int wl1271_load_firmware(struct wl1271 *wl);
 
 #define WL1271_NO_SUBBANDS 8
 #define WL1271_NO_POWER_LEVELS 4
diff --git a/drivers/net/wireless/wl12xx/wl1271_cmd.c b/drivers/net/wireless/wl12xx/cmd.c
index 5d3e8485ea4e..0106628aa5a2 100644
--- a/drivers/net/wireless/wl12xx/wl1271_cmd.c
+++ b/drivers/net/wireless/wl12xx/cmd.c
@@ -29,13 +29,13 @@
 #include <linux/ieee80211.h>
 #include <linux/slab.h>
 
-#include "wl1271.h"
-#include "wl1271_reg.h"
-#include "wl1271_io.h"
-#include "wl1271_acx.h"
+#include "wl12xx.h"
+#include "reg.h"
+#include "io.h"
+#include "acx.h"
 #include "wl12xx_80211.h"
-#include "wl1271_cmd.h"
-#include "wl1271_event.h"
+#include "cmd.h"
+#include "event.h"
 
 #define WL1271_CMD_FAST_POLL_COUNT       50
 
@@ -611,6 +611,75 @@ out:
         return ret;
 }
 
+struct sk_buff *wl1271_cmd_build_ap_probe_req(struct wl1271 *wl,
+                                              struct sk_buff *skb)
+{
+        int ret;
+
+        if (!skb)
+                skb = ieee80211_ap_probereq_get(wl->hw, wl->vif);
+        if (!skb)
+                goto out;
+
+        wl1271_dump(DEBUG_SCAN, "AP PROBE REQ: ", skb->data, skb->len);
+
+        if (wl->band == IEEE80211_BAND_2GHZ)
+                ret = wl1271_cmd_template_set(wl, CMD_TEMPL_CFG_PROBE_REQ_2_4,
+                                              skb->data, skb->len, 0,
+                                              wl->conf.tx.basic_rate);
+        else
+                ret = wl1271_cmd_template_set(wl, CMD_TEMPL_CFG_PROBE_REQ_5,
+                                              skb->data, skb->len, 0,
+                                              wl->conf.tx.basic_rate_5);
+
+        if (ret < 0)
+                wl1271_error("Unable to set ap probe request template.");
+
+out:
+        return skb;
+}
+
+int wl1271_cmd_build_arp_rsp(struct wl1271 *wl, __be32 ip_addr)
+{
+        int ret;
+        struct wl12xx_arp_rsp_template tmpl;
+        struct ieee80211_hdr_3addr *hdr;
+        struct arphdr *arp_hdr;
+
+        memset(&tmpl, 0, sizeof(tmpl));
+
+        /* mac80211 header */
+        hdr = &tmpl.hdr;
+        hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_DATA |
+                                         IEEE80211_STYPE_DATA |
+                                         IEEE80211_FCTL_TODS);
+        memcpy(hdr->addr1, wl->vif->bss_conf.bssid, ETH_ALEN);
+        memcpy(hdr->addr2, wl->vif->addr, ETH_ALEN);
+        memset(hdr->addr3, 0xff, ETH_ALEN);
+
+        /* llc layer */
+        memcpy(tmpl.llc_hdr, rfc1042_header, sizeof(rfc1042_header));
+        tmpl.llc_type = htons(ETH_P_ARP);
+
+        /* arp header */
+        arp_hdr = &tmpl.arp_hdr;
+        arp_hdr->ar_hrd = htons(ARPHRD_ETHER);
+        arp_hdr->ar_pro = htons(ETH_P_IP);
+        arp_hdr->ar_hln = ETH_ALEN;
+        arp_hdr->ar_pln = 4;
+        arp_hdr->ar_op = htons(ARPOP_REPLY);
+
+        /* arp payload */
+        memcpy(tmpl.sender_hw, wl->vif->addr, ETH_ALEN);
+        tmpl.sender_ip = ip_addr;
+
+        ret = wl1271_cmd_template_set(wl, CMD_TEMPL_ARP_RSP,
+                                      &tmpl, sizeof(tmpl), 0,
+                                      wl->basic_rate);
+
+        return ret;
+}
+
 int wl1271_build_qos_null_data(struct wl1271 *wl)
 {
         struct ieee80211_qos_hdr template;
diff --git a/drivers/net/wireless/wl12xx/wl1271_cmd.h b/drivers/net/wireless/wl12xx/cmd.h
index a0caf4fc37b1..2a1d9db7ceb8 100644
--- a/drivers/net/wireless/wl12xx/wl1271_cmd.h
+++ b/drivers/net/wireless/wl12xx/cmd.h
@@ -22,10 +22,10 @@
  *
  */
 
-#ifndef __WL1271_CMD_H__
-#define __WL1271_CMD_H__
+#ifndef __CMD_H__
+#define __CMD_H__
 
-#include "wl1271.h"
+#include "wl12xx.h"
 
 struct acx_header;
 
@@ -49,6 +49,9 @@ int wl1271_cmd_build_ps_poll(struct wl1271 *wl, u16 aid);
 int wl1271_cmd_build_probe_req(struct wl1271 *wl,
                                const u8 *ssid, size_t ssid_len,
                                const u8 *ie, size_t ie_len, u8 band);
+struct sk_buff *wl1271_cmd_build_ap_probe_req(struct wl1271 *wl,
+                                              struct sk_buff *skb);
+int wl1271_cmd_build_arp_rsp(struct wl1271 *wl, __be32 ip_addr);
 int wl1271_build_qos_null_data(struct wl1271 *wl);
 int wl1271_cmd_build_klv_null_data(struct wl1271 *wl);
 int wl1271_cmd_set_default_wep_key(struct wl1271 *wl, u8 id);
@@ -122,6 +125,7 @@ enum cmd_templ {
         CMD_TEMPL_CTS,           /*
                                   * For CTS-to-self (FastCTS) mechanism
                                   * for BT/WLAN coexistence (SoftGemini). */
+        CMD_TEMPL_ARP_RSP,
         CMD_TEMPL_MAX = 0xff
 };
 
@@ -327,9 +331,6 @@ enum wl1271_channel_tune_bands {
 
 #define WL1271_PD_REFERENCE_POINT_BAND_B_G  0
 
-#define TEST_CMD_P2G_CAL                    0x02
-#define TEST_CMD_CHANNEL_TUNE               0x0d
-#define TEST_CMD_UPDATE_PD_REFERENCE_POINT  0x1d
 #define TEST_CMD_INI_FILE_RADIO_PARAM       0x19
 #define TEST_CMD_INI_FILE_GENERAL_PARAM     0x1E
 #define TEST_CMD_INI_FILE_RF_EXTENDED_PARAM 0x26
@@ -375,51 +376,6 @@ struct wl1271_ext_radio_parms_cmd {
         u8 padding[3];
 } __packed;
 
-struct wl1271_cmd_cal_channel_tune {
-        struct wl1271_cmd_header header;
-
-        struct wl1271_cmd_test_header test;
-
-        u8 band;
-        u8 channel;
-
-        __le16 radio_status;
-} __packed;
-
-struct wl1271_cmd_cal_update_ref_point {
-        struct wl1271_cmd_header header;
-
-        struct wl1271_cmd_test_header test;
-
-        __le32 ref_power;
-        __le32 ref_detector;
-        u8  sub_band;
-        u8  padding[3];
-} __packed;
-
-#define MAX_TLV_LENGTH         400
-#define MAX_NVS_VERSION_LENGTH 12
-
-#define WL1271_CAL_P2G_BAND_B_G BIT(0)
-
-struct wl1271_cmd_cal_p2g {
-        struct wl1271_cmd_header header;
-
-        struct wl1271_cmd_test_header test;
-
-        __le16 len;
-        u8  buf[MAX_TLV_LENGTH];
-        u8  type;
-        u8  padding;
-
-        __le16 radio_status;
-        u8  nvs_version[MAX_NVS_VERSION_LENGTH];
-
-        u8  sub_band_mask;
-        u8  padding2;
-} __packed;
-
-
 /*
  * There are three types of disconnections:
  *
diff --git a/drivers/net/wireless/wl12xx/wl1271_conf.h b/drivers/net/wireless/wl12xx/conf.h
index 5f78a6cb1433..a16b3616e430 100644
--- a/drivers/net/wireless/wl12xx/wl1271_conf.h
+++ b/drivers/net/wireless/wl12xx/conf.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef __WL1271_CONF_H__
-#define __WL1271_CONF_H__
+#ifndef __CONF_H__
+#define __CONF_H__
 
 enum {
         CONF_HW_BIT_RATE_1MBPS   = BIT(0),
diff --git a/drivers/net/wireless/wl12xx/debugfs.c b/drivers/net/wireless/wl12xx/debugfs.c
new file mode 100644
index 000000000000..ec6077760157
--- /dev/null
+++ b/drivers/net/wireless/wl12xx/debugfs.c
@@ -0,0 +1,480 @@
+/*
+ * This file is part of wl1271
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Contact: Luciano Coelho <luciano.coelho@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include "debugfs.h"
+
+#include <linux/skbuff.h>
+#include <linux/slab.h>
+
+#include "wl12xx.h"
+#include "acx.h"
+#include "ps.h"
+#include "io.h"
+
+/* ms */
+#define WL1271_DEBUGFS_STATS_LIFETIME 1000
+
+/* debugfs macros idea from mac80211 */
+#define DEBUGFS_FORMAT_BUFFER_SIZE 100
+static int wl1271_format_buffer(char __user *userbuf, size_t count,
+                                    loff_t *ppos, char *fmt, ...)
+{
+        va_list args;
+        char buf[DEBUGFS_FORMAT_BUFFER_SIZE];
+        int res;
+
+        va_start(args, fmt);
+        res = vscnprintf(buf, sizeof(buf), fmt, args);
+        va_end(args);
+
+        return simple_read_from_buffer(userbuf, count, ppos, buf, res);
+}
+
+#define DEBUGFS_READONLY_FILE(name, fmt, value...)                      \
+static ssize_t name## _read(struct file *file, char __user *userbuf,    \
+                            size_t count, loff_t *ppos)                 \
+{                                                                       \
+        struct wl1271 *wl = file->private_data;                         \
+        return wl1271_format_buffer(userbuf, count, ppos,               \
+                                    fmt "\n", ##value);                 \
+}                                                                       \
+                                                                        \
+static const struct file_operations name## _ops = {                     \
+        .read = name## _read,                                           \
+        .open = wl1271_open_file_generic,                               \
+        .llseek = generic_file_llseek,                                  \
+};
+
+#define DEBUGFS_ADD(name, parent)                                       \
+        entry = debugfs_create_file(#name, 0400, parent,                \
+                                    wl, &name## _ops);                  \
+        if (!entry || IS_ERR(entry))                                    \
+                goto err;                                               \
+
+#define DEBUGFS_FWSTATS_FILE(sub, name, fmt)                            \
+static ssize_t sub## _ ##name## _read(struct file *file,                \
+                                      char __user *userbuf,             \
+                                      size_t count, loff_t *ppos)       \
+{                                                                       \
+        struct wl1271 *wl = file->private_data;                         \
+                                                                        \
+        wl1271_debugfs_update_stats(wl);                                \
+                                                                        \
+        return wl1271_format_buffer(userbuf, count, ppos, fmt "\n",     \
+                                    wl->stats.fw_stats->sub.name);      \
+}                                                                       \
+                                                                        \
+static const struct file_operations sub## _ ##name## _ops = {           \
+        .read = sub## _ ##name## _read,                                 \
+        .open = wl1271_open_file_generic,                               \
+        .llseek = generic_file_llseek,                                  \
+};
+
+#define DEBUGFS_FWSTATS_ADD(sub, name)                          \
+        DEBUGFS_ADD(sub## _ ##name, stats)
+
+static void wl1271_debugfs_update_stats(struct wl1271 *wl)
+{
+        int ret;
+
+        mutex_lock(&wl->mutex);
+
+        ret = wl1271_ps_elp_wakeup(wl, false);
+        if (ret < 0)
+                goto out;
+
+        if (wl->state == WL1271_STATE_ON &&
+            time_after(jiffies, wl->stats.fw_stats_update +
+                       msecs_to_jiffies(WL1271_DEBUGFS_STATS_LIFETIME))) {
+                wl1271_acx_statistics(wl, wl->stats.fw_stats);
+                wl->stats.fw_stats_update = jiffies;
+        }
+
+        wl1271_ps_elp_sleep(wl);
+
+out:
+        mutex_unlock(&wl->mutex);
+}
+
+static int wl1271_open_file_generic(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+DEBUGFS_FWSTATS_FILE(tx, internal_desc_overflow, "%u");
+
+DEBUGFS_FWSTATS_FILE(rx, out_of_mem, "%u");
+DEBUGFS_FWSTATS_FILE(rx, hdr_overflow, "%u");
+DEBUGFS_FWSTATS_FILE(rx, hw_stuck, "%u");
+DEBUGFS_FWSTATS_FILE(rx, dropped, "%u");
+DEBUGFS_FWSTATS_FILE(rx, fcs_err, "%u");
+DEBUGFS_FWSTATS_FILE(rx, xfr_hint_trig, "%u");
+DEBUGFS_FWSTATS_FILE(rx, path_reset, "%u");
+DEBUGFS_FWSTATS_FILE(rx, reset_counter, "%u");
+
+DEBUGFS_FWSTATS_FILE(dma, rx_requested, "%u");
+DEBUGFS_FWSTATS_FILE(dma, rx_errors, "%u");
+DEBUGFS_FWSTATS_FILE(dma, tx_requested, "%u");
+DEBUGFS_FWSTATS_FILE(dma, tx_errors, "%u");
+
+DEBUGFS_FWSTATS_FILE(isr, cmd_cmplt, "%u");
+DEBUGFS_FWSTATS_FILE(isr, fiqs, "%u");
+DEBUGFS_FWSTATS_FILE(isr, rx_headers, "%u");
+DEBUGFS_FWSTATS_FILE(isr, rx_mem_overflow, "%u");
+DEBUGFS_FWSTATS_FILE(isr, rx_rdys, "%u");
+DEBUGFS_FWSTATS_FILE(isr, irqs, "%u");
+DEBUGFS_FWSTATS_FILE(isr, tx_procs, "%u");
+DEBUGFS_FWSTATS_FILE(isr, decrypt_done, "%u");
+DEBUGFS_FWSTATS_FILE(isr, dma0_done, "%u");
+DEBUGFS_FWSTATS_FILE(isr, dma1_done, "%u");
+DEBUGFS_FWSTATS_FILE(isr, tx_exch_complete, "%u");
+DEBUGFS_FWSTATS_FILE(isr, commands, "%u");
+DEBUGFS_FWSTATS_FILE(isr, rx_procs, "%u");
+DEBUGFS_FWSTATS_FILE(isr, hw_pm_mode_changes, "%u");
+DEBUGFS_FWSTATS_FILE(isr, host_acknowledges, "%u");
+DEBUGFS_FWSTATS_FILE(isr, pci_pm, "%u");
+DEBUGFS_FWSTATS_FILE(isr, wakeups, "%u");
+DEBUGFS_FWSTATS_FILE(isr, low_rssi, "%u");
+
+DEBUGFS_FWSTATS_FILE(wep, addr_key_count, "%u");
+DEBUGFS_FWSTATS_FILE(wep, default_key_count, "%u");
+/* skipping wep.reserved */
+DEBUGFS_FWSTATS_FILE(wep, key_not_found, "%u");
+DEBUGFS_FWSTATS_FILE(wep, decrypt_fail, "%u");
+DEBUGFS_FWSTATS_FILE(wep, packets, "%u");
+DEBUGFS_FWSTATS_FILE(wep, interrupt, "%u");
+
+DEBUGFS_FWSTATS_FILE(pwr, ps_enter, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, elp_enter, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, missing_bcns, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, wake_on_host, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, wake_on_timer_exp, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, tx_with_ps, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, tx_without_ps, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, rcvd_beacons, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, power_save_off, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, enable_ps, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, disable_ps, "%u");
+DEBUGFS_FWSTATS_FILE(pwr, fix_tsf_ps, "%u");
+/* skipping cont_miss_bcns_spread for now */
+DEBUGFS_FWSTATS_FILE(pwr, rcvd_awake_beacons, "%u");
+
+DEBUGFS_FWSTATS_FILE(mic, rx_pkts, "%u");
+DEBUGFS_FWSTATS_FILE(mic, calc_failure, "%u");
+
+DEBUGFS_FWSTATS_FILE(aes, encrypt_fail, "%u");
+DEBUGFS_FWSTATS_FILE(aes, decrypt_fail, "%u");
+DEBUGFS_FWSTATS_FILE(aes, encrypt_packets, "%u");
+DEBUGFS_FWSTATS_FILE(aes, decrypt_packets, "%u");
+DEBUGFS_FWSTATS_FILE(aes, encrypt_interrupt, "%u");
+DEBUGFS_FWSTATS_FILE(aes, decrypt_interrupt, "%u");
+
+DEBUGFS_FWSTATS_FILE(event, heart_beat, "%u");
+DEBUGFS_FWSTATS_FILE(event, calibration, "%u");
+DEBUGFS_FWSTATS_FILE(event, rx_mismatch, "%u");
+DEBUGFS_FWSTATS_FILE(event, rx_mem_empty, "%u");
+DEBUGFS_FWSTATS_FILE(event, rx_pool, "%u");
+DEBUGFS_FWSTATS_FILE(event, oom_late, "%u");
+DEBUGFS_FWSTATS_FILE(event, phy_transmit_error, "%u");
+DEBUGFS_FWSTATS_FILE(event, tx_stuck, "%u");
+
+DEBUGFS_FWSTATS_FILE(ps, pspoll_timeouts, "%u");
+DEBUGFS_FWSTATS_FILE(ps, upsd_timeouts, "%u");
+DEBUGFS_FWSTATS_FILE(ps, upsd_max_sptime, "%u");
+DEBUGFS_FWSTATS_FILE(ps, upsd_max_apturn, "%u");
+DEBUGFS_FWSTATS_FILE(ps, pspoll_max_apturn, "%u");
+DEBUGFS_FWSTATS_FILE(ps, pspoll_utilization, "%u");
+DEBUGFS_FWSTATS_FILE(ps, upsd_utilization, "%u");
+
+DEBUGFS_FWSTATS_FILE(rxpipe, rx_prep_beacon_drop, "%u");
+DEBUGFS_FWSTATS_FILE(rxpipe, descr_host_int_trig_rx_data, "%u");
+DEBUGFS_FWSTATS_FILE(rxpipe, beacon_buffer_thres_host_int_trig_rx_data, "%u");
+DEBUGFS_FWSTATS_FILE(rxpipe, missed_beacon_host_int_trig_rx_data, "%u");
+DEBUGFS_FWSTATS_FILE(rxpipe, tx_xfr_host_int_trig_rx_data, "%u");
+
+DEBUGFS_READONLY_FILE(retry_count, "%u", wl->stats.retry_count);
+DEBUGFS_READONLY_FILE(excessive_retries, "%u",
+                      wl->stats.excessive_retries);
+
+static ssize_t tx_queue_len_read(struct file *file, char __user *userbuf,
+                                 size_t count, loff_t *ppos)
+{
+        struct wl1271 *wl = file->private_data;
+        u32 queue_len;
+        char buf[20];
+        int res;
+
+        queue_len = wl->tx_queue_count;
+
+        res = scnprintf(buf, sizeof(buf), "%u\n", queue_len);
+        return simple_read_from_buffer(userbuf, count, ppos, buf, res);
+}
+
+static const struct file_operations tx_queue_len_ops = {
+        .read = tx_queue_len_read,
+        .open = wl1271_open_file_generic,
+        .llseek = default_llseek,
+};
+
+static ssize_t gpio_power_read(struct file *file, char __user *user_buf,
+                          size_t count, loff_t *ppos)
+{
+        struct wl1271 *wl = file->private_data;
+        bool state = test_bit(WL1271_FLAG_GPIO_POWER, &wl->flags);
+
+        int res;
+        char buf[10];
+
+        res = scnprintf(buf, sizeof(buf), "%d\n", state);
+
+        return simple_read_from_buffer(user_buf, count, ppos, buf, res);
+}
+
+static ssize_t gpio_power_write(struct file *file,
+                           const char __user *user_buf,
+                           size_t count, loff_t *ppos)
+{
+        struct wl1271 *wl = file->private_data;
+        char buf[10];
+        size_t len;
+        unsigned long value;
+        int ret;
+
+        mutex_lock(&wl->mutex);
+
+        len = min(count, sizeof(buf) - 1);
+        if (copy_from_user(buf, user_buf, len)) {
+                ret = -EFAULT;
+                goto out;
+        }
+        buf[len] = '\0';
+
+        ret = strict_strtoul(buf, 0, &value);
+        if (ret < 0) {
+                wl1271_warning("illegal value in gpio_power");
+                goto out;
+        }
+
+        if (value)
+                wl1271_power_on(wl);
+        else
+                wl1271_power_off(wl);
+
+out:
+        mutex_unlock(&wl->mutex);
+        return count;
+}
+
+static const struct file_operations gpio_power_ops = {
+        .read = gpio_power_read,
+        .write = gpio_power_write,
+        .open = wl1271_open_file_generic,
+        .llseek = default_llseek,
+};
+
+static int wl1271_debugfs_add_files(struct wl1271 *wl)
+{
+        int ret = 0;
+        struct dentry *entry, *stats;
+
+        stats = debugfs_create_dir("fw-statistics", wl->rootdir);
+        if (!stats || IS_ERR(stats)) {
+                entry = stats;
+                goto err;
+        }
+
+        DEBUGFS_FWSTATS_ADD(tx, internal_desc_overflow);
+
+        DEBUGFS_FWSTATS_ADD(rx, out_of_mem);
+        DEBUGFS_FWSTATS_ADD(rx, hdr_overflow);
+        DEBUGFS_FWSTATS_ADD(rx, hw_stuck);
+        DEBUGFS_FWSTATS_ADD(rx, dropped);
+        DEBUGFS_FWSTATS_ADD(rx, fcs_err);
+        DEBUGFS_FWSTATS_ADD(rx, xfr_hint_trig);
+        DEBUGFS_FWSTATS_ADD(rx, path_reset);
+        DEBUGFS_FWSTATS_ADD(rx, reset_counter);
+
+        DEBUGFS_FWSTATS_ADD(dma, rx_requested);
+        DEBUGFS_FWSTATS_ADD(dma, rx_errors);
+        DEBUGFS_FWSTATS_ADD(dma, tx_requested);
+        DEBUGFS_FWSTATS_ADD(dma, tx_errors);
+
+        DEBUGFS_FWSTATS_ADD(isr, cmd_cmplt);
+        DEBUGFS_FWSTATS_ADD(isr, fiqs);
+        DEBUGFS_FWSTATS_ADD(isr, rx_headers);
+        DEBUGFS_FWSTATS_ADD(isr, rx_mem_overflow);
+        DEBUGFS_FWSTATS_ADD(isr, rx_rdys);
+        DEBUGFS_FWSTATS_ADD(isr, irqs);
+        DEBUGFS_FWSTATS_ADD(isr, tx_procs);
+        DEBUGFS_FWSTATS_ADD(isr, decrypt_done);
+        DEBUGFS_FWSTATS_ADD(isr, dma0_done);
+        DEBUGFS_FWSTATS_ADD(isr, dma1_done);
+        DEBUGFS_FWSTATS_ADD(isr, tx_exch_complete);
+        DEBUGFS_FWSTATS_ADD(isr, commands);
+        DEBUGFS_FWSTATS_ADD(isr, rx_procs);
+        DEBUGFS_FWSTATS_ADD(isr, hw_pm_mode_changes);
+        DEBUGFS_FWSTATS_ADD(isr, host_acknowledges);
+        DEBUGFS_FWSTATS_ADD(isr, pci_pm);
+        DEBUGFS_FWSTATS_ADD(isr, wakeups);
+        DEBUGFS_FWSTATS_ADD(isr, low_rssi);
+
+        DEBUGFS_FWSTATS_ADD(wep, addr_key_count);
+        DEBUGFS_FWSTATS_ADD(wep, default_key_count);
+        /* skipping wep.reserved */
+        DEBUGFS_FWSTATS_ADD(wep, key_not_found);
+        DEBUGFS_FWSTATS_ADD(wep, decrypt_fail);
+        DEBUGFS_FWSTATS_ADD(wep, packets);
+        DEBUGFS_FWSTATS_ADD(wep, interrupt);
+
+        DEBUGFS_FWSTATS_ADD(pwr, ps_enter);
+        DEBUGFS_FWSTATS_ADD(pwr, elp_enter);
+        DEBUGFS_FWSTATS_ADD(pwr, missing_bcns);
+        DEBUGFS_FWSTATS_ADD(pwr, wake_on_host);
+        DEBUGFS_FWSTATS_ADD(pwr, wake_on_timer_exp);
+        DEBUGFS_FWSTATS_ADD(pwr, tx_with_ps);
+        DEBUGFS_FWSTATS_ADD(pwr, tx_without_ps);
+        DEBUGFS_FWSTATS_ADD(pwr, rcvd_beacons);
+        DEBUGFS_FWSTATS_ADD(pwr, power_save_off);
+        DEBUGFS_FWSTATS_ADD(pwr, enable_ps);
+        DEBUGFS_FWSTATS_ADD(pwr, disable_ps);
+        DEBUGFS_FWSTATS_ADD(pwr, fix_tsf_ps);
+        /* skipping cont_miss_bcns_spread for now */
+        DEBUGFS_FWSTATS_ADD(pwr, rcvd_awake_beacons);
+
+        DEBUGFS_FWSTATS_ADD(mic, rx_pkts);
+        DEBUGFS_FWSTATS_ADD(mic, calc_failure);
+
+        DEBUGFS_FWSTATS_ADD(aes, encrypt_fail);
+        DEBUGFS_FWSTATS_ADD(aes, decrypt_fail);
+        DEBUGFS_FWSTATS_ADD(aes, encrypt_packets);
+        DEBUGFS_FWSTATS_ADD(aes, decrypt_packets);
+        DEBUGFS_FWSTATS_ADD(aes, encrypt_interrupt);
+        DEBUGFS_FWSTATS_ADD(aes, decrypt_interrupt);
+
+        DEBUGFS_FWSTATS_ADD(event, heart_beat);
+        DEBUGFS_FWSTATS_ADD(event, calibration);
+        DEBUGFS_FWSTATS_ADD(event, rx_mismatch);
+        DEBUGFS_FWSTATS_ADD(event, rx_mem_empty);
+        DEBUGFS_FWSTATS_ADD(event, rx_pool);
+        DEBUGFS_FWSTATS_ADD(event, oom_late);
+        DEBUGFS_FWSTATS_ADD(event, phy_transmit_error);
+        DEBUGFS_FWSTATS_ADD(event, tx_stuck);
+
+        DEBUGFS_FWSTATS_ADD(ps, pspoll_timeouts);
+        DEBUGFS_FWSTATS_ADD(ps, upsd_timeouts);
+        DEBUGFS_FWSTATS_ADD(ps, upsd_max_sptime);
+        DEBUGFS_FWSTATS_ADD(ps, upsd_max_apturn);
+        DEBUGFS_FWSTATS_ADD(ps, pspoll_max_apturn);
+        DEBUGFS_FWSTATS_ADD(ps, pspoll_utilization);
+        DEBUGFS_FWSTATS_ADD(ps, upsd_utilization);
+
+        DEBUGFS_FWSTATS_ADD(rxpipe, rx_prep_beacon_drop);
+        DEBUGFS_FWSTATS_ADD(rxpipe, descr_host_int_trig_rx_data);
+        DEBUGFS_FWSTATS_ADD(rxpipe, beacon_buffer_thres_host_int_trig_rx_data);
+        DEBUGFS_FWSTATS_ADD(rxpipe, missed_beacon_host_int_trig_rx_data);
+        DEBUGFS_FWSTATS_ADD(rxpipe, tx_xfr_host_int_trig_rx_data);
+
+        DEBUGFS_ADD(tx_queue_len, wl->rootdir);
+        DEBUGFS_ADD(retry_count, wl->rootdir);
+        DEBUGFS_ADD(excessive_retries, wl->rootdir);
+
+        DEBUGFS_ADD(gpio_power, wl->rootdir);
+
+        entry = debugfs_create_x32("debug_level", 0600, wl->rootdir,
+                                   &wl12xx_debug_level);
+        if (!entry || IS_ERR(entry))
+                goto err;
+
+        return 0;
+
+err:
+        if (IS_ERR(entry))
+                ret = PTR_ERR(entry);
+        else
+                ret = -ENOMEM;
+
+        return ret;
+}
+
+void wl1271_debugfs_reset(struct wl1271 *wl)
+{
+        if (!wl->rootdir)
+                return;
+
+        memset(wl->stats.fw_stats, 0, sizeof(*wl->stats.fw_stats));
+        wl->stats.retry_count = 0;
+        wl->stats.excessive_retries = 0;
+}
+
+int wl1271_debugfs_init(struct wl1271 *wl)
+{
+        int ret;
+
+        wl->rootdir = debugfs_create_dir(KBUILD_MODNAME,
+                                         wl->hw->wiphy->debugfsdir);
+
+        if (IS_ERR(wl->rootdir)) {
+                ret = PTR_ERR(wl->rootdir);
+                wl->rootdir = NULL;
+                goto err;
+        }
+
+        wl->stats.fw_stats = kzalloc(sizeof(*wl->stats.fw_stats),
+                                      GFP_KERNEL);
+
+        if (!wl->stats.fw_stats) {
+                ret = -ENOMEM;
+                goto err_fw;
+        }
+
+        wl->stats.fw_stats_update = jiffies;
+
+        ret = wl1271_debugfs_add_files(wl);
+
+        if (ret < 0)
+                goto err_file;
+
+        return 0;
+
+err_file:
+        kfree(wl->stats.fw_stats);
+        wl->stats.fw_stats = NULL;
+
+err_fw:
+        debugfs_remove_recursive(wl->rootdir);
+        wl->rootdir = NULL;
+
+err:
+        return ret;
+}
+
+void wl1271_debugfs_exit(struct wl1271 *wl)
+{
+        kfree(wl->stats.fw_stats);
+        wl->stats.fw_stats = NULL;
+
+        debugfs_remove_recursive(wl->rootdir);
+        wl->rootdir = NULL;
+
+}
diff --git a/drivers/net/wireless/wl12xx/wl1271_debugfs.h b/drivers/net/wireless/wl12xx/debugfs.h
index 00a45b2669ad..254c5b292cf6 100644
--- a/drivers/net/wireless/wl12xx/wl1271_debugfs.h
+++ b/drivers/net/wireless/wl12xx/debugfs.h
@@ -21,10 +21,10 @@
  *
  */
 
-#ifndef WL1271_DEBUGFS_H
-#define WL1271_DEBUGFS_H
+#ifndef __DEBUGFS_H__
+#define __DEBUGFS_H__
 
-#include "wl1271.h"
+#include "wl12xx.h"
 
 int wl1271_debugfs_init(struct wl1271 *wl);
 void wl1271_debugfs_exit(struct wl1271 *wl);
diff --git a/drivers/net/wireless/wl12xx/wl1271_event.c b/drivers/net/wireless/wl12xx/event.c
index 7b3f50382963..f9146f5242fb 100644
--- a/drivers/net/wireless/wl12xx/wl1271_event.c
+++ b/drivers/net/wireless/wl12xx/event.c
@@ -21,12 +21,12 @@
  *
  */
 
-#include "wl1271.h"
-#include "wl1271_reg.h"
-#include "wl1271_io.h"
-#include "wl1271_event.h"
-#include "wl1271_ps.h"
-#include "wl1271_scan.h"
+#include "wl12xx.h"
+#include "reg.h"
+#include "io.h"
+#include "event.h"
+#include "ps.h"
+#include "scan.h"
 #include "wl12xx_80211.h"
 
 void wl1271_pspoll_work(struct work_struct *work)
@@ -134,8 +134,6 @@ static int wl1271_event_ps_report(struct wl1271 *wl,
 
                 /* go to extremely low power mode */
                 wl1271_ps_elp_sleep(wl);
-                if (ret < 0)
-                        break;
                 break;
         case EVENT_EXIT_POWER_SAVE_FAIL:
                 wl1271_debug(DEBUG_PSM, "PSM exit failed");
diff --git a/drivers/net/wireless/wl12xx/wl1271_event.h b/drivers/net/wireless/wl12xx/event.h
index e4751667cf5e..6cce0143adb5 100644
--- a/drivers/net/wireless/wl12xx/wl1271_event.h
+++ b/drivers/net/wireless/wl12xx/event.h
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __WL1271_EVENT_H__
-#define __WL1271_EVENT_H__
+#ifndef __EVENT_H__
+#define __EVENT_H__
 
 /*
  * Mbox events
diff --git a/drivers/net/wireless/wl12xx/wl1271_ini.h b/drivers/net/wireless/wl12xx/ini.h
index 2313047d4015..c330a2583dfd 100644
--- a/drivers/net/wireless/wl12xx/wl1271_ini.h
+++ b/drivers/net/wireless/wl12xx/ini.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef __WL1271_INI_H__
-#define __WL1271_INI_H__
+#ifndef __INI_H__
+#define __INI_H__
 
 #define WL1271_INI_MAX_SMART_REFLEX_PARAM 16
 
diff --git a/drivers/net/wireless/wl12xx/wl1271_init.c b/drivers/net/wireless/wl12xx/init.c
index 8044bba70ee7..785a5304bfc4 100644
--- a/drivers/net/wireless/wl12xx/wl1271_init.c
+++ b/drivers/net/wireless/wl12xx/init.c
@@ -25,11 +25,11 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 
-#include "wl1271_init.h"
+#include "init.h"
 #include "wl12xx_80211.h"
-#include "wl1271_acx.h"
-#include "wl1271_cmd.h"
-#include "wl1271_reg.h"
+#include "acx.h"
+#include "cmd.h"
+#include "reg.h"
 
 static int wl1271_init_hwenc_config(struct wl1271 *wl)
 {
@@ -53,18 +53,16 @@ static int wl1271_init_hwenc_config(struct wl1271 *wl)
 int wl1271_init_templates_config(struct wl1271 *wl)
 {
         int ret, i;
-        size_t size;
 
         /* send empty templates for fw memory reservation */
         ret = wl1271_cmd_template_set(wl, CMD_TEMPL_CFG_PROBE_REQ_2_4, NULL,
-                                      sizeof(struct wl12xx_probe_req_template),
+                                      WL1271_CMD_TEMPL_MAX_SIZE,
                                       0, WL1271_RATE_AUTOMATIC);
         if (ret < 0)
                 return ret;
 
-        size = sizeof(struct wl12xx_probe_req_template);
         ret = wl1271_cmd_template_set(wl, CMD_TEMPL_CFG_PROBE_REQ_5,
-                                      NULL, size, 0,
+                                      NULL, WL1271_CMD_TEMPL_MAX_SIZE, 0,
                                       WL1271_RATE_AUTOMATIC);
         if (ret < 0)
                 return ret;
@@ -102,6 +100,13 @@ int wl1271_init_templates_config(struct wl1271 *wl)
         if (ret < 0)
                 return ret;
 
+        ret = wl1271_cmd_template_set(wl, CMD_TEMPL_ARP_RSP, NULL,
+                                      sizeof
+                                      (struct wl12xx_arp_rsp_template),
+                                      0, WL1271_RATE_AUTOMATIC);
+        if (ret < 0)
+                return ret;
+
         for (i = 0; i < CMD_TEMPL_KLV_IDX_MAX; i++) {
                 ret = wl1271_cmd_template_set(wl, CMD_TEMPL_KLV, NULL,
                                               WL1271_CMD_TEMPL_MAX_SIZE, i,
@@ -290,7 +295,7 @@ int wl1271_hw_init(struct wl1271 *wl)
                 goto out_free_memmap;
 
         /* Default fragmentation threshold */
-        ret = wl1271_acx_frag_threshold(wl);
+        ret = wl1271_acx_frag_threshold(wl, wl->conf.tx.frag_threshold);
         if (ret < 0)
                 goto out_free_memmap;
 
diff --git a/drivers/net/wireless/wl12xx/wl1271_init.h b/drivers/net/wireless/wl12xx/init.h
index bc26f8c53b91..7762421f8602 100644
--- a/drivers/net/wireless/wl12xx/wl1271_init.h
+++ b/drivers/net/wireless/wl12xx/init.h
@@ -21,10 +21,10 @@
  *
  */
 
-#ifndef __WL1271_INIT_H__
-#define __WL1271_INIT_H__
+#ifndef __INIT_H__
+#define __INIT_H__
 
-#include "wl1271.h"
+#include "wl12xx.h"
 
 int wl1271_hw_init_power_auth(struct wl1271 *wl);
 int wl1271_init_templates_config(struct wl1271 *wl);
diff --git a/drivers/net/wireless/wl12xx/wl1271_io.c b/drivers/net/wireless/wl12xx/io.c
index c8759acef131..d557f73e7c19 100644
--- a/drivers/net/wireless/wl12xx/wl1271_io.c
+++ b/drivers/net/wireless/wl12xx/io.c
@@ -26,9 +26,9 @@
 #include <linux/crc7.h>
 #include <linux/spi/spi.h>
 
-#include "wl1271.h"
+#include "wl12xx.h"
 #include "wl12xx_80211.h"
-#include "wl1271_io.h"
+#include "io.h"
 
 #define OCP_CMD_LOOP  32
 
@@ -113,6 +113,7 @@ int wl1271_set_partition(struct wl1271 *wl,
 
         return 0;
 }
+EXPORT_SYMBOL_GPL(wl1271_set_partition);
 
 void wl1271_io_reset(struct wl1271 *wl)
 {
diff --git a/drivers/net/wireless/wl12xx/wl1271_io.h b/drivers/net/wireless/wl12xx/io.h
index c1f92e65ded0..844b32b170bb 100644
--- a/drivers/net/wireless/wl12xx/wl1271_io.h
+++ b/drivers/net/wireless/wl12xx/io.h
@@ -22,10 +22,10 @@
  *
  */
 
-#ifndef __WL1271_IO_H__
-#define __WL1271_IO_H__
+#ifndef __IO_H__
+#define __IO_H__
 
-#include "wl1271_reg.h"
+#include "reg.h"
 
 #define HW_ACCESS_MEMORY_MAX_RANGE      0x1FFC0
 
diff --git a/drivers/net/wireless/wl12xx/wl1271_main.c b/drivers/net/wireless/wl12xx/main.c
index 48a4b9961ae6..062247ef3ad2 100644
--- a/drivers/net/wireless/wl12xx/wl1271_main.c
+++ b/drivers/net/wireless/wl12xx/main.c
@@ -31,20 +31,20 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include "wl1271.h"
+#include "wl12xx.h"
 #include "wl12xx_80211.h"
-#include "wl1271_reg.h"
-#include "wl1271_io.h"
-#include "wl1271_event.h"
-#include "wl1271_tx.h"
-#include "wl1271_rx.h"
-#include "wl1271_ps.h"
-#include "wl1271_init.h"
-#include "wl1271_debugfs.h"
-#include "wl1271_cmd.h"
-#include "wl1271_boot.h"
-#include "wl1271_testmode.h"
-#include "wl1271_scan.h"
+#include "reg.h"
+#include "io.h"
+#include "event.h"
+#include "tx.h"
+#include "rx.h"
+#include "ps.h"
+#include "init.h"
+#include "debugfs.h"
+#include "cmd.h"
+#include "boot.h"
+#include "testmode.h"
+#include "scan.h"
 
 #define WL1271_BOOT_RETRIES 3
 
@@ -335,6 +335,28 @@ out:
         return NOTIFY_OK;
 }
 
+static int wl1271_reg_notify(struct wiphy *wiphy,
+                             struct regulatory_request *request)
+{
+        struct ieee80211_supported_band *band;
+        struct ieee80211_channel *ch;
+        int i;
+
+        band = wiphy->bands[IEEE80211_BAND_5GHZ];
+        for (i = 0; i < band->n_channels; i++) {
+                ch = &band->channels[i];
+                if (ch->flags & IEEE80211_CHAN_DISABLED)
+                        continue;
+
+                if (ch->flags & IEEE80211_CHAN_RADAR)
+                        ch->flags |= IEEE80211_CHAN_NO_IBSS |
+                                     IEEE80211_CHAN_PASSIVE_SCAN;
+
+        }
+
+        return 0;
+}
+
 static void wl1271_conf_init(struct wl1271 *wl)
 {
 
@@ -404,7 +426,7 @@ static int wl1271_plt_init(struct wl1271 *wl)
                 goto out_free_memmap;
 
         /* Default fragmentation threshold */
-        ret = wl1271_acx_frag_threshold(wl);
+        ret = wl1271_acx_frag_threshold(wl, wl->conf.tx.frag_threshold);
         if (ret < 0)
                 goto out_free_memmap;
 
@@ -481,9 +503,9 @@ static void wl1271_fw_status(struct wl1271 *wl,
                 total += cnt;
         }
 
-        /* if more blocks are available now, schedule some tx work */
-        if (total && !skb_queue_empty(&wl->tx_queue))
-                ieee80211_queue_work(wl->hw, &wl->tx_work);
+        /* if more blocks are available now, tx work can be scheduled */
+        if (total)
+                clear_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags);
 
         /* update the host-chipset time offset */
         getnstimeofday(&ts);
@@ -529,6 +551,15 @@ static void wl1271_irq_work(struct work_struct *work)
 
                 intr &= WL1271_INTR_MASK;
 
+                if (unlikely(intr & WL1271_ACX_INTR_WATCHDOG)) {
+                        wl1271_error("watchdog interrupt received! "
+                                     "starting recovery.");
+                        ieee80211_queue_work(wl->hw, &wl->recovery_work);
+
+                        /* restarting the chip. ignore any other interrupt. */
+                        goto out;
+                }
+
                 if (intr & WL1271_ACX_INTR_DATA) {
                         wl1271_debug(DEBUG_IRQ, "WL1271_ACX_INTR_DATA");
 
@@ -537,6 +568,16 @@ static void wl1271_irq_work(struct work_struct *work)
                             (wl->tx_results_count & 0xff))
                                 wl1271_tx_complete(wl);
 
+                        /* Check if any tx blocks were freed */
+                        if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags) &&
+                            wl->tx_queue_count) {
+                                /*
+                                 * In order to avoid starvation of the TX path,
+                                 * call the work function directly.
+                                 */
+                                wl1271_tx_work_locked(wl);
+                        }
+
                         wl1271_rx(wl, wl->fw_status);
                 }
 
@@ -850,30 +891,54 @@ static int wl1271_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
         struct ieee80211_tx_info *txinfo = IEEE80211_SKB_CB(skb);
         struct ieee80211_sta *sta = txinfo->control.sta;
         unsigned long flags;
+        int q;
 
-        /* peek into the rates configured in the STA entry */
+        /*
+         * peek into the rates configured in the STA entry.
+         * The rates set after connection stage, The first block only BG sets:
+         * the compare is for bit 0-16 of sta_rate_set. The second block add
+         * HT rates in case of HT supported.
+         */
         spin_lock_irqsave(&wl->wl_lock, flags);
-        if (sta && sta->supp_rates[conf->channel->band] != wl->sta_rate_set) {
+        if (sta &&
+            (sta->supp_rates[conf->channel->band] !=
+            (wl->sta_rate_set & HW_BG_RATES_MASK))) {
                 wl->sta_rate_set = sta->supp_rates[conf->channel->band];
                 set_bit(WL1271_FLAG_STA_RATES_CHANGED, &wl->flags);
         }
+
+#ifdef CONFIG_WL12XX_HT
+        if (sta &&
+            sta->ht_cap.ht_supported &&
+            ((wl->sta_rate_set >> HW_HT_RATES_OFFSET) !=
+              sta->ht_cap.mcs.rx_mask[0])) {
+                /* Clean MCS bits before setting them */
+                wl->sta_rate_set &= HW_BG_RATES_MASK;
+                wl->sta_rate_set |=
+                        (sta->ht_cap.mcs.rx_mask[0] << HW_HT_RATES_OFFSET);
+                set_bit(WL1271_FLAG_STA_RATES_CHANGED, &wl->flags);
+        }
+#endif
+        wl->tx_queue_count++;
         spin_unlock_irqrestore(&wl->wl_lock, flags);
 
         /* queue the packet */
-        skb_queue_tail(&wl->tx_queue, skb);
+        q = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
+        skb_queue_tail(&wl->tx_queue[q], skb);
 
         /*
          * The chip specific setup must run before the first TX packet -
          * before that, the tx_work will not be initialized!
          */
 
-        ieee80211_queue_work(wl->hw, &wl->tx_work);
+        if (!test_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags))
+                ieee80211_queue_work(wl->hw, &wl->tx_work);
 
         /*
          * The workqueue is slow to process the tx_queue and we need stop
          * the queue here, otherwise the queue will get too long.
          */
-        if (skb_queue_len(&wl->tx_queue) >= WL1271_TX_QUEUE_HIGH_WATERMARK) {
+        if (wl->tx_queue_count >= WL1271_TX_QUEUE_HIGH_WATERMARK) {
                 wl1271_debug(DEBUG_TX, "op_tx: stopping queues");
 
                 spin_lock_irqsave(&wl->wl_lock, flags);
@@ -919,18 +984,19 @@ static int wl1271_op_add_interface(struct ieee80211_hw *hw,
         struct wiphy *wiphy = hw->wiphy;
         int retries = WL1271_BOOT_RETRIES;
         int ret = 0;
+        bool booted = false;
 
         wl1271_debug(DEBUG_MAC80211, "mac80211 add interface type %d mac %pM",
                      vif->type, vif->addr);
 
         mutex_lock(&wl->mutex);
         if (wl->vif) {
+                wl1271_debug(DEBUG_MAC80211,
+                             "multiple vifs are not supported yet");
                 ret = -EBUSY;
                 goto out;
         }
 
-        wl->vif = vif;
-
         switch (vif->type) {
         case NL80211_IFTYPE_STATION:
                 wl->bss_type = BSS_TYPE_STA_BSS;
@@ -968,15 +1034,8 @@ static int wl1271_op_add_interface(struct ieee80211_hw *hw,
                 if (ret < 0)
                         goto irq_disable;
 
-                wl->state = WL1271_STATE_ON;
-                wl1271_info("firmware booted (%s)", wl->chip.fw_ver);
-
-                /* update hw/fw version info in wiphy struct */
-                wiphy->hw_version = wl->chip.id;
-                strncpy(wiphy->fw_version, wl->chip.fw_ver,
-                        sizeof(wiphy->fw_version));
-
-                goto out;
+                booted = true;
+                break;
 
 irq_disable:
                 wl1271_disable_interrupts(wl);
@@ -994,8 +1053,31 @@ power_off:
                 wl1271_power_off(wl);
         }
 
-        wl1271_error("firmware boot failed despite %d retries",
-                     WL1271_BOOT_RETRIES);
+        if (!booted) {
+                wl1271_error("firmware boot failed despite %d retries",
+                             WL1271_BOOT_RETRIES);
+                goto out;
+        }
+
+        wl->vif = vif;
+        wl->state = WL1271_STATE_ON;
+        wl1271_info("firmware booted (%s)", wl->chip.fw_ver);
+
+        /* update hw/fw version info in wiphy struct */
+        wiphy->hw_version = wl->chip.id;
+        strncpy(wiphy->fw_version, wl->chip.fw_ver,
+                sizeof(wiphy->fw_version));
+
+        /*
+         * Now we know if 11a is supported (info from the NVS), so disable
+         * 11a channels if not supported
+         */
+        if (!wl->enable_11a)
+                wiphy->bands[IEEE80211_BAND_5GHZ]->n_channels = 0;
+
+        wl1271_debug(DEBUG_MAC80211, "11a is %ssupported",
+                     wl->enable_11a ? "" : "not ");
+
 out:
         mutex_unlock(&wl->mutex);
 
@@ -1025,6 +1107,7 @@ static void __wl1271_op_remove_interface(struct wl1271 *wl)
                 wl->scan.state = WL1271_SCAN_STATE_IDLE;
                 kfree(wl->scan.scanned_ch);
                 wl->scan.scanned_ch = NULL;
+                wl->scan.req = NULL;
                 ieee80211_scan_completed(wl->hw, true);
         }
 
@@ -1088,10 +1171,16 @@ static void wl1271_op_remove_interface(struct ieee80211_hw *hw,
         struct wl1271 *wl = hw->priv;
 
         mutex_lock(&wl->mutex);
-        WARN_ON(wl->vif != vif);
-        __wl1271_op_remove_interface(wl);
-        mutex_unlock(&wl->mutex);
+        /*
+         * wl->vif can be null here if someone shuts down the interface
+         * just when hardware recovery has been started.
+         */
+        if (wl->vif) {
+                WARN_ON(wl->vif != vif);
+                __wl1271_op_remove_interface(wl);
+        }
 
+        mutex_unlock(&wl->mutex);
         cancel_work_sync(&wl->recovery_work);
 }
 
@@ -1312,8 +1401,10 @@ static int wl1271_op_config(struct ieee80211_hw *hw, u32 changed)
 
         mutex_lock(&wl->mutex);
 
-        if (unlikely(wl->state == WL1271_STATE_OFF))
+        if (unlikely(wl->state == WL1271_STATE_OFF)) {
+                ret = -EAGAIN;
                 goto out;
+        }
 
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
@@ -1536,6 +1627,11 @@ static int wl1271_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
 
         mutex_lock(&wl->mutex);
 
+        if (unlikely(wl->state == WL1271_STATE_OFF)) {
+                ret = -EAGAIN;
+                goto out_unlock;
+        }
+
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
                 goto out_unlock;
@@ -1645,6 +1741,16 @@ static int wl1271_op_hw_scan(struct ieee80211_hw *hw,
 
         mutex_lock(&wl->mutex);
 
+        if (wl->state == WL1271_STATE_OFF) {
+                /*
+                 * We cannot return -EBUSY here because cfg80211 will expect
+                 * a call to ieee80211_scan_completed if we do - in this case
+                 * there won't be any call.
+                 */
+                ret = -EAGAIN;
+                goto out;
+        }
+
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
                 goto out;
@@ -1659,6 +1765,34 @@ out:
         return ret;
 }
 
+static int wl1271_op_set_frag_threshold(struct ieee80211_hw *hw, u32 value)
+{
+        struct wl1271 *wl = hw->priv;
+        int ret = 0;
+
+        mutex_lock(&wl->mutex);
+
+        if (unlikely(wl->state == WL1271_STATE_OFF)) {
+                ret = -EAGAIN;
+                goto out;
+        }
+
+        ret = wl1271_ps_elp_wakeup(wl, false);
+        if (ret < 0)
+                goto out;
+
+        ret = wl1271_acx_frag_threshold(wl, (u16)value);
+        if (ret < 0)
+                wl1271_warning("wl1271_op_set_frag_threshold failed: %d", ret);
+
+        wl1271_ps_elp_sleep(wl);
+
+out:
+        mutex_unlock(&wl->mutex);
+
+        return ret;
+}
+
 static int wl1271_op_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
 {
         struct wl1271 *wl = hw->priv;
@@ -1666,8 +1800,10 @@ static int wl1271_op_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
 
         mutex_lock(&wl->mutex);
 
-        if (unlikely(wl->state == WL1271_STATE_OFF))
+        if (unlikely(wl->state == WL1271_STATE_OFF)) {
+                ret = -EAGAIN;
                 goto out;
+        }
 
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
@@ -1685,21 +1821,21 @@ out:
         return ret;
 }
 
-static void wl1271_ssid_set(struct wl1271 *wl, struct sk_buff *beacon)
+static void wl1271_ssid_set(struct wl1271 *wl, struct sk_buff *skb,
+                            int offset)
 {
-        u8 *ptr = beacon->data +
-                offsetof(struct ieee80211_mgmt, u.beacon.variable);
+        u8 *ptr = skb->data + offset;
 
         /* find the location of the ssid in the beacon */
-        while (ptr < beacon->data + beacon->len) {
+        while (ptr < skb->data + skb->len) {
                 if (ptr[0] == WLAN_EID_SSID) {
                         wl->ssid_len = ptr[1];
                         memcpy(wl->ssid, ptr+2, wl->ssid_len);
                         return;
                 }
-                ptr += ptr[1];
+                ptr += (ptr[1] + 2);
         }
-        wl1271_error("ad-hoc beacon template has no SSID!\n");
+        wl1271_error("No SSID in IEs!\n");
 }
 
 static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
@@ -1709,6 +1845,7 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
 {
         enum wl1271_cmd_ps_mode mode;
         struct wl1271 *wl = hw->priv;
+        struct ieee80211_sta *sta = ieee80211_find_sta(vif, bss_conf->bssid);
         bool do_join = false;
         bool set_assoc = false;
         int ret;
@@ -1717,6 +1854,9 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
 
         mutex_lock(&wl->mutex);
 
+        if (unlikely(wl->state == WL1271_STATE_OFF))
+                goto out;
+
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
                 goto out;
@@ -1738,8 +1878,11 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
 
                 if (beacon) {
                         struct ieee80211_hdr *hdr;
+                        int ieoffset = offsetof(struct ieee80211_mgmt,
+                                                u.beacon.variable);
+
+                        wl1271_ssid_set(wl, beacon, ieoffset);
 
-                        wl1271_ssid_set(wl, beacon);
                         ret = wl1271_cmd_template_set(wl, CMD_TEMPL_BEACON,
                                                       beacon->data,
                                                       beacon->len, 0,
@@ -1819,6 +1962,7 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
         if (changed & BSS_CHANGED_ASSOC) {
                 if (bss_conf->assoc) {
                         u32 rates;
+                        int ieoffset;
                         wl->aid = bss_conf->aid;
                         set_assoc = true;
 
@@ -1847,13 +1991,13 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
                                 goto out_sleep;
 
                         /*
-                         * The SSID is intentionally set to NULL here - the
-                         * firmware will set the probe request with a
-                         * broadcast SSID regardless of what we set in the
-                         * template.
+                         * Get a template for hardware connection maintenance
                          */
-                        ret = wl1271_cmd_build_probe_req(wl, NULL, 0,
-                                                         NULL, 0, wl->band);
+                        dev_kfree_skb(wl->probereq);
+                        wl->probereq = wl1271_cmd_build_ap_probe_req(wl, NULL);
+                        ieoffset = offsetof(struct ieee80211_mgmt,
+                                            u.probe_req.variable);
+                        wl1271_ssid_set(wl, wl->probereq, ieoffset);
 
                         /* enable the connection monitoring feature */
                         ret = wl1271_acx_conn_monit_params(wl, true);
@@ -1876,6 +2020,10 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
                         clear_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags);
                         wl->aid = 0;
 
+                        /* free probe-request template */
+                        dev_kfree_skb(wl->probereq);
+                        wl->probereq = NULL;
+
                         /* re-enable dynamic ps - just in case */
                         ieee80211_enable_dyn_ps(wl->vif);
 
@@ -1891,9 +2039,12 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
 
                         /* Disable the keep-alive feature */
                         ret = wl1271_acx_keep_alive_mode(wl, false);
-
                         if (ret < 0)
                                 goto out_sleep;
+
+                        /* restore the bssid filter and go to dummy bssid */
+                        wl1271_unjoin(wl);
+                        wl1271_dummy_join(wl);
                 }
 
         }
@@ -1927,14 +2078,61 @@ static void wl1271_op_bss_info_changed(struct ieee80211_hw *hw,
                 }
         }
 
+        /*
+         * Takes care of: New association with HT enable,
+         *                HT information change in beacon.
+         */
+        if (sta &&
+            (changed & BSS_CHANGED_HT) &&
+            (bss_conf->channel_type != NL80211_CHAN_NO_HT)) {
+                ret = wl1271_acx_set_ht_capabilities(wl, &sta->ht_cap, true);
+                if (ret < 0) {
+                        wl1271_warning("Set ht cap true failed %d", ret);
+                        goto out_sleep;
+                }
+                        ret = wl1271_acx_set_ht_information(wl,
+                                bss_conf->ht_operation_mode);
+                if (ret < 0) {
+                        wl1271_warning("Set ht information failed %d", ret);
+                        goto out_sleep;
+                }
+        }
+        /*
+         * Takes care of: New association without HT,
+         *                Disassociation.
+         */
+        else if (sta && (changed & BSS_CHANGED_ASSOC)) {
+                ret = wl1271_acx_set_ht_capabilities(wl, &sta->ht_cap, false);
+                if (ret < 0) {
+                        wl1271_warning("Set ht cap false failed %d", ret);
+                        goto out_sleep;
+                }
+        }
+
         if (changed & BSS_CHANGED_ARP_FILTER) {
                 __be32 addr = bss_conf->arp_addr_list[0];
                 WARN_ON(wl->bss_type != BSS_TYPE_STA_BSS);
 
-                if (bss_conf->arp_addr_cnt == 1 && bss_conf->arp_filter_enabled)
-                        ret = wl1271_acx_arp_ip_filter(wl, true, addr);
-                else
-                        ret = wl1271_acx_arp_ip_filter(wl, false, addr);
+                if (bss_conf->arp_addr_cnt == 1 &&
+                    bss_conf->arp_filter_enabled) {
+                        /*
+                         * The template should have been configured only upon
+                         * association. however, it seems that the correct ip
+                         * isn't being set (when sending), so we have to
+                         * reconfigure the template upon every ip change.
+                         */
+                        ret = wl1271_cmd_build_arp_rsp(wl, addr);
+                        if (ret < 0) {
+                                wl1271_warning("build arp rsp failed: %d", ret);
+                                goto out_sleep;
+                        }
+
+                        ret = wl1271_acx_arp_ip_filter(wl,
+                                (ACX_ARP_FILTER_ARP_FILTERING |
+                                 ACX_ARP_FILTER_AUTO_ARP),
+                                addr);
+                } else
+                        ret = wl1271_acx_arp_ip_filter(wl, 0, addr);
 
                 if (ret < 0)
                         goto out_sleep;
@@ -1966,6 +2164,11 @@ static int wl1271_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
 
         wl1271_debug(DEBUG_MAC80211, "mac80211 conf tx %d", queue);
 
+        if (unlikely(wl->state == WL1271_STATE_OFF)) {
+                ret = -EAGAIN;
+                goto out;
+        }
+
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
                 goto out;
@@ -2009,6 +2212,9 @@ static u64 wl1271_op_get_tsf(struct ieee80211_hw *hw)
 
         mutex_lock(&wl->mutex);
 
+        if (unlikely(wl->state == WL1271_STATE_OFF))
+                goto out;
+
         ret = wl1271_ps_elp_wakeup(wl, false);
         if (ret < 0)
                 goto out;
@@ -2030,14 +2236,14 @@ static int wl1271_op_get_survey(struct ieee80211_hw *hw, int idx,
 {
         struct wl1271 *wl = hw->priv;
         struct ieee80211_conf *conf = &hw->conf;
- 
+
         if (idx != 0)
                 return -ENOENT;
- 
+
         survey->channel = conf->channel;
         survey->filled = SURVEY_INFO_NOISE_DBM;
         survey->noise = wl->noise;
- 
+
         return 0;
 }
 
@@ -2084,37 +2290,34 @@ static struct ieee80211_rate wl1271_rates[] = {
           .hw_value_short = CONF_HW_BIT_RATE_54MBPS, },
 };
 
-/*
- * Can't be const, mac80211 writes to this. The order of the channels here
- * is designed to improve scanning.
- */
+/* can't be const, mac80211 writes to this */
 static struct ieee80211_channel wl1271_channels[] = {
         { .hw_value = 1, .center_freq = 2412, .max_power = 25 },
-        { .hw_value = 5, .center_freq = 2432, .max_power = 25 },
-        { .hw_value = 9, .center_freq = 2452, .max_power = 25 },
-        { .hw_value = 13, .center_freq = 2472, .max_power = 25 },
-        { .hw_value = 4, .center_freq = 2427, .max_power = 25 },
-        { .hw_value = 8, .center_freq = 2447, .max_power = 25 },
-        { .hw_value = 12, .center_freq = 2467, .max_power = 25 },
-        { .hw_value = 3, .center_freq = 2422, .max_power = 25 },
-        { .hw_value = 7, .center_freq = 2442, .max_power = 25 },
-        { .hw_value = 11, .center_freq = 2462, .max_power = 25 },
         { .hw_value = 2, .center_freq = 2417, .max_power = 25 },
+        { .hw_value = 3, .center_freq = 2422, .max_power = 25 },
+        { .hw_value = 4, .center_freq = 2427, .max_power = 25 },
+        { .hw_value = 5, .center_freq = 2432, .max_power = 25 },
         { .hw_value = 6, .center_freq = 2437, .max_power = 25 },
+        { .hw_value = 7, .center_freq = 2442, .max_power = 25 },
+        { .hw_value = 8, .center_freq = 2447, .max_power = 25 },
+        { .hw_value = 9, .center_freq = 2452, .max_power = 25 },
         { .hw_value = 10, .center_freq = 2457, .max_power = 25 },
+        { .hw_value = 11, .center_freq = 2462, .max_power = 25 },
+        { .hw_value = 12, .center_freq = 2467, .max_power = 25 },
+        { .hw_value = 13, .center_freq = 2472, .max_power = 25 },
 };
 
 /* mapping to indexes for wl1271_rates */
 static const u8 wl1271_rate_to_idx_2ghz[] = {
         /* MCS rates are used only with 11n */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS7 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS6 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS5 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS4 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS3 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS2 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS1 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS0 */
+        7,                            /* CONF_HW_RXTX_RATE_MCS7 */
+        6,                            /* CONF_HW_RXTX_RATE_MCS6 */
+        5,                            /* CONF_HW_RXTX_RATE_MCS5 */
+        4,                            /* CONF_HW_RXTX_RATE_MCS4 */
+        3,                            /* CONF_HW_RXTX_RATE_MCS3 */
+        2,                            /* CONF_HW_RXTX_RATE_MCS2 */
+        1,                            /* CONF_HW_RXTX_RATE_MCS1 */
+        0,                            /* CONF_HW_RXTX_RATE_MCS0 */
 
         11,                            /* CONF_HW_RXTX_RATE_54   */
         10,                            /* CONF_HW_RXTX_RATE_48   */
@@ -2134,12 +2337,34 @@ static const u8 wl1271_rate_to_idx_2ghz[] = {
         0                              /* CONF_HW_RXTX_RATE_1    */
 };
 
+/* 11n STA capabilities */
+#define HW_RX_HIGHEST_RATE      72
+
+#ifdef CONFIG_WL12XX_HT
+#define WL12XX_HT_CAP { \
+        .cap = IEEE80211_HT_CAP_GRN_FLD | IEEE80211_HT_CAP_SGI_20, \
+        .ht_supported = true, \
+        .ampdu_factor = IEEE80211_HT_MAX_AMPDU_8K, \
+        .ampdu_density = IEEE80211_HT_MPDU_DENSITY_8, \
+        .mcs = { \
+                .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, \
+                .rx_highest = cpu_to_le16(HW_RX_HIGHEST_RATE), \
+                .tx_params = IEEE80211_HT_MCS_TX_DEFINED, \
+                }, \
+}
+#else
+#define WL12XX_HT_CAP { \
+        .ht_supported = false, \
+}
+#endif
+
 /* can't be const, mac80211 writes to this */
 static struct ieee80211_supported_band wl1271_band_2ghz = {
         .channels = wl1271_channels,
         .n_channels = ARRAY_SIZE(wl1271_channels),
         .bitrates = wl1271_rates,
         .n_bitrates = ARRAY_SIZE(wl1271_rates),
+        .ht_cap = WL12XX_HT_CAP,
 };
 
 /* 5 GHz data rates for WL1273 */
@@ -2170,66 +2395,55 @@ static struct ieee80211_rate wl1271_rates_5ghz[] = {
           .hw_value_short = CONF_HW_BIT_RATE_54MBPS, },
 };
 
-/*
- * 5 GHz band channels for WL1273 - can't be const, mac80211 writes to this.
- * The order of the channels here is designed to improve scanning.
- */
+/* 5 GHz band channels for WL1273 */
 static struct ieee80211_channel wl1271_channels_5ghz[] = {
-        { .hw_value = 183, .center_freq = 4915},
-        { .hw_value = 188, .center_freq = 4940},
+        { .hw_value = 7, .center_freq = 5035},
         { .hw_value = 8, .center_freq = 5040},
-        { .hw_value = 34, .center_freq = 5170},
-        { .hw_value = 44, .center_freq = 5220},
-        { .hw_value = 60, .center_freq = 5300},
-        { .hw_value = 112, .center_freq = 5560},
-        { .hw_value = 132, .center_freq = 5660},
-        { .hw_value = 157, .center_freq = 5785},
-        { .hw_value = 184, .center_freq = 4920},
-        { .hw_value = 189, .center_freq = 4945},
         { .hw_value = 9, .center_freq = 5045},
-        { .hw_value = 36, .center_freq = 5180},
-        { .hw_value = 46, .center_freq = 5230},
-        { .hw_value = 64, .center_freq = 5320},
-        { .hw_value = 116, .center_freq = 5580},
-        { .hw_value = 136, .center_freq = 5680},
-        { .hw_value = 192, .center_freq = 4960},
         { .hw_value = 11, .center_freq = 5055},
-        { .hw_value = 38, .center_freq = 5190},
-        { .hw_value = 48, .center_freq = 5240},
-        { .hw_value = 100, .center_freq = 5500},
-        { .hw_value = 120, .center_freq = 5600},
-        { .hw_value = 140, .center_freq = 5700},
-        { .hw_value = 185, .center_freq = 4925},
-        { .hw_value = 196, .center_freq = 4980},
         { .hw_value = 12, .center_freq = 5060},
-        { .hw_value = 40, .center_freq = 5200},
-        { .hw_value = 52, .center_freq = 5260},
-        { .hw_value = 104, .center_freq = 5520},
-        { .hw_value = 124, .center_freq = 5620},
-        { .hw_value = 149, .center_freq = 5745},
-        { .hw_value = 161, .center_freq = 5805},
-        { .hw_value = 187, .center_freq = 4935},
-        { .hw_value = 7, .center_freq = 5035},
         { .hw_value = 16, .center_freq = 5080},
+        { .hw_value = 34, .center_freq = 5170},
+        { .hw_value = 36, .center_freq = 5180},
+        { .hw_value = 38, .center_freq = 5190},
+        { .hw_value = 40, .center_freq = 5200},
         { .hw_value = 42, .center_freq = 5210},
+        { .hw_value = 44, .center_freq = 5220},
+        { .hw_value = 46, .center_freq = 5230},
+        { .hw_value = 48, .center_freq = 5240},
+        { .hw_value = 52, .center_freq = 5260},
         { .hw_value = 56, .center_freq = 5280},
+        { .hw_value = 60, .center_freq = 5300},
+        { .hw_value = 64, .center_freq = 5320},
+        { .hw_value = 100, .center_freq = 5500},
+        { .hw_value = 104, .center_freq = 5520},
         { .hw_value = 108, .center_freq = 5540},
+        { .hw_value = 112, .center_freq = 5560},
+        { .hw_value = 116, .center_freq = 5580},
+        { .hw_value = 120, .center_freq = 5600},
+        { .hw_value = 124, .center_freq = 5620},
         { .hw_value = 128, .center_freq = 5640},
+        { .hw_value = 132, .center_freq = 5660},
+        { .hw_value = 136, .center_freq = 5680},
+        { .hw_value = 140, .center_freq = 5700},
+        { .hw_value = 149, .center_freq = 5745},
         { .hw_value = 153, .center_freq = 5765},
+        { .hw_value = 157, .center_freq = 5785},
+        { .hw_value = 161, .center_freq = 5805},
         { .hw_value = 165, .center_freq = 5825},
 };
 
 /* mapping to indexes for wl1271_rates_5ghz */
 static const u8 wl1271_rate_to_idx_5ghz[] = {
         /* MCS rates are used only with 11n */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS7 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS6 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS5 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS4 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS3 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS2 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS1 */
-        CONF_HW_RXTX_RATE_UNSUPPORTED, /* CONF_HW_RXTX_RATE_MCS0 */
+        7,                            /* CONF_HW_RXTX_RATE_MCS7 */
+        6,                            /* CONF_HW_RXTX_RATE_MCS6 */
+        5,                            /* CONF_HW_RXTX_RATE_MCS5 */
+        4,                            /* CONF_HW_RXTX_RATE_MCS4 */
+        3,                            /* CONF_HW_RXTX_RATE_MCS3 */
+        2,                            /* CONF_HW_RXTX_RATE_MCS2 */
+        1,                            /* CONF_HW_RXTX_RATE_MCS1 */
+        0,                            /* CONF_HW_RXTX_RATE_MCS0 */
 
         7,                             /* CONF_HW_RXTX_RATE_54   */
         6,                             /* CONF_HW_RXTX_RATE_48   */
@@ -2254,6 +2468,7 @@ static struct ieee80211_supported_band wl1271_band_5ghz = {
         .n_channels = ARRAY_SIZE(wl1271_channels_5ghz),
         .bitrates = wl1271_rates_5ghz,
         .n_bitrates = ARRAY_SIZE(wl1271_rates_5ghz),
+        .ht_cap = WL12XX_HT_CAP,
 };
 
 static const u8 *wl1271_band_rate_to_idx[] = {
@@ -2273,6 +2488,7 @@ static const struct ieee80211_ops wl1271_ops = {
         .set_key = wl1271_op_set_key,
         .hw_scan = wl1271_op_hw_scan,
         .bss_info_changed = wl1271_op_bss_info_changed,
+        .set_frag_threshold = wl1271_op_set_frag_threshold,
         .set_rts_threshold = wl1271_op_set_rts_threshold,
         .conf_tx = wl1271_op_conf_tx,
         .get_tsf = wl1271_op_get_tsf,
@@ -2281,18 +2497,18 @@ static const struct ieee80211_ops wl1271_ops = {
 };
 
 
-u8 wl1271_rate_to_idx(struct wl1271 *wl, int rate)
+u8 wl1271_rate_to_idx(int rate, enum ieee80211_band band)
 {
         u8 idx;
 
-        BUG_ON(wl->band >= sizeof(wl1271_band_rate_to_idx)/sizeof(u8 *));
+        BUG_ON(band >= sizeof(wl1271_band_rate_to_idx)/sizeof(u8 *));
 
         if (unlikely(rate >= CONF_HW_RXTX_RATE_MAX)) {
                 wl1271_error("Illegal RX rate from HW: %d", rate);
                 return 0;
         }
 
-        idx = wl1271_band_rate_to_idx[wl->band][rate];
+        idx = wl1271_band_rate_to_idx[band][rate];
         if (unlikely(idx == CONF_HW_RXTX_RATE_UNSUPPORTED)) {
                 wl1271_error("Unsupported RX rate from HW: %d", rate);
                 return 0;
@@ -2401,6 +2617,8 @@ int wl1271_register_hw(struct wl1271 *wl)
 
         wl->mac80211_registered = true;
 
+        wl1271_debugfs_init(wl);
+
         register_netdevice_notifier(&wl1271_dev_notifier);
 
         wl1271_notice("loaded");
@@ -2451,12 +2669,21 @@ int wl1271_init_ieee80211(struct wl1271 *wl)
         wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
                 BIT(NL80211_IFTYPE_ADHOC);
         wl->hw->wiphy->max_scan_ssids = 1;
+        /*
+         * Maximum length of elements in scanning probe request templates
+         * should be the maximum length possible for a template, without
+         * the IEEE80211 header of the template
+         */
+        wl->hw->wiphy->max_scan_ie_len = WL1271_CMD_TEMPL_MAX_SIZE -
+                        sizeof(struct ieee80211_header);
         wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &wl1271_band_2ghz;
         wl->hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &wl1271_band_5ghz;
 
         wl->hw->queues = 4;
         wl->hw->max_rates = 1;
 
+        wl->hw->wiphy->reg_notifier = wl1271_reg_notify;
+
         SET_IEEE80211_DEV(wl->hw, wl1271_wl_to_dev(wl));
 
         return 0;
@@ -2495,7 +2722,8 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
         wl->hw = hw;
         wl->plat_dev = plat_dev;
 
-        skb_queue_head_init(&wl->tx_queue);
+        for (i = 0; i < NUM_TX_QUEUES; i++)
+                skb_queue_head_init(&wl->tx_queue[i]);
 
         INIT_DELAYED_WORK(&wl->elp_work, wl1271_elp_work);
         INIT_DELAYED_WORK(&wl->pspoll_work, wl1271_pspoll_work);
@@ -2521,6 +2749,7 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
         wl->sg_enabled = true;
         wl->hw_pg_ver = -1;
 
+        memset(wl->tx_frames_map, 0, sizeof(wl->tx_frames_map));
         for (i = 0; i < ACX_TX_DESCRIPTORS; i++)
                 wl->tx_frames[i] = NULL;
 
@@ -2532,8 +2761,6 @@ struct ieee80211_hw *wl1271_alloc_hw(void)
         /* Apply default driver configuration. */
         wl1271_conf_init(wl);
 
-        wl1271_debugfs_init(wl);
-
         order = get_order(WL1271_AGGR_BUFFER_SIZE);
         wl->aggr_buf = (u8 *)__get_free_pages(GFP_KERNEL, order);
         if (!wl->aggr_buf) {
@@ -2610,6 +2837,11 @@ int wl1271_free_hw(struct wl1271 *wl)
 }
 EXPORT_SYMBOL_GPL(wl1271_free_hw);
 
+u32 wl12xx_debug_level;
+EXPORT_SYMBOL_GPL(wl12xx_debug_level);
+module_param_named(debug_level, wl12xx_debug_level, uint, DEBUG_NONE);
+MODULE_PARM_DESC(debug_level, "wl12xx debugging level");
+
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Luciano Coelho <luciano.coelho@nokia.com>");
 MODULE_AUTHOR("Juuso Oikarinen <juuso.oikarinen@nokia.com>");
diff --git a/drivers/net/wireless/wl12xx/wl1271_ps.c b/drivers/net/wireless/wl12xx/ps.c
index e3c332e2f97c..60a3738eadb0 100644
--- a/drivers/net/wireless/wl12xx/wl1271_ps.c
+++ b/drivers/net/wireless/wl12xx/ps.c
@@ -21,9 +21,9 @@
  *
  */
 
-#include "wl1271_reg.h"
-#include "wl1271_ps.h"
-#include "wl1271_io.h"
+#include "reg.h"
+#include "ps.h"
+#include "io.h"
 
 #define WL1271_WAKEUP_TIMEOUT 500
 
diff --git a/drivers/net/wireless/wl12xx/wl1271_ps.h b/drivers/net/wireless/wl12xx/ps.h
index 6ba7b032736f..8415060f08e5 100644
--- a/drivers/net/wireless/wl12xx/wl1271_ps.h
+++ b/drivers/net/wireless/wl12xx/ps.h
@@ -21,11 +21,11 @@
  *
  */
 
-#ifndef __WL1271_PS_H__
-#define __WL1271_PS_H__
+#ifndef __PS_H__
+#define __PS_H__
 
-#include "wl1271.h"
-#include "wl1271_acx.h"
+#include "wl12xx.h"
+#include "acx.h"
 
 int wl1271_ps_set_mode(struct wl1271 *wl, enum wl1271_cmd_ps_mode mode,
                        u32 rates, bool send);
diff --git a/drivers/net/wireless/wl12xx/wl1271_reg.h b/drivers/net/wireless/wl12xx/reg.h
index 990960771528..990960771528 100644
--- a/drivers/net/wireless/wl12xx/wl1271_reg.h
+++ b/drivers/net/wireless/wl12xx/reg.h
diff --git a/drivers/net/wireless/wl12xx/wl1271_rx.c b/drivers/net/wireless/wl12xx/rx.c
index bea133b6e489..682304c30b81 100644
--- a/drivers/net/wireless/wl12xx/wl1271_rx.c
+++ b/drivers/net/wireless/wl12xx/rx.c
@@ -23,11 +23,11 @@
 
 #include <linux/gfp.h>
 
-#include "wl1271.h"
-#include "wl1271_acx.h"
-#include "wl1271_reg.h"
-#include "wl1271_rx.h"
-#include "wl1271_io.h"
+#include "wl12xx.h"
+#include "acx.h"
+#include "reg.h"
+#include "rx.h"
+#include "io.h"
 
 static u8 wl1271_rx_get_mem_block(struct wl1271_fw_status *status,
                                   u32 drv_rx_counter)
@@ -48,10 +48,24 @@ static void wl1271_rx_status(struct wl1271 *wl,
                              struct ieee80211_rx_status *status,
                              u8 beacon)
 {
+        enum ieee80211_band desc_band;
+
         memset(status, 0, sizeof(struct ieee80211_rx_status));
 
         status->band = wl->band;
-        status->rate_idx = wl1271_rate_to_idx(wl, desc->rate);
+
+        if ((desc->flags & WL1271_RX_DESC_BAND_MASK) == WL1271_RX_DESC_BAND_BG)
+                desc_band = IEEE80211_BAND_2GHZ;
+        else
+                desc_band = IEEE80211_BAND_5GHZ;
+
+        status->rate_idx = wl1271_rate_to_idx(desc->rate, desc_band);
+
+#ifdef CONFIG_WL12XX_HT
+        /* 11n support */
+        if (desc->rate <= CONF_HW_RXTX_RATE_MCS0)
+                status->flag |= RX_FLAG_HT;
+#endif
 
         status->signal = desc->rssi;
 
@@ -170,10 +184,14 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status)
                 while (pkt_offset < buf_size) {
                         pkt_length = wl1271_rx_get_buf_size(status,
                                         drv_rx_counter);
-                        if (wl1271_rx_handle_data(wl,
-                                        wl->aggr_buf + pkt_offset,
-                                        pkt_length) < 0)
-                                break;
+                        /*
+                         * the handle data call can only fail in memory-outage
+                         * conditions, in that case the received frame will just
+                         * be dropped.
+                         */
+                        wl1271_rx_handle_data(wl,
+                                              wl->aggr_buf + pkt_offset,
+                                              pkt_length);
                         wl->rx_counter++;
                         drv_rx_counter++;
                         drv_rx_counter &= NUM_RX_PKT_DESC_MOD_MASK;
diff --git a/drivers/net/wireless/wl12xx/wl1271_rx.h b/drivers/net/wireless/wl12xx/rx.h
index 13a232333b13..3abb26fe0364 100644
--- a/drivers/net/wireless/wl12xx/wl1271_rx.h
+++ b/drivers/net/wireless/wl12xx/rx.h
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __WL1271_RX_H__
-#define __WL1271_RX_H__
+#ifndef __RX_H__
+#define __RX_H__
 
 #include <linux/bitops.h>
 
@@ -116,6 +116,6 @@ struct wl1271_rx_descriptor {
 } __packed;
 
 void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status);
-u8 wl1271_rate_to_idx(struct wl1271 *wl, int rate);
+u8 wl1271_rate_to_idx(int rate, enum ieee80211_band band);
 
 #endif
diff --git a/drivers/net/wireless/wl12xx/wl1271_scan.c b/drivers/net/wireless/wl12xx/scan.c
index 909bb47995b6..6f897b9d90ca 100644
--- a/drivers/net/wireless/wl12xx/wl1271_scan.c
+++ b/drivers/net/wireless/wl12xx/scan.c
@@ -23,10 +23,10 @@
 
 #include <linux/ieee80211.h>
 
-#include "wl1271.h"
-#include "wl1271_cmd.h"
-#include "wl1271_scan.h"
-#include "wl1271_acx.h"
+#include "wl12xx.h"
+#include "cmd.h"
+#include "scan.h"
+#include "acx.h"
 
 void wl1271_scan_complete_work(struct work_struct *work)
 {
@@ -48,14 +48,19 @@ void wl1271_scan_complete_work(struct work_struct *work)
         wl->scan.state = WL1271_SCAN_STATE_IDLE;
         kfree(wl->scan.scanned_ch);
         wl->scan.scanned_ch = NULL;
-        mutex_unlock(&wl->mutex);
-
+        wl->scan.req = NULL;
         ieee80211_scan_completed(wl->hw, false);
 
+        /* restore hardware connection monitoring template */
+        if (test_bit(WL1271_FLAG_STA_ASSOCIATED, &wl->flags))
+                wl1271_cmd_build_ap_probe_req(wl, wl->probereq);
+
         if (wl->scan.failed) {
                 wl1271_info("Scan completed due to error.");
                 ieee80211_queue_work(wl->hw, &wl->recovery_work);
         }
+        mutex_unlock(&wl->mutex);
+
 }
 
 
diff --git a/drivers/net/wireless/wl12xx/wl1271_scan.h b/drivers/net/wireless/wl12xx/scan.h
index 6d57127b5e6b..421a750add5a 100644
--- a/drivers/net/wireless/wl12xx/wl1271_scan.h
+++ b/drivers/net/wireless/wl12xx/scan.h
@@ -21,10 +21,10 @@
  *
  */
 
-#ifndef __WL1271_SCAN_H__
-#define __WL1271_SCAN_H__
+#ifndef __SCAN_H__
+#define __SCAN_H__
 
-#include "wl1271.h"
+#include "wl12xx.h"
 
 int wl1271_scan(struct wl1271 *wl, const u8 *ssid, size_t ssid_len,
                 struct cfg80211_scan_request *req);
diff --git a/drivers/net/wireless/wl12xx/wl1271_sdio.c b/drivers/net/wireless/wl12xx/sdio.c
index 784ef3432641..93cbb8d5aba9 100644
--- a/drivers/net/wireless/wl12xx/wl1271_sdio.c
+++ b/drivers/net/wireless/wl12xx/sdio.c
@@ -32,9 +32,9 @@
 #include <linux/wl12xx.h>
 #include <linux/pm_runtime.h>
 
-#include "wl1271.h"
+#include "wl12xx.h"
 #include "wl12xx_80211.h"
-#include "wl1271_io.h"
+#include "io.h"
 
 #ifndef SDIO_VENDOR_ID_TI
 #define SDIO_VENDOR_ID_TI               0x0097
diff --git a/drivers/net/wireless/wl12xx/sdio_test.c b/drivers/net/wireless/wl12xx/sdio_test.c
new file mode 100644
index 000000000000..9fcbd3dd8490
--- /dev/null
+++ b/drivers/net/wireless/wl12xx/sdio_test.c
@@ -0,0 +1,520 @@
+/*
+ * SDIO testing driver for wl12xx
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Contact: Roger Quadros <roger.quadros@nokia.com>
+ *
+ * wl12xx read/write routines taken from the main module
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/crc7.h>
+#include <linux/vmalloc.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/mmc/card.h>
+#include <linux/gpio.h>
+#include <linux/wl12xx.h>
+#include <linux/kthread.h>
+#include <linux/firmware.h>
+#include <linux/pm_runtime.h>
+
+#include "wl12xx.h"
+#include "io.h"
+#include "boot.h"
+
+#ifndef SDIO_VENDOR_ID_TI
+#define SDIO_VENDOR_ID_TI               0x0097
+#endif
+
+#ifndef SDIO_DEVICE_ID_TI_WL1271
+#define SDIO_DEVICE_ID_TI_WL1271        0x4076
+#endif
+
+static bool rx, tx;
+
+module_param(rx, bool, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(rx, "Perform rx test. Default (0). "
+        "This test continuously reads data from the SDIO device.\n");
+
+module_param(tx, bool, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(tx, "Perform tx test. Default (0). "
+        "This test continuously writes data to the SDIO device.\n");
+
+struct wl1271_test {
+        struct wl1271 wl;
+        struct task_struct *test_task;
+};
+
+static const struct sdio_device_id wl1271_devices[] = {
+        { SDIO_DEVICE(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271) },
+        {}
+};
+
+static inline struct sdio_func *wl_to_func(struct wl1271 *wl)
+{
+        return wl->if_priv;
+}
+
+static struct device *wl1271_sdio_wl_to_dev(struct wl1271 *wl)
+{
+        return &(wl_to_func(wl)->dev);
+}
+
+static void wl1271_sdio_raw_read(struct wl1271 *wl, int addr, void *buf,
+                size_t len, bool fixed)
+{
+        int ret = 0;
+        struct sdio_func *func = wl_to_func(wl);
+
+        if (unlikely(addr == HW_ACCESS_ELP_CTRL_REG_ADDR)) {
+                ((u8 *)buf)[0] = sdio_f0_readb(func, addr, &ret);
+                wl1271_debug(DEBUG_SDIO, "sdio read 52 addr 0x%x, byte 0x%02x",
+                                addr, ((u8 *)buf)[0]);
+        } else {
+                if (fixed)
+                        ret = sdio_readsb(func, buf, addr, len);
+                else
+                        ret = sdio_memcpy_fromio(func, buf, addr, len);
+
+                wl1271_debug(DEBUG_SDIO, "sdio read 53 addr 0x%x, %zu bytes",
+                                addr, len);
+                wl1271_dump_ascii(DEBUG_SDIO, "data: ", buf, len);
+        }
+
+        if (ret)
+                wl1271_error("sdio read failed (%d)", ret);
+}
+
+static void wl1271_sdio_raw_write(struct wl1271 *wl, int addr, void *buf,
+                size_t len, bool fixed)
+{
+        int ret = 0;
+        struct sdio_func *func = wl_to_func(wl);
+
+        if (unlikely(addr == HW_ACCESS_ELP_CTRL_REG_ADDR)) {
+                sdio_f0_writeb(func, ((u8 *)buf)[0], addr, &ret);
+                wl1271_debug(DEBUG_SDIO, "sdio write 52 addr 0x%x, byte 0x%02x",
+                                addr, ((u8 *)buf)[0]);
+        } else {
+                wl1271_debug(DEBUG_SDIO, "sdio write 53 addr 0x%x, %zu bytes",
+                                addr, len);
+                wl1271_dump_ascii(DEBUG_SDIO, "data: ", buf, len);
+
+                if (fixed)
+                        ret = sdio_writesb(func, addr, buf, len);
+                else
+                        ret = sdio_memcpy_toio(func, addr, buf, len);
+        }
+        if (ret)
+                wl1271_error("sdio write failed (%d)", ret);
+
+}
+
+static int wl1271_sdio_set_power(struct wl1271 *wl, bool enable)
+{
+        struct sdio_func *func = wl_to_func(wl);
+        int ret;
+
+        /* Let the SDIO stack handle wlan_enable control, so we
+         * keep host claimed while wlan is in use to keep wl1271
+         * alive.
+         */
+        if (enable) {
+                /* Power up the card */
+                ret = pm_runtime_get_sync(&func->dev);
+                if (ret < 0)
+                        goto out;
+                sdio_claim_host(func);
+                sdio_enable_func(func);
+                sdio_release_host(func);
+        } else {
+                sdio_claim_host(func);
+                sdio_disable_func(func);
+                sdio_release_host(func);
+
+                /* Power down the card */
+                ret = pm_runtime_put_sync(&func->dev);
+        }
+
+out:
+        return ret;
+}
+
+static void wl1271_sdio_disable_interrupts(struct wl1271 *wl)
+{
+}
+
+static void wl1271_sdio_enable_interrupts(struct wl1271 *wl)
+{
+}
+
+
+static struct wl1271_if_operations sdio_ops = {
+        .read           = wl1271_sdio_raw_read,
+        .write          = wl1271_sdio_raw_write,
+        .power          = wl1271_sdio_set_power,
+        .dev            = wl1271_sdio_wl_to_dev,
+        .enable_irq     = wl1271_sdio_enable_interrupts,
+        .disable_irq    = wl1271_sdio_disable_interrupts,
+};
+
+static void wl1271_fw_wakeup(struct wl1271 *wl)
+{
+        u32 elp_reg;
+
+        elp_reg = ELPCTRL_WAKE_UP;
+        wl1271_raw_write32(wl, HW_ACCESS_ELP_CTRL_REG_ADDR, elp_reg);
+}
+
+static int wl1271_fetch_firmware(struct wl1271 *wl)
+{
+        const struct firmware *fw;
+        int ret;
+
+        ret = request_firmware(&fw, WL1271_FW_NAME, wl1271_wl_to_dev(wl));
+
+        if (ret < 0) {
+                wl1271_error("could not get firmware: %d", ret);
+                return ret;
+        }
+
+        if (fw->size % 4) {
+                wl1271_error("firmware size is not multiple of 32 bits: %zu",
+                                fw->size);
+                ret = -EILSEQ;
+                goto out;
+        }
+
+        wl->fw_len = fw->size;
+        wl->fw = vmalloc(wl->fw_len);
+
+        if (!wl->fw) {
+                wl1271_error("could not allocate memory for the firmware");
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        memcpy(wl->fw, fw->data, wl->fw_len);
+
+        ret = 0;
+
+out:
+        release_firmware(fw);
+
+        return ret;
+}
+
+static int wl1271_fetch_nvs(struct wl1271 *wl)
+{
+        const struct firmware *fw;
+        int ret;
+
+        ret = request_firmware(&fw, WL1271_NVS_NAME, wl1271_wl_to_dev(wl));
+
+        if (ret < 0) {
+                wl1271_error("could not get nvs file: %d", ret);
+                return ret;
+        }
+
+        wl->nvs = kmemdup(fw->data, sizeof(struct wl1271_nvs_file), GFP_KERNEL);
+
+        if (!wl->nvs) {
+                wl1271_error("could not allocate memory for the nvs file");
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        wl->nvs_len = fw->size;
+
+out:
+        release_firmware(fw);
+
+        return ret;
+}
+
+static int wl1271_chip_wakeup(struct wl1271 *wl)
+{
+        struct wl1271_partition_set partition;
+        int ret;
+
+        msleep(WL1271_PRE_POWER_ON_SLEEP);
+        ret = wl1271_power_on(wl);
+        if (ret)
+                return ret;
+
+        msleep(WL1271_POWER_ON_SLEEP);
+
+        /* We don't need a real memory partition here, because we only want
+         * to use the registers at this point. */
+        memset(&partition, 0, sizeof(partition));
+        partition.reg.start = REGISTERS_BASE;
+        partition.reg.size = REGISTERS_DOWN_SIZE;
+        wl1271_set_partition(wl, &partition);
+
+        /* ELP module wake up */
+        wl1271_fw_wakeup(wl);
+
+        /* whal_FwCtrl_BootSm() */
+
+        /* 0. read chip id from CHIP_ID */
+        wl->chip.id = wl1271_read32(wl, CHIP_ID_B);
+
+        /* 1. check if chip id is valid */
+
+        switch (wl->chip.id) {
+        case CHIP_ID_1271_PG10:
+                wl1271_warning("chip id 0x%x (1271 PG10) support is obsolete",
+                                wl->chip.id);
+                break;
+        case CHIP_ID_1271_PG20:
+                wl1271_notice("chip id 0x%x (1271 PG20)",
+                                wl->chip.id);
+                break;
+        default:
+                wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
+                return -ENODEV;
+        }
+
+        return ret;
+}
+
+static struct wl1271_partition_set part_down = {
+        .mem = {
+                .start = 0x00000000,
+                .size  = 0x000177c0
+        },
+        .reg = {
+                .start = REGISTERS_BASE,
+                .size  = 0x00008800
+        },
+        .mem2 = {
+                .start = 0x00000000,
+                .size  = 0x00000000
+        },
+        .mem3 = {
+                .start = 0x00000000,
+                .size  = 0x00000000
+        },
+};
+
+static int tester(void *data)
+{
+        struct wl1271 *wl = data;
+        struct sdio_func *func = wl_to_func(wl);
+        struct device *pdev = &func->dev;
+        int ret = 0;
+        bool rx_started = 0;
+        bool tx_started = 0;
+        uint8_t *tx_buf, *rx_buf;
+        int test_size = PAGE_SIZE;
+        u32 addr = 0;
+        struct wl1271_partition_set partition;
+
+        /* We assume chip is powered up and firmware fetched */
+
+        memcpy(&partition, &part_down, sizeof(partition));
+        partition.mem.start = addr;
+        wl1271_set_partition(wl, &partition);
+
+        tx_buf = kmalloc(test_size, GFP_KERNEL);
+        rx_buf = kmalloc(test_size, GFP_KERNEL);
+        if (!tx_buf || !rx_buf) {
+                dev_err(pdev,
+                        "Could not allocate memory. Test will not run.\n");
+                ret = -ENOMEM;
+                goto free;
+        }
+
+        memset(tx_buf, 0x5a, test_size);
+
+        /* write something in data area so we can read it back */
+        wl1271_write(wl, addr, tx_buf, test_size, false);
+
+        while (!kthread_should_stop()) {
+                if (rx && !rx_started) {
+                        dev_info(pdev, "starting rx test\n");
+                        rx_started = 1;
+                } else if (!rx && rx_started) {
+                        dev_info(pdev, "stopping rx test\n");
+                        rx_started = 0;
+                }
+
+                if (tx && !tx_started) {
+                        dev_info(pdev, "starting tx test\n");
+                        tx_started = 1;
+                } else if (!tx && tx_started) {
+                        dev_info(pdev, "stopping tx test\n");
+                        tx_started = 0;
+                }
+
+                if (rx_started)
+                        wl1271_read(wl, addr, rx_buf, test_size, false);
+
+                if (tx_started)
+                        wl1271_write(wl, addr, tx_buf, test_size, false);
+
+                if (!rx_started && !tx_started)
+                        msleep(100);
+        }
+
+free:
+        kfree(tx_buf);
+        kfree(rx_buf);
+        return ret;
+}
+
+static int __devinit wl1271_probe(struct sdio_func *func,
+                const struct sdio_device_id *id)
+{
+        const struct wl12xx_platform_data *wlan_data;
+        struct wl1271 *wl;
+        struct wl1271_test *wl_test;
+        int ret = 0;
+
+        /* wl1271 has 2 sdio functions we handle just the wlan part */
+        if (func->num != 0x02)
+                return -ENODEV;
+
+        wl_test = kzalloc(sizeof(struct wl1271_test), GFP_KERNEL);
+        if (!wl_test) {
+                dev_err(&func->dev, "Could not allocate memory\n");
+                return -ENOMEM;
+        }
+
+        wl = &wl_test->wl;
+
+        wl->if_priv = func;
+        wl->if_ops = &sdio_ops;
+
+        /* Grab access to FN0 for ELP reg. */
+        func->card->quirks |= MMC_QUIRK_LENIENT_FN0;
+
+        wlan_data = wl12xx_get_platform_data();
+        if (IS_ERR(wlan_data)) {
+                ret = PTR_ERR(wlan_data);
+                dev_err(&func->dev, "missing wlan platform data: %d\n", ret);
+                goto out_free;
+        }
+
+        wl->irq = wlan_data->irq;
+        wl->ref_clock = wlan_data->board_ref_clock;
+
+        sdio_set_drvdata(func, wl_test);
+
+
+        /* power up the device */
+        ret = wl1271_chip_wakeup(wl);
+        if (ret) {
+                dev_err(&func->dev, "could not wake up chip\n");
+                goto out_free;
+        }
+
+        if (wl->fw == NULL) {
+                ret = wl1271_fetch_firmware(wl);
+                if (ret < 0) {
+                        dev_err(&func->dev, "firmware fetch error\n");
+                        goto out_off;
+                }
+        }
+
+        /* fetch NVS */
+        if (wl->nvs == NULL) {
+                ret = wl1271_fetch_nvs(wl);
+                if (ret < 0) {
+                        dev_err(&func->dev, "NVS fetch error\n");
+                        goto out_off;
+                }
+        }
+
+        ret = wl1271_load_firmware(wl);
+        if (ret < 0) {
+                dev_err(&func->dev, "firmware load error: %d\n", ret);
+                goto out_free;
+        }
+
+        dev_info(&func->dev, "initialized\n");
+
+        /* I/O testing will be done in the tester thread */
+
+        wl_test->test_task = kthread_run(tester, wl, "sdio_tester");
+        if (IS_ERR(wl_test->test_task)) {
+                dev_err(&func->dev, "unable to create kernel thread\n");
+                ret = PTR_ERR(wl_test->test_task);
+                goto out_free;
+        }
+
+        return 0;
+
+out_off:
+        /* power off the chip */
+        wl1271_power_off(wl);
+
+out_free:
+        kfree(wl_test);
+        return ret;
+}
+
+static void __devexit wl1271_remove(struct sdio_func *func)
+{
+        struct wl1271_test *wl_test = sdio_get_drvdata(func);
+
+        /* stop the I/O test thread */
+        kthread_stop(wl_test->test_task);
+
+        /* power off the chip */
+        wl1271_power_off(&wl_test->wl);
+
+        vfree(wl_test->wl.fw);
+        wl_test->wl.fw = NULL;
+        kfree(wl_test->wl.nvs);
+        wl_test->wl.nvs = NULL;
+
+        kfree(wl_test);
+}
+
+static struct sdio_driver wl1271_sdio_driver = {
+        .name           = "wl12xx_sdio_test",
+        .id_table       = wl1271_devices,
+        .probe          = wl1271_probe,
+        .remove         = __devexit_p(wl1271_remove),
+};
+
+static int __init wl1271_init(void)
+{
+        int ret;
+
+        ret = sdio_register_driver(&wl1271_sdio_driver);
+        if (ret < 0)
+                pr_err("failed to register sdio driver: %d\n", ret);
+
+        return ret;
+}
+module_init(wl1271_init);
+
+static void __exit wl1271_exit(void)
+{
+        sdio_unregister_driver(&wl1271_sdio_driver);
+}
+module_exit(wl1271_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Roger Quadros <roger.quadros@nokia.com>");
+
diff --git a/drivers/net/wireless/wl12xx/wl1271_spi.c b/drivers/net/wireless/wl12xx/spi.c
index ef801680773f..46714910f98c 100644
--- a/drivers/net/wireless/wl12xx/wl1271_spi.c
+++ b/drivers/net/wireless/wl12xx/spi.c
@@ -28,11 +28,11 @@
 #include <linux/wl12xx.h>
 #include <linux/slab.h>
 
-#include "wl1271.h"
+#include "wl12xx.h"
 #include "wl12xx_80211.h"
-#include "wl1271_io.h"
+#include "io.h"
 
-#include "wl1271_reg.h"
+#include "reg.h"
 
 #define WSPI_CMD_READ                 0x40000000
 #define WSPI_CMD_WRITE                0x00000000
diff --git a/drivers/net/wireless/wl12xx/wl1271_testmode.c b/drivers/net/wireless/wl12xx/testmode.c
index a3aa84386c88..e64403b6896d 100644
--- a/drivers/net/wireless/wl12xx/wl1271_testmode.c
+++ b/drivers/net/wireless/wl12xx/testmode.c
@@ -20,13 +20,13 @@
  * 02110-1301 USA
  *
  */
-#include "wl1271_testmode.h"
+#include "testmode.h"
 
 #include <linux/slab.h>
 #include <net/genetlink.h>
 
-#include "wl1271.h"
-#include "wl1271_acx.h"
+#include "wl12xx.h"
+#include "acx.h"
 
 #define WL1271_TM_MAX_DATA_LENGTH 1024
 
@@ -37,6 +37,7 @@ enum wl1271_tm_commands {
         WL1271_TM_CMD_CONFIGURE,
         WL1271_TM_CMD_NVS_PUSH,
         WL1271_TM_CMD_SET_PLT_MODE,
+        WL1271_TM_CMD_RECOVER,
 
         __WL1271_TM_CMD_AFTER_LAST
 };
@@ -248,6 +249,15 @@ static int wl1271_tm_cmd_set_plt_mode(struct wl1271 *wl, struct nlattr *tb[])
         return ret;
 }
 
+static int wl1271_tm_cmd_recover(struct wl1271 *wl, struct nlattr *tb[])
+{
+        wl1271_debug(DEBUG_TESTMODE, "testmode cmd recover");
+
+        ieee80211_queue_work(wl->hw, &wl->recovery_work);
+
+        return 0;
+}
+
 int wl1271_tm_cmd(struct ieee80211_hw *hw, void *data, int len)
 {
         struct wl1271 *wl = hw->priv;
@@ -272,6 +282,8 @@ int wl1271_tm_cmd(struct ieee80211_hw *hw, void *data, int len)
                 return wl1271_tm_cmd_nvs_push(wl, tb);
         case WL1271_TM_CMD_SET_PLT_MODE:
                 return wl1271_tm_cmd_set_plt_mode(wl, tb);
+        case WL1271_TM_CMD_RECOVER:
+                return wl1271_tm_cmd_recover(wl, tb);
         default:
                 return -EOPNOTSUPP;
         }
diff --git a/drivers/net/wireless/wl12xx/wl1271_testmode.h b/drivers/net/wireless/wl12xx/testmode.h
index c196d28f9d9d..8071654259ea 100644
--- a/drivers/net/wireless/wl12xx/wl1271_testmode.h
+++ b/drivers/net/wireless/wl12xx/testmode.h
@@ -21,8 +21,8 @@
  *
  */
 
-#ifndef __WL1271_TESTMODE_H__
-#define __WL1271_TESTMODE_H__
+#ifndef __TESTMODE_H__
+#define __TESTMODE_H__
 
 #include <net/mac80211.h>
 
diff --git a/drivers/net/wireless/wl12xx/wl1271_tx.c b/drivers/net/wireless/wl12xx/tx.c
index e3dc13c4d01a..b44c75cd8c1e 100644
--- a/drivers/net/wireless/wl12xx/wl1271_tx.c
+++ b/drivers/net/wireless/wl12xx/tx.c
@@ -24,23 +24,32 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 
-#include "wl1271.h"
-#include "wl1271_io.h"
-#include "wl1271_reg.h"
-#include "wl1271_ps.h"
-#include "wl1271_tx.h"
+#include "wl12xx.h"
+#include "io.h"
+#include "reg.h"
+#include "ps.h"
+#include "tx.h"
 
-static int wl1271_tx_id(struct wl1271 *wl, struct sk_buff *skb)
+static int wl1271_alloc_tx_id(struct wl1271 *wl, struct sk_buff *skb)
 {
-        int i;
-        for (i = 0; i < ACX_TX_DESCRIPTORS; i++)
-                if (wl->tx_frames[i] == NULL) {
-                        wl->tx_frames[i] = skb;
-                        wl->tx_frames_cnt++;
-                        return i;
-                }
+        int id;
+
+        id = find_first_zero_bit(wl->tx_frames_map, ACX_TX_DESCRIPTORS);
+        if (id >= ACX_TX_DESCRIPTORS)
+                return -EBUSY;
 
-        return -EBUSY;
+        __set_bit(id, wl->tx_frames_map);
+        wl->tx_frames[id] = skb;
+        wl->tx_frames_cnt++;
+        return id;
+}
+
+static void wl1271_free_tx_id(struct wl1271 *wl, int id)
+{
+        if (__test_and_clear_bit(id, wl->tx_frames_map)) {
+                wl->tx_frames[id] = NULL;
+                wl->tx_frames_cnt--;
+        }
 }
 
 static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra,
@@ -52,10 +61,10 @@ static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra,
         int id, ret = -EBUSY;
 
         if (buf_offset + total_len > WL1271_AGGR_BUFFER_SIZE)
-                return -EBUSY;
+                return -EAGAIN;
 
         /* allocate free identifier for the packet */
-        id = wl1271_tx_id(wl, skb);
+        id = wl1271_alloc_tx_id(wl, skb);
         if (id < 0)
                 return id;
 
@@ -79,8 +88,7 @@ static int wl1271_tx_allocate(struct wl1271 *wl, struct sk_buff *skb, u32 extra,
                              "tx_allocate: size: %d, blocks: %d, id: %d",
                              total_len, total_blocks, id);
         } else {
-                wl->tx_frames[id] = NULL;
-                wl->tx_frames_cnt--;
+                wl1271_free_tx_id(wl, id);
         }
 
         return ret;
@@ -117,7 +125,6 @@ static void wl1271_tx_fill_hdr(struct wl1271 *wl, struct sk_buff *skb,
         /* queue (we use same identifiers for tid's and ac's */
         ac = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
         desc->tid = ac;
-
         desc->aid = TX_HW_DEFAULT_AID;
         desc->reserved = 0;
 
@@ -201,42 +208,105 @@ u32 wl1271_tx_enabled_rates_get(struct wl1271 *wl, u32 rate_set)
                 rate_set >>= 1;
         }
 
+#ifdef CONFIG_WL12XX_HT
+        /* MCS rates indication are on bits 16 - 23 */
+        rate_set >>= HW_HT_RATES_OFFSET - band->n_bitrates;
+
+        for (bit = 0; bit < 8; bit++) {
+                if (rate_set & 0x1)
+                        enabled_rates |= (CONF_HW_BIT_RATE_MCS_0 << bit);
+                rate_set >>= 1;
+        }
+#endif
+
         return enabled_rates;
 }
 
-void wl1271_tx_work(struct work_struct *work)
+static void handle_tx_low_watermark(struct wl1271 *wl)
+{
+        unsigned long flags;
+
+        if (test_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags) &&
+            wl->tx_queue_count <= WL1271_TX_QUEUE_LOW_WATERMARK) {
+                /* firmware buffer has space, restart queues */
+                spin_lock_irqsave(&wl->wl_lock, flags);
+                ieee80211_wake_queues(wl->hw);
+                clear_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags);
+                spin_unlock_irqrestore(&wl->wl_lock, flags);
+        }
+}
+
+static struct sk_buff *wl1271_skb_dequeue(struct wl1271 *wl)
+{
+        struct sk_buff *skb = NULL;
+        unsigned long flags;
+
+        skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_VO]);
+        if (skb)
+                goto out;
+        skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_VI]);
+        if (skb)
+                goto out;
+        skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_BE]);
+        if (skb)
+                goto out;
+        skb = skb_dequeue(&wl->tx_queue[CONF_TX_AC_BK]);
+
+out:
+        if (skb) {
+                spin_lock_irqsave(&wl->wl_lock, flags);
+                wl->tx_queue_count--;
+                spin_unlock_irqrestore(&wl->wl_lock, flags);
+        }
+
+        return skb;
+}
+
+static void wl1271_skb_queue_head(struct wl1271 *wl, struct sk_buff *skb)
+{
+        unsigned long flags;
+        int q = wl1271_tx_get_queue(skb_get_queue_mapping(skb));
+
+        skb_queue_head(&wl->tx_queue[q], skb);
+        spin_lock_irqsave(&wl->wl_lock, flags);
+        wl->tx_queue_count++;
+        spin_unlock_irqrestore(&wl->wl_lock, flags);
+}
+
+void wl1271_tx_work_locked(struct wl1271 *wl)
 {
-        struct wl1271 *wl = container_of(work, struct wl1271, tx_work);
         struct sk_buff *skb;
         bool woken_up = false;
         u32 sta_rates = 0;
-        u32 buf_offset;
+        u32 buf_offset = 0;
+        bool sent_packets = false;
         int ret;
 
         /* check if the rates supported by the AP have changed */
         if (unlikely(test_and_clear_bit(WL1271_FLAG_STA_RATES_CHANGED,
                                         &wl->flags))) {
                 unsigned long flags;
+
                 spin_lock_irqsave(&wl->wl_lock, flags);
                 sta_rates = wl->sta_rate_set;
                 spin_unlock_irqrestore(&wl->wl_lock, flags);
         }
 
-        mutex_lock(&wl->mutex);
-
         if (unlikely(wl->state == WL1271_STATE_OFF))
                 goto out;
 
         /* if rates have changed, re-configure the rate policy */
         if (unlikely(sta_rates)) {
+                ret = wl1271_ps_elp_wakeup(wl, false);
+                if (ret < 0)
+                        goto out;
+                woken_up = true;
+
                 wl->rate_set = wl1271_tx_enabled_rates_get(wl, sta_rates);
                 wl1271_acx_rate_policies(wl);
         }
 
-        /* Prepare the transfer buffer, by aggregating all
-         * available packets */
-        buf_offset = 0;
-        while ((skb = skb_dequeue(&wl->tx_queue))) {
+        while ((skb = wl1271_skb_dequeue(wl))) {
                 if (!woken_up) {
                         ret = wl1271_ps_elp_wakeup(wl, false);
                         if (ret < 0)
@@ -245,13 +315,25 @@ void wl1271_tx_work(struct work_struct *work)
                 }
 
                 ret = wl1271_prepare_tx_frame(wl, skb, buf_offset);
-                if (ret == -EBUSY) {
+                if (ret == -EAGAIN) {
+                        /*
+                         * Aggregation buffer is full.
+                         * Flush buffer and try again.
+                         */
+                        wl1271_skb_queue_head(wl, skb);
+                        wl1271_write(wl, WL1271_SLV_MEM_DATA, wl->aggr_buf,
+                                     buf_offset, true);
+                        sent_packets = true;
+                        buf_offset = 0;
+                        continue;
+                } else if (ret == -EBUSY) {
                         /*
-                         * Either the firmware buffer is full, or the
-                         * aggregation buffer is.
+                         * Firmware buffer is full.
                          * Queue back last skb, and stop aggregating.
                          */
-                        skb_queue_head(&wl->tx_queue, skb);
+                        wl1271_skb_queue_head(wl, skb);
+                        /* No work left, avoid scheduling redundant tx work */
+                        set_bit(WL1271_FLAG_FW_TX_BUSY, &wl->flags);
                         goto out_ack;
                 } else if (ret < 0) {
                         dev_kfree_skb(skb);
@@ -265,14 +347,25 @@ out_ack:
         if (buf_offset) {
                 wl1271_write(wl, WL1271_SLV_MEM_DATA, wl->aggr_buf,
                                 buf_offset, true);
+                sent_packets = true;
+        }
+        if (sent_packets) {
                 /* interrupt the firmware with the new packets */
                 wl1271_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count);
+                handle_tx_low_watermark(wl);
         }
 
 out:
         if (woken_up)
                 wl1271_ps_elp_sleep(wl);
+}
 
+void wl1271_tx_work(struct work_struct *work)
+{
+        struct wl1271 *wl = container_of(work, struct wl1271, tx_work);
+
+        mutex_lock(&wl->mutex);
+        wl1271_tx_work_locked(wl);
         mutex_unlock(&wl->mutex);
 }
 
@@ -298,7 +391,7 @@ static void wl1271_tx_complete_packet(struct wl1271 *wl,
         if (result->status == TX_SUCCESS) {
                 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK))
                         info->flags |= IEEE80211_TX_STAT_ACK;
-                rate = wl1271_rate_to_idx(wl, result->rate_class_index);
+                rate = wl1271_rate_to_idx(result->rate_class_index, wl->band);
                 retries = result->ack_failures;
         } else if (result->status == TX_RETRY_EXCEEDED) {
                 wl->stats.excessive_retries++;
@@ -335,8 +428,7 @@ static void wl1271_tx_complete_packet(struct wl1271 *wl,
 
         /* return the packet to the stack */
         ieee80211_tx_status(wl->hw, skb);
-        wl->tx_frames[result->id] = NULL;
-        wl->tx_frames_cnt--;
+        wl1271_free_tx_id(wl, result->id);
 }
 
 /* Called upon reception of a TX complete interrupt */
@@ -375,19 +467,6 @@ void wl1271_tx_complete(struct wl1271 *wl)
 
                 wl->tx_results_count++;
         }
-
-        if (test_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags) &&
-            skb_queue_len(&wl->tx_queue) <= WL1271_TX_QUEUE_LOW_WATERMARK) {
-                unsigned long flags;
-
-                /* firmware buffer has space, restart queues */
-                wl1271_debug(DEBUG_TX, "tx_complete: waking queues");
-                spin_lock_irqsave(&wl->wl_lock, flags);
-                ieee80211_wake_queues(wl->hw);
-                clear_bit(WL1271_FLAG_TX_QUEUE_STOPPED, &wl->flags);
-                spin_unlock_irqrestore(&wl->wl_lock, flags);
-                ieee80211_queue_work(wl->hw, &wl->tx_work);
-        }
 }
 
 /* caller must hold wl->mutex */
@@ -397,19 +476,27 @@ void wl1271_tx_reset(struct wl1271 *wl)
         struct sk_buff *skb;
 
         /* TX failure */
-        while ((skb = skb_dequeue(&wl->tx_queue))) {
-                wl1271_debug(DEBUG_TX, "freeing skb 0x%p", skb);
-                ieee80211_tx_status(wl->hw, skb);
+        for (i = 0; i < NUM_TX_QUEUES; i++) {
+                while ((skb = skb_dequeue(&wl->tx_queue[i]))) {
+                        wl1271_debug(DEBUG_TX, "freeing skb 0x%p", skb);
+                        ieee80211_tx_status(wl->hw, skb);
+                }
         }
+        wl->tx_queue_count = 0;
+
+        /*
+         * Make sure the driver is at a consistent state, in case this
+         * function is called from a context other than interface removal.
+         */
+        handle_tx_low_watermark(wl);
 
         for (i = 0; i < ACX_TX_DESCRIPTORS; i++)
                 if (wl->tx_frames[i] != NULL) {
                         skb = wl->tx_frames[i];
-                        wl->tx_frames[i] = NULL;
+                        wl1271_free_tx_id(wl, i);
                         wl1271_debug(DEBUG_TX, "freeing skb 0x%p", skb);
                         ieee80211_tx_status(wl->hw, skb);
                 }
-        wl->tx_frames_cnt = 0;
 }
 
 #define WL1271_TX_FLUSH_TIMEOUT 500000
@@ -424,8 +511,7 @@ void wl1271_tx_flush(struct wl1271 *wl)
                 mutex_lock(&wl->mutex);
                 wl1271_debug(DEBUG_TX, "flushing tx buffer: %d",
                              wl->tx_frames_cnt);
-                if ((wl->tx_frames_cnt == 0) &&
-                    skb_queue_empty(&wl->tx_queue)) {
+                if ((wl->tx_frames_cnt == 0) && (wl->tx_queue_count == 0)) {
                         mutex_unlock(&wl->mutex);
                         return;
                 }
diff --git a/drivers/net/wireless/wl12xx/wl1271_tx.h b/drivers/net/wireless/wl12xx/tx.h
index d12a129ad11c..903e5dc69b7a 100644
--- a/drivers/net/wireless/wl12xx/wl1271_tx.h
+++ b/drivers/net/wireless/wl12xx/tx.h
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __WL1271_TX_H__
-#define __WL1271_TX_H__
+#ifndef __TX_H__
+#define __TX_H__
 
 #define TX_HW_BLOCK_SPARE                2
 #define TX_HW_BLOCK_SIZE                 252
@@ -140,10 +140,11 @@ static inline int wl1271_tx_get_queue(int queue)
 }
 
 void wl1271_tx_work(struct work_struct *work);
+void wl1271_tx_work_locked(struct wl1271 *wl);
 void wl1271_tx_complete(struct wl1271 *wl);
 void wl1271_tx_reset(struct wl1271 *wl);
 void wl1271_tx_flush(struct wl1271 *wl);
-u8 wl1271_rate_to_idx(struct wl1271 *wl, int rate);
+u8 wl1271_rate_to_idx(int rate, enum ieee80211_band band);
 u32 wl1271_tx_enabled_rates_get(struct wl1271 *wl, u32 rate_set);
 
 #endif
diff --git a/drivers/net/wireless/wl12xx/wl1271_debugfs.c b/drivers/net/wireless/wl12xx/wl1271_debugfs.c
deleted file mode 100644
index 66c2b90ddfd4..000000000000
--- a/drivers/net/wireless/wl12xx/wl1271_debugfs.c
+++ /dev/null
@@ -1,583 +0,0 @@
-/*
- * This file is part of wl1271
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * Contact: Luciano Coelho <luciano.coelho@nokia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include "wl1271_debugfs.h"
-
-#include <linux/skbuff.h>
-#include <linux/slab.h>
-
-#include "wl1271.h"
-#include "wl1271_acx.h"
-#include "wl1271_ps.h"
-#include "wl1271_io.h"
-
-/* ms */
-#define WL1271_DEBUGFS_STATS_LIFETIME 1000
-
-/* debugfs macros idea from mac80211 */
-
-#define DEBUGFS_READONLY_FILE(name, buflen, fmt, value...)              \
-static ssize_t name## _read(struct file *file, char __user *userbuf,    \
-                            size_t count, loff_t *ppos)                 \
-{                                                                       \
-        struct wl1271 *wl = file->private_data;                         \
-        char buf[buflen];                                               \
-        int res;                                                        \
-                                                                        \
-        res = scnprintf(buf, buflen, fmt "\n", ##value);                \
-        return simple_read_from_buffer(userbuf, count, ppos, buf, res); \
-}                                                                       \
-                                                                        \
-static const struct file_operations name## _ops = {                     \
-        .read = name## _read,                                           \
-        .open = wl1271_open_file_generic,                               \
-        .llseek = generic_file_llseek,                                  \
-};
-
-#define DEBUGFS_ADD(name, parent)                                       \
-        wl->debugfs.name = debugfs_create_file(#name, 0400, parent,     \
-                                               wl, &name## _ops);       \
-        if (IS_ERR(wl->debugfs.name)) {                                 \
-                ret = PTR_ERR(wl->debugfs.name);                        \
-                wl->debugfs.name = NULL;                                \
-                goto out;                                               \
-        }
-
-#define DEBUGFS_DEL(name)                                               \
-        do {                                                            \
-                debugfs_remove(wl->debugfs.name);                       \
-                wl->debugfs.name = NULL;                                \
-        } while (0)
-
-#define DEBUGFS_FWSTATS_FILE(sub, name, buflen, fmt)                    \
-static ssize_t sub## _ ##name## _read(struct file *file,                \
-                                      char __user *userbuf,             \
-                                      size_t count, loff_t *ppos)       \
-{                                                                       \
-        struct wl1271 *wl = file->private_data;                         \
-        char buf[buflen];                                               \
-        int res;                                                        \
-                                                                        \
-        wl1271_debugfs_update_stats(wl);                                \
-                                                                        \
-        res = scnprintf(buf, buflen, fmt "\n",                          \
-                        wl->stats.fw_stats->sub.name);                  \
-        return simple_read_from_buffer(userbuf, count, ppos, buf, res); \
-}                                                                       \
-                                                                        \
-static const struct file_operations sub## _ ##name## _ops = {           \
-        .read = sub## _ ##name## _read,                                 \
-        .open = wl1271_open_file_generic,                               \
-        .llseek = generic_file_llseek,                                  \
-};
-
-#define DEBUGFS_FWSTATS_ADD(sub, name)                          \
-        DEBUGFS_ADD(sub## _ ##name, wl->debugfs.fw_statistics)
-
-#define DEBUGFS_FWSTATS_DEL(sub, name)                          \
-        DEBUGFS_DEL(sub## _ ##name)
-
-static void wl1271_debugfs_update_stats(struct wl1271 *wl)
-{
-        int ret;
-
-        mutex_lock(&wl->mutex);
-
-        ret = wl1271_ps_elp_wakeup(wl, false);
-        if (ret < 0)
-                goto out;
-
-        if (wl->state == WL1271_STATE_ON &&
-            time_after(jiffies, wl->stats.fw_stats_update +
-                       msecs_to_jiffies(WL1271_DEBUGFS_STATS_LIFETIME))) {
-                wl1271_acx_statistics(wl, wl->stats.fw_stats);
-                wl->stats.fw_stats_update = jiffies;
-        }
-
-        wl1271_ps_elp_sleep(wl);
-
-out:
-        mutex_unlock(&wl->mutex);
-}
-
-static int wl1271_open_file_generic(struct inode *inode, struct file *file)
-{
-        file->private_data = inode->i_private;
-        return 0;
-}
-
-DEBUGFS_FWSTATS_FILE(tx, internal_desc_overflow, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(rx, out_of_mem, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, hdr_overflow, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, hw_stuck, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, dropped, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, fcs_err, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, xfr_hint_trig, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, path_reset, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rx, reset_counter, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(dma, rx_requested, 20, "%u");
-DEBUGFS_FWSTATS_FILE(dma, rx_errors, 20, "%u");
-DEBUGFS_FWSTATS_FILE(dma, tx_requested, 20, "%u");
-DEBUGFS_FWSTATS_FILE(dma, tx_errors, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(isr, cmd_cmplt, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, fiqs, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, rx_headers, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, rx_mem_overflow, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, rx_rdys, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, irqs, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, tx_procs, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, decrypt_done, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, dma0_done, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, dma1_done, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, tx_exch_complete, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, commands, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, rx_procs, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, hw_pm_mode_changes, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, host_acknowledges, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, pci_pm, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, wakeups, 20, "%u");
-DEBUGFS_FWSTATS_FILE(isr, low_rssi, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(wep, addr_key_count, 20, "%u");
-DEBUGFS_FWSTATS_FILE(wep, default_key_count, 20, "%u");
-/* skipping wep.reserved */
-DEBUGFS_FWSTATS_FILE(wep, key_not_found, 20, "%u");
-DEBUGFS_FWSTATS_FILE(wep, decrypt_fail, 20, "%u");
-DEBUGFS_FWSTATS_FILE(wep, packets, 20, "%u");
-DEBUGFS_FWSTATS_FILE(wep, interrupt, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(pwr, ps_enter, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, elp_enter, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, missing_bcns, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, wake_on_host, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, wake_on_timer_exp, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, tx_with_ps, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, tx_without_ps, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, rcvd_beacons, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, power_save_off, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, enable_ps, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, disable_ps, 20, "%u");
-DEBUGFS_FWSTATS_FILE(pwr, fix_tsf_ps, 20, "%u");
-/* skipping cont_miss_bcns_spread for now */
-DEBUGFS_FWSTATS_FILE(pwr, rcvd_awake_beacons, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(mic, rx_pkts, 20, "%u");
-DEBUGFS_FWSTATS_FILE(mic, calc_failure, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(aes, encrypt_fail, 20, "%u");
-DEBUGFS_FWSTATS_FILE(aes, decrypt_fail, 20, "%u");
-DEBUGFS_FWSTATS_FILE(aes, encrypt_packets, 20, "%u");
-DEBUGFS_FWSTATS_FILE(aes, decrypt_packets, 20, "%u");
-DEBUGFS_FWSTATS_FILE(aes, encrypt_interrupt, 20, "%u");
-DEBUGFS_FWSTATS_FILE(aes, decrypt_interrupt, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(event, heart_beat, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, calibration, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, rx_mismatch, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, rx_mem_empty, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, rx_pool, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, oom_late, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, phy_transmit_error, 20, "%u");
-DEBUGFS_FWSTATS_FILE(event, tx_stuck, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(ps, pspoll_timeouts, 20, "%u");
-DEBUGFS_FWSTATS_FILE(ps, upsd_timeouts, 20, "%u");
-DEBUGFS_FWSTATS_FILE(ps, upsd_max_sptime, 20, "%u");
-DEBUGFS_FWSTATS_FILE(ps, upsd_max_apturn, 20, "%u");
-DEBUGFS_FWSTATS_FILE(ps, pspoll_max_apturn, 20, "%u");
-DEBUGFS_FWSTATS_FILE(ps, pspoll_utilization, 20, "%u");
-DEBUGFS_FWSTATS_FILE(ps, upsd_utilization, 20, "%u");
-
-DEBUGFS_FWSTATS_FILE(rxpipe, rx_prep_beacon_drop, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rxpipe, descr_host_int_trig_rx_data, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rxpipe, beacon_buffer_thres_host_int_trig_rx_data,
-                     20, "%u");
-DEBUGFS_FWSTATS_FILE(rxpipe, missed_beacon_host_int_trig_rx_data, 20, "%u");
-DEBUGFS_FWSTATS_FILE(rxpipe, tx_xfr_host_int_trig_rx_data, 20, "%u");
-
-DEBUGFS_READONLY_FILE(retry_count, 20, "%u", wl->stats.retry_count);
-DEBUGFS_READONLY_FILE(excessive_retries, 20, "%u",
-                      wl->stats.excessive_retries);
-
-static ssize_t tx_queue_len_read(struct file *file, char __user *userbuf,
-                                 size_t count, loff_t *ppos)
-{
-        struct wl1271 *wl = file->private_data;
-        u32 queue_len;
-        char buf[20];
-        int res;
-
-        queue_len = skb_queue_len(&wl->tx_queue);
-
-        res = scnprintf(buf, sizeof(buf), "%u\n", queue_len);
-        return simple_read_from_buffer(userbuf, count, ppos, buf, res);
-}
-
-static const struct file_operations tx_queue_len_ops = {
-        .read = tx_queue_len_read,
-        .open = wl1271_open_file_generic,
-        .llseek = default_llseek,
-};
-
-static ssize_t gpio_power_read(struct file *file, char __user *user_buf,
-                          size_t count, loff_t *ppos)
-{
-        struct wl1271 *wl = file->private_data;
-        bool state = test_bit(WL1271_FLAG_GPIO_POWER, &wl->flags);
-
-        int res;
-        char buf[10];
-
-        res = scnprintf(buf, sizeof(buf), "%d\n", state);
-
-        return simple_read_from_buffer(user_buf, count, ppos, buf, res);
-}
-
-static ssize_t gpio_power_write(struct file *file,
-                           const char __user *user_buf,
-                           size_t count, loff_t *ppos)
-{
-        struct wl1271 *wl = file->private_data;
-        char buf[10];
-        size_t len;
-        unsigned long value;
-        int ret;
-
-        mutex_lock(&wl->mutex);
-
-        len = min(count, sizeof(buf) - 1);
-        if (copy_from_user(buf, user_buf, len)) {
-                ret = -EFAULT;
-                goto out;
-        }
-        buf[len] = '\0';
-
-        ret = strict_strtoul(buf, 0, &value);
-        if (ret < 0) {
-                wl1271_warning("illegal value in gpio_power");
-                goto out;
-        }
-
-        if (value)
-                wl1271_power_on(wl);
-        else
-                wl1271_power_off(wl);
-
-out:
-        mutex_unlock(&wl->mutex);
-        return count;
-}
-
-static const struct file_operations gpio_power_ops = {
-        .read = gpio_power_read,
-        .write = gpio_power_write,
-        .open = wl1271_open_file_generic,
-        .llseek = default_llseek,
-};
-
-static void wl1271_debugfs_delete_files(struct wl1271 *wl)
-{
-        DEBUGFS_FWSTATS_DEL(tx, internal_desc_overflow);
-
-        DEBUGFS_FWSTATS_DEL(rx, out_of_mem);
-        DEBUGFS_FWSTATS_DEL(rx, hdr_overflow);
-        DEBUGFS_FWSTATS_DEL(rx, hw_stuck);
-        DEBUGFS_FWSTATS_DEL(rx, dropped);
-        DEBUGFS_FWSTATS_DEL(rx, fcs_err);
-        DEBUGFS_FWSTATS_DEL(rx, xfr_hint_trig);
-        DEBUGFS_FWSTATS_DEL(rx, path_reset);
-        DEBUGFS_FWSTATS_DEL(rx, reset_counter);
-
-        DEBUGFS_FWSTATS_DEL(dma, rx_requested);
-        DEBUGFS_FWSTATS_DEL(dma, rx_errors);
-        DEBUGFS_FWSTATS_DEL(dma, tx_requested);
-        DEBUGFS_FWSTATS_DEL(dma, tx_errors);
-
-        DEBUGFS_FWSTATS_DEL(isr, cmd_cmplt);
-        DEBUGFS_FWSTATS_DEL(isr, fiqs);
-        DEBUGFS_FWSTATS_DEL(isr, rx_headers);
-        DEBUGFS_FWSTATS_DEL(isr, rx_mem_overflow);
-        DEBUGFS_FWSTATS_DEL(isr, rx_rdys);
-        DEBUGFS_FWSTATS_DEL(isr, irqs);
-        DEBUGFS_FWSTATS_DEL(isr, tx_procs);
-        DEBUGFS_FWSTATS_DEL(isr, decrypt_done);
-        DEBUGFS_FWSTATS_DEL(isr, dma0_done);
-        DEBUGFS_FWSTATS_DEL(isr, dma1_done);
-        DEBUGFS_FWSTATS_DEL(isr, tx_exch_complete);
-        DEBUGFS_FWSTATS_DEL(isr, commands);
-        DEBUGFS_FWSTATS_DEL(isr, rx_procs);
-        DEBUGFS_FWSTATS_DEL(isr, hw_pm_mode_changes);
-        DEBUGFS_FWSTATS_DEL(isr, host_acknowledges);
-        DEBUGFS_FWSTATS_DEL(isr, pci_pm);
-        DEBUGFS_FWSTATS_DEL(isr, wakeups);
-        DEBUGFS_FWSTATS_DEL(isr, low_rssi);
-
-        DEBUGFS_FWSTATS_DEL(wep, addr_key_count);
-        DEBUGFS_FWSTATS_DEL(wep, default_key_count);
-        /* skipping wep.reserved */
-        DEBUGFS_FWSTATS_DEL(wep, key_not_found);
-        DEBUGFS_FWSTATS_DEL(wep, decrypt_fail);
-        DEBUGFS_FWSTATS_DEL(wep, packets);
-        DEBUGFS_FWSTATS_DEL(wep, interrupt);
-
-        DEBUGFS_FWSTATS_DEL(pwr, ps_enter);
-        DEBUGFS_FWSTATS_DEL(pwr, elp_enter);
-        DEBUGFS_FWSTATS_DEL(pwr, missing_bcns);
-        DEBUGFS_FWSTATS_DEL(pwr, wake_on_host);
-        DEBUGFS_FWSTATS_DEL(pwr, wake_on_timer_exp);
-        DEBUGFS_FWSTATS_DEL(pwr, tx_with_ps);
-        DEBUGFS_FWSTATS_DEL(pwr, tx_without_ps);
-        DEBUGFS_FWSTATS_DEL(pwr, rcvd_beacons);
-        DEBUGFS_FWSTATS_DEL(pwr, power_save_off);
-        DEBUGFS_FWSTATS_DEL(pwr, enable_ps);
-        DEBUGFS_FWSTATS_DEL(pwr, disable_ps);
-        DEBUGFS_FWSTATS_DEL(pwr, fix_tsf_ps);
-        /* skipping cont_miss_bcns_spread for now */
-        DEBUGFS_FWSTATS_DEL(pwr, rcvd_awake_beacons);
-
-        DEBUGFS_FWSTATS_DEL(mic, rx_pkts);
-        DEBUGFS_FWSTATS_DEL(mic, calc_failure);
-
-        DEBUGFS_FWSTATS_DEL(aes, encrypt_fail);
-        DEBUGFS_FWSTATS_DEL(aes, decrypt_fail);
-        DEBUGFS_FWSTATS_DEL(aes, encrypt_packets);
-        DEBUGFS_FWSTATS_DEL(aes, decrypt_packets);
-        DEBUGFS_FWSTATS_DEL(aes, encrypt_interrupt);
-        DEBUGFS_FWSTATS_DEL(aes, decrypt_interrupt);
-
-        DEBUGFS_FWSTATS_DEL(event, heart_beat);
-        DEBUGFS_FWSTATS_DEL(event, calibration);
-        DEBUGFS_FWSTATS_DEL(event, rx_mismatch);
-        DEBUGFS_FWSTATS_DEL(event, rx_mem_empty);
-        DEBUGFS_FWSTATS_DEL(event, rx_pool);
-        DEBUGFS_FWSTATS_DEL(event, oom_late);
-        DEBUGFS_FWSTATS_DEL(event, phy_transmit_error);
-        DEBUGFS_FWSTATS_DEL(event, tx_stuck);
-
-        DEBUGFS_FWSTATS_DEL(ps, pspoll_timeouts);
-        DEBUGFS_FWSTATS_DEL(ps, upsd_timeouts);
-        DEBUGFS_FWSTATS_DEL(ps, upsd_max_sptime);
-        DEBUGFS_FWSTATS_DEL(ps, upsd_max_apturn);
-        DEBUGFS_FWSTATS_DEL(ps, pspoll_max_apturn);
-        DEBUGFS_FWSTATS_DEL(ps, pspoll_utilization);
-        DEBUGFS_FWSTATS_DEL(ps, upsd_utilization);
-
-        DEBUGFS_FWSTATS_DEL(rxpipe, rx_prep_beacon_drop);
-        DEBUGFS_FWSTATS_DEL(rxpipe, descr_host_int_trig_rx_data);
-        DEBUGFS_FWSTATS_DEL(rxpipe, beacon_buffer_thres_host_int_trig_rx_data);
-        DEBUGFS_FWSTATS_DEL(rxpipe, missed_beacon_host_int_trig_rx_data);
-        DEBUGFS_FWSTATS_DEL(rxpipe, tx_xfr_host_int_trig_rx_data);
-
-        DEBUGFS_DEL(tx_queue_len);
-        DEBUGFS_DEL(retry_count);
-        DEBUGFS_DEL(excessive_retries);
-
-        DEBUGFS_DEL(gpio_power);
-}
-
-static int wl1271_debugfs_add_files(struct wl1271 *wl)
-{
-        int ret = 0;
-
-        DEBUGFS_FWSTATS_ADD(tx, internal_desc_overflow);
-
-        DEBUGFS_FWSTATS_ADD(rx, out_of_mem);
-        DEBUGFS_FWSTATS_ADD(rx, hdr_overflow);
-        DEBUGFS_FWSTATS_ADD(rx, hw_stuck);
-        DEBUGFS_FWSTATS_ADD(rx, dropped);
-        DEBUGFS_FWSTATS_ADD(rx, fcs_err);
-        DEBUGFS_FWSTATS_ADD(rx, xfr_hint_trig);
-        DEBUGFS_FWSTATS_ADD(rx, path_reset);
-        DEBUGFS_FWSTATS_ADD(rx, reset_counter);
-
-        DEBUGFS_FWSTATS_ADD(dma, rx_requested);
-        DEBUGFS_FWSTATS_ADD(dma, rx_errors);
-        DEBUGFS_FWSTATS_ADD(dma, tx_requested);
-        DEBUGFS_FWSTATS_ADD(dma, tx_errors);
-
-        DEBUGFS_FWSTATS_ADD(isr, cmd_cmplt);
-        DEBUGFS_FWSTATS_ADD(isr, fiqs);
-        DEBUGFS_FWSTATS_ADD(isr, rx_headers);
-        DEBUGFS_FWSTATS_ADD(isr, rx_mem_overflow);
-        DEBUGFS_FWSTATS_ADD(isr, rx_rdys);
-        DEBUGFS_FWSTATS_ADD(isr, irqs);
-        DEBUGFS_FWSTATS_ADD(isr, tx_procs);
-        DEBUGFS_FWSTATS_ADD(isr, decrypt_done);
-        DEBUGFS_FWSTATS_ADD(isr, dma0_done);
-        DEBUGFS_FWSTATS_ADD(isr, dma1_done);
-        DEBUGFS_FWSTATS_ADD(isr, tx_exch_complete);
-        DEBUGFS_FWSTATS_ADD(isr, commands);
-        DEBUGFS_FWSTATS_ADD(isr, rx_procs);
-        DEBUGFS_FWSTATS_ADD(isr, hw_pm_mode_changes);
-        DEBUGFS_FWSTATS_ADD(isr, host_acknowledges);
-        DEBUGFS_FWSTATS_ADD(isr, pci_pm);
-        DEBUGFS_FWSTATS_ADD(isr, wakeups);
-        DEBUGFS_FWSTATS_ADD(isr, low_rssi);
-
-        DEBUGFS_FWSTATS_ADD(wep, addr_key_count);
-        DEBUGFS_FWSTATS_ADD(wep, default_key_count);
-        /* skipping wep.reserved */
-        DEBUGFS_FWSTATS_ADD(wep, key_not_found);
-        DEBUGFS_FWSTATS_ADD(wep, decrypt_fail);
-        DEBUGFS_FWSTATS_ADD(wep, packets);
-        DEBUGFS_FWSTATS_ADD(wep, interrupt);
-
-        DEBUGFS_FWSTATS_ADD(pwr, ps_enter);
-        DEBUGFS_FWSTATS_ADD(pwr, elp_enter);
-        DEBUGFS_FWSTATS_ADD(pwr, missing_bcns);
-        DEBUGFS_FWSTATS_ADD(pwr, wake_on_host);
-        DEBUGFS_FWSTATS_ADD(pwr, wake_on_timer_exp);
-        DEBUGFS_FWSTATS_ADD(pwr, tx_with_ps);
-        DEBUGFS_FWSTATS_ADD(pwr, tx_without_ps);
-        DEBUGFS_FWSTATS_ADD(pwr, rcvd_beacons);
-        DEBUGFS_FWSTATS_ADD(pwr, power_save_off);
-        DEBUGFS_FWSTATS_ADD(pwr, enable_ps);
-        DEBUGFS_FWSTATS_ADD(pwr, disable_ps);
-        DEBUGFS_FWSTATS_ADD(pwr, fix_tsf_ps);
-        /* skipping cont_miss_bcns_spread for now */
-        DEBUGFS_FWSTATS_ADD(pwr, rcvd_awake_beacons);
-
-        DEBUGFS_FWSTATS_ADD(mic, rx_pkts);
-        DEBUGFS_FWSTATS_ADD(mic, calc_failure);
-
-        DEBUGFS_FWSTATS_ADD(aes, encrypt_fail);
-        DEBUGFS_FWSTATS_ADD(aes, decrypt_fail);
-        DEBUGFS_FWSTATS_ADD(aes, encrypt_packets);
-        DEBUGFS_FWSTATS_ADD(aes, decrypt_packets);
-        DEBUGFS_FWSTATS_ADD(aes, encrypt_interrupt);
-        DEBUGFS_FWSTATS_ADD(aes, decrypt_interrupt);
-
-        DEBUGFS_FWSTATS_ADD(event, heart_beat);
-        DEBUGFS_FWSTATS_ADD(event, calibration);
-        DEBUGFS_FWSTATS_ADD(event, rx_mismatch);
-        DEBUGFS_FWSTATS_ADD(event, rx_mem_empty);
-        DEBUGFS_FWSTATS_ADD(event, rx_pool);
-        DEBUGFS_FWSTATS_ADD(event, oom_late);
-        DEBUGFS_FWSTATS_ADD(event, phy_transmit_error);
-        DEBUGFS_FWSTATS_ADD(event, tx_stuck);
-
-        DEBUGFS_FWSTATS_ADD(ps, pspoll_timeouts);
-        DEBUGFS_FWSTATS_ADD(ps, upsd_timeouts);
-        DEBUGFS_FWSTATS_ADD(ps, upsd_max_sptime);
-        DEBUGFS_FWSTATS_ADD(ps, upsd_max_apturn);
-        DEBUGFS_FWSTATS_ADD(ps, pspoll_max_apturn);
-        DEBUGFS_FWSTATS_ADD(ps, pspoll_utilization);
-        DEBUGFS_FWSTATS_ADD(ps, upsd_utilization);
-
-        DEBUGFS_FWSTATS_ADD(rxpipe, rx_prep_beacon_drop);
-        DEBUGFS_FWSTATS_ADD(rxpipe, descr_host_int_trig_rx_data);
-        DEBUGFS_FWSTATS_ADD(rxpipe, beacon_buffer_thres_host_int_trig_rx_data);
-        DEBUGFS_FWSTATS_ADD(rxpipe, missed_beacon_host_int_trig_rx_data);
-        DEBUGFS_FWSTATS_ADD(rxpipe, tx_xfr_host_int_trig_rx_data);
-
-        DEBUGFS_ADD(tx_queue_len, wl->debugfs.rootdir);
-        DEBUGFS_ADD(retry_count, wl->debugfs.rootdir);
-        DEBUGFS_ADD(excessive_retries, wl->debugfs.rootdir);
-
-        DEBUGFS_ADD(gpio_power, wl->debugfs.rootdir);
-
-out:
-        if (ret < 0)
-                wl1271_debugfs_delete_files(wl);
-
-        return ret;
-}
-
-void wl1271_debugfs_reset(struct wl1271 *wl)
-{
-        memset(wl->stats.fw_stats, 0, sizeof(*wl->stats.fw_stats));
-        wl->stats.retry_count = 0;
-        wl->stats.excessive_retries = 0;
-}
-
-int wl1271_debugfs_init(struct wl1271 *wl)
-{
-        int ret;
-
-        wl->debugfs.rootdir = debugfs_create_dir(KBUILD_MODNAME, NULL);
-
-        if (IS_ERR(wl->debugfs.rootdir)) {
-                ret = PTR_ERR(wl->debugfs.rootdir);
-                wl->debugfs.rootdir = NULL;
-                goto err;
-        }
-
-        wl->debugfs.fw_statistics = debugfs_create_dir("fw-statistics",
-                                                       wl->debugfs.rootdir);
-
-        if (IS_ERR(wl->debugfs.fw_statistics)) {
-                ret = PTR_ERR(wl->debugfs.fw_statistics);
-                wl->debugfs.fw_statistics = NULL;
-                goto err_root;
-        }
-
-        wl->stats.fw_stats = kzalloc(sizeof(*wl->stats.fw_stats),
-                                      GFP_KERNEL);
-
-        if (!wl->stats.fw_stats) {
-                ret = -ENOMEM;
-                goto err_fw;
-        }
-
-        wl->stats.fw_stats_update = jiffies;
-
-        ret = wl1271_debugfs_add_files(wl);
-
-        if (ret < 0)
-                goto err_file;
-
-        return 0;
-
-err_file:
-        kfree(wl->stats.fw_stats);
-        wl->stats.fw_stats = NULL;
-
-err_fw:
-        debugfs_remove(wl->debugfs.fw_statistics);
-        wl->debugfs.fw_statistics = NULL;
-
-err_root:
-        debugfs_remove(wl->debugfs.rootdir);
-        wl->debugfs.rootdir = NULL;
-
-err:
-        return ret;
-}
-
-void wl1271_debugfs_exit(struct wl1271 *wl)
-{
-        wl1271_debugfs_delete_files(wl);
-
-        kfree(wl->stats.fw_stats);
-        wl->stats.fw_stats = NULL;
-
-        debugfs_remove(wl->debugfs.fw_statistics);
-        wl->debugfs.fw_statistics = NULL;
-
-        debugfs_remove(wl->debugfs.rootdir);
-        wl->debugfs.rootdir = NULL;
-
-}
diff --git a/drivers/net/wireless/wl12xx/wl1271.h b/drivers/net/wireless/wl12xx/wl12xx.h
index 046acb816d2f..9050dd9b62d2 100644
--- a/drivers/net/wireless/wl12xx/wl1271.h
+++ b/drivers/net/wireless/wl12xx/wl12xx.h
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __WL1271_H__
-#define __WL1271_H__
+#ifndef __WL12XX_H__
+#define __WL12XX_H__
 
 #include <linux/mutex.h>
 #include <linux/completion.h>
@@ -32,8 +32,8 @@
 #include <linux/bitops.h>
 #include <net/mac80211.h>
 
-#include "wl1271_conf.h"
-#include "wl1271_ini.h"
+#include "conf.h"
+#include "ini.h"
 
 #define DRIVER_NAME "wl1271"
 #define DRIVER_PREFIX DRIVER_NAME ": "
@@ -60,31 +60,32 @@ enum {
         DEBUG_ALL       = ~0,
 };
 
-#define DEBUG_LEVEL (DEBUG_NONE)
+extern u32 wl12xx_debug_level;
 
 #define DEBUG_DUMP_LIMIT 1024
 
 #define wl1271_error(fmt, arg...) \
-        printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
+        pr_err(DRIVER_PREFIX "ERROR " fmt "\n", ##arg)
 
 #define wl1271_warning(fmt, arg...) \
-        printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
+        pr_warning(DRIVER_PREFIX "WARNING " fmt "\n", ##arg)
 
 #define wl1271_notice(fmt, arg...) \
-        printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg)
+        pr_info(DRIVER_PREFIX fmt "\n", ##arg)
 
 #define wl1271_info(fmt, arg...) \
-        printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg)
+        pr_info(DRIVER_PREFIX fmt "\n", ##arg)
 
 #define wl1271_debug(level, fmt, arg...) \
         do { \
-                if (level & DEBUG_LEVEL) \
-                        printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \
+                if (level & wl12xx_debug_level) \
+                        pr_debug(DRIVER_PREFIX fmt "\n", ##arg); \
         } while (0)
 
+/* TODO: use pr_debug_hex_dump when it will be available */
 #define wl1271_dump(level, prefix, buf, len)    \
         do { \
-                if (level & DEBUG_LEVEL) \
+                if (level & wl12xx_debug_level) \
                         print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
                                        DUMP_PREFIX_OFFSET, 16, 1,       \
                                        buf,                             \
@@ -94,7 +95,7 @@ enum {
 
 #define wl1271_dump_ascii(level, prefix, buf, len)      \
         do { \
-                if (level & DEBUG_LEVEL) \
+                if (level & wl12xx_debug_level) \
                         print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \
                                        DUMP_PREFIX_OFFSET, 16, 1,       \
                                        buf,                             \
@@ -174,108 +175,6 @@ struct wl1271_stats {
         unsigned int excessive_retries;
 };
 
-struct wl1271_debugfs {
-        struct dentry *rootdir;
-        struct dentry *fw_statistics;
-
-        struct dentry *tx_internal_desc_overflow;
-
-        struct dentry *rx_out_of_mem;
-        struct dentry *rx_hdr_overflow;
-        struct dentry *rx_hw_stuck;
-        struct dentry *rx_dropped;
-        struct dentry *rx_fcs_err;
-        struct dentry *rx_xfr_hint_trig;
-        struct dentry *rx_path_reset;
-        struct dentry *rx_reset_counter;
-
-        struct dentry *dma_rx_requested;
-        struct dentry *dma_rx_errors;
-        struct dentry *dma_tx_requested;
-        struct dentry *dma_tx_errors;
-
-        struct dentry *isr_cmd_cmplt;
-        struct dentry *isr_fiqs;
-        struct dentry *isr_rx_headers;
-        struct dentry *isr_rx_mem_overflow;
-        struct dentry *isr_rx_rdys;
-        struct dentry *isr_irqs;
-        struct dentry *isr_tx_procs;
-        struct dentry *isr_decrypt_done;
-        struct dentry *isr_dma0_done;
-        struct dentry *isr_dma1_done;
-        struct dentry *isr_tx_exch_complete;
-        struct dentry *isr_commands;
-        struct dentry *isr_rx_procs;
-        struct dentry *isr_hw_pm_mode_changes;
-        struct dentry *isr_host_acknowledges;
-        struct dentry *isr_pci_pm;
-        struct dentry *isr_wakeups;
-        struct dentry *isr_low_rssi;
-
-        struct dentry *wep_addr_key_count;
-        struct dentry *wep_default_key_count;
-        /* skipping wep.reserved */
-        struct dentry *wep_key_not_found;
-        struct dentry *wep_decrypt_fail;
-        struct dentry *wep_packets;
-        struct dentry *wep_interrupt;
-
-        struct dentry *pwr_ps_enter;
-        struct dentry *pwr_elp_enter;
-        struct dentry *pwr_missing_bcns;
-        struct dentry *pwr_wake_on_host;
-        struct dentry *pwr_wake_on_timer_exp;
-        struct dentry *pwr_tx_with_ps;
-        struct dentry *pwr_tx_without_ps;
-        struct dentry *pwr_rcvd_beacons;
-        struct dentry *pwr_power_save_off;
-        struct dentry *pwr_enable_ps;
-        struct dentry *pwr_disable_ps;
-        struct dentry *pwr_fix_tsf_ps;
-        /* skipping cont_miss_bcns_spread for now */
-        struct dentry *pwr_rcvd_awake_beacons;
-
-        struct dentry *mic_rx_pkts;
-        struct dentry *mic_calc_failure;
-
-        struct dentry *aes_encrypt_fail;
-        struct dentry *aes_decrypt_fail;
-        struct dentry *aes_encrypt_packets;
-        struct dentry *aes_decrypt_packets;
-        struct dentry *aes_encrypt_interrupt;
-        struct dentry *aes_decrypt_interrupt;
-
-        struct dentry *event_heart_beat;
-        struct dentry *event_calibration;
-        struct dentry *event_rx_mismatch;
-        struct dentry *event_rx_mem_empty;
-        struct dentry *event_rx_pool;
-        struct dentry *event_oom_late;
-        struct dentry *event_phy_transmit_error;
-        struct dentry *event_tx_stuck;
-
-        struct dentry *ps_pspoll_timeouts;
-        struct dentry *ps_upsd_timeouts;
-        struct dentry *ps_upsd_max_sptime;
-        struct dentry *ps_upsd_max_apturn;
-        struct dentry *ps_pspoll_max_apturn;
-        struct dentry *ps_pspoll_utilization;
-        struct dentry *ps_upsd_utilization;
-
-        struct dentry *rxpipe_rx_prep_beacon_drop;
-        struct dentry *rxpipe_descr_host_int_trig_rx_data;
-        struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data;
-        struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data;
-        struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data;
-
-        struct dentry *tx_queue_len;
-
-        struct dentry *retry_count;
-        struct dentry *excessive_retries;
-        struct dentry *gpio_power;
-};
-
 #define NUM_TX_QUEUES              4
 #define NUM_RX_PKT_DESC            8
 
@@ -351,6 +250,7 @@ struct wl1271 {
 #define WL1271_FLAG_IDLE_REQUESTED    (11)
 #define WL1271_FLAG_PSPOLL_FAILURE    (12)
 #define WL1271_FLAG_STA_STATE_SENT    (13)
+#define WL1271_FLAG_FW_TX_BUSY        (14)
         unsigned long flags;
 
         struct wl1271_partition_set part;
@@ -392,11 +292,13 @@ struct wl1271 {
         int session_counter;
 
         /* Frames scheduled for transmission, not handled yet */
-        struct sk_buff_head tx_queue;
+        struct sk_buff_head tx_queue[NUM_TX_QUEUES];
+        int tx_queue_count;
 
         struct work_struct tx_work;
 
         /* Pending TX frames */
+        unsigned long tx_frames_map[BITS_TO_LONGS(ACX_TX_DESCRIPTORS)];
         struct sk_buff *tx_frames[ACX_TX_DESCRIPTORS];
         int tx_frames_cnt;
 
@@ -429,10 +331,18 @@ struct wl1271 {
         struct wl1271_scan scan;
         struct delayed_work scan_complete_work;
 
+        /* probe-req template for the current AP */
+        struct sk_buff *probereq;
+
         /* Our association ID */
         u16 aid;
 
-        /* currently configured rate set */
+        /*
+         * currently configured rate set:
+         *      bits  0-15 - 802.11abg rates
+         *      bits 16-23 - 802.11n   MCS index mask
+         * support only 1 stream, thus only 8 bits for the MCS rates (0-7).
+         */
         u32 sta_rate_set;
         u32 basic_rate_set;
         u32 basic_rate;
@@ -468,7 +378,7 @@ struct wl1271 {
         int last_rssi_event;
 
         struct wl1271_stats stats;
-        struct wl1271_debugfs debugfs;
+        struct dentry *rootdir;
 
         __le32 buffer_32;
         u32 buffer_cmd;
@@ -509,4 +419,8 @@ int wl1271_plt_stop(struct wl1271 *wl);
 #define WL1271_PRE_POWER_ON_SLEEP 20 /* in milliseconds */
 #define WL1271_POWER_ON_SLEEP 200 /* in milliseconds */
 
+/* Macros to handle wl1271.sta_rate_set */
+#define HW_BG_RATES_MASK        0xffff
+#define HW_HT_RATES_OFFSET      16
+
 #endif
diff --git a/drivers/net/wireless/wl12xx/wl12xx_80211.h b/drivers/net/wireless/wl12xx/wl12xx_80211.h
index 184628027213..be21032f4dc1 100644
--- a/drivers/net/wireless/wl12xx/wl12xx_80211.h
+++ b/drivers/net/wireless/wl12xx/wl12xx_80211.h
@@ -2,6 +2,7 @@
 #define __WL12XX_80211_H__
 
 #include <linux/if_ether.h>     /* ETH_ALEN */
+#include <linux/if_arp.h>
 
 /* RATES */
 #define IEEE80211_CCK_RATE_1MB                  0x02
@@ -133,11 +134,17 @@ struct wl12xx_qos_null_data_template {
         __le16 qos_ctl;
 } __packed;
 
-struct wl12xx_probe_req_template {
-        struct ieee80211_header header;
-        struct wl12xx_ie_ssid ssid;
-        struct wl12xx_ie_rates rates;
-        struct wl12xx_ie_rates ext_rates;
+struct wl12xx_arp_rsp_template {
+        struct ieee80211_hdr_3addr hdr;
+
+        u8 llc_hdr[sizeof(rfc1042_header)];
+        u16 llc_type;
+
+        struct arphdr arp_hdr;
+        u8 sender_hw[ETH_ALEN];
+        u32 sender_ip;
+        u8 target_hw[ETH_ALEN];
+        u32 target_ip;
 } __packed;
 
 
diff --git a/drivers/net/wireless/zd1201.c b/drivers/net/wireless/zd1201.c
index 390d77f762c4..415eec401e2e 100644
--- a/drivers/net/wireless/zd1201.c
+++ b/drivers/net/wireless/zd1201.c
@@ -30,6 +30,7 @@ static struct usb_device_id zd1201_table[] = {
         {USB_DEVICE(0x0ace, 0x1201)}, /* ZyDAS ZD1201 Wireless USB Adapter */
         {USB_DEVICE(0x050d, 0x6051)}, /* Belkin F5D6051 usb  adapter */
         {USB_DEVICE(0x0db0, 0x6823)}, /* MSI UB11B usb  adapter */
+        {USB_DEVICE(0x1044, 0x8004)}, /* Gigabyte GN-WLBZ101 */
         {USB_DEVICE(0x1044, 0x8005)}, /* GIGABYTE GN-WLBZ201 usb adapter */
         {}
 };
@@ -1829,7 +1830,7 @@ err_zd:
 
 static void zd1201_disconnect(struct usb_interface *interface)
 {
-        struct zd1201 *zd=(struct zd1201 *)usb_get_intfdata(interface);
+        struct zd1201 *zd = usb_get_intfdata(interface);
         struct hlist_node *node, *node2;
         struct zd1201_frag *frag;
 
diff --git a/drivers/net/wireless/zd1211rw/zd_chip.c b/drivers/net/wireless/zd1211rw/zd_chip.c
index 87a95bcfee57..6a9b66051cf7 100644
--- a/drivers/net/wireless/zd1211rw/zd_chip.c
+++ b/drivers/net/wireless/zd1211rw/zd_chip.c
@@ -117,6 +117,7 @@ int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr
 
         /* Allocate a single memory block for values and addresses. */
         count16 = 2*count;
+        /* zd_addr_t is __nocast, so the kmalloc needs an explicit cast */
         a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
                                    GFP_KERNEL);
         if (!a16) {
@@ -1448,7 +1449,7 @@ int zd_rfwritev_locked(struct zd_chip *chip,
  */
 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
 {
-        struct zd_ioreq16 ioreqs[] = {
+        const struct zd_ioreq16 ioreqs[] = {
                 { CR244, (value >> 16) & 0xff },
                 { CR243, (value >>  8) & 0xff },
                 { CR242,  value        & 0xff },
@@ -1475,7 +1476,7 @@ int zd_rfwritev_cr_locked(struct zd_chip *chip,
 int zd_chip_set_multicast_hash(struct zd_chip *chip,
                                struct zd_mc_hash *hash)
 {
-        struct zd_ioreq32 ioreqs[] = {
+        const struct zd_ioreq32 ioreqs[] = {
                 { CR_GROUP_HASH_P1, hash->low },
                 { CR_GROUP_HASH_P2, hash->high },
         };
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c
index 43307bd42a69..6107304cb94c 100644
--- a/drivers/net/wireless/zd1211rw/zd_mac.c
+++ b/drivers/net/wireless/zd1211rw/zd_mac.c
@@ -1207,7 +1207,6 @@ static void housekeeping_enable(struct zd_mac *mac)
 static void housekeeping_disable(struct zd_mac *mac)
 {
         dev_dbg_f(zd_mac_dev(mac), "\n");
-        cancel_rearming_delayed_workqueue(zd_workqueue,
-                &mac->housekeeping.link_led_work);
+        cancel_delayed_work_sync(&mac->housekeeping.link_led_work);
         zd_chip_control_leds(&mac->chip, ZD_LED_OFF);
 }
diff --git a/drivers/net/wireless/zd1211rw/zd_usb.c b/drivers/net/wireless/zd1211rw/zd_usb.c
index 818e1480ca93..06041cb1c422 100644
--- a/drivers/net/wireless/zd1211rw/zd_usb.c
+++ b/drivers/net/wireless/zd1211rw/zd_usb.c
@@ -55,6 +55,7 @@ static struct usb_device_id usb_ids[] = {
         { USB_DEVICE(0x129b, 0x1666), .driver_info = DEVICE_ZD1211 },
         { USB_DEVICE(0x13b1, 0x001e), .driver_info = DEVICE_ZD1211 },
         { USB_DEVICE(0x1435, 0x0711), .driver_info = DEVICE_ZD1211 },
+        { USB_DEVICE(0x14ea, 0xab10), .driver_info = DEVICE_ZD1211 },
         { USB_DEVICE(0x14ea, 0xab13), .driver_info = DEVICE_ZD1211 },
         { USB_DEVICE(0x157e, 0x300a), .driver_info = DEVICE_ZD1211 },
         { USB_DEVICE(0x157e, 0x300b), .driver_info = DEVICE_ZD1211 },
@@ -92,6 +93,7 @@ static struct usb_device_id usb_ids[] = {
         { USB_DEVICE(0x157e, 0x300d), .driver_info = DEVICE_ZD1211B },
         { USB_DEVICE(0x1582, 0x6003), .driver_info = DEVICE_ZD1211B },
         { USB_DEVICE(0x2019, 0x5303), .driver_info = DEVICE_ZD1211B },
+        { USB_DEVICE(0x2019, 0xed01), .driver_info = DEVICE_ZD1211B },
         /* "Driverless" devices that need ejecting */
         { USB_DEVICE(0x0ace, 0x2011), .driver_info = DEVICE_INSTALLER },
         { USB_DEVICE(0x0ace, 0x20ff), .driver_info = DEVICE_INSTALLER },
diff --git a/drivers/net/xen-netfront.c b/drivers/net/xen-netfront.c
index cdbeec9f83ea..546de5749824 100644
--- a/drivers/net/xen-netfront.c
+++ b/drivers/net/xen-netfront.c
@@ -488,7 +488,7 @@ static int xennet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         if (unlikely(!netif_carrier_ok(dev) ||
                      (frags > 1 && !xennet_can_sg(dev)) ||
-                     netif_needs_gso(dev, skb))) {
+                     netif_needs_gso(skb, netif_skb_features(skb)))) {
                 spin_unlock_irq(&np->tx_lock);
                 goto drop;
         }
diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c
index 14f0955eca68..cad66ce1640b 100644
--- a/drivers/net/xilinx_emaclite.c
+++ b/drivers/net/xilinx_emaclite.c
@@ -24,6 +24,7 @@
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
 #include <linux/of_mdio.h>
+#include <linux/of_net.h>
 #include <linux/phy.h>
 
 #define DRIVER_NAME "xilinx_emaclite"
@@ -515,7 +516,7 @@ static void xemaclite_update_address(struct net_local *drvdata,
  */
 static int xemaclite_set_mac_address(struct net_device *dev, void *address)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
         struct sockaddr *addr = address;
 
         if (netif_running(dev))
@@ -534,7 +535,7 @@ static int xemaclite_set_mac_address(struct net_device *dev, void *address)
  */
 static void xemaclite_tx_timeout(struct net_device *dev)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
         unsigned long flags;
 
         dev_err(&lp->ndev->dev, "Exceeded transmit timeout of %lu ms\n",
@@ -578,7 +579,7 @@ static void xemaclite_tx_timeout(struct net_device *dev)
  */
 static void xemaclite_tx_handler(struct net_device *dev)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
 
         dev->stats.tx_packets++;
         if (lp->deferred_skb) {
@@ -605,7 +606,7 @@ static void xemaclite_tx_handler(struct net_device *dev)
  */
 static void xemaclite_rx_handler(struct net_device *dev)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
         struct sk_buff *skb;
         unsigned int align;
         u32 len;
@@ -661,7 +662,7 @@ static irqreturn_t xemaclite_interrupt(int irq, void *dev_id)
 {
         bool tx_complete = 0;
         struct net_device *dev = dev_id;
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
         void __iomem *base_addr = lp->base_addr;
         u32 tx_status;
 
@@ -918,7 +919,7 @@ void xemaclite_adjust_link(struct net_device *ndev)
  */
 static int xemaclite_open(struct net_device *dev)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
         int retval;
 
         /* Just to be safe, stop the device first */
@@ -987,7 +988,7 @@ static int xemaclite_open(struct net_device *dev)
  */
 static int xemaclite_close(struct net_device *dev)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
 
         netif_stop_queue(dev);
         xemaclite_disable_interrupts(lp);
@@ -1001,21 +1002,6 @@ static int xemaclite_close(struct net_device *dev)
 }
 
 /**
- * xemaclite_get_stats - Get the stats for the net_device
- * @dev:        Pointer to the network device
- *
- * This function returns the address of the 'net_device_stats' structure for the
- * given network device. This structure holds usage statistics for the network
- * device.
- *
- * Return:      Pointer to the net_device_stats structure.
- */
-static struct net_device_stats *xemaclite_get_stats(struct net_device *dev)
-{
-        return &dev->stats;
-}
-
-/**
  * xemaclite_send - Transmit a frame
  * @orig_skb:   Pointer to the socket buffer to be transmitted
  * @dev:        Pointer to the network device
@@ -1031,7 +1017,7 @@ static struct net_device_stats *xemaclite_get_stats(struct net_device *dev)
  */
 static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
 {
-        struct net_local *lp = (struct net_local *) netdev_priv(dev);
+        struct net_local *lp = netdev_priv(dev);
         struct sk_buff *new_skb;
         unsigned int len;
         unsigned long flags;
@@ -1068,7 +1054,7 @@ static int xemaclite_send(struct sk_buff *orig_skb, struct net_device *dev)
 static void xemaclite_remove_ndev(struct net_device *ndev)
 {
         if (ndev) {
-                struct net_local *lp = (struct net_local *) netdev_priv(ndev);
+                struct net_local *lp = netdev_priv(ndev);
 
                 if (lp->base_addr)
                         iounmap((void __iomem __force *) (lp->base_addr));
@@ -1245,7 +1231,7 @@ static int __devexit xemaclite_of_remove(struct platform_device *of_dev)
         struct device *dev = &of_dev->dev;
         struct net_device *ndev = dev_get_drvdata(dev);
 
-        struct net_local *lp = (struct net_local *) netdev_priv(ndev);
+        struct net_local *lp = netdev_priv(ndev);
 
         /* Un-register the mii_bus, if configured */
         if (lp->has_mdio) {
@@ -1285,7 +1271,6 @@ static struct net_device_ops xemaclite_netdev_ops = {
         .ndo_start_xmit         = xemaclite_send,
         .ndo_set_mac_address    = xemaclite_set_mac_address,
         .ndo_tx_timeout         = xemaclite_tx_timeout,
-        .ndo_get_stats          = xemaclite_get_stats,
 #ifdef CONFIG_NET_POLL_CONTROLLER
         .ndo_poll_controller = xemaclite_poll_controller,
 #endif
diff --git a/drivers/net/yellowfin.c b/drivers/net/yellowfin.c
index cd1b3dcd61db..ec47e22fa186 100644
--- a/drivers/net/yellowfin.c
+++ b/drivers/net/yellowfin.c
@@ -744,7 +744,7 @@ static int yellowfin_init_ring(struct net_device *dev)
         }
 
         for (i = 0; i < RX_RING_SIZE; i++) {
-                struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
+                struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz + 2);
                 yp->rx_skbuff[i] = skb;
                 if (skb == NULL)
                         break;
@@ -1157,7 +1157,7 @@ static int yellowfin_rx(struct net_device *dev)
         for (; yp->cur_rx - yp->dirty_rx > 0; yp->dirty_rx++) {
                 entry = yp->dirty_rx % RX_RING_SIZE;
                 if (yp->rx_skbuff[entry] == NULL) {
-                        struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz);
+                        struct sk_buff *skb = dev_alloc_skb(yp->rx_buf_sz + 2);
                         if (skb == NULL)
                                 break;                          /* Better luck next round. */
                         yp->rx_skbuff[entry] = skb;
diff --git a/drivers/net/znet.c b/drivers/net/znet.c
index c3a329204511..ae07b3dfbcc1 100644
--- a/drivers/net/znet.c
+++ b/drivers/net/znet.c
@@ -124,7 +124,7 @@ MODULE_LICENSE("GPL");
 #define TX_BUF_SIZE 8192
 #define DMA_BUF_SIZE (RX_BUF_SIZE + 16) /* 8k + 16 bytes for trailers */
 
-#define TX_TIMEOUT      10
+#define TX_TIMEOUT      (HZ/10)
 
 struct znet_private {
         int rx_dma, tx_dma;