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-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x.h26
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c197
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h38
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c221
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c189
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c528
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c150
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h9
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c63
9 files changed, 694 insertions, 727 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index c0cf313e6519..f534bf132373 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -58,18 +58,22 @@
58#define DRV_MODULE_NAME "bnx2x" 58#define DRV_MODULE_NAME "bnx2x"
59 59
60/* for messages that are currently off */ 60/* for messages that are currently off */
61#define BNX2X_MSG_OFF 0 61#define BNX2X_MSG_OFF 0x0
62#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ 62#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
63#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ 63#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
64#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ 64#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
65#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ 65#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
66#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 66#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
67#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 67#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
68#define BNX2X_MSG_IOV 0x0800000
69#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
70#define BNX2X_MSG_ETHTOOL 0x4000000
71#define BNX2X_MSG_DCB 0x8000000
68 72
69/* regular debug print */ 73/* regular debug print */
70#define DP(__mask, fmt, ...) \ 74#define DP(__mask, fmt, ...) \
71do { \ 75do { \
72 if (bp->msg_enable & (__mask)) \ 76 if (unlikely(bp->msg_enable & (__mask))) \
73 pr_notice("[%s:%d(%s)]" fmt, \ 77 pr_notice("[%s:%d(%s)]" fmt, \
74 __func__, __LINE__, \ 78 __func__, __LINE__, \
75 bp->dev ? (bp->dev->name) : "?", \ 79 bp->dev ? (bp->dev->name) : "?", \
@@ -78,14 +82,14 @@ do { \
78 82
79#define DP_CONT(__mask, fmt, ...) \ 83#define DP_CONT(__mask, fmt, ...) \
80do { \ 84do { \
81 if (bp->msg_enable & (__mask)) \ 85 if (unlikely(bp->msg_enable & (__mask))) \
82 pr_cont(fmt, ##__VA_ARGS__); \ 86 pr_cont(fmt, ##__VA_ARGS__); \
83} while (0) 87} while (0)
84 88
85/* errors debug print */ 89/* errors debug print */
86#define BNX2X_DBG_ERR(fmt, ...) \ 90#define BNX2X_DBG_ERR(fmt, ...) \
87do { \ 91do { \
88 if (netif_msg_probe(bp)) \ 92 if (unlikely(netif_msg_probe(bp))) \
89 pr_err("[%s:%d(%s)]" fmt, \ 93 pr_err("[%s:%d(%s)]" fmt, \
90 __func__, __LINE__, \ 94 __func__, __LINE__, \
91 bp->dev ? (bp->dev->name) : "?", \ 95 bp->dev ? (bp->dev->name) : "?", \
@@ -108,7 +112,7 @@ do { \
108/* before we have a dev->name use dev_info() */ 112/* before we have a dev->name use dev_info() */
109#define BNX2X_DEV_INFO(fmt, ...) \ 113#define BNX2X_DEV_INFO(fmt, ...) \
110do { \ 114do { \
111 if (netif_msg_probe(bp)) \ 115 if (unlikely(netif_msg_probe(bp))) \
112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 116 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
113} while (0) 117} while (0)
114 118
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index d888228d0787..d2fb7ba38143 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -75,11 +75,10 @@ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
75 /* prefetch skb end pointer to speedup dev_kfree_skb() */ 75 /* prefetch skb end pointer to speedup dev_kfree_skb() */
76 prefetch(&skb->end); 76 prefetch(&skb->end);
77 77
78 DP(BNX2X_MSG_FP, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n", 78 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
79 txdata->txq_index, idx, tx_buf, skb); 79 txdata->txq_index, idx, tx_buf, skb);
80 80
81 /* unmap first bd */ 81 /* unmap first bd */
82 DP(BNX2X_MSG_OFF, "free bd_idx %d\n", bd_idx);
83 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd; 82 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
84 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd), 83 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
85 BD_UNMAP_LEN(tx_start_bd), DMA_TO_DEVICE); 84 BD_UNMAP_LEN(tx_start_bd), DMA_TO_DEVICE);
@@ -110,7 +109,6 @@ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
110 /* now free frags */ 109 /* now free frags */
111 while (nbd > 0) { 110 while (nbd > 0) {
112 111
113 DP(BNX2X_MSG_OFF, "free frag bd_idx %d\n", bd_idx);
114 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd; 112 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
115 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd), 113 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
116 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE); 114 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
@@ -152,8 +150,8 @@ int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
152 150
153 pkt_cons = TX_BD(sw_cons); 151 pkt_cons = TX_BD(sw_cons);
154 152
155 DP(NETIF_MSG_TX_DONE, "queue[%d]: hw_cons %u sw_cons %u " 153 DP(NETIF_MSG_TX_DONE,
156 " pkt_cons %u\n", 154 "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n",
157 txdata->txq_index, hw_cons, sw_cons, pkt_cons); 155 txdata->txq_index, hw_cons, sw_cons, pkt_cons);
158 156
159 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons, 157 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
@@ -531,8 +529,7 @@ static inline void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
531 if (likely(skb)) { 529 if (likely(skb)) {
532#ifdef BNX2X_STOP_ON_ERROR 530#ifdef BNX2X_STOP_ON_ERROR
533 if (pad + len > fp->rx_buf_size) { 531 if (pad + len > fp->rx_buf_size) {
534 BNX2X_ERR("skb_put is about to fail... " 532 BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
535 "pad %d len %d rx_buf_size %d\n",
536 pad, len, fp->rx_buf_size); 533 pad, len, fp->rx_buf_size);
537 bnx2x_panic(); 534 bnx2x_panic();
538 return; 535 return;
@@ -552,8 +549,8 @@ static inline void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
552 __vlan_hwaccel_put_tag(skb, tpa_info->vlan_tag); 549 __vlan_hwaccel_put_tag(skb, tpa_info->vlan_tag);
553 napi_gro_receive(&fp->napi, skb); 550 napi_gro_receive(&fp->napi, skb);
554 } else { 551 } else {
555 DP(NETIF_MSG_RX_STATUS, "Failed to allocate new pages" 552 DP(NETIF_MSG_RX_STATUS,
556 " - dropping packet!\n"); 553 "Failed to allocate new pages - dropping packet!\n");
557 dev_kfree_skb_any(skb); 554 dev_kfree_skb_any(skb);
558 } 555 }
559 556
@@ -629,8 +626,9 @@ int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
629 cqe_fp_flags = cqe_fp->type_error_flags; 626 cqe_fp_flags = cqe_fp->type_error_flags;
630 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 627 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
631 628
632 DP(NETIF_MSG_RX_STATUS, "CQE type %x err %x status %x" 629 DP(NETIF_MSG_RX_STATUS,
633 " queue %x vlan %x len %u\n", CQE_TYPE(cqe_fp_flags), 630 "CQE type %x err %x status %x queue %x vlan %x len %u\n",
631 CQE_TYPE(cqe_fp_flags),
634 cqe_fp_flags, cqe_fp->status_flags, 632 cqe_fp_flags, cqe_fp->status_flags,
635 le32_to_cpu(cqe_fp->rss_hash_result), 633 le32_to_cpu(cqe_fp->rss_hash_result),
636 le16_to_cpu(cqe_fp->vlan_tag), 634 le16_to_cpu(cqe_fp->vlan_tag),
@@ -653,8 +651,7 @@ int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
653 if (fp->disable_tpa && 651 if (fp->disable_tpa &&
654 (CQE_TYPE_START(cqe_fp_type) || 652 (CQE_TYPE_START(cqe_fp_type) ||
655 CQE_TYPE_STOP(cqe_fp_type))) 653 CQE_TYPE_STOP(cqe_fp_type)))
656 BNX2X_ERR("START/STOP packet while " 654 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
657 "disable_tpa type %x\n",
658 CQE_TYPE(cqe_fp_type)); 655 CQE_TYPE(cqe_fp_type));
659#endif 656#endif
660 657
@@ -708,7 +705,7 @@ int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
708 prefetch(data + pad); /* speedup eth_type_trans() */ 705 prefetch(data + pad); /* speedup eth_type_trans() */
709 /* is this an error packet? */ 706 /* is this an error packet? */
710 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) { 707 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
711 DP(NETIF_MSG_RX_ERR, 708 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
712 "ERROR flags %x rx packet %u\n", 709 "ERROR flags %x rx packet %u\n",
713 cqe_fp_flags, sw_comp_cons); 710 cqe_fp_flags, sw_comp_cons);
714 fp->eth_q_stats.rx_err_discard_pkt++; 711 fp->eth_q_stats.rx_err_discard_pkt++;
@@ -722,7 +719,7 @@ int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
722 (len <= RX_COPY_THRESH)) { 719 (len <= RX_COPY_THRESH)) {
723 skb = netdev_alloc_skb_ip_align(bp->dev, len); 720 skb = netdev_alloc_skb_ip_align(bp->dev, len);
724 if (skb == NULL) { 721 if (skb == NULL) {
725 DP(NETIF_MSG_RX_ERR, 722 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
726 "ERROR packet dropped because of alloc failure\n"); 723 "ERROR packet dropped because of alloc failure\n");
727 fp->eth_q_stats.rx_skb_alloc_failed++; 724 fp->eth_q_stats.rx_skb_alloc_failed++;
728 goto reuse_rx; 725 goto reuse_rx;
@@ -743,9 +740,8 @@ int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
743 } 740 }
744 skb_reserve(skb, pad); 741 skb_reserve(skb, pad);
745 } else { 742 } else {
746 DP(NETIF_MSG_RX_ERR, 743 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
747 "ERROR packet dropped because " 744 "ERROR packet dropped because of alloc failure\n");
748 "of alloc failure\n");
749 fp->eth_q_stats.rx_skb_alloc_failed++; 745 fp->eth_q_stats.rx_skb_alloc_failed++;
750reuse_rx: 746reuse_rx:
751 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod); 747 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
@@ -814,8 +810,8 @@ static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
814 struct bnx2x *bp = fp->bp; 810 struct bnx2x *bp = fp->bp;
815 u8 cos; 811 u8 cos;
816 812
817 DP(BNX2X_MSG_FP, "got an MSI-X interrupt on IDX:SB " 813 DP(NETIF_MSG_INTR,
818 "[fp %d fw_sd %d igusb %d]\n", 814 "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
819 fp->index, fp->fw_sb_id, fp->igu_sb_id); 815 fp->index, fp->fw_sb_id, fp->igu_sb_id);
820 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 816 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
821 817
@@ -1028,10 +1024,8 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
1028 first_buf->data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, 1024 first_buf->data = kmalloc(fp->rx_buf_size + NET_SKB_PAD,
1029 GFP_ATOMIC); 1025 GFP_ATOMIC);
1030 if (!first_buf->data) { 1026 if (!first_buf->data) {
1031 BNX2X_ERR("Failed to allocate TPA " 1027 BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1032 "skb pool for queue[%d] - " 1028 j);
1033 "disabling TPA on this "
1034 "queue!\n", j);
1035 bnx2x_free_tpa_pool(bp, fp, i); 1029 bnx2x_free_tpa_pool(bp, fp, i);
1036 fp->disable_tpa = 1; 1030 fp->disable_tpa = 1;
1037 break; 1031 break;
@@ -1051,10 +1045,10 @@ void bnx2x_init_rx_rings(struct bnx2x *bp)
1051 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) { 1045 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1052 1046
1053 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) { 1047 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
1054 BNX2X_ERR("was only able to allocate " 1048 BNX2X_ERR("was only able to allocate %d rx sges\n",
1055 "%d rx sges\n", i); 1049 i);
1056 BNX2X_ERR("disabling TPA for " 1050 BNX2X_ERR("disabling TPA for queue[%d]\n",
1057 "queue[%d]\n", j); 1051 j);
1058 /* Cleanup already allocated elements */ 1052 /* Cleanup already allocated elements */
1059 bnx2x_free_rx_sge_range(bp, fp, 1053 bnx2x_free_rx_sge_range(bp, fp,
1060 ring_prod); 1054 ring_prod);
@@ -1209,8 +1203,8 @@ static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1209 for_each_eth_queue(bp, i) { 1203 for_each_eth_queue(bp, i) {
1210 if (nvecs == offset) 1204 if (nvecs == offset)
1211 return; 1205 return;
1212 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d " 1206 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1213 "irq\n", i, bp->msix_table[offset].vector); 1207 i, bp->msix_table[offset].vector);
1214 1208
1215 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]); 1209 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1216 } 1210 }
@@ -1232,21 +1226,21 @@ int bnx2x_enable_msix(struct bnx2x *bp)
1232 int msix_vec = 0, i, rc, req_cnt; 1226 int msix_vec = 0, i, rc, req_cnt;
1233 1227
1234 bp->msix_table[msix_vec].entry = msix_vec; 1228 bp->msix_table[msix_vec].entry = msix_vec;
1235 DP(NETIF_MSG_IFUP, "msix_table[0].entry = %d (slowpath)\n", 1229 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1236 bp->msix_table[0].entry); 1230 bp->msix_table[0].entry);
1237 msix_vec++; 1231 msix_vec++;
1238 1232
1239#ifdef BCM_CNIC 1233#ifdef BCM_CNIC
1240 bp->msix_table[msix_vec].entry = msix_vec; 1234 bp->msix_table[msix_vec].entry = msix_vec;
1241 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d (CNIC)\n", 1235 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1242 bp->msix_table[msix_vec].entry, bp->msix_table[msix_vec].entry); 1236 bp->msix_table[msix_vec].entry, bp->msix_table[msix_vec].entry);
1243 msix_vec++; 1237 msix_vec++;
1244#endif 1238#endif
1245 /* We need separate vectors for ETH queues only (not FCoE) */ 1239 /* We need separate vectors for ETH queues only (not FCoE) */
1246 for_each_eth_queue(bp, i) { 1240 for_each_eth_queue(bp, i) {
1247 bp->msix_table[msix_vec].entry = msix_vec; 1241 bp->msix_table[msix_vec].entry = msix_vec;
1248 DP(NETIF_MSG_IFUP, "msix_table[%d].entry = %d " 1242 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1249 "(fastpath #%u)\n", msix_vec, msix_vec, i); 1243 msix_vec, msix_vec, i);
1250 msix_vec++; 1244 msix_vec++;
1251 } 1245 }
1252 1246
@@ -1262,14 +1256,12 @@ int bnx2x_enable_msix(struct bnx2x *bp)
1262 /* how less vectors we will have? */ 1256 /* how less vectors we will have? */
1263 int diff = req_cnt - rc; 1257 int diff = req_cnt - rc;
1264 1258
1265 DP(NETIF_MSG_IFUP, 1259 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1266 "Trying to use less MSI-X vectors: %d\n", rc);
1267 1260
1268 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], rc); 1261 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], rc);
1269 1262
1270 if (rc) { 1263 if (rc) {
1271 DP(NETIF_MSG_IFUP, 1264 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1272 "MSI-X is not attainable rc %d\n", rc);
1273 return rc; 1265 return rc;
1274 } 1266 }
1275 /* 1267 /*
@@ -1277,13 +1269,13 @@ int bnx2x_enable_msix(struct bnx2x *bp)
1277 */ 1269 */
1278 bp->num_queues -= diff; 1270 bp->num_queues -= diff;
1279 1271
1280 DP(NETIF_MSG_IFUP, "New queue configuration set: %d\n", 1272 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1281 bp->num_queues); 1273 bp->num_queues);
1282 } else if (rc) { 1274 } else if (rc) {
1283 /* fall to INTx if not enough memory */ 1275 /* fall to INTx if not enough memory */
1284 if (rc == -ENOMEM) 1276 if (rc == -ENOMEM)
1285 bp->flags |= DISABLE_MSI_FLAG; 1277 bp->flags |= DISABLE_MSI_FLAG;
1286 DP(NETIF_MSG_IFUP, "MSI-X is not attainable rc %d\n", rc); 1278 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1287 return rc; 1279 return rc;
1288 } 1280 }
1289 1281
@@ -1326,8 +1318,7 @@ static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1326 1318
1327 i = BNX2X_NUM_ETH_QUEUES(bp); 1319 i = BNX2X_NUM_ETH_QUEUES(bp);
1328 offset = 1 + CNIC_PRESENT; 1320 offset = 1 + CNIC_PRESENT;
1329 netdev_info(bp->dev, "using MSI-X IRQs: sp %d fp[%d] %d" 1321 netdev_info(bp->dev, "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
1330 " ... fp[%d] %d\n",
1331 bp->msix_table[0].vector, 1322 bp->msix_table[0].vector,
1332 0, bp->msix_table[offset].vector, 1323 0, bp->msix_table[offset].vector,
1333 i - 1, bp->msix_table[offset + i - 1].vector); 1324 i - 1, bp->msix_table[offset + i - 1].vector);
@@ -1341,7 +1332,7 @@ int bnx2x_enable_msi(struct bnx2x *bp)
1341 1332
1342 rc = pci_enable_msi(bp->pdev); 1333 rc = pci_enable_msi(bp->pdev);
1343 if (rc) { 1334 if (rc) {
1344 DP(NETIF_MSG_IFUP, "MSI is not attainable\n"); 1335 BNX2X_DEV_INFO("MSI is not attainable\n");
1345 return -1; 1336 return -1;
1346 } 1337 }
1347 bp->flags |= USING_MSI_FLAG; 1338 bp->flags |= USING_MSI_FLAG;
@@ -1518,7 +1509,7 @@ static inline int bnx2x_set_real_num_queues(struct bnx2x *bp)
1518 return rc; 1509 return rc;
1519 } 1510 }
1520 1511
1521 DP(NETIF_MSG_DRV, "Setting real num queues to (tx, rx) (%d, %d)\n", 1512 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
1522 tx, rx); 1513 tx, rx);
1523 1514
1524 return rc; 1515 return rc;
@@ -1699,8 +1690,8 @@ static void bnx2x_squeeze_objects(struct bnx2x *bp)
1699 /* Add a DEL command... */ 1690 /* Add a DEL command... */
1700 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 1691 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
1701 if (rc < 0) 1692 if (rc < 0)
1702 BNX2X_ERR("Failed to add a new DEL command to a multi-cast " 1693 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
1703 "object: %d\n", rc); 1694 rc);
1704 1695
1705 /* ...and wait until all pending commands are cleared */ 1696 /* ...and wait until all pending commands are cleared */
1706 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); 1697 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
@@ -1738,8 +1729,10 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1738 int i, rc; 1729 int i, rc;
1739 1730
1740#ifdef BNX2X_STOP_ON_ERROR 1731#ifdef BNX2X_STOP_ON_ERROR
1741 if (unlikely(bp->panic)) 1732 if (unlikely(bp->panic)) {
1733 BNX2X_ERR("Can't load NIC when there is panic\n");
1742 return -EPERM; 1734 return -EPERM;
1735 }
1743#endif 1736#endif
1744 1737
1745 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD; 1738 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
@@ -1759,6 +1752,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1759 * allocated only once, fp index, max_cos, bp pointer. 1752 * allocated only once, fp index, max_cos, bp pointer.
1760 * Also set fp->disable_tpa. 1753 * Also set fp->disable_tpa.
1761 */ 1754 */
1755 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
1762 for_each_queue(bp, i) 1756 for_each_queue(bp, i)
1763 bnx2x_bz_fp(bp, i); 1757 bnx2x_bz_fp(bp, i);
1764 1758
@@ -1815,6 +1809,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1815 LOAD_ERROR_EXIT(bp, load_error1); 1809 LOAD_ERROR_EXIT(bp, load_error1);
1816 } 1810 }
1817 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) { 1811 if (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED) {
1812 BNX2X_ERR("Driver load refused\n");
1818 rc = -EBUSY; /* other port in diagnostic mode */ 1813 rc = -EBUSY; /* other port in diagnostic mode */
1819 LOAD_ERROR_EXIT(bp, load_error1); 1814 LOAD_ERROR_EXIT(bp, load_error1);
1820 } 1815 }
@@ -1875,7 +1870,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1875 } else 1870 } else
1876 bp->port.pmf = 0; 1871 bp->port.pmf = 0;
1877 1872
1878 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 1873 DP(NETIF_MSG_IFUP, "pmf %d\n", bp->port.pmf);
1879 1874
1880 /* Init Function state controlling object */ 1875 /* Init Function state controlling object */
1881 bnx2x__init_func_obj(bp); 1876 bnx2x__init_func_obj(bp);
@@ -1891,6 +1886,7 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1891 /* Connect to IRQs */ 1886 /* Connect to IRQs */
1892 rc = bnx2x_setup_irqs(bp); 1887 rc = bnx2x_setup_irqs(bp);
1893 if (rc) { 1888 if (rc) {
1889 BNX2X_ERR("IRQs setup failed\n");
1894 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); 1890 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
1895 LOAD_ERROR_EXIT(bp, load_error2); 1891 LOAD_ERROR_EXIT(bp, load_error2);
1896 } 1892 }
@@ -1941,21 +1937,27 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
1941 1937
1942 for_each_nondefault_queue(bp, i) { 1938 for_each_nondefault_queue(bp, i) {
1943 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0); 1939 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
1944 if (rc) 1940 if (rc) {
1941 BNX2X_ERR("Queue setup failed\n");
1945 LOAD_ERROR_EXIT(bp, load_error4); 1942 LOAD_ERROR_EXIT(bp, load_error4);
1943 }
1946 } 1944 }
1947 1945
1948 rc = bnx2x_init_rss_pf(bp); 1946 rc = bnx2x_init_rss_pf(bp);
1949 if (rc) 1947 if (rc) {
1948 BNX2X_ERR("PF RSS init failed\n");
1950 LOAD_ERROR_EXIT(bp, load_error4); 1949 LOAD_ERROR_EXIT(bp, load_error4);
1950 }
1951 1951
1952 /* Now when Clients are configured we are ready to work */ 1952 /* Now when Clients are configured we are ready to work */
1953 bp->state = BNX2X_STATE_OPEN; 1953 bp->state = BNX2X_STATE_OPEN;
1954 1954
1955 /* Configure a ucast MAC */ 1955 /* Configure a ucast MAC */
1956 rc = bnx2x_set_eth_mac(bp, true); 1956 rc = bnx2x_set_eth_mac(bp, true);
1957 if (rc) 1957 if (rc) {
1958 BNX2X_ERR("Setting Ethernet MAC failed\n");
1958 LOAD_ERROR_EXIT(bp, load_error4); 1959 LOAD_ERROR_EXIT(bp, load_error4);
1960 }
1959 1961
1960 if (bp->pending_max) { 1962 if (bp->pending_max) {
1961 bnx2x_update_max_mf_config(bp, bp->pending_max); 1963 bnx2x_update_max_mf_config(bp, bp->pending_max);
@@ -2092,8 +2094,8 @@ int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode)
2092 bnx2x_release_leader_lock(bp); 2094 bnx2x_release_leader_lock(bp);
2093 smp_mb(); 2095 smp_mb();
2094 2096
2095 DP(NETIF_MSG_HW, "Releasing a leadership...\n"); 2097 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
2096 2098 BNX2X_ERR("Can't unload in closed or error state\n");
2097 return -EINVAL; 2099 return -EINVAL;
2098 } 2100 }
2099 2101
@@ -2198,7 +2200,7 @@ int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
2198 2200
2199 /* If there is no power capability, silently succeed */ 2201 /* If there is no power capability, silently succeed */
2200 if (!bp->pm_cap) { 2202 if (!bp->pm_cap) {
2201 DP(NETIF_MSG_HW, "No power capability. Breaking.\n"); 2203 BNX2X_DEV_INFO("No power capability. Breaking.\n");
2202 return 0; 2204 return 0;
2203 } 2205 }
2204 2206
@@ -2239,6 +2241,7 @@ int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
2239 break; 2241 break;
2240 2242
2241 default: 2243 default:
2244 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
2242 return -EINVAL; 2245 return -EINVAL;
2243 } 2246 }
2244 return 0; 2247 return 0;
@@ -2308,7 +2311,7 @@ int bnx2x_poll(struct napi_struct *napi, int budget)
2308 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) { 2311 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
2309 napi_complete(napi); 2312 napi_complete(napi);
2310 /* Re-enable interrupts */ 2313 /* Re-enable interrupts */
2311 DP(NETIF_MSG_HW, 2314 DP(NETIF_MSG_RX_STATUS,
2312 "Update index to %d\n", fp->fp_hc_idx); 2315 "Update index to %d\n", fp->fp_hc_idx);
2313 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 2316 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
2314 le16_to_cpu(fp->fp_hc_idx), 2317 le16_to_cpu(fp->fp_hc_idx),
@@ -2342,9 +2345,8 @@ static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
2342 h_tx_bd->nbd = cpu_to_le16(nbd); 2345 h_tx_bd->nbd = cpu_to_le16(nbd);
2343 h_tx_bd->nbytes = cpu_to_le16(hlen); 2346 h_tx_bd->nbytes = cpu_to_le16(hlen);
2344 2347
2345 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d " 2348 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x) nbd %d\n",
2346 "(%x:%x) nbd %d\n", h_tx_bd->nbytes, h_tx_bd->addr_hi, 2349 h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo, h_tx_bd->nbd);
2347 h_tx_bd->addr_lo, h_tx_bd->nbd);
2348 2350
2349 /* now get a new data BD 2351 /* now get a new data BD
2350 * (after the pbd) and fill it */ 2352 * (after the pbd) and fill it */
@@ -2484,8 +2486,7 @@ static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
2484exit_lbl: 2486exit_lbl:
2485 if (unlikely(to_copy)) 2487 if (unlikely(to_copy))
2486 DP(NETIF_MSG_TX_QUEUED, 2488 DP(NETIF_MSG_TX_QUEUED,
2487 "Linearization IS REQUIRED for %s packet. " 2489 "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n",
2488 "num_frags %d hlen %d first_bd_sz %d\n",
2489 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO", 2490 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
2490 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz); 2491 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
2491 2492
@@ -2693,7 +2694,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2693#endif 2694#endif
2694 2695
2695 /* enable this debug print to view the transmission queue being used 2696 /* enable this debug print to view the transmission queue being used
2696 DP(BNX2X_MSG_FP, "indices: txq %d, fp %d, txdata %d\n", 2697 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n",
2697 txq_index, fp_index, txdata_index); */ 2698 txq_index, fp_index, txdata_index); */
2698 2699
2699 /* locate the fastpath and the txdata */ 2700 /* locate the fastpath and the txdata */
@@ -2701,8 +2702,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2701 txdata = &fp->txdata[txdata_index]; 2702 txdata = &fp->txdata[txdata_index];
2702 2703
2703 /* enable this debug print to view the tranmission details 2704 /* enable this debug print to view the tranmission details
2704 DP(BNX2X_MSG_FP,"transmitting packet cid %d fp index %d txdata_index %d" 2705 DP(NETIF_MSG_TX_QUEUED,
2705 " tx_data ptr %p fp pointer %p\n", 2706 "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n",
2706 txdata->cid, fp_index, txdata_index, txdata, fp); */ 2707 txdata->cid, fp_index, txdata_index, txdata, fp); */
2707 2708
2708 if (unlikely(bnx2x_tx_avail(bp, txdata) < 2709 if (unlikely(bnx2x_tx_avail(bp, txdata) <
@@ -2713,8 +2714,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2713 return NETDEV_TX_BUSY; 2714 return NETDEV_TX_BUSY;
2714 } 2715 }
2715 2716
2716 DP(NETIF_MSG_TX_QUEUED, "queue[%d]: SKB: summed %x protocol %x " 2717 DP(NETIF_MSG_TX_QUEUED,
2717 "protocol(%x,%x) gso type %x xmit_type %x\n", 2718 "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x\n",
2718 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr, 2719 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
2719 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type); 2720 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type);
2720 2721
@@ -2736,8 +2737,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2736 /* Statistics of linearization */ 2737 /* Statistics of linearization */
2737 bp->lin_cnt++; 2738 bp->lin_cnt++;
2738 if (skb_linearize(skb) != 0) { 2739 if (skb_linearize(skb) != 0) {
2739 DP(NETIF_MSG_TX_QUEUED, "SKB linearization failed - " 2740 DP(NETIF_MSG_TX_QUEUED,
2740 "silently dropping this SKB\n"); 2741 "SKB linearization failed - silently dropping this SKB\n");
2741 dev_kfree_skb_any(skb); 2742 dev_kfree_skb_any(skb);
2742 return NETDEV_TX_OK; 2743 return NETDEV_TX_OK;
2743 } 2744 }
@@ -2747,8 +2748,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2747 mapping = dma_map_single(&bp->pdev->dev, skb->data, 2748 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2748 skb_headlen(skb), DMA_TO_DEVICE); 2749 skb_headlen(skb), DMA_TO_DEVICE);
2749 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2750 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2750 DP(NETIF_MSG_TX_QUEUED, "SKB mapping failed - " 2751 DP(NETIF_MSG_TX_QUEUED,
2751 "silently dropping this SKB\n"); 2752 "SKB mapping failed - silently dropping this SKB\n");
2752 dev_kfree_skb_any(skb); 2753 dev_kfree_skb_any(skb);
2753 return NETDEV_TX_OK; 2754 return NETDEV_TX_OK;
2754 } 2755 }
@@ -2843,8 +2844,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2843 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb)); 2844 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2844 pkt_size = tx_start_bd->nbytes; 2845 pkt_size = tx_start_bd->nbytes;
2845 2846
2846 DP(NETIF_MSG_TX_QUEUED, "first bd @%p addr (%x:%x) nbd %d" 2847 DP(NETIF_MSG_TX_QUEUED,
2847 " nbytes %d flags %x vlan %x\n", 2848 "first bd @%p addr (%x:%x) nbd %d nbytes %d flags %x vlan %x\n",
2848 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo, 2849 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
2849 le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes), 2850 le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
2850 tx_start_bd->bd_flags.as_bitfield, 2851 tx_start_bd->bd_flags.as_bitfield,
@@ -2887,8 +2888,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2887 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 2888 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2888 unsigned int pkts_compl = 0, bytes_compl = 0; 2889 unsigned int pkts_compl = 0, bytes_compl = 0;
2889 2890
2890 DP(NETIF_MSG_TX_QUEUED, "Unable to map page - " 2891 DP(NETIF_MSG_TX_QUEUED,
2891 "dropping packet...\n"); 2892 "Unable to map page - dropping packet...\n");
2892 2893
2893 /* we need unmap all buffers already mapped 2894 /* we need unmap all buffers already mapped
2894 * for this SKB; 2895 * for this SKB;
@@ -2944,8 +2945,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
2944 2945
2945 if (pbd_e1x) 2946 if (pbd_e1x)
2946 DP(NETIF_MSG_TX_QUEUED, 2947 DP(NETIF_MSG_TX_QUEUED,
2947 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u" 2948 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n",
2948 " tcp_flags %x xsum %x seq %u hlen %u\n",
2949 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w, 2949 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w,
2950 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags, 2950 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags,
2951 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq, 2951 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq,
@@ -3021,23 +3021,22 @@ int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
3021 3021
3022 /* requested to support too many traffic classes */ 3022 /* requested to support too many traffic classes */
3023 if (num_tc > bp->max_cos) { 3023 if (num_tc > bp->max_cos) {
3024 DP(NETIF_MSG_TX_ERR, "support for too many traffic classes" 3024 BNX2X_ERR("support for too many traffic classes requested: %d. max supported is %d\n",
3025 " requested: %d. max supported is %d\n", 3025 num_tc, bp->max_cos);
3026 num_tc, bp->max_cos);
3027 return -EINVAL; 3026 return -EINVAL;
3028 } 3027 }
3029 3028
3030 /* declare amount of supported traffic classes */ 3029 /* declare amount of supported traffic classes */
3031 if (netdev_set_num_tc(dev, num_tc)) { 3030 if (netdev_set_num_tc(dev, num_tc)) {
3032 DP(NETIF_MSG_TX_ERR, "failed to declare %d traffic classes\n", 3031 BNX2X_ERR("failed to declare %d traffic classes\n", num_tc);
3033 num_tc);
3034 return -EINVAL; 3032 return -EINVAL;
3035 } 3033 }
3036 3034
3037 /* configure priority to traffic class mapping */ 3035 /* configure priority to traffic class mapping */
3038 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) { 3036 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
3039 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]); 3037 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
3040 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 3038 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3039 "mapping priority %d to tc %d\n",
3041 prio, bp->prio_to_cos[prio]); 3040 prio, bp->prio_to_cos[prio]);
3042 } 3041 }
3043 3042
@@ -3057,7 +3056,8 @@ int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
3057 count = BNX2X_NUM_ETH_QUEUES(bp); 3056 count = BNX2X_NUM_ETH_QUEUES(bp);
3058 offset = cos * MAX_TXQS_PER_COS; 3057 offset = cos * MAX_TXQS_PER_COS;
3059 netdev_set_tc_queue(dev, cos, count, offset); 3058 netdev_set_tc_queue(dev, cos, count, offset);
3060 DP(BNX2X_MSG_SP, "mapping tc %d to offset %d count %d\n", 3059 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3060 "mapping tc %d to offset %d count %d\n",
3061 cos, offset, count); 3061 cos, offset, count);
3062 } 3062 }
3063 3063
@@ -3071,12 +3071,16 @@ int bnx2x_change_mac_addr(struct net_device *dev, void *p)
3071 struct bnx2x *bp = netdev_priv(dev); 3071 struct bnx2x *bp = netdev_priv(dev);
3072 int rc = 0; 3072 int rc = 0;
3073 3073
3074 if (!bnx2x_is_valid_ether_addr(bp, addr->sa_data)) 3074 if (!bnx2x_is_valid_ether_addr(bp, addr->sa_data)) {
3075 BNX2X_ERR("Requested MAC address is not valid\n");
3075 return -EINVAL; 3076 return -EINVAL;
3077 }
3076 3078
3077#ifdef BCM_CNIC 3079#ifdef BCM_CNIC
3078 if (IS_MF_ISCSI_SD(bp) && !is_zero_ether_addr(addr->sa_data)) 3080 if (IS_MF_ISCSI_SD(bp) && !is_zero_ether_addr(addr->sa_data)) {
3081 BNX2X_ERR("Can't configure non-zero address on iSCSI or FCoE functions in MF-SD mode\n");
3079 return -EINVAL; 3082 return -EINVAL;
3083 }
3080#endif 3084#endif
3081 3085
3082 if (netif_running(dev)) { 3086 if (netif_running(dev)) {
@@ -3150,7 +3154,7 @@ static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
3150 for_each_cos_in_tx_queue(fp, cos) { 3154 for_each_cos_in_tx_queue(fp, cos) {
3151 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 3155 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
3152 3156
3153 DP(BNX2X_MSG_SP, 3157 DP(NETIF_MSG_IFDOWN,
3154 "freeing tx memory of fp %d cos %d cid %d\n", 3158 "freeing tx memory of fp %d cos %d cid %d\n",
3155 fp_index, cos, txdata->cid); 3159 fp_index, cos, txdata->cid);
3156 3160
@@ -3249,8 +3253,8 @@ static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
3249 for_each_cos_in_tx_queue(fp, cos) { 3253 for_each_cos_in_tx_queue(fp, cos) {
3250 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; 3254 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
3251 3255
3252 DP(BNX2X_MSG_SP, "allocating tx memory of " 3256 DP(NETIF_MSG_IFUP,
3253 "fp %d cos %d\n", 3257 "allocating tx memory of fp %d cos %d\n",
3254 index, cos); 3258 index, cos);
3255 3259
3256 BNX2X_ALLOC(txdata->tx_buf_ring, 3260 BNX2X_ALLOC(txdata->tx_buf_ring,
@@ -3487,6 +3491,7 @@ int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
3487 cp->fcoe_wwn_port_name_lo); 3491 cp->fcoe_wwn_port_name_lo);
3488 break; 3492 break;
3489 default: 3493 default:
3494 BNX2X_ERR("Wrong WWN type requested - %d\n", type);
3490 return -EINVAL; 3495 return -EINVAL;
3491 } 3496 }
3492 3497
@@ -3500,13 +3505,15 @@ int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
3500 struct bnx2x *bp = netdev_priv(dev); 3505 struct bnx2x *bp = netdev_priv(dev);
3501 3506
3502 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 3507 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3503 netdev_err(dev, "Handling parity error recovery. Try again later\n"); 3508 BNX2X_ERR("Can't perform change MTU during parity recovery\n");
3504 return -EAGAIN; 3509 return -EAGAIN;
3505 } 3510 }
3506 3511
3507 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) || 3512 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
3508 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE)) 3513 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE)) {
3514 BNX2X_ERR("Can't support requested MTU size\n");
3509 return -EINVAL; 3515 return -EINVAL;
3516 }
3510 3517
3511 /* This does not race with packet allocation 3518 /* This does not race with packet allocation
3512 * because the actual alloc size is 3519 * because the actual alloc size is
@@ -3636,7 +3643,7 @@ int bnx2x_resume(struct pci_dev *pdev)
3636 bp = netdev_priv(dev); 3643 bp = netdev_priv(dev);
3637 3644
3638 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 3645 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
3639 netdev_err(dev, "Handling parity error recovery. Try again later\n"); 3646 BNX2X_ERR("Handling parity error recovery. Try again later\n");
3640 return -EAGAIN; 3647 return -EAGAIN;
3641 } 3648 }
3642 3649
@@ -3681,8 +3688,9 @@ static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
3681 u32 addr = BAR_CSTRORM_INTMEM + 3688 u32 addr = BAR_CSTRORM_INTMEM +
3682 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index); 3689 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
3683 REG_WR8(bp, addr, ticks); 3690 REG_WR8(bp, addr, ticks);
3684 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n", 3691 DP(NETIF_MSG_IFUP,
3685 port, fw_sb_id, sb_index, ticks); 3692 "port %x fw_sb_id %d sb_index %d ticks %d\n",
3693 port, fw_sb_id, sb_index, ticks);
3686} 3694}
3687 3695
3688static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port, 3696static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
@@ -3697,8 +3705,9 @@ static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
3697 flags &= ~HC_INDEX_DATA_HC_ENABLED; 3705 flags &= ~HC_INDEX_DATA_HC_ENABLED;
3698 flags |= enable_flag; 3706 flags |= enable_flag;
3699 REG_WR16(bp, addr, flags); 3707 REG_WR16(bp, addr, flags);
3700 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n", 3708 DP(NETIF_MSG_IFUP,
3701 port, fw_sb_id, sb_index, disable); 3709 "port %x fw_sb_id %d sb_index %d disable %d\n",
3710 port, fw_sb_id, sb_index, disable);
3702} 3711}
3703 3712
3704void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 3713void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index 5904b1b1dad4..bba47fb8755c 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -598,7 +598,7 @@ static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id,
598 (update << IGU_REGULAR_BUPDATE_SHIFT) | 598 (update << IGU_REGULAR_BUPDATE_SHIFT) |
599 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 599 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
600 600
601 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", 601 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n",
602 cmd_data.sb_id_and_flags, igu_addr); 602 cmd_data.sb_id_and_flags, igu_addr);
603 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 603 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags);
604 604
@@ -648,8 +648,8 @@ static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
648 648
649 649
650 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 650 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
651 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " 651 DP(NETIF_MSG_HW,
652 "idu_sb_id %d offset %d bit %d (cnt %d)\n", 652 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
653 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 653 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
654 } 654 }
655} 655}
@@ -668,8 +668,6 @@ static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id,
668 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 668 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
669 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 669 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
670 670
671 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n",
672 (*(u32 *)&igu_ack), hc_addr);
673 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 671 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack));
674 672
675 /* Make sure that ACK is written */ 673 /* Make sure that ACK is written */
@@ -703,9 +701,6 @@ static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp)
703 COMMAND_REG_SIMD_MASK); 701 COMMAND_REG_SIMD_MASK);
704 u32 result = REG_RD(bp, hc_addr); 702 u32 result = REG_RD(bp, hc_addr);
705 703
706 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n",
707 result, hc_addr);
708
709 barrier(); 704 barrier();
710 return result; 705 return result;
711} 706}
@@ -715,7 +710,7 @@ static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp)
715 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 710 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
716 u32 result = REG_RD(bp, igu_addr); 711 u32 result = REG_RD(bp, igu_addr);
717 712
718 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", 713 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n",
719 result, igu_addr); 714 result, igu_addr);
720 715
721 barrier(); 716 barrier();
@@ -893,13 +888,16 @@ static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp,
893 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 888 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
894 dma_addr_t mapping; 889 dma_addr_t mapping;
895 890
896 if (unlikely(page == NULL)) 891 if (unlikely(page == NULL)) {
892 BNX2X_ERR("Can't alloc sge\n");
897 return -ENOMEM; 893 return -ENOMEM;
894 }
898 895
899 mapping = dma_map_page(&bp->pdev->dev, page, 0, 896 mapping = dma_map_page(&bp->pdev->dev, page, 0,
900 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 897 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE);
901 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 898 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
902 __free_pages(page, PAGES_PER_SGE_SHIFT); 899 __free_pages(page, PAGES_PER_SGE_SHIFT);
900 BNX2X_ERR("Can't map sge\n");
903 return -ENOMEM; 901 return -ENOMEM;
904 } 902 }
905 903
@@ -929,6 +927,7 @@ static inline int bnx2x_alloc_rx_data(struct bnx2x *bp,
929 DMA_FROM_DEVICE); 927 DMA_FROM_DEVICE);
930 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 928 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
931 kfree(data); 929 kfree(data);
930 BNX2X_ERR("Can't map rx data\n");
932 return -ENOMEM; 931 return -ENOMEM;
933 } 932 }
934 933
@@ -1299,7 +1298,7 @@ static inline void bnx2x_init_txdata(struct bnx2x *bp,
1299 txdata->txq_index = txq_index; 1298 txdata->txq_index = txq_index;
1300 txdata->tx_cons_sb = tx_cons_sb; 1299 txdata->tx_cons_sb = tx_cons_sb;
1301 1300
1302 DP(BNX2X_MSG_SP, "created tx data cid %d, txq %d\n", 1301 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n",
1303 txdata->cid, txdata->txq_index); 1302 txdata->cid, txdata->txq_index);
1304} 1303}
1305 1304
@@ -1344,7 +1343,7 @@ static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1344 bnx2x_init_txdata(bp, &bnx2x_fcoe(bp, txdata[0]), 1343 bnx2x_init_txdata(bp, &bnx2x_fcoe(bp, txdata[0]),
1345 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX); 1344 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX);
1346 1345
1347 DP(BNX2X_MSG_SP, "created fcoe tx data (fp index %d)\n", fp->index); 1346 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
1348 1347
1349 /* qZone id equals to FW (per path) client id */ 1348 /* qZone id equals to FW (per path) client id */
1350 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1349 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
@@ -1363,8 +1362,8 @@ static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp)
1363 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1362 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
1364 bnx2x_sp_mapping(bp, q_rdata), q_type); 1363 bnx2x_sp_mapping(bp, q_rdata), q_type);
1365 1364
1366 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d " 1365 DP(NETIF_MSG_IFUP,
1367 "igu_sb %d\n", 1366 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
1368 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1367 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
1369 fp->igu_sb_id); 1368 fp->igu_sb_id);
1370} 1369}
@@ -1377,8 +1376,7 @@ static inline int bnx2x_clean_tx_queue(struct bnx2x *bp,
1377 1376
1378 while (bnx2x_has_tx_work_unload(txdata)) { 1377 while (bnx2x_has_tx_work_unload(txdata)) {
1379 if (!cnt) { 1378 if (!cnt) {
1380 BNX2X_ERR("timeout waiting for queue[%d]: " 1379 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1381 "txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n",
1382 txdata->txq_index, txdata->tx_pkt_prod, 1380 txdata->txq_index, txdata->tx_pkt_prod,
1383 txdata->tx_pkt_cons); 1381 txdata->tx_pkt_cons);
1384#ifdef BNX2X_STOP_ON_ERROR 1382#ifdef BNX2X_STOP_ON_ERROR
@@ -1455,8 +1453,8 @@ static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask)
1455 1453
1456 netif_addr_lock_bh(bp->dev); 1454 netif_addr_lock_bh(bp->dev);
1457 if (bp->sp_state & mask) { 1455 if (bp->sp_state & mask) {
1458 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, " 1456 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n",
1459 "mask 0x%lx\n", bp->sp_state, mask); 1457 bp->sp_state, mask);
1460 netif_addr_unlock_bh(bp->dev); 1458 netif_addr_unlock_bh(bp->dev);
1461 return false; 1459 return false;
1462 } 1460 }
@@ -1492,7 +1490,7 @@ static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg)
1492 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1490 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
1493 FUNC_MF_CFG_MAX_BW_SHIFT; 1491 FUNC_MF_CFG_MAX_BW_SHIFT;
1494 if (!max_cfg) { 1492 if (!max_cfg) {
1495 DP(NETIF_MSG_LINK, 1493 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL,
1496 "Max BW configured to 0 - using 100 instead\n"); 1494 "Max BW configured to 0 - using 100 instead\n");
1497 max_cfg = 100; 1495 max_cfg = 100;
1498 } 1496 }
@@ -1655,7 +1653,7 @@ static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set)
1655 RESET_FLAGS(drv_flags, flags); 1653 RESET_FLAGS(drv_flags, flags);
1656 1654
1657 SHMEM2_WR(bp, drv_flags, drv_flags); 1655 SHMEM2_WR(bp, drv_flags, drv_flags);
1658 DP(NETIF_MSG_HW, "drv_flags 0x%08x\n", drv_flags); 1656 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags);
1659 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1657 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS);
1660 } 1658 }
1661} 1659}
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
index 4446a42e8bdc..b19669ab993b 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
@@ -167,27 +167,27 @@ static void bnx2x_dump_dcbx_drv_param(struct bnx2x *bp,
167 DCBX_PRI_PG_GET(features->ets.pri_pg_tbl, i)); 167 DCBX_PRI_PG_GET(features->ets.pri_pg_tbl, i));
168 168
169 /* pfc */ 169 /* pfc */
170 DP(NETIF_MSG_LINK, "dcbx_features.pfc.pri_en_bitmap %x\n", 170 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pri_en_bitmap %x\n",
171 features->pfc.pri_en_bitmap); 171 features->pfc.pri_en_bitmap);
172 DP(NETIF_MSG_LINK, "dcbx_features.pfc.pfc_caps %x\n", 172 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.pfc_caps %x\n",
173 features->pfc.pfc_caps); 173 features->pfc.pfc_caps);
174 DP(NETIF_MSG_LINK, "dcbx_features.pfc.enabled %x\n", 174 DP(BNX2X_MSG_DCB, "dcbx_features.pfc.enabled %x\n",
175 features->pfc.enabled); 175 features->pfc.enabled);
176 176
177 DP(NETIF_MSG_LINK, "dcbx_features.app.default_pri %x\n", 177 DP(BNX2X_MSG_DCB, "dcbx_features.app.default_pri %x\n",
178 features->app.default_pri); 178 features->app.default_pri);
179 DP(NETIF_MSG_LINK, "dcbx_features.app.tc_supported %x\n", 179 DP(BNX2X_MSG_DCB, "dcbx_features.app.tc_supported %x\n",
180 features->app.tc_supported); 180 features->app.tc_supported);
181 DP(NETIF_MSG_LINK, "dcbx_features.app.enabled %x\n", 181 DP(BNX2X_MSG_DCB, "dcbx_features.app.enabled %x\n",
182 features->app.enabled); 182 features->app.enabled);
183 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) { 183 for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
184 DP(NETIF_MSG_LINK, 184 DP(BNX2X_MSG_DCB,
185 "dcbx_features.app.app_pri_tbl[%x].app_id %x\n", 185 "dcbx_features.app.app_pri_tbl[%x].app_id %x\n",
186 i, features->app.app_pri_tbl[i].app_id); 186 i, features->app.app_pri_tbl[i].app_id);
187 DP(NETIF_MSG_LINK, 187 DP(BNX2X_MSG_DCB,
188 "dcbx_features.app.app_pri_tbl[%x].pri_bitmap %x\n", 188 "dcbx_features.app.app_pri_tbl[%x].pri_bitmap %x\n",
189 i, features->app.app_pri_tbl[i].pri_bitmap); 189 i, features->app.app_pri_tbl[i].pri_bitmap);
190 DP(NETIF_MSG_LINK, 190 DP(BNX2X_MSG_DCB,
191 "dcbx_features.app.app_pri_tbl[%x].appBitfield %x\n", 191 "dcbx_features.app.app_pri_tbl[%x].appBitfield %x\n",
192 i, features->app.app_pri_tbl[i].appBitfield); 192 i, features->app.app_pri_tbl[i].appBitfield);
193 } 193 }
@@ -221,10 +221,10 @@ static void bnx2x_dcbx_get_ap_feature(struct bnx2x *bp,
221 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority; 221 u32 *ttp = bp->dcbx_port_params.app.traffic_type_priority;
222 222
223 if (GET_FLAGS(error, DCBX_LOCAL_APP_ERROR)) 223 if (GET_FLAGS(error, DCBX_LOCAL_APP_ERROR))
224 DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_ERROR\n"); 224 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_ERROR\n");
225 225
226 if (GET_FLAGS(error, DCBX_LOCAL_APP_MISMATCH)) 226 if (GET_FLAGS(error, DCBX_LOCAL_APP_MISMATCH))
227 DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_MISMATCH\n"); 227 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_MISMATCH\n");
228 228
229 if (app->enabled && 229 if (app->enabled &&
230 !GET_FLAGS(error, DCBX_LOCAL_APP_ERROR | DCBX_LOCAL_APP_MISMATCH)) { 230 !GET_FLAGS(error, DCBX_LOCAL_APP_ERROR | DCBX_LOCAL_APP_MISMATCH)) {
@@ -256,7 +256,7 @@ static void bnx2x_dcbx_get_ap_feature(struct bnx2x *bp,
256 LLFC_TRAFFIC_TYPE_ISCSI); 256 LLFC_TRAFFIC_TYPE_ISCSI);
257 } 257 }
258 } else { 258 } else {
259 DP(NETIF_MSG_LINK, "DCBX_LOCAL_APP_DISABLED\n"); 259 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_APP_DISABLED\n");
260 bp->dcbx_port_params.app.enabled = false; 260 bp->dcbx_port_params.app.enabled = false;
261 for (index = 0 ; index < LLFC_DRIVER_TRAFFIC_TYPE_MAX; index++) 261 for (index = 0 ; index < LLFC_DRIVER_TRAFFIC_TYPE_MAX; index++)
262 ttp[index] = INVALID_TRAFFIC_TYPE_PRIORITY; 262 ttp[index] = INVALID_TRAFFIC_TYPE_PRIORITY;
@@ -276,7 +276,7 @@ static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
276 276
277 277
278 if (GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR)) 278 if (GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR))
279 DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_ERROR\n"); 279 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_ETS_ERROR\n");
280 280
281 281
282 /* Clean up old settings of ets on COS */ 282 /* Clean up old settings of ets on COS */
@@ -290,7 +290,7 @@ static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
290 if (bp->dcbx_port_params.app.enabled && 290 if (bp->dcbx_port_params.app.enabled &&
291 !GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR) && 291 !GET_FLAGS(error, DCBX_LOCAL_ETS_ERROR) &&
292 ets->enabled) { 292 ets->enabled) {
293 DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_ENABLE\n"); 293 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_ETS_ENABLE\n");
294 bp->dcbx_port_params.ets.enabled = true; 294 bp->dcbx_port_params.ets.enabled = true;
295 295
296 bnx2x_dcbx_get_ets_pri_pg_tbl(bp, 296 bnx2x_dcbx_get_ets_pri_pg_tbl(bp,
@@ -305,7 +305,7 @@ static void bnx2x_dcbx_get_ets_feature(struct bnx2x *bp,
305 ets, pg_pri_orginal_spread); 305 ets, pg_pri_orginal_spread);
306 306
307 } else { 307 } else {
308 DP(NETIF_MSG_LINK, "DCBX_LOCAL_ETS_DISABLED\n"); 308 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_ETS_DISABLED\n");
309 bp->dcbx_port_params.ets.enabled = false; 309 bp->dcbx_port_params.ets.enabled = false;
310 ets->pri_pg_tbl[0] = 0; 310 ets->pri_pg_tbl[0] = 0;
311 311
@@ -319,7 +319,7 @@ static void bnx2x_dcbx_get_pfc_feature(struct bnx2x *bp,
319{ 319{
320 320
321 if (GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR)) 321 if (GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR))
322 DP(NETIF_MSG_LINK, "DCBX_LOCAL_PFC_ERROR\n"); 322 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_PFC_ERROR\n");
323 323
324 if (bp->dcbx_port_params.app.enabled && 324 if (bp->dcbx_port_params.app.enabled &&
325 !GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR | DCBX_LOCAL_PFC_MISMATCH) && 325 !GET_FLAGS(error, DCBX_LOCAL_PFC_ERROR | DCBX_LOCAL_PFC_MISMATCH) &&
@@ -328,7 +328,7 @@ static void bnx2x_dcbx_get_pfc_feature(struct bnx2x *bp,
328 bp->dcbx_port_params.pfc.priority_non_pauseable_mask = 328 bp->dcbx_port_params.pfc.priority_non_pauseable_mask =
329 ~(pfc->pri_en_bitmap); 329 ~(pfc->pri_en_bitmap);
330 } else { 330 } else {
331 DP(NETIF_MSG_LINK, "DCBX_LOCAL_PFC_DISABLED\n"); 331 DP(BNX2X_MSG_DCB, "DCBX_LOCAL_PFC_DISABLED\n");
332 bp->dcbx_port_params.pfc.enabled = false; 332 bp->dcbx_port_params.pfc.enabled = false;
333 bp->dcbx_port_params.pfc.priority_non_pauseable_mask = 0; 333 bp->dcbx_port_params.pfc.priority_non_pauseable_mask = 0;
334 } 334 }
@@ -352,7 +352,7 @@ static void bnx2x_dcbx_map_nw(struct bnx2x *bp)
352 for (i = 0; i < ARRAY_SIZE(bp->dcbx_port_params.ets.cos_params); i++) { 352 for (i = 0; i < ARRAY_SIZE(bp->dcbx_port_params.ets.cos_params); i++) {
353 if (cos_params[i].pri_bitmask & nw_prio) { 353 if (cos_params[i].pri_bitmask & nw_prio) {
354 /* extend the bitmask with unmapped */ 354 /* extend the bitmask with unmapped */
355 DP(NETIF_MSG_LINK, 355 DP(BNX2X_MSG_DCB,
356 "cos %d extended with 0x%08x\n", i, unmapped); 356 "cos %d extended with 0x%08x\n", i, unmapped);
357 cos_params[i].pri_bitmask |= unmapped; 357 cos_params[i].pri_bitmask |= unmapped;
358 break; 358 break;
@@ -448,7 +448,7 @@ static int bnx2x_dcbx_stop_hw_tx(struct bnx2x *bp)
448 func_params.f_obj = &bp->func_obj; 448 func_params.f_obj = &bp->func_obj;
449 func_params.cmd = BNX2X_F_CMD_TX_STOP; 449 func_params.cmd = BNX2X_F_CMD_TX_STOP;
450 450
451 DP(NETIF_MSG_LINK, "STOP TRAFFIC\n"); 451 DP(BNX2X_MSG_DCB, "STOP TRAFFIC\n");
452 return bnx2x_func_state_change(bp, &func_params); 452 return bnx2x_func_state_change(bp, &func_params);
453} 453}
454 454
@@ -463,7 +463,7 @@ static int bnx2x_dcbx_resume_hw_tx(struct bnx2x *bp)
463 463
464 bnx2x_dcbx_fw_struct(bp, tx_params); 464 bnx2x_dcbx_fw_struct(bp, tx_params);
465 465
466 DP(NETIF_MSG_LINK, "START TRAFFIC\n"); 466 DP(BNX2X_MSG_DCB, "START TRAFFIC\n");
467 return bnx2x_func_state_change(bp, &func_params); 467 return bnx2x_func_state_change(bp, &func_params);
468} 468}
469 469
@@ -588,7 +588,7 @@ static int bnx2x_dcbx_read_shmem_remote_mib(struct bnx2x *bp)
588 u32 dcbx_remote_mib_offset = SHMEM2_RD(bp, dcbx_remote_mib_offset); 588 u32 dcbx_remote_mib_offset = SHMEM2_RD(bp, dcbx_remote_mib_offset);
589 int rc; 589 int rc;
590 590
591 DP(NETIF_MSG_LINK, "dcbx_remote_mib_offset 0x%x\n", 591 DP(BNX2X_MSG_DCB, "dcbx_remote_mib_offset 0x%x\n",
592 dcbx_remote_mib_offset); 592 dcbx_remote_mib_offset);
593 593
594 if (SHMEM_DCBX_REMOTE_MIB_NONE == dcbx_remote_mib_offset) { 594 if (SHMEM_DCBX_REMOTE_MIB_NONE == dcbx_remote_mib_offset) {
@@ -617,7 +617,7 @@ static int bnx2x_dcbx_read_shmem_neg_results(struct bnx2x *bp)
617 u32 dcbx_neg_res_offset = SHMEM2_RD(bp, dcbx_neg_res_offset); 617 u32 dcbx_neg_res_offset = SHMEM2_RD(bp, dcbx_neg_res_offset);
618 int rc; 618 int rc;
619 619
620 DP(NETIF_MSG_LINK, "dcbx_neg_res_offset 0x%x\n", dcbx_neg_res_offset); 620 DP(BNX2X_MSG_DCB, "dcbx_neg_res_offset 0x%x\n", dcbx_neg_res_offset);
621 621
622 if (SHMEM_DCBX_NEG_RES_NONE == dcbx_neg_res_offset) { 622 if (SHMEM_DCBX_NEG_RES_NONE == dcbx_neg_res_offset) {
623 BNX2X_ERR("FW doesn't support dcbx_neg_res_offset\n"); 623 BNX2X_ERR("FW doesn't support dcbx_neg_res_offset\n");
@@ -693,7 +693,7 @@ static inline void bnx2x_dcbx_update_tc_mapping(struct bnx2x *bp)
693 if (bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask 693 if (bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask
694 & (1 << prio)) { 694 & (1 << prio)) {
695 bp->prio_to_cos[prio] = cos; 695 bp->prio_to_cos[prio] = cos;
696 DP(NETIF_MSG_LINK, 696 DP(BNX2X_MSG_DCB,
697 "tx_mapping %d --> %d\n", prio, cos); 697 "tx_mapping %d --> %d\n", prio, cos);
698 } 698 }
699 } 699 }
@@ -712,7 +712,7 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
712 switch (state) { 712 switch (state) {
713 case BNX2X_DCBX_STATE_NEG_RECEIVED: 713 case BNX2X_DCBX_STATE_NEG_RECEIVED:
714 { 714 {
715 DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_NEG_RECEIVED\n"); 715 DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_NEG_RECEIVED\n");
716#ifdef BCM_DCBNL 716#ifdef BCM_DCBNL
717 /** 717 /**
718 * Delete app tlvs from dcbnl before reading new 718 * Delete app tlvs from dcbnl before reading new
@@ -762,7 +762,7 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
762 return; 762 return;
763 } 763 }
764 case BNX2X_DCBX_STATE_TX_PAUSED: 764 case BNX2X_DCBX_STATE_TX_PAUSED:
765 DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_TX_PAUSED\n"); 765 DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_TX_PAUSED\n");
766 bnx2x_pfc_set_pfc(bp); 766 bnx2x_pfc_set_pfc(bp);
767 767
768 bnx2x_dcbx_update_ets_params(bp); 768 bnx2x_dcbx_update_ets_params(bp);
@@ -770,7 +770,7 @@ void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state)
770 770
771 return; 771 return;
772 case BNX2X_DCBX_STATE_TX_RELEASED: 772 case BNX2X_DCBX_STATE_TX_RELEASED:
773 DP(NETIF_MSG_LINK, "BNX2X_DCBX_STATE_TX_RELEASED\n"); 773 DP(BNX2X_MSG_DCB, "BNX2X_DCBX_STATE_TX_RELEASED\n");
774 bnx2x_fw_command(bp, DRV_MSG_CODE_DCBX_PMF_DRV_OK, 0); 774 bnx2x_fw_command(bp, DRV_MSG_CODE_DCBX_PMF_DRV_OK, 0);
775#ifdef BCM_DCBNL 775#ifdef BCM_DCBNL
776 /* 776 /*
@@ -861,7 +861,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
861 DCBX_PG_BW_SET(af->ets.pg_bw_tbl, i, 861 DCBX_PG_BW_SET(af->ets.pg_bw_tbl, i,
862 (u8)dp->admin_configuration_bw_precentage[i]); 862 (u8)dp->admin_configuration_bw_precentage[i]);
863 863
864 DP(NETIF_MSG_LINK, "pg_bw_tbl[%d] = %02x\n", 864 DP(BNX2X_MSG_DCB, "pg_bw_tbl[%d] = %02x\n",
865 i, DCBX_PG_BW_GET(af->ets.pg_bw_tbl, i)); 865 i, DCBX_PG_BW_GET(af->ets.pg_bw_tbl, i));
866 } 866 }
867 867
@@ -869,7 +869,7 @@ static void bnx2x_dcbx_admin_mib_updated_params(struct bnx2x *bp,
869 DCBX_PRI_PG_SET(af->ets.pri_pg_tbl, i, 869 DCBX_PRI_PG_SET(af->ets.pri_pg_tbl, i,
870 (u8)dp->admin_configuration_ets_pg[i]); 870 (u8)dp->admin_configuration_ets_pg[i]);
871 871
872 DP(NETIF_MSG_LINK, "pri_pg_tbl[%d] = %02x\n", 872 DP(BNX2X_MSG_DCB, "pri_pg_tbl[%d] = %02x\n",
873 i, DCBX_PRI_PG_GET(af->ets.pri_pg_tbl, i)); 873 i, DCBX_PRI_PG_GET(af->ets.pri_pg_tbl, i));
874 } 874 }
875 875
@@ -923,7 +923,7 @@ void bnx2x_dcbx_set_state(struct bnx2x *bp, bool dcb_on, u32 dcbx_enabled)
923 bp->dcb_state = false; 923 bp->dcb_state = false;
924 bp->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID; 924 bp->dcbx_enabled = BNX2X_DCBX_ENABLED_INVALID;
925 } 925 }
926 DP(NETIF_MSG_LINK, "DCB state [%s:%s]\n", 926 DP(BNX2X_MSG_DCB, "DCB state [%s:%s]\n",
927 dcb_on ? "ON" : "OFF", 927 dcb_on ? "ON" : "OFF",
928 dcbx_enabled == BNX2X_DCBX_ENABLED_OFF ? "user-mode" : 928 dcbx_enabled == BNX2X_DCBX_ENABLED_OFF ? "user-mode" :
929 dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_OFF ? "on-chip static" : 929 dcbx_enabled == BNX2X_DCBX_ENABLED_ON_NEG_OFF ? "on-chip static" :
@@ -1011,7 +1011,7 @@ void bnx2x_dcbx_init(struct bnx2x *bp)
1011 * the function is pmf 1011 * the function is pmf
1012 * shmem2 contains DCBX support fields 1012 * shmem2 contains DCBX support fields
1013 */ 1013 */
1014 DP(NETIF_MSG_LINK, "dcb_state %d bp->port.pmf %d\n", 1014 DP(BNX2X_MSG_DCB, "dcb_state %d bp->port.pmf %d\n",
1015 bp->dcb_state, bp->port.pmf); 1015 bp->dcb_state, bp->port.pmf);
1016 1016
1017 if (bp->dcb_state == BNX2X_DCB_STATE_ON && bp->port.pmf && 1017 if (bp->dcb_state == BNX2X_DCB_STATE_ON && bp->port.pmf &&
@@ -1019,7 +1019,7 @@ void bnx2x_dcbx_init(struct bnx2x *bp)
1019 dcbx_lldp_params_offset = 1019 dcbx_lldp_params_offset =
1020 SHMEM2_RD(bp, dcbx_lldp_params_offset); 1020 SHMEM2_RD(bp, dcbx_lldp_params_offset);
1021 1021
1022 DP(NETIF_MSG_LINK, "dcbx_lldp_params_offset 0x%x\n", 1022 DP(BNX2X_MSG_DCB, "dcbx_lldp_params_offset 0x%x\n",
1023 dcbx_lldp_params_offset); 1023 dcbx_lldp_params_offset);
1024 1024
1025 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_DCB_CONFIGURED, 0); 1025 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_DCB_CONFIGURED, 0);
@@ -1041,38 +1041,36 @@ bnx2x_dcbx_print_cos_params(struct bnx2x *bp,
1041 u8 pri = 0; 1041 u8 pri = 0;
1042 u8 cos = 0; 1042 u8 cos = 0;
1043 1043
1044 DP(NETIF_MSG_LINK, 1044 DP(BNX2X_MSG_DCB,
1045 "pfc_fw_cfg->dcb_version %x\n", pfc_fw_cfg->dcb_version); 1045 "pfc_fw_cfg->dcb_version %x\n", pfc_fw_cfg->dcb_version);
1046 DP(NETIF_MSG_LINK, 1046 DP(BNX2X_MSG_DCB,
1047 "pdev->params.dcbx_port_params.pfc." 1047 "pdev->params.dcbx_port_params.pfc.priority_non_pauseable_mask %x\n",
1048 "priority_non_pauseable_mask %x\n",
1049 bp->dcbx_port_params.pfc.priority_non_pauseable_mask); 1048 bp->dcbx_port_params.pfc.priority_non_pauseable_mask);
1050 1049
1051 for (cos = 0 ; cos < bp->dcbx_port_params.ets.num_of_cos ; cos++) { 1050 for (cos = 0 ; cos < bp->dcbx_port_params.ets.num_of_cos ; cos++) {
1052 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets." 1051 DP(BNX2X_MSG_DCB,
1053 "cos_params[%d].pri_bitmask %x\n", cos, 1052 "pdev->params.dcbx_port_params.ets.cos_params[%d].pri_bitmask %x\n",
1054 bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask); 1053 cos, bp->dcbx_port_params.ets.cos_params[cos].pri_bitmask);
1055 1054
1056 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets." 1055 DP(BNX2X_MSG_DCB,
1057 "cos_params[%d].bw_tbl %x\n", cos, 1056 "pdev->params.dcbx_port_params.ets.cos_params[%d].bw_tbl %x\n",
1058 bp->dcbx_port_params.ets.cos_params[cos].bw_tbl); 1057 cos, bp->dcbx_port_params.ets.cos_params[cos].bw_tbl);
1059 1058
1060 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets." 1059 DP(BNX2X_MSG_DCB,
1061 "cos_params[%d].strict %x\n", cos, 1060 "pdev->params.dcbx_port_params.ets.cos_params[%d].strict %x\n",
1062 bp->dcbx_port_params.ets.cos_params[cos].strict); 1061 cos, bp->dcbx_port_params.ets.cos_params[cos].strict);
1063 1062
1064 DP(NETIF_MSG_LINK, "pdev->params.dcbx_port_params.ets." 1063 DP(BNX2X_MSG_DCB,
1065 "cos_params[%d].pauseable %x\n", cos, 1064 "pdev->params.dcbx_port_params.ets.cos_params[%d].pauseable %x\n",
1066 bp->dcbx_port_params.ets.cos_params[cos].pauseable); 1065 cos, bp->dcbx_port_params.ets.cos_params[cos].pauseable);
1067 } 1066 }
1068 1067
1069 for (pri = 0; pri < LLFC_DRIVER_TRAFFIC_TYPE_MAX; pri++) { 1068 for (pri = 0; pri < LLFC_DRIVER_TRAFFIC_TYPE_MAX; pri++) {
1070 DP(NETIF_MSG_LINK, 1069 DP(BNX2X_MSG_DCB,
1071 "pfc_fw_cfg->traffic_type_to_priority_cos[%d]." 1070 "pfc_fw_cfg->traffic_type_to_priority_cos[%d].priority %x\n",
1072 "priority %x\n", pri, 1071 pri, pfc_fw_cfg->traffic_type_to_priority_cos[pri].priority);
1073 pfc_fw_cfg->traffic_type_to_priority_cos[pri].priority);
1074 1072
1075 DP(NETIF_MSG_LINK, 1073 DP(BNX2X_MSG_DCB,
1076 "pfc_fw_cfg->traffic_type_to_priority_cos[%d].cos %x\n", 1074 "pfc_fw_cfg->traffic_type_to_priority_cos[%d].cos %x\n",
1077 pri, pfc_fw_cfg->traffic_type_to_priority_cos[pri].cos); 1075 pri, pfc_fw_cfg->traffic_type_to_priority_cos[pri].cos);
1078 } 1076 }
@@ -1119,7 +1117,7 @@ static void bnx2x_dcbx_get_num_pg_traf_type(struct bnx2x *bp,
1119 help_data->num_of_pg++; 1117 help_data->num_of_pg++;
1120 } 1118 }
1121 } 1119 }
1122 DP(NETIF_MSG_LINK, 1120 DP(BNX2X_MSG_DCB,
1123 "add_traf_type %d pg_found %s num_of_pg %d\n", 1121 "add_traf_type %d pg_found %s num_of_pg %d\n",
1124 add_traf_type, (false == pg_found) ? "NO" : "YES", 1122 add_traf_type, (false == pg_found) ? "NO" : "YES",
1125 help_data->num_of_pg); 1123 help_data->num_of_pg);
@@ -1312,8 +1310,7 @@ static void bnx2x_dcbx_2cos_limit_cee_single_pg_to_cos_params(struct bnx2x *bp,
1312 } 1310 }
1313 1311
1314 if (i == LLFC_DRIVER_TRAFFIC_TYPE_MAX) 1312 if (i == LLFC_DRIVER_TRAFFIC_TYPE_MAX)
1315 BNX2X_ERR("Invalid value for pri_join_mask -" 1313 BNX2X_ERR("Invalid value for pri_join_mask - could not find a priority\n");
1316 " could not find a priority\n");
1317 1314
1318 cos_data->data[0].pri_join_mask = pri_mask_without_pri; 1315 cos_data->data[0].pri_join_mask = pri_mask_without_pri;
1319 cos_data->data[1].pri_join_mask = pri_tested; 1316 cos_data->data[1].pri_join_mask = pri_tested;
@@ -1626,8 +1623,10 @@ static int bnx2x_dcbx_spread_strict_pri(struct bnx2x *bp,
1626 num_of_app_pri--; 1623 num_of_app_pri--;
1627 } 1624 }
1628 1625
1629 if (num_spread_of_entries) 1626 if (num_spread_of_entries) {
1627 BNX2X_ERR("Didn't succeed to spread strict priorities\n");
1630 return -EINVAL; 1628 return -EINVAL;
1629 }
1631 1630
1632 return 0; 1631 return 0;
1633} 1632}
@@ -1675,8 +1674,7 @@ static void bnx2x_dcbx_cee_fill_cos_params(struct bnx2x *bp,
1675 if (help_data->num_of_pg > DCBX_COS_MAX_NUM_E3B0) { 1674 if (help_data->num_of_pg > DCBX_COS_MAX_NUM_E3B0) {
1676 if (bnx2x_dcbx_join_pgs(bp, ets, help_data, 1675 if (bnx2x_dcbx_join_pgs(bp, ets, help_data,
1677 DCBX_COS_MAX_NUM_E3B0)) { 1676 DCBX_COS_MAX_NUM_E3B0)) {
1678 BNX2X_ERR("Unable to reduce the number of PGs -" 1677 BNX2X_ERR("Unable to reduce the number of PGs - we will disables ETS\n");
1679 "we will disables ETS\n");
1680 bnx2x_dcbx_ets_disabled_entry_data(bp, cos_data, 1678 bnx2x_dcbx_ets_disabled_entry_data(bp, cos_data,
1681 pri_join_mask); 1679 pri_join_mask);
1682 return; 1680 return;
@@ -1776,24 +1774,24 @@ static void bnx2x_dcbx_fill_cos_params(struct bnx2x *bp,
1776 if (p->pauseable && 1774 if (p->pauseable &&
1777 DCBX_PFC_PRI_GET_NON_PAUSE(bp, 1775 DCBX_PFC_PRI_GET_NON_PAUSE(bp,
1778 p->pri_bitmask) != 0) 1776 p->pri_bitmask) != 0)
1779 BNX2X_ERR("Inconsistent config for " 1777 BNX2X_ERR("Inconsistent config for pausable COS %d\n",
1780 "pausable COS %d\n", i); 1778 i);
1781 1779
1782 if (!p->pauseable && 1780 if (!p->pauseable &&
1783 DCBX_PFC_PRI_GET_PAUSE(bp, 1781 DCBX_PFC_PRI_GET_PAUSE(bp,
1784 p->pri_bitmask) != 0) 1782 p->pri_bitmask) != 0)
1785 BNX2X_ERR("Inconsistent config for " 1783 BNX2X_ERR("Inconsistent config for nonpausable COS %d\n",
1786 "nonpausable COS %d\n", i); 1784 i);
1787 } 1785 }
1788 } 1786 }
1789 1787
1790 if (p->pauseable) 1788 if (p->pauseable)
1791 DP(NETIF_MSG_LINK, "COS %d PAUSABLE prijoinmask 0x%x\n", 1789 DP(BNX2X_MSG_DCB, "COS %d PAUSABLE prijoinmask 0x%x\n",
1792 i, cos_data.data[i].pri_join_mask); 1790 i, cos_data.data[i].pri_join_mask);
1793 else 1791 else
1794 DP(NETIF_MSG_LINK, "COS %d NONPAUSABLE prijoinmask " 1792 DP(BNX2X_MSG_DCB,
1795 "0x%x\n", 1793 "COS %d NONPAUSABLE prijoinmask 0x%x\n",
1796 i, cos_data.data[i].pri_join_mask); 1794 i, cos_data.data[i].pri_join_mask);
1797 } 1795 }
1798 1796
1799 bp->dcbx_port_params.ets.num_of_cos = cos_data.num_of_cos ; 1797 bp->dcbx_port_params.ets.num_of_cos = cos_data.num_of_cos ;
@@ -1808,7 +1806,7 @@ static void bnx2x_dcbx_get_ets_pri_pg_tbl(struct bnx2x *bp,
1808 for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) { 1806 for (i = 0; i < DCBX_MAX_NUM_PRI_PG_ENTRIES; i++) {
1809 set_configuration_ets_pg[i] = DCBX_PRI_PG_GET(pri_pg_tbl, i); 1807 set_configuration_ets_pg[i] = DCBX_PRI_PG_GET(pri_pg_tbl, i);
1810 1808
1811 DP(NETIF_MSG_LINK, "set_configuration_ets_pg[%d] = 0x%x\n", 1809 DP(BNX2X_MSG_DCB, "set_configuration_ets_pg[%d] = 0x%x\n",
1812 i, set_configuration_ets_pg[i]); 1810 i, set_configuration_ets_pg[i]);
1813 } 1811 }
1814} 1812}
@@ -1904,14 +1902,14 @@ static inline bool bnx2x_dcbnl_set_valid(struct bnx2x *bp)
1904static u8 bnx2x_dcbnl_get_state(struct net_device *netdev) 1902static u8 bnx2x_dcbnl_get_state(struct net_device *netdev)
1905{ 1903{
1906 struct bnx2x *bp = netdev_priv(netdev); 1904 struct bnx2x *bp = netdev_priv(netdev);
1907 DP(NETIF_MSG_LINK, "state = %d\n", bp->dcb_state); 1905 DP(BNX2X_MSG_DCB, "state = %d\n", bp->dcb_state);
1908 return bp->dcb_state; 1906 return bp->dcb_state;
1909} 1907}
1910 1908
1911static u8 bnx2x_dcbnl_set_state(struct net_device *netdev, u8 state) 1909static u8 bnx2x_dcbnl_set_state(struct net_device *netdev, u8 state)
1912{ 1910{
1913 struct bnx2x *bp = netdev_priv(netdev); 1911 struct bnx2x *bp = netdev_priv(netdev);
1914 DP(NETIF_MSG_LINK, "state = %s\n", state ? "on" : "off"); 1912 DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off");
1915 1913
1916 bnx2x_dcbx_set_state(bp, (state ? true : false), bp->dcbx_enabled); 1914 bnx2x_dcbx_set_state(bp, (state ? true : false), bp->dcbx_enabled);
1917 return 0; 1915 return 0;
@@ -1921,7 +1919,7 @@ static void bnx2x_dcbnl_get_perm_hw_addr(struct net_device *netdev,
1921 u8 *perm_addr) 1919 u8 *perm_addr)
1922{ 1920{
1923 struct bnx2x *bp = netdev_priv(netdev); 1921 struct bnx2x *bp = netdev_priv(netdev);
1924 DP(NETIF_MSG_LINK, "GET-PERM-ADDR\n"); 1922 DP(BNX2X_MSG_DCB, "GET-PERM-ADDR\n");
1925 1923
1926 /* first the HW mac address */ 1924 /* first the HW mac address */
1927 memcpy(perm_addr, netdev->dev_addr, netdev->addr_len); 1925 memcpy(perm_addr, netdev->dev_addr, netdev->addr_len);
@@ -1938,7 +1936,7 @@ static void bnx2x_dcbnl_set_pg_tccfg_tx(struct net_device *netdev, int prio,
1938{ 1936{
1939 struct bnx2x *bp = netdev_priv(netdev); 1937 struct bnx2x *bp = netdev_priv(netdev);
1940 1938
1941 DP(NETIF_MSG_LINK, "prio[%d] = %d\n", prio, pgid); 1939 DP(BNX2X_MSG_DCB, "prio[%d] = %d\n", prio, pgid);
1942 if (!bnx2x_dcbnl_set_valid(bp) || prio >= DCBX_MAX_NUM_PRI_PG_ENTRIES) 1940 if (!bnx2x_dcbnl_set_valid(bp) || prio >= DCBX_MAX_NUM_PRI_PG_ENTRIES)
1943 return; 1941 return;
1944 1942
@@ -1963,7 +1961,7 @@ static void bnx2x_dcbnl_set_pg_bwgcfg_tx(struct net_device *netdev,
1963 int pgid, u8 bw_pct) 1961 int pgid, u8 bw_pct)
1964{ 1962{
1965 struct bnx2x *bp = netdev_priv(netdev); 1963 struct bnx2x *bp = netdev_priv(netdev);
1966 DP(NETIF_MSG_LINK, "pgid[%d] = %d\n", pgid, bw_pct); 1964 DP(BNX2X_MSG_DCB, "pgid[%d] = %d\n", pgid, bw_pct);
1967 1965
1968 if (!bnx2x_dcbnl_set_valid(bp) || pgid >= DCBX_MAX_NUM_PG_BW_ENTRIES) 1966 if (!bnx2x_dcbnl_set_valid(bp) || pgid >= DCBX_MAX_NUM_PG_BW_ENTRIES)
1969 return; 1967 return;
@@ -1977,14 +1975,14 @@ static void bnx2x_dcbnl_set_pg_tccfg_rx(struct net_device *netdev, int prio,
1977 u8 up_map) 1975 u8 up_map)
1978{ 1976{
1979 struct bnx2x *bp = netdev_priv(netdev); 1977 struct bnx2x *bp = netdev_priv(netdev);
1980 DP(NETIF_MSG_LINK, "Nothing to set; No RX support\n"); 1978 DP(BNX2X_MSG_DCB, "Nothing to set; No RX support\n");
1981} 1979}
1982 1980
1983static void bnx2x_dcbnl_set_pg_bwgcfg_rx(struct net_device *netdev, 1981static void bnx2x_dcbnl_set_pg_bwgcfg_rx(struct net_device *netdev,
1984 int pgid, u8 bw_pct) 1982 int pgid, u8 bw_pct)
1985{ 1983{
1986 struct bnx2x *bp = netdev_priv(netdev); 1984 struct bnx2x *bp = netdev_priv(netdev);
1987 DP(NETIF_MSG_LINK, "Nothing to set; No RX support\n"); 1985 DP(BNX2X_MSG_DCB, "Nothing to set; No RX support\n");
1988} 1986}
1989 1987
1990static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio, 1988static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio,
@@ -1992,7 +1990,7 @@ static void bnx2x_dcbnl_get_pg_tccfg_tx(struct net_device *netdev, int prio,
1992 u8 *up_map) 1990 u8 *up_map)
1993{ 1991{
1994 struct bnx2x *bp = netdev_priv(netdev); 1992 struct bnx2x *bp = netdev_priv(netdev);
1995 DP(NETIF_MSG_LINK, "prio = %d\n", prio); 1993 DP(BNX2X_MSG_DCB, "prio = %d\n", prio);
1996 1994
1997 /** 1995 /**
1998 * bw_pct ingnored - band-width percentage devision between user 1996 * bw_pct ingnored - band-width percentage devision between user
@@ -2018,7 +2016,7 @@ static void bnx2x_dcbnl_get_pg_bwgcfg_tx(struct net_device *netdev,
2018 int pgid, u8 *bw_pct) 2016 int pgid, u8 *bw_pct)
2019{ 2017{
2020 struct bnx2x *bp = netdev_priv(netdev); 2018 struct bnx2x *bp = netdev_priv(netdev);
2021 DP(NETIF_MSG_LINK, "pgid = %d\n", pgid); 2019 DP(BNX2X_MSG_DCB, "pgid = %d\n", pgid);
2022 2020
2023 *bw_pct = 0; 2021 *bw_pct = 0;
2024 2022
@@ -2033,7 +2031,7 @@ static void bnx2x_dcbnl_get_pg_tccfg_rx(struct net_device *netdev, int prio,
2033 u8 *up_map) 2031 u8 *up_map)
2034{ 2032{
2035 struct bnx2x *bp = netdev_priv(netdev); 2033 struct bnx2x *bp = netdev_priv(netdev);
2036 DP(NETIF_MSG_LINK, "Nothing to get; No RX support\n"); 2034 DP(BNX2X_MSG_DCB, "Nothing to get; No RX support\n");
2037 2035
2038 *prio_type = *pgid = *bw_pct = *up_map = 0; 2036 *prio_type = *pgid = *bw_pct = *up_map = 0;
2039} 2037}
@@ -2042,7 +2040,7 @@ static void bnx2x_dcbnl_get_pg_bwgcfg_rx(struct net_device *netdev,
2042 int pgid, u8 *bw_pct) 2040 int pgid, u8 *bw_pct)
2043{ 2041{
2044 struct bnx2x *bp = netdev_priv(netdev); 2042 struct bnx2x *bp = netdev_priv(netdev);
2045 DP(NETIF_MSG_LINK, "Nothing to get; No RX support\n"); 2043 DP(BNX2X_MSG_DCB, "Nothing to get; No RX support\n");
2046 2044
2047 *bw_pct = 0; 2045 *bw_pct = 0;
2048} 2046}
@@ -2051,7 +2049,7 @@ static void bnx2x_dcbnl_set_pfc_cfg(struct net_device *netdev, int prio,
2051 u8 setting) 2049 u8 setting)
2052{ 2050{
2053 struct bnx2x *bp = netdev_priv(netdev); 2051 struct bnx2x *bp = netdev_priv(netdev);
2054 DP(NETIF_MSG_LINK, "prio[%d] = %d\n", prio, setting); 2052 DP(BNX2X_MSG_DCB, "prio[%d] = %d\n", prio, setting);
2055 2053
2056 if (!bnx2x_dcbnl_set_valid(bp) || prio >= MAX_PFC_PRIORITIES) 2054 if (!bnx2x_dcbnl_set_valid(bp) || prio >= MAX_PFC_PRIORITIES)
2057 return; 2055 return;
@@ -2066,7 +2064,7 @@ static void bnx2x_dcbnl_get_pfc_cfg(struct net_device *netdev, int prio,
2066 u8 *setting) 2064 u8 *setting)
2067{ 2065{
2068 struct bnx2x *bp = netdev_priv(netdev); 2066 struct bnx2x *bp = netdev_priv(netdev);
2069 DP(NETIF_MSG_LINK, "prio = %d\n", prio); 2067 DP(BNX2X_MSG_DCB, "prio = %d\n", prio);
2070 2068
2071 *setting = 0; 2069 *setting = 0;
2072 2070
@@ -2081,21 +2079,21 @@ static u8 bnx2x_dcbnl_set_all(struct net_device *netdev)
2081 struct bnx2x *bp = netdev_priv(netdev); 2079 struct bnx2x *bp = netdev_priv(netdev);
2082 int rc = 0; 2080 int rc = 0;
2083 2081
2084 DP(NETIF_MSG_LINK, "SET-ALL\n"); 2082 DP(BNX2X_MSG_DCB, "SET-ALL\n");
2085 2083
2086 if (!bnx2x_dcbnl_set_valid(bp)) 2084 if (!bnx2x_dcbnl_set_valid(bp))
2087 return 1; 2085 return 1;
2088 2086
2089 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2087 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2090 netdev_err(bp->dev, "Handling parity error recovery. " 2088 netdev_err(bp->dev,
2091 "Try again later\n"); 2089 "Handling parity error recovery. Try again later\n");
2092 return 1; 2090 return 1;
2093 } 2091 }
2094 if (netif_running(bp->dev)) { 2092 if (netif_running(bp->dev)) {
2095 bnx2x_nic_unload(bp, UNLOAD_NORMAL); 2093 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
2096 rc = bnx2x_nic_load(bp, LOAD_NORMAL); 2094 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2097 } 2095 }
2098 DP(NETIF_MSG_LINK, "set_dcbx_params done (%d)\n", rc); 2096 DP(BNX2X_MSG_DCB, "set_dcbx_params done (%d)\n", rc);
2099 if (rc) 2097 if (rc)
2100 return 1; 2098 return 1;
2101 2099
@@ -2134,13 +2132,16 @@ static u8 bnx2x_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap)
2134 *cap = BNX2X_DCBX_CAPS; 2132 *cap = BNX2X_DCBX_CAPS;
2135 break; 2133 break;
2136 default: 2134 default:
2135 BNX2X_ERR("Non valid capability ID\n");
2137 rval = -EINVAL; 2136 rval = -EINVAL;
2138 break; 2137 break;
2139 } 2138 }
2140 } else 2139 } else {
2140 DP(BNX2X_MSG_DCB, "DCB disabled\n");
2141 rval = -EINVAL; 2141 rval = -EINVAL;
2142 }
2142 2143
2143 DP(NETIF_MSG_LINK, "capid %d:%x\n", capid, *cap); 2144 DP(BNX2X_MSG_DCB, "capid %d:%x\n", capid, *cap);
2144 return rval; 2145 return rval;
2145} 2146}
2146 2147
@@ -2149,7 +2150,7 @@ static int bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid, u8 *num)
2149 struct bnx2x *bp = netdev_priv(netdev); 2150 struct bnx2x *bp = netdev_priv(netdev);
2150 u8 rval = 0; 2151 u8 rval = 0;
2151 2152
2152 DP(NETIF_MSG_LINK, "tcid %d\n", tcid); 2153 DP(BNX2X_MSG_DCB, "tcid %d\n", tcid);
2153 2154
2154 if (bp->dcb_state) { 2155 if (bp->dcb_state) {
2155 switch (tcid) { 2156 switch (tcid) {
@@ -2162,11 +2163,14 @@ static int bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid, u8 *num)
2162 DCBX_COS_MAX_NUM_E2; 2163 DCBX_COS_MAX_NUM_E2;
2163 break; 2164 break;
2164 default: 2165 default:
2166 BNX2X_ERR("Non valid TC-ID\n");
2165 rval = -EINVAL; 2167 rval = -EINVAL;
2166 break; 2168 break;
2167 } 2169 }
2168 } else 2170 } else {
2171 DP(BNX2X_MSG_DCB, "DCB disabled\n");
2169 rval = -EINVAL; 2172 rval = -EINVAL;
2173 }
2170 2174
2171 return rval; 2175 return rval;
2172} 2176}
@@ -2174,14 +2178,14 @@ static int bnx2x_dcbnl_get_numtcs(struct net_device *netdev, int tcid, u8 *num)
2174static int bnx2x_dcbnl_set_numtcs(struct net_device *netdev, int tcid, u8 num) 2178static int bnx2x_dcbnl_set_numtcs(struct net_device *netdev, int tcid, u8 num)
2175{ 2179{
2176 struct bnx2x *bp = netdev_priv(netdev); 2180 struct bnx2x *bp = netdev_priv(netdev);
2177 DP(NETIF_MSG_LINK, "num tcs = %d; Not supported\n", num); 2181 DP(BNX2X_MSG_DCB, "num tcs = %d; Not supported\n", num);
2178 return -EINVAL; 2182 return -EINVAL;
2179} 2183}
2180 2184
2181static u8 bnx2x_dcbnl_get_pfc_state(struct net_device *netdev) 2185static u8 bnx2x_dcbnl_get_pfc_state(struct net_device *netdev)
2182{ 2186{
2183 struct bnx2x *bp = netdev_priv(netdev); 2187 struct bnx2x *bp = netdev_priv(netdev);
2184 DP(NETIF_MSG_LINK, "state = %d\n", bp->dcbx_local_feat.pfc.enabled); 2188 DP(BNX2X_MSG_DCB, "state = %d\n", bp->dcbx_local_feat.pfc.enabled);
2185 2189
2186 if (!bp->dcb_state) 2190 if (!bp->dcb_state)
2187 return 0; 2191 return 0;
@@ -2192,7 +2196,7 @@ static u8 bnx2x_dcbnl_get_pfc_state(struct net_device *netdev)
2192static void bnx2x_dcbnl_set_pfc_state(struct net_device *netdev, u8 state) 2196static void bnx2x_dcbnl_set_pfc_state(struct net_device *netdev, u8 state)
2193{ 2197{
2194 struct bnx2x *bp = netdev_priv(netdev); 2198 struct bnx2x *bp = netdev_priv(netdev);
2195 DP(NETIF_MSG_LINK, "state = %s\n", state ? "on" : "off"); 2199 DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off");
2196 2200
2197 if (!bnx2x_dcbnl_set_valid(bp)) 2201 if (!bnx2x_dcbnl_set_valid(bp))
2198 return; 2202 return;
@@ -2269,9 +2273,11 @@ static int bnx2x_set_admin_app_up(struct bnx2x *bp, u8 idtype, u16 idval, u8 up)
2269 bnx2x_admin_app_set_ent( 2273 bnx2x_admin_app_set_ent(
2270 &bp->dcbx_config_params.admin_priority_app_table[ff], 2274 &bp->dcbx_config_params.admin_priority_app_table[ff],
2271 idtype, idval, up); 2275 idtype, idval, up);
2272 else 2276 else {
2273 /* app table is full */ 2277 /* app table is full */
2278 BNX2X_ERR("Application table is too large\n");
2274 return -EBUSY; 2279 return -EBUSY;
2280 }
2275 2281
2276 /* up configured, if not 0 make sure feature is enabled */ 2282 /* up configured, if not 0 make sure feature is enabled */
2277 if (up) 2283 if (up)
@@ -2285,11 +2291,13 @@ static u8 bnx2x_dcbnl_set_app_up(struct net_device *netdev, u8 idtype,
2285{ 2291{
2286 struct bnx2x *bp = netdev_priv(netdev); 2292 struct bnx2x *bp = netdev_priv(netdev);
2287 2293
2288 DP(NETIF_MSG_LINK, "app_type %d, app_id %x, prio bitmap %d\n", 2294 DP(BNX2X_MSG_DCB, "app_type %d, app_id %x, prio bitmap %d\n",
2289 idtype, idval, up); 2295 idtype, idval, up);
2290 2296
2291 if (!bnx2x_dcbnl_set_valid(bp)) 2297 if (!bnx2x_dcbnl_set_valid(bp)) {
2298 DP(BNX2X_MSG_DCB, "dcbnl call not valid\n");
2292 return -EINVAL; 2299 return -EINVAL;
2300 }
2293 2301
2294 /* verify idtype */ 2302 /* verify idtype */
2295 switch (idtype) { 2303 switch (idtype) {
@@ -2297,6 +2305,7 @@ static u8 bnx2x_dcbnl_set_app_up(struct net_device *netdev, u8 idtype,
2297 case DCB_APP_IDTYPE_PORTNUM: 2305 case DCB_APP_IDTYPE_PORTNUM:
2298 break; 2306 break;
2299 default: 2307 default:
2308 DP(BNX2X_MSG_DCB, "Wrong ID type\n");
2300 return -EINVAL; 2309 return -EINVAL;
2301 } 2310 }
2302 return bnx2x_set_admin_app_up(bp, idtype, idval, up); 2311 return bnx2x_set_admin_app_up(bp, idtype, idval, up);
@@ -2318,13 +2327,13 @@ static u8 bnx2x_dcbnl_get_dcbx(struct net_device *netdev)
2318static u8 bnx2x_dcbnl_set_dcbx(struct net_device *netdev, u8 state) 2327static u8 bnx2x_dcbnl_set_dcbx(struct net_device *netdev, u8 state)
2319{ 2328{
2320 struct bnx2x *bp = netdev_priv(netdev); 2329 struct bnx2x *bp = netdev_priv(netdev);
2321 DP(NETIF_MSG_LINK, "state = %02x\n", state); 2330 DP(BNX2X_MSG_DCB, "state = %02x\n", state);
2322 2331
2323 /* set dcbx mode */ 2332 /* set dcbx mode */
2324 2333
2325 if ((state & BNX2X_DCBX_CAPS) != state) { 2334 if ((state & BNX2X_DCBX_CAPS) != state) {
2326 BNX2X_ERR("Requested DCBX mode %x is beyond advertised " 2335 BNX2X_ERR("Requested DCBX mode %x is beyond advertised capabilities\n",
2327 "capabilities\n", state); 2336 state);
2328 return 1; 2337 return 1;
2329 } 2338 }
2330 2339
@@ -2348,7 +2357,7 @@ static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
2348 struct bnx2x *bp = netdev_priv(netdev); 2357 struct bnx2x *bp = netdev_priv(netdev);
2349 u8 rval = 0; 2358 u8 rval = 0;
2350 2359
2351 DP(NETIF_MSG_LINK, "featid %d\n", featid); 2360 DP(BNX2X_MSG_DCB, "featid %d\n", featid);
2352 2361
2353 if (bp->dcb_state) { 2362 if (bp->dcb_state) {
2354 *flags = 0; 2363 *flags = 0;
@@ -2374,11 +2383,14 @@ static u8 bnx2x_dcbnl_get_featcfg(struct net_device *netdev, int featid,
2374 *flags |= DCB_FEATCFG_ERROR; 2383 *flags |= DCB_FEATCFG_ERROR;
2375 break; 2384 break;
2376 default: 2385 default:
2386 BNX2X_ERR("Non valid featrue-ID\n");
2377 rval = -EINVAL; 2387 rval = -EINVAL;
2378 break; 2388 break;
2379 } 2389 }
2380 } else 2390 } else {
2391 DP(BNX2X_MSG_DCB, "DCB disabled\n");
2381 rval = -EINVAL; 2392 rval = -EINVAL;
2393 }
2382 2394
2383 return rval; 2395 return rval;
2384} 2396}
@@ -2389,7 +2401,7 @@ static u8 bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
2389 struct bnx2x *bp = netdev_priv(netdev); 2401 struct bnx2x *bp = netdev_priv(netdev);
2390 u8 rval = 0; 2402 u8 rval = 0;
2391 2403
2392 DP(NETIF_MSG_LINK, "featid = %d flags = %02x\n", featid, flags); 2404 DP(BNX2X_MSG_DCB, "featid = %d flags = %02x\n", featid, flags);
2393 2405
2394 /* ignore the 'advertise' flag */ 2406 /* ignore the 'advertise' flag */
2395 if (bnx2x_dcbnl_set_valid(bp)) { 2407 if (bnx2x_dcbnl_set_valid(bp)) {
@@ -2412,11 +2424,14 @@ static u8 bnx2x_dcbnl_set_featcfg(struct net_device *netdev, int featid,
2412 flags & DCB_FEATCFG_WILLING ? 1 : 0; 2424 flags & DCB_FEATCFG_WILLING ? 1 : 0;
2413 break; 2425 break;
2414 default: 2426 default:
2427 BNX2X_ERR("Non valid featrue-ID\n");
2415 rval = -EINVAL; 2428 rval = -EINVAL;
2416 break; 2429 break;
2417 } 2430 }
2418 } else 2431 } else {
2432 DP(BNX2X_MSG_DCB, "dcbnl call not valid\n");
2419 rval = -EINVAL; 2433 rval = -EINVAL;
2434 }
2420 2435
2421 return rval; 2436 return rval;
2422} 2437}
@@ -2427,7 +2442,7 @@ static int bnx2x_peer_appinfo(struct net_device *netdev,
2427 int i; 2442 int i;
2428 struct bnx2x *bp = netdev_priv(netdev); 2443 struct bnx2x *bp = netdev_priv(netdev);
2429 2444
2430 DP(NETIF_MSG_LINK, "APP-INFO\n"); 2445 DP(BNX2X_MSG_DCB, "APP-INFO\n");
2431 2446
2432 info->willing = (bp->dcbx_remote_flags & DCBX_APP_REM_WILLING) ?: 0; 2447 info->willing = (bp->dcbx_remote_flags & DCBX_APP_REM_WILLING) ?: 0;
2433 info->error = (bp->dcbx_remote_flags & DCBX_APP_RX_ERROR) ?: 0; 2448 info->error = (bp->dcbx_remote_flags & DCBX_APP_RX_ERROR) ?: 0;
@@ -2446,7 +2461,7 @@ static int bnx2x_peer_apptable(struct net_device *netdev,
2446 int i, j; 2461 int i, j;
2447 struct bnx2x *bp = netdev_priv(netdev); 2462 struct bnx2x *bp = netdev_priv(netdev);
2448 2463
2449 DP(NETIF_MSG_LINK, "APP-TABLE\n"); 2464 DP(BNX2X_MSG_DCB, "APP-TABLE\n");
2450 2465
2451 for (i = 0, j = 0; i < DCBX_MAX_APP_PROTOCOL; i++) { 2466 for (i = 0, j = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
2452 struct dcbx_app_priority_entry *ent = 2467 struct dcbx_app_priority_entry *ent =
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index 858d1b5433de..3618a00a8144 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -280,7 +280,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
280 cmd->maxtxpkt = 0; 280 cmd->maxtxpkt = 0;
281 cmd->maxrxpkt = 0; 281 cmd->maxrxpkt = 0;
282 282
283 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 283 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
284 " supported 0x%x advertising 0x%x speed %u\n" 284 " supported 0x%x advertising 0x%x speed %u\n"
285 " duplex %d port %d phy_address %d transceiver %d\n" 285 " duplex %d port %d phy_address %d transceiver %d\n"
286 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 286 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
@@ -301,7 +301,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
301 if (IS_MF_SD(bp)) 301 if (IS_MF_SD(bp))
302 return 0; 302 return 0;
303 303
304 DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n" 304 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
305 " supported 0x%x advertising 0x%x speed %u\n" 305 " supported 0x%x advertising 0x%x speed %u\n"
306 " duplex %d port %d phy_address %d transceiver %d\n" 306 " duplex %d port %d phy_address %d transceiver %d\n"
307 " autoneg %d maxtxpkt %d maxrxpkt %d\n", 307 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
@@ -325,18 +325,17 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
325 line_speed = 10000; 325 line_speed = 10000;
326 326
327 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) { 327 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
328 BNX2X_DEV_INFO("To set speed BC %X or higher " 328 DP(BNX2X_MSG_ETHTOOL,
329 "is required, please upgrade BC\n", 329 "To set speed BC %X or higher is required, please upgrade BC\n",
330 REQ_BC_VER_4_SET_MF_BW); 330 REQ_BC_VER_4_SET_MF_BW);
331 return -EINVAL; 331 return -EINVAL;
332 } 332 }
333 333
334 part = (speed * 100) / line_speed; 334 part = (speed * 100) / line_speed;
335 335
336 if (line_speed < speed || !part) { 336 if (line_speed < speed || !part) {
337 BNX2X_DEV_INFO("Speed setting should be in a range " 337 DP(BNX2X_MSG_ETHTOOL,
338 "from 1%% to 100%% " 338 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
339 "of actual line speed\n");
340 return -EINVAL; 339 return -EINVAL;
341 } 340 }
342 341
@@ -358,7 +357,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
358 357
359 if (!(bp->port.supported[0] & SUPPORTED_TP || 358 if (!(bp->port.supported[0] & SUPPORTED_TP ||
360 bp->port.supported[1] & SUPPORTED_TP)) { 359 bp->port.supported[1] & SUPPORTED_TP)) {
361 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 360 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
362 return -EINVAL; 361 return -EINVAL;
363 } 362 }
364 bp->link_params.multi_phy_config &= 363 bp->link_params.multi_phy_config &=
@@ -378,7 +377,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
378 377
379 if (!(bp->port.supported[0] & SUPPORTED_FIBRE || 378 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
380 bp->port.supported[1] & SUPPORTED_FIBRE)) { 379 bp->port.supported[1] & SUPPORTED_FIBRE)) {
381 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 380 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
382 return -EINVAL; 381 return -EINVAL;
383 } 382 }
384 bp->link_params.multi_phy_config &= 383 bp->link_params.multi_phy_config &=
@@ -392,7 +391,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
392 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 391 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
393 break; 392 break;
394 default: 393 default:
395 DP(NETIF_MSG_LINK, "Unsupported port type\n"); 394 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
396 return -EINVAL; 395 return -EINVAL;
397 } 396 }
398 /* Save new config in case command complete successully */ 397 /* Save new config in case command complete successully */
@@ -401,7 +400,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
401 cfg_idx = bnx2x_get_link_cfg_idx(bp); 400 cfg_idx = bnx2x_get_link_cfg_idx(bp);
402 /* Restore old config in case command failed */ 401 /* Restore old config in case command failed */
403 bp->link_params.multi_phy_config = old_multi_phy_config; 402 bp->link_params.multi_phy_config = old_multi_phy_config;
404 DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx); 403 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
405 404
406 if (cmd->autoneg == AUTONEG_ENABLE) { 405 if (cmd->autoneg == AUTONEG_ENABLE) {
407 u32 an_supported_speed = bp->port.supported[cfg_idx]; 406 u32 an_supported_speed = bp->port.supported[cfg_idx];
@@ -410,14 +409,14 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
410 an_supported_speed |= (SUPPORTED_100baseT_Half | 409 an_supported_speed |= (SUPPORTED_100baseT_Half |
411 SUPPORTED_100baseT_Full); 410 SUPPORTED_100baseT_Full);
412 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 411 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
413 DP(NETIF_MSG_LINK, "Autoneg not supported\n"); 412 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
414 return -EINVAL; 413 return -EINVAL;
415 } 414 }
416 415
417 /* advertise the requested speed and duplex if supported */ 416 /* advertise the requested speed and duplex if supported */
418 if (cmd->advertising & ~an_supported_speed) { 417 if (cmd->advertising & ~an_supported_speed) {
419 DP(NETIF_MSG_LINK, "Advertisement parameters " 418 DP(BNX2X_MSG_ETHTOOL,
420 "are not supported\n"); 419 "Advertisement parameters are not supported\n");
421 return -EINVAL; 420 return -EINVAL;
422 } 421 }
423 422
@@ -466,7 +465,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
466 if (cmd->duplex == DUPLEX_FULL) { 465 if (cmd->duplex == DUPLEX_FULL) {
467 if (!(bp->port.supported[cfg_idx] & 466 if (!(bp->port.supported[cfg_idx] &
468 SUPPORTED_10baseT_Full)) { 467 SUPPORTED_10baseT_Full)) {
469 DP(NETIF_MSG_LINK, 468 DP(BNX2X_MSG_ETHTOOL,
470 "10M full not supported\n"); 469 "10M full not supported\n");
471 return -EINVAL; 470 return -EINVAL;
472 } 471 }
@@ -476,7 +475,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
476 } else { 475 } else {
477 if (!(bp->port.supported[cfg_idx] & 476 if (!(bp->port.supported[cfg_idx] &
478 SUPPORTED_10baseT_Half)) { 477 SUPPORTED_10baseT_Half)) {
479 DP(NETIF_MSG_LINK, 478 DP(BNX2X_MSG_ETHTOOL,
480 "10M half not supported\n"); 479 "10M half not supported\n");
481 return -EINVAL; 480 return -EINVAL;
482 } 481 }
@@ -490,7 +489,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
490 if (cmd->duplex == DUPLEX_FULL) { 489 if (cmd->duplex == DUPLEX_FULL) {
491 if (!(bp->port.supported[cfg_idx] & 490 if (!(bp->port.supported[cfg_idx] &
492 SUPPORTED_100baseT_Full)) { 491 SUPPORTED_100baseT_Full)) {
493 DP(NETIF_MSG_LINK, 492 DP(BNX2X_MSG_ETHTOOL,
494 "100M full not supported\n"); 493 "100M full not supported\n");
495 return -EINVAL; 494 return -EINVAL;
496 } 495 }
@@ -500,7 +499,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
500 } else { 499 } else {
501 if (!(bp->port.supported[cfg_idx] & 500 if (!(bp->port.supported[cfg_idx] &
502 SUPPORTED_100baseT_Half)) { 501 SUPPORTED_100baseT_Half)) {
503 DP(NETIF_MSG_LINK, 502 DP(BNX2X_MSG_ETHTOOL,
504 "100M half not supported\n"); 503 "100M half not supported\n");
505 return -EINVAL; 504 return -EINVAL;
506 } 505 }
@@ -512,13 +511,15 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
512 511
513 case SPEED_1000: 512 case SPEED_1000:
514 if (cmd->duplex != DUPLEX_FULL) { 513 if (cmd->duplex != DUPLEX_FULL) {
515 DP(NETIF_MSG_LINK, "1G half not supported\n"); 514 DP(BNX2X_MSG_ETHTOOL,
515 "1G half not supported\n");
516 return -EINVAL; 516 return -EINVAL;
517 } 517 }
518 518
519 if (!(bp->port.supported[cfg_idx] & 519 if (!(bp->port.supported[cfg_idx] &
520 SUPPORTED_1000baseT_Full)) { 520 SUPPORTED_1000baseT_Full)) {
521 DP(NETIF_MSG_LINK, "1G full not supported\n"); 521 DP(BNX2X_MSG_ETHTOOL,
522 "1G full not supported\n");
522 return -EINVAL; 523 return -EINVAL;
523 } 524 }
524 525
@@ -528,14 +529,14 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
528 529
529 case SPEED_2500: 530 case SPEED_2500:
530 if (cmd->duplex != DUPLEX_FULL) { 531 if (cmd->duplex != DUPLEX_FULL) {
531 DP(NETIF_MSG_LINK, 532 DP(BNX2X_MSG_ETHTOOL,
532 "2.5G half not supported\n"); 533 "2.5G half not supported\n");
533 return -EINVAL; 534 return -EINVAL;
534 } 535 }
535 536
536 if (!(bp->port.supported[cfg_idx] 537 if (!(bp->port.supported[cfg_idx]
537 & SUPPORTED_2500baseX_Full)) { 538 & SUPPORTED_2500baseX_Full)) {
538 DP(NETIF_MSG_LINK, 539 DP(BNX2X_MSG_ETHTOOL,
539 "2.5G full not supported\n"); 540 "2.5G full not supported\n");
540 return -EINVAL; 541 return -EINVAL;
541 } 542 }
@@ -546,13 +547,15 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
546 547
547 case SPEED_10000: 548 case SPEED_10000:
548 if (cmd->duplex != DUPLEX_FULL) { 549 if (cmd->duplex != DUPLEX_FULL) {
549 DP(NETIF_MSG_LINK, "10G half not supported\n"); 550 DP(BNX2X_MSG_ETHTOOL,
551 "10G half not supported\n");
550 return -EINVAL; 552 return -EINVAL;
551 } 553 }
552 554
553 if (!(bp->port.supported[cfg_idx] 555 if (!(bp->port.supported[cfg_idx]
554 & SUPPORTED_10000baseT_Full)) { 556 & SUPPORTED_10000baseT_Full)) {
555 DP(NETIF_MSG_LINK, "10G full not supported\n"); 557 DP(BNX2X_MSG_ETHTOOL,
558 "10G full not supported\n");
556 return -EINVAL; 559 return -EINVAL;
557 } 560 }
558 561
@@ -561,7 +564,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
561 break; 564 break;
562 565
563 default: 566 default:
564 DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed); 567 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
565 return -EINVAL; 568 return -EINVAL;
566 } 569 }
567 570
@@ -570,7 +573,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
570 bp->port.advertising[cfg_idx] = advertising; 573 bp->port.advertising[cfg_idx] = advertising;
571 } 574 }
572 575
573 DP(NETIF_MSG_LINK, "req_line_speed %d\n" 576 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
574 " req_duplex %d advertising 0x%x\n", 577 " req_duplex %d advertising 0x%x\n",
575 bp->link_params.req_line_speed[cfg_idx], 578 bp->link_params.req_line_speed[cfg_idx],
576 bp->link_params.req_duplex[cfg_idx], 579 bp->link_params.req_duplex[cfg_idx],
@@ -850,13 +853,16 @@ static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
850{ 853{
851 struct bnx2x *bp = netdev_priv(dev); 854 struct bnx2x *bp = netdev_priv(dev);
852 855
853 if (wol->wolopts & ~WAKE_MAGIC) 856 if (wol->wolopts & ~WAKE_MAGIC) {
857 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
854 return -EINVAL; 858 return -EINVAL;
859 }
855 860
856 if (wol->wolopts & WAKE_MAGIC) { 861 if (wol->wolopts & WAKE_MAGIC) {
857 if (bp->flags & NO_WOL_FLAG) 862 if (bp->flags & NO_WOL_FLAG) {
863 DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
858 return -EINVAL; 864 return -EINVAL;
859 865 }
860 bp->wol = 1; 866 bp->wol = 1;
861 } else 867 } else
862 bp->wol = 0; 868 bp->wol = 0;
@@ -955,7 +961,8 @@ static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
955 } 961 }
956 962
957 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 963 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
958 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n"); 964 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
965 "cannot get access to nvram interface\n");
959 return -EBUSY; 966 return -EBUSY;
960 } 967 }
961 968
@@ -986,7 +993,8 @@ static int bnx2x_release_nvram_lock(struct bnx2x *bp)
986 } 993 }
987 994
988 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 995 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
989 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n"); 996 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
997 "cannot free access to nvram interface\n");
990 return -EBUSY; 998 return -EBUSY;
991 } 999 }
992 1000
@@ -1060,7 +1068,9 @@ static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1060 break; 1068 break;
1061 } 1069 }
1062 } 1070 }
1063 1071 if (rc == -EBUSY)
1072 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1073 "nvram read timeout expired\n");
1064 return rc; 1074 return rc;
1065} 1075}
1066 1076
@@ -1072,15 +1082,15 @@ static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1072 __be32 val; 1082 __be32 val;
1073 1083
1074 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1084 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1075 DP(BNX2X_MSG_NVM, 1085 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1076 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1086 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1077 offset, buf_size); 1087 offset, buf_size);
1078 return -EINVAL; 1088 return -EINVAL;
1079 } 1089 }
1080 1090
1081 if (offset + buf_size > bp->common.flash_size) { 1091 if (offset + buf_size > bp->common.flash_size) {
1082 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1092 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1083 " buf_size (0x%x) > flash_size (0x%x)\n", 1093 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1084 offset, buf_size, bp->common.flash_size); 1094 offset, buf_size, bp->common.flash_size);
1085 return -EINVAL; 1095 return -EINVAL;
1086 } 1096 }
@@ -1125,10 +1135,13 @@ static int bnx2x_get_eeprom(struct net_device *dev,
1125 struct bnx2x *bp = netdev_priv(dev); 1135 struct bnx2x *bp = netdev_priv(dev);
1126 int rc; 1136 int rc;
1127 1137
1128 if (!netif_running(dev)) 1138 if (!netif_running(dev)) {
1139 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1140 "cannot access eeprom when the interface is down\n");
1129 return -EAGAIN; 1141 return -EAGAIN;
1142 }
1130 1143
1131 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1144 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1132 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1145 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1133 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1146 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1134 eeprom->len, eeprom->len); 1147 eeprom->len, eeprom->len);
@@ -1177,6 +1190,9 @@ static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1177 } 1190 }
1178 } 1191 }
1179 1192
1193 if (rc == -EBUSY)
1194 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1195 "nvram write timeout expired\n");
1180 return rc; 1196 return rc;
1181} 1197}
1182 1198
@@ -1191,8 +1207,8 @@ static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1191 __be32 val; 1207 __be32 val;
1192 1208
1193 if (offset + buf_size > bp->common.flash_size) { 1209 if (offset + buf_size > bp->common.flash_size) {
1194 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1210 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1195 " buf_size (0x%x) > flash_size (0x%x)\n", 1211 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1196 offset, buf_size, bp->common.flash_size); 1212 offset, buf_size, bp->common.flash_size);
1197 return -EINVAL; 1213 return -EINVAL;
1198 } 1214 }
@@ -1240,15 +1256,15 @@ static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1240 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size); 1256 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1241 1257
1242 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1258 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1243 DP(BNX2X_MSG_NVM, 1259 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1244 "Invalid parameter: offset 0x%x buf_size 0x%x\n", 1260 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1245 offset, buf_size); 1261 offset, buf_size);
1246 return -EINVAL; 1262 return -EINVAL;
1247 } 1263 }
1248 1264
1249 if (offset + buf_size > bp->common.flash_size) { 1265 if (offset + buf_size > bp->common.flash_size) {
1250 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +" 1266 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1251 " buf_size (0x%x) > flash_size (0x%x)\n", 1267 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1252 offset, buf_size, bp->common.flash_size); 1268 offset, buf_size, bp->common.flash_size);
1253 return -EINVAL; 1269 return -EINVAL;
1254 } 1270 }
@@ -1296,10 +1312,13 @@ static int bnx2x_set_eeprom(struct net_device *dev,
1296 int port = BP_PORT(bp); 1312 int port = BP_PORT(bp);
1297 int rc = 0; 1313 int rc = 0;
1298 u32 ext_phy_config; 1314 u32 ext_phy_config;
1299 if (!netif_running(dev)) 1315 if (!netif_running(dev)) {
1316 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1317 "cannot access eeprom when the interface is down\n");
1300 return -EAGAIN; 1318 return -EAGAIN;
1319 }
1301 1320
1302 DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n" 1321 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1303 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n", 1322 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1304 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset, 1323 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1305 eeprom->len, eeprom->len); 1324 eeprom->len, eeprom->len);
@@ -1308,8 +1327,11 @@ static int bnx2x_set_eeprom(struct net_device *dev,
1308 1327
1309 /* PHY eeprom can be accessed only by the PMF */ 1328 /* PHY eeprom can be accessed only by the PMF */
1310 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) && 1329 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1311 !bp->port.pmf) 1330 !bp->port.pmf) {
1331 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1332 "wrong magic or interface is not pmf\n");
1312 return -EINVAL; 1333 return -EINVAL;
1334 }
1313 1335
1314 ext_phy_config = 1336 ext_phy_config =
1315 SHMEM_RD(bp, 1337 SHMEM_RD(bp,
@@ -1421,8 +1443,8 @@ static int bnx2x_set_ringparam(struct net_device *dev,
1421 struct bnx2x *bp = netdev_priv(dev); 1443 struct bnx2x *bp = netdev_priv(dev);
1422 1444
1423 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 1445 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1424 netdev_err(dev, "Handling parity error recovery. " 1446 DP(BNX2X_MSG_ETHTOOL,
1425 "Try again later\n"); 1447 "Handling parity error recovery. Try again later\n");
1426 return -EAGAIN; 1448 return -EAGAIN;
1427 } 1449 }
1428 1450
@@ -1430,8 +1452,10 @@ static int bnx2x_set_ringparam(struct net_device *dev,
1430 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA : 1452 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1431 MIN_RX_SIZE_TPA)) || 1453 MIN_RX_SIZE_TPA)) ||
1432 (ering->tx_pending > MAX_TX_AVAIL) || 1454 (ering->tx_pending > MAX_TX_AVAIL) ||
1433 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) 1455 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1456 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1434 return -EINVAL; 1457 return -EINVAL;
1458 }
1435 1459
1436 bp->rx_ring_size = ering->rx_pending; 1460 bp->rx_ring_size = ering->rx_pending;
1437 bp->tx_ring_size = ering->tx_pending; 1461 bp->tx_ring_size = ering->tx_pending;
@@ -1459,7 +1483,7 @@ static void bnx2x_get_pauseparam(struct net_device *dev,
1459 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) == 1483 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1460 BNX2X_FLOW_CTRL_TX); 1484 BNX2X_FLOW_CTRL_TX);
1461 1485
1462 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1486 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1463 " autoneg %d rx_pause %d tx_pause %d\n", 1487 " autoneg %d rx_pause %d tx_pause %d\n",
1464 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1488 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1465} 1489}
@@ -1472,7 +1496,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
1472 if (IS_MF(bp)) 1496 if (IS_MF(bp))
1473 return 0; 1497 return 0;
1474 1498
1475 DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n" 1499 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1476 " autoneg %d rx_pause %d tx_pause %d\n", 1500 " autoneg %d rx_pause %d tx_pause %d\n",
1477 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause); 1501 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1478 1502
@@ -1489,7 +1513,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
1489 1513
1490 if (epause->autoneg) { 1514 if (epause->autoneg) {
1491 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) { 1515 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1492 DP(NETIF_MSG_LINK, "autoneg not supported\n"); 1516 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1493 return -EINVAL; 1517 return -EINVAL;
1494 } 1518 }
1495 1519
@@ -1499,7 +1523,7 @@ static int bnx2x_set_pauseparam(struct net_device *dev,
1499 } 1523 }
1500 } 1524 }
1501 1525
1502 DP(NETIF_MSG_LINK, 1526 DP(BNX2X_MSG_ETHTOOL,
1503 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]); 1527 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1504 1528
1505 if (netif_running(dev)) { 1529 if (netif_running(dev)) {
@@ -1631,8 +1655,11 @@ static int bnx2x_test_registers(struct bnx2x *bp)
1631 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 } 1655 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
1632 }; 1656 };
1633 1657
1634 if (!netif_running(bp->dev)) 1658 if (!netif_running(bp->dev)) {
1659 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1660 "cannot access eeprom when the interface is down\n");
1635 return rc; 1661 return rc;
1662 }
1636 1663
1637 if (CHIP_IS_E1(bp)) 1664 if (CHIP_IS_E1(bp))
1638 hw = BNX2X_CHIP_MASK_E1; 1665 hw = BNX2X_CHIP_MASK_E1;
@@ -1677,7 +1704,7 @@ static int bnx2x_test_registers(struct bnx2x *bp)
1677 1704
1678 /* verify value is as expected */ 1705 /* verify value is as expected */
1679 if ((val & mask) != (wr_val & mask)) { 1706 if ((val & mask) != (wr_val & mask)) {
1680 DP(NETIF_MSG_HW, 1707 DP(BNX2X_MSG_ETHTOOL,
1681 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n", 1708 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1682 offset, val, wr_val, mask); 1709 offset, val, wr_val, mask);
1683 goto test_reg_exit; 1710 goto test_reg_exit;
@@ -1731,8 +1758,11 @@ static int bnx2x_test_memory(struct bnx2x *bp)
1731 { NULL, 0xffffffff, {0, 0, 0, 0} } 1758 { NULL, 0xffffffff, {0, 0, 0, 0} }
1732 }; 1759 };
1733 1760
1734 if (!netif_running(bp->dev)) 1761 if (!netif_running(bp->dev)) {
1762 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1763 "cannot access eeprom when the interface is down\n");
1735 return rc; 1764 return rc;
1765 }
1736 1766
1737 if (CHIP_IS_E1(bp)) 1767 if (CHIP_IS_E1(bp))
1738 index = BNX2X_CHIP_E1_OFST; 1768 index = BNX2X_CHIP_E1_OFST;
@@ -1747,7 +1777,7 @@ static int bnx2x_test_memory(struct bnx2x *bp)
1747 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1777 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1748 val = REG_RD(bp, prty_tbl[i].offset); 1778 val = REG_RD(bp, prty_tbl[i].offset);
1749 if (val & ~(prty_tbl[i].hw_mask[index])) { 1779 if (val & ~(prty_tbl[i].hw_mask[index])) {
1750 DP(NETIF_MSG_HW, 1780 DP(BNX2X_MSG_ETHTOOL,
1751 "%s is 0x%x\n", prty_tbl[i].name, val); 1781 "%s is 0x%x\n", prty_tbl[i].name, val);
1752 goto test_mem_exit; 1782 goto test_mem_exit;
1753 } 1783 }
@@ -1762,7 +1792,7 @@ static int bnx2x_test_memory(struct bnx2x *bp)
1762 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) { 1792 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1763 val = REG_RD(bp, prty_tbl[i].offset); 1793 val = REG_RD(bp, prty_tbl[i].offset);
1764 if (val & ~(prty_tbl[i].hw_mask[index])) { 1794 if (val & ~(prty_tbl[i].hw_mask[index])) {
1765 DP(NETIF_MSG_HW, 1795 DP(BNX2X_MSG_ETHTOOL,
1766 "%s is 0x%x\n", prty_tbl[i].name, val); 1796 "%s is 0x%x\n", prty_tbl[i].name, val);
1767 goto test_mem_exit; 1797 goto test_mem_exit;
1768 } 1798 }
@@ -1783,7 +1813,7 @@ static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1783 msleep(20); 1813 msleep(20);
1784 1814
1785 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes)) 1815 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
1786 DP(NETIF_MSG_LINK, "Timeout waiting for link up\n"); 1816 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
1787 } 1817 }
1788} 1818}
1789 1819
@@ -1833,6 +1863,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1833 bnx2x_phy_init(&bp->link_params, &bp->link_vars); 1863 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1834 break; 1864 break;
1835 default: 1865 default:
1866 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1836 return -EINVAL; 1867 return -EINVAL;
1837 } 1868 }
1838 1869
@@ -1841,6 +1872,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1841 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN); 1872 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1842 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size); 1873 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1843 if (!skb) { 1874 if (!skb) {
1875 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
1844 rc = -ENOMEM; 1876 rc = -ENOMEM;
1845 goto test_loopback_exit; 1877 goto test_loopback_exit;
1846 } 1878 }
@@ -1855,7 +1887,7 @@ static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
1855 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 1887 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
1856 rc = -ENOMEM; 1888 rc = -ENOMEM;
1857 dev_kfree_skb(skb); 1889 dev_kfree_skb(skb);
1858 BNX2X_ERR("Unable to map SKB\n"); 1890 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
1859 goto test_loopback_exit; 1891 goto test_loopback_exit;
1860 } 1892 }
1861 1893
@@ -1985,13 +2017,13 @@ static int bnx2x_test_loopback(struct bnx2x *bp)
1985 2017
1986 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK); 2018 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
1987 if (res) { 2019 if (res) {
1988 DP(NETIF_MSG_PROBE, " PHY loopback failed (res %d)\n", res); 2020 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
1989 rc |= BNX2X_PHY_LOOPBACK_FAILED; 2021 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1990 } 2022 }
1991 2023
1992 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK); 2024 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
1993 if (res) { 2025 if (res) {
1994 DP(NETIF_MSG_PROBE, " MAC loopback failed (res %d)\n", res); 2026 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
1995 rc |= BNX2X_MAC_LOOPBACK_FAILED; 2027 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1996 } 2028 }
1997 2029
@@ -2027,7 +2059,7 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
2027 2059
2028 buf = kmalloc(0x350, GFP_KERNEL); 2060 buf = kmalloc(0x350, GFP_KERNEL);
2029 if (!buf) { 2061 if (!buf) {
2030 DP(NETIF_MSG_PROBE, "kmalloc failed\n"); 2062 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2031 rc = -ENOMEM; 2063 rc = -ENOMEM;
2032 goto test_nvram_exit; 2064 goto test_nvram_exit;
2033 } 2065 }
@@ -2035,13 +2067,15 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
2035 2067
2036 rc = bnx2x_nvram_read(bp, 0, data, 4); 2068 rc = bnx2x_nvram_read(bp, 0, data, 4);
2037 if (rc) { 2069 if (rc) {
2038 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc); 2070 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2071 "magic value read (rc %d)\n", rc);
2039 goto test_nvram_exit; 2072 goto test_nvram_exit;
2040 } 2073 }
2041 2074
2042 magic = be32_to_cpu(buf[0]); 2075 magic = be32_to_cpu(buf[0]);
2043 if (magic != 0x669955aa) { 2076 if (magic != 0x669955aa) {
2044 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic); 2077 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2078 "wrong magic value (0x%08x)\n", magic);
2045 rc = -ENODEV; 2079 rc = -ENODEV;
2046 goto test_nvram_exit; 2080 goto test_nvram_exit;
2047 } 2081 }
@@ -2051,15 +2085,15 @@ static int bnx2x_test_nvram(struct bnx2x *bp)
2051 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data, 2085 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
2052 nvram_tbl[i].size); 2086 nvram_tbl[i].size);
2053 if (rc) { 2087 if (rc) {
2054 DP(NETIF_MSG_PROBE, 2088 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2055 "nvram_tbl[%d] read data (rc %d)\n", i, rc); 2089 "nvram_tbl[%d] read data (rc %d)\n", i, rc);
2056 goto test_nvram_exit; 2090 goto test_nvram_exit;
2057 } 2091 }
2058 2092
2059 crc = ether_crc_le(nvram_tbl[i].size, data); 2093 crc = ether_crc_le(nvram_tbl[i].size, data);
2060 if (crc != CRC32_RESIDUAL) { 2094 if (crc != CRC32_RESIDUAL) {
2061 DP(NETIF_MSG_PROBE, 2095 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2062 "nvram_tbl[%d] crc value (0x%08x)\n", i, crc); 2096 "nvram_tbl[%d] wrong crc value (0x%08x)\n", i, crc);
2063 rc = -ENODEV; 2097 rc = -ENODEV;
2064 goto test_nvram_exit; 2098 goto test_nvram_exit;
2065 } 2099 }
@@ -2075,8 +2109,11 @@ static int bnx2x_test_intr(struct bnx2x *bp)
2075{ 2109{
2076 struct bnx2x_queue_state_params params = {0}; 2110 struct bnx2x_queue_state_params params = {0};
2077 2111
2078 if (!netif_running(bp->dev)) 2112 if (!netif_running(bp->dev)) {
2113 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2114 "cannot access eeprom when the interface is down\n");
2079 return -ENODEV; 2115 return -ENODEV;
2116 }
2080 2117
2081 params.q_obj = &bp->fp->q_obj; 2118 params.q_obj = &bp->fp->q_obj;
2082 params.cmd = BNX2X_Q_CMD_EMPTY; 2119 params.cmd = BNX2X_Q_CMD_EMPTY;
@@ -2092,8 +2129,8 @@ static void bnx2x_self_test(struct net_device *dev,
2092 struct bnx2x *bp = netdev_priv(dev); 2129 struct bnx2x *bp = netdev_priv(dev);
2093 u8 is_serdes; 2130 u8 is_serdes;
2094 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 2131 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2095 netdev_err(bp->dev, "Handling parity error recovery. " 2132 netdev_err(bp->dev,
2096 "Try again later\n"); 2133 "Handling parity error recovery. Try again later\n");
2097 etest->flags |= ETH_TEST_FL_FAILED; 2134 etest->flags |= ETH_TEST_FL_FAILED;
2098 return; 2135 return;
2099 } 2136 }
@@ -2306,11 +2343,16 @@ static int bnx2x_set_phys_id(struct net_device *dev,
2306{ 2343{
2307 struct bnx2x *bp = netdev_priv(dev); 2344 struct bnx2x *bp = netdev_priv(dev);
2308 2345
2309 if (!netif_running(dev)) 2346 if (!netif_running(dev)) {
2347 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2348 "cannot access eeprom when the interface is down\n");
2310 return -EAGAIN; 2349 return -EAGAIN;
2350 }
2311 2351
2312 if (!bp->port.pmf) 2352 if (!bp->port.pmf) {
2353 DP(BNX2X_MSG_ETHTOOL, "Interface is not pmf\n");
2313 return -EOPNOTSUPP; 2354 return -EOPNOTSUPP;
2355 }
2314 2356
2315 switch (state) { 2357 switch (state) {
2316 case ETHTOOL_ID_ACTIVE: 2358 case ETHTOOL_ID_ACTIVE:
@@ -2347,6 +2389,7 @@ static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2347 return 0; 2389 return 0;
2348 2390
2349 default: 2391 default:
2392 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2350 return -EOPNOTSUPP; 2393 return -EOPNOTSUPP;
2351 } 2394 }
2352} 2395}
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index a743a5fcb22c..5e5367aa5b4d 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -375,9 +375,6 @@ void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx); 375 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) { 376 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); 377 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
378
379 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
380 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
381 } 378 }
382 REG_WR(bp, dmae_reg_go_c[idx], 1); 379 REG_WR(bp, dmae_reg_go_c[idx], 1);
383} 380}
@@ -442,10 +439,6 @@ static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; 439 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
443 int rc = 0; 440 int rc = 0;
444 441
445 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
446 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
447 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
448
449 /* 442 /*
450 * Lock the dmae channel. Disable BHs to prevent a dead-lock 443 * Lock the dmae channel. Disable BHs to prevent a dead-lock
451 * as long as this code is called both from syscall context and 444 * as long as this code is called both from syscall context and
@@ -462,7 +455,6 @@ static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
462 /* wait for completion */ 455 /* wait for completion */
463 udelay(5); 456 udelay(5);
464 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 457 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
465 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
466 458
467 if (!cnt || 459 if (!cnt ||
468 (bp->recovery_state != BNX2X_RECOVERY_DONE && 460 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
@@ -479,10 +471,6 @@ static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
479 rc = DMAE_PCI_ERROR; 471 rc = DMAE_PCI_ERROR;
480 } 472 }
481 473
482 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
483 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
484 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
485
486unlock: 474unlock:
487 spin_unlock_bh(&bp->dmae_lock); 475 spin_unlock_bh(&bp->dmae_lock);
488 return rc; 476 return rc;
@@ -496,9 +484,6 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
496 if (!bp->dmae_ready) { 484 if (!bp->dmae_ready) {
497 u32 *data = bnx2x_sp(bp, wb_data[0]); 485 u32 *data = bnx2x_sp(bp, wb_data[0]);
498 486
499 DP(BNX2X_MSG_OFF,
500 "DMAE is not ready (dst_addr %08x len32 %d) using indirect\n",
501 dst_addr, len32);
502 if (CHIP_IS_E1(bp)) 487 if (CHIP_IS_E1(bp))
503 bnx2x_init_ind_wr(bp, dst_addr, data, len32); 488 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
504 else 489 else
@@ -530,13 +515,10 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
530 u32 *data = bnx2x_sp(bp, wb_data[0]); 515 u32 *data = bnx2x_sp(bp, wb_data[0]);
531 int i; 516 int i;
532 517
533 if (CHIP_IS_E1(bp)) { 518 if (CHIP_IS_E1(bp))
534 DP(BNX2X_MSG_OFF,
535 "DMAE is not ready (src_addr %08x len32 %d) using indirect\n",
536 src_addr, len32);
537 for (i = 0; i < len32; i++) 519 for (i = 0; i < len32; i++)
538 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); 520 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
539 } else 521 else
540 for (i = 0; i < len32; i++) 522 for (i = 0; i < len32; i++)
541 data[i] = REG_RD(bp, src_addr + i*4); 523 data[i] = REG_RD(bp, src_addr + i*4);
542 524
@@ -621,8 +603,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
621 XSTORM_ASSERT_LIST_OFFSET(i) + 12); 603 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
622 604
623 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 605 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
624 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x" 606 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
625 " 0x%08x 0x%08x 0x%08x\n",
626 i, row3, row2, row1, row0); 607 i, row3, row2, row1, row0);
627 rc++; 608 rc++;
628 } else { 609 } else {
@@ -649,8 +630,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
649 TSTORM_ASSERT_LIST_OFFSET(i) + 12); 630 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
650 631
651 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 632 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
652 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x" 633 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
653 " 0x%08x 0x%08x 0x%08x\n",
654 i, row3, row2, row1, row0); 634 i, row3, row2, row1, row0);
655 rc++; 635 rc++;
656 } else { 636 } else {
@@ -677,8 +657,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
677 CSTORM_ASSERT_LIST_OFFSET(i) + 12); 657 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
678 658
679 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 659 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
680 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x" 660 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
681 " 0x%08x 0x%08x 0x%08x\n",
682 i, row3, row2, row1, row0); 661 i, row3, row2, row1, row0);
683 rc++; 662 rc++;
684 } else { 663 } else {
@@ -705,8 +684,7 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
705 USTORM_ASSERT_LIST_OFFSET(i) + 12); 684 USTORM_ASSERT_LIST_OFFSET(i) + 12);
706 685
707 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 686 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
708 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x" 687 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
709 " 0x%08x 0x%08x 0x%08x\n",
710 i, row3, row2, row1, row0); 688 i, row3, row2, row1, row0);
711 rc++; 689 rc++;
712 } else { 690 } else {
@@ -735,7 +713,7 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
735 713
736 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); 714 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
737 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) 715 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
738 printk("%s" "MCP PC at 0x%x\n", lvl, val); 716 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
739 717
740 if (BP_PATH(bp) == 0) 718 if (BP_PATH(bp) == 0)
741 trace_shmem_base = bp->common.shmem_base; 719 trace_shmem_base = bp->common.shmem_base;
@@ -787,8 +765,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
787 765
788 /* Indices */ 766 /* Indices */
789 /* Common */ 767 /* Common */
790 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)" 768 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
791 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
792 bp->def_idx, bp->def_att_idx, bp->attn_state, 769 bp->def_idx, bp->def_att_idx, bp->attn_state,
793 bp->spq_prod_idx, bp->stats_counter); 770 bp->spq_prod_idx, bp->stats_counter);
794 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n", 771 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
@@ -835,14 +812,11 @@ void bnx2x_panic_dump(struct bnx2x *bp)
835 struct bnx2x_fp_txdata txdata; 812 struct bnx2x_fp_txdata txdata;
836 813
837 /* Rx */ 814 /* Rx */
838 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)" 815 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
839 " rx_comp_prod(0x%x)"
840 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
841 i, fp->rx_bd_prod, fp->rx_bd_cons, 816 i, fp->rx_bd_prod, fp->rx_bd_cons,
842 fp->rx_comp_prod, 817 fp->rx_comp_prod,
843 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb)); 818 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
844 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)" 819 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
845 " fp_hc_idx(0x%x)\n",
846 fp->rx_sge_prod, fp->last_max_sge, 820 fp->rx_sge_prod, fp->last_max_sge,
847 le16_to_cpu(fp->fp_hc_idx)); 821 le16_to_cpu(fp->fp_hc_idx));
848 822
@@ -850,9 +824,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
850 for_each_cos_in_tx_queue(fp, cos) 824 for_each_cos_in_tx_queue(fp, cos)
851 { 825 {
852 txdata = fp->txdata[cos]; 826 txdata = fp->txdata[cos];
853 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)" 827 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
854 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
855 " *tx_cons_sb(0x%x)\n",
856 i, txdata.tx_pkt_prod, 828 i, txdata.tx_pkt_prod,
857 txdata.tx_pkt_cons, txdata.tx_bd_prod, 829 txdata.tx_pkt_cons, txdata.tx_bd_prod,
858 txdata.tx_bd_cons, 830 txdata.tx_bd_cons,
@@ -894,9 +866,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
894 j * sizeof(u32)); 866 j * sizeof(u32));
895 867
896 if (!CHIP_IS_E1x(bp)) { 868 if (!CHIP_IS_E1x(bp)) {
897 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 869 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
898 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
899 "state(0x%x)\n",
900 sb_data_e2.common.p_func.pf_id, 870 sb_data_e2.common.p_func.pf_id,
901 sb_data_e2.common.p_func.vf_id, 871 sb_data_e2.common.p_func.vf_id,
902 sb_data_e2.common.p_func.vf_valid, 872 sb_data_e2.common.p_func.vf_valid,
@@ -904,9 +874,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
904 sb_data_e2.common.same_igu_sb_1b, 874 sb_data_e2.common.same_igu_sb_1b,
905 sb_data_e2.common.state); 875 sb_data_e2.common.state);
906 } else { 876 } else {
907 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) " 877 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
908 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
909 "state(0x%x)\n",
910 sb_data_e1x.common.p_func.pf_id, 878 sb_data_e1x.common.p_func.pf_id,
911 sb_data_e1x.common.p_func.vf_id, 879 sb_data_e1x.common.p_func.vf_id,
912 sb_data_e1x.common.p_func.vf_valid, 880 sb_data_e1x.common.p_func.vf_valid,
@@ -917,21 +885,17 @@ void bnx2x_panic_dump(struct bnx2x *bp)
917 885
918 /* SB_SMs data */ 886 /* SB_SMs data */
919 for (j = 0; j < HC_SB_MAX_SM; j++) { 887 for (j = 0; j < HC_SB_MAX_SM; j++) {
920 pr_cont("SM[%d] __flags (0x%x) " 888 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
921 "igu_sb_id (0x%x) igu_seg_id(0x%x) " 889 j, hc_sm_p[j].__flags,
922 "time_to_expire (0x%x) " 890 hc_sm_p[j].igu_sb_id,
923 "timer_value(0x%x)\n", j, 891 hc_sm_p[j].igu_seg_id,
924 hc_sm_p[j].__flags, 892 hc_sm_p[j].time_to_expire,
925 hc_sm_p[j].igu_sb_id, 893 hc_sm_p[j].timer_value);
926 hc_sm_p[j].igu_seg_id,
927 hc_sm_p[j].time_to_expire,
928 hc_sm_p[j].timer_value);
929 } 894 }
930 895
931 /* Indecies data */ 896 /* Indecies data */
932 for (j = 0; j < loop; j++) { 897 for (j = 0; j < loop; j++) {
933 pr_cont("INDEX[%d] flags (0x%x) " 898 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
934 "timeout (0x%x)\n", j,
935 hc_index_p[j].flags, 899 hc_index_p[j].flags,
936 hc_index_p[j].timeout); 900 hc_index_p[j].timeout);
937 } 901 }
@@ -985,8 +949,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
985 struct sw_tx_bd *sw_bd = 949 struct sw_tx_bd *sw_bd =
986 &txdata->tx_buf_ring[j]; 950 &txdata->tx_buf_ring[j];
987 951
988 BNX2X_ERR("fp%d: txdata %d, " 952 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
989 "packet[%x]=[%p,%x]\n",
990 i, cos, j, sw_bd->skb, 953 i, cos, j, sw_bd->skb,
991 sw_bd->first_bd); 954 sw_bd->first_bd);
992 } 955 }
@@ -996,8 +959,7 @@ void bnx2x_panic_dump(struct bnx2x *bp)
996 for (j = start; j != end; j = TX_BD(j + 1)) { 959 for (j = start; j != end; j = TX_BD(j + 1)) {
997 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j]; 960 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
998 961
999 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=" 962 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1000 "[%x:%x:%x:%x]\n",
1001 i, cos, j, tx_bd[0], tx_bd[1], 963 i, cos, j, tx_bd[0], tx_bd[1],
1002 tx_bd[2], tx_bd[3]); 964 tx_bd[2], tx_bd[3]);
1003 } 965 }
@@ -1233,6 +1195,8 @@ static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1233 1195
1234 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { 1196 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1235 BNX2X_ERR("FW final cleanup did not succeed\n"); 1197 BNX2X_ERR("FW final cleanup did not succeed\n");
1198 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1199 (REG_RD(bp, comp_addr)));
1236 ret = 1; 1200 ret = 1;
1237 } 1201 }
1238 /* Zero completion for nxt FLR */ 1202 /* Zero completion for nxt FLR */
@@ -1402,8 +1366,8 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp)
1402 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1366 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1403 1367
1404 if (!CHIP_IS_E1(bp)) { 1368 if (!CHIP_IS_E1(bp)) {
1405 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1369 DP(NETIF_MSG_IFUP,
1406 val, port, addr); 1370 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1407 1371
1408 REG_WR(bp, addr, val); 1372 REG_WR(bp, addr, val);
1409 1373
@@ -1414,8 +1378,9 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp)
1414 if (CHIP_IS_E1(bp)) 1378 if (CHIP_IS_E1(bp))
1415 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); 1379 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1416 1380
1417 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 1381 DP(NETIF_MSG_IFUP,
1418 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1382 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1383 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1419 1384
1420 REG_WR(bp, addr, val); 1385 REG_WR(bp, addr, val);
1421 /* 1386 /*
@@ -1470,7 +1435,7 @@ static void bnx2x_igu_int_enable(struct bnx2x *bp)
1470 IGU_PF_CONF_SINGLE_ISR_EN); 1435 IGU_PF_CONF_SINGLE_ISR_EN);
1471 } 1436 }
1472 1437
1473 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n", 1438 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1474 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx"))); 1439 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1475 1440
1476 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); 1441 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
@@ -1528,7 +1493,8 @@ static void bnx2x_hc_int_disable(struct bnx2x *bp)
1528 HC_CONFIG_0_REG_INT_LINE_EN_0 | 1493 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1529 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1530 1495
1531 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n", 1496 DP(NETIF_MSG_IFDOWN,
1497 "write %x to HC %d (addr 0x%x)\n",
1532 val, port, addr); 1498 val, port, addr);
1533 1499
1534 /* flush all outstanding writes */ 1500 /* flush all outstanding writes */
@@ -1547,7 +1513,7 @@ static void bnx2x_igu_int_disable(struct bnx2x *bp)
1547 IGU_PF_CONF_INT_LINE_EN | 1513 IGU_PF_CONF_INT_LINE_EN |
1548 IGU_PF_CONF_ATTN_BIT_EN); 1514 IGU_PF_CONF_ATTN_BIT_EN);
1549 1515
1550 DP(NETIF_MSG_INTR, "write %x to IGU\n", val); 1516 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1551 1517
1552 /* flush all outstanding writes */ 1518 /* flush all outstanding writes */
1553 mmiowb(); 1519 mmiowb();
@@ -1606,11 +1572,12 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1606 int func = BP_FUNC(bp); 1572 int func = BP_FUNC(bp);
1607 u32 hw_lock_control_reg; 1573 u32 hw_lock_control_reg;
1608 1574
1609 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource); 1575 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1576 "Trying to take a lock on resource %d\n", resource);
1610 1577
1611 /* Validating that the resource is within range */ 1578 /* Validating that the resource is within range */
1612 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1579 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1613 DP(NETIF_MSG_HW, 1580 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1614 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 1581 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1615 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1582 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1616 return false; 1583 return false;
@@ -1628,7 +1595,8 @@ static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1628 if (lock_status & resource_bit) 1595 if (lock_status & resource_bit)
1629 return true; 1596 return true;
1630 1597
1631 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource); 1598 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1599 "Failed to get a lock on resource %d\n", resource);
1632 return false; 1600 return false;
1633} 1601}
1634 1602
@@ -1689,7 +1657,7 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1689 break; 1657 break;
1690 1658
1691 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 1659 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1692 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid); 1660 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1693 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY; 1661 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1694 break; 1662 break;
1695 1663
@@ -1831,8 +1799,7 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1831 1799
1832 /* Validating that the resource is within range */ 1800 /* Validating that the resource is within range */
1833 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1801 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1834 DP(NETIF_MSG_HW, 1802 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1835 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1836 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1803 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1837 return -EINVAL; 1804 return -EINVAL;
1838 } 1805 }
@@ -1847,7 +1814,7 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1847 /* Validating that the resource is not already taken */ 1814 /* Validating that the resource is not already taken */
1848 lock_status = REG_RD(bp, hw_lock_control_reg); 1815 lock_status = REG_RD(bp, hw_lock_control_reg);
1849 if (lock_status & resource_bit) { 1816 if (lock_status & resource_bit) {
1850 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1817 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1851 lock_status, resource_bit); 1818 lock_status, resource_bit);
1852 return -EEXIST; 1819 return -EEXIST;
1853 } 1820 }
@@ -1862,7 +1829,7 @@ int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1862 1829
1863 msleep(5); 1830 msleep(5);
1864 } 1831 }
1865 DP(NETIF_MSG_HW, "Timeout\n"); 1832 BNX2X_ERR("Timeout\n");
1866 return -EAGAIN; 1833 return -EAGAIN;
1867} 1834}
1868 1835
@@ -1878,12 +1845,9 @@ int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1878 int func = BP_FUNC(bp); 1845 int func = BP_FUNC(bp);
1879 u32 hw_lock_control_reg; 1846 u32 hw_lock_control_reg;
1880 1847
1881 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1882
1883 /* Validating that the resource is within range */ 1848 /* Validating that the resource is within range */
1884 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1849 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1885 DP(NETIF_MSG_HW, 1850 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1886 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1887 resource, HW_LOCK_MAX_RESOURCE_VALUE); 1851 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1888 return -EINVAL; 1852 return -EINVAL;
1889 } 1853 }
@@ -1898,7 +1862,7 @@ int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1898 /* Validating that the resource is currently taken */ 1862 /* Validating that the resource is currently taken */
1899 lock_status = REG_RD(bp, hw_lock_control_reg); 1863 lock_status = REG_RD(bp, hw_lock_control_reg);
1900 if (!(lock_status & resource_bit)) { 1864 if (!(lock_status & resource_bit)) {
1901 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n", 1865 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1902 lock_status, resource_bit); 1866 lock_status, resource_bit);
1903 return -EFAULT; 1867 return -EFAULT;
1904 } 1868 }
@@ -1959,7 +1923,8 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1959 1923
1960 switch (mode) { 1924 switch (mode) {
1961 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1925 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n", 1926 DP(NETIF_MSG_LINK,
1927 "Set GPIO %d (shift %d) -> output low\n",
1963 gpio_num, gpio_shift); 1928 gpio_num, gpio_shift);
1964 /* clear FLOAT and set CLR */ 1929 /* clear FLOAT and set CLR */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1930 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
@@ -1967,7 +1932,8 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1967 break; 1932 break;
1968 1933
1969 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1934 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n", 1935 DP(NETIF_MSG_LINK,
1936 "Set GPIO %d (shift %d) -> output high\n",
1971 gpio_num, gpio_shift); 1937 gpio_num, gpio_shift);
1972 /* clear FLOAT and set SET */ 1938 /* clear FLOAT and set SET */
1973 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1939 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
@@ -1975,7 +1941,8 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1975 break; 1941 break;
1976 1942
1977 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1943 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1978 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n", 1944 DP(NETIF_MSG_LINK,
1945 "Set GPIO %d (shift %d) -> input\n",
1979 gpio_num, gpio_shift); 1946 gpio_num, gpio_shift);
1980 /* set FLOAT */ 1947 /* set FLOAT */
1981 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1948 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
@@ -2059,16 +2026,18 @@ int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2059 2026
2060 switch (mode) { 2027 switch (mode) {
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2028 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2062 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> " 2029 DP(NETIF_MSG_LINK,
2063 "output low\n", gpio_num, gpio_shift); 2030 "Clear GPIO INT %d (shift %d) -> output low\n",
2031 gpio_num, gpio_shift);
2064 /* clear SET and set CLR */ 2032 /* clear SET and set CLR */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2033 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2034 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2067 break; 2035 break;
2068 2036
2069 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2037 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2070 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> " 2038 DP(NETIF_MSG_LINK,
2071 "output high\n", gpio_num, gpio_shift); 2039 "Set GPIO INT %d (shift %d) -> output high\n",
2040 gpio_num, gpio_shift);
2072 /* clear CLR and set SET */ 2041 /* clear CLR and set SET */
2073 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2042 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2074 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2043 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
@@ -2101,21 +2070,21 @@ static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2101 2070
2102 switch (mode) { 2071 switch (mode) {
2103 case MISC_REGISTERS_SPIO_OUTPUT_LOW: 2072 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2104 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num); 2073 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2105 /* clear FLOAT and set CLR */ 2074 /* clear FLOAT and set CLR */
2106 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2075 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2107 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS); 2076 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2108 break; 2077 break;
2109 2078
2110 case MISC_REGISTERS_SPIO_OUTPUT_HIGH: 2079 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2111 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num); 2080 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2112 /* clear FLOAT and set SET */ 2081 /* clear FLOAT and set SET */
2113 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2082 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2114 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS); 2083 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2115 break; 2084 break;
2116 2085
2117 case MISC_REGISTERS_SPIO_INPUT_HI_Z: 2086 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2118 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num); 2087 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2119 /* set FLOAT */ 2088 /* set FLOAT */
2120 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS); 2089 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2121 break; 2090 break;
@@ -2557,7 +2526,7 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
2557 u32 val; 2526 u32 val;
2558 2527
2559 bp->port.pmf = 1; 2528 bp->port.pmf = 1;
2560 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf); 2529 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2561 2530
2562 /* 2531 /*
2563 * We need the mb() to ensure the ordering between the writing to 2532 * We need the mb() to ensure the ordering between the writing to
@@ -3138,12 +3107,12 @@ static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3138 * locks 3107 * locks
3139 */ 3108 */
3140 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { 3109 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3141 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n"); 3110 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3142 bp->flags |= MF_FUNC_DIS; 3111 bp->flags |= MF_FUNC_DIS;
3143 3112
3144 bnx2x_e1h_disable(bp); 3113 bnx2x_e1h_disable(bp);
3145 } else { 3114 } else {
3146 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n"); 3115 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3147 bp->flags &= ~MF_FUNC_DIS; 3116 bp->flags &= ~MF_FUNC_DIS;
3148 3117
3149 bnx2x_e1h_enable(bp); 3118 bnx2x_e1h_enable(bp);
@@ -3170,7 +3139,7 @@ static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3170 if (bp->spq_prod_bd == bp->spq_last_bd) { 3139 if (bp->spq_prod_bd == bp->spq_last_bd) {
3171 bp->spq_prod_bd = bp->spq; 3140 bp->spq_prod_bd = bp->spq;
3172 bp->spq_prod_idx = 0; 3141 bp->spq_prod_idx = 0;
3173 DP(NETIF_MSG_TIMER, "end of spq\n"); 3142 DP(BNX2X_MSG_SP, "end of spq\n");
3174 } else { 3143 } else {
3175 bp->spq_prod_bd++; 3144 bp->spq_prod_bd++;
3176 bp->spq_prod_idx++; 3145 bp->spq_prod_idx++;
@@ -3239,8 +3208,10 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3239 bool common = bnx2x_is_contextless_ramrod(command, cmd_type); 3208 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3240 3209
3241#ifdef BNX2X_STOP_ON_ERROR 3210#ifdef BNX2X_STOP_ON_ERROR
3242 if (unlikely(bp->panic)) 3211 if (unlikely(bp->panic)) {
3212 BNX2X_ERR("Can't post SP when there is panic\n");
3243 return -EIO; 3213 return -EIO;
3214 }
3244#endif 3215#endif
3245 3216
3246 spin_lock_bh(&bp->spq_lock); 3217 spin_lock_bh(&bp->spq_lock);
@@ -3287,9 +3258,8 @@ int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3287 atomic_dec(&bp->cq_spq_left); 3258 atomic_dec(&bp->cq_spq_left);
3288 3259
3289 3260
3290 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/, 3261 DP(BNX2X_MSG_SP,
3291 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) " 3262 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3292 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3293 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), 3263 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3294 (u32)(U64_LO(bp->spq_mapping) + 3264 (u32)(U64_LO(bp->spq_mapping) +
3295 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, 3265 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
@@ -3481,9 +3451,8 @@ static inline void bnx2x_fan_failure(struct bnx2x *bp)
3481 ext_phy_config); 3451 ext_phy_config);
3482 3452
3483 /* log the failure */ 3453 /* log the failure */
3484 netdev_err(bp->dev, "Fan Failure on Network Controller has caused" 3454 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3485 " the driver to shutdown the card to prevent permanent" 3455 "Please contact OEM Support for assistance\n");
3486 " damage. Please contact OEM Support for assistance\n");
3487 3456
3488 /* 3457 /*
3489 * Scheudle device reset (unload) 3458 * Scheudle device reset (unload)
@@ -3829,7 +3798,7 @@ void bnx2x_set_pf_load(struct bnx2x *bp)
3829 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3798 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3830 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3799 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3831 3800
3832 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3801 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3833 3802
3834 /* get the current counter value */ 3803 /* get the current counter value */
3835 val1 = (val & mask) >> shift; 3804 val1 = (val & mask) >> shift;
@@ -3866,7 +3835,7 @@ bool bnx2x_clear_pf_load(struct bnx2x *bp)
3866 3835
3867 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); 3836 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3868 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3837 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3869 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val); 3838 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
3870 3839
3871 /* get the current counter value */ 3840 /* get the current counter value */
3872 val1 = (val & mask) >> shift; 3841 val1 = (val & mask) >> shift;
@@ -3898,11 +3867,12 @@ static inline bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
3898 BNX2X_PATH0_LOAD_CNT_SHIFT); 3867 BNX2X_PATH0_LOAD_CNT_SHIFT);
3899 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); 3868 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3900 3869
3901 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val); 3870 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
3902 3871
3903 val = (val & mask) >> shift; 3872 val = (val & mask) >> shift;
3904 3873
3905 DP(NETIF_MSG_HW, "load mask for engine %d = 0x%x\n", engine, val); 3874 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
3875 engine, val);
3906 3876
3907 return val != 0; 3877 return val != 0;
3908} 3878}
@@ -4190,9 +4160,8 @@ static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4190 (sig[3] & HW_PRTY_ASSERT_SET_3) || 4160 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4191 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 4161 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4192 int par_num = 0; 4162 int par_num = 0;
4193 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: " 4163 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4194 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x " 4164 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4195 "[4]:0x%08x\n",
4196 sig[0] & HW_PRTY_ASSERT_SET_0, 4165 sig[0] & HW_PRTY_ASSERT_SET_0,
4197 sig[1] & HW_PRTY_ASSERT_SET_1, 4166 sig[1] & HW_PRTY_ASSERT_SET_1,
4198 sig[2] & HW_PRTY_ASSERT_SET_2, 4167 sig[2] & HW_PRTY_ASSERT_SET_2,
@@ -4262,34 +4231,25 @@ static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4262 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 4231 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4263 BNX2X_ERR("PGLUE hw attention 0x%x\n", val); 4232 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4264 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 4233 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4265 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4234 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4266 "ADDRESS_ERROR\n");
4267 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 4235 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4268 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4236 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4269 "INCORRECT_RCV_BEHAVIOR\n");
4270 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 4237 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4271 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4238 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4272 "WAS_ERROR_ATTN\n");
4273 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 4239 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4274 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4240 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4275 "VF_LENGTH_VIOLATION_ATTN\n");
4276 if (val & 4241 if (val &
4277 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 4242 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4278 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4243 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4279 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4280 if (val & 4244 if (val &
4281 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 4245 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4282 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4246 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4283 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4284 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 4247 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4285 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4248 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4286 "TCPL_ERROR_ATTN\n");
4287 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 4249 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4288 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4250 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4289 "TCPL_IN_TWO_RCBS_ATTN\n");
4290 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 4251 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4291 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_" 4252 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4292 "CSSNOOP_FIFO_OVERFLOW\n");
4293 } 4253 }
4294 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 4254 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4295 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); 4255 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
@@ -4297,19 +4257,15 @@ static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4297 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 4257 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4298 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 4258 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4299 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 4259 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4300 BNX2X_ERR("ATC_ATC_INT_STS_REG" 4260 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4301 "_ATC_TCPL_TO_NOT_PEND\n");
4302 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 4261 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4303 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4262 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4304 "ATC_GPA_MULTIPLE_HITS\n");
4305 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 4263 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4306 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4264 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4307 "ATC_RCPL_TO_EMPTY_CNT\n");
4308 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 4265 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4309 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 4266 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4310 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 4267 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4311 BNX2X_ERR("ATC_ATC_INT_STS_REG_" 4268 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4312 "ATC_IREQ_LESS_THAN_STU\n");
4313 } 4269 }
4314 4270
4315 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 4271 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
@@ -4368,8 +4324,7 @@ static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4368 if (deasserted & (1 << index)) { 4324 if (deasserted & (1 << index)) {
4369 group_mask = &bp->attn_group[index]; 4325 group_mask = &bp->attn_group[index];
4370 4326
4371 DP(NETIF_MSG_HW, "group[%d]: %08x %08x " 4327 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4372 "%08x %08x %08x\n",
4373 index, 4328 index,
4374 group_mask->sig[0], group_mask->sig[1], 4329 group_mask->sig[0], group_mask->sig[1],
4375 group_mask->sig[2], group_mask->sig[3], 4330 group_mask->sig[2], group_mask->sig[3],
@@ -4529,6 +4484,7 @@ static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4529 4484
4530 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) { 4485 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4531 case BNX2X_FILTER_MAC_PENDING: 4486 case BNX2X_FILTER_MAC_PENDING:
4487 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4532#ifdef BCM_CNIC 4488#ifdef BCM_CNIC
4533 if (cid == BNX2X_ISCSI_ETH_CID) 4489 if (cid == BNX2X_ISCSI_ETH_CID)
4534 vlan_mac_obj = &bp->iscsi_l2_mac_obj; 4490 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
@@ -4538,6 +4494,7 @@ static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4538 4494
4539 break; 4495 break;
4540 case BNX2X_FILTER_MCAST_PENDING: 4496 case BNX2X_FILTER_MCAST_PENDING:
4497 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4541 /* This is only relevant for 57710 where multicast MACs are 4498 /* This is only relevant for 57710 where multicast MACs are
4542 * configured as unicast MACs using the same ramrod. 4499 * configured as unicast MACs using the same ramrod.
4543 */ 4500 */
@@ -4639,7 +4596,8 @@ static void bnx2x_eq_int(struct bnx2x *bp)
4639 /* handle eq element */ 4596 /* handle eq element */
4640 switch (opcode) { 4597 switch (opcode) {
4641 case EVENT_RING_OPCODE_STAT_QUERY: 4598 case EVENT_RING_OPCODE_STAT_QUERY:
4642 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n", 4599 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4600 "got statistics comp event %d\n",
4643 bp->stats_comp++); 4601 bp->stats_comp++);
4644 /* nothing to do with stats comp */ 4602 /* nothing to do with stats comp */
4645 goto next_spqe; 4603 goto next_spqe;
@@ -4666,7 +4624,7 @@ static void bnx2x_eq_int(struct bnx2x *bp)
4666 goto next_spqe; 4624 goto next_spqe;
4667 4625
4668 case EVENT_RING_OPCODE_STOP_TRAFFIC: 4626 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4669 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n"); 4627 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4670 if (f_obj->complete_cmd(bp, f_obj, 4628 if (f_obj->complete_cmd(bp, f_obj,
4671 BNX2X_F_CMD_TX_STOP)) 4629 BNX2X_F_CMD_TX_STOP))
4672 break; 4630 break;
@@ -4674,21 +4632,23 @@ static void bnx2x_eq_int(struct bnx2x *bp)
4674 goto next_spqe; 4632 goto next_spqe;
4675 4633
4676 case EVENT_RING_OPCODE_START_TRAFFIC: 4634 case EVENT_RING_OPCODE_START_TRAFFIC:
4677 DP(BNX2X_MSG_SP, "got START TRAFFIC\n"); 4635 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4678 if (f_obj->complete_cmd(bp, f_obj, 4636 if (f_obj->complete_cmd(bp, f_obj,
4679 BNX2X_F_CMD_TX_START)) 4637 BNX2X_F_CMD_TX_START))
4680 break; 4638 break;
4681 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); 4639 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4682 goto next_spqe; 4640 goto next_spqe;
4683 case EVENT_RING_OPCODE_FUNCTION_START: 4641 case EVENT_RING_OPCODE_FUNCTION_START:
4684 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n"); 4642 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4643 "got FUNC_START ramrod\n");
4685 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) 4644 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4686 break; 4645 break;
4687 4646
4688 goto next_spqe; 4647 goto next_spqe;
4689 4648
4690 case EVENT_RING_OPCODE_FUNCTION_STOP: 4649 case EVENT_RING_OPCODE_FUNCTION_STOP:
4691 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n"); 4650 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4651 "got FUNC_STOP ramrod\n");
4692 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) 4652 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4693 break; 4653 break;
4694 4654
@@ -4770,7 +4730,7 @@ static void bnx2x_sp_task(struct work_struct *work)
4770/* if (status == 0) */ 4730/* if (status == 0) */
4771/* BNX2X_ERR("spurious slowpath interrupt!\n"); */ 4731/* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4772 4732
4773 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status); 4733 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4774 4734
4775 /* HW attentions */ 4735 /* HW attentions */
4776 if (status & BNX2X_DEF_SB_ATT_IDX) { 4736 if (status & BNX2X_DEF_SB_ATT_IDX) {
@@ -4804,7 +4764,7 @@ static void bnx2x_sp_task(struct work_struct *work)
4804 } 4764 }
4805 4765
4806 if (unlikely(status)) 4766 if (unlikely(status))
4807 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n", 4767 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
4808 status); 4768 status);
4809 4769
4810 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, 4770 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
@@ -5082,7 +5042,7 @@ static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5082 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], 5042 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5083 igu_sb_id, igu_seg_id); 5043 igu_sb_id, igu_seg_id);
5084 5044
5085 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id); 5045 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5086 5046
5087 /* write indecies to HW */ 5047 /* write indecies to HW */
5088 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); 5048 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
@@ -5460,8 +5420,7 @@ static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5460 */ 5420 */
5461 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX); 5421 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5462 5422
5463 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) " 5423 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5464 "cl_id %d fw_sb %d igu_sb %d\n",
5465 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 5424 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5466 fp->igu_sb_id); 5425 fp->igu_sb_id);
5467 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, 5426 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
@@ -5548,8 +5507,7 @@ gunzip_nomem2:
5548 bp->gunzip_buf = NULL; 5507 bp->gunzip_buf = NULL;
5549 5508
5550gunzip_nomem1: 5509gunzip_nomem1:
5551 netdev_err(bp->dev, "Cannot allocate firmware buffer for" 5510 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5552 " un-compression\n");
5553 return -ENOMEM; 5511 return -ENOMEM;
5554} 5512}
5555 5513
@@ -5601,8 +5559,8 @@ static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5601 5559
5602 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); 5560 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5603 if (bp->gunzip_outlen & 0x3) 5561 if (bp->gunzip_outlen & 0x3)
5604 netdev_err(bp->dev, "Firmware decompression error:" 5562 netdev_err(bp->dev,
5605 " gunzip_outlen (%d) not aligned\n", 5563 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5606 bp->gunzip_outlen); 5564 bp->gunzip_outlen);
5607 bp->gunzip_outlen >>= 2; 5565 bp->gunzip_outlen >>= 2;
5608 5566
@@ -6021,7 +5979,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
6021{ 5979{
6022 u32 val; 5980 u32 val;
6023 5981
6024 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp)); 5982 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6025 5983
6026 /* 5984 /*
6027 * take the UNDI lock to protect undi_unload flow from accessing 5985 * take the UNDI lock to protect undi_unload flow from accessing
@@ -6345,9 +6303,9 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
6345 6303
6346 if (sizeof(union cdu_context) != 1024) 6304 if (sizeof(union cdu_context) != 1024)
6347 /* we currently assume that a context is 1024 bytes */ 6305 /* we currently assume that a context is 1024 bytes */
6348 dev_alert(&bp->pdev->dev, "please adjust the size " 6306 dev_alert(&bp->pdev->dev,
6349 "of cdu_context(%ld)\n", 6307 "please adjust the size of cdu_context(%ld)\n",
6350 (long)sizeof(union cdu_context)); 6308 (long)sizeof(union cdu_context));
6351 6309
6352 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); 6310 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6353 val = (4 << 24) + (0 << 12) + 1024; 6311 val = (4 << 24) + (0 << 12) + 1024;
@@ -6476,7 +6434,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
6476 6434
6477 bnx2x__link_reset(bp); 6435 bnx2x__link_reset(bp);
6478 6436
6479 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port); 6437 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6480 6438
6481 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 6439 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6482 6440
@@ -6699,7 +6657,7 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
6699 u32 main_mem_base, main_mem_size, main_mem_prty_clr; 6657 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6700 int i, main_mem_width, rc; 6658 int i, main_mem_width, rc;
6701 6659
6702 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func); 6660 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
6703 6661
6704 /* FLR cleanup - hmmm */ 6662 /* FLR cleanup - hmmm */
6705 if (!CHIP_IS_E1x(bp)) { 6663 if (!CHIP_IS_E1x(bp)) {
@@ -6959,9 +6917,9 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
6959 6917
6960 val = REG_RD(bp, main_mem_prty_clr); 6918 val = REG_RD(bp, main_mem_prty_clr);
6961 if (val) 6919 if (val)
6962 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC " 6920 DP(NETIF_MSG_HW,
6963 "block during " 6921 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
6964 "function init (0x%x)!\n", val); 6922 val);
6965 6923
6966 /* Clear "false" parity errors in MSI-X table */ 6924 /* Clear "false" parity errors in MSI-X table */
6967 for (i = main_mem_base; 6925 for (i = main_mem_base;
@@ -7089,6 +7047,7 @@ static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7089alloc_mem_err: 7047alloc_mem_err:
7090 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, 7048 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7091 bp->fw_stats_data_sz + bp->fw_stats_req_sz); 7049 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7050 BNX2X_ERR("Can't allocate memory\n");
7092 return -ENOMEM; 7051 return -ENOMEM;
7093} 7052}
7094 7053
@@ -7152,6 +7111,7 @@ int bnx2x_alloc_mem(struct bnx2x *bp)
7152 7111
7153alloc_mem_err: 7112alloc_mem_err:
7154 bnx2x_free_mem(bp); 7113 bnx2x_free_mem(bp);
7114 BNX2X_ERR("Can't allocate memory\n");
7155 return -ENOMEM; 7115 return -ENOMEM;
7156} 7116}
7157 7117
@@ -7218,7 +7178,8 @@ int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7218 7178
7219#ifdef BCM_CNIC 7179#ifdef BCM_CNIC
7220 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) { 7180 if (is_zero_ether_addr(bp->dev->dev_addr) && IS_MF_ISCSI_SD(bp)) {
7221 DP(NETIF_MSG_IFUP, "Ignoring Zero MAC for iSCSI SD mode\n"); 7181 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7182 "Ignoring Zero MAC for STORAGE SD mode\n");
7222 return 0; 7183 return 0;
7223 } 7184 }
7224#endif 7185#endif
@@ -7251,14 +7212,13 @@ static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7251 /* falling through... */ 7212 /* falling through... */
7252 case INT_MODE_INTx: 7213 case INT_MODE_INTx:
7253 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7214 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7254 DP(NETIF_MSG_IFUP, "set number of queues to 1\n"); 7215 BNX2X_DEV_INFO("set number of queues to 1\n");
7255 break; 7216 break;
7256 default: 7217 default:
7257 /* Set number of queues according to bp->multi_mode value */ 7218 /* Set number of queues according to bp->multi_mode value */
7258 bnx2x_set_num_queues(bp); 7219 bnx2x_set_num_queues(bp);
7259 7220
7260 DP(NETIF_MSG_IFUP, "set number of queues to %d\n", 7221 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
7261 bp->num_queues);
7262 7222
7263 /* if we can't use MSI-X we only need one fp, 7223 /* if we can't use MSI-X we only need one fp,
7264 * so try to enable MSI-X with the requested number of fp's 7224 * so try to enable MSI-X with the requested number of fp's
@@ -7266,13 +7226,9 @@ static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7266 */ 7226 */
7267 if (bnx2x_enable_msix(bp)) { 7227 if (bnx2x_enable_msix(bp)) {
7268 /* failed to enable MSI-X */ 7228 /* failed to enable MSI-X */
7269 if (bp->multi_mode) 7229 BNX2X_DEV_INFO("Failed to enable MSI-X (%d), set number of queues to %d\n",
7270 DP(NETIF_MSG_IFUP, 7230 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7271 "Multi requested but failed to " 7231
7272 "enable MSI-X (%d), "
7273 "set number of queues to %d\n",
7274 bp->num_queues,
7275 1 + NON_ETH_CONTEXT_USE);
7276 bp->num_queues = 1 + NON_ETH_CONTEXT_USE; 7232 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7277 7233
7278 /* Try to enable MSI */ 7234 /* Try to enable MSI */
@@ -7310,8 +7266,7 @@ void bnx2x_ilt_set_info(struct bnx2x *bp)
7310#endif 7266#endif
7311 ilt_client->end = line - 1; 7267 ilt_client->end = line - 1;
7312 7268
7313 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, " 7269 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7314 "flags 0x%x, hw psz %d\n",
7315 ilt_client->start, 7270 ilt_client->start,
7316 ilt_client->end, 7271 ilt_client->end,
7317 ilt_client->page_size, 7272 ilt_client->page_size,
@@ -7332,8 +7287,8 @@ void bnx2x_ilt_set_info(struct bnx2x *bp)
7332 7287
7333 ilt_client->end = line - 1; 7288 ilt_client->end = line - 1;
7334 7289
7335 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, " 7290 DP(NETIF_MSG_IFUP,
7336 "flags 0x%x, hw psz %d\n", 7291 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7337 ilt_client->start, 7292 ilt_client->start,
7338 ilt_client->end, 7293 ilt_client->end,
7339 ilt_client->page_size, 7294 ilt_client->page_size,
@@ -7351,8 +7306,8 @@ void bnx2x_ilt_set_info(struct bnx2x *bp)
7351 line += SRC_ILT_LINES; 7306 line += SRC_ILT_LINES;
7352 ilt_client->end = line - 1; 7307 ilt_client->end = line - 1;
7353 7308
7354 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, " 7309 DP(NETIF_MSG_IFUP,
7355 "flags 0x%x, hw psz %d\n", 7310 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7356 ilt_client->start, 7311 ilt_client->start,
7357 ilt_client->end, 7312 ilt_client->end,
7358 ilt_client->page_size, 7313 ilt_client->page_size,
@@ -7373,8 +7328,8 @@ void bnx2x_ilt_set_info(struct bnx2x *bp)
7373 line += TM_ILT_LINES; 7328 line += TM_ILT_LINES;
7374 ilt_client->end = line - 1; 7329 ilt_client->end = line - 1;
7375 7330
7376 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, " 7331 DP(NETIF_MSG_IFUP,
7377 "flags 0x%x, hw psz %d\n", 7332 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7378 ilt_client->start, 7333 ilt_client->start,
7379 ilt_client->end, 7334 ilt_client->end,
7380 ilt_client->page_size, 7335 ilt_client->page_size,
@@ -7435,7 +7390,7 @@ static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7435 /* set maximum number of COSs supported by this queue */ 7390 /* set maximum number of COSs supported by this queue */
7436 init_params->max_cos = fp->max_cos; 7391 init_params->max_cos = fp->max_cos;
7437 7392
7438 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d\n", 7393 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7439 fp->index, init_params->max_cos); 7394 fp->index, init_params->max_cos);
7440 7395
7441 /* set the context pointers queue object */ 7396 /* set the context pointers queue object */
@@ -7466,9 +7421,8 @@ int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7466 /* Set Tx TX_ONLY_SETUP parameters */ 7421 /* Set Tx TX_ONLY_SETUP parameters */
7467 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); 7422 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7468 7423
7469 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:" 7424 DP(NETIF_MSG_IFUP,
7470 "cos %d, primary cid %d, cid %d, " 7425 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7471 "client id %d, sp-client id %d, flags %lx\n",
7472 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX], 7426 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7473 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id, 7427 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7474 tx_only_params->gen_params.spcl_id, tx_only_params->flags); 7428 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
@@ -7500,7 +7454,7 @@ int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7500 int rc; 7454 int rc;
7501 u8 tx_index; 7455 u8 tx_index;
7502 7456
7503 DP(BNX2X_MSG_SP, "setting up queue %d\n", fp->index); 7457 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7504 7458
7505 /* reset IGU state skip FCoE L2 queue */ 7459 /* reset IGU state skip FCoE L2 queue */
7506 if (!IS_FCOE_FP(fp)) 7460 if (!IS_FCOE_FP(fp))
@@ -7524,7 +7478,7 @@ int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7524 return rc; 7478 return rc;
7525 } 7479 }
7526 7480
7527 DP(BNX2X_MSG_SP, "init complete\n"); 7481 DP(NETIF_MSG_IFUP, "init complete\n");
7528 7482
7529 7483
7530 /* Now move the Queue to the SETUP state... */ 7484 /* Now move the Queue to the SETUP state... */
@@ -7578,7 +7532,7 @@ static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7578 struct bnx2x_queue_state_params q_params = {0}; 7532 struct bnx2x_queue_state_params q_params = {0};
7579 int rc, tx_index; 7533 int rc, tx_index;
7580 7534
7581 DP(BNX2X_MSG_SP, "stopping queue %d cid %d\n", index, fp->cid); 7535 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7582 7536
7583 q_params.q_obj = &fp->q_obj; 7537 q_params.q_obj = &fp->q_obj;
7584 /* We want to wait for completion in this context */ 7538 /* We want to wait for completion in this context */
@@ -7593,7 +7547,7 @@ static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7593 /* ascertain this is a normal queue*/ 7547 /* ascertain this is a normal queue*/
7594 txdata = &fp->txdata[tx_index]; 7548 txdata = &fp->txdata[tx_index];
7595 7549
7596 DP(BNX2X_MSG_SP, "stopping tx-only queue %d\n", 7550 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7597 txdata->txq_index); 7551 txdata->txq_index);
7598 7552
7599 /* send halt terminate on tx-only connection */ 7553 /* send halt terminate on tx-only connection */
@@ -7785,8 +7739,7 @@ static inline int bnx2x_func_stop(struct bnx2x *bp)
7785#ifdef BNX2X_STOP_ON_ERROR 7739#ifdef BNX2X_STOP_ON_ERROR
7786 return rc; 7740 return rc;
7787#else 7741#else
7788 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry " 7742 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
7789 "transaction\n");
7790 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 7743 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7791 return bnx2x_func_state_change(bp, &func_params); 7744 return bnx2x_func_state_change(bp, &func_params);
7792#endif 7745#endif
@@ -7849,14 +7802,12 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7849 else { 7802 else {
7850 int path = BP_PATH(bp); 7803 int path = BP_PATH(bp);
7851 7804
7852 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] " 7805 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
7853 "%d, %d, %d\n",
7854 path, load_count[path][0], load_count[path][1], 7806 path, load_count[path][0], load_count[path][1],
7855 load_count[path][2]); 7807 load_count[path][2]);
7856 load_count[path][0]--; 7808 load_count[path][0]--;
7857 load_count[path][1 + port]--; 7809 load_count[path][1 + port]--;
7858 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] " 7810 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
7859 "%d, %d, %d\n",
7860 path, load_count[path][0], load_count[path][1], 7811 path, load_count[path][0], load_count[path][1],
7861 load_count[path][2]); 7812 load_count[path][2]);
7862 if (load_count[path][0] == 0) 7813 if (load_count[path][0] == 0)
@@ -7919,6 +7870,7 @@ static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7919 if (bnx2x_func_get_state(bp, &bp->func_obj) != 7870 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7920 BNX2X_F_STATE_STARTED) { 7871 BNX2X_F_STATE_STARTED) {
7921#ifdef BNX2X_STOP_ON_ERROR 7872#ifdef BNX2X_STOP_ON_ERROR
7873 BNX2X_ERR("Wrong function state\n");
7922 return -EBUSY; 7874 return -EBUSY;
7923#else 7875#else
7924 /* 7876 /*
@@ -7927,8 +7879,8 @@ static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7927 */ 7879 */
7928 struct bnx2x_func_state_params func_params = {0}; 7880 struct bnx2x_func_state_params func_params = {0};
7929 7881
7930 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! " 7882 DP(NETIF_MSG_IFDOWN,
7931 "Forcing STARTED-->TX_ST0PPED-->STARTED\n"); 7883 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7932 7884
7933 func_params.f_obj = &bp->func_obj; 7885 func_params.f_obj = &bp->func_obj;
7934 __set_bit(RAMROD_DRV_CLR_ONLY, 7886 __set_bit(RAMROD_DRV_CLR_ONLY,
@@ -7979,8 +7931,8 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7979 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC, 7931 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7980 true); 7932 true);
7981 if (rc < 0) 7933 if (rc < 0)
7982 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: " 7934 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
7983 "%d\n", rc); 7935 rc);
7984 7936
7985 /* Disable LLH */ 7937 /* Disable LLH */
7986 if (!CHIP_IS_E1(bp)) 7938 if (!CHIP_IS_E1(bp))
@@ -8073,7 +8025,7 @@ void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8073{ 8025{
8074 u32 val; 8026 u32 val;
8075 8027
8076 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n"); 8028 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8077 8029
8078 if (CHIP_IS_E1(bp)) { 8030 if (CHIP_IS_E1(bp)) {
8079 int port = BP_PORT(bp); 8031 int port = BP_PORT(bp);
@@ -8126,7 +8078,7 @@ static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8126 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 8078 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8127 } 8079 }
8128 8080
8129 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n", 8081 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8130 close ? "closing" : "opening"); 8082 close ? "closing" : "opening");
8131 mmiowb(); 8083 mmiowb();
8132} 8084}
@@ -8168,7 +8120,7 @@ static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8168 u32 shmem; 8120 u32 shmem;
8169 u32 validity_offset; 8121 u32 validity_offset;
8170 8122
8171 DP(NETIF_MSG_HW, "Starting\n"); 8123 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8172 8124
8173 /* Set `magic' bit in order to save MF config */ 8125 /* Set `magic' bit in order to save MF config */
8174 if (!CHIP_IS_E1(bp)) 8126 if (!CHIP_IS_E1(bp))
@@ -8405,12 +8357,8 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8405 } while (cnt-- > 0); 8357 } while (cnt-- > 0);
8406 8358
8407 if (cnt <= 0) { 8359 if (cnt <= 0) {
8408 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there" 8360 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8409 " are still" 8361 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8410 " outstanding read requests after 1s!\n");
8411 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8412 " port_is_idle_0=0x%08x,"
8413 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8414 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, 8362 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8415 pgl_exp_rom2); 8363 pgl_exp_rom2);
8416 return -EAGAIN; 8364 return -EAGAIN;
@@ -8504,8 +8452,8 @@ int bnx2x_leader_reset(struct bnx2x *bp)
8504 8452
8505 /* Try to recover after the failure */ 8453 /* Try to recover after the failure */
8506 if (bnx2x_process_kill(bp, global)) { 8454 if (bnx2x_process_kill(bp, global)) {
8507 netdev_err(bp->dev, "Something bad had happen on engine %d! " 8455 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8508 "Aii!\n", BP_PATH(bp)); 8456 BP_PATH(bp));
8509 rc = -EAGAIN; 8457 rc = -EAGAIN;
8510 goto exit_leader_reset2; 8458 goto exit_leader_reset2;
8511 } 8459 }
@@ -8685,9 +8633,7 @@ static void bnx2x_parity_recover(struct bnx2x *bp)
8685 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { 8633 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
8686 error_unrecovered++; 8634 error_unrecovered++;
8687 netdev_err(bp->dev, 8635 netdev_err(bp->dev,
8688 "Recovery failed. " 8636 "Recovery failed. Power cycle needed\n");
8689 "Power cycle "
8690 "needed\n");
8691 /* Disconnect this device */ 8637 /* Disconnect this device */
8692 netif_device_detach(bp->dev); 8638 netif_device_detach(bp->dev);
8693 /* Shut down the power */ 8639 /* Shut down the power */
@@ -8730,8 +8676,7 @@ static void bnx2x_sp_rtnl_task(struct work_struct *work)
8730 8676
8731 /* if stop on error is defined no recovery flows should be executed */ 8677 /* if stop on error is defined no recovery flows should be executed */
8732#ifdef BNX2X_STOP_ON_ERROR 8678#ifdef BNX2X_STOP_ON_ERROR
8733 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined " 8679 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
8734 "so reset not done to allow debug dump,\n"
8735 "you will need to reboot when done\n"); 8680 "you will need to reboot when done\n");
8736 goto sp_rtnl_not_reset; 8681 goto sp_rtnl_not_reset;
8737#endif 8682#endif
@@ -8774,7 +8719,7 @@ sp_rtnl_not_reset:
8774 * damage 8719 * damage
8775 */ 8720 */
8776 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { 8721 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
8777 DP(BNX2X_MSG_SP, "fan failure detected. Unloading driver\n"); 8722 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
8778 netif_device_detach(bp->dev); 8723 netif_device_detach(bp->dev);
8779 bnx2x_close(bp->dev); 8724 bnx2x_close(bp->dev);
8780 } 8725 }
@@ -9002,6 +8947,8 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9002 bp->pfid = bp->pf_num; /* 0..7 */ 8947 bp->pfid = bp->pf_num; /* 0..7 */
9003 } 8948 }
9004 8949
8950 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
8951
9005 bp->link_params.chip_id = bp->common.chip_id; 8952 bp->link_params.chip_id = bp->common.chip_id;
9006 BNX2X_DEV_INFO("chip ID is 0x%x\n", id); 8953 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9007 8954
@@ -9059,8 +9006,8 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9059 if (val < BNX2X_BC_VER) { 9006 if (val < BNX2X_BC_VER) {
9060 /* for now only warn 9007 /* for now only warn
9061 * later we might need to enforce this */ 9008 * later we might need to enforce this */
9062 BNX2X_ERR("This driver needs bc_ver %X but found %X, " 9009 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9063 "please upgrade BC\n", BNX2X_BC_VER, val); 9010 BNX2X_BC_VER, val);
9064 } 9011 }
9065 bp->link_params.feature_config_flags |= 9012 bp->link_params.feature_config_flags |=
9066 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ? 9013 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
@@ -9201,8 +9148,7 @@ static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9201 } 9148 }
9202 9149
9203 if (!(bp->port.supported[0] || bp->port.supported[1])) { 9150 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9204 BNX2X_ERR("NVRAM config error. BAD phy config." 9151 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9205 "PHY1 config 0x%x, PHY2 config 0x%x\n",
9206 SHMEM_RD(bp, 9152 SHMEM_RD(bp,
9207 dev_info.port_hw_config[port].external_phy_config), 9153 dev_info.port_hw_config[port].external_phy_config),
9208 SHMEM_RD(bp, 9154 SHMEM_RD(bp,
@@ -9314,9 +9260,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9314 (ADVERTISED_10baseT_Full | 9260 (ADVERTISED_10baseT_Full |
9315 ADVERTISED_TP); 9261 ADVERTISED_TP);
9316 } else { 9262 } else {
9317 BNX2X_ERR("NVRAM config error. " 9263 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9318 "Invalid link_config 0x%x"
9319 " speed_cap_mask 0x%x\n",
9320 link_config, 9264 link_config,
9321 bp->link_params.speed_cap_mask[idx]); 9265 bp->link_params.speed_cap_mask[idx]);
9322 return; 9266 return;
@@ -9333,9 +9277,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9333 (ADVERTISED_10baseT_Half | 9277 (ADVERTISED_10baseT_Half |
9334 ADVERTISED_TP); 9278 ADVERTISED_TP);
9335 } else { 9279 } else {
9336 BNX2X_ERR("NVRAM config error. " 9280 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9337 "Invalid link_config 0x%x"
9338 " speed_cap_mask 0x%x\n",
9339 link_config, 9281 link_config,
9340 bp->link_params.speed_cap_mask[idx]); 9282 bp->link_params.speed_cap_mask[idx]);
9341 return; 9283 return;
@@ -9351,9 +9293,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9351 (ADVERTISED_100baseT_Full | 9293 (ADVERTISED_100baseT_Full |
9352 ADVERTISED_TP); 9294 ADVERTISED_TP);
9353 } else { 9295 } else {
9354 BNX2X_ERR("NVRAM config error. " 9296 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9355 "Invalid link_config 0x%x"
9356 " speed_cap_mask 0x%x\n",
9357 link_config, 9297 link_config,
9358 bp->link_params.speed_cap_mask[idx]); 9298 bp->link_params.speed_cap_mask[idx]);
9359 return; 9299 return;
@@ -9371,9 +9311,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9371 (ADVERTISED_100baseT_Half | 9311 (ADVERTISED_100baseT_Half |
9372 ADVERTISED_TP); 9312 ADVERTISED_TP);
9373 } else { 9313 } else {
9374 BNX2X_ERR("NVRAM config error. " 9314 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9375 "Invalid link_config 0x%x"
9376 " speed_cap_mask 0x%x\n",
9377 link_config, 9315 link_config,
9378 bp->link_params.speed_cap_mask[idx]); 9316 bp->link_params.speed_cap_mask[idx]);
9379 return; 9317 return;
@@ -9389,9 +9327,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9389 (ADVERTISED_1000baseT_Full | 9327 (ADVERTISED_1000baseT_Full |
9390 ADVERTISED_TP); 9328 ADVERTISED_TP);
9391 } else { 9329 } else {
9392 BNX2X_ERR("NVRAM config error. " 9330 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9393 "Invalid link_config 0x%x"
9394 " speed_cap_mask 0x%x\n",
9395 link_config, 9331 link_config,
9396 bp->link_params.speed_cap_mask[idx]); 9332 bp->link_params.speed_cap_mask[idx]);
9397 return; 9333 return;
@@ -9407,9 +9343,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9407 (ADVERTISED_2500baseX_Full | 9343 (ADVERTISED_2500baseX_Full |
9408 ADVERTISED_TP); 9344 ADVERTISED_TP);
9409 } else { 9345 } else {
9410 BNX2X_ERR("NVRAM config error. " 9346 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9411 "Invalid link_config 0x%x"
9412 " speed_cap_mask 0x%x\n",
9413 link_config, 9347 link_config,
9414 bp->link_params.speed_cap_mask[idx]); 9348 bp->link_params.speed_cap_mask[idx]);
9415 return; 9349 return;
@@ -9425,9 +9359,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9425 (ADVERTISED_10000baseT_Full | 9359 (ADVERTISED_10000baseT_Full |
9426 ADVERTISED_FIBRE); 9360 ADVERTISED_FIBRE);
9427 } else { 9361 } else {
9428 BNX2X_ERR("NVRAM config error. " 9362 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9429 "Invalid link_config 0x%x"
9430 " speed_cap_mask 0x%x\n",
9431 link_config, 9363 link_config,
9432 bp->link_params.speed_cap_mask[idx]); 9364 bp->link_params.speed_cap_mask[idx]);
9433 return; 9365 return;
@@ -9438,8 +9370,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9438 9370
9439 break; 9371 break;
9440 default: 9372 default:
9441 BNX2X_ERR("NVRAM config error. " 9373 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
9442 "BAD link speed link_config 0x%x\n",
9443 link_config); 9374 link_config);
9444 bp->link_params.req_line_speed[idx] = 9375 bp->link_params.req_line_speed[idx] =
9445 SPEED_AUTO_NEG; 9376 SPEED_AUTO_NEG;
@@ -9457,8 +9388,7 @@ static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9457 BNX2X_FLOW_CTRL_NONE; 9388 BNX2X_FLOW_CTRL_NONE;
9458 } 9389 }
9459 9390
9460 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl" 9391 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
9461 " 0x%x advertising 0x%x\n",
9462 bp->link_params.req_line_speed[idx], 9392 bp->link_params.req_line_speed[idx],
9463 bp->link_params.req_duplex[idx], 9393 bp->link_params.req_duplex[idx],
9464 bp->link_params.req_flow_ctrl[idx], 9394 bp->link_params.req_flow_ctrl[idx],
@@ -9507,8 +9437,7 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9507 bp->wol = (!(bp->flags & NO_WOL_FLAG) && 9437 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9508 (config & PORT_FEATURE_WOL_ENABLED)); 9438 (config & PORT_FEATURE_WOL_ENABLED));
9509 9439
9510 BNX2X_DEV_INFO("lane_config 0x%08x " 9440 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9511 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9512 bp->link_params.lane_config, 9441 bp->link_params.lane_config,
9513 bp->link_params.speed_cap_mask[0], 9442 bp->link_params.speed_cap_mask[0],
9514 bp->port.link_config[0]); 9443 bp->port.link_config[0]);
@@ -9773,10 +9702,11 @@ static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9773 9702
9774 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr)) 9703 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
9775 dev_err(&bp->pdev->dev, 9704 dev_err(&bp->pdev->dev,
9776 "bad Ethernet MAC address configuration: " 9705 "bad Ethernet MAC address configuration: %pM\n"
9777 "%pM, change it manually before bringing up " 9706 "change it manually before bringing up the appropriate network interface\n",
9778 "the appropriate network interface\n",
9779 bp->dev->dev_addr); 9707 bp->dev->dev_addr);
9708
9709
9780} 9710}
9781 9711
9782static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) 9712static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
@@ -9897,8 +9827,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9897 bp->mf_config[vn] = MF_CFG_RD(bp, 9827 bp->mf_config[vn] = MF_CFG_RD(bp,
9898 func_mf_config[func].config); 9828 func_mf_config[func].config);
9899 } else 9829 } else
9900 BNX2X_DEV_INFO("illegal MAC address " 9830 BNX2X_DEV_INFO("illegal MAC address for SI\n");
9901 "for SI\n");
9902 break; 9831 break;
9903 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 9832 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9904 /* get OV configuration */ 9833 /* get OV configuration */
@@ -9916,7 +9845,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9916 default: 9845 default:
9917 /* Unknown configuration: reset mf_config */ 9846 /* Unknown configuration: reset mf_config */
9918 bp->mf_config[vn] = 0; 9847 bp->mf_config[vn] = 0;
9919 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val); 9848 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
9920 } 9849 }
9921 } 9850 }
9922 9851
@@ -9931,25 +9860,24 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9931 bp->mf_ov = val; 9860 bp->mf_ov = val;
9932 bp->path_has_ovlan = true; 9861 bp->path_has_ovlan = true;
9933 9862
9934 BNX2X_DEV_INFO("MF OV for func %d is %d " 9863 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
9935 "(0x%04x)\n", func, bp->mf_ov, 9864 func, bp->mf_ov, bp->mf_ov);
9936 bp->mf_ov);
9937 } else { 9865 } else {
9938 dev_err(&bp->pdev->dev, 9866 dev_err(&bp->pdev->dev,
9939 "No valid MF OV for func %d, " 9867 "No valid MF OV for func %d, aborting\n",
9940 "aborting\n", func); 9868 func);
9941 return -EPERM; 9869 return -EPERM;
9942 } 9870 }
9943 break; 9871 break;
9944 case MULTI_FUNCTION_SI: 9872 case MULTI_FUNCTION_SI:
9945 BNX2X_DEV_INFO("func %d is in MF " 9873 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
9946 "switch-independent mode\n", func); 9874 func);
9947 break; 9875 break;
9948 default: 9876 default:
9949 if (vn) { 9877 if (vn) {
9950 dev_err(&bp->pdev->dev, 9878 dev_err(&bp->pdev->dev,
9951 "VN %d is in a single function mode, " 9879 "VN %d is in a single function mode, aborting\n",
9952 "aborting\n", vn); 9880 vn);
9953 return -EPERM; 9881 return -EPERM;
9954 } 9882 }
9955 break; 9883 break;
@@ -10157,8 +10085,7 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10157 dev_err(&bp->pdev->dev, "FPGA detected\n"); 10085 dev_err(&bp->pdev->dev, "FPGA detected\n");
10158 10086
10159 if (BP_NOMCP(bp) && (func == 0)) 10087 if (BP_NOMCP(bp) && (func == 0))
10160 dev_err(&bp->pdev->dev, "MCP disabled, " 10088 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10161 "must load devices in order!\n");
10162 10089
10163 bp->multi_mode = multi_mode; 10090 bp->multi_mode = multi_mode;
10164 10091
@@ -10282,10 +10209,8 @@ static int bnx2x_open(struct net_device *dev)
10282 bnx2x_set_power_state(bp, PCI_D3hot); 10209 bnx2x_set_power_state(bp, PCI_D3hot);
10283 bp->recovery_state = BNX2X_RECOVERY_FAILED; 10210 bp->recovery_state = BNX2X_RECOVERY_FAILED;
10284 10211
10285 netdev_err(bp->dev, "Recovery flow hasn't been properly" 10212 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10286 " completed yet. Try again later. If u still see this" 10213 "If you still see this message after a few retries then power cycle is required.\n");
10287 " message after a few retries then power cycle is"
10288 " required.\n");
10289 10214
10290 return -EAGAIN; 10215 return -EAGAIN;
10291 } while (0); 10216 } while (0);
@@ -10392,8 +10317,7 @@ static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10392 /* first, clear all configured multicast MACs */ 10317 /* first, clear all configured multicast MACs */
10393 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); 10318 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10394 if (rc < 0) { 10319 if (rc < 0) {
10395 BNX2X_ERR("Failed to clear multicast " 10320 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
10396 "configuration: %d\n", rc);
10397 return rc; 10321 return rc;
10398 } 10322 }
10399 10323
@@ -10401,8 +10325,8 @@ static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10401 if (netdev_mc_count(dev)) { 10325 if (netdev_mc_count(dev)) {
10402 rc = bnx2x_init_mcast_macs_list(bp, &rparam); 10326 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10403 if (rc) { 10327 if (rc) {
10404 BNX2X_ERR("Failed to create multicast MACs " 10328 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
10405 "list: %d\n", rc); 10329 rc);
10406 return rc; 10330 return rc;
10407 } 10331 }
10408 10332
@@ -10410,8 +10334,8 @@ static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10410 rc = bnx2x_config_mcast(bp, &rparam, 10334 rc = bnx2x_config_mcast(bp, &rparam,
10411 BNX2X_MCAST_CMD_ADD); 10335 BNX2X_MCAST_CMD_ADD);
10412 if (rc < 0) 10336 if (rc < 0)
10413 BNX2X_ERR("Failed to set a new multicast " 10337 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
10414 "configuration: %d\n", rc); 10338 rc);
10415 10339
10416 bnx2x_free_mcast_macs_list(&rparam); 10340 bnx2x_free_mcast_macs_list(&rparam);
10417 } 10341 }
@@ -10495,8 +10419,9 @@ static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10495 struct bnx2x *bp = netdev_priv(netdev); 10419 struct bnx2x *bp = netdev_priv(netdev);
10496 int rc; 10420 int rc;
10497 10421
10498 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x," 10422 DP(NETIF_MSG_LINK,
10499 " value 0x%x\n", prtad, devad, addr, value); 10423 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
10424 prtad, devad, addr, value);
10500 10425
10501 /* The HW expects different devad if CL22 is used */ 10426 /* The HW expects different devad if CL22 is used */
10502 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad; 10427 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
@@ -10537,8 +10462,10 @@ static int bnx2x_validate_addr(struct net_device *dev)
10537{ 10462{
10538 struct bnx2x *bp = netdev_priv(dev); 10463 struct bnx2x *bp = netdev_priv(dev);
10539 10464
10540 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) 10465 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
10466 BNX2X_ERR("Non-valid Ethernet address\n");
10541 return -EADDRNOTAVAIL; 10467 return -EADDRNOTAVAIL;
10468 }
10542 return 0; 10469 return 0;
10543} 10470}
10544 10471
@@ -10572,8 +10499,7 @@ static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10572 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) { 10499 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10573 bp->flags |= USING_DAC_FLAG; 10500 bp->flags |= USING_DAC_FLAG;
10574 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) { 10501 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10575 dev_err(dev, "dma_set_coherent_mask failed, " 10502 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
10576 "aborting\n");
10577 return -EIO; 10503 return -EIO;
10578 } 10504 }
10579 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) { 10505 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
@@ -10644,7 +10570,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10644 } 10570 }
10645 10571
10646 if (!pci_is_pcie(pdev)) { 10572 if (!pci_is_pcie(pdev)) {
10647 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); 10573 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10648 rc = -EIO; 10574 rc = -EIO;
10649 goto err_out_release; 10575 goto err_out_release;
10650 } 10576 }
@@ -10680,7 +10606,7 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10680 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> 10606 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
10681 ME_REG_ABS_PF_NUM_SHIFT); 10607 ME_REG_ABS_PF_NUM_SHIFT);
10682 } 10608 }
10683 DP(BNX2X_MSG_SP, "me reg PF num: %d\n", bp->pf_num); 10609 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
10684 10610
10685 bnx2x_set_power_state(bp, PCI_D0); 10611 bnx2x_set_power_state(bp, PCI_D0);
10686 10612
@@ -10782,8 +10708,10 @@ static int bnx2x_check_firmware(struct bnx2x *bp)
10782 int i; 10708 int i;
10783 const u8 *fw_ver; 10709 const u8 *fw_ver;
10784 10710
10785 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) 10711 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
10712 BNX2X_ERR("Wrong FW size\n");
10786 return -EINVAL; 10713 return -EINVAL;
10714 }
10787 10715
10788 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data; 10716 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10789 sections = (struct bnx2x_fw_file_section *)fw_hdr; 10717 sections = (struct bnx2x_fw_file_section *)fw_hdr;
@@ -10794,8 +10722,7 @@ static int bnx2x_check_firmware(struct bnx2x *bp)
10794 offset = be32_to_cpu(sections[i].offset); 10722 offset = be32_to_cpu(sections[i].offset);
10795 len = be32_to_cpu(sections[i].len); 10723 len = be32_to_cpu(sections[i].len);
10796 if (offset + len > firmware->size) { 10724 if (offset + len > firmware->size) {
10797 dev_err(&bp->pdev->dev, 10725 BNX2X_ERR("Section %d length is out of bounds\n", i);
10798 "Section %d length is out of bounds\n", i);
10799 return -EINVAL; 10726 return -EINVAL;
10800 } 10727 }
10801 } 10728 }
@@ -10807,8 +10734,7 @@ static int bnx2x_check_firmware(struct bnx2x *bp)
10807 10734
10808 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) { 10735 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10809 if (be16_to_cpu(ops_offsets[i]) > num_ops) { 10736 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10810 dev_err(&bp->pdev->dev, 10737 BNX2X_ERR("Section offset %d is out of bounds\n", i);
10811 "Section offset %d is out of bounds\n", i);
10812 return -EINVAL; 10738 return -EINVAL;
10813 } 10739 }
10814 } 10740 }
@@ -10820,10 +10746,9 @@ static int bnx2x_check_firmware(struct bnx2x *bp)
10820 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) || 10746 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10821 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) || 10747 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10822 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) { 10748 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10823 dev_err(&bp->pdev->dev, 10749 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10824 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n", 10750 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
10825 fw_ver[0], fw_ver[1], fw_ver[2], 10751 BCM_5710_FW_MAJOR_VERSION,
10826 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10827 BCM_5710_FW_MINOR_VERSION, 10752 BCM_5710_FW_MINOR_VERSION,
10828 BCM_5710_FW_REVISION_VERSION, 10753 BCM_5710_FW_REVISION_VERSION,
10829 BCM_5710_FW_ENGINEERING_VERSION); 10754 BCM_5710_FW_ENGINEERING_VERSION);
@@ -11142,7 +11067,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11142 11067
11143 bp = netdev_priv(dev); 11068 bp = netdev_priv(dev);
11144 11069
11145 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n", 11070 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11146 tx_count, rx_count); 11071 tx_count, rx_count);
11147 11072
11148 bp->igu_sb_cnt = max_non_def_sbs; 11073 bp->igu_sb_cnt = max_non_def_sbs;
@@ -11155,7 +11080,7 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11155 return rc; 11080 return rc;
11156 } 11081 }
11157 11082
11158 DP(NETIF_MSG_DRV, "max_non_def_sbs %d\n", max_non_def_sbs); 11083 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11159 11084
11160 rc = bnx2x_init_bp(bp); 11085 rc = bnx2x_init_bp(bp);
11161 if (rc) 11086 if (rc)
@@ -11210,7 +11135,8 @@ static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11210 11135
11211 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed); 11136 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11212 11137
11213 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n", 11138 BNX2X_DEV_INFO(
11139 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11214 board_info[ent->driver_data].name, 11140 board_info[ent->driver_data].name,
11215 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), 11141 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11216 pcie_width, 11142 pcie_width,
@@ -11429,8 +11355,7 @@ static void bnx2x_io_resume(struct pci_dev *pdev)
11429 struct bnx2x *bp = netdev_priv(dev); 11355 struct bnx2x *bp = netdev_priv(dev);
11430 11356
11431 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { 11357 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11432 netdev_err(bp->dev, "Handling parity error recovery. " 11358 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
11433 "Try again later\n");
11434 return; 11359 return;
11435 } 11360 }
11436 11361
@@ -11581,7 +11506,7 @@ static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11581 spe = bnx2x_sp_get_next(bp); 11506 spe = bnx2x_sp_get_next(bp);
11582 *spe = *bp->cnic_kwq_cons; 11507 *spe = *bp->cnic_kwq_cons;
11583 11508
11584 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n", 11509 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
11585 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); 11510 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11586 11511
11587 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) 11512 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
@@ -11600,14 +11525,15 @@ static int bnx2x_cnic_sp_queue(struct net_device *dev,
11600 int i; 11525 int i;
11601 11526
11602#ifdef BNX2X_STOP_ON_ERROR 11527#ifdef BNX2X_STOP_ON_ERROR
11603 if (unlikely(bp->panic)) 11528 if (unlikely(bp->panic)) {
11529 BNX2X_ERR("Can't post to SP queue while panic\n");
11604 return -EIO; 11530 return -EIO;
11531 }
11605#endif 11532#endif
11606 11533
11607 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && 11534 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
11608 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { 11535 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
11609 netdev_err(dev, "Handling parity error recovery. Try again " 11536 BNX2X_ERR("Handling parity error recovery. Try again later\n");
11610 "later\n");
11611 return -EAGAIN; 11537 return -EAGAIN;
11612 } 11538 }
11613 11539
@@ -11623,7 +11549,7 @@ static int bnx2x_cnic_sp_queue(struct net_device *dev,
11623 11549
11624 bp->cnic_kwq_pending++; 11550 bp->cnic_kwq_pending++;
11625 11551
11626 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n", 11552 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
11627 spe->hdr.conn_and_cmd_data, spe->hdr.type, 11553 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11628 spe->data.update_data_addr.hi, 11554 spe->data.update_data_addr.hi,
11629 spe->data.update_data_addr.lo, 11555 spe->data.update_data_addr.lo,
@@ -11904,8 +11830,10 @@ static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11904 struct bnx2x *bp = netdev_priv(dev); 11830 struct bnx2x *bp = netdev_priv(dev);
11905 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; 11831 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11906 11832
11907 if (ops == NULL) 11833 if (ops == NULL) {
11834 BNX2X_ERR("NULL ops received\n");
11908 return -EINVAL; 11835 return -EINVAL;
11836 }
11909 11837
11910 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); 11838 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11911 if (!bp->cnic_kwq) 11839 if (!bp->cnic_kwq)
@@ -11988,8 +11916,8 @@ struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11988 if (NO_FCOE(bp)) 11916 if (NO_FCOE(bp))
11989 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE; 11917 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11990 11918
11991 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, " 11919 BNX2X_DEV_INFO(
11992 "starting cid %d\n", 11920 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
11993 cp->ctx_blk_size, 11921 cp->ctx_blk_size,
11994 cp->ctx_tbl_offset, 11922 cp->ctx_tbl_offset,
11995 cp->ctx_tbl_len, 11923 cp->ctx_tbl_len,
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 484498f6bf1e..3f52fadee3ed 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -72,8 +72,8 @@ static inline void bnx2x_exe_queue_init(struct bnx2x *bp,
72 o->execute = exec; 72 o->execute = exec;
73 o->get = get; 73 o->get = get;
74 74
75 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk " 75 DP(BNX2X_MSG_SP, "Setup the execution queue with the chunk length of %d\n",
76 "length of %d\n", exe_len); 76 exe_len);
77} 77}
78 78
79static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp, 79static inline void bnx2x_exe_queue_free_elem(struct bnx2x *bp,
@@ -203,8 +203,7 @@ static inline int bnx2x_exe_queue_step(struct bnx2x *bp,
203 */ 203 */
204 if (!list_empty(&o->pending_comp)) { 204 if (!list_empty(&o->pending_comp)) {
205 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 205 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
206 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: " 206 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
207 "resetting pending_comp\n");
208 __bnx2x_exe_queue_reset_pending(bp, o); 207 __bnx2x_exe_queue_reset_pending(bp, o);
209 } else { 208 } else {
210 spin_unlock_bh(&o->lock); 209 spin_unlock_bh(&o->lock);
@@ -476,11 +475,14 @@ static int bnx2x_get_n_elements(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
476} 475}
477 476
478/* check_add() callbacks */ 477/* check_add() callbacks */
479static int bnx2x_check_mac_add(struct bnx2x_vlan_mac_obj *o, 478static int bnx2x_check_mac_add(struct bnx2x *bp,
479 struct bnx2x_vlan_mac_obj *o,
480 union bnx2x_classification_ramrod_data *data) 480 union bnx2x_classification_ramrod_data *data)
481{ 481{
482 struct bnx2x_vlan_mac_registry_elem *pos; 482 struct bnx2x_vlan_mac_registry_elem *pos;
483 483
484 DP(BNX2X_MSG_SP, "Checking MAC %pM for ADD command\n", data->mac.mac);
485
484 if (!is_valid_ether_addr(data->mac.mac)) 486 if (!is_valid_ether_addr(data->mac.mac))
485 return -EINVAL; 487 return -EINVAL;
486 488
@@ -492,11 +494,14 @@ static int bnx2x_check_mac_add(struct bnx2x_vlan_mac_obj *o,
492 return 0; 494 return 0;
493} 495}
494 496
495static int bnx2x_check_vlan_add(struct bnx2x_vlan_mac_obj *o, 497static int bnx2x_check_vlan_add(struct bnx2x *bp,
498 struct bnx2x_vlan_mac_obj *o,
496 union bnx2x_classification_ramrod_data *data) 499 union bnx2x_classification_ramrod_data *data)
497{ 500{
498 struct bnx2x_vlan_mac_registry_elem *pos; 501 struct bnx2x_vlan_mac_registry_elem *pos;
499 502
503 DP(BNX2X_MSG_SP, "Checking VLAN %d for ADD command\n", data->vlan.vlan);
504
500 list_for_each_entry(pos, &o->head, link) 505 list_for_each_entry(pos, &o->head, link)
501 if (data->vlan.vlan == pos->u.vlan.vlan) 506 if (data->vlan.vlan == pos->u.vlan.vlan)
502 return -EEXIST; 507 return -EEXIST;
@@ -504,11 +509,15 @@ static int bnx2x_check_vlan_add(struct bnx2x_vlan_mac_obj *o,
504 return 0; 509 return 0;
505} 510}
506 511
507static int bnx2x_check_vlan_mac_add(struct bnx2x_vlan_mac_obj *o, 512static int bnx2x_check_vlan_mac_add(struct bnx2x *bp,
513 struct bnx2x_vlan_mac_obj *o,
508 union bnx2x_classification_ramrod_data *data) 514 union bnx2x_classification_ramrod_data *data)
509{ 515{
510 struct bnx2x_vlan_mac_registry_elem *pos; 516 struct bnx2x_vlan_mac_registry_elem *pos;
511 517
518 DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for ADD command\n",
519 data->vlan_mac.mac, data->vlan_mac.vlan);
520
512 list_for_each_entry(pos, &o->head, link) 521 list_for_each_entry(pos, &o->head, link)
513 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 522 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
514 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, 523 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
@@ -521,11 +530,14 @@ static int bnx2x_check_vlan_mac_add(struct bnx2x_vlan_mac_obj *o,
521 530
522/* check_del() callbacks */ 531/* check_del() callbacks */
523static struct bnx2x_vlan_mac_registry_elem * 532static struct bnx2x_vlan_mac_registry_elem *
524 bnx2x_check_mac_del(struct bnx2x_vlan_mac_obj *o, 533 bnx2x_check_mac_del(struct bnx2x *bp,
534 struct bnx2x_vlan_mac_obj *o,
525 union bnx2x_classification_ramrod_data *data) 535 union bnx2x_classification_ramrod_data *data)
526{ 536{
527 struct bnx2x_vlan_mac_registry_elem *pos; 537 struct bnx2x_vlan_mac_registry_elem *pos;
528 538
539 DP(BNX2X_MSG_SP, "Checking MAC %pM for DEL command\n", data->mac.mac);
540
529 list_for_each_entry(pos, &o->head, link) 541 list_for_each_entry(pos, &o->head, link)
530 if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) 542 if (!memcmp(data->mac.mac, pos->u.mac.mac, ETH_ALEN))
531 return pos; 543 return pos;
@@ -534,11 +546,14 @@ static struct bnx2x_vlan_mac_registry_elem *
534} 546}
535 547
536static struct bnx2x_vlan_mac_registry_elem * 548static struct bnx2x_vlan_mac_registry_elem *
537 bnx2x_check_vlan_del(struct bnx2x_vlan_mac_obj *o, 549 bnx2x_check_vlan_del(struct bnx2x *bp,
550 struct bnx2x_vlan_mac_obj *o,
538 union bnx2x_classification_ramrod_data *data) 551 union bnx2x_classification_ramrod_data *data)
539{ 552{
540 struct bnx2x_vlan_mac_registry_elem *pos; 553 struct bnx2x_vlan_mac_registry_elem *pos;
541 554
555 DP(BNX2X_MSG_SP, "Checking VLAN %d for DEL command\n", data->vlan.vlan);
556
542 list_for_each_entry(pos, &o->head, link) 557 list_for_each_entry(pos, &o->head, link)
543 if (data->vlan.vlan == pos->u.vlan.vlan) 558 if (data->vlan.vlan == pos->u.vlan.vlan)
544 return pos; 559 return pos;
@@ -547,11 +562,15 @@ static struct bnx2x_vlan_mac_registry_elem *
547} 562}
548 563
549static struct bnx2x_vlan_mac_registry_elem * 564static struct bnx2x_vlan_mac_registry_elem *
550 bnx2x_check_vlan_mac_del(struct bnx2x_vlan_mac_obj *o, 565 bnx2x_check_vlan_mac_del(struct bnx2x *bp,
566 struct bnx2x_vlan_mac_obj *o,
551 union bnx2x_classification_ramrod_data *data) 567 union bnx2x_classification_ramrod_data *data)
552{ 568{
553 struct bnx2x_vlan_mac_registry_elem *pos; 569 struct bnx2x_vlan_mac_registry_elem *pos;
554 570
571 DP(BNX2X_MSG_SP, "Checking VLAN_MAC (%pM, %d) for DEL command\n",
572 data->vlan_mac.mac, data->vlan_mac.vlan);
573
555 list_for_each_entry(pos, &o->head, link) 574 list_for_each_entry(pos, &o->head, link)
556 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) && 575 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
557 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac, 576 (!memcmp(data->vlan_mac.mac, pos->u.vlan_mac.mac,
@@ -562,7 +581,8 @@ static struct bnx2x_vlan_mac_registry_elem *
562} 581}
563 582
564/* check_move() callback */ 583/* check_move() callback */
565static bool bnx2x_check_move(struct bnx2x_vlan_mac_obj *src_o, 584static bool bnx2x_check_move(struct bnx2x *bp,
585 struct bnx2x_vlan_mac_obj *src_o,
566 struct bnx2x_vlan_mac_obj *dst_o, 586 struct bnx2x_vlan_mac_obj *dst_o,
567 union bnx2x_classification_ramrod_data *data) 587 union bnx2x_classification_ramrod_data *data)
568{ 588{
@@ -572,10 +592,10 @@ static bool bnx2x_check_move(struct bnx2x_vlan_mac_obj *src_o,
572 /* Check if we can delete the requested configuration from the first 592 /* Check if we can delete the requested configuration from the first
573 * object. 593 * object.
574 */ 594 */
575 pos = src_o->check_del(src_o, data); 595 pos = src_o->check_del(bp, src_o, data);
576 596
577 /* check if configuration can be added */ 597 /* check if configuration can be added */
578 rc = dst_o->check_add(dst_o, data); 598 rc = dst_o->check_add(bp, dst_o, data);
579 599
580 /* If this classification can not be added (is already set) 600 /* If this classification can not be added (is already set)
581 * or can't be deleted - return an error. 601 * or can't be deleted - return an error.
@@ -587,6 +607,7 @@ static bool bnx2x_check_move(struct bnx2x_vlan_mac_obj *src_o,
587} 607}
588 608
589static bool bnx2x_check_move_always_err( 609static bool bnx2x_check_move_always_err(
610 struct bnx2x *bp,
590 struct bnx2x_vlan_mac_obj *src_o, 611 struct bnx2x_vlan_mac_obj *src_o,
591 struct bnx2x_vlan_mac_obj *dst_o, 612 struct bnx2x_vlan_mac_obj *dst_o,
592 union bnx2x_classification_ramrod_data *data) 613 union bnx2x_classification_ramrod_data *data)
@@ -740,7 +761,7 @@ static void bnx2x_set_one_mac_e2(struct bnx2x *bp,
740 &rule_entry->mac.header); 761 &rule_entry->mac.header);
741 762
742 DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n", 763 DP(BNX2X_MSG_SP, "About to %s MAC %pM for Queue %d\n",
743 add ? "add" : "delete", mac, raw->cl_id); 764 (add ? "add" : "delete"), mac, raw->cl_id);
744 765
745 /* Set a MAC itself */ 766 /* Set a MAC itself */
746 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb, 767 bnx2x_set_fw_mac_addr(&rule_entry->mac.mac_msb,
@@ -833,7 +854,7 @@ static inline void bnx2x_vlan_mac_set_rdata_e1x(struct bnx2x *bp,
833 cfg_entry); 854 cfg_entry);
834 855
835 DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n", 856 DP(BNX2X_MSG_SP, "%s MAC %pM CLID %d CAM offset %d\n",
836 add ? "setting" : "clearing", 857 (add ? "setting" : "clearing"),
837 mac, raw->cl_id, cam_offset); 858 mac, raw->cl_id, cam_offset);
838} 859}
839 860
@@ -1152,10 +1173,9 @@ static inline int bnx2x_validate_vlan_mac_add(struct bnx2x *bp,
1152 int rc; 1173 int rc;
1153 1174
1154 /* Check the registry */ 1175 /* Check the registry */
1155 rc = o->check_add(o, &elem->cmd_data.vlan_mac.u); 1176 rc = o->check_add(bp, o, &elem->cmd_data.vlan_mac.u);
1156 if (rc) { 1177 if (rc) {
1157 DP(BNX2X_MSG_SP, "ADD command is not allowed considering " 1178 DP(BNX2X_MSG_SP, "ADD command is not allowed considering current registry state.\n");
1158 "current registry state\n");
1159 return rc; 1179 return rc;
1160 } 1180 }
1161 1181
@@ -1206,10 +1226,9 @@ static inline int bnx2x_validate_vlan_mac_del(struct bnx2x *bp,
1206 /* If this classification can not be deleted (doesn't exist) 1226 /* If this classification can not be deleted (doesn't exist)
1207 * - return a BNX2X_EXIST. 1227 * - return a BNX2X_EXIST.
1208 */ 1228 */
1209 pos = o->check_del(o, &elem->cmd_data.vlan_mac.u); 1229 pos = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1210 if (!pos) { 1230 if (!pos) {
1211 DP(BNX2X_MSG_SP, "DEL command is not allowed considering " 1231 DP(BNX2X_MSG_SP, "DEL command is not allowed considering current registry state\n");
1212 "current registry state\n");
1213 return -EEXIST; 1232 return -EEXIST;
1214 } 1233 }
1215 1234
@@ -1269,9 +1288,9 @@ static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1269 * Check if we can perform this operation based on the current registry 1288 * Check if we can perform this operation based on the current registry
1270 * state. 1289 * state.
1271 */ 1290 */
1272 if (!src_o->check_move(src_o, dest_o, &elem->cmd_data.vlan_mac.u)) { 1291 if (!src_o->check_move(bp, src_o, dest_o,
1273 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering " 1292 &elem->cmd_data.vlan_mac.u)) {
1274 "current registry state\n"); 1293 DP(BNX2X_MSG_SP, "MOVE command is not allowed considering current registry state\n");
1275 return -EINVAL; 1294 return -EINVAL;
1276 } 1295 }
1277 1296
@@ -1285,8 +1304,7 @@ static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1285 /* Check DEL on source */ 1304 /* Check DEL on source */
1286 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL; 1305 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_DEL;
1287 if (src_exeq->get(src_exeq, &query_elem)) { 1306 if (src_exeq->get(src_exeq, &query_elem)) {
1288 BNX2X_ERR("There is a pending DEL command on the source " 1307 BNX2X_ERR("There is a pending DEL command on the source queue already\n");
1289 "queue already\n");
1290 return -EINVAL; 1308 return -EINVAL;
1291 } 1309 }
1292 1310
@@ -1299,8 +1317,7 @@ static inline int bnx2x_validate_vlan_mac_move(struct bnx2x *bp,
1299 /* Check ADD on destination */ 1317 /* Check ADD on destination */
1300 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD; 1318 query_elem.cmd_data.vlan_mac.cmd = BNX2X_VLAN_MAC_ADD;
1301 if (dest_exeq->get(dest_exeq, &query_elem)) { 1319 if (dest_exeq->get(dest_exeq, &query_elem)) {
1302 BNX2X_ERR("There is a pending ADD command on the " 1320 BNX2X_ERR("There is a pending ADD command on the destination queue already\n");
1303 "destination queue already\n");
1304 return -EINVAL; 1321 return -EINVAL;
1305 } 1322 }
1306 1323
@@ -1475,12 +1492,10 @@ static int bnx2x_optimize_vlan_mac(struct bnx2x *bp,
1475 &pos->cmd_data.vlan_mac.vlan_mac_flags)) { 1492 &pos->cmd_data.vlan_mac.vlan_mac_flags)) {
1476 if ((query.cmd_data.vlan_mac.cmd == 1493 if ((query.cmd_data.vlan_mac.cmd ==
1477 BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) { 1494 BNX2X_VLAN_MAC_ADD) && !o->put_credit(o)) {
1478 BNX2X_ERR("Failed to return the credit for the " 1495 BNX2X_ERR("Failed to return the credit for the optimized ADD command\n");
1479 "optimized ADD command\n");
1480 return -EINVAL; 1496 return -EINVAL;
1481 } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */ 1497 } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */
1482 BNX2X_ERR("Failed to recover the credit from " 1498 BNX2X_ERR("Failed to recover the credit from the optimized DEL command\n");
1483 "the optimized DEL command\n");
1484 return -EINVAL; 1499 return -EINVAL;
1485 } 1500 }
1486 } 1501 }
@@ -1546,7 +1561,7 @@ static inline int bnx2x_vlan_mac_get_registry_elem(
1546 reg_elem->vlan_mac_flags = 1561 reg_elem->vlan_mac_flags =
1547 elem->cmd_data.vlan_mac.vlan_mac_flags; 1562 elem->cmd_data.vlan_mac.vlan_mac_flags;
1548 } else /* DEL, RESTORE */ 1563 } else /* DEL, RESTORE */
1549 reg_elem = o->check_del(o, &elem->cmd_data.vlan_mac.u); 1564 reg_elem = o->check_del(bp, o, &elem->cmd_data.vlan_mac.u);
1550 1565
1551 *re = reg_elem; 1566 *re = reg_elem;
1552 return 0; 1567 return 0;
@@ -1644,7 +1659,8 @@ static int bnx2x_execute_vlan_mac(struct bnx2x *bp,
1644 cmd = elem->cmd_data.vlan_mac.cmd; 1659 cmd = elem->cmd_data.vlan_mac.cmd;
1645 if ((cmd == BNX2X_VLAN_MAC_DEL) || 1660 if ((cmd == BNX2X_VLAN_MAC_DEL) ||
1646 (cmd == BNX2X_VLAN_MAC_MOVE)) { 1661 (cmd == BNX2X_VLAN_MAC_MOVE)) {
1647 reg_elem = o->check_del(o, &elem->cmd_data.vlan_mac.u); 1662 reg_elem = o->check_del(bp, o,
1663 &elem->cmd_data.vlan_mac.u);
1648 1664
1649 WARN_ON(!reg_elem); 1665 WARN_ON(!reg_elem);
1650 1666
@@ -1675,7 +1691,7 @@ error_exit:
1675 if (!restore && 1691 if (!restore &&
1676 ((cmd == BNX2X_VLAN_MAC_ADD) || 1692 ((cmd == BNX2X_VLAN_MAC_ADD) ||
1677 (cmd == BNX2X_VLAN_MAC_MOVE))) { 1693 (cmd == BNX2X_VLAN_MAC_MOVE))) {
1678 reg_elem = o->check_del(cam_obj, 1694 reg_elem = o->check_del(bp, cam_obj,
1679 &elem->cmd_data.vlan_mac.u); 1695 &elem->cmd_data.vlan_mac.u);
1680 if (reg_elem) { 1696 if (reg_elem) {
1681 list_del(&reg_elem->link); 1697 list_del(&reg_elem->link);
@@ -1750,8 +1766,7 @@ int bnx2x_config_vlan_mac(
1750 rc = 1; 1766 rc = 1;
1751 1767
1752 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) { 1768 if (test_bit(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
1753 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: " 1769 DP(BNX2X_MSG_SP, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
1754 "clearing a pending bit.\n");
1755 raw->clear_pending(raw); 1770 raw->clear_pending(raw);
1756 } 1771 }
1757 1772
@@ -2149,12 +2164,10 @@ static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
2149 mac_filters->unmatched_unicast & ~mask; 2164 mac_filters->unmatched_unicast & ~mask;
2150 2165
2151 DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n" 2166 DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2152 "accp_mcast 0x%x\naccp_bcast 0x%x\n", 2167 "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2153 mac_filters->ucast_drop_all, 2168 mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
2154 mac_filters->mcast_drop_all, 2169 mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
2155 mac_filters->ucast_accept_all, 2170 mac_filters->bcast_accept_all);
2156 mac_filters->mcast_accept_all,
2157 mac_filters->bcast_accept_all);
2158 2171
2159 /* write the MAC filter structure*/ 2172 /* write the MAC filter structure*/
2160 __storm_memset_mac_filters(bp, mac_filters, p->func_id); 2173 __storm_memset_mac_filters(bp, mac_filters, p->func_id);
@@ -2303,8 +2316,7 @@ static int bnx2x_set_rx_mode_e2(struct bnx2x *bp,
2303 */ 2316 */
2304 bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx); 2317 bnx2x_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
2305 2318
2306 DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, " 2319 DP(BNX2X_MSG_SP, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2307 "tx_accept_flags 0x%lx\n",
2308 data->header.rule_cnt, p->rx_accept_flags, 2320 data->header.rule_cnt, p->rx_accept_flags,
2309 p->tx_accept_flags); 2321 p->tx_accept_flags);
2310 2322
@@ -2437,8 +2449,8 @@ static int bnx2x_mcast_enqueue_cmd(struct bnx2x *bp,
2437 if (!new_cmd) 2449 if (!new_cmd)
2438 return -ENOMEM; 2450 return -ENOMEM;
2439 2451
2440 DP(BNX2X_MSG_SP, "About to enqueue a new %d command. " 2452 DP(BNX2X_MSG_SP, "About to enqueue a new %d command. macs_list_len=%d\n",
2441 "macs_list_len=%d\n", cmd, macs_list_len); 2453 cmd, macs_list_len);
2442 2454
2443 INIT_LIST_HEAD(&new_cmd->data.macs_head); 2455 INIT_LIST_HEAD(&new_cmd->data.macs_head);
2444 2456
@@ -2653,7 +2665,7 @@ static inline void bnx2x_mcast_hdl_pending_add_e2(struct bnx2x *bp,
2653 cnt++; 2665 cnt++;
2654 2666
2655 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n", 2667 DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
2656 pmac_pos->mac); 2668 pmac_pos->mac);
2657 2669
2658 list_del(&pmac_pos->link); 2670 list_del(&pmac_pos->link);
2659 2671
@@ -3177,8 +3189,8 @@ static int bnx2x_mcast_validate_e1(struct bnx2x *bp,
3177 * matter. 3189 * matter.
3178 */ 3190 */
3179 if (p->mcast_list_len > o->max_cmd_len) { 3191 if (p->mcast_list_len > o->max_cmd_len) {
3180 BNX2X_ERR("Can't configure more than %d multicast MACs" 3192 BNX2X_ERR("Can't configure more than %d multicast MACs on 57710\n",
3181 "on 57710\n", o->max_cmd_len); 3193 o->max_cmd_len);
3182 return -EINVAL; 3194 return -EINVAL;
3183 } 3195 }
3184 /* Every configured MAC should be cleared if DEL command is 3196 /* Every configured MAC should be cleared if DEL command is
@@ -3426,7 +3438,7 @@ static inline int bnx2x_mcast_refresh_registry_e1(struct bnx2x *bp,
3426 &data->config_table[i].lsb_mac_addr, 3438 &data->config_table[i].lsb_mac_addr,
3427 elem->mac); 3439 elem->mac);
3428 DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n", 3440 DP(BNX2X_MSG_SP, "Adding registry entry for [%pM]\n",
3429 elem->mac); 3441 elem->mac);
3430 list_add_tail(&elem->link, 3442 list_add_tail(&elem->link,
3431 &o->registry.exact_match.macs); 3443 &o->registry.exact_match.macs);
3432 } 3444 }
@@ -3567,9 +3579,8 @@ int bnx2x_config_mcast(struct bnx2x *bp,
3567 if ((!p->mcast_list_len) && (!o->check_sched(o))) 3579 if ((!p->mcast_list_len) && (!o->check_sched(o)))
3568 return 0; 3580 return 0;
3569 3581
3570 DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d " 3582 DP(BNX2X_MSG_SP, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3571 "o->max_cmd_len=%d\n", o->total_pending_num, 3583 o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
3572 p->mcast_list_len, o->max_cmd_len);
3573 3584
3574 /* Enqueue the current command to the pending list if we can't complete 3585 /* Enqueue the current command to the pending list if we can't complete
3575 * it in the current iteration 3586 * it in the current iteration
@@ -4294,9 +4305,8 @@ static int bnx2x_queue_comp_cmd(struct bnx2x *bp,
4294 unsigned long cur_pending = o->pending; 4305 unsigned long cur_pending = o->pending;
4295 4306
4296 if (!test_and_clear_bit(cmd, &cur_pending)) { 4307 if (!test_and_clear_bit(cmd, &cur_pending)) {
4297 BNX2X_ERR("Bad MC reply %d for queue %d in state %d " 4308 BNX2X_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4298 "pending 0x%lx, next_state %d\n", cmd, 4309 cmd, o->cids[BNX2X_PRIMARY_CID_INDEX],
4299 o->cids[BNX2X_PRIMARY_CID_INDEX],
4300 o->state, cur_pending, o->next_state); 4310 o->state, cur_pending, o->next_state);
4301 return -EINVAL; 4311 return -EINVAL;
4302 } 4312 }
@@ -4308,13 +4318,13 @@ static int bnx2x_queue_comp_cmd(struct bnx2x *bp,
4308 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d", 4318 BNX2X_ERR("illegal value for next tx_only: %d. max cos was %d",
4309 o->next_tx_only, o->max_cos); 4319 o->next_tx_only, o->max_cos);
4310 4320
4311 DP(BNX2X_MSG_SP, "Completing command %d for queue %d, " 4321 DP(BNX2X_MSG_SP,
4312 "setting state to %d\n", cmd, 4322 "Completing command %d for queue %d, setting state to %d\n",
4313 o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state); 4323 cmd, o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_state);
4314 4324
4315 if (o->next_tx_only) /* print num tx-only if any exist */ 4325 if (o->next_tx_only) /* print num tx-only if any exist */
4316 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n", 4326 DP(BNX2X_MSG_SP, "primary cid %d: num tx-only cons %d\n",
4317 o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only); 4327 o->cids[BNX2X_PRIMARY_CID_INDEX], o->next_tx_only);
4318 4328
4319 o->state = o->next_state; 4329 o->state = o->next_state;
4320 o->num_tx_only = o->next_tx_only; 4330 o->num_tx_only = o->next_tx_only;
@@ -4529,8 +4539,10 @@ static void bnx2x_q_fill_setup_tx_only(struct bnx2x *bp,
4529 &data->tx, 4539 &data->tx,
4530 &cmd_params->params.tx_only.flags); 4540 &cmd_params->params.tx_only.flags);
4531 4541
4532 DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x\n",cmd_params->q_obj->cids[0], 4542 DP(BNX2X_MSG_SP, "cid %d, tx bd page lo %x hi %x",
4533 data->tx.tx_bd_page_base.lo, data->tx.tx_bd_page_base.hi); 4543 cmd_params->q_obj->cids[0],
4544 data->tx.tx_bd_page_base.lo,
4545 data->tx.tx_bd_page_base.hi);
4534} 4546}
4535 4547
4536/** 4548/**
@@ -4677,10 +4689,8 @@ static inline int bnx2x_q_send_setup_tx_only(struct bnx2x *bp,
4677 /* Fill the ramrod data */ 4689 /* Fill the ramrod data */
4678 bnx2x_q_fill_setup_tx_only(bp, params, rdata); 4690 bnx2x_q_fill_setup_tx_only(bp, params, rdata);
4679 4691
4680 DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d," 4692 DP(BNX2X_MSG_SP, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
4681 "sp-client id %d, cos %d\n", 4693 o->cids[cid_index], rdata->general.client_id,
4682 o->cids[cid_index],
4683 rdata->general.client_id,
4684 rdata->general.sp_client_id, rdata->general.cos); 4694 rdata->general.sp_client_id, rdata->general.cos);
4685 4695
4686 /* 4696 /*
@@ -5222,9 +5232,9 @@ static inline int bnx2x_func_state_change_comp(struct bnx2x *bp,
5222 unsigned long cur_pending = o->pending; 5232 unsigned long cur_pending = o->pending;
5223 5233
5224 if (!test_and_clear_bit(cmd, &cur_pending)) { 5234 if (!test_and_clear_bit(cmd, &cur_pending)) {
5225 BNX2X_ERR("Bad MC reply %d for func %d in state %d " 5235 BNX2X_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5226 "pending 0x%lx, next_state %d\n", cmd, BP_FUNC(bp), 5236 cmd, BP_FUNC(bp), o->state,
5227 o->state, cur_pending, o->next_state); 5237 cur_pending, o->next_state);
5228 return -EINVAL; 5238 return -EINVAL;
5229 } 5239 }
5230 5240
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
index 4ce351b4d517..61a7670adfcd 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
@@ -315,7 +315,8 @@ struct bnx2x_vlan_mac_obj {
315 * @return zero if the element may be added 315 * @return zero if the element may be added
316 */ 316 */
317 317
318 int (*check_add)(struct bnx2x_vlan_mac_obj *o, 318 int (*check_add)(struct bnx2x *bp,
319 struct bnx2x_vlan_mac_obj *o,
319 union bnx2x_classification_ramrod_data *data); 320 union bnx2x_classification_ramrod_data *data);
320 321
321 /** 322 /**
@@ -324,7 +325,8 @@ struct bnx2x_vlan_mac_obj {
324 * @return true if the element may be deleted 325 * @return true if the element may be deleted
325 */ 326 */
326 struct bnx2x_vlan_mac_registry_elem * 327 struct bnx2x_vlan_mac_registry_elem *
327 (*check_del)(struct bnx2x_vlan_mac_obj *o, 328 (*check_del)(struct bnx2x *bp,
329 struct bnx2x_vlan_mac_obj *o,
328 union bnx2x_classification_ramrod_data *data); 330 union bnx2x_classification_ramrod_data *data);
329 331
330 /** 332 /**
@@ -332,7 +334,8 @@ struct bnx2x_vlan_mac_obj {
332 * 334 *
333 * @return true if the element may be deleted 335 * @return true if the element may be deleted
334 */ 336 */
335 bool (*check_move)(struct bnx2x_vlan_mac_obj *src_o, 337 bool (*check_move)(struct bnx2x *bp,
338 struct bnx2x_vlan_mac_obj *src_o,
336 struct bnx2x_vlan_mac_obj *dst_o, 339 struct bnx2x_vlan_mac_obj *dst_o,
337 union bnx2x_classification_ramrod_data *data); 340 union bnx2x_classification_ramrod_data *data);
338 341
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
index 4cd4f127fe79..ca1effceff6f 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
@@ -75,7 +75,7 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
75 bp->fw_stats_req->hdr.drv_stats_counter = 75 bp->fw_stats_req->hdr.drv_stats_counter =
76 cpu_to_le16(bp->stats_counter++); 76 cpu_to_le16(bp->stats_counter++);
77 77
78 DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n", 78 DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n",
79 bp->fw_stats_req->hdr.drv_stats_counter); 79 bp->fw_stats_req->hdr.drv_stats_counter);
80 80
81 81
@@ -818,29 +818,29 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
818 818
819 /* are storm stats valid? */ 819 /* are storm stats valid? */
820 if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) { 820 if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
821 DP(BNX2X_MSG_STATS, "stats not updated by xstorm" 821 DP(BNX2X_MSG_STATS,
822 " xstorm counter (0x%x) != stats_counter (0x%x)\n", 822 "stats not updated by xstorm xstorm counter (0x%x) != stats_counter (0x%x)\n",
823 le16_to_cpu(counters->xstats_counter), bp->stats_counter); 823 le16_to_cpu(counters->xstats_counter), bp->stats_counter);
824 return -EAGAIN; 824 return -EAGAIN;
825 } 825 }
826 826
827 if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) { 827 if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
828 DP(BNX2X_MSG_STATS, "stats not updated by ustorm" 828 DP(BNX2X_MSG_STATS,
829 " ustorm counter (0x%x) != stats_counter (0x%x)\n", 829 "stats not updated by ustorm ustorm counter (0x%x) != stats_counter (0x%x)\n",
830 le16_to_cpu(counters->ustats_counter), bp->stats_counter); 830 le16_to_cpu(counters->ustats_counter), bp->stats_counter);
831 return -EAGAIN; 831 return -EAGAIN;
832 } 832 }
833 833
834 if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) { 834 if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
835 DP(BNX2X_MSG_STATS, "stats not updated by cstorm" 835 DP(BNX2X_MSG_STATS,
836 " cstorm counter (0x%x) != stats_counter (0x%x)\n", 836 "stats not updated by cstorm cstorm counter (0x%x) != stats_counter (0x%x)\n",
837 le16_to_cpu(counters->cstats_counter), bp->stats_counter); 837 le16_to_cpu(counters->cstats_counter), bp->stats_counter);
838 return -EAGAIN; 838 return -EAGAIN;
839 } 839 }
840 840
841 if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) { 841 if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
842 DP(BNX2X_MSG_STATS, "stats not updated by tstorm" 842 DP(BNX2X_MSG_STATS,
843 " tstorm counter (0x%x) != stats_counter (0x%x)\n", 843 "stats not updated by tstorm tstorm counter (0x%x) != stats_counter (0x%x)\n",
844 le16_to_cpu(counters->tstats_counter), bp->stats_counter); 844 le16_to_cpu(counters->tstats_counter), bp->stats_counter);
845 return -EAGAIN; 845 return -EAGAIN;
846 } 846 }
@@ -867,8 +867,7 @@ static int bnx2x_storm_stats_update(struct bnx2x *bp)
867 867
868 u32 diff; 868 u32 diff;
869 869
870 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, " 870 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, bcast_sent 0x%x mcast_sent 0x%x\n",
871 "bcast_sent 0x%x mcast_sent 0x%x\n",
872 i, xclient->ucast_pkts_sent, 871 i, xclient->ucast_pkts_sent,
873 xclient->bcast_pkts_sent, xclient->mcast_pkts_sent); 872 xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
874 873
@@ -1147,51 +1146,9 @@ static void bnx2x_stats_update(struct bnx2x *bp)
1147 1146
1148 if (netif_msg_timer(bp)) { 1147 if (netif_msg_timer(bp)) {
1149 struct bnx2x_eth_stats *estats = &bp->eth_stats; 1148 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1150 int i, cos;
1151 1149
1152 netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n", 1150 netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
1153 estats->brb_drop_lo, estats->brb_truncate_lo); 1151 estats->brb_drop_lo, estats->brb_truncate_lo);
1154
1155 for_each_eth_queue(bp, i) {
1156 struct bnx2x_fastpath *fp = &bp->fp[i];
1157 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1158
1159 pr_debug("%s: rx usage(%4u) *rx_cons_sb(%u) rx pkt(%lu) rx calls(%lu %lu)\n",
1160 fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
1161 fp->rx_comp_cons),
1162 le16_to_cpu(*fp->rx_cons_sb),
1163 bnx2x_hilo(&qstats->
1164 total_unicast_packets_received_hi),
1165 fp->rx_calls, fp->rx_pkt);
1166 }
1167
1168 for_each_eth_queue(bp, i) {
1169 struct bnx2x_fastpath *fp = &bp->fp[i];
1170 struct bnx2x_fp_txdata *txdata;
1171 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1172 struct netdev_queue *txq;
1173
1174 pr_debug("%s: tx pkt(%lu) (Xoff events %u)",
1175 fp->name,
1176 bnx2x_hilo(
1177 &qstats->total_unicast_packets_transmitted_hi),
1178 qstats->driver_xoff);
1179
1180 for_each_cos_in_tx_queue(fp, cos) {
1181 txdata = &fp->txdata[cos];
1182 txq = netdev_get_tx_queue(bp->dev,
1183 FP_COS_TO_TXQ(fp, cos));
1184
1185 pr_debug("%d: tx avail(%4u) *tx_cons_sb(%u) tx calls (%lu) %s\n",
1186 cos,
1187 bnx2x_tx_avail(bp, txdata),
1188 le16_to_cpu(*txdata->tx_cons_sb),
1189 txdata->tx_pkt,
1190 (netif_tx_queue_stopped(txq) ?
1191 "Xoff" : "Xon")
1192 );
1193 }
1194 }
1195 } 1152 }
1196 1153
1197 bnx2x_hw_stats_post(bp); 1154 bnx2x_hw_stats_post(bp);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 17:33:32 -0400