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-rw-r--r--drivers/net/sky2.c5
-rw-r--r--drivers/net/sky2.h14
2 files changed, 19 insertions, 0 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index fbe39d929277..1f1b6db434be 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -230,6 +230,11 @@ static void sky2_power_on(struct sky2_hw *hw)
230 sky2_pci_write32(hw, PCI_DEV_REG5, reg); 230 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
231 231
232 sky2_pci_write32(hw, PCI_CFG_REG_1, 0); 232 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
233
234 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
235 reg = sky2_read32(hw, B2_GP_IO);
236 reg |= GLB_GPIO_STAT_RACE_DIS;
237 sky2_write32(hw, B2_GP_IO, reg);
233 } 238 }
234} 239}
235 240
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index 00907f58019e..c6c0baffc082 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -441,6 +441,20 @@ enum {
441 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */ 441 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
442}; 442};
443 443
444/* B2_GPIO */
445enum {
446 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
447 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
448
449 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
450 GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
451 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
452 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
453 GLB_GPIO_TEST_SEL_BASE = 1<<11,
454 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
455 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
456};
457
444/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 458/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
445enum { 459enum {
446 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */ 460 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */