diff options
Diffstat (limited to 'drivers/net')
54 files changed, 780 insertions, 503 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8d0314dbd946..a44874e24f2a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
@@ -2535,7 +2535,7 @@ config S6GMAC | |||
2535 | source "drivers/net/stmmac/Kconfig" | 2535 | source "drivers/net/stmmac/Kconfig" |
2536 | 2536 | ||
2537 | config PCH_GBE | 2537 | config PCH_GBE |
2538 | tristate "Intel EG20T PCH / OKI SEMICONDUCTOR ML7223 IOH GbE" | 2538 | tristate "Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7223/ML7831) GbE" |
2539 | depends on PCI | 2539 | depends on PCI |
2540 | select MII | 2540 | select MII |
2541 | ---help--- | 2541 | ---help--- |
@@ -2548,10 +2548,11 @@ config PCH_GBE | |||
2548 | This driver enables Gigabit Ethernet function. | 2548 | This driver enables Gigabit Ethernet function. |
2549 | 2549 | ||
2550 | This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ | 2550 | This driver also can be used for OKI SEMICONDUCTOR IOH(Input/ |
2551 | Output Hub), ML7223. | 2551 | Output Hub), ML7223/ML7831. |
2552 | ML7223 IOH is for MP(Media Phone) use. | 2552 | ML7223 IOH is for MP(Media Phone) use. ML7831 IOH is for general |
2553 | ML7223 is companion chip for Intel Atom E6xx series. | 2553 | purpose use. |
2554 | ML7223 is completely compatible for Intel EG20T PCH. | 2554 | ML7223/ML7831 is companion chip for Intel Atom E6xx series. |
2555 | ML7223/ML7831 is completely compatible for Intel EG20T PCH. | ||
2555 | 2556 | ||
2556 | config FTGMAC100 | 2557 | config FTGMAC100 |
2557 | tristate "Faraday FTGMAC100 Gigabit Ethernet support" | 2558 | tristate "Faraday FTGMAC100 Gigabit Ethernet support" |
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c index 52fe21e1e2cd..3b1416e3d217 100644 --- a/drivers/net/arm/am79c961a.c +++ b/drivers/net/arm/am79c961a.c | |||
@@ -308,8 +308,11 @@ static void am79c961_timer(unsigned long data) | |||
308 | struct net_device *dev = (struct net_device *)data; | 308 | struct net_device *dev = (struct net_device *)data; |
309 | struct dev_priv *priv = netdev_priv(dev); | 309 | struct dev_priv *priv = netdev_priv(dev); |
310 | unsigned int lnkstat, carrier; | 310 | unsigned int lnkstat, carrier; |
311 | unsigned long flags; | ||
311 | 312 | ||
313 | spin_lock_irqsave(&priv->chip_lock, flags); | ||
312 | lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST; | 314 | lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST; |
315 | spin_unlock_irqrestore(&priv->chip_lock, flags); | ||
313 | carrier = netif_carrier_ok(dev); | 316 | carrier = netif_carrier_ok(dev); |
314 | 317 | ||
315 | if (lnkstat && !carrier) { | 318 | if (lnkstat && !carrier) { |
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h index c423504a755f..e46df5331c55 100644 --- a/drivers/net/bnx2x/bnx2x.h +++ b/drivers/net/bnx2x/bnx2x.h | |||
@@ -315,6 +315,14 @@ union db_prod { | |||
315 | u32 raw; | 315 | u32 raw; |
316 | }; | 316 | }; |
317 | 317 | ||
318 | /* dropless fc FW/HW related params */ | ||
319 | #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) | ||
320 | #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ | ||
321 | ETH_MAX_AGGREGATION_QUEUES_E1 :\ | ||
322 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2) | ||
323 | #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) | ||
324 | #define FW_PREFETCH_CNT 16 | ||
325 | #define DROPLESS_FC_HEADROOM 100 | ||
318 | 326 | ||
319 | /* MC hsi */ | 327 | /* MC hsi */ |
320 | #define BCM_PAGE_SHIFT 12 | 328 | #define BCM_PAGE_SHIFT 12 |
@@ -331,15 +339,35 @@ union db_prod { | |||
331 | /* SGE ring related macros */ | 339 | /* SGE ring related macros */ |
332 | #define NUM_RX_SGE_PAGES 2 | 340 | #define NUM_RX_SGE_PAGES 2 |
333 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) | 341 | #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) |
334 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - 2) | 342 | #define NEXT_PAGE_SGE_DESC_CNT 2 |
343 | #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) | ||
335 | /* RX_SGE_CNT is promised to be a power of 2 */ | 344 | /* RX_SGE_CNT is promised to be a power of 2 */ |
336 | #define RX_SGE_MASK (RX_SGE_CNT - 1) | 345 | #define RX_SGE_MASK (RX_SGE_CNT - 1) |
337 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) | 346 | #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) |
338 | #define MAX_RX_SGE (NUM_RX_SGE - 1) | 347 | #define MAX_RX_SGE (NUM_RX_SGE - 1) |
339 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ | 348 | #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ |
340 | (MAX_RX_SGE_CNT - 1)) ? (x) + 3 : (x) + 1) | 349 | (MAX_RX_SGE_CNT - 1)) ? \ |
350 | (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ | ||
351 | (x) + 1) | ||
341 | #define RX_SGE(x) ((x) & MAX_RX_SGE) | 352 | #define RX_SGE(x) ((x) & MAX_RX_SGE) |
342 | 353 | ||
354 | /* | ||
355 | * Number of required SGEs is the sum of two: | ||
356 | * 1. Number of possible opened aggregations (next packet for | ||
357 | * these aggregations will probably consume SGE immidiatelly) | ||
358 | * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only | ||
359 | * after placement on BD for new TPA aggregation) | ||
360 | * | ||
361 | * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page | ||
362 | */ | ||
363 | #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ | ||
364 | (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) | ||
365 | #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ | ||
366 | MAX_RX_SGE_CNT) | ||
367 | #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ | ||
368 | NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) | ||
369 | #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) | ||
370 | |||
343 | /* Manipulate a bit vector defined as an array of u64 */ | 371 | /* Manipulate a bit vector defined as an array of u64 */ |
344 | 372 | ||
345 | /* Number of bits in one sge_mask array element */ | 373 | /* Number of bits in one sge_mask array element */ |
@@ -551,24 +579,43 @@ struct bnx2x_fastpath { | |||
551 | 579 | ||
552 | #define NUM_TX_RINGS 16 | 580 | #define NUM_TX_RINGS 16 |
553 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) | 581 | #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) |
554 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - 1) | 582 | #define NEXT_PAGE_TX_DESC_CNT 1 |
583 | #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) | ||
555 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) | 584 | #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) |
556 | #define MAX_TX_BD (NUM_TX_BD - 1) | 585 | #define MAX_TX_BD (NUM_TX_BD - 1) |
557 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) | 586 | #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) |
558 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ | 587 | #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ |
559 | (MAX_TX_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | 588 | (MAX_TX_DESC_CNT - 1)) ? \ |
589 | (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ | ||
590 | (x) + 1) | ||
560 | #define TX_BD(x) ((x) & MAX_TX_BD) | 591 | #define TX_BD(x) ((x) & MAX_TX_BD) |
561 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) | 592 | #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) |
562 | 593 | ||
563 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ | 594 | /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ |
564 | #define NUM_RX_RINGS 8 | 595 | #define NUM_RX_RINGS 8 |
565 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) | 596 | #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) |
566 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - 2) | 597 | #define NEXT_PAGE_RX_DESC_CNT 2 |
598 | #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) | ||
567 | #define RX_DESC_MASK (RX_DESC_CNT - 1) | 599 | #define RX_DESC_MASK (RX_DESC_CNT - 1) |
568 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) | 600 | #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) |
569 | #define MAX_RX_BD (NUM_RX_BD - 1) | 601 | #define MAX_RX_BD (NUM_RX_BD - 1) |
570 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) | 602 | #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) |
571 | #define MIN_RX_AVAIL 128 | 603 | |
604 | /* dropless fc calculations for BDs | ||
605 | * | ||
606 | * Number of BDs should as number of buffers in BRB: | ||
607 | * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT | ||
608 | * "next" elements on each page | ||
609 | */ | ||
610 | #define NUM_BD_REQ BRB_SIZE(bp) | ||
611 | #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ | ||
612 | MAX_RX_DESC_CNT) | ||
613 | #define BD_TH_LO(bp) (NUM_BD_REQ + \ | ||
614 | NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ | ||
615 | FW_DROP_LEVEL(bp)) | ||
616 | #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) | ||
617 | |||
618 | #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) | ||
572 | 619 | ||
573 | #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ | 620 | #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ |
574 | ETH_MIN_RX_CQES_WITH_TPA_E1 : \ | 621 | ETH_MIN_RX_CQES_WITH_TPA_E1 : \ |
@@ -579,7 +626,9 @@ struct bnx2x_fastpath { | |||
579 | MIN_RX_AVAIL)) | 626 | MIN_RX_AVAIL)) |
580 | 627 | ||
581 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ | 628 | #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ |
582 | (MAX_RX_DESC_CNT - 1)) ? (x) + 3 : (x) + 1) | 629 | (MAX_RX_DESC_CNT - 1)) ? \ |
630 | (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ | ||
631 | (x) + 1) | ||
583 | #define RX_BD(x) ((x) & MAX_RX_BD) | 632 | #define RX_BD(x) ((x) & MAX_RX_BD) |
584 | 633 | ||
585 | /* | 634 | /* |
@@ -589,14 +638,31 @@ struct bnx2x_fastpath { | |||
589 | #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) | 638 | #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) |
590 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) | 639 | #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) |
591 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) | 640 | #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) |
592 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - 1) | 641 | #define NEXT_PAGE_RCQ_DESC_CNT 1 |
642 | #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) | ||
593 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) | 643 | #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) |
594 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) | 644 | #define MAX_RCQ_BD (NUM_RCQ_BD - 1) |
595 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) | 645 | #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) |
596 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ | 646 | #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ |
597 | (MAX_RCQ_DESC_CNT - 1)) ? (x) + 2 : (x) + 1) | 647 | (MAX_RCQ_DESC_CNT - 1)) ? \ |
648 | (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ | ||
649 | (x) + 1) | ||
598 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) | 650 | #define RCQ_BD(x) ((x) & MAX_RCQ_BD) |
599 | 651 | ||
652 | /* dropless fc calculations for RCQs | ||
653 | * | ||
654 | * Number of RCQs should be as number of buffers in BRB: | ||
655 | * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT | ||
656 | * "next" elements on each page | ||
657 | */ | ||
658 | #define NUM_RCQ_REQ BRB_SIZE(bp) | ||
659 | #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ | ||
660 | MAX_RCQ_DESC_CNT) | ||
661 | #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ | ||
662 | NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ | ||
663 | FW_DROP_LEVEL(bp)) | ||
664 | #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) | ||
665 | |||
600 | 666 | ||
601 | /* This is needed for determining of last_max */ | 667 | /* This is needed for determining of last_max */ |
602 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) | 668 | #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) |
@@ -685,24 +751,17 @@ struct bnx2x_fastpath { | |||
685 | #define FP_CSB_FUNC_OFF \ | 751 | #define FP_CSB_FUNC_OFF \ |
686 | offsetof(struct cstorm_status_block_c, func) | 752 | offsetof(struct cstorm_status_block_c, func) |
687 | 753 | ||
688 | #define HC_INDEX_TOE_RX_CQ_CONS 0 /* Formerly Ustorm TOE CQ index */ | 754 | #define HC_INDEX_ETH_RX_CQ_CONS 1 |
689 | /* (HC_INDEX_U_TOE_RX_CQ_CONS) */ | ||
690 | #define HC_INDEX_ETH_RX_CQ_CONS 1 /* Formerly Ustorm ETH CQ index */ | ||
691 | /* (HC_INDEX_U_ETH_RX_CQ_CONS) */ | ||
692 | #define HC_INDEX_ETH_RX_BD_CONS 2 /* Formerly Ustorm ETH BD index */ | ||
693 | /* (HC_INDEX_U_ETH_RX_BD_CONS) */ | ||
694 | |||
695 | #define HC_INDEX_TOE_TX_CQ_CONS 4 /* Formerly Cstorm TOE CQ index */ | ||
696 | /* (HC_INDEX_C_TOE_TX_CQ_CONS) */ | ||
697 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 /* Formerly Cstorm ETH CQ index */ | ||
698 | /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ | ||
699 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 /* Formerly Cstorm ETH CQ index */ | ||
700 | /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ | ||
701 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 /* Formerly Cstorm ETH CQ index */ | ||
702 | /* (HC_INDEX_C_ETH_TX_CQ_CONS) */ | ||
703 | 755 | ||
704 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 | 756 | #define HC_INDEX_OOO_TX_CQ_CONS 4 |
705 | 757 | ||
758 | #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 | ||
759 | |||
760 | #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 | ||
761 | |||
762 | #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 | ||
763 | |||
764 | #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 | ||
706 | 765 | ||
707 | #define BNX2X_RX_SB_INDEX \ | 766 | #define BNX2X_RX_SB_INDEX \ |
708 | (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) | 767 | (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) |
@@ -1100,11 +1159,12 @@ struct bnx2x { | |||
1100 | #define BP_PORT(bp) (bp->pfid & 1) | 1159 | #define BP_PORT(bp) (bp->pfid & 1) |
1101 | #define BP_FUNC(bp) (bp->pfid) | 1160 | #define BP_FUNC(bp) (bp->pfid) |
1102 | #define BP_ABS_FUNC(bp) (bp->pf_num) | 1161 | #define BP_ABS_FUNC(bp) (bp->pf_num) |
1103 | #define BP_E1HVN(bp) (bp->pfid >> 1) | 1162 | #define BP_VN(bp) ((bp)->pfid >> 1) |
1104 | #define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/ | 1163 | #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) |
1105 | #define BP_L_ID(bp) (BP_E1HVN(bp) << 2) | 1164 | #define BP_L_ID(bp) (BP_VN(bp) << 2) |
1106 | #define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ | 1165 | #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ |
1107 | BP_VN(bp) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) | 1166 | (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) |
1167 | #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) | ||
1108 | 1168 | ||
1109 | struct net_device *dev; | 1169 | struct net_device *dev; |
1110 | struct pci_dev *pdev; | 1170 | struct pci_dev *pdev; |
@@ -1767,7 +1827,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, | |||
1767 | 1827 | ||
1768 | #define MAX_DMAE_C_PER_PORT 8 | 1828 | #define MAX_DMAE_C_PER_PORT 8 |
1769 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ | 1829 | #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
1770 | BP_E1HVN(bp)) | 1830 | BP_VN(bp)) |
1771 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ | 1831 | #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ |
1772 | E1HVN_MAX) | 1832 | E1HVN_MAX) |
1773 | 1833 | ||
@@ -1793,7 +1853,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, | |||
1793 | 1853 | ||
1794 | /* must be used on a CID before placing it on a HW ring */ | 1854 | /* must be used on a CID before placing it on a HW ring */ |
1795 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ | 1855 | #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ |
1796 | (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \ | 1856 | (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ |
1797 | (x)) | 1857 | (x)) |
1798 | 1858 | ||
1799 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) | 1859 | #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) |
diff --git a/drivers/net/bnx2x/bnx2x_cmn.c b/drivers/net/bnx2x/bnx2x_cmn.c index 37e5790681ad..c4cbf9736414 100644 --- a/drivers/net/bnx2x/bnx2x_cmn.c +++ b/drivers/net/bnx2x/bnx2x_cmn.c | |||
@@ -987,8 +987,6 @@ void __bnx2x_link_report(struct bnx2x *bp) | |||
987 | void bnx2x_init_rx_rings(struct bnx2x *bp) | 987 | void bnx2x_init_rx_rings(struct bnx2x *bp) |
988 | { | 988 | { |
989 | int func = BP_FUNC(bp); | 989 | int func = BP_FUNC(bp); |
990 | int max_agg_queues = CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 : | ||
991 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2; | ||
992 | u16 ring_prod; | 990 | u16 ring_prod; |
993 | int i, j; | 991 | int i, j; |
994 | 992 | ||
@@ -1001,7 +999,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp) | |||
1001 | 999 | ||
1002 | if (!fp->disable_tpa) { | 1000 | if (!fp->disable_tpa) { |
1003 | /* Fill the per-aggregtion pool */ | 1001 | /* Fill the per-aggregtion pool */ |
1004 | for (i = 0; i < max_agg_queues; i++) { | 1002 | for (i = 0; i < MAX_AGG_QS(bp); i++) { |
1005 | struct bnx2x_agg_info *tpa_info = | 1003 | struct bnx2x_agg_info *tpa_info = |
1006 | &fp->tpa_info[i]; | 1004 | &fp->tpa_info[i]; |
1007 | struct sw_rx_bd *first_buf = | 1005 | struct sw_rx_bd *first_buf = |
@@ -1041,7 +1039,7 @@ void bnx2x_init_rx_rings(struct bnx2x *bp) | |||
1041 | bnx2x_free_rx_sge_range(bp, fp, | 1039 | bnx2x_free_rx_sge_range(bp, fp, |
1042 | ring_prod); | 1040 | ring_prod); |
1043 | bnx2x_free_tpa_pool(bp, fp, | 1041 | bnx2x_free_tpa_pool(bp, fp, |
1044 | max_agg_queues); | 1042 | MAX_AGG_QS(bp)); |
1045 | fp->disable_tpa = 1; | 1043 | fp->disable_tpa = 1; |
1046 | ring_prod = 0; | 1044 | ring_prod = 0; |
1047 | break; | 1045 | break; |
@@ -1137,9 +1135,7 @@ static void bnx2x_free_rx_skbs(struct bnx2x *bp) | |||
1137 | bnx2x_free_rx_bds(fp); | 1135 | bnx2x_free_rx_bds(fp); |
1138 | 1136 | ||
1139 | if (!fp->disable_tpa) | 1137 | if (!fp->disable_tpa) |
1140 | bnx2x_free_tpa_pool(bp, fp, CHIP_IS_E1(bp) ? | 1138 | bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp)); |
1141 | ETH_MAX_AGGREGATION_QUEUES_E1 : | ||
1142 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2); | ||
1143 | } | 1139 | } |
1144 | } | 1140 | } |
1145 | 1141 | ||
@@ -3095,15 +3091,20 @@ static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index) | |||
3095 | struct bnx2x_fastpath *fp = &bp->fp[index]; | 3091 | struct bnx2x_fastpath *fp = &bp->fp[index]; |
3096 | int ring_size = 0; | 3092 | int ring_size = 0; |
3097 | u8 cos; | 3093 | u8 cos; |
3094 | int rx_ring_size = 0; | ||
3098 | 3095 | ||
3099 | /* if rx_ring_size specified - use it */ | 3096 | /* if rx_ring_size specified - use it */ |
3100 | int rx_ring_size = bp->rx_ring_size ? bp->rx_ring_size : | 3097 | if (!bp->rx_ring_size) { |
3101 | MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp); | ||
3102 | 3098 | ||
3103 | /* allocate at least number of buffers required by FW */ | 3099 | rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp); |
3104 | rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA : | 3100 | |
3105 | MIN_RX_SIZE_TPA, | 3101 | /* allocate at least number of buffers required by FW */ |
3106 | rx_ring_size); | 3102 | rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA : |
3103 | MIN_RX_SIZE_TPA, rx_ring_size); | ||
3104 | |||
3105 | bp->rx_ring_size = rx_ring_size; | ||
3106 | } else | ||
3107 | rx_ring_size = bp->rx_ring_size; | ||
3107 | 3108 | ||
3108 | /* Common */ | 3109 | /* Common */ |
3109 | sb = &bnx2x_fp(bp, index, status_blk); | 3110 | sb = &bnx2x_fp(bp, index, status_blk); |
diff --git a/drivers/net/bnx2x/bnx2x_ethtool.c b/drivers/net/bnx2x/bnx2x_ethtool.c index 221863059dae..cf3e47914dd7 100644 --- a/drivers/net/bnx2x/bnx2x_ethtool.c +++ b/drivers/net/bnx2x/bnx2x_ethtool.c | |||
@@ -363,13 +363,50 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
363 | } | 363 | } |
364 | 364 | ||
365 | /* advertise the requested speed and duplex if supported */ | 365 | /* advertise the requested speed and duplex if supported */ |
366 | cmd->advertising &= bp->port.supported[cfg_idx]; | 366 | if (cmd->advertising & ~(bp->port.supported[cfg_idx])) { |
367 | DP(NETIF_MSG_LINK, "Advertisement parameters " | ||
368 | "are not supported\n"); | ||
369 | return -EINVAL; | ||
370 | } | ||
367 | 371 | ||
368 | bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; | 372 | bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG; |
369 | bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL; | 373 | bp->link_params.req_duplex[cfg_idx] = cmd->duplex; |
370 | bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg | | 374 | bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg | |
371 | cmd->advertising); | 375 | cmd->advertising); |
376 | if (cmd->advertising) { | ||
377 | |||
378 | bp->link_params.speed_cap_mask[cfg_idx] = 0; | ||
379 | if (cmd->advertising & ADVERTISED_10baseT_Half) { | ||
380 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
381 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF; | ||
382 | } | ||
383 | if (cmd->advertising & ADVERTISED_10baseT_Full) | ||
384 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
385 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL; | ||
372 | 386 | ||
387 | if (cmd->advertising & ADVERTISED_100baseT_Full) | ||
388 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
389 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL; | ||
390 | |||
391 | if (cmd->advertising & ADVERTISED_100baseT_Half) { | ||
392 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
393 | PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF; | ||
394 | } | ||
395 | if (cmd->advertising & ADVERTISED_1000baseT_Half) { | ||
396 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
397 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; | ||
398 | } | ||
399 | if (cmd->advertising & (ADVERTISED_1000baseT_Full | | ||
400 | ADVERTISED_1000baseKX_Full)) | ||
401 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
402 | PORT_HW_CFG_SPEED_CAPABILITY_D0_1G; | ||
403 | |||
404 | if (cmd->advertising & (ADVERTISED_10000baseT_Full | | ||
405 | ADVERTISED_10000baseKX4_Full | | ||
406 | ADVERTISED_10000baseKR_Full)) | ||
407 | bp->link_params.speed_cap_mask[cfg_idx] |= | ||
408 | PORT_HW_CFG_SPEED_CAPABILITY_D0_10G; | ||
409 | } | ||
373 | } else { /* forced speed */ | 410 | } else { /* forced speed */ |
374 | /* advertise the requested speed and duplex if supported */ | 411 | /* advertise the requested speed and duplex if supported */ |
375 | switch (speed) { | 412 | switch (speed) { |
@@ -1310,10 +1347,7 @@ static void bnx2x_get_ringparam(struct net_device *dev, | |||
1310 | if (bp->rx_ring_size) | 1347 | if (bp->rx_ring_size) |
1311 | ering->rx_pending = bp->rx_ring_size; | 1348 | ering->rx_pending = bp->rx_ring_size; |
1312 | else | 1349 | else |
1313 | if (bp->state == BNX2X_STATE_OPEN && bp->num_queues) | 1350 | ering->rx_pending = MAX_RX_AVAIL; |
1314 | ering->rx_pending = MAX_RX_AVAIL/bp->num_queues; | ||
1315 | else | ||
1316 | ering->rx_pending = MAX_RX_AVAIL; | ||
1317 | 1351 | ||
1318 | ering->rx_mini_pending = 0; | 1352 | ering->rx_mini_pending = 0; |
1319 | ering->rx_jumbo_pending = 0; | 1353 | ering->rx_jumbo_pending = 0; |
diff --git a/drivers/net/bnx2x/bnx2x_link.c b/drivers/net/bnx2x/bnx2x_link.c index d45b1555a602..ba15bdc5a1a9 100644 --- a/drivers/net/bnx2x/bnx2x_link.c +++ b/drivers/net/bnx2x/bnx2x_link.c | |||
@@ -778,9 +778,9 @@ static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, | |||
778 | { | 778 | { |
779 | u32 nig_reg_adress_crd_weight = 0; | 779 | u32 nig_reg_adress_crd_weight = 0; |
780 | u32 pbf_reg_adress_crd_weight = 0; | 780 | u32 pbf_reg_adress_crd_weight = 0; |
781 | /* Calculate and set BW for this COS*/ | 781 | /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ |
782 | const u32 cos_bw_nig = (bw * min_w_val_nig) / total_bw; | 782 | const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; |
783 | const u32 cos_bw_pbf = (bw * min_w_val_pbf) / total_bw; | 783 | const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; |
784 | 784 | ||
785 | switch (cos_entry) { | 785 | switch (cos_entry) { |
786 | case 0: | 786 | case 0: |
@@ -852,18 +852,12 @@ static int bnx2x_ets_e3b0_get_total_bw( | |||
852 | /* Calculate total BW requested */ | 852 | /* Calculate total BW requested */ |
853 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { | 853 | for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { |
854 | if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) { | 854 | if (bnx2x_cos_state_bw == ets_params->cos[cos_idx].state) { |
855 | 855 | *total_bw += | |
856 | if (0 == ets_params->cos[cos_idx].params.bw_params.bw) { | 856 | ets_params->cos[cos_idx].params.bw_params.bw; |
857 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" | ||
858 | "was set to 0\n"); | ||
859 | return -EINVAL; | ||
860 | } | 857 | } |
861 | *total_bw += | ||
862 | ets_params->cos[cos_idx].params.bw_params.bw; | ||
863 | } | ||
864 | } | 858 | } |
865 | 859 | ||
866 | /*Check taotl BW is valid */ | 860 | /* Check total BW is valid */ |
867 | if ((100 != *total_bw) || (0 == *total_bw)) { | 861 | if ((100 != *total_bw) || (0 == *total_bw)) { |
868 | if (0 == *total_bw) { | 862 | if (0 == *total_bw) { |
869 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW" | 863 | DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config toatl BW" |
@@ -1726,7 +1720,7 @@ static int bnx2x_xmac_enable(struct link_params *params, | |||
1726 | 1720 | ||
1727 | /* Check loopback mode */ | 1721 | /* Check loopback mode */ |
1728 | if (lb) | 1722 | if (lb) |
1729 | val |= XMAC_CTRL_REG_CORE_LOCAL_LPBK; | 1723 | val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; |
1730 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); | 1724 | REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); |
1731 | bnx2x_set_xumac_nig(params, | 1725 | bnx2x_set_xumac_nig(params, |
1732 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); | 1726 | ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); |
@@ -3630,6 +3624,12 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy, | |||
3630 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | 3624 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, |
3631 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); | 3625 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, val16); |
3632 | 3626 | ||
3627 | /* Advertised and set FEC (Forward Error Correction) */ | ||
3628 | bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, | ||
3629 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, | ||
3630 | (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | | ||
3631 | MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); | ||
3632 | |||
3633 | /* Enable CL37 BAM */ | 3633 | /* Enable CL37 BAM */ |
3634 | if (REG_RD(bp, params->shmem_base + | 3634 | if (REG_RD(bp, params->shmem_base + |
3635 | offsetof(struct shmem_region, dev_info. | 3635 | offsetof(struct shmem_region, dev_info. |
@@ -5924,7 +5924,7 @@ int bnx2x_set_led(struct link_params *params, | |||
5924 | (tmp | EMAC_LED_OVERRIDE)); | 5924 | (tmp | EMAC_LED_OVERRIDE)); |
5925 | /* | 5925 | /* |
5926 | * return here without enabling traffic | 5926 | * return here without enabling traffic |
5927 | * LED blink andsetting rate in ON mode. | 5927 | * LED blink and setting rate in ON mode. |
5928 | * In oper mode, enabling LED blink | 5928 | * In oper mode, enabling LED blink |
5929 | * and setting rate is needed. | 5929 | * and setting rate is needed. |
5930 | */ | 5930 | */ |
@@ -5936,7 +5936,11 @@ int bnx2x_set_led(struct link_params *params, | |||
5936 | * This is a work-around for HW issue found when link | 5936 | * This is a work-around for HW issue found when link |
5937 | * is up in CL73 | 5937 | * is up in CL73 |
5938 | */ | 5938 | */ |
5939 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | 5939 | if ((!CHIP_IS_E3(bp)) || |
5940 | (CHIP_IS_E3(bp) && | ||
5941 | mode == LED_MODE_ON)) | ||
5942 | REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); | ||
5943 | |||
5940 | if (CHIP_IS_E1x(bp) || | 5944 | if (CHIP_IS_E1x(bp) || |
5941 | CHIP_IS_E2(bp) || | 5945 | CHIP_IS_E2(bp) || |
5942 | (mode == LED_MODE_ON)) | 5946 | (mode == LED_MODE_ON)) |
@@ -10638,8 +10642,7 @@ static struct bnx2x_phy phy_warpcore = { | |||
10638 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, | 10642 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, |
10639 | .addr = 0xff, | 10643 | .addr = 0xff, |
10640 | .def_md_devad = 0, | 10644 | .def_md_devad = 0, |
10641 | .flags = (FLAGS_HW_LOCK_REQUIRED | | 10645 | .flags = FLAGS_HW_LOCK_REQUIRED, |
10642 | FLAGS_TX_ERROR_CHECK), | ||
10643 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10646 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10644 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10647 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10645 | .mdio_ctrl = 0, | 10648 | .mdio_ctrl = 0, |
@@ -10765,8 +10768,7 @@ static struct bnx2x_phy phy_8706 = { | |||
10765 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, | 10768 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, |
10766 | .addr = 0xff, | 10769 | .addr = 0xff, |
10767 | .def_md_devad = 0, | 10770 | .def_md_devad = 0, |
10768 | .flags = (FLAGS_INIT_XGXS_FIRST | | 10771 | .flags = FLAGS_INIT_XGXS_FIRST, |
10769 | FLAGS_TX_ERROR_CHECK), | ||
10770 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10772 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10771 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10773 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10772 | .mdio_ctrl = 0, | 10774 | .mdio_ctrl = 0, |
@@ -10797,8 +10799,7 @@ static struct bnx2x_phy phy_8726 = { | |||
10797 | .addr = 0xff, | 10799 | .addr = 0xff, |
10798 | .def_md_devad = 0, | 10800 | .def_md_devad = 0, |
10799 | .flags = (FLAGS_HW_LOCK_REQUIRED | | 10801 | .flags = (FLAGS_HW_LOCK_REQUIRED | |
10800 | FLAGS_INIT_XGXS_FIRST | | 10802 | FLAGS_INIT_XGXS_FIRST), |
10801 | FLAGS_TX_ERROR_CHECK), | ||
10802 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10803 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10803 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10804 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10804 | .mdio_ctrl = 0, | 10805 | .mdio_ctrl = 0, |
@@ -10829,8 +10830,7 @@ static struct bnx2x_phy phy_8727 = { | |||
10829 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, | 10830 | .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, |
10830 | .addr = 0xff, | 10831 | .addr = 0xff, |
10831 | .def_md_devad = 0, | 10832 | .def_md_devad = 0, |
10832 | .flags = (FLAGS_FAN_FAILURE_DET_REQ | | 10833 | .flags = FLAGS_FAN_FAILURE_DET_REQ, |
10833 | FLAGS_TX_ERROR_CHECK), | ||
10834 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10834 | .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10835 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, | 10835 | .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, |
10836 | .mdio_ctrl = 0, | 10836 | .mdio_ctrl = 0, |
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c index f74582a22c68..c027e9341a1a 100644 --- a/drivers/net/bnx2x/bnx2x_main.c +++ b/drivers/net/bnx2x/bnx2x_main.c | |||
@@ -407,8 +407,8 @@ u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, | |||
407 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); | 407 | opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); |
408 | 408 | ||
409 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); | 409 | opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); |
410 | opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) | | 410 | opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | |
411 | (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); | 411 | (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); |
412 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); | 412 | opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); |
413 | 413 | ||
414 | #ifdef __BIG_ENDIAN | 414 | #ifdef __BIG_ENDIAN |
@@ -1419,7 +1419,7 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp) | |||
1419 | if (!CHIP_IS_E1(bp)) { | 1419 | if (!CHIP_IS_E1(bp)) { |
1420 | /* init leading/trailing edge */ | 1420 | /* init leading/trailing edge */ |
1421 | if (IS_MF(bp)) { | 1421 | if (IS_MF(bp)) { |
1422 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); | 1422 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
1423 | if (bp->port.pmf) | 1423 | if (bp->port.pmf) |
1424 | /* enable nig and gpio3 attention */ | 1424 | /* enable nig and gpio3 attention */ |
1425 | val |= 0x1100; | 1425 | val |= 0x1100; |
@@ -1471,7 +1471,7 @@ static void bnx2x_igu_int_enable(struct bnx2x *bp) | |||
1471 | 1471 | ||
1472 | /* init leading/trailing edge */ | 1472 | /* init leading/trailing edge */ |
1473 | if (IS_MF(bp)) { | 1473 | if (IS_MF(bp)) { |
1474 | val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); | 1474 | val = (0xee0f | (1 << (BP_VN(bp) + 4))); |
1475 | if (bp->port.pmf) | 1475 | if (bp->port.pmf) |
1476 | /* enable nig and gpio3 attention */ | 1476 | /* enable nig and gpio3 attention */ |
1477 | val |= 0x1100; | 1477 | val |= 0x1100; |
@@ -2287,7 +2287,7 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) | |||
2287 | int vn; | 2287 | int vn; |
2288 | 2288 | ||
2289 | bp->vn_weight_sum = 0; | 2289 | bp->vn_weight_sum = 0; |
2290 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | 2290 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
2291 | u32 vn_cfg = bp->mf_config[vn]; | 2291 | u32 vn_cfg = bp->mf_config[vn]; |
2292 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> | 2292 | u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> |
2293 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; | 2293 | FUNC_MF_CFG_MIN_BW_SHIFT) * 100; |
@@ -2320,12 +2320,18 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp) | |||
2320 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; | 2320 | CMNG_FLAGS_PER_PORT_FAIRNESS_VN; |
2321 | } | 2321 | } |
2322 | 2322 | ||
2323 | /* returns func by VN for current port */ | ||
2324 | static inline int func_by_vn(struct bnx2x *bp, int vn) | ||
2325 | { | ||
2326 | return 2 * vn + BP_PORT(bp); | ||
2327 | } | ||
2328 | |||
2323 | static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) | 2329 | static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) |
2324 | { | 2330 | { |
2325 | struct rate_shaping_vars_per_vn m_rs_vn; | 2331 | struct rate_shaping_vars_per_vn m_rs_vn; |
2326 | struct fairness_vars_per_vn m_fair_vn; | 2332 | struct fairness_vars_per_vn m_fair_vn; |
2327 | u32 vn_cfg = bp->mf_config[vn]; | 2333 | u32 vn_cfg = bp->mf_config[vn]; |
2328 | int func = 2*vn + BP_PORT(bp); | 2334 | int func = func_by_vn(bp, vn); |
2329 | u16 vn_min_rate, vn_max_rate; | 2335 | u16 vn_min_rate, vn_max_rate; |
2330 | int i; | 2336 | int i; |
2331 | 2337 | ||
@@ -2422,7 +2428,7 @@ void bnx2x_read_mf_cfg(struct bnx2x *bp) | |||
2422 | * | 2428 | * |
2423 | * and there are 2 functions per port | 2429 | * and there are 2 functions per port |
2424 | */ | 2430 | */ |
2425 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | 2431 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
2426 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); | 2432 | int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); |
2427 | 2433 | ||
2428 | if (func >= E1H_FUNC_MAX) | 2434 | if (func >= E1H_FUNC_MAX) |
@@ -2454,7 +2460,7 @@ static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |||
2454 | 2460 | ||
2455 | /* calculate and set min-max rate for each vn */ | 2461 | /* calculate and set min-max rate for each vn */ |
2456 | if (bp->port.pmf) | 2462 | if (bp->port.pmf) |
2457 | for (vn = VN_0; vn < E1HVN_MAX; vn++) | 2463 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) |
2458 | bnx2x_init_vn_minmax(bp, vn); | 2464 | bnx2x_init_vn_minmax(bp, vn); |
2459 | 2465 | ||
2460 | /* always enable rate shaping and fairness */ | 2466 | /* always enable rate shaping and fairness */ |
@@ -2473,16 +2479,15 @@ static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) | |||
2473 | 2479 | ||
2474 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) | 2480 | static inline void bnx2x_link_sync_notify(struct bnx2x *bp) |
2475 | { | 2481 | { |
2476 | int port = BP_PORT(bp); | ||
2477 | int func; | 2482 | int func; |
2478 | int vn; | 2483 | int vn; |
2479 | 2484 | ||
2480 | /* Set the attention towards other drivers on the same port */ | 2485 | /* Set the attention towards other drivers on the same port */ |
2481 | for (vn = VN_0; vn < E1HVN_MAX; vn++) { | 2486 | for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { |
2482 | if (vn == BP_E1HVN(bp)) | 2487 | if (vn == BP_VN(bp)) |
2483 | continue; | 2488 | continue; |
2484 | 2489 | ||
2485 | func = ((vn << 1) | port); | 2490 | func = func_by_vn(bp, vn); |
2486 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + | 2491 | REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + |
2487 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); | 2492 | (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); |
2488 | } | 2493 | } |
@@ -2577,7 +2582,7 @@ static void bnx2x_pmf_update(struct bnx2x *bp) | |||
2577 | bnx2x_dcbx_pmf_update(bp); | 2582 | bnx2x_dcbx_pmf_update(bp); |
2578 | 2583 | ||
2579 | /* enable nig attention */ | 2584 | /* enable nig attention */ |
2580 | val = (0xff0f | (1 << (BP_E1HVN(bp) + 4))); | 2585 | val = (0xff0f | (1 << (BP_VN(bp) + 4))); |
2581 | if (bp->common.int_block == INT_BLOCK_HC) { | 2586 | if (bp->common.int_block == INT_BLOCK_HC) { |
2582 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); | 2587 | REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); |
2583 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); | 2588 | REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); |
@@ -2756,8 +2761,14 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |||
2756 | u16 tpa_agg_size = 0; | 2761 | u16 tpa_agg_size = 0; |
2757 | 2762 | ||
2758 | if (!fp->disable_tpa) { | 2763 | if (!fp->disable_tpa) { |
2759 | pause->sge_th_hi = 250; | 2764 | pause->sge_th_lo = SGE_TH_LO(bp); |
2760 | pause->sge_th_lo = 150; | 2765 | pause->sge_th_hi = SGE_TH_HI(bp); |
2766 | |||
2767 | /* validate SGE ring has enough to cross high threshold */ | ||
2768 | WARN_ON(bp->dropless_fc && | ||
2769 | pause->sge_th_hi + FW_PREFETCH_CNT > | ||
2770 | MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES); | ||
2771 | |||
2761 | tpa_agg_size = min_t(u32, | 2772 | tpa_agg_size = min_t(u32, |
2762 | (min_t(u32, 8, MAX_SKB_FRAGS) * | 2773 | (min_t(u32, 8, MAX_SKB_FRAGS) * |
2763 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); | 2774 | SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff); |
@@ -2771,10 +2782,21 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |||
2771 | 2782 | ||
2772 | /* pause - not for e1 */ | 2783 | /* pause - not for e1 */ |
2773 | if (!CHIP_IS_E1(bp)) { | 2784 | if (!CHIP_IS_E1(bp)) { |
2774 | pause->bd_th_hi = 350; | 2785 | pause->bd_th_lo = BD_TH_LO(bp); |
2775 | pause->bd_th_lo = 250; | 2786 | pause->bd_th_hi = BD_TH_HI(bp); |
2776 | pause->rcq_th_hi = 350; | 2787 | |
2777 | pause->rcq_th_lo = 250; | 2788 | pause->rcq_th_lo = RCQ_TH_LO(bp); |
2789 | pause->rcq_th_hi = RCQ_TH_HI(bp); | ||
2790 | /* | ||
2791 | * validate that rings have enough entries to cross | ||
2792 | * high thresholds | ||
2793 | */ | ||
2794 | WARN_ON(bp->dropless_fc && | ||
2795 | pause->bd_th_hi + FW_PREFETCH_CNT > | ||
2796 | bp->rx_ring_size); | ||
2797 | WARN_ON(bp->dropless_fc && | ||
2798 | pause->rcq_th_hi + FW_PREFETCH_CNT > | ||
2799 | NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT); | ||
2778 | 2800 | ||
2779 | pause->pri_map = 1; | 2801 | pause->pri_map = 1; |
2780 | } | 2802 | } |
@@ -2802,9 +2824,7 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, | |||
2802 | * For PF Clients it should be the maximum avaliable number. | 2824 | * For PF Clients it should be the maximum avaliable number. |
2803 | * VF driver(s) may want to define it to a smaller value. | 2825 | * VF driver(s) may want to define it to a smaller value. |
2804 | */ | 2826 | */ |
2805 | rxq_init->max_tpa_queues = | 2827 | rxq_init->max_tpa_queues = MAX_AGG_QS(bp); |
2806 | (CHIP_IS_E1(bp) ? ETH_MAX_AGGREGATION_QUEUES_E1 : | ||
2807 | ETH_MAX_AGGREGATION_QUEUES_E1H_E2); | ||
2808 | 2828 | ||
2809 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; | 2829 | rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT; |
2810 | rxq_init->fw_sb_id = fp->fw_sb_id; | 2830 | rxq_init->fw_sb_id = fp->fw_sb_id; |
@@ -4808,6 +4828,37 @@ void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, | |||
4808 | hc_sm->time_to_expire = 0xFFFFFFFF; | 4828 | hc_sm->time_to_expire = 0xFFFFFFFF; |
4809 | } | 4829 | } |
4810 | 4830 | ||
4831 | |||
4832 | /* allocates state machine ids. */ | ||
4833 | static inline | ||
4834 | void bnx2x_map_sb_state_machines(struct hc_index_data *index_data) | ||
4835 | { | ||
4836 | /* zero out state machine indices */ | ||
4837 | /* rx indices */ | ||
4838 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | ||
4839 | |||
4840 | /* tx indices */ | ||
4841 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; | ||
4842 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; | ||
4843 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; | ||
4844 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; | ||
4845 | |||
4846 | /* map indices */ | ||
4847 | /* rx indices */ | ||
4848 | index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= | ||
4849 | SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | ||
4850 | |||
4851 | /* tx indices */ | ||
4852 | index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= | ||
4853 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | ||
4854 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= | ||
4855 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | ||
4856 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= | ||
4857 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | ||
4858 | index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= | ||
4859 | SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT; | ||
4860 | } | ||
4861 | |||
4811 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, | 4862 | static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, |
4812 | u8 vf_valid, int fw_sb_id, int igu_sb_id) | 4863 | u8 vf_valid, int fw_sb_id, int igu_sb_id) |
4813 | { | 4864 | { |
@@ -4839,6 +4890,7 @@ static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, | |||
4839 | hc_sm_p = sb_data_e2.common.state_machine; | 4890 | hc_sm_p = sb_data_e2.common.state_machine; |
4840 | sb_data_p = (u32 *)&sb_data_e2; | 4891 | sb_data_p = (u32 *)&sb_data_e2; |
4841 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); | 4892 | data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32); |
4893 | bnx2x_map_sb_state_machines(sb_data_e2.index_data); | ||
4842 | } else { | 4894 | } else { |
4843 | memset(&sb_data_e1x, 0, | 4895 | memset(&sb_data_e1x, 0, |
4844 | sizeof(struct hc_status_block_data_e1x)); | 4896 | sizeof(struct hc_status_block_data_e1x)); |
@@ -4853,6 +4905,7 @@ static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, | |||
4853 | hc_sm_p = sb_data_e1x.common.state_machine; | 4905 | hc_sm_p = sb_data_e1x.common.state_machine; |
4854 | sb_data_p = (u32 *)&sb_data_e1x; | 4906 | sb_data_p = (u32 *)&sb_data_e1x; |
4855 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); | 4907 | data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32); |
4908 | bnx2x_map_sb_state_machines(sb_data_e1x.index_data); | ||
4856 | } | 4909 | } |
4857 | 4910 | ||
4858 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], | 4911 | bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], |
@@ -5802,7 +5855,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp) | |||
5802 | * take the UNDI lock to protect undi_unload flow from accessing | 5855 | * take the UNDI lock to protect undi_unload flow from accessing |
5803 | * registers while we're resetting the chip | 5856 | * registers while we're resetting the chip |
5804 | */ | 5857 | */ |
5805 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | 5858 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
5806 | 5859 | ||
5807 | bnx2x_reset_common(bp); | 5860 | bnx2x_reset_common(bp); |
5808 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); | 5861 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); |
@@ -5814,7 +5867,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp) | |||
5814 | } | 5867 | } |
5815 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); | 5868 | REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); |
5816 | 5869 | ||
5817 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | 5870 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); |
5818 | 5871 | ||
5819 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); | 5872 | bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); |
5820 | 5873 | ||
@@ -6671,12 +6724,16 @@ static int bnx2x_init_hw_func(struct bnx2x *bp) | |||
6671 | if (CHIP_MODE_IS_4_PORT(bp)) | 6724 | if (CHIP_MODE_IS_4_PORT(bp)) |
6672 | dsb_idx = BP_FUNC(bp); | 6725 | dsb_idx = BP_FUNC(bp); |
6673 | else | 6726 | else |
6674 | dsb_idx = BP_E1HVN(bp); | 6727 | dsb_idx = BP_VN(bp); |
6675 | 6728 | ||
6676 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? | 6729 | prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? |
6677 | IGU_BC_BASE_DSB_PROD + dsb_idx : | 6730 | IGU_BC_BASE_DSB_PROD + dsb_idx : |
6678 | IGU_NORM_BASE_DSB_PROD + dsb_idx); | 6731 | IGU_NORM_BASE_DSB_PROD + dsb_idx); |
6679 | 6732 | ||
6733 | /* | ||
6734 | * igu prods come in chunks of E1HVN_MAX (4) - | ||
6735 | * does not matters what is the current chip mode | ||
6736 | */ | ||
6680 | for (i = 0; i < (num_segs * E1HVN_MAX); | 6737 | for (i = 0; i < (num_segs * E1HVN_MAX); |
6681 | i += E1HVN_MAX) { | 6738 | i += E1HVN_MAX) { |
6682 | addr = IGU_REG_PROD_CONS_MEMORY + | 6739 | addr = IGU_REG_PROD_CONS_MEMORY + |
@@ -7570,7 +7627,7 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) | |||
7570 | u32 val; | 7627 | u32 val; |
7571 | /* The mac address is written to entries 1-4 to | 7628 | /* The mac address is written to entries 1-4 to |
7572 | preserve entry 0 which is used by the PMF */ | 7629 | preserve entry 0 which is used by the PMF */ |
7573 | u8 entry = (BP_E1HVN(bp) + 1)*8; | 7630 | u8 entry = (BP_VN(bp) + 1)*8; |
7574 | 7631 | ||
7575 | val = (mac_addr[0] << 8) | mac_addr[1]; | 7632 | val = (mac_addr[0] << 8) | mac_addr[1]; |
7576 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); | 7633 | EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); |
@@ -8546,10 +8603,12 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp) | |||
8546 | /* Check if there is any driver already loaded */ | 8603 | /* Check if there is any driver already loaded */ |
8547 | val = REG_RD(bp, MISC_REG_UNPREPARED); | 8604 | val = REG_RD(bp, MISC_REG_UNPREPARED); |
8548 | if (val == 0x1) { | 8605 | if (val == 0x1) { |
8549 | /* Check if it is the UNDI driver | 8606 | |
8607 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | ||
8608 | /* | ||
8609 | * Check if it is the UNDI driver | ||
8550 | * UNDI driver initializes CID offset for normal bell to 0x7 | 8610 | * UNDI driver initializes CID offset for normal bell to 0x7 |
8551 | */ | 8611 | */ |
8552 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | ||
8553 | val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); | 8612 | val = REG_RD(bp, DORQ_REG_NORM_CID_OFST); |
8554 | if (val == 0x7) { | 8613 | if (val == 0x7) { |
8555 | u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; | 8614 | u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; |
@@ -8587,9 +8646,6 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp) | |||
8587 | bnx2x_fw_command(bp, reset_code, 0); | 8646 | bnx2x_fw_command(bp, reset_code, 0); |
8588 | } | 8647 | } |
8589 | 8648 | ||
8590 | /* now it's safe to release the lock */ | ||
8591 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | ||
8592 | |||
8593 | bnx2x_undi_int_disable(bp); | 8649 | bnx2x_undi_int_disable(bp); |
8594 | port = BP_PORT(bp); | 8650 | port = BP_PORT(bp); |
8595 | 8651 | ||
@@ -8639,8 +8695,10 @@ static void __devinit bnx2x_undi_unload(struct bnx2x *bp) | |||
8639 | bp->fw_seq = | 8695 | bp->fw_seq = |
8640 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & | 8696 | (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) & |
8641 | DRV_MSG_SEQ_NUMBER_MASK); | 8697 | DRV_MSG_SEQ_NUMBER_MASK); |
8642 | } else | 8698 | } |
8643 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI); | 8699 | |
8700 | /* now it's safe to release the lock */ | ||
8701 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | ||
8644 | } | 8702 | } |
8645 | } | 8703 | } |
8646 | 8704 | ||
@@ -8777,13 +8835,13 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp) | |||
8777 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) | 8835 | static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) |
8778 | { | 8836 | { |
8779 | int pfid = BP_FUNC(bp); | 8837 | int pfid = BP_FUNC(bp); |
8780 | int vn = BP_E1HVN(bp); | ||
8781 | int igu_sb_id; | 8838 | int igu_sb_id; |
8782 | u32 val; | 8839 | u32 val; |
8783 | u8 fid, igu_sb_cnt = 0; | 8840 | u8 fid, igu_sb_cnt = 0; |
8784 | 8841 | ||
8785 | bp->igu_base_sb = 0xff; | 8842 | bp->igu_base_sb = 0xff; |
8786 | if (CHIP_INT_MODE_IS_BC(bp)) { | 8843 | if (CHIP_INT_MODE_IS_BC(bp)) { |
8844 | int vn = BP_VN(bp); | ||
8787 | igu_sb_cnt = bp->igu_sb_cnt; | 8845 | igu_sb_cnt = bp->igu_sb_cnt; |
8788 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * | 8846 | bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * |
8789 | FP_SB_MAX_E1x; | 8847 | FP_SB_MAX_E1x; |
@@ -9416,6 +9474,10 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
9416 | bp->igu_base_sb = 0; | 9474 | bp->igu_base_sb = 0; |
9417 | } else { | 9475 | } else { |
9418 | bp->common.int_block = INT_BLOCK_IGU; | 9476 | bp->common.int_block = INT_BLOCK_IGU; |
9477 | |||
9478 | /* do not allow device reset during IGU info preocessing */ | ||
9479 | bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | ||
9480 | |||
9419 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); | 9481 | val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); |
9420 | 9482 | ||
9421 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { | 9483 | if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { |
@@ -9447,6 +9509,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
9447 | 9509 | ||
9448 | bnx2x_get_igu_cam_info(bp); | 9510 | bnx2x_get_igu_cam_info(bp); |
9449 | 9511 | ||
9512 | bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); | ||
9450 | } | 9513 | } |
9451 | 9514 | ||
9452 | /* | 9515 | /* |
@@ -9473,7 +9536,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
9473 | 9536 | ||
9474 | bp->mf_ov = 0; | 9537 | bp->mf_ov = 0; |
9475 | bp->mf_mode = 0; | 9538 | bp->mf_mode = 0; |
9476 | vn = BP_E1HVN(bp); | 9539 | vn = BP_VN(bp); |
9477 | 9540 | ||
9478 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { | 9541 | if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { |
9479 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", | 9542 | BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", |
@@ -9593,13 +9656,6 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp) | |||
9593 | /* port info */ | 9656 | /* port info */ |
9594 | bnx2x_get_port_hwinfo(bp); | 9657 | bnx2x_get_port_hwinfo(bp); |
9595 | 9658 | ||
9596 | if (!BP_NOMCP(bp)) { | ||
9597 | bp->fw_seq = | ||
9598 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | ||
9599 | DRV_MSG_SEQ_NUMBER_MASK); | ||
9600 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | ||
9601 | } | ||
9602 | |||
9603 | /* Get MAC addresses */ | 9659 | /* Get MAC addresses */ |
9604 | bnx2x_get_mac_hwinfo(bp); | 9660 | bnx2x_get_mac_hwinfo(bp); |
9605 | 9661 | ||
@@ -9765,6 +9821,14 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp) | |||
9765 | if (!BP_NOMCP(bp)) | 9821 | if (!BP_NOMCP(bp)) |
9766 | bnx2x_undi_unload(bp); | 9822 | bnx2x_undi_unload(bp); |
9767 | 9823 | ||
9824 | /* init fw_seq after undi_unload! */ | ||
9825 | if (!BP_NOMCP(bp)) { | ||
9826 | bp->fw_seq = | ||
9827 | (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & | ||
9828 | DRV_MSG_SEQ_NUMBER_MASK); | ||
9829 | BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); | ||
9830 | } | ||
9831 | |||
9768 | if (CHIP_REV_IS_FPGA(bp)) | 9832 | if (CHIP_REV_IS_FPGA(bp)) |
9769 | dev_err(&bp->pdev->dev, "FPGA detected\n"); | 9833 | dev_err(&bp->pdev->dev, "FPGA detected\n"); |
9770 | 9834 | ||
@@ -10259,17 +10323,21 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev, | |||
10259 | /* clean indirect addresses */ | 10323 | /* clean indirect addresses */ |
10260 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, | 10324 | pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, |
10261 | PCICFG_VENDOR_ID_OFFSET); | 10325 | PCICFG_VENDOR_ID_OFFSET); |
10262 | /* Clean the following indirect addresses for all functions since it | 10326 | /* |
10327 | * Clean the following indirect addresses for all functions since it | ||
10263 | * is not used by the driver. | 10328 | * is not used by the driver. |
10264 | */ | 10329 | */ |
10265 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); | 10330 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); |
10266 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); | 10331 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); |
10267 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); | 10332 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); |
10268 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); | 10333 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); |
10269 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); | 10334 | |
10270 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); | 10335 | if (CHIP_IS_E1x(bp)) { |
10271 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | 10336 | REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); |
10272 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | 10337 | REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); |
10338 | REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); | ||
10339 | REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); | ||
10340 | } | ||
10273 | 10341 | ||
10274 | /* | 10342 | /* |
10275 | * Enable internal target-read (in case we are probed after PF FLR). | 10343 | * Enable internal target-read (in case we are probed after PF FLR). |
diff --git a/drivers/net/bnx2x/bnx2x_reg.h b/drivers/net/bnx2x/bnx2x_reg.h index 40266c14e6dc..750e8445dac4 100644 --- a/drivers/net/bnx2x/bnx2x_reg.h +++ b/drivers/net/bnx2x/bnx2x_reg.h | |||
@@ -5320,7 +5320,7 @@ | |||
5320 | #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 | 5320 | #define XCM_REG_XX_OVFL_EVNT_ID 0x20058 |
5321 | #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) | 5321 | #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) |
5322 | #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) | 5322 | #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) |
5323 | #define XMAC_CTRL_REG_CORE_LOCAL_LPBK (0x1<<3) | 5323 | #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2) |
5324 | #define XMAC_CTRL_REG_RX_EN (0x1<<1) | 5324 | #define XMAC_CTRL_REG_RX_EN (0x1<<1) |
5325 | #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) | 5325 | #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) |
5326 | #define XMAC_CTRL_REG_TX_EN (0x1<<0) | 5326 | #define XMAC_CTRL_REG_TX_EN (0x1<<0) |
@@ -5766,7 +5766,7 @@ | |||
5766 | #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 | 5766 | #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 |
5767 | #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 | 5767 | #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 |
5768 | #define HW_LOCK_RESOURCE_SPIO 2 | 5768 | #define HW_LOCK_RESOURCE_SPIO 2 |
5769 | #define HW_LOCK_RESOURCE_UNDI 5 | 5769 | #define HW_LOCK_RESOURCE_RESET 5 |
5770 | #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) | 5770 | #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) |
5771 | #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) | 5771 | #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) |
5772 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) | 5772 | #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) |
@@ -6853,6 +6853,9 @@ Theotherbitsarereservedandshouldbezero*/ | |||
6853 | #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 | 6853 | #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 |
6854 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 | 6854 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 |
6855 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 | 6855 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 |
6856 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 | ||
6857 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 | ||
6858 | #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 | ||
6856 | #define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96 | 6859 | #define MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150 0x96 |
6857 | #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 | 6860 | #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 |
6858 | #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e | 6861 | #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e |
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c index 771f6803b238..9908f2bbcf73 100644 --- a/drivers/net/bnx2x/bnx2x_stats.c +++ b/drivers/net/bnx2x/bnx2x_stats.c | |||
@@ -710,7 +710,8 @@ static int bnx2x_hw_stats_update(struct bnx2x *bp) | |||
710 | break; | 710 | break; |
711 | 711 | ||
712 | case MAC_TYPE_NONE: /* unreached */ | 712 | case MAC_TYPE_NONE: /* unreached */ |
713 | BNX2X_ERR("stats updated by DMAE but no MAC active\n"); | 713 | DP(BNX2X_MSG_STATS, |
714 | "stats updated by DMAE but no MAC active\n"); | ||
714 | return -1; | 715 | return -1; |
715 | 716 | ||
716 | default: /* unreached */ | 717 | default: /* unreached */ |
@@ -1391,7 +1392,7 @@ static void bnx2x_port_stats_base_init(struct bnx2x *bp) | |||
1391 | 1392 | ||
1392 | static void bnx2x_func_stats_base_init(struct bnx2x *bp) | 1393 | static void bnx2x_func_stats_base_init(struct bnx2x *bp) |
1393 | { | 1394 | { |
1394 | int vn, vn_max = IS_MF(bp) ? E1HVN_MAX : E1VN_MAX; | 1395 | int vn, vn_max = IS_MF(bp) ? BP_MAX_VN_NUM(bp) : E1VN_MAX; |
1395 | u32 func_stx; | 1396 | u32 func_stx; |
1396 | 1397 | ||
1397 | /* sanity */ | 1398 | /* sanity */ |
@@ -1404,7 +1405,7 @@ static void bnx2x_func_stats_base_init(struct bnx2x *bp) | |||
1404 | func_stx = bp->func_stx; | 1405 | func_stx = bp->func_stx; |
1405 | 1406 | ||
1406 | for (vn = VN_0; vn < vn_max; vn++) { | 1407 | for (vn = VN_0; vn < vn_max; vn++) { |
1407 | int mb_idx = CHIP_IS_E1x(bp) ? 2*vn + BP_PORT(bp) : vn; | 1408 | int mb_idx = BP_FW_MB_IDX_VN(bp, vn); |
1408 | 1409 | ||
1409 | bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param); | 1410 | bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param); |
1410 | bnx2x_func_stats_init(bp); | 1411 | bnx2x_func_stats_init(bp); |
diff --git a/drivers/net/can/ti_hecc.c b/drivers/net/can/ti_hecc.c index f7bbde9eb2cb..2adc294f512a 100644 --- a/drivers/net/can/ti_hecc.c +++ b/drivers/net/can/ti_hecc.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include <linux/skbuff.h> | 46 | #include <linux/skbuff.h> |
47 | #include <linux/platform_device.h> | 47 | #include <linux/platform_device.h> |
48 | #include <linux/clk.h> | 48 | #include <linux/clk.h> |
49 | #include <linux/io.h> | ||
49 | 50 | ||
50 | #include <linux/can/dev.h> | 51 | #include <linux/can/dev.h> |
51 | #include <linux/can/error.h> | 52 | #include <linux/can/error.h> |
@@ -503,9 +504,9 @@ static netdev_tx_t ti_hecc_xmit(struct sk_buff *skb, struct net_device *ndev) | |||
503 | spin_unlock_irqrestore(&priv->mbx_lock, flags); | 504 | spin_unlock_irqrestore(&priv->mbx_lock, flags); |
504 | 505 | ||
505 | /* Prepare mailbox for transmission */ | 506 | /* Prepare mailbox for transmission */ |
507 | data = cf->can_dlc | (get_tx_head_prio(priv) << 8); | ||
506 | if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ | 508 | if (cf->can_id & CAN_RTR_FLAG) /* Remote transmission request */ |
507 | data |= HECC_CANMCF_RTR; | 509 | data |= HECC_CANMCF_RTR; |
508 | data |= get_tx_head_prio(priv) << 8; | ||
509 | hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); | 510 | hecc_write_mbx(priv, mbxno, HECC_CANMCF, data); |
510 | 511 | ||
511 | if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ | 512 | if (cf->can_id & CAN_EFF_FLAG) /* Extended frame format */ |
@@ -923,6 +924,7 @@ static int ti_hecc_probe(struct platform_device *pdev) | |||
923 | priv->can.do_get_state = ti_hecc_get_state; | 924 | priv->can.do_get_state = ti_hecc_get_state; |
924 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; | 925 | priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; |
925 | 926 | ||
927 | spin_lock_init(&priv->mbx_lock); | ||
926 | ndev->irq = irq->start; | 928 | ndev->irq = irq->start; |
927 | ndev->flags |= IFF_ECHO; | 929 | ndev->flags |= IFF_ECHO; |
928 | platform_set_drvdata(pdev, ndev); | 930 | platform_set_drvdata(pdev, ndev); |
diff --git a/drivers/net/cassini.c b/drivers/net/cassini.c index 646c86bcc545..fdb7a1756409 100644 --- a/drivers/net/cassini.c +++ b/drivers/net/cassini.c | |||
@@ -2452,14 +2452,13 @@ static irqreturn_t cas_interruptN(int irq, void *dev_id) | |||
2452 | struct net_device *dev = dev_id; | 2452 | struct net_device *dev = dev_id; |
2453 | struct cas *cp = netdev_priv(dev); | 2453 | struct cas *cp = netdev_priv(dev); |
2454 | unsigned long flags; | 2454 | unsigned long flags; |
2455 | int ring; | 2455 | int ring = (irq == cp->pci_irq_INTC) ? 2 : 3; |
2456 | u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); | 2456 | u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); |
2457 | 2457 | ||
2458 | /* check for shared irq */ | 2458 | /* check for shared irq */ |
2459 | if (status == 0) | 2459 | if (status == 0) |
2460 | return IRQ_NONE; | 2460 | return IRQ_NONE; |
2461 | 2461 | ||
2462 | ring = (irq == cp->pci_irq_INTC) ? 2 : 3; | ||
2463 | spin_lock_irqsave(&cp->lock, flags); | 2462 | spin_lock_irqsave(&cp->lock, flags); |
2464 | if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ | 2463 | if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ |
2465 | #ifdef USE_NAPI | 2464 | #ifdef USE_NAPI |
diff --git a/drivers/net/e1000/e1000_hw.c b/drivers/net/e1000/e1000_hw.c index 8545c7aa93eb..a5a89ecb6f36 100644 --- a/drivers/net/e1000/e1000_hw.c +++ b/drivers/net/e1000/e1000_hw.c | |||
@@ -4026,6 +4026,12 @@ s32 e1000_validate_eeprom_checksum(struct e1000_hw *hw) | |||
4026 | checksum += eeprom_data; | 4026 | checksum += eeprom_data; |
4027 | } | 4027 | } |
4028 | 4028 | ||
4029 | #ifdef CONFIG_PARISC | ||
4030 | /* This is a signature and not a checksum on HP c8000 */ | ||
4031 | if ((hw->subsystem_vendor_id == 0x103C) && (eeprom_data == 0x16d6)) | ||
4032 | return E1000_SUCCESS; | ||
4033 | |||
4034 | #endif | ||
4029 | if (checksum == (u16) EEPROM_SUM) | 4035 | if (checksum == (u16) EEPROM_SUM) |
4030 | return E1000_SUCCESS; | 4036 | return E1000_SUCCESS; |
4031 | else { | 4037 | else { |
diff --git a/drivers/net/gianfar_ethtool.c b/drivers/net/gianfar_ethtool.c index 25a8c2adb001..0caf3c323ec0 100644 --- a/drivers/net/gianfar_ethtool.c +++ b/drivers/net/gianfar_ethtool.c | |||
@@ -1669,10 +1669,10 @@ static int gfar_get_cls_all(struct gfar_private *priv, | |||
1669 | u32 i = 0; | 1669 | u32 i = 0; |
1670 | 1670 | ||
1671 | list_for_each_entry(comp, &priv->rx_list.list, list) { | 1671 | list_for_each_entry(comp, &priv->rx_list.list, list) { |
1672 | if (i <= cmd->rule_cnt) { | 1672 | if (i == cmd->rule_cnt) |
1673 | rule_locs[i] = comp->fs.location; | 1673 | return -EMSGSIZE; |
1674 | i++; | 1674 | rule_locs[i] = comp->fs.location; |
1675 | } | 1675 | i++; |
1676 | } | 1676 | } |
1677 | 1677 | ||
1678 | cmd->data = MAX_FILER_IDX; | 1678 | cmd->data = MAX_FILER_IDX; |
diff --git a/drivers/net/greth.c b/drivers/net/greth.c index 16ce45c11934..52a39000c42c 100644 --- a/drivers/net/greth.c +++ b/drivers/net/greth.c | |||
@@ -428,6 +428,7 @@ greth_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
428 | dma_sync_single_for_device(greth->dev, dma_addr, skb->len, DMA_TO_DEVICE); | 428 | dma_sync_single_for_device(greth->dev, dma_addr, skb->len, DMA_TO_DEVICE); |
429 | 429 | ||
430 | status = GRETH_BD_EN | GRETH_BD_IE | (skb->len & GRETH_BD_LEN); | 430 | status = GRETH_BD_EN | GRETH_BD_IE | (skb->len & GRETH_BD_LEN); |
431 | greth->tx_bufs_length[greth->tx_next] = skb->len & GRETH_BD_LEN; | ||
431 | 432 | ||
432 | /* Wrap around descriptor ring */ | 433 | /* Wrap around descriptor ring */ |
433 | if (greth->tx_next == GRETH_TXBD_NUM_MASK) { | 434 | if (greth->tx_next == GRETH_TXBD_NUM_MASK) { |
@@ -490,7 +491,8 @@ greth_start_xmit_gbit(struct sk_buff *skb, struct net_device *dev) | |||
490 | if (nr_frags != 0) | 491 | if (nr_frags != 0) |
491 | status = GRETH_TXBD_MORE; | 492 | status = GRETH_TXBD_MORE; |
492 | 493 | ||
493 | status |= GRETH_TXBD_CSALL; | 494 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
495 | status |= GRETH_TXBD_CSALL; | ||
494 | status |= skb_headlen(skb) & GRETH_BD_LEN; | 496 | status |= skb_headlen(skb) & GRETH_BD_LEN; |
495 | if (greth->tx_next == GRETH_TXBD_NUM_MASK) | 497 | if (greth->tx_next == GRETH_TXBD_NUM_MASK) |
496 | status |= GRETH_BD_WR; | 498 | status |= GRETH_BD_WR; |
@@ -513,7 +515,9 @@ greth_start_xmit_gbit(struct sk_buff *skb, struct net_device *dev) | |||
513 | greth->tx_skbuff[curr_tx] = NULL; | 515 | greth->tx_skbuff[curr_tx] = NULL; |
514 | bdp = greth->tx_bd_base + curr_tx; | 516 | bdp = greth->tx_bd_base + curr_tx; |
515 | 517 | ||
516 | status = GRETH_TXBD_CSALL | GRETH_BD_EN; | 518 | status = GRETH_BD_EN; |
519 | if (skb->ip_summed == CHECKSUM_PARTIAL) | ||
520 | status |= GRETH_TXBD_CSALL; | ||
517 | status |= frag->size & GRETH_BD_LEN; | 521 | status |= frag->size & GRETH_BD_LEN; |
518 | 522 | ||
519 | /* Wrap around descriptor ring */ | 523 | /* Wrap around descriptor ring */ |
@@ -641,6 +645,7 @@ static void greth_clean_tx(struct net_device *dev) | |||
641 | dev->stats.tx_fifo_errors++; | 645 | dev->stats.tx_fifo_errors++; |
642 | } | 646 | } |
643 | dev->stats.tx_packets++; | 647 | dev->stats.tx_packets++; |
648 | dev->stats.tx_bytes += greth->tx_bufs_length[greth->tx_last]; | ||
644 | greth->tx_last = NEXT_TX(greth->tx_last); | 649 | greth->tx_last = NEXT_TX(greth->tx_last); |
645 | greth->tx_free++; | 650 | greth->tx_free++; |
646 | } | 651 | } |
@@ -695,6 +700,7 @@ static void greth_clean_tx_gbit(struct net_device *dev) | |||
695 | greth->tx_skbuff[greth->tx_last] = NULL; | 700 | greth->tx_skbuff[greth->tx_last] = NULL; |
696 | 701 | ||
697 | greth_update_tx_stats(dev, stat); | 702 | greth_update_tx_stats(dev, stat); |
703 | dev->stats.tx_bytes += skb->len; | ||
698 | 704 | ||
699 | bdp = greth->tx_bd_base + greth->tx_last; | 705 | bdp = greth->tx_bd_base + greth->tx_last; |
700 | 706 | ||
@@ -796,6 +802,7 @@ static int greth_rx(struct net_device *dev, int limit) | |||
796 | memcpy(skb_put(skb, pkt_len), phys_to_virt(dma_addr), pkt_len); | 802 | memcpy(skb_put(skb, pkt_len), phys_to_virt(dma_addr), pkt_len); |
797 | 803 | ||
798 | skb->protocol = eth_type_trans(skb, dev); | 804 | skb->protocol = eth_type_trans(skb, dev); |
805 | dev->stats.rx_bytes += pkt_len; | ||
799 | dev->stats.rx_packets++; | 806 | dev->stats.rx_packets++; |
800 | netif_receive_skb(skb); | 807 | netif_receive_skb(skb); |
801 | } | 808 | } |
@@ -910,6 +917,7 @@ static int greth_rx_gbit(struct net_device *dev, int limit) | |||
910 | 917 | ||
911 | skb->protocol = eth_type_trans(skb, dev); | 918 | skb->protocol = eth_type_trans(skb, dev); |
912 | dev->stats.rx_packets++; | 919 | dev->stats.rx_packets++; |
920 | dev->stats.rx_bytes += pkt_len; | ||
913 | netif_receive_skb(skb); | 921 | netif_receive_skb(skb); |
914 | 922 | ||
915 | greth->rx_skbuff[greth->rx_cur] = newskb; | 923 | greth->rx_skbuff[greth->rx_cur] = newskb; |
diff --git a/drivers/net/greth.h b/drivers/net/greth.h index 9a0040dee4da..232a622a85b7 100644 --- a/drivers/net/greth.h +++ b/drivers/net/greth.h | |||
@@ -103,6 +103,7 @@ struct greth_private { | |||
103 | 103 | ||
104 | unsigned char *tx_bufs[GRETH_TXBD_NUM]; | 104 | unsigned char *tx_bufs[GRETH_TXBD_NUM]; |
105 | unsigned char *rx_bufs[GRETH_RXBD_NUM]; | 105 | unsigned char *rx_bufs[GRETH_RXBD_NUM]; |
106 | u16 tx_bufs_length[GRETH_TXBD_NUM]; | ||
106 | 107 | ||
107 | u16 tx_next; | 108 | u16 tx_next; |
108 | u16 tx_last; | 109 | u16 tx_last; |
diff --git a/drivers/net/ibmveth.c b/drivers/net/ibmveth.c index ba99af05bf62..8dd5fccef725 100644 --- a/drivers/net/ibmveth.c +++ b/drivers/net/ibmveth.c | |||
@@ -395,7 +395,7 @@ static inline struct sk_buff *ibmveth_rxq_get_buffer(struct ibmveth_adapter *ada | |||
395 | } | 395 | } |
396 | 396 | ||
397 | /* recycle the current buffer on the rx queue */ | 397 | /* recycle the current buffer on the rx queue */ |
398 | static void ibmveth_rxq_recycle_buffer(struct ibmveth_adapter *adapter) | 398 | static int ibmveth_rxq_recycle_buffer(struct ibmveth_adapter *adapter) |
399 | { | 399 | { |
400 | u32 q_index = adapter->rx_queue.index; | 400 | u32 q_index = adapter->rx_queue.index; |
401 | u64 correlator = adapter->rx_queue.queue_addr[q_index].correlator; | 401 | u64 correlator = adapter->rx_queue.queue_addr[q_index].correlator; |
@@ -403,6 +403,7 @@ static void ibmveth_rxq_recycle_buffer(struct ibmveth_adapter *adapter) | |||
403 | unsigned int index = correlator & 0xffffffffUL; | 403 | unsigned int index = correlator & 0xffffffffUL; |
404 | union ibmveth_buf_desc desc; | 404 | union ibmveth_buf_desc desc; |
405 | unsigned long lpar_rc; | 405 | unsigned long lpar_rc; |
406 | int ret = 1; | ||
406 | 407 | ||
407 | BUG_ON(pool >= IBMVETH_NUM_BUFF_POOLS); | 408 | BUG_ON(pool >= IBMVETH_NUM_BUFF_POOLS); |
408 | BUG_ON(index >= adapter->rx_buff_pool[pool].size); | 409 | BUG_ON(index >= adapter->rx_buff_pool[pool].size); |
@@ -410,7 +411,7 @@ static void ibmveth_rxq_recycle_buffer(struct ibmveth_adapter *adapter) | |||
410 | if (!adapter->rx_buff_pool[pool].active) { | 411 | if (!adapter->rx_buff_pool[pool].active) { |
411 | ibmveth_rxq_harvest_buffer(adapter); | 412 | ibmveth_rxq_harvest_buffer(adapter); |
412 | ibmveth_free_buffer_pool(adapter, &adapter->rx_buff_pool[pool]); | 413 | ibmveth_free_buffer_pool(adapter, &adapter->rx_buff_pool[pool]); |
413 | return; | 414 | goto out; |
414 | } | 415 | } |
415 | 416 | ||
416 | desc.fields.flags_len = IBMVETH_BUF_VALID | | 417 | desc.fields.flags_len = IBMVETH_BUF_VALID | |
@@ -423,12 +424,16 @@ static void ibmveth_rxq_recycle_buffer(struct ibmveth_adapter *adapter) | |||
423 | netdev_dbg(adapter->netdev, "h_add_logical_lan_buffer failed " | 424 | netdev_dbg(adapter->netdev, "h_add_logical_lan_buffer failed " |
424 | "during recycle rc=%ld", lpar_rc); | 425 | "during recycle rc=%ld", lpar_rc); |
425 | ibmveth_remove_buffer_from_pool(adapter, adapter->rx_queue.queue_addr[adapter->rx_queue.index].correlator); | 426 | ibmveth_remove_buffer_from_pool(adapter, adapter->rx_queue.queue_addr[adapter->rx_queue.index].correlator); |
427 | ret = 0; | ||
426 | } | 428 | } |
427 | 429 | ||
428 | if (++adapter->rx_queue.index == adapter->rx_queue.num_slots) { | 430 | if (++adapter->rx_queue.index == adapter->rx_queue.num_slots) { |
429 | adapter->rx_queue.index = 0; | 431 | adapter->rx_queue.index = 0; |
430 | adapter->rx_queue.toggle = !adapter->rx_queue.toggle; | 432 | adapter->rx_queue.toggle = !adapter->rx_queue.toggle; |
431 | } | 433 | } |
434 | |||
435 | out: | ||
436 | return ret; | ||
432 | } | 437 | } |
433 | 438 | ||
434 | static void ibmveth_rxq_harvest_buffer(struct ibmveth_adapter *adapter) | 439 | static void ibmveth_rxq_harvest_buffer(struct ibmveth_adapter *adapter) |
@@ -752,7 +757,7 @@ static int ibmveth_set_csum_offload(struct net_device *dev, u32 data) | |||
752 | struct ibmveth_adapter *adapter = netdev_priv(dev); | 757 | struct ibmveth_adapter *adapter = netdev_priv(dev); |
753 | unsigned long set_attr, clr_attr, ret_attr; | 758 | unsigned long set_attr, clr_attr, ret_attr; |
754 | unsigned long set_attr6, clr_attr6; | 759 | unsigned long set_attr6, clr_attr6; |
755 | long ret, ret6; | 760 | long ret, ret4, ret6; |
756 | int rc1 = 0, rc2 = 0; | 761 | int rc1 = 0, rc2 = 0; |
757 | int restart = 0; | 762 | int restart = 0; |
758 | 763 | ||
@@ -765,6 +770,8 @@ static int ibmveth_set_csum_offload(struct net_device *dev, u32 data) | |||
765 | 770 | ||
766 | set_attr = 0; | 771 | set_attr = 0; |
767 | clr_attr = 0; | 772 | clr_attr = 0; |
773 | set_attr6 = 0; | ||
774 | clr_attr6 = 0; | ||
768 | 775 | ||
769 | if (data) { | 776 | if (data) { |
770 | set_attr = IBMVETH_ILLAN_IPV4_TCP_CSUM; | 777 | set_attr = IBMVETH_ILLAN_IPV4_TCP_CSUM; |
@@ -779,16 +786,20 @@ static int ibmveth_set_csum_offload(struct net_device *dev, u32 data) | |||
779 | if (ret == H_SUCCESS && !(ret_attr & IBMVETH_ILLAN_ACTIVE_TRUNK) && | 786 | if (ret == H_SUCCESS && !(ret_attr & IBMVETH_ILLAN_ACTIVE_TRUNK) && |
780 | !(ret_attr & IBMVETH_ILLAN_TRUNK_PRI_MASK) && | 787 | !(ret_attr & IBMVETH_ILLAN_TRUNK_PRI_MASK) && |
781 | (ret_attr & IBMVETH_ILLAN_PADDED_PKT_CSUM)) { | 788 | (ret_attr & IBMVETH_ILLAN_PADDED_PKT_CSUM)) { |
782 | ret = h_illan_attributes(adapter->vdev->unit_address, clr_attr, | 789 | ret4 = h_illan_attributes(adapter->vdev->unit_address, clr_attr, |
783 | set_attr, &ret_attr); | 790 | set_attr, &ret_attr); |
784 | 791 | ||
785 | if (ret != H_SUCCESS) { | 792 | if (ret4 != H_SUCCESS) { |
786 | netdev_err(dev, "unable to change IPv4 checksum " | 793 | netdev_err(dev, "unable to change IPv4 checksum " |
787 | "offload settings. %d rc=%ld\n", | 794 | "offload settings. %d rc=%ld\n", |
788 | data, ret); | 795 | data, ret4); |
796 | |||
797 | h_illan_attributes(adapter->vdev->unit_address, | ||
798 | set_attr, clr_attr, &ret_attr); | ||
799 | |||
800 | if (data == 1) | ||
801 | dev->features &= ~NETIF_F_IP_CSUM; | ||
789 | 802 | ||
790 | ret = h_illan_attributes(adapter->vdev->unit_address, | ||
791 | set_attr, clr_attr, &ret_attr); | ||
792 | } else { | 803 | } else { |
793 | adapter->fw_ipv4_csum_support = data; | 804 | adapter->fw_ipv4_csum_support = data; |
794 | } | 805 | } |
@@ -799,15 +810,18 @@ static int ibmveth_set_csum_offload(struct net_device *dev, u32 data) | |||
799 | if (ret6 != H_SUCCESS) { | 810 | if (ret6 != H_SUCCESS) { |
800 | netdev_err(dev, "unable to change IPv6 checksum " | 811 | netdev_err(dev, "unable to change IPv6 checksum " |
801 | "offload settings. %d rc=%ld\n", | 812 | "offload settings. %d rc=%ld\n", |
802 | data, ret); | 813 | data, ret6); |
814 | |||
815 | h_illan_attributes(adapter->vdev->unit_address, | ||
816 | set_attr6, clr_attr6, &ret_attr); | ||
817 | |||
818 | if (data == 1) | ||
819 | dev->features &= ~NETIF_F_IPV6_CSUM; | ||
803 | 820 | ||
804 | ret = h_illan_attributes(adapter->vdev->unit_address, | ||
805 | set_attr6, clr_attr6, | ||
806 | &ret_attr); | ||
807 | } else | 821 | } else |
808 | adapter->fw_ipv6_csum_support = data; | 822 | adapter->fw_ipv6_csum_support = data; |
809 | 823 | ||
810 | if (ret != H_SUCCESS || ret6 != H_SUCCESS) | 824 | if (ret4 == H_SUCCESS || ret6 == H_SUCCESS) |
811 | adapter->rx_csum = data; | 825 | adapter->rx_csum = data; |
812 | else | 826 | else |
813 | rc1 = -EIO; | 827 | rc1 = -EIO; |
@@ -925,6 +939,7 @@ static netdev_tx_t ibmveth_start_xmit(struct sk_buff *skb, | |||
925 | union ibmveth_buf_desc descs[6]; | 939 | union ibmveth_buf_desc descs[6]; |
926 | int last, i; | 940 | int last, i; |
927 | int force_bounce = 0; | 941 | int force_bounce = 0; |
942 | dma_addr_t dma_addr; | ||
928 | 943 | ||
929 | /* | 944 | /* |
930 | * veth handles a maximum of 6 segments including the header, so | 945 | * veth handles a maximum of 6 segments including the header, so |
@@ -989,17 +1004,16 @@ retry_bounce: | |||
989 | } | 1004 | } |
990 | 1005 | ||
991 | /* Map the header */ | 1006 | /* Map the header */ |
992 | descs[0].fields.address = dma_map_single(&adapter->vdev->dev, skb->data, | 1007 | dma_addr = dma_map_single(&adapter->vdev->dev, skb->data, |
993 | skb_headlen(skb), | 1008 | skb_headlen(skb), DMA_TO_DEVICE); |
994 | DMA_TO_DEVICE); | 1009 | if (dma_mapping_error(&adapter->vdev->dev, dma_addr)) |
995 | if (dma_mapping_error(&adapter->vdev->dev, descs[0].fields.address)) | ||
996 | goto map_failed; | 1010 | goto map_failed; |
997 | 1011 | ||
998 | descs[0].fields.flags_len = desc_flags | skb_headlen(skb); | 1012 | descs[0].fields.flags_len = desc_flags | skb_headlen(skb); |
1013 | descs[0].fields.address = dma_addr; | ||
999 | 1014 | ||
1000 | /* Map the frags */ | 1015 | /* Map the frags */ |
1001 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | 1016 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { |
1002 | unsigned long dma_addr; | ||
1003 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | 1017 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1004 | 1018 | ||
1005 | dma_addr = dma_map_page(&adapter->vdev->dev, frag->page, | 1019 | dma_addr = dma_map_page(&adapter->vdev->dev, frag->page, |
@@ -1021,7 +1035,12 @@ retry_bounce: | |||
1021 | netdev->stats.tx_bytes += skb->len; | 1035 | netdev->stats.tx_bytes += skb->len; |
1022 | } | 1036 | } |
1023 | 1037 | ||
1024 | for (i = 0; i < skb_shinfo(skb)->nr_frags + 1; i++) | 1038 | dma_unmap_single(&adapter->vdev->dev, |
1039 | descs[0].fields.address, | ||
1040 | descs[0].fields.flags_len & IBMVETH_BUF_LEN_MASK, | ||
1041 | DMA_TO_DEVICE); | ||
1042 | |||
1043 | for (i = 1; i < skb_shinfo(skb)->nr_frags + 1; i++) | ||
1025 | dma_unmap_page(&adapter->vdev->dev, descs[i].fields.address, | 1044 | dma_unmap_page(&adapter->vdev->dev, descs[i].fields.address, |
1026 | descs[i].fields.flags_len & IBMVETH_BUF_LEN_MASK, | 1045 | descs[i].fields.flags_len & IBMVETH_BUF_LEN_MASK, |
1027 | DMA_TO_DEVICE); | 1046 | DMA_TO_DEVICE); |
@@ -1084,8 +1103,9 @@ restart_poll: | |||
1084 | if (rx_flush) | 1103 | if (rx_flush) |
1085 | ibmveth_flush_buffer(skb->data, | 1104 | ibmveth_flush_buffer(skb->data, |
1086 | length + offset); | 1105 | length + offset); |
1106 | if (!ibmveth_rxq_recycle_buffer(adapter)) | ||
1107 | kfree_skb(skb); | ||
1087 | skb = new_skb; | 1108 | skb = new_skb; |
1088 | ibmveth_rxq_recycle_buffer(adapter); | ||
1089 | } else { | 1109 | } else { |
1090 | ibmveth_rxq_harvest_buffer(adapter); | 1110 | ibmveth_rxq_harvest_buffer(adapter); |
1091 | skb_reserve(skb, offset); | 1111 | skb_reserve(skb, offset); |
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index 22790394318a..e1fcc9589278 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c | |||
@@ -1321,8 +1321,8 @@ static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, | |||
1321 | if (ring_is_rsc_enabled(rx_ring)) | 1321 | if (ring_is_rsc_enabled(rx_ring)) |
1322 | pkt_is_rsc = ixgbe_get_rsc_state(rx_desc); | 1322 | pkt_is_rsc = ixgbe_get_rsc_state(rx_desc); |
1323 | 1323 | ||
1324 | /* if this is a skb from previous receive DMA will be 0 */ | 1324 | /* linear means we are building an skb from multiple pages */ |
1325 | if (rx_buffer_info->dma) { | 1325 | if (!skb_is_nonlinear(skb)) { |
1326 | u16 hlen; | 1326 | u16 hlen; |
1327 | if (pkt_is_rsc && | 1327 | if (pkt_is_rsc && |
1328 | !(staterr & IXGBE_RXD_STAT_EOP) && | 1328 | !(staterr & IXGBE_RXD_STAT_EOP) && |
diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index dfc82720065a..ed2a3977c6e7 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c | |||
@@ -799,5 +799,11 @@ static void __exit cleanup_netconsole(void) | |||
799 | } | 799 | } |
800 | } | 800 | } |
801 | 801 | ||
802 | module_init(init_netconsole); | 802 | /* |
803 | * Use late_initcall to ensure netconsole is | ||
804 | * initialized after network device driver if built-in. | ||
805 | * | ||
806 | * late_initcall() and module_init() are identical if built as module. | ||
807 | */ | ||
808 | late_initcall(init_netconsole); | ||
803 | module_exit(cleanup_netconsole); | 809 | module_exit(cleanup_netconsole); |
diff --git a/drivers/net/pch_gbe/pch_gbe.h b/drivers/net/pch_gbe/pch_gbe.h index 59fac77d0dbb..a09a07197eb5 100644 --- a/drivers/net/pch_gbe/pch_gbe.h +++ b/drivers/net/pch_gbe/pch_gbe.h | |||
@@ -127,8 +127,8 @@ struct pch_gbe_regs { | |||
127 | 127 | ||
128 | /* Reset */ | 128 | /* Reset */ |
129 | #define PCH_GBE_ALL_RST 0x80000000 /* All reset */ | 129 | #define PCH_GBE_ALL_RST 0x80000000 /* All reset */ |
130 | #define PCH_GBE_TX_RST 0x40000000 /* TX MAC, TX FIFO, TX DMA reset */ | 130 | #define PCH_GBE_TX_RST 0x00008000 /* TX MAC, TX FIFO, TX DMA reset */ |
131 | #define PCH_GBE_RX_RST 0x04000000 /* RX MAC, RX FIFO, RX DMA reset */ | 131 | #define PCH_GBE_RX_RST 0x00004000 /* RX MAC, RX FIFO, RX DMA reset */ |
132 | 132 | ||
133 | /* TCP/IP Accelerator Control */ | 133 | /* TCP/IP Accelerator Control */ |
134 | #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ | 134 | #define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */ |
@@ -276,6 +276,9 @@ struct pch_gbe_regs { | |||
276 | #define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ | 276 | #define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */ |
277 | #define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ | 277 | #define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */ |
278 | 278 | ||
279 | /* RX DMA STATUS */ | ||
280 | #define PCH_GBE_IDLE_CHECK 0xFFFFFFFE | ||
281 | |||
279 | /* Wake On LAN Status */ | 282 | /* Wake On LAN Status */ |
280 | #define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */ | 283 | #define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */ |
281 | #define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ | 284 | #define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */ |
@@ -471,6 +474,7 @@ struct pch_gbe_tx_desc { | |||
471 | struct pch_gbe_buffer { | 474 | struct pch_gbe_buffer { |
472 | struct sk_buff *skb; | 475 | struct sk_buff *skb; |
473 | dma_addr_t dma; | 476 | dma_addr_t dma; |
477 | unsigned char *rx_buffer; | ||
474 | unsigned long time_stamp; | 478 | unsigned long time_stamp; |
475 | u16 length; | 479 | u16 length; |
476 | bool mapped; | 480 | bool mapped; |
@@ -511,6 +515,9 @@ struct pch_gbe_tx_ring { | |||
511 | struct pch_gbe_rx_ring { | 515 | struct pch_gbe_rx_ring { |
512 | struct pch_gbe_rx_desc *desc; | 516 | struct pch_gbe_rx_desc *desc; |
513 | dma_addr_t dma; | 517 | dma_addr_t dma; |
518 | unsigned char *rx_buff_pool; | ||
519 | dma_addr_t rx_buff_pool_logic; | ||
520 | unsigned int rx_buff_pool_size; | ||
514 | unsigned int size; | 521 | unsigned int size; |
515 | unsigned int count; | 522 | unsigned int count; |
516 | unsigned int next_to_use; | 523 | unsigned int next_to_use; |
@@ -622,6 +629,7 @@ struct pch_gbe_adapter { | |||
622 | unsigned long rx_buffer_len; | 629 | unsigned long rx_buffer_len; |
623 | unsigned long tx_queue_len; | 630 | unsigned long tx_queue_len; |
624 | bool have_msi; | 631 | bool have_msi; |
632 | bool rx_stop_flag; | ||
625 | }; | 633 | }; |
626 | 634 | ||
627 | extern const char pch_driver_version[]; | 635 | extern const char pch_driver_version[]; |
diff --git a/drivers/net/pch_gbe/pch_gbe_main.c b/drivers/net/pch_gbe/pch_gbe_main.c index eac3c5ca9731..567ff10889be 100644 --- a/drivers/net/pch_gbe/pch_gbe_main.c +++ b/drivers/net/pch_gbe/pch_gbe_main.c | |||
@@ -20,7 +20,6 @@ | |||
20 | 20 | ||
21 | #include "pch_gbe.h" | 21 | #include "pch_gbe.h" |
22 | #include "pch_gbe_api.h" | 22 | #include "pch_gbe_api.h" |
23 | #include <linux/prefetch.h> | ||
24 | 23 | ||
25 | #define DRV_VERSION "1.00" | 24 | #define DRV_VERSION "1.00" |
26 | const char pch_driver_version[] = DRV_VERSION; | 25 | const char pch_driver_version[] = DRV_VERSION; |
@@ -34,11 +33,15 @@ const char pch_driver_version[] = DRV_VERSION; | |||
34 | #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */ | 33 | #define PCH_GBE_WATCHDOG_PERIOD (1 * HZ) /* watchdog time */ |
35 | #define PCH_GBE_COPYBREAK_DEFAULT 256 | 34 | #define PCH_GBE_COPYBREAK_DEFAULT 256 |
36 | #define PCH_GBE_PCI_BAR 1 | 35 | #define PCH_GBE_PCI_BAR 1 |
36 | #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */ | ||
37 | 37 | ||
38 | /* Macros for ML7223 */ | 38 | /* Macros for ML7223 */ |
39 | #define PCI_VENDOR_ID_ROHM 0x10db | 39 | #define PCI_VENDOR_ID_ROHM 0x10db |
40 | #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 | 40 | #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 |
41 | 41 | ||
42 | /* Macros for ML7831 */ | ||
43 | #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802 | ||
44 | |||
42 | #define PCH_GBE_TX_WEIGHT 64 | 45 | #define PCH_GBE_TX_WEIGHT 64 |
43 | #define PCH_GBE_RX_WEIGHT 64 | 46 | #define PCH_GBE_RX_WEIGHT 64 |
44 | #define PCH_GBE_RX_BUFFER_WRITE 16 | 47 | #define PCH_GBE_RX_BUFFER_WRITE 16 |
@@ -52,6 +55,7 @@ const char pch_driver_version[] = DRV_VERSION; | |||
52 | ) | 55 | ) |
53 | 56 | ||
54 | /* Ethertype field values */ | 57 | /* Ethertype field values */ |
58 | #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880 | ||
55 | #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 | 59 | #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 |
56 | #define PCH_GBE_FRAME_SIZE_2048 2048 | 60 | #define PCH_GBE_FRAME_SIZE_2048 2048 |
57 | #define PCH_GBE_FRAME_SIZE_4096 4096 | 61 | #define PCH_GBE_FRAME_SIZE_4096 4096 |
@@ -83,10 +87,12 @@ const char pch_driver_version[] = DRV_VERSION; | |||
83 | #define PCH_GBE_INT_ENABLE_MASK ( \ | 87 | #define PCH_GBE_INT_ENABLE_MASK ( \ |
84 | PCH_GBE_INT_RX_DMA_CMPLT | \ | 88 | PCH_GBE_INT_RX_DMA_CMPLT | \ |
85 | PCH_GBE_INT_RX_DSC_EMP | \ | 89 | PCH_GBE_INT_RX_DSC_EMP | \ |
90 | PCH_GBE_INT_RX_FIFO_ERR | \ | ||
86 | PCH_GBE_INT_WOL_DET | \ | 91 | PCH_GBE_INT_WOL_DET | \ |
87 | PCH_GBE_INT_TX_CMPLT \ | 92 | PCH_GBE_INT_TX_CMPLT \ |
88 | ) | 93 | ) |
89 | 94 | ||
95 | #define PCH_GBE_INT_DISABLE_ALL 0 | ||
90 | 96 | ||
91 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; | 97 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; |
92 | 98 | ||
@@ -138,6 +144,27 @@ static void pch_gbe_wait_clr_bit(void *reg, u32 bit) | |||
138 | if (!tmp) | 144 | if (!tmp) |
139 | pr_err("Error: busy bit is not cleared\n"); | 145 | pr_err("Error: busy bit is not cleared\n"); |
140 | } | 146 | } |
147 | |||
148 | /** | ||
149 | * pch_gbe_wait_clr_bit_irq - Wait to clear a bit for interrupt context | ||
150 | * @reg: Pointer of register | ||
151 | * @busy: Busy bit | ||
152 | */ | ||
153 | static int pch_gbe_wait_clr_bit_irq(void *reg, u32 bit) | ||
154 | { | ||
155 | u32 tmp; | ||
156 | int ret = -1; | ||
157 | /* wait busy */ | ||
158 | tmp = 20; | ||
159 | while ((ioread32(reg) & bit) && --tmp) | ||
160 | udelay(5); | ||
161 | if (!tmp) | ||
162 | pr_err("Error: busy bit is not cleared\n"); | ||
163 | else | ||
164 | ret = 0; | ||
165 | return ret; | ||
166 | } | ||
167 | |||
141 | /** | 168 | /** |
142 | * pch_gbe_mac_mar_set - Set MAC address register | 169 | * pch_gbe_mac_mar_set - Set MAC address register |
143 | * @hw: Pointer to the HW structure | 170 | * @hw: Pointer to the HW structure |
@@ -189,6 +216,17 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) | |||
189 | return; | 216 | return; |
190 | } | 217 | } |
191 | 218 | ||
219 | static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw) | ||
220 | { | ||
221 | /* Read the MAC address. and store to the private data */ | ||
222 | pch_gbe_mac_read_mac_addr(hw); | ||
223 | iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET); | ||
224 | pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST); | ||
225 | /* Setup the MAC address */ | ||
226 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); | ||
227 | return; | ||
228 | } | ||
229 | |||
192 | /** | 230 | /** |
193 | * pch_gbe_mac_init_rx_addrs - Initialize receive address's | 231 | * pch_gbe_mac_init_rx_addrs - Initialize receive address's |
194 | * @hw: Pointer to the HW structure | 232 | * @hw: Pointer to the HW structure |
@@ -671,13 +709,8 @@ static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter) | |||
671 | 709 | ||
672 | tcpip = ioread32(&hw->reg->TCPIP_ACC); | 710 | tcpip = ioread32(&hw->reg->TCPIP_ACC); |
673 | 711 | ||
674 | if (netdev->features & NETIF_F_RXCSUM) { | 712 | tcpip |= PCH_GBE_RX_TCPIPACC_OFF; |
675 | tcpip &= ~PCH_GBE_RX_TCPIPACC_OFF; | 713 | tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; |
676 | tcpip |= PCH_GBE_RX_TCPIPACC_EN; | ||
677 | } else { | ||
678 | tcpip |= PCH_GBE_RX_TCPIPACC_OFF; | ||
679 | tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; | ||
680 | } | ||
681 | iowrite32(tcpip, &hw->reg->TCPIP_ACC); | 714 | iowrite32(tcpip, &hw->reg->TCPIP_ACC); |
682 | return; | 715 | return; |
683 | } | 716 | } |
@@ -717,13 +750,6 @@ static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter) | |||
717 | iowrite32(rdba, &hw->reg->RX_DSC_BASE); | 750 | iowrite32(rdba, &hw->reg->RX_DSC_BASE); |
718 | iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); | 751 | iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); |
719 | iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); | 752 | iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); |
720 | |||
721 | /* Enables Receive DMA */ | ||
722 | rxdma = ioread32(&hw->reg->DMA_CTRL); | ||
723 | rxdma |= PCH_GBE_RX_DMA_EN; | ||
724 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | ||
725 | /* Enables Receive */ | ||
726 | iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN); | ||
727 | } | 753 | } |
728 | 754 | ||
729 | /** | 755 | /** |
@@ -1097,6 +1123,48 @@ void pch_gbe_update_stats(struct pch_gbe_adapter *adapter) | |||
1097 | spin_unlock_irqrestore(&adapter->stats_lock, flags); | 1123 | spin_unlock_irqrestore(&adapter->stats_lock, flags); |
1098 | } | 1124 | } |
1099 | 1125 | ||
1126 | static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter) | ||
1127 | { | ||
1128 | struct pch_gbe_hw *hw = &adapter->hw; | ||
1129 | u32 rxdma; | ||
1130 | u16 value; | ||
1131 | int ret; | ||
1132 | |||
1133 | /* Disable Receive DMA */ | ||
1134 | rxdma = ioread32(&hw->reg->DMA_CTRL); | ||
1135 | rxdma &= ~PCH_GBE_RX_DMA_EN; | ||
1136 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | ||
1137 | /* Wait Rx DMA BUS is IDLE */ | ||
1138 | ret = pch_gbe_wait_clr_bit_irq(&hw->reg->RX_DMA_ST, PCH_GBE_IDLE_CHECK); | ||
1139 | if (ret) { | ||
1140 | /* Disable Bus master */ | ||
1141 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &value); | ||
1142 | value &= ~PCI_COMMAND_MASTER; | ||
1143 | pci_write_config_word(adapter->pdev, PCI_COMMAND, value); | ||
1144 | /* Stop Receive */ | ||
1145 | pch_gbe_mac_reset_rx(hw); | ||
1146 | /* Enable Bus master */ | ||
1147 | value |= PCI_COMMAND_MASTER; | ||
1148 | pci_write_config_word(adapter->pdev, PCI_COMMAND, value); | ||
1149 | } else { | ||
1150 | /* Stop Receive */ | ||
1151 | pch_gbe_mac_reset_rx(hw); | ||
1152 | } | ||
1153 | } | ||
1154 | |||
1155 | static void pch_gbe_start_receive(struct pch_gbe_hw *hw) | ||
1156 | { | ||
1157 | u32 rxdma; | ||
1158 | |||
1159 | /* Enables Receive DMA */ | ||
1160 | rxdma = ioread32(&hw->reg->DMA_CTRL); | ||
1161 | rxdma |= PCH_GBE_RX_DMA_EN; | ||
1162 | iowrite32(rxdma, &hw->reg->DMA_CTRL); | ||
1163 | /* Enables Receive */ | ||
1164 | iowrite32(PCH_GBE_MRE_MAC_RX_EN, &hw->reg->MAC_RX_EN); | ||
1165 | return; | ||
1166 | } | ||
1167 | |||
1100 | /** | 1168 | /** |
1101 | * pch_gbe_intr - Interrupt Handler | 1169 | * pch_gbe_intr - Interrupt Handler |
1102 | * @irq: Interrupt number | 1170 | * @irq: Interrupt number |
@@ -1123,7 +1191,15 @@ static irqreturn_t pch_gbe_intr(int irq, void *data) | |||
1123 | if (int_st & PCH_GBE_INT_RX_FRAME_ERR) | 1191 | if (int_st & PCH_GBE_INT_RX_FRAME_ERR) |
1124 | adapter->stats.intr_rx_frame_err_count++; | 1192 | adapter->stats.intr_rx_frame_err_count++; |
1125 | if (int_st & PCH_GBE_INT_RX_FIFO_ERR) | 1193 | if (int_st & PCH_GBE_INT_RX_FIFO_ERR) |
1126 | adapter->stats.intr_rx_fifo_err_count++; | 1194 | if (!adapter->rx_stop_flag) { |
1195 | adapter->stats.intr_rx_fifo_err_count++; | ||
1196 | pr_debug("Rx fifo over run\n"); | ||
1197 | adapter->rx_stop_flag = true; | ||
1198 | int_en = ioread32(&hw->reg->INT_EN); | ||
1199 | iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR), | ||
1200 | &hw->reg->INT_EN); | ||
1201 | pch_gbe_stop_receive(adapter); | ||
1202 | } | ||
1127 | if (int_st & PCH_GBE_INT_RX_DMA_ERR) | 1203 | if (int_st & PCH_GBE_INT_RX_DMA_ERR) |
1128 | adapter->stats.intr_rx_dma_err_count++; | 1204 | adapter->stats.intr_rx_dma_err_count++; |
1129 | if (int_st & PCH_GBE_INT_TX_FIFO_ERR) | 1205 | if (int_st & PCH_GBE_INT_TX_FIFO_ERR) |
@@ -1135,7 +1211,7 @@ static irqreturn_t pch_gbe_intr(int irq, void *data) | |||
1135 | /* When Rx descriptor is empty */ | 1211 | /* When Rx descriptor is empty */ |
1136 | if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { | 1212 | if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { |
1137 | adapter->stats.intr_rx_dsc_empty_count++; | 1213 | adapter->stats.intr_rx_dsc_empty_count++; |
1138 | pr_err("Rx descriptor is empty\n"); | 1214 | pr_debug("Rx descriptor is empty\n"); |
1139 | int_en = ioread32(&hw->reg->INT_EN); | 1215 | int_en = ioread32(&hw->reg->INT_EN); |
1140 | iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); | 1216 | iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); |
1141 | if (hw->mac.tx_fc_enable) { | 1217 | if (hw->mac.tx_fc_enable) { |
@@ -1185,29 +1261,23 @@ pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, | |||
1185 | unsigned int i; | 1261 | unsigned int i; |
1186 | unsigned int bufsz; | 1262 | unsigned int bufsz; |
1187 | 1263 | ||
1188 | bufsz = adapter->rx_buffer_len + PCH_GBE_DMA_ALIGN; | 1264 | bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; |
1189 | i = rx_ring->next_to_use; | 1265 | i = rx_ring->next_to_use; |
1190 | 1266 | ||
1191 | while ((cleaned_count--)) { | 1267 | while ((cleaned_count--)) { |
1192 | buffer_info = &rx_ring->buffer_info[i]; | 1268 | buffer_info = &rx_ring->buffer_info[i]; |
1193 | skb = buffer_info->skb; | 1269 | skb = netdev_alloc_skb(netdev, bufsz); |
1194 | if (skb) { | 1270 | if (unlikely(!skb)) { |
1195 | skb_trim(skb, 0); | 1271 | /* Better luck next round */ |
1196 | } else { | 1272 | adapter->stats.rx_alloc_buff_failed++; |
1197 | skb = netdev_alloc_skb(netdev, bufsz); | 1273 | break; |
1198 | if (unlikely(!skb)) { | ||
1199 | /* Better luck next round */ | ||
1200 | adapter->stats.rx_alloc_buff_failed++; | ||
1201 | break; | ||
1202 | } | ||
1203 | /* 64byte align */ | ||
1204 | skb_reserve(skb, PCH_GBE_DMA_ALIGN); | ||
1205 | |||
1206 | buffer_info->skb = skb; | ||
1207 | buffer_info->length = adapter->rx_buffer_len; | ||
1208 | } | 1274 | } |
1275 | /* align */ | ||
1276 | skb_reserve(skb, NET_IP_ALIGN); | ||
1277 | buffer_info->skb = skb; | ||
1278 | |||
1209 | buffer_info->dma = dma_map_single(&pdev->dev, | 1279 | buffer_info->dma = dma_map_single(&pdev->dev, |
1210 | skb->data, | 1280 | buffer_info->rx_buffer, |
1211 | buffer_info->length, | 1281 | buffer_info->length, |
1212 | DMA_FROM_DEVICE); | 1282 | DMA_FROM_DEVICE); |
1213 | if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { | 1283 | if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { |
@@ -1240,6 +1310,36 @@ pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, | |||
1240 | return; | 1310 | return; |
1241 | } | 1311 | } |
1242 | 1312 | ||
1313 | static int | ||
1314 | pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter, | ||
1315 | struct pch_gbe_rx_ring *rx_ring, int cleaned_count) | ||
1316 | { | ||
1317 | struct pci_dev *pdev = adapter->pdev; | ||
1318 | struct pch_gbe_buffer *buffer_info; | ||
1319 | unsigned int i; | ||
1320 | unsigned int bufsz; | ||
1321 | unsigned int size; | ||
1322 | |||
1323 | bufsz = adapter->rx_buffer_len; | ||
1324 | |||
1325 | size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY; | ||
1326 | rx_ring->rx_buff_pool = dma_alloc_coherent(&pdev->dev, size, | ||
1327 | &rx_ring->rx_buff_pool_logic, | ||
1328 | GFP_KERNEL); | ||
1329 | if (!rx_ring->rx_buff_pool) { | ||
1330 | pr_err("Unable to allocate memory for the receive poll buffer\n"); | ||
1331 | return -ENOMEM; | ||
1332 | } | ||
1333 | memset(rx_ring->rx_buff_pool, 0, size); | ||
1334 | rx_ring->rx_buff_pool_size = size; | ||
1335 | for (i = 0; i < rx_ring->count; i++) { | ||
1336 | buffer_info = &rx_ring->buffer_info[i]; | ||
1337 | buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i; | ||
1338 | buffer_info->length = bufsz; | ||
1339 | } | ||
1340 | return 0; | ||
1341 | } | ||
1342 | |||
1243 | /** | 1343 | /** |
1244 | * pch_gbe_alloc_tx_buffers - Allocate transmit buffers | 1344 | * pch_gbe_alloc_tx_buffers - Allocate transmit buffers |
1245 | * @adapter: Board private structure | 1345 | * @adapter: Board private structure |
@@ -1380,7 +1480,7 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1380 | unsigned int i; | 1480 | unsigned int i; |
1381 | unsigned int cleaned_count = 0; | 1481 | unsigned int cleaned_count = 0; |
1382 | bool cleaned = false; | 1482 | bool cleaned = false; |
1383 | struct sk_buff *skb, *new_skb; | 1483 | struct sk_buff *skb; |
1384 | u8 dma_status; | 1484 | u8 dma_status; |
1385 | u16 gbec_status; | 1485 | u16 gbec_status; |
1386 | u32 tcp_ip_status; | 1486 | u32 tcp_ip_status; |
@@ -1401,13 +1501,12 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1401 | rx_desc->gbec_status = DSC_INIT16; | 1501 | rx_desc->gbec_status = DSC_INIT16; |
1402 | buffer_info = &rx_ring->buffer_info[i]; | 1502 | buffer_info = &rx_ring->buffer_info[i]; |
1403 | skb = buffer_info->skb; | 1503 | skb = buffer_info->skb; |
1504 | buffer_info->skb = NULL; | ||
1404 | 1505 | ||
1405 | /* unmap dma */ | 1506 | /* unmap dma */ |
1406 | dma_unmap_single(&pdev->dev, buffer_info->dma, | 1507 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
1407 | buffer_info->length, DMA_FROM_DEVICE); | 1508 | buffer_info->length, DMA_FROM_DEVICE); |
1408 | buffer_info->mapped = false; | 1509 | buffer_info->mapped = false; |
1409 | /* Prefetch the packet */ | ||
1410 | prefetch(skb->data); | ||
1411 | 1510 | ||
1412 | pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x " | 1511 | pr_debug("RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x " |
1413 | "TCP:0x%08x] BufInf = 0x%p\n", | 1512 | "TCP:0x%08x] BufInf = 0x%p\n", |
@@ -1427,70 +1526,16 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1427 | pr_err("Receive CRC Error\n"); | 1526 | pr_err("Receive CRC Error\n"); |
1428 | } else { | 1527 | } else { |
1429 | /* get receive length */ | 1528 | /* get receive length */ |
1430 | /* length convert[-3] */ | 1529 | /* length convert[-3], length includes FCS length */ |
1431 | length = (rx_desc->rx_words_eob) - 3; | 1530 | length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN; |
1432 | 1531 | if (rx_desc->rx_words_eob & 0x02) | |
1433 | /* Decide the data conversion method */ | 1532 | length = length - 4; |
1434 | if (!(netdev->features & NETIF_F_RXCSUM)) { | 1533 | /* |
1435 | /* [Header:14][payload] */ | 1534 | * buffer_info->rx_buffer: [Header:14][payload] |
1436 | if (NET_IP_ALIGN) { | 1535 | * skb->data: [Reserve:2][Header:14][payload] |
1437 | /* Because alignment differs, | 1536 | */ |
1438 | * the new_skb is newly allocated, | 1537 | memcpy(skb->data, buffer_info->rx_buffer, length); |
1439 | * and data is copied to new_skb.*/ | 1538 | |
1440 | new_skb = netdev_alloc_skb(netdev, | ||
1441 | length + NET_IP_ALIGN); | ||
1442 | if (!new_skb) { | ||
1443 | /* dorrop error */ | ||
1444 | pr_err("New skb allocation " | ||
1445 | "Error\n"); | ||
1446 | goto dorrop; | ||
1447 | } | ||
1448 | skb_reserve(new_skb, NET_IP_ALIGN); | ||
1449 | memcpy(new_skb->data, skb->data, | ||
1450 | length); | ||
1451 | skb = new_skb; | ||
1452 | } else { | ||
1453 | /* DMA buffer is used as SKB as it is.*/ | ||
1454 | buffer_info->skb = NULL; | ||
1455 | } | ||
1456 | } else { | ||
1457 | /* [Header:14][padding:2][payload] */ | ||
1458 | /* The length includes padding length */ | ||
1459 | length = length - PCH_GBE_DMA_PADDING; | ||
1460 | if ((length < copybreak) || | ||
1461 | (NET_IP_ALIGN != PCH_GBE_DMA_PADDING)) { | ||
1462 | /* Because alignment differs, | ||
1463 | * the new_skb is newly allocated, | ||
1464 | * and data is copied to new_skb. | ||
1465 | * Padding data is deleted | ||
1466 | * at the time of a copy.*/ | ||
1467 | new_skb = netdev_alloc_skb(netdev, | ||
1468 | length + NET_IP_ALIGN); | ||
1469 | if (!new_skb) { | ||
1470 | /* dorrop error */ | ||
1471 | pr_err("New skb allocation " | ||
1472 | "Error\n"); | ||
1473 | goto dorrop; | ||
1474 | } | ||
1475 | skb_reserve(new_skb, NET_IP_ALIGN); | ||
1476 | memcpy(new_skb->data, skb->data, | ||
1477 | ETH_HLEN); | ||
1478 | memcpy(&new_skb->data[ETH_HLEN], | ||
1479 | &skb->data[ETH_HLEN + | ||
1480 | PCH_GBE_DMA_PADDING], | ||
1481 | length - ETH_HLEN); | ||
1482 | skb = new_skb; | ||
1483 | } else { | ||
1484 | /* Padding data is deleted | ||
1485 | * by moving header data.*/ | ||
1486 | memmove(&skb->data[PCH_GBE_DMA_PADDING], | ||
1487 | &skb->data[0], ETH_HLEN); | ||
1488 | skb_reserve(skb, NET_IP_ALIGN); | ||
1489 | buffer_info->skb = NULL; | ||
1490 | } | ||
1491 | } | ||
1492 | /* The length includes FCS length */ | ||
1493 | length = length - ETH_FCS_LEN; | ||
1494 | /* update status of driver */ | 1539 | /* update status of driver */ |
1495 | adapter->stats.rx_bytes += length; | 1540 | adapter->stats.rx_bytes += length; |
1496 | adapter->stats.rx_packets++; | 1541 | adapter->stats.rx_packets++; |
@@ -1509,7 +1554,6 @@ pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, | |||
1509 | pr_debug("Receive skb->ip_summed: %d length: %d\n", | 1554 | pr_debug("Receive skb->ip_summed: %d length: %d\n", |
1510 | skb->ip_summed, length); | 1555 | skb->ip_summed, length); |
1511 | } | 1556 | } |
1512 | dorrop: | ||
1513 | /* return some buffers to hardware, one at a time is too slow */ | 1557 | /* return some buffers to hardware, one at a time is too slow */ |
1514 | if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { | 1558 | if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { |
1515 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, | 1559 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, |
@@ -1714,9 +1758,15 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter) | |||
1714 | pr_err("Error: can't bring device up\n"); | 1758 | pr_err("Error: can't bring device up\n"); |
1715 | return err; | 1759 | return err; |
1716 | } | 1760 | } |
1761 | err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count); | ||
1762 | if (err) { | ||
1763 | pr_err("Error: can't bring device up\n"); | ||
1764 | return err; | ||
1765 | } | ||
1717 | pch_gbe_alloc_tx_buffers(adapter, tx_ring); | 1766 | pch_gbe_alloc_tx_buffers(adapter, tx_ring); |
1718 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); | 1767 | pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); |
1719 | adapter->tx_queue_len = netdev->tx_queue_len; | 1768 | adapter->tx_queue_len = netdev->tx_queue_len; |
1769 | pch_gbe_start_receive(&adapter->hw); | ||
1720 | 1770 | ||
1721 | mod_timer(&adapter->watchdog_timer, jiffies); | 1771 | mod_timer(&adapter->watchdog_timer, jiffies); |
1722 | 1772 | ||
@@ -1734,6 +1784,7 @@ int pch_gbe_up(struct pch_gbe_adapter *adapter) | |||
1734 | void pch_gbe_down(struct pch_gbe_adapter *adapter) | 1784 | void pch_gbe_down(struct pch_gbe_adapter *adapter) |
1735 | { | 1785 | { |
1736 | struct net_device *netdev = adapter->netdev; | 1786 | struct net_device *netdev = adapter->netdev; |
1787 | struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; | ||
1737 | 1788 | ||
1738 | /* signal that we're down so the interrupt handler does not | 1789 | /* signal that we're down so the interrupt handler does not |
1739 | * reschedule our watchdog timer */ | 1790 | * reschedule our watchdog timer */ |
@@ -1752,6 +1803,12 @@ void pch_gbe_down(struct pch_gbe_adapter *adapter) | |||
1752 | pch_gbe_reset(adapter); | 1803 | pch_gbe_reset(adapter); |
1753 | pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); | 1804 | pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); |
1754 | pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); | 1805 | pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); |
1806 | |||
1807 | pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size, | ||
1808 | rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic); | ||
1809 | rx_ring->rx_buff_pool_logic = 0; | ||
1810 | rx_ring->rx_buff_pool_size = 0; | ||
1811 | rx_ring->rx_buff_pool = NULL; | ||
1755 | } | 1812 | } |
1756 | 1813 | ||
1757 | /** | 1814 | /** |
@@ -2004,6 +2061,8 @@ static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) | |||
2004 | { | 2061 | { |
2005 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | 2062 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); |
2006 | int max_frame; | 2063 | int max_frame; |
2064 | unsigned long old_rx_buffer_len = adapter->rx_buffer_len; | ||
2065 | int err; | ||
2007 | 2066 | ||
2008 | max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | 2067 | max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; |
2009 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || | 2068 | if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) || |
@@ -2018,14 +2077,24 @@ static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) | |||
2018 | else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) | 2077 | else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) |
2019 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; | 2078 | adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; |
2020 | else | 2079 | else |
2021 | adapter->rx_buffer_len = PCH_GBE_MAX_JUMBO_FRAME_SIZE; | 2080 | adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE; |
2022 | netdev->mtu = new_mtu; | ||
2023 | adapter->hw.mac.max_frame_size = max_frame; | ||
2024 | 2081 | ||
2025 | if (netif_running(netdev)) | 2082 | if (netif_running(netdev)) { |
2026 | pch_gbe_reinit_locked(adapter); | 2083 | pch_gbe_down(adapter); |
2027 | else | 2084 | err = pch_gbe_up(adapter); |
2085 | if (err) { | ||
2086 | adapter->rx_buffer_len = old_rx_buffer_len; | ||
2087 | pch_gbe_up(adapter); | ||
2088 | return -ENOMEM; | ||
2089 | } else { | ||
2090 | netdev->mtu = new_mtu; | ||
2091 | adapter->hw.mac.max_frame_size = max_frame; | ||
2092 | } | ||
2093 | } else { | ||
2028 | pch_gbe_reset(adapter); | 2094 | pch_gbe_reset(adapter); |
2095 | netdev->mtu = new_mtu; | ||
2096 | adapter->hw.mac.max_frame_size = max_frame; | ||
2097 | } | ||
2029 | 2098 | ||
2030 | pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", | 2099 | pr_debug("max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", |
2031 | max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, | 2100 | max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, |
@@ -2103,6 +2172,7 @@ static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) | |||
2103 | int work_done = 0; | 2172 | int work_done = 0; |
2104 | bool poll_end_flag = false; | 2173 | bool poll_end_flag = false; |
2105 | bool cleaned = false; | 2174 | bool cleaned = false; |
2175 | u32 int_en; | ||
2106 | 2176 | ||
2107 | pr_debug("budget : %d\n", budget); | 2177 | pr_debug("budget : %d\n", budget); |
2108 | 2178 | ||
@@ -2110,8 +2180,15 @@ static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) | |||
2110 | if (!netif_carrier_ok(netdev)) { | 2180 | if (!netif_carrier_ok(netdev)) { |
2111 | poll_end_flag = true; | 2181 | poll_end_flag = true; |
2112 | } else { | 2182 | } else { |
2113 | cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); | ||
2114 | pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); | 2183 | pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); |
2184 | if (adapter->rx_stop_flag) { | ||
2185 | adapter->rx_stop_flag = false; | ||
2186 | pch_gbe_start_receive(&adapter->hw); | ||
2187 | int_en = ioread32(&adapter->hw.reg->INT_EN); | ||
2188 | iowrite32((int_en | PCH_GBE_INT_RX_FIFO_ERR), | ||
2189 | &adapter->hw.reg->INT_EN); | ||
2190 | } | ||
2191 | cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); | ||
2115 | 2192 | ||
2116 | if (cleaned) | 2193 | if (cleaned) |
2117 | work_done = budget; | 2194 | work_done = budget; |
@@ -2452,6 +2529,13 @@ static DEFINE_PCI_DEVICE_TABLE(pch_gbe_pcidev_id) = { | |||
2452 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | 2529 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), |
2453 | .class_mask = (0xFFFF00) | 2530 | .class_mask = (0xFFFF00) |
2454 | }, | 2531 | }, |
2532 | {.vendor = PCI_VENDOR_ID_ROHM, | ||
2533 | .device = PCI_DEVICE_ID_ROHM_ML7831_GBE, | ||
2534 | .subvendor = PCI_ANY_ID, | ||
2535 | .subdevice = PCI_ANY_ID, | ||
2536 | .class = (PCI_CLASS_NETWORK_ETHERNET << 8), | ||
2537 | .class_mask = (0xFFFF00) | ||
2538 | }, | ||
2455 | /* required last entry */ | 2539 | /* required last entry */ |
2456 | {0} | 2540 | {0} |
2457 | }; | 2541 | }; |
diff --git a/drivers/net/phy/national.c b/drivers/net/phy/national.c index 0620ba963508..04bb8fcc0cb5 100644 --- a/drivers/net/phy/national.c +++ b/drivers/net/phy/national.c | |||
@@ -25,8 +25,9 @@ | |||
25 | /* DP83865 phy identifier values */ | 25 | /* DP83865 phy identifier values */ |
26 | #define DP83865_PHY_ID 0x20005c7a | 26 | #define DP83865_PHY_ID 0x20005c7a |
27 | 27 | ||
28 | #define DP83865_INT_MASK_REG 0x15 | 28 | #define DP83865_INT_STATUS 0x14 |
29 | #define DP83865_INT_MASK_STATUS 0x14 | 29 | #define DP83865_INT_MASK 0x15 |
30 | #define DP83865_INT_CLEAR 0x17 | ||
30 | 31 | ||
31 | #define DP83865_INT_REMOTE_FAULT 0x0008 | 32 | #define DP83865_INT_REMOTE_FAULT 0x0008 |
32 | #define DP83865_INT_ANE_COMPLETED 0x0010 | 33 | #define DP83865_INT_ANE_COMPLETED 0x0010 |
@@ -68,21 +69,25 @@ static int ns_config_intr(struct phy_device *phydev) | |||
68 | int err; | 69 | int err; |
69 | 70 | ||
70 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | 71 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
71 | err = phy_write(phydev, DP83865_INT_MASK_REG, | 72 | err = phy_write(phydev, DP83865_INT_MASK, |
72 | DP83865_INT_MASK_DEFAULT); | 73 | DP83865_INT_MASK_DEFAULT); |
73 | else | 74 | else |
74 | err = phy_write(phydev, DP83865_INT_MASK_REG, 0); | 75 | err = phy_write(phydev, DP83865_INT_MASK, 0); |
75 | 76 | ||
76 | return err; | 77 | return err; |
77 | } | 78 | } |
78 | 79 | ||
79 | static int ns_ack_interrupt(struct phy_device *phydev) | 80 | static int ns_ack_interrupt(struct phy_device *phydev) |
80 | { | 81 | { |
81 | int ret = phy_read(phydev, DP83865_INT_MASK_STATUS); | 82 | int ret = phy_read(phydev, DP83865_INT_STATUS); |
82 | if (ret < 0) | 83 | if (ret < 0) |
83 | return ret; | 84 | return ret; |
84 | 85 | ||
85 | return 0; | 86 | /* Clear the interrupt status bit by writing a “1” |
87 | * to the corresponding bit in INT_CLEAR (2:0 are reserved) */ | ||
88 | ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); | ||
89 | |||
90 | return ret; | ||
86 | } | 91 | } |
87 | 92 | ||
88 | static void ns_giga_speed_fallback(struct phy_device *phydev, int mode) | 93 | static void ns_giga_speed_fallback(struct phy_device *phydev, int mode) |
diff --git a/drivers/net/ppp_generic.c b/drivers/net/ppp_generic.c index 10e5d985afa3..edfa15d2e795 100644 --- a/drivers/net/ppp_generic.c +++ b/drivers/net/ppp_generic.c | |||
@@ -1465,7 +1465,12 @@ static int ppp_mp_explode(struct ppp *ppp, struct sk_buff *skb) | |||
1465 | continue; | 1465 | continue; |
1466 | } | 1466 | } |
1467 | 1467 | ||
1468 | mtu = pch->chan->mtu - hdrlen; | 1468 | /* |
1469 | * hdrlen includes the 2-byte PPP protocol field, but the | ||
1470 | * MTU counts only the payload excluding the protocol field. | ||
1471 | * (RFC1661 Section 2) | ||
1472 | */ | ||
1473 | mtu = pch->chan->mtu - (hdrlen - 2); | ||
1469 | if (mtu < 4) | 1474 | if (mtu < 4) |
1470 | mtu = 4; | 1475 | mtu = 4; |
1471 | if (flen > mtu) | 1476 | if (flen > mtu) |
diff --git a/drivers/net/pxa168_eth.c b/drivers/net/pxa168_eth.c index 1a3033d8e7ed..d17d0624c5e6 100644 --- a/drivers/net/pxa168_eth.c +++ b/drivers/net/pxa168_eth.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <linux/clk.h> | 40 | #include <linux/clk.h> |
41 | #include <linux/phy.h> | 41 | #include <linux/phy.h> |
42 | #include <linux/io.h> | 42 | #include <linux/io.h> |
43 | #include <linux/interrupt.h> | ||
43 | #include <linux/types.h> | 44 | #include <linux/types.h> |
44 | #include <asm/pgtable.h> | 45 | #include <asm/pgtable.h> |
45 | #include <asm/system.h> | 46 | #include <asm/system.h> |
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 02339b3352e7..c23667017922 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c | |||
@@ -407,6 +407,7 @@ enum rtl_register_content { | |||
407 | RxOK = 0x0001, | 407 | RxOK = 0x0001, |
408 | 408 | ||
409 | /* RxStatusDesc */ | 409 | /* RxStatusDesc */ |
410 | RxBOVF = (1 << 24), | ||
410 | RxFOVF = (1 << 23), | 411 | RxFOVF = (1 << 23), |
411 | RxRWT = (1 << 22), | 412 | RxRWT = (1 << 22), |
412 | RxRES = (1 << 21), | 413 | RxRES = (1 << 21), |
@@ -682,6 +683,7 @@ struct rtl8169_private { | |||
682 | struct mii_if_info mii; | 683 | struct mii_if_info mii; |
683 | struct rtl8169_counters counters; | 684 | struct rtl8169_counters counters; |
684 | u32 saved_wolopts; | 685 | u32 saved_wolopts; |
686 | u32 opts1_mask; | ||
685 | 687 | ||
686 | struct rtl_fw { | 688 | struct rtl_fw { |
687 | const struct firmware *fw; | 689 | const struct firmware *fw; |
@@ -710,6 +712,7 @@ MODULE_FIRMWARE(FIRMWARE_8168D_1); | |||
710 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | 712 | MODULE_FIRMWARE(FIRMWARE_8168D_2); |
711 | MODULE_FIRMWARE(FIRMWARE_8168E_1); | 713 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
712 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | 714 | MODULE_FIRMWARE(FIRMWARE_8168E_2); |
715 | MODULE_FIRMWARE(FIRMWARE_8168E_3); | ||
713 | MODULE_FIRMWARE(FIRMWARE_8105E_1); | 716 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
714 | 717 | ||
715 | static int rtl8169_open(struct net_device *dev); | 718 | static int rtl8169_open(struct net_device *dev); |
@@ -3077,6 +3080,14 @@ static void rtl8169_phy_reset(struct net_device *dev, | |||
3077 | netif_err(tp, link, dev, "PHY reset failed\n"); | 3080 | netif_err(tp, link, dev, "PHY reset failed\n"); |
3078 | } | 3081 | } |
3079 | 3082 | ||
3083 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) | ||
3084 | { | ||
3085 | void __iomem *ioaddr = tp->mmio_addr; | ||
3086 | |||
3087 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | ||
3088 | (RTL_R8(PHYstatus) & TBI_Enable); | ||
3089 | } | ||
3090 | |||
3080 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) | 3091 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
3081 | { | 3092 | { |
3082 | void __iomem *ioaddr = tp->mmio_addr; | 3093 | void __iomem *ioaddr = tp->mmio_addr; |
@@ -3109,7 +3120,7 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) | |||
3109 | ADVERTISED_1000baseT_Half | | 3120 | ADVERTISED_1000baseT_Half | |
3110 | ADVERTISED_1000baseT_Full : 0)); | 3121 | ADVERTISED_1000baseT_Full : 0)); |
3111 | 3122 | ||
3112 | if (RTL_R8(PHYstatus) & TBI_Enable) | 3123 | if (rtl_tbi_enabled(tp)) |
3113 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); | 3124 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
3114 | } | 3125 | } |
3115 | 3126 | ||
@@ -3319,9 +3330,16 @@ static void r810x_phy_power_up(struct rtl8169_private *tp) | |||
3319 | 3330 | ||
3320 | static void r810x_pll_power_down(struct rtl8169_private *tp) | 3331 | static void r810x_pll_power_down(struct rtl8169_private *tp) |
3321 | { | 3332 | { |
3333 | void __iomem *ioaddr = tp->mmio_addr; | ||
3334 | |||
3322 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { | 3335 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
3323 | rtl_writephy(tp, 0x1f, 0x0000); | 3336 | rtl_writephy(tp, 0x1f, 0x0000); |
3324 | rtl_writephy(tp, MII_BMCR, 0x0000); | 3337 | rtl_writephy(tp, MII_BMCR, 0x0000); |
3338 | |||
3339 | if (tp->mac_version == RTL_GIGA_MAC_VER_29 || | ||
3340 | tp->mac_version == RTL_GIGA_MAC_VER_30) | ||
3341 | RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | | ||
3342 | AcceptMulticast | AcceptMyPhys); | ||
3325 | return; | 3343 | return; |
3326 | } | 3344 | } |
3327 | 3345 | ||
@@ -3417,7 +3435,8 @@ static void r8168_pll_power_down(struct rtl8169_private *tp) | |||
3417 | rtl_writephy(tp, MII_BMCR, 0x0000); | 3435 | rtl_writephy(tp, MII_BMCR, 0x0000); |
3418 | 3436 | ||
3419 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || | 3437 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
3420 | tp->mac_version == RTL_GIGA_MAC_VER_33) | 3438 | tp->mac_version == RTL_GIGA_MAC_VER_33 || |
3439 | tp->mac_version == RTL_GIGA_MAC_VER_34) | ||
3421 | RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | | 3440 | RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | |
3422 | AcceptMulticast | AcceptMyPhys); | 3441 | AcceptMulticast | AcceptMyPhys); |
3423 | return; | 3442 | return; |
@@ -3727,8 +3746,7 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
3727 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); | 3746 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
3728 | RTL_W8(Cfg9346, Cfg9346_Lock); | 3747 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3729 | 3748 | ||
3730 | if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && | 3749 | if (rtl_tbi_enabled(tp)) { |
3731 | (RTL_R8(PHYstatus) & TBI_Enable)) { | ||
3732 | tp->set_speed = rtl8169_set_speed_tbi; | 3750 | tp->set_speed = rtl8169_set_speed_tbi; |
3733 | tp->get_settings = rtl8169_gset_tbi; | 3751 | tp->get_settings = rtl8169_gset_tbi; |
3734 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | 3752 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; |
@@ -3777,6 +3795,9 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
3777 | tp->intr_event = cfg->intr_event; | 3795 | tp->intr_event = cfg->intr_event; |
3778 | tp->napi_event = cfg->napi_event; | 3796 | tp->napi_event = cfg->napi_event; |
3779 | 3797 | ||
3798 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? | ||
3799 | ~(RxBOVF | RxFOVF) : ~0; | ||
3800 | |||
3780 | init_timer(&tp->timer); | 3801 | init_timer(&tp->timer); |
3781 | tp->timer.data = (unsigned long) dev; | 3802 | tp->timer.data = (unsigned long) dev; |
3782 | tp->timer.function = rtl8169_phy_timer; | 3803 | tp->timer.function = rtl8169_phy_timer; |
@@ -3988,6 +4009,7 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp) | |||
3988 | while (RTL_R8(TxPoll) & NPQ) | 4009 | while (RTL_R8(TxPoll) & NPQ) |
3989 | udelay(20); | 4010 | udelay(20); |
3990 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) { | 4011 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
4012 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | ||
3991 | while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) | 4013 | while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) |
3992 | udelay(100); | 4014 | udelay(100); |
3993 | } else { | 4015 | } else { |
@@ -5314,7 +5336,7 @@ static int rtl8169_rx_interrupt(struct net_device *dev, | |||
5314 | u32 status; | 5336 | u32 status; |
5315 | 5337 | ||
5316 | rmb(); | 5338 | rmb(); |
5317 | status = le32_to_cpu(desc->opts1); | 5339 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
5318 | 5340 | ||
5319 | if (status & DescOwn) | 5341 | if (status & DescOwn) |
5320 | break; | 5342 | break; |
diff --git a/drivers/net/rionet.c b/drivers/net/rionet.c index 86ac38c96bcf..3bb131137033 100644 --- a/drivers/net/rionet.c +++ b/drivers/net/rionet.c | |||
@@ -80,13 +80,13 @@ static int rionet_capable = 1; | |||
80 | */ | 80 | */ |
81 | static struct rio_dev **rionet_active; | 81 | static struct rio_dev **rionet_active; |
82 | 82 | ||
83 | #define is_rionet_capable(pef, src_ops, dst_ops) \ | 83 | #define is_rionet_capable(src_ops, dst_ops) \ |
84 | ((pef & RIO_PEF_INB_MBOX) && \ | 84 | ((src_ops & RIO_SRC_OPS_DATA_MSG) && \ |
85 | (pef & RIO_PEF_INB_DOORBELL) && \ | 85 | (dst_ops & RIO_DST_OPS_DATA_MSG) && \ |
86 | (src_ops & RIO_SRC_OPS_DOORBELL) && \ | 86 | (src_ops & RIO_SRC_OPS_DOORBELL) && \ |
87 | (dst_ops & RIO_DST_OPS_DOORBELL)) | 87 | (dst_ops & RIO_DST_OPS_DOORBELL)) |
88 | #define dev_rionet_capable(dev) \ | 88 | #define dev_rionet_capable(dev) \ |
89 | is_rionet_capable(dev->pef, dev->src_ops, dev->dst_ops) | 89 | is_rionet_capable(dev->src_ops, dev->dst_ops) |
90 | 90 | ||
91 | #define RIONET_MAC_MATCH(x) (*(u32 *)x == 0x00010001) | 91 | #define RIONET_MAC_MATCH(x) (*(u32 *)x == 0x00010001) |
92 | #define RIONET_GET_DESTID(x) (*(u16 *)(x + 4)) | 92 | #define RIONET_GET_DESTID(x) (*(u16 *)(x + 4)) |
@@ -282,7 +282,6 @@ static int rionet_open(struct net_device *ndev) | |||
282 | { | 282 | { |
283 | int i, rc = 0; | 283 | int i, rc = 0; |
284 | struct rionet_peer *peer, *tmp; | 284 | struct rionet_peer *peer, *tmp; |
285 | u32 pwdcsr; | ||
286 | struct rionet_private *rnet = netdev_priv(ndev); | 285 | struct rionet_private *rnet = netdev_priv(ndev); |
287 | 286 | ||
288 | if (netif_msg_ifup(rnet)) | 287 | if (netif_msg_ifup(rnet)) |
@@ -332,13 +331,8 @@ static int rionet_open(struct net_device *ndev) | |||
332 | continue; | 331 | continue; |
333 | } | 332 | } |
334 | 333 | ||
335 | /* | 334 | /* Send a join message */ |
336 | * If device has initialized inbound doorbells, | 335 | rio_send_doorbell(peer->rdev, RIONET_DOORBELL_JOIN); |
337 | * send a join message | ||
338 | */ | ||
339 | rio_read_config_32(peer->rdev, RIO_WRITE_PORT_CSR, &pwdcsr); | ||
340 | if (pwdcsr & RIO_DOORBELL_AVAIL) | ||
341 | rio_send_doorbell(peer->rdev, RIONET_DOORBELL_JOIN); | ||
342 | } | 336 | } |
343 | 337 | ||
344 | out: | 338 | out: |
@@ -492,7 +486,7 @@ static int rionet_setup_netdev(struct rio_mport *mport, struct net_device *ndev) | |||
492 | static int rionet_probe(struct rio_dev *rdev, const struct rio_device_id *id) | 486 | static int rionet_probe(struct rio_dev *rdev, const struct rio_device_id *id) |
493 | { | 487 | { |
494 | int rc = -ENODEV; | 488 | int rc = -ENODEV; |
495 | u32 lpef, lsrc_ops, ldst_ops; | 489 | u32 lsrc_ops, ldst_ops; |
496 | struct rionet_peer *peer; | 490 | struct rionet_peer *peer; |
497 | struct net_device *ndev = NULL; | 491 | struct net_device *ndev = NULL; |
498 | 492 | ||
@@ -515,12 +509,11 @@ static int rionet_probe(struct rio_dev *rdev, const struct rio_device_id *id) | |||
515 | * on later probes | 509 | * on later probes |
516 | */ | 510 | */ |
517 | if (!rionet_check) { | 511 | if (!rionet_check) { |
518 | rio_local_read_config_32(rdev->net->hport, RIO_PEF_CAR, &lpef); | ||
519 | rio_local_read_config_32(rdev->net->hport, RIO_SRC_OPS_CAR, | 512 | rio_local_read_config_32(rdev->net->hport, RIO_SRC_OPS_CAR, |
520 | &lsrc_ops); | 513 | &lsrc_ops); |
521 | rio_local_read_config_32(rdev->net->hport, RIO_DST_OPS_CAR, | 514 | rio_local_read_config_32(rdev->net->hport, RIO_DST_OPS_CAR, |
522 | &ldst_ops); | 515 | &ldst_ops); |
523 | if (!is_rionet_capable(lpef, lsrc_ops, ldst_ops)) { | 516 | if (!is_rionet_capable(lsrc_ops, ldst_ops)) { |
524 | printk(KERN_ERR | 517 | printk(KERN_ERR |
525 | "%s: local device is not network capable\n", | 518 | "%s: local device is not network capable\n", |
526 | DRV_NAME); | 519 | DRV_NAME); |
diff --git a/drivers/net/sfc/efx.c b/drivers/net/sfc/efx.c index faca764aa21b..b59abc706d93 100644 --- a/drivers/net/sfc/efx.c +++ b/drivers/net/sfc/efx.c | |||
@@ -1050,7 +1050,6 @@ static int efx_init_io(struct efx_nic *efx) | |||
1050 | { | 1050 | { |
1051 | struct pci_dev *pci_dev = efx->pci_dev; | 1051 | struct pci_dev *pci_dev = efx->pci_dev; |
1052 | dma_addr_t dma_mask = efx->type->max_dma_mask; | 1052 | dma_addr_t dma_mask = efx->type->max_dma_mask; |
1053 | bool use_wc; | ||
1054 | int rc; | 1053 | int rc; |
1055 | 1054 | ||
1056 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); | 1055 | netif_dbg(efx, probe, efx->net_dev, "initialising I/O\n"); |
@@ -1101,21 +1100,8 @@ static int efx_init_io(struct efx_nic *efx) | |||
1101 | rc = -EIO; | 1100 | rc = -EIO; |
1102 | goto fail3; | 1101 | goto fail3; |
1103 | } | 1102 | } |
1104 | 1103 | efx->membase = ioremap_nocache(efx->membase_phys, | |
1105 | /* bug22643: If SR-IOV is enabled then tx push over a write combined | 1104 | efx->type->mem_map_size); |
1106 | * mapping is unsafe. We need to disable write combining in this case. | ||
1107 | * MSI is unsupported when SR-IOV is enabled, and the firmware will | ||
1108 | * have removed the MSI capability. So write combining is safe if | ||
1109 | * there is an MSI capability. | ||
1110 | */ | ||
1111 | use_wc = (!EFX_WORKAROUND_22643(efx) || | ||
1112 | pci_find_capability(pci_dev, PCI_CAP_ID_MSI)); | ||
1113 | if (use_wc) | ||
1114 | efx->membase = ioremap_wc(efx->membase_phys, | ||
1115 | efx->type->mem_map_size); | ||
1116 | else | ||
1117 | efx->membase = ioremap_nocache(efx->membase_phys, | ||
1118 | efx->type->mem_map_size); | ||
1119 | if (!efx->membase) { | 1105 | if (!efx->membase) { |
1120 | netif_err(efx, probe, efx->net_dev, | 1106 | netif_err(efx, probe, efx->net_dev, |
1121 | "could not map memory BAR at %llx+%x\n", | 1107 | "could not map memory BAR at %llx+%x\n", |
diff --git a/drivers/net/sfc/io.h b/drivers/net/sfc/io.h index cc978803d484..751d1ec112cc 100644 --- a/drivers/net/sfc/io.h +++ b/drivers/net/sfc/io.h | |||
@@ -103,7 +103,6 @@ static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value, | |||
103 | _efx_writed(efx, value->u32[2], reg + 8); | 103 | _efx_writed(efx, value->u32[2], reg + 8); |
104 | _efx_writed(efx, value->u32[3], reg + 12); | 104 | _efx_writed(efx, value->u32[3], reg + 12); |
105 | #endif | 105 | #endif |
106 | wmb(); | ||
107 | mmiowb(); | 106 | mmiowb(); |
108 | spin_unlock_irqrestore(&efx->biu_lock, flags); | 107 | spin_unlock_irqrestore(&efx->biu_lock, flags); |
109 | } | 108 | } |
@@ -126,7 +125,6 @@ static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, | |||
126 | __raw_writel((__force u32)value->u32[0], membase + addr); | 125 | __raw_writel((__force u32)value->u32[0], membase + addr); |
127 | __raw_writel((__force u32)value->u32[1], membase + addr + 4); | 126 | __raw_writel((__force u32)value->u32[1], membase + addr + 4); |
128 | #endif | 127 | #endif |
129 | wmb(); | ||
130 | mmiowb(); | 128 | mmiowb(); |
131 | spin_unlock_irqrestore(&efx->biu_lock, flags); | 129 | spin_unlock_irqrestore(&efx->biu_lock, flags); |
132 | } | 130 | } |
@@ -141,7 +139,6 @@ static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value, | |||
141 | 139 | ||
142 | /* No lock required */ | 140 | /* No lock required */ |
143 | _efx_writed(efx, value->u32[0], reg); | 141 | _efx_writed(efx, value->u32[0], reg); |
144 | wmb(); | ||
145 | } | 142 | } |
146 | 143 | ||
147 | /* Read a 128-bit CSR, locking as appropriate. */ | 144 | /* Read a 128-bit CSR, locking as appropriate. */ |
@@ -152,7 +149,6 @@ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value, | |||
152 | 149 | ||
153 | spin_lock_irqsave(&efx->biu_lock, flags); | 150 | spin_lock_irqsave(&efx->biu_lock, flags); |
154 | value->u32[0] = _efx_readd(efx, reg + 0); | 151 | value->u32[0] = _efx_readd(efx, reg + 0); |
155 | rmb(); | ||
156 | value->u32[1] = _efx_readd(efx, reg + 4); | 152 | value->u32[1] = _efx_readd(efx, reg + 4); |
157 | value->u32[2] = _efx_readd(efx, reg + 8); | 153 | value->u32[2] = _efx_readd(efx, reg + 8); |
158 | value->u32[3] = _efx_readd(efx, reg + 12); | 154 | value->u32[3] = _efx_readd(efx, reg + 12); |
@@ -175,7 +171,6 @@ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, | |||
175 | value->u64[0] = (__force __le64)__raw_readq(membase + addr); | 171 | value->u64[0] = (__force __le64)__raw_readq(membase + addr); |
176 | #else | 172 | #else |
177 | value->u32[0] = (__force __le32)__raw_readl(membase + addr); | 173 | value->u32[0] = (__force __le32)__raw_readl(membase + addr); |
178 | rmb(); | ||
179 | value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); | 174 | value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4); |
180 | #endif | 175 | #endif |
181 | spin_unlock_irqrestore(&efx->biu_lock, flags); | 176 | spin_unlock_irqrestore(&efx->biu_lock, flags); |
@@ -249,7 +244,6 @@ static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value, | |||
249 | _efx_writed(efx, value->u32[2], reg + 8); | 244 | _efx_writed(efx, value->u32[2], reg + 8); |
250 | _efx_writed(efx, value->u32[3], reg + 12); | 245 | _efx_writed(efx, value->u32[3], reg + 12); |
251 | #endif | 246 | #endif |
252 | wmb(); | ||
253 | } | 247 | } |
254 | #define efx_writeo_page(efx, value, reg, page) \ | 248 | #define efx_writeo_page(efx, value, reg, page) \ |
255 | _efx_writeo_page(efx, value, \ | 249 | _efx_writeo_page(efx, value, \ |
diff --git a/drivers/net/sfc/mcdi.c b/drivers/net/sfc/mcdi.c index 3dd45ed61f0a..81a425397468 100644 --- a/drivers/net/sfc/mcdi.c +++ b/drivers/net/sfc/mcdi.c | |||
@@ -50,20 +50,6 @@ static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx) | |||
50 | return &nic_data->mcdi; | 50 | return &nic_data->mcdi; |
51 | } | 51 | } |
52 | 52 | ||
53 | static inline void | ||
54 | efx_mcdi_readd(struct efx_nic *efx, efx_dword_t *value, unsigned reg) | ||
55 | { | ||
56 | struct siena_nic_data *nic_data = efx->nic_data; | ||
57 | value->u32[0] = (__force __le32)__raw_readl(nic_data->mcdi_smem + reg); | ||
58 | } | ||
59 | |||
60 | static inline void | ||
61 | efx_mcdi_writed(struct efx_nic *efx, const efx_dword_t *value, unsigned reg) | ||
62 | { | ||
63 | struct siena_nic_data *nic_data = efx->nic_data; | ||
64 | __raw_writel((__force u32)value->u32[0], nic_data->mcdi_smem + reg); | ||
65 | } | ||
66 | |||
67 | void efx_mcdi_init(struct efx_nic *efx) | 53 | void efx_mcdi_init(struct efx_nic *efx) |
68 | { | 54 | { |
69 | struct efx_mcdi_iface *mcdi; | 55 | struct efx_mcdi_iface *mcdi; |
@@ -84,8 +70,8 @@ static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd, | |||
84 | const u8 *inbuf, size_t inlen) | 70 | const u8 *inbuf, size_t inlen) |
85 | { | 71 | { |
86 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | 72 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); |
87 | unsigned pdu = MCDI_PDU(efx); | 73 | unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); |
88 | unsigned doorbell = MCDI_DOORBELL(efx); | 74 | unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx); |
89 | unsigned int i; | 75 | unsigned int i; |
90 | efx_dword_t hdr; | 76 | efx_dword_t hdr; |
91 | u32 xflags, seqno; | 77 | u32 xflags, seqno; |
@@ -106,28 +92,29 @@ static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd, | |||
106 | MCDI_HEADER_SEQ, seqno, | 92 | MCDI_HEADER_SEQ, seqno, |
107 | MCDI_HEADER_XFLAGS, xflags); | 93 | MCDI_HEADER_XFLAGS, xflags); |
108 | 94 | ||
109 | efx_mcdi_writed(efx, &hdr, pdu); | 95 | efx_writed(efx, &hdr, pdu); |
110 | 96 | ||
111 | for (i = 0; i < inlen; i += 4) | 97 | for (i = 0; i < inlen; i += 4) |
112 | efx_mcdi_writed(efx, (const efx_dword_t *)(inbuf + i), | 98 | _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i); |
113 | pdu + 4 + i); | 99 | |
100 | /* Ensure the payload is written out before the header */ | ||
101 | wmb(); | ||
114 | 102 | ||
115 | /* ring the doorbell with a distinctive value */ | 103 | /* ring the doorbell with a distinctive value */ |
116 | EFX_POPULATE_DWORD_1(hdr, EFX_DWORD_0, 0x45789abc); | 104 | _efx_writed(efx, (__force __le32) 0x45789abc, doorbell); |
117 | efx_mcdi_writed(efx, &hdr, doorbell); | ||
118 | } | 105 | } |
119 | 106 | ||
120 | static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen) | 107 | static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen) |
121 | { | 108 | { |
122 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | 109 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); |
123 | unsigned int pdu = MCDI_PDU(efx); | 110 | unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); |
124 | int i; | 111 | int i; |
125 | 112 | ||
126 | BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT); | 113 | BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT); |
127 | BUG_ON(outlen & 3 || outlen >= 0x100); | 114 | BUG_ON(outlen & 3 || outlen >= 0x100); |
128 | 115 | ||
129 | for (i = 0; i < outlen; i += 4) | 116 | for (i = 0; i < outlen; i += 4) |
130 | efx_mcdi_readd(efx, (efx_dword_t *)(outbuf + i), pdu + 4 + i); | 117 | *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i); |
131 | } | 118 | } |
132 | 119 | ||
133 | static int efx_mcdi_poll(struct efx_nic *efx) | 120 | static int efx_mcdi_poll(struct efx_nic *efx) |
@@ -135,7 +122,7 @@ static int efx_mcdi_poll(struct efx_nic *efx) | |||
135 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); | 122 | struct efx_mcdi_iface *mcdi = efx_mcdi(efx); |
136 | unsigned int time, finish; | 123 | unsigned int time, finish; |
137 | unsigned int respseq, respcmd, error; | 124 | unsigned int respseq, respcmd, error; |
138 | unsigned int pdu = MCDI_PDU(efx); | 125 | unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx); |
139 | unsigned int rc, spins; | 126 | unsigned int rc, spins; |
140 | efx_dword_t reg; | 127 | efx_dword_t reg; |
141 | 128 | ||
@@ -161,7 +148,8 @@ static int efx_mcdi_poll(struct efx_nic *efx) | |||
161 | 148 | ||
162 | time = get_seconds(); | 149 | time = get_seconds(); |
163 | 150 | ||
164 | efx_mcdi_readd(efx, ®, pdu); | 151 | rmb(); |
152 | efx_readd(efx, ®, pdu); | ||
165 | 153 | ||
166 | /* All 1's indicates that shared memory is in reset (and is | 154 | /* All 1's indicates that shared memory is in reset (and is |
167 | * not a valid header). Wait for it to come out reset before | 155 | * not a valid header). Wait for it to come out reset before |
@@ -188,7 +176,7 @@ static int efx_mcdi_poll(struct efx_nic *efx) | |||
188 | respseq, mcdi->seqno); | 176 | respseq, mcdi->seqno); |
189 | rc = EIO; | 177 | rc = EIO; |
190 | } else if (error) { | 178 | } else if (error) { |
191 | efx_mcdi_readd(efx, ®, pdu + 4); | 179 | efx_readd(efx, ®, pdu + 4); |
192 | switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) { | 180 | switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) { |
193 | #define TRANSLATE_ERROR(name) \ | 181 | #define TRANSLATE_ERROR(name) \ |
194 | case MC_CMD_ERR_ ## name: \ | 182 | case MC_CMD_ERR_ ## name: \ |
@@ -222,21 +210,21 @@ out: | |||
222 | /* Test and clear MC-rebooted flag for this port/function */ | 210 | /* Test and clear MC-rebooted flag for this port/function */ |
223 | int efx_mcdi_poll_reboot(struct efx_nic *efx) | 211 | int efx_mcdi_poll_reboot(struct efx_nic *efx) |
224 | { | 212 | { |
225 | unsigned int addr = MCDI_REBOOT_FLAG(efx); | 213 | unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_REBOOT_FLAG(efx); |
226 | efx_dword_t reg; | 214 | efx_dword_t reg; |
227 | uint32_t value; | 215 | uint32_t value; |
228 | 216 | ||
229 | if (efx_nic_rev(efx) < EFX_REV_SIENA_A0) | 217 | if (efx_nic_rev(efx) < EFX_REV_SIENA_A0) |
230 | return false; | 218 | return false; |
231 | 219 | ||
232 | efx_mcdi_readd(efx, ®, addr); | 220 | efx_readd(efx, ®, addr); |
233 | value = EFX_DWORD_FIELD(reg, EFX_DWORD_0); | 221 | value = EFX_DWORD_FIELD(reg, EFX_DWORD_0); |
234 | 222 | ||
235 | if (value == 0) | 223 | if (value == 0) |
236 | return 0; | 224 | return 0; |
237 | 225 | ||
238 | EFX_ZERO_DWORD(reg); | 226 | EFX_ZERO_DWORD(reg); |
239 | efx_mcdi_writed(efx, ®, addr); | 227 | efx_writed(efx, ®, addr); |
240 | 228 | ||
241 | if (value == MC_STATUS_DWORD_ASSERT) | 229 | if (value == MC_STATUS_DWORD_ASSERT) |
242 | return -EINTR; | 230 | return -EINTR; |
diff --git a/drivers/net/sfc/nic.c b/drivers/net/sfc/nic.c index bafa23a6874c..3edfbaf5f022 100644 --- a/drivers/net/sfc/nic.c +++ b/drivers/net/sfc/nic.c | |||
@@ -1936,13 +1936,6 @@ void efx_nic_get_regs(struct efx_nic *efx, void *buf) | |||
1936 | 1936 | ||
1937 | size = min_t(size_t, table->step, 16); | 1937 | size = min_t(size_t, table->step, 16); |
1938 | 1938 | ||
1939 | if (table->offset >= efx->type->mem_map_size) { | ||
1940 | /* No longer mapped; return dummy data */ | ||
1941 | memcpy(buf, "\xde\xc0\xad\xde", 4); | ||
1942 | buf += table->rows * size; | ||
1943 | continue; | ||
1944 | } | ||
1945 | |||
1946 | for (i = 0; i < table->rows; i++) { | 1939 | for (i = 0; i < table->rows; i++) { |
1947 | switch (table->step) { | 1940 | switch (table->step) { |
1948 | case 4: /* 32-bit register or SRAM */ | 1941 | case 4: /* 32-bit register or SRAM */ |
diff --git a/drivers/net/sfc/nic.h b/drivers/net/sfc/nic.h index 4bd1f2839dfe..7443f99c977f 100644 --- a/drivers/net/sfc/nic.h +++ b/drivers/net/sfc/nic.h | |||
@@ -143,12 +143,10 @@ static inline struct falcon_board *falcon_board(struct efx_nic *efx) | |||
143 | /** | 143 | /** |
144 | * struct siena_nic_data - Siena NIC state | 144 | * struct siena_nic_data - Siena NIC state |
145 | * @mcdi: Management-Controller-to-Driver Interface | 145 | * @mcdi: Management-Controller-to-Driver Interface |
146 | * @mcdi_smem: MCDI shared memory mapping. The mapping is always uncacheable. | ||
147 | * @wol_filter_id: Wake-on-LAN packet filter id | 146 | * @wol_filter_id: Wake-on-LAN packet filter id |
148 | */ | 147 | */ |
149 | struct siena_nic_data { | 148 | struct siena_nic_data { |
150 | struct efx_mcdi_iface mcdi; | 149 | struct efx_mcdi_iface mcdi; |
151 | void __iomem *mcdi_smem; | ||
152 | int wol_filter_id; | 150 | int wol_filter_id; |
153 | }; | 151 | }; |
154 | 152 | ||
diff --git a/drivers/net/sfc/siena.c b/drivers/net/sfc/siena.c index 5735e84c69de..2c3bd93fab54 100644 --- a/drivers/net/sfc/siena.c +++ b/drivers/net/sfc/siena.c | |||
@@ -250,26 +250,12 @@ static int siena_probe_nic(struct efx_nic *efx) | |||
250 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); | 250 | efx_reado(efx, ®, FR_AZ_CS_DEBUG); |
251 | efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; | 251 | efx->net_dev->dev_id = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1; |
252 | 252 | ||
253 | /* Initialise MCDI */ | ||
254 | nic_data->mcdi_smem = ioremap_nocache(efx->membase_phys + | ||
255 | FR_CZ_MC_TREG_SMEM, | ||
256 | FR_CZ_MC_TREG_SMEM_STEP * | ||
257 | FR_CZ_MC_TREG_SMEM_ROWS); | ||
258 | if (!nic_data->mcdi_smem) { | ||
259 | netif_err(efx, probe, efx->net_dev, | ||
260 | "could not map MCDI at %llx+%x\n", | ||
261 | (unsigned long long)efx->membase_phys + | ||
262 | FR_CZ_MC_TREG_SMEM, | ||
263 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS); | ||
264 | rc = -ENOMEM; | ||
265 | goto fail1; | ||
266 | } | ||
267 | efx_mcdi_init(efx); | 253 | efx_mcdi_init(efx); |
268 | 254 | ||
269 | /* Recover from a failed assertion before probing */ | 255 | /* Recover from a failed assertion before probing */ |
270 | rc = efx_mcdi_handle_assertion(efx); | 256 | rc = efx_mcdi_handle_assertion(efx); |
271 | if (rc) | 257 | if (rc) |
272 | goto fail2; | 258 | goto fail1; |
273 | 259 | ||
274 | /* Let the BMC know that the driver is now in charge of link and | 260 | /* Let the BMC know that the driver is now in charge of link and |
275 | * filter settings. We must do this before we reset the NIC */ | 261 | * filter settings. We must do this before we reset the NIC */ |
@@ -324,7 +310,6 @@ fail4: | |||
324 | fail3: | 310 | fail3: |
325 | efx_mcdi_drv_attach(efx, false, NULL); | 311 | efx_mcdi_drv_attach(efx, false, NULL); |
326 | fail2: | 312 | fail2: |
327 | iounmap(nic_data->mcdi_smem); | ||
328 | fail1: | 313 | fail1: |
329 | kfree(efx->nic_data); | 314 | kfree(efx->nic_data); |
330 | return rc; | 315 | return rc; |
@@ -404,8 +389,6 @@ static int siena_init_nic(struct efx_nic *efx) | |||
404 | 389 | ||
405 | static void siena_remove_nic(struct efx_nic *efx) | 390 | static void siena_remove_nic(struct efx_nic *efx) |
406 | { | 391 | { |
407 | struct siena_nic_data *nic_data = efx->nic_data; | ||
408 | |||
409 | efx_nic_free_buffer(efx, &efx->irq_status); | 392 | efx_nic_free_buffer(efx, &efx->irq_status); |
410 | 393 | ||
411 | siena_reset_hw(efx, RESET_TYPE_ALL); | 394 | siena_reset_hw(efx, RESET_TYPE_ALL); |
@@ -415,8 +398,7 @@ static void siena_remove_nic(struct efx_nic *efx) | |||
415 | efx_mcdi_drv_attach(efx, false, NULL); | 398 | efx_mcdi_drv_attach(efx, false, NULL); |
416 | 399 | ||
417 | /* Tear down the private nic state */ | 400 | /* Tear down the private nic state */ |
418 | iounmap(nic_data->mcdi_smem); | 401 | kfree(efx->nic_data); |
419 | kfree(nic_data); | ||
420 | efx->nic_data = NULL; | 402 | efx->nic_data = NULL; |
421 | } | 403 | } |
422 | 404 | ||
@@ -656,7 +638,8 @@ const struct efx_nic_type siena_a0_nic_type = { | |||
656 | .default_mac_ops = &efx_mcdi_mac_operations, | 638 | .default_mac_ops = &efx_mcdi_mac_operations, |
657 | 639 | ||
658 | .revision = EFX_REV_SIENA_A0, | 640 | .revision = EFX_REV_SIENA_A0, |
659 | .mem_map_size = FR_CZ_MC_TREG_SMEM, /* MC_TREG_SMEM mapped separately */ | 641 | .mem_map_size = (FR_CZ_MC_TREG_SMEM + |
642 | FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS), | ||
660 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | 643 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
661 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | 644 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, |
662 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | 645 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, |
diff --git a/drivers/net/sfc/workarounds.h b/drivers/net/sfc/workarounds.h index 99ff11400cef..e4dd3a7f304b 100644 --- a/drivers/net/sfc/workarounds.h +++ b/drivers/net/sfc/workarounds.h | |||
@@ -38,8 +38,6 @@ | |||
38 | #define EFX_WORKAROUND_15783 EFX_WORKAROUND_ALWAYS | 38 | #define EFX_WORKAROUND_15783 EFX_WORKAROUND_ALWAYS |
39 | /* Legacy interrupt storm when interrupt fifo fills */ | 39 | /* Legacy interrupt storm when interrupt fifo fills */ |
40 | #define EFX_WORKAROUND_17213 EFX_WORKAROUND_SIENA | 40 | #define EFX_WORKAROUND_17213 EFX_WORKAROUND_SIENA |
41 | /* Write combining and sriov=enabled are incompatible */ | ||
42 | #define EFX_WORKAROUND_22643 EFX_WORKAROUND_SIENA | ||
43 | 41 | ||
44 | /* Spurious parity errors in TSORT buffers */ | 42 | /* Spurious parity errors in TSORT buffers */ |
45 | #define EFX_WORKAROUND_5129 EFX_WORKAROUND_FALCON_A | 43 | #define EFX_WORKAROUND_5129 EFX_WORKAROUND_FALCON_A |
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 190f619e4215..1c1666e99106 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <linux/phy.h> | 31 | #include <linux/phy.h> |
32 | #include <linux/cache.h> | 32 | #include <linux/cache.h> |
33 | #include <linux/io.h> | 33 | #include <linux/io.h> |
34 | #include <linux/interrupt.h> | ||
34 | #include <linux/pm_runtime.h> | 35 | #include <linux/pm_runtime.h> |
35 | #include <linux/slab.h> | 36 | #include <linux/slab.h> |
36 | #include <linux/ethtool.h> | 37 | #include <linux/ethtool.h> |
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index dc3fbf61910b..4a1374df6084 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -6234,12 +6234,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
6234 | } | 6234 | } |
6235 | } | 6235 | } |
6236 | 6236 | ||
6237 | #ifdef BCM_KERNEL_SUPPORTS_8021Q | ||
6238 | if (vlan_tx_tag_present(skb)) { | 6237 | if (vlan_tx_tag_present(skb)) { |
6239 | base_flags |= TXD_FLAG_VLAN; | 6238 | base_flags |= TXD_FLAG_VLAN; |
6240 | vlan = vlan_tx_tag_get(skb); | 6239 | vlan = vlan_tx_tag_get(skb); |
6241 | } | 6240 | } |
6242 | #endif | ||
6243 | 6241 | ||
6244 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && | 6242 | if (tg3_flag(tp, USE_JUMBO_BDFLAG) && |
6245 | !mss && skb->len > VLAN_ETH_FRAME_LEN) | 6243 | !mss && skb->len > VLAN_ETH_FRAME_LEN) |
diff --git a/drivers/net/usb/ipheth.c b/drivers/net/usb/ipheth.c index 15772b1b6a91..13c1f044b40d 100644 --- a/drivers/net/usb/ipheth.c +++ b/drivers/net/usb/ipheth.c | |||
@@ -59,6 +59,7 @@ | |||
59 | #define USB_PRODUCT_IPHONE_3G 0x1292 | 59 | #define USB_PRODUCT_IPHONE_3G 0x1292 |
60 | #define USB_PRODUCT_IPHONE_3GS 0x1294 | 60 | #define USB_PRODUCT_IPHONE_3GS 0x1294 |
61 | #define USB_PRODUCT_IPHONE_4 0x1297 | 61 | #define USB_PRODUCT_IPHONE_4 0x1297 |
62 | #define USB_PRODUCT_IPHONE_4_VZW 0x129c | ||
62 | 63 | ||
63 | #define IPHETH_USBINTF_CLASS 255 | 64 | #define IPHETH_USBINTF_CLASS 255 |
64 | #define IPHETH_USBINTF_SUBCLASS 253 | 65 | #define IPHETH_USBINTF_SUBCLASS 253 |
@@ -98,6 +99,10 @@ static struct usb_device_id ipheth_table[] = { | |||
98 | USB_VENDOR_APPLE, USB_PRODUCT_IPHONE_4, | 99 | USB_VENDOR_APPLE, USB_PRODUCT_IPHONE_4, |
99 | IPHETH_USBINTF_CLASS, IPHETH_USBINTF_SUBCLASS, | 100 | IPHETH_USBINTF_CLASS, IPHETH_USBINTF_SUBCLASS, |
100 | IPHETH_USBINTF_PROTO) }, | 101 | IPHETH_USBINTF_PROTO) }, |
102 | { USB_DEVICE_AND_INTERFACE_INFO( | ||
103 | USB_VENDOR_APPLE, USB_PRODUCT_IPHONE_4_VZW, | ||
104 | IPHETH_USBINTF_CLASS, IPHETH_USBINTF_SUBCLASS, | ||
105 | IPHETH_USBINTF_PROTO) }, | ||
101 | { } | 106 | { } |
102 | }; | 107 | }; |
103 | MODULE_DEVICE_TABLE(usb, ipheth_table); | 108 | MODULE_DEVICE_TABLE(usb, ipheth_table); |
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_calib.c b/drivers/net/wireless/ath/ath9k/ar9002_calib.c index 2d4c0910295b..2d394af82171 100644 --- a/drivers/net/wireless/ath/ath9k/ar9002_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9002_calib.c | |||
@@ -41,7 +41,8 @@ static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, | |||
41 | case ADC_DC_CAL: | 41 | case ADC_DC_CAL: |
42 | /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */ | 42 | /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */ |
43 | if (!IS_CHAN_B(chan) && | 43 | if (!IS_CHAN_B(chan) && |
44 | !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan))) | 44 | !((IS_CHAN_2GHZ(chan) || IS_CHAN_A_FAST_CLOCK(ah, chan)) && |
45 | IS_CHAN_HT20(chan))) | ||
45 | supported = true; | 46 | supported = true; |
46 | break; | 47 | break; |
47 | } | 48 | } |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index c34bef1bf2b0..1b9400371eaf 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c | |||
@@ -69,7 +69,7 @@ static int ar9003_hw_power_interpolate(int32_t x, | |||
69 | static const struct ar9300_eeprom ar9300_default = { | 69 | static const struct ar9300_eeprom ar9300_default = { |
70 | .eepromVersion = 2, | 70 | .eepromVersion = 2, |
71 | .templateVersion = 2, | 71 | .templateVersion = 2, |
72 | .macAddr = {1, 2, 3, 4, 5, 6}, | 72 | .macAddr = {0, 2, 3, 4, 5, 6}, |
73 | .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 73 | .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
74 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, | 74 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, |
75 | .baseEepHeader = { | 75 | .baseEepHeader = { |
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index 1baca8e4715d..fcafec0605f4 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c | |||
@@ -671,7 +671,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, | |||
671 | REG_WRITE_ARRAY(&ah->iniModesAdditional, | 671 | REG_WRITE_ARRAY(&ah->iniModesAdditional, |
672 | modesIndex, regWrites); | 672 | modesIndex, regWrites); |
673 | 673 | ||
674 | if (AR_SREV_9300(ah)) | 674 | if (AR_SREV_9330(ah)) |
675 | REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); | 675 | REG_WRITE_ARRAY(&ah->iniModesAdditional, 1, regWrites); |
676 | 676 | ||
677 | if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) | 677 | if (AR_SREV_9340(ah) && !ah->is_clk_25mhz) |
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index 9098aaad97a9..722967b86cf1 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c | |||
@@ -2283,7 +2283,11 @@ static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) | |||
2283 | 2283 | ||
2284 | mutex_lock(&sc->mutex); | 2284 | mutex_lock(&sc->mutex); |
2285 | ah->coverage_class = coverage_class; | 2285 | ah->coverage_class = coverage_class; |
2286 | |||
2287 | ath9k_ps_wakeup(sc); | ||
2286 | ath9k_hw_init_global_settings(ah); | 2288 | ath9k_hw_init_global_settings(ah); |
2289 | ath9k_ps_restore(sc); | ||
2290 | |||
2287 | mutex_unlock(&sc->mutex); | 2291 | mutex_unlock(&sc->mutex); |
2288 | } | 2292 | } |
2289 | 2293 | ||
@@ -2299,6 +2303,12 @@ static void ath9k_flush(struct ieee80211_hw *hw, bool drop) | |||
2299 | mutex_lock(&sc->mutex); | 2303 | mutex_lock(&sc->mutex); |
2300 | cancel_delayed_work_sync(&sc->tx_complete_work); | 2304 | cancel_delayed_work_sync(&sc->tx_complete_work); |
2301 | 2305 | ||
2306 | if (ah->ah_flags & AH_UNPLUGGED) { | ||
2307 | ath_dbg(common, ATH_DBG_ANY, "Device has been unplugged!\n"); | ||
2308 | mutex_unlock(&sc->mutex); | ||
2309 | return; | ||
2310 | } | ||
2311 | |||
2302 | if (sc->sc_flags & SC_OP_INVALID) { | 2312 | if (sc->sc_flags & SC_OP_INVALID) { |
2303 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); | 2313 | ath_dbg(common, ATH_DBG_ANY, "Device not present\n"); |
2304 | mutex_unlock(&sc->mutex); | 2314 | mutex_unlock(&sc->mutex); |
diff --git a/drivers/net/wireless/ath/carl9170/main.c b/drivers/net/wireless/ath/carl9170/main.c index 0122930b14c7..0474e6638d21 100644 --- a/drivers/net/wireless/ath/carl9170/main.c +++ b/drivers/net/wireless/ath/carl9170/main.c | |||
@@ -1066,8 +1066,10 @@ static int carl9170_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
1066 | * the high througput speed in 802.11n networks. | 1066 | * the high througput speed in 802.11n networks. |
1067 | */ | 1067 | */ |
1068 | 1068 | ||
1069 | if (!is_main_vif(ar, vif)) | 1069 | if (!is_main_vif(ar, vif)) { |
1070 | mutex_lock(&ar->mutex); | ||
1070 | goto err_softw; | 1071 | goto err_softw; |
1072 | } | ||
1071 | 1073 | ||
1072 | /* | 1074 | /* |
1073 | * While the hardware supports *catch-all* key, for offloading | 1075 | * While the hardware supports *catch-all* key, for offloading |
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c index 26f1ab840cc7..e293a7921bf0 100644 --- a/drivers/net/wireless/b43/main.c +++ b/drivers/net/wireless/b43/main.c | |||
@@ -1632,7 +1632,8 @@ static void handle_irq_beacon(struct b43_wldev *dev) | |||
1632 | u32 cmd, beacon0_valid, beacon1_valid; | 1632 | u32 cmd, beacon0_valid, beacon1_valid; |
1633 | 1633 | ||
1634 | if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && | 1634 | if (!b43_is_mode(wl, NL80211_IFTYPE_AP) && |
1635 | !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) | 1635 | !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) && |
1636 | !b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) | ||
1636 | return; | 1637 | return; |
1637 | 1638 | ||
1638 | /* This is the bottom half of the asynchronous beacon update. */ | 1639 | /* This is the bottom half of the asynchronous beacon update. */ |
diff --git a/drivers/net/wireless/ipw2x00/ipw2100.c b/drivers/net/wireless/ipw2x00/ipw2100.c index 3774dd034746..ef9ad79d1bfd 100644 --- a/drivers/net/wireless/ipw2x00/ipw2100.c +++ b/drivers/net/wireless/ipw2x00/ipw2100.c | |||
@@ -1903,15 +1903,17 @@ static void ipw2100_down(struct ipw2100_priv *priv) | |||
1903 | static int ipw2100_net_init(struct net_device *dev) | 1903 | static int ipw2100_net_init(struct net_device *dev) |
1904 | { | 1904 | { |
1905 | struct ipw2100_priv *priv = libipw_priv(dev); | 1905 | struct ipw2100_priv *priv = libipw_priv(dev); |
1906 | |||
1907 | return ipw2100_up(priv, 1); | ||
1908 | } | ||
1909 | |||
1910 | static int ipw2100_wdev_init(struct net_device *dev) | ||
1911 | { | ||
1912 | struct ipw2100_priv *priv = libipw_priv(dev); | ||
1906 | const struct libipw_geo *geo = libipw_get_geo(priv->ieee); | 1913 | const struct libipw_geo *geo = libipw_get_geo(priv->ieee); |
1907 | struct wireless_dev *wdev = &priv->ieee->wdev; | 1914 | struct wireless_dev *wdev = &priv->ieee->wdev; |
1908 | int ret; | ||
1909 | int i; | 1915 | int i; |
1910 | 1916 | ||
1911 | ret = ipw2100_up(priv, 1); | ||
1912 | if (ret) | ||
1913 | return ret; | ||
1914 | |||
1915 | memcpy(wdev->wiphy->perm_addr, priv->mac_addr, ETH_ALEN); | 1917 | memcpy(wdev->wiphy->perm_addr, priv->mac_addr, ETH_ALEN); |
1916 | 1918 | ||
1917 | /* fill-out priv->ieee->bg_band */ | 1919 | /* fill-out priv->ieee->bg_band */ |
@@ -6350,9 +6352,13 @@ static int ipw2100_pci_init_one(struct pci_dev *pci_dev, | |||
6350 | "Error calling register_netdev.\n"); | 6352 | "Error calling register_netdev.\n"); |
6351 | goto fail; | 6353 | goto fail; |
6352 | } | 6354 | } |
6355 | registered = 1; | ||
6356 | |||
6357 | err = ipw2100_wdev_init(dev); | ||
6358 | if (err) | ||
6359 | goto fail; | ||
6353 | 6360 | ||
6354 | mutex_lock(&priv->action_mutex); | 6361 | mutex_lock(&priv->action_mutex); |
6355 | registered = 1; | ||
6356 | 6362 | ||
6357 | IPW_DEBUG_INFO("%s: Bound to %s\n", dev->name, pci_name(pci_dev)); | 6363 | IPW_DEBUG_INFO("%s: Bound to %s\n", dev->name, pci_name(pci_dev)); |
6358 | 6364 | ||
@@ -6389,7 +6395,8 @@ static int ipw2100_pci_init_one(struct pci_dev *pci_dev, | |||
6389 | 6395 | ||
6390 | fail_unlock: | 6396 | fail_unlock: |
6391 | mutex_unlock(&priv->action_mutex); | 6397 | mutex_unlock(&priv->action_mutex); |
6392 | 6398 | wiphy_unregister(priv->ieee->wdev.wiphy); | |
6399 | kfree(priv->ieee->bg_band.channels); | ||
6393 | fail: | 6400 | fail: |
6394 | if (dev) { | 6401 | if (dev) { |
6395 | if (registered) | 6402 | if (registered) |
diff --git a/drivers/net/wireless/ipw2x00/ipw2200.c b/drivers/net/wireless/ipw2x00/ipw2200.c index 87813c33bdc2..4ffebede5e03 100644 --- a/drivers/net/wireless/ipw2x00/ipw2200.c +++ b/drivers/net/wireless/ipw2x00/ipw2200.c | |||
@@ -11425,16 +11425,23 @@ static void ipw_bg_down(struct work_struct *work) | |||
11425 | /* Called by register_netdev() */ | 11425 | /* Called by register_netdev() */ |
11426 | static int ipw_net_init(struct net_device *dev) | 11426 | static int ipw_net_init(struct net_device *dev) |
11427 | { | 11427 | { |
11428 | int rc = 0; | ||
11429 | struct ipw_priv *priv = libipw_priv(dev); | ||
11430 | |||
11431 | mutex_lock(&priv->mutex); | ||
11432 | if (ipw_up(priv)) | ||
11433 | rc = -EIO; | ||
11434 | mutex_unlock(&priv->mutex); | ||
11435 | |||
11436 | return rc; | ||
11437 | } | ||
11438 | |||
11439 | static int ipw_wdev_init(struct net_device *dev) | ||
11440 | { | ||
11428 | int i, rc = 0; | 11441 | int i, rc = 0; |
11429 | struct ipw_priv *priv = libipw_priv(dev); | 11442 | struct ipw_priv *priv = libipw_priv(dev); |
11430 | const struct libipw_geo *geo = libipw_get_geo(priv->ieee); | 11443 | const struct libipw_geo *geo = libipw_get_geo(priv->ieee); |
11431 | struct wireless_dev *wdev = &priv->ieee->wdev; | 11444 | struct wireless_dev *wdev = &priv->ieee->wdev; |
11432 | mutex_lock(&priv->mutex); | ||
11433 | |||
11434 | if (ipw_up(priv)) { | ||
11435 | rc = -EIO; | ||
11436 | goto out; | ||
11437 | } | ||
11438 | 11445 | ||
11439 | memcpy(wdev->wiphy->perm_addr, priv->mac_addr, ETH_ALEN); | 11446 | memcpy(wdev->wiphy->perm_addr, priv->mac_addr, ETH_ALEN); |
11440 | 11447 | ||
@@ -11519,13 +11526,9 @@ static int ipw_net_init(struct net_device *dev) | |||
11519 | set_wiphy_dev(wdev->wiphy, &priv->pci_dev->dev); | 11526 | set_wiphy_dev(wdev->wiphy, &priv->pci_dev->dev); |
11520 | 11527 | ||
11521 | /* With that information in place, we can now register the wiphy... */ | 11528 | /* With that information in place, we can now register the wiphy... */ |
11522 | if (wiphy_register(wdev->wiphy)) { | 11529 | if (wiphy_register(wdev->wiphy)) |
11523 | rc = -EIO; | 11530 | rc = -EIO; |
11524 | goto out; | ||
11525 | } | ||
11526 | |||
11527 | out: | 11531 | out: |
11528 | mutex_unlock(&priv->mutex); | ||
11529 | return rc; | 11532 | return rc; |
11530 | } | 11533 | } |
11531 | 11534 | ||
@@ -11832,14 +11835,22 @@ static int __devinit ipw_pci_probe(struct pci_dev *pdev, | |||
11832 | goto out_remove_sysfs; | 11835 | goto out_remove_sysfs; |
11833 | } | 11836 | } |
11834 | 11837 | ||
11838 | err = ipw_wdev_init(net_dev); | ||
11839 | if (err) { | ||
11840 | IPW_ERROR("failed to register wireless device\n"); | ||
11841 | goto out_unregister_netdev; | ||
11842 | } | ||
11843 | |||
11835 | #ifdef CONFIG_IPW2200_PROMISCUOUS | 11844 | #ifdef CONFIG_IPW2200_PROMISCUOUS |
11836 | if (rtap_iface) { | 11845 | if (rtap_iface) { |
11837 | err = ipw_prom_alloc(priv); | 11846 | err = ipw_prom_alloc(priv); |
11838 | if (err) { | 11847 | if (err) { |
11839 | IPW_ERROR("Failed to register promiscuous network " | 11848 | IPW_ERROR("Failed to register promiscuous network " |
11840 | "device (error %d).\n", err); | 11849 | "device (error %d).\n", err); |
11841 | unregister_netdev(priv->net_dev); | 11850 | wiphy_unregister(priv->ieee->wdev.wiphy); |
11842 | goto out_remove_sysfs; | 11851 | kfree(priv->ieee->a_band.channels); |
11852 | kfree(priv->ieee->bg_band.channels); | ||
11853 | goto out_unregister_netdev; | ||
11843 | } | 11854 | } |
11844 | } | 11855 | } |
11845 | #endif | 11856 | #endif |
@@ -11851,6 +11862,8 @@ static int __devinit ipw_pci_probe(struct pci_dev *pdev, | |||
11851 | 11862 | ||
11852 | return 0; | 11863 | return 0; |
11853 | 11864 | ||
11865 | out_unregister_netdev: | ||
11866 | unregister_netdev(priv->net_dev); | ||
11854 | out_remove_sysfs: | 11867 | out_remove_sysfs: |
11855 | sysfs_remove_group(&pdev->dev.kobj, &ipw_attribute_group); | 11868 | sysfs_remove_group(&pdev->dev.kobj, &ipw_attribute_group); |
11856 | out_release_irq: | 11869 | out_release_irq: |
diff --git a/drivers/net/wireless/iwlegacy/iwl-3945-rs.c b/drivers/net/wireless/iwlegacy/iwl-3945-rs.c index 977bd2477c6a..164bcae821f8 100644 --- a/drivers/net/wireless/iwlegacy/iwl-3945-rs.c +++ b/drivers/net/wireless/iwlegacy/iwl-3945-rs.c | |||
@@ -822,12 +822,15 @@ static void iwl3945_rs_get_rate(void *priv_r, struct ieee80211_sta *sta, | |||
822 | 822 | ||
823 | out: | 823 | out: |
824 | 824 | ||
825 | rs_sta->last_txrate_idx = index; | 825 | if (sband->band == IEEE80211_BAND_5GHZ) { |
826 | if (sband->band == IEEE80211_BAND_5GHZ) | 826 | if (WARN_ON_ONCE(index < IWL_FIRST_OFDM_RATE)) |
827 | info->control.rates[0].idx = rs_sta->last_txrate_idx - | 827 | index = IWL_FIRST_OFDM_RATE; |
828 | IWL_FIRST_OFDM_RATE; | 828 | rs_sta->last_txrate_idx = index; |
829 | else | 829 | info->control.rates[0].idx = index - IWL_FIRST_OFDM_RATE; |
830 | } else { | ||
831 | rs_sta->last_txrate_idx = index; | ||
830 | info->control.rates[0].idx = rs_sta->last_txrate_idx; | 832 | info->control.rates[0].idx = rs_sta->last_txrate_idx; |
833 | } | ||
831 | 834 | ||
832 | IWL_DEBUG_RATE(priv, "leave: %d\n", index); | 835 | IWL_DEBUG_RATE(priv, "leave: %d\n", index); |
833 | } | 836 | } |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c index a895a099d086..56211006a182 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn-ucode.c | |||
@@ -167,7 +167,7 @@ static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv) | |||
167 | 167 | ||
168 | memset(&cmd, 0, sizeof(cmd)); | 168 | memset(&cmd, 0, sizeof(cmd)); |
169 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD); | 169 | iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD); |
170 | memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(offset_calib)); | 170 | memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib)); |
171 | if (!(cmd.radio_sensor_offset)) | 171 | if (!(cmd.radio_sensor_offset)) |
172 | cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET; | 172 | cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET; |
173 | 173 | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index b0ae4de7f083..f9c3cd95d614 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
@@ -2140,7 +2140,12 @@ static int iwl_mac_setup_register(struct iwl_priv *priv, | |||
2140 | IEEE80211_HW_SPECTRUM_MGMT | | 2140 | IEEE80211_HW_SPECTRUM_MGMT | |
2141 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; | 2141 | IEEE80211_HW_REPORTS_TX_ACK_STATUS; |
2142 | 2142 | ||
2143 | /* | ||
2144 | * Including the following line will crash some AP's. This | ||
2145 | * workaround removes the stimulus which causes the crash until | ||
2146 | * the AP software can be fixed. | ||
2143 | hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; | 2147 | hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF; |
2148 | */ | ||
2144 | 2149 | ||
2145 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | | 2150 | hw->flags |= IEEE80211_HW_SUPPORTS_PS | |
2146 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; | 2151 | IEEE80211_HW_SUPPORTS_DYNAMIC_PS; |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c index a6b2b1db0b1d..222d410c586e 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c +++ b/drivers/net/wireless/iwlwifi/iwl-trans-tx-pcie.c | |||
@@ -771,6 +771,8 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb) | |||
771 | cmd = txq->cmd[cmd_index]; | 771 | cmd = txq->cmd[cmd_index]; |
772 | meta = &txq->meta[cmd_index]; | 772 | meta = &txq->meta[cmd_index]; |
773 | 773 | ||
774 | txq->time_stamp = jiffies; | ||
775 | |||
774 | iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); | 776 | iwlagn_unmap_tfd(priv, meta, &txq->tfds[index], DMA_BIDIRECTIONAL); |
775 | 777 | ||
776 | /* Input error checking is done when commands are added to queue. */ | 778 | /* Input error checking is done when commands are added to queue. */ |
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index ef67f6786a84..0019dfd8fb01 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c | |||
@@ -3697,14 +3697,15 @@ static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i) | |||
3697 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); | 3697 | rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, ®); |
3698 | 3698 | ||
3699 | /* Apparently the data is read from end to start */ | 3699 | /* Apparently the data is read from end to start */ |
3700 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, | 3700 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA3, ®); |
3701 | (u32 *)&rt2x00dev->eeprom[i]); | 3701 | /* The returned value is in CPU order, but eeprom is le */ |
3702 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, | 3702 | rt2x00dev->eeprom[i] = cpu_to_le32(reg); |
3703 | (u32 *)&rt2x00dev->eeprom[i + 2]); | 3703 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA2, ®); |
3704 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, | 3704 | *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); |
3705 | (u32 *)&rt2x00dev->eeprom[i + 4]); | 3705 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA1, ®); |
3706 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, | 3706 | *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); |
3707 | (u32 *)&rt2x00dev->eeprom[i + 6]); | 3707 | rt2800_register_read_lock(rt2x00dev, EFUSE_DATA0, ®); |
3708 | *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); | ||
3708 | 3709 | ||
3709 | mutex_unlock(&rt2x00dev->csr_mutex); | 3710 | mutex_unlock(&rt2x00dev->csr_mutex); |
3710 | } | 3711 | } |
@@ -3870,19 +3871,23 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) | |||
3870 | return -ENODEV; | 3871 | return -ENODEV; |
3871 | } | 3872 | } |
3872 | 3873 | ||
3873 | if (!rt2x00_rf(rt2x00dev, RF2820) && | 3874 | switch (rt2x00dev->chip.rf) { |
3874 | !rt2x00_rf(rt2x00dev, RF2850) && | 3875 | case RF2820: |
3875 | !rt2x00_rf(rt2x00dev, RF2720) && | 3876 | case RF2850: |
3876 | !rt2x00_rf(rt2x00dev, RF2750) && | 3877 | case RF2720: |
3877 | !rt2x00_rf(rt2x00dev, RF3020) && | 3878 | case RF2750: |
3878 | !rt2x00_rf(rt2x00dev, RF2020) && | 3879 | case RF3020: |
3879 | !rt2x00_rf(rt2x00dev, RF3021) && | 3880 | case RF2020: |
3880 | !rt2x00_rf(rt2x00dev, RF3022) && | 3881 | case RF3021: |
3881 | !rt2x00_rf(rt2x00dev, RF3052) && | 3882 | case RF3022: |
3882 | !rt2x00_rf(rt2x00dev, RF3320) && | 3883 | case RF3052: |
3883 | !rt2x00_rf(rt2x00dev, RF5370) && | 3884 | case RF3320: |
3884 | !rt2x00_rf(rt2x00dev, RF5390)) { | 3885 | case RF5370: |
3885 | ERROR(rt2x00dev, "Invalid RF chipset detected.\n"); | 3886 | case RF5390: |
3887 | break; | ||
3888 | default: | ||
3889 | ERROR(rt2x00dev, "Invalid RF chipset 0x%x detected.\n", | ||
3890 | rt2x00dev->chip.rf); | ||
3886 | return -ENODEV; | 3891 | return -ENODEV; |
3887 | } | 3892 | } |
3888 | 3893 | ||
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c index 7fbb55c9da82..1e31050dafc9 100644 --- a/drivers/net/wireless/rt2x00/rt2x00usb.c +++ b/drivers/net/wireless/rt2x00/rt2x00usb.c | |||
@@ -871,18 +871,8 @@ int rt2x00usb_suspend(struct usb_interface *usb_intf, pm_message_t state) | |||
871 | { | 871 | { |
872 | struct ieee80211_hw *hw = usb_get_intfdata(usb_intf); | 872 | struct ieee80211_hw *hw = usb_get_intfdata(usb_intf); |
873 | struct rt2x00_dev *rt2x00dev = hw->priv; | 873 | struct rt2x00_dev *rt2x00dev = hw->priv; |
874 | int retval; | ||
875 | |||
876 | retval = rt2x00lib_suspend(rt2x00dev, state); | ||
877 | if (retval) | ||
878 | return retval; | ||
879 | 874 | ||
880 | /* | 875 | return rt2x00lib_suspend(rt2x00dev, state); |
881 | * Decrease usbdev refcount. | ||
882 | */ | ||
883 | usb_put_dev(interface_to_usbdev(usb_intf)); | ||
884 | |||
885 | return 0; | ||
886 | } | 876 | } |
887 | EXPORT_SYMBOL_GPL(rt2x00usb_suspend); | 877 | EXPORT_SYMBOL_GPL(rt2x00usb_suspend); |
888 | 878 | ||
@@ -891,8 +881,6 @@ int rt2x00usb_resume(struct usb_interface *usb_intf) | |||
891 | struct ieee80211_hw *hw = usb_get_intfdata(usb_intf); | 881 | struct ieee80211_hw *hw = usb_get_intfdata(usb_intf); |
892 | struct rt2x00_dev *rt2x00dev = hw->priv; | 882 | struct rt2x00_dev *rt2x00dev = hw->priv; |
893 | 883 | ||
894 | usb_get_dev(interface_to_usbdev(usb_intf)); | ||
895 | |||
896 | return rt2x00lib_resume(rt2x00dev); | 884 | return rt2x00lib_resume(rt2x00dev); |
897 | } | 885 | } |
898 | EXPORT_SYMBOL_GPL(rt2x00usb_resume); | 886 | EXPORT_SYMBOL_GPL(rt2x00usb_resume); |
diff --git a/drivers/net/wireless/rtlwifi/core.c b/drivers/net/wireless/rtlwifi/core.c index 1bdc1aa305c0..04c4e9eb6ee6 100644 --- a/drivers/net/wireless/rtlwifi/core.c +++ b/drivers/net/wireless/rtlwifi/core.c | |||
@@ -610,6 +610,11 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, | |||
610 | 610 | ||
611 | mac->link_state = MAC80211_NOLINK; | 611 | mac->link_state = MAC80211_NOLINK; |
612 | memset(mac->bssid, 0, 6); | 612 | memset(mac->bssid, 0, 6); |
613 | |||
614 | /* reset sec info */ | ||
615 | rtl_cam_reset_sec_info(hw); | ||
616 | |||
617 | rtl_cam_reset_all_entry(hw); | ||
613 | mac->vendor = PEER_UNKNOWN; | 618 | mac->vendor = PEER_UNKNOWN; |
614 | 619 | ||
615 | RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, | 620 | RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, |
@@ -1063,6 +1068,9 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |||
1063 | *or clear all entry here. | 1068 | *or clear all entry here. |
1064 | */ | 1069 | */ |
1065 | rtl_cam_delete_one_entry(hw, mac_addr, key_idx); | 1070 | rtl_cam_delete_one_entry(hw, mac_addr, key_idx); |
1071 | |||
1072 | rtl_cam_reset_sec_info(hw); | ||
1073 | |||
1066 | break; | 1074 | break; |
1067 | default: | 1075 | default: |
1068 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | 1076 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c index 906e7aa55bc3..3e52a5496224 100644 --- a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c +++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c | |||
@@ -549,15 +549,16 @@ void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw, | |||
549 | (tcb_desc->rts_use_shortpreamble ? 1 : 0) | 549 | (tcb_desc->rts_use_shortpreamble ? 1 : 0) |
550 | : (tcb_desc->rts_use_shortgi ? 1 : 0))); | 550 | : (tcb_desc->rts_use_shortgi ? 1 : 0))); |
551 | if (mac->bw_40) { | 551 | if (mac->bw_40) { |
552 | if (tcb_desc->packet_bw) { | 552 | if (rate_flag & IEEE80211_TX_RC_DUP_DATA) { |
553 | SET_TX_DESC_DATA_BW(txdesc, 1); | 553 | SET_TX_DESC_DATA_BW(txdesc, 1); |
554 | SET_TX_DESC_DATA_SC(txdesc, 3); | 554 | SET_TX_DESC_DATA_SC(txdesc, 3); |
555 | } else if(rate_flag & IEEE80211_TX_RC_40_MHZ_WIDTH){ | ||
556 | SET_TX_DESC_DATA_BW(txdesc, 1); | ||
557 | SET_TX_DESC_DATA_SC(txdesc, mac->cur_40_prime_sc); | ||
555 | } else { | 558 | } else { |
556 | SET_TX_DESC_DATA_BW(txdesc, 0); | 559 | SET_TX_DESC_DATA_BW(txdesc, 0); |
557 | if (rate_flag & IEEE80211_TX_RC_DUP_DATA) | 560 | SET_TX_DESC_DATA_SC(txdesc, 0); |
558 | SET_TX_DESC_DATA_SC(txdesc, | 561 | } |
559 | mac->cur_40_prime_sc); | ||
560 | } | ||
561 | } else { | 562 | } else { |
562 | SET_TX_DESC_DATA_BW(txdesc, 0); | 563 | SET_TX_DESC_DATA_BW(txdesc, 0); |
563 | SET_TX_DESC_DATA_SC(txdesc, 0); | 564 | SET_TX_DESC_DATA_SC(txdesc, 0); |
diff --git a/drivers/net/wireless/wl12xx/main.c b/drivers/net/wireless/wl12xx/main.c index e58c22d21e39..b70ae40ad660 100644 --- a/drivers/net/wireless/wl12xx/main.c +++ b/drivers/net/wireless/wl12xx/main.c | |||
@@ -4283,6 +4283,7 @@ int wl1271_init_ieee80211(struct wl1271 *wl) | |||
4283 | wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | | 4283 | wl->hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | |
4284 | BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); | 4284 | BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_AP); |
4285 | wl->hw->wiphy->max_scan_ssids = 1; | 4285 | wl->hw->wiphy->max_scan_ssids = 1; |
4286 | wl->hw->wiphy->max_sched_scan_ssids = 1; | ||
4286 | /* | 4287 | /* |
4287 | * Maximum length of elements in scanning probe request templates | 4288 | * Maximum length of elements in scanning probe request templates |
4288 | * should be the maximum length possible for a template, without | 4289 | * should be the maximum length possible for a template, without |
diff --git a/drivers/net/wireless/wl12xx/sdio.c b/drivers/net/wireless/wl12xx/sdio.c index 5cf18c2c23f0..fb1fd5af75ea 100644 --- a/drivers/net/wireless/wl12xx/sdio.c +++ b/drivers/net/wireless/wl12xx/sdio.c | |||
@@ -164,7 +164,7 @@ static int wl1271_sdio_power_on(struct wl1271 *wl) | |||
164 | /* If enabled, tell runtime PM not to power off the card */ | 164 | /* If enabled, tell runtime PM not to power off the card */ |
165 | if (pm_runtime_enabled(&func->dev)) { | 165 | if (pm_runtime_enabled(&func->dev)) { |
166 | ret = pm_runtime_get_sync(&func->dev); | 166 | ret = pm_runtime_get_sync(&func->dev); |
167 | if (ret) | 167 | if (ret < 0) |
168 | goto out; | 168 | goto out; |
169 | } else { | 169 | } else { |
170 | /* Runtime PM is disabled: power up the card manually */ | 170 | /* Runtime PM is disabled: power up the card manually */ |
diff --git a/drivers/net/wireless/wl12xx/testmode.c b/drivers/net/wireless/wl12xx/testmode.c index 88add68bd9ac..4ae8effaee22 100644 --- a/drivers/net/wireless/wl12xx/testmode.c +++ b/drivers/net/wireless/wl12xx/testmode.c | |||
@@ -36,7 +36,6 @@ enum wl1271_tm_commands { | |||
36 | WL1271_TM_CMD_TEST, | 36 | WL1271_TM_CMD_TEST, |
37 | WL1271_TM_CMD_INTERROGATE, | 37 | WL1271_TM_CMD_INTERROGATE, |
38 | WL1271_TM_CMD_CONFIGURE, | 38 | WL1271_TM_CMD_CONFIGURE, |
39 | WL1271_TM_CMD_NVS_PUSH, | ||
40 | WL1271_TM_CMD_SET_PLT_MODE, | 39 | WL1271_TM_CMD_SET_PLT_MODE, |
41 | WL1271_TM_CMD_RECOVER, | 40 | WL1271_TM_CMD_RECOVER, |
42 | 41 | ||
@@ -190,48 +189,6 @@ static int wl1271_tm_cmd_configure(struct wl1271 *wl, struct nlattr *tb[]) | |||
190 | return 0; | 189 | return 0; |
191 | } | 190 | } |
192 | 191 | ||
193 | static int wl1271_tm_cmd_nvs_push(struct wl1271 *wl, struct nlattr *tb[]) | ||
194 | { | ||
195 | int ret = 0; | ||
196 | size_t len; | ||
197 | void *buf; | ||
198 | |||
199 | wl1271_debug(DEBUG_TESTMODE, "testmode cmd nvs push"); | ||
200 | |||
201 | if (!tb[WL1271_TM_ATTR_DATA]) | ||
202 | return -EINVAL; | ||
203 | |||
204 | buf = nla_data(tb[WL1271_TM_ATTR_DATA]); | ||
205 | len = nla_len(tb[WL1271_TM_ATTR_DATA]); | ||
206 | |||
207 | mutex_lock(&wl->mutex); | ||
208 | |||
209 | kfree(wl->nvs); | ||
210 | |||
211 | if ((wl->chip.id == CHIP_ID_1283_PG20) && | ||
212 | (len != sizeof(struct wl128x_nvs_file))) | ||
213 | return -EINVAL; | ||
214 | else if (len != sizeof(struct wl1271_nvs_file)) | ||
215 | return -EINVAL; | ||
216 | |||
217 | wl->nvs = kzalloc(len, GFP_KERNEL); | ||
218 | if (!wl->nvs) { | ||
219 | wl1271_error("could not allocate memory for the nvs file"); | ||
220 | ret = -ENOMEM; | ||
221 | goto out; | ||
222 | } | ||
223 | |||
224 | memcpy(wl->nvs, buf, len); | ||
225 | wl->nvs_len = len; | ||
226 | |||
227 | wl1271_debug(DEBUG_TESTMODE, "testmode pushed nvs"); | ||
228 | |||
229 | out: | ||
230 | mutex_unlock(&wl->mutex); | ||
231 | |||
232 | return ret; | ||
233 | } | ||
234 | |||
235 | static int wl1271_tm_cmd_set_plt_mode(struct wl1271 *wl, struct nlattr *tb[]) | 192 | static int wl1271_tm_cmd_set_plt_mode(struct wl1271 *wl, struct nlattr *tb[]) |
236 | { | 193 | { |
237 | u32 val; | 194 | u32 val; |
@@ -288,8 +245,6 @@ int wl1271_tm_cmd(struct ieee80211_hw *hw, void *data, int len) | |||
288 | return wl1271_tm_cmd_interrogate(wl, tb); | 245 | return wl1271_tm_cmd_interrogate(wl, tb); |
289 | case WL1271_TM_CMD_CONFIGURE: | 246 | case WL1271_TM_CMD_CONFIGURE: |
290 | return wl1271_tm_cmd_configure(wl, tb); | 247 | return wl1271_tm_cmd_configure(wl, tb); |
291 | case WL1271_TM_CMD_NVS_PUSH: | ||
292 | return wl1271_tm_cmd_nvs_push(wl, tb); | ||
293 | case WL1271_TM_CMD_SET_PLT_MODE: | 248 | case WL1271_TM_CMD_SET_PLT_MODE: |
294 | return wl1271_tm_cmd_set_plt_mode(wl, tb); | 249 | return wl1271_tm_cmd_set_plt_mode(wl, tb); |
295 | case WL1271_TM_CMD_RECOVER: | 250 | case WL1271_TM_CMD_RECOVER: |