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-rw-r--r--drivers/net/Kconfig11
-rw-r--r--drivers/net/Makefile1
-rw-r--r--drivers/net/atlx/Makefile2
-rw-r--r--drivers/net/atlx/atl2.c3127
-rw-r--r--drivers/net/atlx/atl2.h530
5 files changed, 3671 insertions, 0 deletions
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4a11296a9514..81a3e959c6c3 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1840,6 +1840,17 @@ config NE_H8300
1840 Say Y here if you want to use the NE2000 compatible 1840 Say Y here if you want to use the NE2000 compatible
1841 controller on the Renesas H8/300 processor. 1841 controller on the Renesas H8/300 processor.
1842 1842
1843config ATL2
1844 tristate "Atheros L2 Fast Ethernet support"
1845 depends on PCI
1846 select CRC32
1847 select MII
1848 help
1849 This driver supports the Atheros L2 fast ethernet adapter.
1850
1851 To compile this driver as a module, choose M here. The module
1852 will be called atl2.
1853
1843source "drivers/net/fs_enet/Kconfig" 1854source "drivers/net/fs_enet/Kconfig"
1844 1855
1845endif # NET_ETHERNET 1856endif # NET_ETHERNET
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index f66b79bd3b89..9221346a515e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_EHEA) += ehea/
15obj-$(CONFIG_CAN) += can/ 15obj-$(CONFIG_CAN) += can/
16obj-$(CONFIG_BONDING) += bonding/ 16obj-$(CONFIG_BONDING) += bonding/
17obj-$(CONFIG_ATL1) += atlx/ 17obj-$(CONFIG_ATL1) += atlx/
18obj-$(CONFIG_ATL2) += atlx/
18obj-$(CONFIG_ATL1E) += atl1e/ 19obj-$(CONFIG_ATL1E) += atl1e/
19obj-$(CONFIG_GIANFAR) += gianfar_driver.o 20obj-$(CONFIG_GIANFAR) += gianfar_driver.o
20obj-$(CONFIG_TEHUTI) += tehuti.o 21obj-$(CONFIG_TEHUTI) += tehuti.o
diff --git a/drivers/net/atlx/Makefile b/drivers/net/atlx/Makefile
index ca45553a040d..e4f6022ca552 100644
--- a/drivers/net/atlx/Makefile
+++ b/drivers/net/atlx/Makefile
@@ -1 +1,3 @@
1obj-$(CONFIG_ATL1) += atl1.o 1obj-$(CONFIG_ATL1) += atl1.o
2obj-$(CONFIG_ATL2) += atl2.o
3
diff --git a/drivers/net/atlx/atl2.c b/drivers/net/atlx/atl2.c
new file mode 100644
index 000000000000..d548a67da1e8
--- /dev/null
+++ b/drivers/net/atlx/atl2.c
@@ -0,0 +1,3127 @@
1/*
2 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
3 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
4 *
5 * Derived from Intel e1000 driver
6 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#include <asm/atomic.h>
24#include <linux/crc32.h>
25#include <linux/dma-mapping.h>
26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/hardirq.h>
29#include <linux/if_vlan.h>
30#include <linux/in.h>
31#include <linux/interrupt.h>
32#include <linux/ip.h>
33#include <linux/irqflags.h>
34#include <linux/irqreturn.h>
35#include <linux/mii.h>
36#include <linux/net.h>
37#include <linux/netdevice.h>
38#include <linux/pci.h>
39#include <linux/pci_ids.h>
40#include <linux/pm.h>
41#include <linux/skbuff.h>
42#include <linux/spinlock.h>
43#include <linux/string.h>
44#include <linux/tcp.h>
45#include <linux/timer.h>
46#include <linux/types.h>
47#include <linux/workqueue.h>
48
49#include "atl2.h"
50
51#define ATL2_DRV_VERSION "2.2.3"
52
53static char atl2_driver_name[] = "atl2";
54static const char atl2_driver_string[] = "Atheros(R) L2 Ethernet Driver";
55static char atl2_copyright[] = "Copyright (c) 2007 Atheros Corporation.";
56static char atl2_driver_version[] = ATL2_DRV_VERSION;
57
58MODULE_AUTHOR("Atheros Corporation <xiong.huang@atheros.com>, Chris Snook <csnook@redhat.com>");
59MODULE_DESCRIPTION("Atheros Fast Ethernet Network Driver");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(ATL2_DRV_VERSION);
62
63/*
64 * atl2_pci_tbl - PCI Device ID Table
65 */
66static struct pci_device_id atl2_pci_tbl[] = {
67 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L2)},
68 /* required last entry */
69 {0,}
70};
71MODULE_DEVICE_TABLE(pci, atl2_pci_tbl);
72
73static void atl2_set_ethtool_ops(struct net_device *netdev);
74
75static void atl2_check_options(struct atl2_adapter *adapter);
76
77/*
78 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
79 * @adapter: board private structure to initialize
80 *
81 * atl2_sw_init initializes the Adapter private data structure.
82 * Fields are initialized based on PCI device information and
83 * OS network device settings (MTU size).
84 */
85static int __devinit atl2_sw_init(struct atl2_adapter *adapter)
86{
87 struct atl2_hw *hw = &adapter->hw;
88 struct pci_dev *pdev = adapter->pdev;
89
90 /* PCI config space info */
91 hw->vendor_id = pdev->vendor;
92 hw->device_id = pdev->device;
93 hw->subsystem_vendor_id = pdev->subsystem_vendor;
94 hw->subsystem_id = pdev->subsystem_device;
95
96 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
97 pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
98
99 adapter->wol = 0;
100 adapter->ict = 50000; /* ~100ms */
101 adapter->link_speed = SPEED_0; /* hardware init */
102 adapter->link_duplex = FULL_DUPLEX;
103
104 hw->phy_configured = false;
105 hw->preamble_len = 7;
106 hw->ipgt = 0x60;
107 hw->min_ifg = 0x50;
108 hw->ipgr1 = 0x40;
109 hw->ipgr2 = 0x60;
110 hw->retry_buf = 2;
111 hw->max_retry = 0xf;
112 hw->lcol = 0x37;
113 hw->jam_ipg = 7;
114 hw->fc_rxd_hi = 0;
115 hw->fc_rxd_lo = 0;
116 hw->max_frame_size = adapter->netdev->mtu;
117
118 spin_lock_init(&adapter->stats_lock);
119 spin_lock_init(&adapter->tx_lock);
120
121 set_bit(__ATL2_DOWN, &adapter->flags);
122
123 return 0;
124}
125
126/*
127 * atl2_set_multi - Multicast and Promiscuous mode set
128 * @netdev: network interface device structure
129 *
130 * The set_multi entry point is called whenever the multicast address
131 * list or the network interface flags are updated. This routine is
132 * responsible for configuring the hardware for proper multicast,
133 * promiscuous mode, and all-multi behavior.
134 */
135static void atl2_set_multi(struct net_device *netdev)
136{
137 struct atl2_adapter *adapter = netdev_priv(netdev);
138 struct atl2_hw *hw = &adapter->hw;
139 struct dev_mc_list *mc_ptr;
140 u32 rctl;
141 u32 hash_value;
142
143 /* Check for Promiscuous and All Multicast modes */
144 rctl = ATL2_READ_REG(hw, REG_MAC_CTRL);
145
146 if (netdev->flags & IFF_PROMISC) {
147 rctl |= MAC_CTRL_PROMIS_EN;
148 } else if (netdev->flags & IFF_ALLMULTI) {
149 rctl |= MAC_CTRL_MC_ALL_EN;
150 rctl &= ~MAC_CTRL_PROMIS_EN;
151 } else
152 rctl &= ~(MAC_CTRL_PROMIS_EN | MAC_CTRL_MC_ALL_EN);
153
154 ATL2_WRITE_REG(hw, REG_MAC_CTRL, rctl);
155
156 /* clear the old settings from the multicast hash table */
157 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
158 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
159
160 /* comoute mc addresses' hash value ,and put it into hash table */
161 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
162 hash_value = atl2_hash_mc_addr(hw, mc_ptr->dmi_addr);
163 atl2_hash_set(hw, hash_value);
164 }
165}
166
167static void init_ring_ptrs(struct atl2_adapter *adapter)
168{
169 /* Read / Write Ptr Initialize: */
170 adapter->txd_write_ptr = 0;
171 atomic_set(&adapter->txd_read_ptr, 0);
172
173 adapter->rxd_read_ptr = 0;
174 adapter->rxd_write_ptr = 0;
175
176 atomic_set(&adapter->txs_write_ptr, 0);
177 adapter->txs_next_clear = 0;
178}
179
180/*
181 * atl2_configure - Configure Transmit&Receive Unit after Reset
182 * @adapter: board private structure
183 *
184 * Configure the Tx /Rx unit of the MAC after a reset.
185 */
186static int atl2_configure(struct atl2_adapter *adapter)
187{
188 struct atl2_hw *hw = &adapter->hw;
189 u32 value;
190
191 /* clear interrupt status */
192 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0xffffffff);
193
194 /* set MAC Address */
195 value = (((u32)hw->mac_addr[2]) << 24) |
196 (((u32)hw->mac_addr[3]) << 16) |
197 (((u32)hw->mac_addr[4]) << 8) |
198 (((u32)hw->mac_addr[5]));
199 ATL2_WRITE_REG(hw, REG_MAC_STA_ADDR, value);
200 value = (((u32)hw->mac_addr[0]) << 8) |
201 (((u32)hw->mac_addr[1]));
202 ATL2_WRITE_REG(hw, (REG_MAC_STA_ADDR+4), value);
203
204 /* HI base address */
205 ATL2_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI,
206 (u32)((adapter->ring_dma & 0xffffffff00000000ULL) >> 32));
207
208 /* LO base address */
209 ATL2_WRITE_REG(hw, REG_TXD_BASE_ADDR_LO,
210 (u32)(adapter->txd_dma & 0x00000000ffffffffULL));
211 ATL2_WRITE_REG(hw, REG_TXS_BASE_ADDR_LO,
212 (u32)(adapter->txs_dma & 0x00000000ffffffffULL));
213 ATL2_WRITE_REG(hw, REG_RXD_BASE_ADDR_LO,
214 (u32)(adapter->rxd_dma & 0x00000000ffffffffULL));
215
216 /* element count */
217 ATL2_WRITE_REGW(hw, REG_TXD_MEM_SIZE, (u16)(adapter->txd_ring_size/4));
218 ATL2_WRITE_REGW(hw, REG_TXS_MEM_SIZE, (u16)adapter->txs_ring_size);
219 ATL2_WRITE_REGW(hw, REG_RXD_BUF_NUM, (u16)adapter->rxd_ring_size);
220
221 /* config Internal SRAM */
222/*
223 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_tx_end);
224 ATL2_WRITE_REGW(hw, REG_SRAM_TXRAM_END, sram_rx_end);
225*/
226
227 /* config IPG/IFG */
228 value = (((u32)hw->ipgt & MAC_IPG_IFG_IPGT_MASK) <<
229 MAC_IPG_IFG_IPGT_SHIFT) |
230 (((u32)hw->min_ifg & MAC_IPG_IFG_MIFG_MASK) <<
231 MAC_IPG_IFG_MIFG_SHIFT) |
232 (((u32)hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK) <<
233 MAC_IPG_IFG_IPGR1_SHIFT)|
234 (((u32)hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK) <<
235 MAC_IPG_IFG_IPGR2_SHIFT);
236 ATL2_WRITE_REG(hw, REG_MAC_IPG_IFG, value);
237
238 /* config Half-Duplex Control */
239 value = ((u32)hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
240 (((u32)hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK) <<
241 MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
242 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
243 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
244 (((u32)hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK) <<
245 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
246 ATL2_WRITE_REG(hw, REG_MAC_HALF_DUPLX_CTRL, value);
247
248 /* set Interrupt Moderator Timer */
249 ATL2_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, adapter->imt);
250 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_ITIMER_EN);
251
252 /* set Interrupt Clear Timer */
253 ATL2_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, adapter->ict);
254
255 /* set MTU */
256 ATL2_WRITE_REG(hw, REG_MTU, adapter->netdev->mtu +
257 ENET_HEADER_SIZE + VLAN_SIZE + ETHERNET_FCS_SIZE);
258
259 /* 1590 */
260 ATL2_WRITE_REG(hw, REG_TX_CUT_THRESH, 0x177);
261
262 /* flow control */
263 ATL2_WRITE_REGW(hw, REG_PAUSE_ON_TH, hw->fc_rxd_hi);
264 ATL2_WRITE_REGW(hw, REG_PAUSE_OFF_TH, hw->fc_rxd_lo);
265
266 /* Init mailbox */
267 ATL2_WRITE_REGW(hw, REG_MB_TXD_WR_IDX, (u16)adapter->txd_write_ptr);
268 ATL2_WRITE_REGW(hw, REG_MB_RXD_RD_IDX, (u16)adapter->rxd_read_ptr);
269
270 /* enable DMA read/write */
271 ATL2_WRITE_REGB(hw, REG_DMAR, DMAR_EN);
272 ATL2_WRITE_REGB(hw, REG_DMAW, DMAW_EN);
273
274 value = ATL2_READ_REG(&adapter->hw, REG_ISR);
275 if ((value & ISR_PHY_LINKDOWN) != 0)
276 value = 1; /* config failed */
277 else
278 value = 0;
279
280 /* clear all interrupt status */
281 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0x3fffffff);
282 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
283 return value;
284}
285
286/*
287 * atl2_setup_ring_resources - allocate Tx / RX descriptor resources
288 * @adapter: board private structure
289 *
290 * Return 0 on success, negative on failure
291 */
292static s32 atl2_setup_ring_resources(struct atl2_adapter *adapter)
293{
294 struct pci_dev *pdev = adapter->pdev;
295 int size;
296 u8 offset = 0;
297
298 /* real ring DMA buffer */
299 adapter->ring_size = size =
300 adapter->txd_ring_size * 1 + 7 + /* dword align */
301 adapter->txs_ring_size * 4 + 7 + /* dword align */
302 adapter->rxd_ring_size * 1536 + 127; /* 128bytes align */
303
304 adapter->ring_vir_addr = pci_alloc_consistent(pdev, size,
305 &adapter->ring_dma);
306 if (!adapter->ring_vir_addr)
307 return -ENOMEM;
308 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
309
310 /* Init TXD Ring */
311 adapter->txd_dma = adapter->ring_dma ;
312 offset = (adapter->txd_dma & 0x7) ? (8 - (adapter->txd_dma & 0x7)) : 0;
313 adapter->txd_dma += offset;
314 adapter->txd_ring = (struct tx_pkt_header *) (adapter->ring_vir_addr +
315 offset);
316
317 /* Init TXS Ring */
318 adapter->txs_dma = adapter->txd_dma + adapter->txd_ring_size;
319 offset = (adapter->txs_dma & 0x7) ? (8 - (adapter->txs_dma & 0x7)) : 0;
320 adapter->txs_dma += offset;
321 adapter->txs_ring = (struct tx_pkt_status *)
322 (((u8 *)adapter->txd_ring) + (adapter->txd_ring_size + offset));
323
324 /* Init RXD Ring */
325 adapter->rxd_dma = adapter->txs_dma + adapter->txs_ring_size * 4;
326 offset = (adapter->rxd_dma & 127) ?
327 (128 - (adapter->rxd_dma & 127)) : 0;
328 if (offset > 7)
329 offset -= 8;
330 else
331 offset += (128 - 8);
332
333 adapter->rxd_dma += offset;
334 adapter->rxd_ring = (struct rx_desc *) (((u8 *)adapter->txs_ring) +
335 (adapter->txs_ring_size * 4 + offset));
336
337/*
338 * Read / Write Ptr Initialize:
339 * init_ring_ptrs(adapter);
340 */
341 return 0;
342}
343
344/*
345 * atl2_irq_enable - Enable default interrupt generation settings
346 * @adapter: board private structure
347 */
348static inline void atl2_irq_enable(struct atl2_adapter *adapter)
349{
350 ATL2_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
351 ATL2_WRITE_FLUSH(&adapter->hw);
352}
353
354/*
355 * atl2_irq_disable - Mask off interrupt generation on the NIC
356 * @adapter: board private structure
357 */
358static inline void atl2_irq_disable(struct atl2_adapter *adapter)
359{
360 ATL2_WRITE_REG(&adapter->hw, REG_IMR, 0);
361 ATL2_WRITE_FLUSH(&adapter->hw);
362 synchronize_irq(adapter->pdev->irq);
363}
364
365#ifdef NETIF_F_HW_VLAN_TX
366static void atl2_vlan_rx_register(struct net_device *netdev,
367 struct vlan_group *grp)
368{
369 struct atl2_adapter *adapter = netdev_priv(netdev);
370 u32 ctrl;
371
372 atl2_irq_disable(adapter);
373 adapter->vlgrp = grp;
374
375 if (grp) {
376 /* enable VLAN tag insert/strip */
377 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
378 ctrl |= MAC_CTRL_RMV_VLAN;
379 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
380 } else {
381 /* disable VLAN tag insert/strip */
382 ctrl = ATL2_READ_REG(&adapter->hw, REG_MAC_CTRL);
383 ctrl &= ~MAC_CTRL_RMV_VLAN;
384 ATL2_WRITE_REG(&adapter->hw, REG_MAC_CTRL, ctrl);
385 }
386
387 atl2_irq_enable(adapter);
388}
389
390static void atl2_restore_vlan(struct atl2_adapter *adapter)
391{
392 atl2_vlan_rx_register(adapter->netdev, adapter->vlgrp);
393}
394#endif
395
396static void atl2_intr_rx(struct atl2_adapter *adapter)
397{
398 struct net_device *netdev = adapter->netdev;
399 struct rx_desc *rxd;
400 struct sk_buff *skb;
401
402 do {
403 rxd = adapter->rxd_ring+adapter->rxd_write_ptr;
404 if (!rxd->status.update)
405 break; /* end of tx */
406
407 /* clear this flag at once */
408 rxd->status.update = 0;
409
410 if (rxd->status.ok && rxd->status.pkt_size >= 60) {
411 int rx_size = (int)(rxd->status.pkt_size - 4);
412 /* alloc new buffer */
413 skb = netdev_alloc_skb(netdev, rx_size + NET_IP_ALIGN);
414 if (NULL == skb) {
415 printk(KERN_WARNING
416 "%s: Mem squeeze, deferring packet.\n",
417 netdev->name);
418 /*
419 * Check that some rx space is free. If not,
420 * free one and mark stats->rx_dropped++.
421 */
422 adapter->net_stats.rx_dropped++;
423 break;
424 }
425 skb_reserve(skb, NET_IP_ALIGN);
426 skb->dev = netdev;
427 memcpy(skb->data, rxd->packet, rx_size);
428 skb_put(skb, rx_size);
429 skb->protocol = eth_type_trans(skb, netdev);
430#ifdef NETIF_F_HW_VLAN_TX
431 if (adapter->vlgrp && (rxd->status.vlan)) {
432 u16 vlan_tag = (rxd->status.vtag>>4) |
433 ((rxd->status.vtag&7) << 13) |
434 ((rxd->status.vtag&8) << 9);
435 vlan_hwaccel_rx(skb, adapter->vlgrp, vlan_tag);
436 } else
437#endif
438 netif_rx(skb);
439 adapter->net_stats.rx_bytes += rx_size;
440 adapter->net_stats.rx_packets++;
441 netdev->last_rx = jiffies;
442 } else {
443 adapter->net_stats.rx_errors++;
444
445 if (rxd->status.ok && rxd->status.pkt_size <= 60)
446 adapter->net_stats.rx_length_errors++;
447 if (rxd->status.mcast)
448 adapter->net_stats.multicast++;
449 if (rxd->status.crc)
450 adapter->net_stats.rx_crc_errors++;
451 if (rxd->status.align)
452 adapter->net_stats.rx_frame_errors++;
453 }
454
455 /* advance write ptr */
456 if (++adapter->rxd_write_ptr == adapter->rxd_ring_size)
457 adapter->rxd_write_ptr = 0;
458 } while (1);
459
460 /* update mailbox? */
461 adapter->rxd_read_ptr = adapter->rxd_write_ptr;
462 ATL2_WRITE_REGW(&adapter->hw, REG_MB_RXD_RD_IDX, adapter->rxd_read_ptr);
463}
464
465static void atl2_intr_tx(struct atl2_adapter *adapter)
466{
467 u32 txd_read_ptr;
468 u32 txs_write_ptr;
469 struct tx_pkt_status *txs;
470 struct tx_pkt_header *txph;
471 int free_hole = 0;
472
473 do {
474 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
475 txs = adapter->txs_ring + txs_write_ptr;
476 if (!txs->update)
477 break; /* tx stop here */
478
479 free_hole = 1;
480 txs->update = 0;
481
482 if (++txs_write_ptr == adapter->txs_ring_size)
483 txs_write_ptr = 0;
484 atomic_set(&adapter->txs_write_ptr, (int)txs_write_ptr);
485
486 txd_read_ptr = (u32) atomic_read(&adapter->txd_read_ptr);
487 txph = (struct tx_pkt_header *)
488 (((u8 *)adapter->txd_ring) + txd_read_ptr);
489
490 if (txph->pkt_size != txs->pkt_size) {
491 struct tx_pkt_status *old_txs = txs;
492 printk(KERN_WARNING
493 "%s: txs packet size not consistent with txd"
494 " txd_:0x%08x, txs_:0x%08x!\n",
495 adapter->netdev->name,
496 *(u32 *)txph, *(u32 *)txs);
497 printk(KERN_WARNING
498 "txd read ptr: 0x%x\n",
499 txd_read_ptr);
500 txs = adapter->txs_ring + txs_write_ptr;
501 printk(KERN_WARNING
502 "txs-behind:0x%08x\n",
503 *(u32 *)txs);
504 if (txs_write_ptr < 2) {
505 txs = adapter->txs_ring +
506 (adapter->txs_ring_size +
507 txs_write_ptr - 2);
508 } else {
509 txs = adapter->txs_ring + (txs_write_ptr - 2);
510 }
511 printk(KERN_WARNING
512 "txs-before:0x%08x\n",
513 *(u32 *)txs);
514 txs = old_txs;
515 }
516
517 /* 4for TPH */
518 txd_read_ptr += (((u32)(txph->pkt_size) + 7) & ~3);
519 if (txd_read_ptr >= adapter->txd_ring_size)
520 txd_read_ptr -= adapter->txd_ring_size;
521
522 atomic_set(&adapter->txd_read_ptr, (int)txd_read_ptr);
523
524 /* tx statistics: */
525 if (txs->ok)
526 adapter->net_stats.tx_packets++;
527 else
528 adapter->net_stats.tx_errors++;
529
530 if (txs->defer)
531 adapter->net_stats.collisions++;
532 if (txs->abort_col)
533 adapter->net_stats.tx_aborted_errors++;
534 if (txs->late_col)
535 adapter->net_stats.tx_window_errors++;
536 if (txs->underun)
537 adapter->net_stats.tx_fifo_errors++;
538 } while (1);
539
540 if (free_hole) {
541 if (netif_queue_stopped(adapter->netdev) &&
542 netif_carrier_ok(adapter->netdev))
543 netif_wake_queue(adapter->netdev);
544 }
545}
546
547static void atl2_check_for_link(struct atl2_adapter *adapter)
548{
549 struct net_device *netdev = adapter->netdev;
550 u16 phy_data = 0;
551
552 spin_lock(&adapter->stats_lock);
553 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
554 atl2_read_phy_reg(&adapter->hw, MII_BMSR, &phy_data);
555 spin_unlock(&adapter->stats_lock);
556
557 /* notify upper layer link down ASAP */
558 if (!(phy_data & BMSR_LSTATUS)) { /* Link Down */
559 if (netif_carrier_ok(netdev)) { /* old link state: Up */
560 printk(KERN_INFO "%s: %s NIC Link is Down\n",
561 atl2_driver_name, netdev->name);
562 adapter->link_speed = SPEED_0;
563 netif_carrier_off(netdev);
564 netif_stop_queue(netdev);
565 }
566 }
567 schedule_work(&adapter->link_chg_task);
568}
569
570static inline void atl2_clear_phy_int(struct atl2_adapter *adapter)
571{
572 u16 phy_data;
573 spin_lock(&adapter->stats_lock);
574 atl2_read_phy_reg(&adapter->hw, 19, &phy_data);
575 spin_unlock(&adapter->stats_lock);
576}
577
578/*
579 * atl2_intr - Interrupt Handler
580 * @irq: interrupt number
581 * @data: pointer to a network interface device structure
582 * @pt_regs: CPU registers structure
583 */
584static irqreturn_t atl2_intr(int irq, void *data)
585{
586 struct atl2_adapter *adapter = netdev_priv(data);
587 struct atl2_hw *hw = &adapter->hw;
588 u32 status;
589
590 status = ATL2_READ_REG(hw, REG_ISR);
591 if (0 == status)
592 return IRQ_NONE;
593
594 /* link event */
595 if (status & ISR_PHY)
596 atl2_clear_phy_int(adapter);
597
598 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
599 ATL2_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
600
601 /* check if PCIE PHY Link down */
602 if (status & ISR_PHY_LINKDOWN) {
603 if (netif_running(adapter->netdev)) { /* reset MAC */
604 ATL2_WRITE_REG(hw, REG_ISR, 0);
605 ATL2_WRITE_REG(hw, REG_IMR, 0);
606 ATL2_WRITE_FLUSH(hw);
607 schedule_work(&adapter->reset_task);
608 return IRQ_HANDLED;
609 }
610 }
611
612 /* check if DMA read/write error? */
613 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
614 ATL2_WRITE_REG(hw, REG_ISR, 0);
615 ATL2_WRITE_REG(hw, REG_IMR, 0);
616 ATL2_WRITE_FLUSH(hw);
617 schedule_work(&adapter->reset_task);
618 return IRQ_HANDLED;
619 }
620
621 /* link event */
622 if (status & (ISR_PHY | ISR_MANUAL)) {
623 adapter->net_stats.tx_carrier_errors++;
624 atl2_check_for_link(adapter);
625 }
626
627 /* transmit event */
628 if (status & ISR_TX_EVENT)
629 atl2_intr_tx(adapter);
630
631 /* rx exception */
632 if (status & ISR_RX_EVENT)
633 atl2_intr_rx(adapter);
634
635 /* re-enable Interrupt */
636 ATL2_WRITE_REG(&adapter->hw, REG_ISR, 0);
637 return IRQ_HANDLED;
638}
639
640static int atl2_request_irq(struct atl2_adapter *adapter)
641{
642 struct net_device *netdev = adapter->netdev;
643 int flags, err = 0;
644
645 flags = IRQF_SHARED;
646#ifdef CONFIG_PCI_MSI
647 adapter->have_msi = true;
648 err = pci_enable_msi(adapter->pdev);
649 if (err)
650 adapter->have_msi = false;
651
652 if (adapter->have_msi)
653 flags &= ~IRQF_SHARED;
654#endif
655
656 return request_irq(adapter->pdev->irq, &atl2_intr, flags, netdev->name,
657 netdev);
658}
659
660/*
661 * atl2_free_ring_resources - Free Tx / RX descriptor Resources
662 * @adapter: board private structure
663 *
664 * Free all transmit software resources
665 */
666static void atl2_free_ring_resources(struct atl2_adapter *adapter)
667{
668 struct pci_dev *pdev = adapter->pdev;
669 pci_free_consistent(pdev, adapter->ring_size, adapter->ring_vir_addr,
670 adapter->ring_dma);
671}
672
673/*
674 * atl2_open - Called when a network interface is made active
675 * @netdev: network interface device structure
676 *
677 * Returns 0 on success, negative value on failure
678 *
679 * The open entry point is called when a network interface is made
680 * active by the system (IFF_UP). At this point all resources needed
681 * for transmit and receive operations are allocated, the interrupt
682 * handler is registered with the OS, the watchdog timer is started,
683 * and the stack is notified that the interface is ready.
684 */
685static int atl2_open(struct net_device *netdev)
686{
687 struct atl2_adapter *adapter = netdev_priv(netdev);
688 int err;
689 u32 val;
690
691 /* disallow open during test */
692 if (test_bit(__ATL2_TESTING, &adapter->flags))
693 return -EBUSY;
694
695 /* allocate transmit descriptors */
696 err = atl2_setup_ring_resources(adapter);
697 if (err)
698 return err;
699
700 err = atl2_init_hw(&adapter->hw);
701 if (err) {
702 err = -EIO;
703 goto err_init_hw;
704 }
705
706 /* hardware has been reset, we need to reload some things */
707 atl2_set_multi(netdev);
708 init_ring_ptrs(adapter);
709
710#ifdef NETIF_F_HW_VLAN_TX
711 atl2_restore_vlan(adapter);
712#endif
713
714 if (atl2_configure(adapter)) {
715 err = -EIO;
716 goto err_config;
717 }
718
719 err = atl2_request_irq(adapter);
720 if (err)
721 goto err_req_irq;
722
723 clear_bit(__ATL2_DOWN, &adapter->flags);
724
725 mod_timer(&adapter->watchdog_timer, jiffies + 4*HZ);
726
727 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
728 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
729 val | MASTER_CTRL_MANUAL_INT);
730
731 atl2_irq_enable(adapter);
732
733 return 0;
734
735err_init_hw:
736err_req_irq:
737err_config:
738 atl2_free_ring_resources(adapter);
739 atl2_reset_hw(&adapter->hw);
740
741 return err;
742}
743
744static void atl2_down(struct atl2_adapter *adapter)
745{
746 struct net_device *netdev = adapter->netdev;
747
748 /* signal that we're down so the interrupt handler does not
749 * reschedule our watchdog timer */
750 set_bit(__ATL2_DOWN, &adapter->flags);
751
752#ifdef NETIF_F_LLTX
753 netif_stop_queue(netdev);
754#else
755 netif_tx_disable(netdev);
756#endif
757
758 /* reset MAC to disable all RX/TX */
759 atl2_reset_hw(&adapter->hw);
760 msleep(1);
761
762 atl2_irq_disable(adapter);
763
764 del_timer_sync(&adapter->watchdog_timer);
765 del_timer_sync(&adapter->phy_config_timer);
766 clear_bit(0, &adapter->cfg_phy);
767
768 netif_carrier_off(netdev);
769 adapter->link_speed = SPEED_0;
770 adapter->link_duplex = -1;
771}
772
773static void atl2_free_irq(struct atl2_adapter *adapter)
774{
775 struct net_device *netdev = adapter->netdev;
776
777 free_irq(adapter->pdev->irq, netdev);
778
779#ifdef CONFIG_PCI_MSI
780 if (adapter->have_msi)
781 pci_disable_msi(adapter->pdev);
782#endif
783}
784
785/*
786 * atl2_close - Disables a network interface
787 * @netdev: network interface device structure
788 *
789 * Returns 0, this is not allowed to fail
790 *
791 * The close entry point is called when an interface is de-activated
792 * by the OS. The hardware is still under the drivers control, but
793 * needs to be disabled. A global MAC reset is issued to stop the
794 * hardware, and all transmit and receive resources are freed.
795 */
796static int atl2_close(struct net_device *netdev)
797{
798 struct atl2_adapter *adapter = netdev_priv(netdev);
799
800 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
801
802 atl2_down(adapter);
803 atl2_free_irq(adapter);
804 atl2_free_ring_resources(adapter);
805
806 return 0;
807}
808
809static inline int TxsFreeUnit(struct atl2_adapter *adapter)
810{
811 u32 txs_write_ptr = (u32) atomic_read(&adapter->txs_write_ptr);
812
813 return (adapter->txs_next_clear >= txs_write_ptr) ?
814 (int) (adapter->txs_ring_size - adapter->txs_next_clear +
815 txs_write_ptr - 1) :
816 (int) (txs_write_ptr - adapter->txs_next_clear - 1);
817}
818
819static inline int TxdFreeBytes(struct atl2_adapter *adapter)
820{
821 u32 txd_read_ptr = (u32)atomic_read(&adapter->txd_read_ptr);
822
823 return (adapter->txd_write_ptr >= txd_read_ptr) ?
824 (int) (adapter->txd_ring_size - adapter->txd_write_ptr +
825 txd_read_ptr - 1) :
826 (int) (txd_read_ptr - adapter->txd_write_ptr - 1);
827}
828
829static int atl2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
830{
831 struct atl2_adapter *adapter = netdev_priv(netdev);
832 unsigned long flags;
833 struct tx_pkt_header *txph;
834 u32 offset, copy_len;
835 int txs_unused;
836 int txbuf_unused;
837
838 if (test_bit(__ATL2_DOWN, &adapter->flags)) {
839 dev_kfree_skb_any(skb);
840 return NETDEV_TX_OK;
841 }
842
843 if (unlikely(skb->len <= 0)) {
844 dev_kfree_skb_any(skb);
845 return NETDEV_TX_OK;
846 }
847
848#ifdef NETIF_F_LLTX
849 local_irq_save(flags);
850 if (!spin_trylock(&adapter->tx_lock)) {
851 /* Collision - tell upper layer to requeue */
852 local_irq_restore(flags);
853 return NETDEV_TX_LOCKED;
854 }
855#else
856 spin_lock_irqsave(&adapter->tx_lock, flags);
857#endif
858 txs_unused = TxsFreeUnit(adapter);
859 txbuf_unused = TxdFreeBytes(adapter);
860
861 if (skb->len + sizeof(struct tx_pkt_header) + 4 > txbuf_unused ||
862 txs_unused < 1) {
863 /* not enough resources */
864 netif_stop_queue(netdev);
865 spin_unlock_irqrestore(&adapter->tx_lock, flags);
866 return NETDEV_TX_BUSY;
867 }
868
869 offset = adapter->txd_write_ptr;
870
871 txph = (struct tx_pkt_header *) (((u8 *)adapter->txd_ring) + offset);
872
873 *(u32 *)txph = 0;
874 txph->pkt_size = skb->len;
875
876 offset += 4;
877 if (offset >= adapter->txd_ring_size)
878 offset -= adapter->txd_ring_size;
879 copy_len = adapter->txd_ring_size - offset;
880 if (copy_len >= skb->len) {
881 memcpy(((u8 *)adapter->txd_ring) + offset, skb->data, skb->len);
882 offset += ((u32)(skb->len + 3) & ~3);
883 } else {
884 memcpy(((u8 *)adapter->txd_ring)+offset, skb->data, copy_len);
885 memcpy((u8 *)adapter->txd_ring, skb->data+copy_len,
886 skb->len-copy_len);
887 offset = ((u32)(skb->len-copy_len + 3) & ~3);
888 }
889#ifdef NETIF_F_HW_VLAN_TX
890 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
891 u16 vlan_tag = vlan_tx_tag_get(skb);
892 vlan_tag = (vlan_tag << 4) |
893 (vlan_tag >> 13) |
894 ((vlan_tag >> 9) & 0x8);
895 txph->ins_vlan = 1;
896 txph->vlan = vlan_tag;
897 }
898#endif
899 if (offset >= adapter->txd_ring_size)
900 offset -= adapter->txd_ring_size;
901 adapter->txd_write_ptr = offset;
902
903 /* clear txs before send */
904 adapter->txs_ring[adapter->txs_next_clear].update = 0;
905 if (++adapter->txs_next_clear == adapter->txs_ring_size)
906 adapter->txs_next_clear = 0;
907
908 ATL2_WRITE_REGW(&adapter->hw, REG_MB_TXD_WR_IDX,
909 (adapter->txd_write_ptr >> 2));
910
911 spin_unlock_irqrestore(&adapter->tx_lock, flags);
912
913 netdev->trans_start = jiffies;
914 dev_kfree_skb_any(skb);
915 return NETDEV_TX_OK;
916}
917
918/*
919 * atl2_get_stats - Get System Network Statistics
920 * @netdev: network interface device structure
921 *
922 * Returns the address of the device statistics structure.
923 * The statistics are actually updated from the timer callback.
924 */
925static struct net_device_stats *atl2_get_stats(struct net_device *netdev)
926{
927 struct atl2_adapter *adapter = netdev_priv(netdev);
928 return &adapter->net_stats;
929}
930
931/*
932 * atl2_change_mtu - Change the Maximum Transfer Unit
933 * @netdev: network interface device structure
934 * @new_mtu: new value for maximum frame size
935 *
936 * Returns 0 on success, negative on failure
937 */
938static int atl2_change_mtu(struct net_device *netdev, int new_mtu)
939{
940 struct atl2_adapter *adapter = netdev_priv(netdev);
941 struct atl2_hw *hw = &adapter->hw;
942
943 if ((new_mtu < 40) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
944 return -EINVAL;
945
946 /* set MTU */
947 if (hw->max_frame_size != new_mtu) {
948 netdev->mtu = new_mtu;
949 ATL2_WRITE_REG(hw, REG_MTU, new_mtu + ENET_HEADER_SIZE +
950 VLAN_SIZE + ETHERNET_FCS_SIZE);
951 }
952
953 return 0;
954}
955
956/*
957 * atl2_set_mac - Change the Ethernet Address of the NIC
958 * @netdev: network interface device structure
959 * @p: pointer to an address structure
960 *
961 * Returns 0 on success, negative on failure
962 */
963static int atl2_set_mac(struct net_device *netdev, void *p)
964{
965 struct atl2_adapter *adapter = netdev_priv(netdev);
966 struct sockaddr *addr = p;
967
968 if (!is_valid_ether_addr(addr->sa_data))
969 return -EADDRNOTAVAIL;
970
971 if (netif_running(netdev))
972 return -EBUSY;
973
974 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
975 memcpy(adapter->hw.mac_addr, addr->sa_data, netdev->addr_len);
976
977 atl2_set_mac_addr(&adapter->hw);
978
979 return 0;
980}
981
982/*
983 * atl2_mii_ioctl -
984 * @netdev:
985 * @ifreq:
986 * @cmd:
987 */
988static int atl2_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
989{
990 struct atl2_adapter *adapter = netdev_priv(netdev);
991 struct mii_ioctl_data *data = if_mii(ifr);
992 unsigned long flags;
993
994 switch (cmd) {
995 case SIOCGMIIPHY:
996 data->phy_id = 0;
997 break;
998 case SIOCGMIIREG:
999 if (!capable(CAP_NET_ADMIN))
1000 return -EPERM;
1001 spin_lock_irqsave(&adapter->stats_lock, flags);
1002 if (atl2_read_phy_reg(&adapter->hw,
1003 data->reg_num & 0x1F, &data->val_out)) {
1004 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1005 return -EIO;
1006 }
1007 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1008 break;
1009 case SIOCSMIIREG:
1010 if (!capable(CAP_NET_ADMIN))
1011 return -EPERM;
1012 if (data->reg_num & ~(0x1F))
1013 return -EFAULT;
1014 spin_lock_irqsave(&adapter->stats_lock, flags);
1015 if (atl2_write_phy_reg(&adapter->hw, data->reg_num,
1016 data->val_in)) {
1017 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1018 return -EIO;
1019 }
1020 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1021 break;
1022 default:
1023 return -EOPNOTSUPP;
1024 }
1025 return 0;
1026}
1027
1028/*
1029 * atl2_ioctl -
1030 * @netdev:
1031 * @ifreq:
1032 * @cmd:
1033 */
1034static int atl2_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1035{
1036 switch (cmd) {
1037 case SIOCGMIIPHY:
1038 case SIOCGMIIREG:
1039 case SIOCSMIIREG:
1040 return atl2_mii_ioctl(netdev, ifr, cmd);
1041#ifdef ETHTOOL_OPS_COMPAT
1042 case SIOCETHTOOL:
1043 return ethtool_ioctl(ifr);
1044#endif
1045 default:
1046 return -EOPNOTSUPP;
1047 }
1048}
1049
1050/*
1051 * atl2_tx_timeout - Respond to a Tx Hang
1052 * @netdev: network interface device structure
1053 */
1054static void atl2_tx_timeout(struct net_device *netdev)
1055{
1056 struct atl2_adapter *adapter = netdev_priv(netdev);
1057
1058 /* Do the reset outside of interrupt context */
1059 schedule_work(&adapter->reset_task);
1060}
1061
1062/*
1063 * atl2_watchdog - Timer Call-back
1064 * @data: pointer to netdev cast into an unsigned long
1065 */
1066static void atl2_watchdog(unsigned long data)
1067{
1068 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1069 u32 drop_rxd, drop_rxs;
1070 unsigned long flags;
1071
1072 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1073 spin_lock_irqsave(&adapter->stats_lock, flags);
1074 drop_rxd = ATL2_READ_REG(&adapter->hw, REG_STS_RXD_OV);
1075 drop_rxs = ATL2_READ_REG(&adapter->hw, REG_STS_RXS_OV);
1076 adapter->net_stats.rx_over_errors += (drop_rxd+drop_rxs);
1077 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1078
1079 /* Reset the timer */
1080 mod_timer(&adapter->watchdog_timer, jiffies + 4 * HZ);
1081 }
1082}
1083
1084/*
1085 * atl2_phy_config - Timer Call-back
1086 * @data: pointer to netdev cast into an unsigned long
1087 */
1088static void atl2_phy_config(unsigned long data)
1089{
1090 struct atl2_adapter *adapter = (struct atl2_adapter *) data;
1091 struct atl2_hw *hw = &adapter->hw;
1092 unsigned long flags;
1093
1094 spin_lock_irqsave(&adapter->stats_lock, flags);
1095 atl2_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1096 atl2_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1097 MII_CR_RESTART_AUTO_NEG);
1098 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1099 clear_bit(0, &adapter->cfg_phy);
1100}
1101
1102static int atl2_up(struct atl2_adapter *adapter)
1103{
1104 struct net_device *netdev = adapter->netdev;
1105 int err = 0;
1106 u32 val;
1107
1108 /* hardware has been reset, we need to reload some things */
1109
1110 err = atl2_init_hw(&adapter->hw);
1111 if (err) {
1112 err = -EIO;
1113 return err;
1114 }
1115
1116 atl2_set_multi(netdev);
1117 init_ring_ptrs(adapter);
1118
1119#ifdef NETIF_F_HW_VLAN_TX
1120 atl2_restore_vlan(adapter);
1121#endif
1122
1123 if (atl2_configure(adapter)) {
1124 err = -EIO;
1125 goto err_up;
1126 }
1127
1128 clear_bit(__ATL2_DOWN, &adapter->flags);
1129
1130 val = ATL2_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1131 ATL2_WRITE_REG(&adapter->hw, REG_MASTER_CTRL, val |
1132 MASTER_CTRL_MANUAL_INT);
1133
1134 atl2_irq_enable(adapter);
1135
1136err_up:
1137 return err;
1138}
1139
1140static void atl2_reinit_locked(struct atl2_adapter *adapter)
1141{
1142 WARN_ON(in_interrupt());
1143 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1144 msleep(1);
1145 atl2_down(adapter);
1146 atl2_up(adapter);
1147 clear_bit(__ATL2_RESETTING, &adapter->flags);
1148}
1149
1150static void atl2_reset_task(struct work_struct *work)
1151{
1152 struct atl2_adapter *adapter;
1153 adapter = container_of(work, struct atl2_adapter, reset_task);
1154
1155 atl2_reinit_locked(adapter);
1156}
1157
1158static void atl2_setup_mac_ctrl(struct atl2_adapter *adapter)
1159{
1160 u32 value;
1161 struct atl2_hw *hw = &adapter->hw;
1162 struct net_device *netdev = adapter->netdev;
1163
1164 /* Config MAC CTRL Register */
1165 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1166
1167 /* duplex */
1168 if (FULL_DUPLEX == adapter->link_duplex)
1169 value |= MAC_CTRL_DUPLX;
1170
1171 /* flow control */
1172 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1173
1174 /* PAD & CRC */
1175 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1176
1177 /* preamble length */
1178 value |= (((u32)adapter->hw.preamble_len & MAC_CTRL_PRMLEN_MASK) <<
1179 MAC_CTRL_PRMLEN_SHIFT);
1180
1181 /* vlan */
1182 if (adapter->vlgrp)
1183 value |= MAC_CTRL_RMV_VLAN;
1184
1185 /* filter mode */
1186 value |= MAC_CTRL_BC_EN;
1187 if (netdev->flags & IFF_PROMISC)
1188 value |= MAC_CTRL_PROMIS_EN;
1189 else if (netdev->flags & IFF_ALLMULTI)
1190 value |= MAC_CTRL_MC_ALL_EN;
1191
1192 /* half retry buffer */
1193 value |= (((u32)(adapter->hw.retry_buf &
1194 MAC_CTRL_HALF_LEFT_BUF_MASK)) << MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1195
1196 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1197}
1198
1199static int atl2_check_link(struct atl2_adapter *adapter)
1200{
1201 struct atl2_hw *hw = &adapter->hw;
1202 struct net_device *netdev = adapter->netdev;
1203 int ret_val;
1204 u16 speed, duplex, phy_data;
1205 int reconfig = 0;
1206
1207 /* MII_BMSR must read twise */
1208 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1209 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1210 if (!(phy_data&BMSR_LSTATUS)) { /* link down */
1211 if (netif_carrier_ok(netdev)) { /* old link state: Up */
1212 u32 value;
1213 /* disable rx */
1214 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1215 value &= ~MAC_CTRL_RX_EN;
1216 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1217 adapter->link_speed = SPEED_0;
1218 netif_carrier_off(netdev);
1219 netif_stop_queue(netdev);
1220 }
1221 return 0;
1222 }
1223
1224 /* Link Up */
1225 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1226 if (ret_val)
1227 return ret_val;
1228 switch (hw->MediaType) {
1229 case MEDIA_TYPE_100M_FULL:
1230 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1231 reconfig = 1;
1232 break;
1233 case MEDIA_TYPE_100M_HALF:
1234 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1235 reconfig = 1;
1236 break;
1237 case MEDIA_TYPE_10M_FULL:
1238 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1239 reconfig = 1;
1240 break;
1241 case MEDIA_TYPE_10M_HALF:
1242 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1243 reconfig = 1;
1244 break;
1245 }
1246 /* link result is our setting */
1247 if (reconfig == 0) {
1248 if (adapter->link_speed != speed ||
1249 adapter->link_duplex != duplex) {
1250 adapter->link_speed = speed;
1251 adapter->link_duplex = duplex;
1252 atl2_setup_mac_ctrl(adapter);
1253 printk(KERN_INFO "%s: %s NIC Link is Up<%d Mbps %s>\n",
1254 atl2_driver_name, netdev->name,
1255 adapter->link_speed,
1256 adapter->link_duplex == FULL_DUPLEX ?
1257 "Full Duplex" : "Half Duplex");
1258 }
1259
1260 if (!netif_carrier_ok(netdev)) { /* Link down -> Up */
1261 netif_carrier_on(netdev);
1262 netif_wake_queue(netdev);
1263 }
1264 return 0;
1265 }
1266
1267 /* change original link status */
1268 if (netif_carrier_ok(netdev)) {
1269 u32 value;
1270 /* disable rx */
1271 value = ATL2_READ_REG(hw, REG_MAC_CTRL);
1272 value &= ~MAC_CTRL_RX_EN;
1273 ATL2_WRITE_REG(hw, REG_MAC_CTRL, value);
1274
1275 adapter->link_speed = SPEED_0;
1276 netif_carrier_off(netdev);
1277 netif_stop_queue(netdev);
1278 }
1279
1280 /* auto-neg, insert timer to re-config phy
1281 * (if interval smaller than 5 seconds, something strange) */
1282 if (!test_bit(__ATL2_DOWN, &adapter->flags)) {
1283 if (!test_and_set_bit(0, &adapter->cfg_phy))
1284 mod_timer(&adapter->phy_config_timer, jiffies + 5 * HZ);
1285 }
1286
1287 return 0;
1288}
1289
1290/*
1291 * atl2_link_chg_task - deal with link change event Out of interrupt context
1292 * @netdev: network interface device structure
1293 */
1294static void atl2_link_chg_task(struct work_struct *work)
1295{
1296 struct atl2_adapter *adapter;
1297 unsigned long flags;
1298
1299 adapter = container_of(work, struct atl2_adapter, link_chg_task);
1300
1301 spin_lock_irqsave(&adapter->stats_lock, flags);
1302 atl2_check_link(adapter);
1303 spin_unlock_irqrestore(&adapter->stats_lock, flags);
1304}
1305
1306static void atl2_setup_pcicmd(struct pci_dev *pdev)
1307{
1308 u16 cmd;
1309
1310 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
1311
1312 if (cmd & PCI_COMMAND_INTX_DISABLE)
1313 cmd &= ~PCI_COMMAND_INTX_DISABLE;
1314 if (cmd & PCI_COMMAND_IO)
1315 cmd &= ~PCI_COMMAND_IO;
1316 if (0 == (cmd & PCI_COMMAND_MEMORY))
1317 cmd |= PCI_COMMAND_MEMORY;
1318 if (0 == (cmd & PCI_COMMAND_MASTER))
1319 cmd |= PCI_COMMAND_MASTER;
1320 pci_write_config_word(pdev, PCI_COMMAND, cmd);
1321
1322 /*
1323 * some motherboards BIOS(PXE/EFI) driver may set PME
1324 * while they transfer control to OS (Windows/Linux)
1325 * so we should clear this bit before NIC work normally
1326 */
1327 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
1328}
1329
1330/*
1331 * atl2_probe - Device Initialization Routine
1332 * @pdev: PCI device information struct
1333 * @ent: entry in atl2_pci_tbl
1334 *
1335 * Returns 0 on success, negative on failure
1336 *
1337 * atl2_probe initializes an adapter identified by a pci_dev structure.
1338 * The OS initialization, configuring of the adapter private structure,
1339 * and a hardware reset occur.
1340 */
1341static int __devinit atl2_probe(struct pci_dev *pdev,
1342 const struct pci_device_id *ent)
1343{
1344 struct net_device *netdev;
1345 struct atl2_adapter *adapter;
1346 static int cards_found;
1347 unsigned long mmio_start;
1348 int mmio_len;
1349 int err;
1350
1351 cards_found = 0;
1352
1353 err = pci_enable_device(pdev);
1354 if (err)
1355 return err;
1356
1357 /*
1358 * atl2 is a shared-high-32-bit device, so we're stuck with 32-bit DMA
1359 * until the kernel has the proper infrastructure to support 64-bit DMA
1360 * on these devices.
1361 */
1362 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) &&
1363 pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1364 printk(KERN_ERR "atl2: No usable DMA configuration, aborting\n");
1365 goto err_dma;
1366 }
1367
1368 /* Mark all PCI regions associated with PCI device
1369 * pdev as being reserved by owner atl2_driver_name */
1370 err = pci_request_regions(pdev, atl2_driver_name);
1371 if (err)
1372 goto err_pci_reg;
1373
1374 /* Enables bus-mastering on the device and calls
1375 * pcibios_set_master to do the needed arch specific settings */
1376 pci_set_master(pdev);
1377
1378 err = -ENOMEM;
1379 netdev = alloc_etherdev(sizeof(struct atl2_adapter));
1380 if (!netdev)
1381 goto err_alloc_etherdev;
1382
1383 SET_NETDEV_DEV(netdev, &pdev->dev);
1384
1385 pci_set_drvdata(pdev, netdev);
1386 adapter = netdev_priv(netdev);
1387 adapter->netdev = netdev;
1388 adapter->pdev = pdev;
1389 adapter->hw.back = adapter;
1390
1391 mmio_start = pci_resource_start(pdev, 0x0);
1392 mmio_len = pci_resource_len(pdev, 0x0);
1393
1394 adapter->hw.mem_rang = (u32)mmio_len;
1395 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
1396 if (!adapter->hw.hw_addr) {
1397 err = -EIO;
1398 goto err_ioremap;
1399 }
1400
1401 atl2_setup_pcicmd(pdev);
1402
1403 netdev->open = &atl2_open;
1404 netdev->stop = &atl2_close;
1405 netdev->hard_start_xmit = &atl2_xmit_frame;
1406 netdev->get_stats = &atl2_get_stats;
1407 netdev->set_multicast_list = &atl2_set_multi;
1408 netdev->set_mac_address = &atl2_set_mac;
1409 netdev->change_mtu = &atl2_change_mtu;
1410 netdev->do_ioctl = &atl2_ioctl;
1411 atl2_set_ethtool_ops(netdev);
1412
1413#ifdef HAVE_TX_TIMEOUT
1414 netdev->tx_timeout = &atl2_tx_timeout;
1415 netdev->watchdog_timeo = 5 * HZ;
1416#endif
1417#ifdef NETIF_F_HW_VLAN_TX
1418 netdev->vlan_rx_register = atl2_vlan_rx_register;
1419#endif
1420 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
1421
1422 netdev->mem_start = mmio_start;
1423 netdev->mem_end = mmio_start + mmio_len;
1424 adapter->bd_number = cards_found;
1425 adapter->pci_using_64 = false;
1426
1427 /* setup the private structure */
1428 err = atl2_sw_init(adapter);
1429 if (err)
1430 goto err_sw_init;
1431
1432 err = -EIO;
1433
1434#ifdef NETIF_F_HW_VLAN_TX
1435 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
1436#endif
1437
1438#ifdef NETIF_F_LLTX
1439 netdev->features |= NETIF_F_LLTX;
1440#endif
1441
1442 /* Init PHY as early as possible due to power saving issue */
1443 atl2_phy_init(&adapter->hw);
1444
1445 /* reset the controller to
1446 * put the device in a known good starting state */
1447
1448 if (atl2_reset_hw(&adapter->hw)) {
1449 err = -EIO;
1450 goto err_reset;
1451 }
1452
1453 /* copy the MAC address out of the EEPROM */
1454 atl2_read_mac_addr(&adapter->hw);
1455 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
1456/* FIXME: do we still need this? */
1457#ifdef ETHTOOL_GPERMADDR
1458 memcpy(netdev->perm_addr, adapter->hw.mac_addr, netdev->addr_len);
1459
1460 if (!is_valid_ether_addr(netdev->perm_addr)) {
1461#else
1462 if (!is_valid_ether_addr(netdev->dev_addr)) {
1463#endif
1464 err = -EIO;
1465 goto err_eeprom;
1466 }
1467
1468 atl2_check_options(adapter);
1469
1470 init_timer(&adapter->watchdog_timer);
1471 adapter->watchdog_timer.function = &atl2_watchdog;
1472 adapter->watchdog_timer.data = (unsigned long) adapter;
1473
1474 init_timer(&adapter->phy_config_timer);
1475 adapter->phy_config_timer.function = &atl2_phy_config;
1476 adapter->phy_config_timer.data = (unsigned long) adapter;
1477
1478 INIT_WORK(&adapter->reset_task, atl2_reset_task);
1479 INIT_WORK(&adapter->link_chg_task, atl2_link_chg_task);
1480
1481 strcpy(netdev->name, "eth%d"); /* ?? */
1482 err = register_netdev(netdev);
1483 if (err)
1484 goto err_register;
1485
1486 /* assume we have no link for now */
1487 netif_carrier_off(netdev);
1488 netif_stop_queue(netdev);
1489
1490 cards_found++;
1491
1492 return 0;
1493
1494err_reset:
1495err_register:
1496err_sw_init:
1497err_eeprom:
1498 iounmap(adapter->hw.hw_addr);
1499err_ioremap:
1500 free_netdev(netdev);
1501err_alloc_etherdev:
1502 pci_release_regions(pdev);
1503err_pci_reg:
1504err_dma:
1505 pci_disable_device(pdev);
1506 return err;
1507}
1508
1509/*
1510 * atl2_remove - Device Removal Routine
1511 * @pdev: PCI device information struct
1512 *
1513 * atl2_remove is called by the PCI subsystem to alert the driver
1514 * that it should release a PCI device. The could be caused by a
1515 * Hot-Plug event, or because the driver is going to be removed from
1516 * memory.
1517 */
1518/* FIXME: write the original MAC address back in case it was changed from a
1519 * BIOS-set value, as in atl1 -- CHS */
1520static void __devexit atl2_remove(struct pci_dev *pdev)
1521{
1522 struct net_device *netdev = pci_get_drvdata(pdev);
1523 struct atl2_adapter *adapter = netdev_priv(netdev);
1524
1525 /* flush_scheduled work may reschedule our watchdog task, so
1526 * explicitly disable watchdog tasks from being rescheduled */
1527 set_bit(__ATL2_DOWN, &adapter->flags);
1528
1529 del_timer_sync(&adapter->watchdog_timer);
1530 del_timer_sync(&adapter->phy_config_timer);
1531
1532 flush_scheduled_work();
1533
1534 unregister_netdev(netdev);
1535
1536 atl2_force_ps(&adapter->hw);
1537
1538 iounmap(adapter->hw.hw_addr);
1539 pci_release_regions(pdev);
1540
1541 free_netdev(netdev);
1542
1543 pci_disable_device(pdev);
1544}
1545
1546static int atl2_suspend(struct pci_dev *pdev, pm_message_t state)
1547{
1548 struct net_device *netdev = pci_get_drvdata(pdev);
1549 struct atl2_adapter *adapter = netdev_priv(netdev);
1550 struct atl2_hw *hw = &adapter->hw;
1551 u16 speed, duplex;
1552 u32 ctrl = 0;
1553 u32 wufc = adapter->wol;
1554
1555#ifdef CONFIG_PM
1556 int retval = 0;
1557#endif
1558
1559 netif_device_detach(netdev);
1560
1561 if (netif_running(netdev)) {
1562 WARN_ON(test_bit(__ATL2_RESETTING, &adapter->flags));
1563 atl2_down(adapter);
1564 }
1565
1566#ifdef CONFIG_PM
1567 retval = pci_save_state(pdev);
1568 if (retval)
1569 return retval;
1570#endif
1571
1572 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1573 atl2_read_phy_reg(hw, MII_BMSR, (u16 *)&ctrl);
1574 if (ctrl & BMSR_LSTATUS)
1575 wufc &= ~ATLX_WUFC_LNKC;
1576
1577 if (0 != (ctrl & BMSR_LSTATUS) && 0 != wufc) {
1578 u32 ret_val;
1579 /* get current link speed & duplex */
1580 ret_val = atl2_get_speed_and_duplex(hw, &speed, &duplex);
1581 if (ret_val) {
1582 printk(KERN_DEBUG
1583 "%s: get speed&duplex error while suspend\n",
1584 atl2_driver_name);
1585 goto wol_dis;
1586 }
1587
1588 ctrl = 0;
1589
1590 /* turn on magic packet wol */
1591 if (wufc & ATLX_WUFC_MAG)
1592 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
1593
1594 /* ignore Link Chg event when Link is up */
1595 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1596
1597 /* Config MAC CTRL Register */
1598 ctrl = MAC_CTRL_RX_EN | MAC_CTRL_MACLP_CLK_PHY;
1599 if (FULL_DUPLEX == adapter->link_duplex)
1600 ctrl |= MAC_CTRL_DUPLX;
1601 ctrl |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1602 ctrl |= (((u32)adapter->hw.preamble_len &
1603 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1604 ctrl |= (((u32)(adapter->hw.retry_buf &
1605 MAC_CTRL_HALF_LEFT_BUF_MASK)) <<
1606 MAC_CTRL_HALF_LEFT_BUF_SHIFT);
1607 if (wufc & ATLX_WUFC_MAG) {
1608 /* magic packet maybe Broadcast&multicast&Unicast */
1609 ctrl |= MAC_CTRL_BC_EN;
1610 }
1611
1612 ATL2_WRITE_REG(hw, REG_MAC_CTRL, ctrl);
1613
1614 /* pcie patch */
1615 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1616 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1617 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1618 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1619 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1620 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1621
1622 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1623 goto suspend_exit;
1624 }
1625
1626 if (0 == (ctrl&BMSR_LSTATUS) && 0 != (wufc&ATLX_WUFC_LNKC)) {
1627 /* link is down, so only LINK CHG WOL event enable */
1628 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
1629 ATL2_WRITE_REG(hw, REG_WOL_CTRL, ctrl);
1630 ATL2_WRITE_REG(hw, REG_MAC_CTRL, 0);
1631
1632 /* pcie patch */
1633 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1634 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1635 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1636 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1637 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1638 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1639
1640 hw->phy_configured = false; /* re-init PHY when resume */
1641
1642 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
1643
1644 goto suspend_exit;
1645 }
1646
1647wol_dis:
1648 /* WOL disabled */
1649 ATL2_WRITE_REG(hw, REG_WOL_CTRL, 0);
1650
1651 /* pcie patch */
1652 ctrl = ATL2_READ_REG(hw, REG_PCIE_PHYMISC);
1653 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
1654 ATL2_WRITE_REG(hw, REG_PCIE_PHYMISC, ctrl);
1655 ctrl = ATL2_READ_REG(hw, REG_PCIE_DLL_TX_CTRL1);
1656 ctrl |= PCIE_DLL_TX_CTRL1_SEL_NOR_CLK;
1657 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, ctrl);
1658
1659 atl2_force_ps(hw);
1660 hw->phy_configured = false; /* re-init PHY when resume */
1661
1662 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1663
1664suspend_exit:
1665 if (netif_running(netdev))
1666 atl2_free_irq(adapter);
1667
1668 pci_disable_device(pdev);
1669
1670 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1671
1672 return 0;
1673}
1674
1675#ifdef CONFIG_PM
1676static int atl2_resume(struct pci_dev *pdev)
1677{
1678 struct net_device *netdev = pci_get_drvdata(pdev);
1679 struct atl2_adapter *adapter = netdev_priv(netdev);
1680 u32 err;
1681
1682 pci_set_power_state(pdev, PCI_D0);
1683 pci_restore_state(pdev);
1684
1685 err = pci_enable_device(pdev);
1686 if (err) {
1687 printk(KERN_ERR
1688 "atl2: Cannot enable PCI device from suspend\n");
1689 return err;
1690 }
1691
1692 pci_set_master(pdev);
1693
1694 ATL2_READ_REG(&adapter->hw, REG_WOL_CTRL); /* clear WOL status */
1695
1696 pci_enable_wake(pdev, PCI_D3hot, 0);
1697 pci_enable_wake(pdev, PCI_D3cold, 0);
1698
1699 ATL2_WRITE_REG(&adapter->hw, REG_WOL_CTRL, 0);
1700
1701 err = atl2_request_irq(adapter);
1702 if (netif_running(netdev) && err)
1703 return err;
1704
1705 atl2_reset_hw(&adapter->hw);
1706
1707 if (netif_running(netdev))
1708 atl2_up(adapter);
1709
1710 netif_device_attach(netdev);
1711
1712 return 0;
1713}
1714#endif
1715
1716static void atl2_shutdown(struct pci_dev *pdev)
1717{
1718 atl2_suspend(pdev, PMSG_SUSPEND);
1719}
1720
1721static struct pci_driver atl2_driver = {
1722 .name = atl2_driver_name,
1723 .id_table = atl2_pci_tbl,
1724 .probe = atl2_probe,
1725 .remove = __devexit_p(atl2_remove),
1726 /* Power Managment Hooks */
1727 .suspend = atl2_suspend,
1728#ifdef CONFIG_PM
1729 .resume = atl2_resume,
1730#endif
1731 .shutdown = atl2_shutdown,
1732};
1733
1734/*
1735 * atl2_init_module - Driver Registration Routine
1736 *
1737 * atl2_init_module is the first routine called when the driver is
1738 * loaded. All it does is register with the PCI subsystem.
1739 */
1740static int __init atl2_init_module(void)
1741{
1742 printk(KERN_INFO "%s - version %s\n", atl2_driver_string,
1743 atl2_driver_version);
1744 printk(KERN_INFO "%s\n", atl2_copyright);
1745 return pci_register_driver(&atl2_driver);
1746}
1747module_init(atl2_init_module);
1748
1749/*
1750 * atl2_exit_module - Driver Exit Cleanup Routine
1751 *
1752 * atl2_exit_module is called just before the driver is removed
1753 * from memory.
1754 */
1755static void __exit atl2_exit_module(void)
1756{
1757 pci_unregister_driver(&atl2_driver);
1758}
1759module_exit(atl2_exit_module);
1760
1761static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1762{
1763 struct atl2_adapter *adapter = hw->back;
1764 pci_read_config_word(adapter->pdev, reg, value);
1765}
1766
1767static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value)
1768{
1769 struct atl2_adapter *adapter = hw->back;
1770 pci_write_config_word(adapter->pdev, reg, *value);
1771}
1772
1773static int atl2_get_settings(struct net_device *netdev,
1774 struct ethtool_cmd *ecmd)
1775{
1776 struct atl2_adapter *adapter = netdev_priv(netdev);
1777 struct atl2_hw *hw = &adapter->hw;
1778
1779 ecmd->supported = (SUPPORTED_10baseT_Half |
1780 SUPPORTED_10baseT_Full |
1781 SUPPORTED_100baseT_Half |
1782 SUPPORTED_100baseT_Full |
1783 SUPPORTED_Autoneg |
1784 SUPPORTED_TP);
1785 ecmd->advertising = ADVERTISED_TP;
1786
1787 ecmd->advertising |= ADVERTISED_Autoneg;
1788 ecmd->advertising |= hw->autoneg_advertised;
1789
1790 ecmd->port = PORT_TP;
1791 ecmd->phy_address = 0;
1792 ecmd->transceiver = XCVR_INTERNAL;
1793
1794 if (adapter->link_speed != SPEED_0) {
1795 ecmd->speed = adapter->link_speed;
1796 if (adapter->link_duplex == FULL_DUPLEX)
1797 ecmd->duplex = DUPLEX_FULL;
1798 else
1799 ecmd->duplex = DUPLEX_HALF;
1800 } else {
1801 ecmd->speed = -1;
1802 ecmd->duplex = -1;
1803 }
1804
1805 ecmd->autoneg = AUTONEG_ENABLE;
1806 return 0;
1807}
1808
1809static int atl2_set_settings(struct net_device *netdev,
1810 struct ethtool_cmd *ecmd)
1811{
1812 struct atl2_adapter *adapter = netdev_priv(netdev);
1813 struct atl2_hw *hw = &adapter->hw;
1814
1815 while (test_and_set_bit(__ATL2_RESETTING, &adapter->flags))
1816 msleep(1);
1817
1818 if (ecmd->autoneg == AUTONEG_ENABLE) {
1819#define MY_ADV_MASK (ADVERTISE_10_HALF | \
1820 ADVERTISE_10_FULL | \
1821 ADVERTISE_100_HALF| \
1822 ADVERTISE_100_FULL)
1823
1824 if ((ecmd->advertising & MY_ADV_MASK) == MY_ADV_MASK) {
1825 hw->MediaType = MEDIA_TYPE_AUTO_SENSOR;
1826 hw->autoneg_advertised = MY_ADV_MASK;
1827 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1828 ADVERTISE_100_FULL) {
1829 hw->MediaType = MEDIA_TYPE_100M_FULL;
1830 hw->autoneg_advertised = ADVERTISE_100_FULL;
1831 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1832 ADVERTISE_100_HALF) {
1833 hw->MediaType = MEDIA_TYPE_100M_HALF;
1834 hw->autoneg_advertised = ADVERTISE_100_HALF;
1835 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1836 ADVERTISE_10_FULL) {
1837 hw->MediaType = MEDIA_TYPE_10M_FULL;
1838 hw->autoneg_advertised = ADVERTISE_10_FULL;
1839 } else if ((ecmd->advertising & MY_ADV_MASK) ==
1840 ADVERTISE_10_HALF) {
1841 hw->MediaType = MEDIA_TYPE_10M_HALF;
1842 hw->autoneg_advertised = ADVERTISE_10_HALF;
1843 } else {
1844 clear_bit(__ATL2_RESETTING, &adapter->flags);
1845 return -EINVAL;
1846 }
1847 ecmd->advertising = hw->autoneg_advertised |
1848 ADVERTISED_TP | ADVERTISED_Autoneg;
1849 } else {
1850 clear_bit(__ATL2_RESETTING, &adapter->flags);
1851 return -EINVAL;
1852 }
1853
1854 /* reset the link */
1855 if (netif_running(adapter->netdev)) {
1856 atl2_down(adapter);
1857 atl2_up(adapter);
1858 } else
1859 atl2_reset_hw(&adapter->hw);
1860
1861 clear_bit(__ATL2_RESETTING, &adapter->flags);
1862 return 0;
1863}
1864
1865static u32 atl2_get_tx_csum(struct net_device *netdev)
1866{
1867 return (netdev->features & NETIF_F_HW_CSUM) != 0;
1868}
1869
1870static u32 atl2_get_msglevel(struct net_device *netdev)
1871{
1872 return 0;
1873}
1874
1875/*
1876 * It's sane for this to be empty, but we might want to take advantage of this.
1877 */
1878static void atl2_set_msglevel(struct net_device *netdev, u32 data)
1879{
1880}
1881
1882static int atl2_get_regs_len(struct net_device *netdev)
1883{
1884#define ATL2_REGS_LEN 42
1885 return sizeof(u32) * ATL2_REGS_LEN;
1886}
1887
1888static void atl2_get_regs(struct net_device *netdev,
1889 struct ethtool_regs *regs, void *p)
1890{
1891 struct atl2_adapter *adapter = netdev_priv(netdev);
1892 struct atl2_hw *hw = &adapter->hw;
1893 u32 *regs_buff = p;
1894 u16 phy_data;
1895
1896 memset(p, 0, sizeof(u32) * ATL2_REGS_LEN);
1897
1898 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
1899
1900 regs_buff[0] = ATL2_READ_REG(hw, REG_VPD_CAP);
1901 regs_buff[1] = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
1902 regs_buff[2] = ATL2_READ_REG(hw, REG_SPI_FLASH_CONFIG);
1903 regs_buff[3] = ATL2_READ_REG(hw, REG_TWSI_CTRL);
1904 regs_buff[4] = ATL2_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL);
1905 regs_buff[5] = ATL2_READ_REG(hw, REG_MASTER_CTRL);
1906 regs_buff[6] = ATL2_READ_REG(hw, REG_MANUAL_TIMER_INIT);
1907 regs_buff[7] = ATL2_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT);
1908 regs_buff[8] = ATL2_READ_REG(hw, REG_PHY_ENABLE);
1909 regs_buff[9] = ATL2_READ_REG(hw, REG_CMBDISDMA_TIMER);
1910 regs_buff[10] = ATL2_READ_REG(hw, REG_IDLE_STATUS);
1911 regs_buff[11] = ATL2_READ_REG(hw, REG_MDIO_CTRL);
1912 regs_buff[12] = ATL2_READ_REG(hw, REG_SERDES_LOCK);
1913 regs_buff[13] = ATL2_READ_REG(hw, REG_MAC_CTRL);
1914 regs_buff[14] = ATL2_READ_REG(hw, REG_MAC_IPG_IFG);
1915 regs_buff[15] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
1916 regs_buff[16] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR+4);
1917 regs_buff[17] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE);
1918 regs_buff[18] = ATL2_READ_REG(hw, REG_RX_HASH_TABLE+4);
1919 regs_buff[19] = ATL2_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL);
1920 regs_buff[20] = ATL2_READ_REG(hw, REG_MTU);
1921 regs_buff[21] = ATL2_READ_REG(hw, REG_WOL_CTRL);
1922 regs_buff[22] = ATL2_READ_REG(hw, REG_SRAM_TXRAM_END);
1923 regs_buff[23] = ATL2_READ_REG(hw, REG_DESC_BASE_ADDR_HI);
1924 regs_buff[24] = ATL2_READ_REG(hw, REG_TXD_BASE_ADDR_LO);
1925 regs_buff[25] = ATL2_READ_REG(hw, REG_TXD_MEM_SIZE);
1926 regs_buff[26] = ATL2_READ_REG(hw, REG_TXS_BASE_ADDR_LO);
1927 regs_buff[27] = ATL2_READ_REG(hw, REG_TXS_MEM_SIZE);
1928 regs_buff[28] = ATL2_READ_REG(hw, REG_RXD_BASE_ADDR_LO);
1929 regs_buff[29] = ATL2_READ_REG(hw, REG_RXD_BUF_NUM);
1930 regs_buff[30] = ATL2_READ_REG(hw, REG_DMAR);
1931 regs_buff[31] = ATL2_READ_REG(hw, REG_TX_CUT_THRESH);
1932 regs_buff[32] = ATL2_READ_REG(hw, REG_DMAW);
1933 regs_buff[33] = ATL2_READ_REG(hw, REG_PAUSE_ON_TH);
1934 regs_buff[34] = ATL2_READ_REG(hw, REG_PAUSE_OFF_TH);
1935 regs_buff[35] = ATL2_READ_REG(hw, REG_MB_TXD_WR_IDX);
1936 regs_buff[36] = ATL2_READ_REG(hw, REG_MB_RXD_RD_IDX);
1937 regs_buff[38] = ATL2_READ_REG(hw, REG_ISR);
1938 regs_buff[39] = ATL2_READ_REG(hw, REG_IMR);
1939
1940 atl2_read_phy_reg(hw, MII_BMCR, &phy_data);
1941 regs_buff[40] = (u32)phy_data;
1942 atl2_read_phy_reg(hw, MII_BMSR, &phy_data);
1943 regs_buff[41] = (u32)phy_data;
1944}
1945
1946static int atl2_get_eeprom_len(struct net_device *netdev)
1947{
1948 struct atl2_adapter *adapter = netdev_priv(netdev);
1949
1950 if (!atl2_check_eeprom_exist(&adapter->hw))
1951 return 512;
1952 else
1953 return 0;
1954}
1955
1956static int atl2_get_eeprom(struct net_device *netdev,
1957 struct ethtool_eeprom *eeprom, u8 *bytes)
1958{
1959 struct atl2_adapter *adapter = netdev_priv(netdev);
1960 struct atl2_hw *hw = &adapter->hw;
1961 u32 *eeprom_buff;
1962 int first_dword, last_dword;
1963 int ret_val = 0;
1964 int i;
1965
1966 if (eeprom->len == 0)
1967 return -EINVAL;
1968
1969 if (atl2_check_eeprom_exist(hw))
1970 return -EINVAL;
1971
1972 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1973
1974 first_dword = eeprom->offset >> 2;
1975 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
1976
1977 eeprom_buff = kmalloc(sizeof(u32) * (last_dword - first_dword + 1),
1978 GFP_KERNEL);
1979 if (!eeprom_buff)
1980 return -ENOMEM;
1981
1982 for (i = first_dword; i < last_dword; i++) {
1983 if (!atl2_read_eeprom(hw, i*4, &(eeprom_buff[i-first_dword])))
1984 return -EIO;
1985 }
1986
1987 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 3),
1988 eeprom->len);
1989 kfree(eeprom_buff);
1990
1991 return ret_val;
1992}
1993
1994static int atl2_set_eeprom(struct net_device *netdev,
1995 struct ethtool_eeprom *eeprom, u8 *bytes)
1996{
1997 struct atl2_adapter *adapter = netdev_priv(netdev);
1998 struct atl2_hw *hw = &adapter->hw;
1999 u32 *eeprom_buff;
2000 u32 *ptr;
2001 int max_len, first_dword, last_dword, ret_val = 0;
2002 int i;
2003
2004 if (eeprom->len == 0)
2005 return -EOPNOTSUPP;
2006
2007 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
2008 return -EFAULT;
2009
2010 max_len = 512;
2011
2012 first_dword = eeprom->offset >> 2;
2013 last_dword = (eeprom->offset + eeprom->len - 1) >> 2;
2014 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
2015 if (!eeprom_buff)
2016 return -ENOMEM;
2017
2018 ptr = (u32 *)eeprom_buff;
2019
2020 if (eeprom->offset & 3) {
2021 /* need read/modify/write of first changed EEPROM word */
2022 /* only the second byte of the word is being modified */
2023 if (!atl2_read_eeprom(hw, first_dword*4, &(eeprom_buff[0])))
2024 return -EIO;
2025 ptr++;
2026 }
2027 if (((eeprom->offset + eeprom->len) & 3)) {
2028 /*
2029 * need read/modify/write of last changed EEPROM word
2030 * only the first byte of the word is being modified
2031 */
2032 if (!atl2_read_eeprom(hw, last_dword * 4,
2033 &(eeprom_buff[last_dword - first_dword])))
2034 return -EIO;
2035 }
2036
2037 /* Device's eeprom is always little-endian, word addressable */
2038 memcpy(ptr, bytes, eeprom->len);
2039
2040 for (i = 0; i < last_dword - first_dword + 1; i++) {
2041 if (!atl2_write_eeprom(hw, ((first_dword+i)*4), eeprom_buff[i]))
2042 return -EIO;
2043 }
2044
2045 kfree(eeprom_buff);
2046 return ret_val;
2047}
2048
2049static void atl2_get_drvinfo(struct net_device *netdev,
2050 struct ethtool_drvinfo *drvinfo)
2051{
2052 struct atl2_adapter *adapter = netdev_priv(netdev);
2053
2054 strncpy(drvinfo->driver, atl2_driver_name, 32);
2055 strncpy(drvinfo->version, atl2_driver_version, 32);
2056 strncpy(drvinfo->fw_version, "L2", 32);
2057 strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
2058 drvinfo->n_stats = 0;
2059 drvinfo->testinfo_len = 0;
2060 drvinfo->regdump_len = atl2_get_regs_len(netdev);
2061 drvinfo->eedump_len = atl2_get_eeprom_len(netdev);
2062}
2063
2064static void atl2_get_wol(struct net_device *netdev,
2065 struct ethtool_wolinfo *wol)
2066{
2067 struct atl2_adapter *adapter = netdev_priv(netdev);
2068
2069 wol->supported = WAKE_MAGIC;
2070 wol->wolopts = 0;
2071
2072 if (adapter->wol & ATLX_WUFC_EX)
2073 wol->wolopts |= WAKE_UCAST;
2074 if (adapter->wol & ATLX_WUFC_MC)
2075 wol->wolopts |= WAKE_MCAST;
2076 if (adapter->wol & ATLX_WUFC_BC)
2077 wol->wolopts |= WAKE_BCAST;
2078 if (adapter->wol & ATLX_WUFC_MAG)
2079 wol->wolopts |= WAKE_MAGIC;
2080 if (adapter->wol & ATLX_WUFC_LNKC)
2081 wol->wolopts |= WAKE_PHY;
2082}
2083
2084static int atl2_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2085{
2086 struct atl2_adapter *adapter = netdev_priv(netdev);
2087
2088 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2089 return -EOPNOTSUPP;
2090
2091 if (wol->wolopts & (WAKE_MCAST|WAKE_BCAST|WAKE_MCAST))
2092 return -EOPNOTSUPP;
2093
2094 /* these settings will always override what we currently have */
2095 adapter->wol = 0;
2096
2097 if (wol->wolopts & WAKE_MAGIC)
2098 adapter->wol |= ATLX_WUFC_MAG;
2099 if (wol->wolopts & WAKE_PHY)
2100 adapter->wol |= ATLX_WUFC_LNKC;
2101
2102 return 0;
2103}
2104
2105static int atl2_nway_reset(struct net_device *netdev)
2106{
2107 struct atl2_adapter *adapter = netdev_priv(netdev);
2108 if (netif_running(netdev))
2109 atl2_reinit_locked(adapter);
2110 return 0;
2111}
2112
2113static struct ethtool_ops atl2_ethtool_ops = {
2114 .get_settings = atl2_get_settings,
2115 .set_settings = atl2_set_settings,
2116 .get_drvinfo = atl2_get_drvinfo,
2117 .get_regs_len = atl2_get_regs_len,
2118 .get_regs = atl2_get_regs,
2119 .get_wol = atl2_get_wol,
2120 .set_wol = atl2_set_wol,
2121 .get_msglevel = atl2_get_msglevel,
2122 .set_msglevel = atl2_set_msglevel,
2123 .nway_reset = atl2_nway_reset,
2124 .get_link = ethtool_op_get_link,
2125 .get_eeprom_len = atl2_get_eeprom_len,
2126 .get_eeprom = atl2_get_eeprom,
2127 .set_eeprom = atl2_set_eeprom,
2128 .get_tx_csum = atl2_get_tx_csum,
2129 .get_sg = ethtool_op_get_sg,
2130 .set_sg = ethtool_op_set_sg,
2131#ifdef NETIF_F_TSO
2132 .get_tso = ethtool_op_get_tso,
2133#endif
2134};
2135
2136static void atl2_set_ethtool_ops(struct net_device *netdev)
2137{
2138 SET_ETHTOOL_OPS(netdev, &atl2_ethtool_ops);
2139}
2140
2141#define LBYTESWAP(a) ((((a) & 0x00ff00ff) << 8) | \
2142 (((a) & 0xff00ff00) >> 8))
2143#define LONGSWAP(a) ((LBYTESWAP(a) << 16) | (LBYTESWAP(a) >> 16))
2144#define SHORTSWAP(a) (((a) << 8) | ((a) >> 8))
2145
2146/*
2147 * Reset the transmit and receive units; mask and clear all interrupts.
2148 *
2149 * hw - Struct containing variables accessed by shared code
2150 * return : 0 or idle status (if error)
2151 */
2152static s32 atl2_reset_hw(struct atl2_hw *hw)
2153{
2154 u32 icr;
2155 u16 pci_cfg_cmd_word;
2156 int i;
2157
2158 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
2159 atl2_read_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2160 if ((pci_cfg_cmd_word &
2161 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) !=
2162 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER)) {
2163 pci_cfg_cmd_word |=
2164 (CMD_IO_SPACE|CMD_MEMORY_SPACE|CMD_BUS_MASTER);
2165 atl2_write_pci_cfg(hw, PCI_REG_COMMAND, &pci_cfg_cmd_word);
2166 }
2167
2168 /* Clear Interrupt mask to stop board from generating
2169 * interrupts & Clear any pending interrupt events
2170 */
2171 /* FIXME */
2172 /* ATL2_WRITE_REG(hw, REG_IMR, 0); */
2173 /* ATL2_WRITE_REG(hw, REG_ISR, 0xffffffff); */
2174
2175 /* Issue Soft Reset to the MAC. This will reset the chip's
2176 * transmit, receive, DMA. It will not effect
2177 * the current PCI configuration. The global reset bit is self-
2178 * clearing, and should clear within a microsecond.
2179 */
2180 ATL2_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_SOFT_RST);
2181 wmb();
2182 msleep(1); /* delay about 1ms */
2183
2184 /* Wait at least 10ms for All module to be Idle */
2185 for (i = 0; i < 10; i++) {
2186 icr = ATL2_READ_REG(hw, REG_IDLE_STATUS);
2187 if (!icr)
2188 break;
2189 msleep(1); /* delay 1 ms */
2190 cpu_relax();
2191 }
2192
2193 if (icr)
2194 return icr;
2195
2196 return 0;
2197}
2198
2199#define CUSTOM_SPI_CS_SETUP 2
2200#define CUSTOM_SPI_CLK_HI 2
2201#define CUSTOM_SPI_CLK_LO 2
2202#define CUSTOM_SPI_CS_HOLD 2
2203#define CUSTOM_SPI_CS_HI 3
2204
2205static struct atl2_spi_flash_dev flash_table[] =
2206{
2207/* MFR WRSR READ PROGRAM WREN WRDI RDSR RDID SECTOR_ERASE CHIP_ERASE */
2208{"Atmel", 0x0, 0x03, 0x02, 0x06, 0x04, 0x05, 0x15, 0x52, 0x62 },
2209{"SST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0x90, 0x20, 0x60 },
2210{"ST", 0x01, 0x03, 0x02, 0x06, 0x04, 0x05, 0xAB, 0xD8, 0xC7 },
2211};
2212
2213static bool atl2_spi_read(struct atl2_hw *hw, u32 addr, u32 *buf)
2214{
2215 int i;
2216 u32 value;
2217
2218 ATL2_WRITE_REG(hw, REG_SPI_DATA, 0);
2219 ATL2_WRITE_REG(hw, REG_SPI_ADDR, addr);
2220
2221 value = SPI_FLASH_CTRL_WAIT_READY |
2222 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
2223 SPI_FLASH_CTRL_CS_SETUP_SHIFT |
2224 (CUSTOM_SPI_CLK_HI & SPI_FLASH_CTRL_CLK_HI_MASK) <<
2225 SPI_FLASH_CTRL_CLK_HI_SHIFT |
2226 (CUSTOM_SPI_CLK_LO & SPI_FLASH_CTRL_CLK_LO_MASK) <<
2227 SPI_FLASH_CTRL_CLK_LO_SHIFT |
2228 (CUSTOM_SPI_CS_HOLD & SPI_FLASH_CTRL_CS_HOLD_MASK) <<
2229 SPI_FLASH_CTRL_CS_HOLD_SHIFT |
2230 (CUSTOM_SPI_CS_HI & SPI_FLASH_CTRL_CS_HI_MASK) <<
2231 SPI_FLASH_CTRL_CS_HI_SHIFT |
2232 (0x1 & SPI_FLASH_CTRL_INS_MASK) << SPI_FLASH_CTRL_INS_SHIFT;
2233
2234 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2235
2236 value |= SPI_FLASH_CTRL_START;
2237
2238 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2239
2240 for (i = 0; i < 10; i++) {
2241 msleep(1);
2242 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2243 if (!(value & SPI_FLASH_CTRL_START))
2244 break;
2245 }
2246
2247 if (value & SPI_FLASH_CTRL_START)
2248 return false;
2249
2250 *buf = ATL2_READ_REG(hw, REG_SPI_DATA);
2251
2252 return true;
2253}
2254
2255/*
2256 * get_permanent_address
2257 * return 0 if get valid mac address,
2258 */
2259static int get_permanent_address(struct atl2_hw *hw)
2260{
2261 u32 Addr[2];
2262 u32 i, Control;
2263 u16 Register;
2264 u8 EthAddr[NODE_ADDRESS_SIZE];
2265 bool KeyValid;
2266
2267 if (is_valid_ether_addr(hw->perm_mac_addr))
2268 return 0;
2269
2270 Addr[0] = 0;
2271 Addr[1] = 0;
2272
2273 if (!atl2_check_eeprom_exist(hw)) { /* eeprom exists */
2274 Register = 0;
2275 KeyValid = false;
2276
2277 /* Read out all EEPROM content */
2278 i = 0;
2279 while (1) {
2280 if (atl2_read_eeprom(hw, i + 0x100, &Control)) {
2281 if (KeyValid) {
2282 if (Register == REG_MAC_STA_ADDR)
2283 Addr[0] = Control;
2284 else if (Register ==
2285 (REG_MAC_STA_ADDR + 4))
2286 Addr[1] = Control;
2287 KeyValid = false;
2288 } else if ((Control & 0xff) == 0x5A) {
2289 KeyValid = true;
2290 Register = (u16) (Control >> 16);
2291 } else {
2292 /* assume data end while encount an invalid KEYWORD */
2293 break;
2294 }
2295 } else {
2296 break; /* read error */
2297 }
2298 i += 4;
2299 }
2300
2301 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2302 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2303
2304 if (is_valid_ether_addr(EthAddr)) {
2305 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2306 return 0;
2307 }
2308 return 1;
2309 }
2310
2311 /* see if SPI flash exists? */
2312 Addr[0] = 0;
2313 Addr[1] = 0;
2314 Register = 0;
2315 KeyValid = false;
2316 i = 0;
2317 while (1) {
2318 if (atl2_spi_read(hw, i + 0x1f000, &Control)) {
2319 if (KeyValid) {
2320 if (Register == REG_MAC_STA_ADDR)
2321 Addr[0] = Control;
2322 else if (Register == (REG_MAC_STA_ADDR + 4))
2323 Addr[1] = Control;
2324 KeyValid = false;
2325 } else if ((Control & 0xff) == 0x5A) {
2326 KeyValid = true;
2327 Register = (u16) (Control >> 16);
2328 } else {
2329 break; /* data end */
2330 }
2331 } else {
2332 break; /* read error */
2333 }
2334 i += 4;
2335 }
2336
2337 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2338 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *)&Addr[1]);
2339 if (is_valid_ether_addr(EthAddr)) {
2340 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2341 return 0;
2342 }
2343 /* maybe MAC-address is from BIOS */
2344 Addr[0] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR);
2345 Addr[1] = ATL2_READ_REG(hw, REG_MAC_STA_ADDR + 4);
2346 *(u32 *) &EthAddr[2] = LONGSWAP(Addr[0]);
2347 *(u16 *) &EthAddr[0] = SHORTSWAP(*(u16 *) &Addr[1]);
2348
2349 if (is_valid_ether_addr(EthAddr)) {
2350 memcpy(hw->perm_mac_addr, EthAddr, NODE_ADDRESS_SIZE);
2351 return 0;
2352 }
2353
2354 return 1;
2355}
2356
2357/*
2358 * Reads the adapter's MAC address from the EEPROM
2359 *
2360 * hw - Struct containing variables accessed by shared code
2361 */
2362static s32 atl2_read_mac_addr(struct atl2_hw *hw)
2363{
2364 u16 i;
2365
2366 if (get_permanent_address(hw)) {
2367 /* for test */
2368 /* FIXME: shouldn't we use random_ether_addr() here? */
2369 hw->perm_mac_addr[0] = 0x00;
2370 hw->perm_mac_addr[1] = 0x13;
2371 hw->perm_mac_addr[2] = 0x74;
2372 hw->perm_mac_addr[3] = 0x00;
2373 hw->perm_mac_addr[4] = 0x5c;
2374 hw->perm_mac_addr[5] = 0x38;
2375 }
2376
2377 for (i = 0; i < NODE_ADDRESS_SIZE; i++)
2378 hw->mac_addr[i] = hw->perm_mac_addr[i];
2379
2380 return 0;
2381}
2382
2383/*
2384 * Hashes an address to determine its location in the multicast table
2385 *
2386 * hw - Struct containing variables accessed by shared code
2387 * mc_addr - the multicast address to hash
2388 *
2389 * atl2_hash_mc_addr
2390 * purpose
2391 * set hash value for a multicast address
2392 * hash calcu processing :
2393 * 1. calcu 32bit CRC for multicast address
2394 * 2. reverse crc with MSB to LSB
2395 */
2396static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr)
2397{
2398 u32 crc32, value;
2399 int i;
2400
2401 value = 0;
2402 crc32 = ether_crc_le(6, mc_addr);
2403
2404 for (i = 0; i < 32; i++)
2405 value |= (((crc32 >> i) & 1) << (31 - i));
2406
2407 return value;
2408}
2409
2410/*
2411 * Sets the bit in the multicast table corresponding to the hash value.
2412 *
2413 * hw - Struct containing variables accessed by shared code
2414 * hash_value - Multicast address hash value
2415 */
2416static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value)
2417{
2418 u32 hash_bit, hash_reg;
2419 u32 mta;
2420
2421 /* The HASH Table is a register array of 2 32-bit registers.
2422 * It is treated like an array of 64 bits. We want to set
2423 * bit BitArray[hash_value]. So we figure out what register
2424 * the bit is in, read it, OR in the new bit, then write
2425 * back the new value. The register is determined by the
2426 * upper 7 bits of the hash value and the bit within that
2427 * register are determined by the lower 5 bits of the value.
2428 */
2429 hash_reg = (hash_value >> 31) & 0x1;
2430 hash_bit = (hash_value >> 26) & 0x1F;
2431
2432 mta = ATL2_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
2433
2434 mta |= (1 << hash_bit);
2435
2436 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
2437}
2438
2439/*
2440 * atl2_init_pcie - init PCIE module
2441 */
2442static void atl2_init_pcie(struct atl2_hw *hw)
2443{
2444 u32 value;
2445 value = LTSSM_TEST_MODE_DEF;
2446 ATL2_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
2447
2448 value = PCIE_DLL_TX_CTRL1_DEF;
2449 ATL2_WRITE_REG(hw, REG_PCIE_DLL_TX_CTRL1, value);
2450}
2451
2452static void atl2_init_flash_opcode(struct atl2_hw *hw)
2453{
2454 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
2455 hw->flash_vendor = 0; /* ATMEL */
2456
2457 /* Init OP table */
2458 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_PROGRAM,
2459 flash_table[hw->flash_vendor].cmdPROGRAM);
2460 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_SC_ERASE,
2461 flash_table[hw->flash_vendor].cmdSECTOR_ERASE);
2462 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_CHIP_ERASE,
2463 flash_table[hw->flash_vendor].cmdCHIP_ERASE);
2464 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDID,
2465 flash_table[hw->flash_vendor].cmdRDID);
2466 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WREN,
2467 flash_table[hw->flash_vendor].cmdWREN);
2468 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_RDSR,
2469 flash_table[hw->flash_vendor].cmdRDSR);
2470 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_WRSR,
2471 flash_table[hw->flash_vendor].cmdWRSR);
2472 ATL2_WRITE_REGB(hw, REG_SPI_FLASH_OP_READ,
2473 flash_table[hw->flash_vendor].cmdREAD);
2474}
2475
2476/********************************************************************
2477* Performs basic configuration of the adapter.
2478*
2479* hw - Struct containing variables accessed by shared code
2480* Assumes that the controller has previously been reset and is in a
2481* post-reset uninitialized state. Initializes multicast table,
2482* and Calls routines to setup link
2483* Leaves the transmit and receive units disabled and uninitialized.
2484********************************************************************/
2485static s32 atl2_init_hw(struct atl2_hw *hw)
2486{
2487 u32 ret_val = 0;
2488
2489 atl2_init_pcie(hw);
2490
2491 /* Zero out the Multicast HASH table */
2492 /* clear the old settings from the multicast hash table */
2493 ATL2_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
2494 ATL2_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
2495
2496 atl2_init_flash_opcode(hw);
2497
2498 ret_val = atl2_phy_init(hw);
2499
2500 return ret_val;
2501}
2502
2503/*
2504 * Detects the current speed and duplex settings of the hardware.
2505 *
2506 * hw - Struct containing variables accessed by shared code
2507 * speed - Speed of the connection
2508 * duplex - Duplex setting of the connection
2509 */
2510static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
2511 u16 *duplex)
2512{
2513 s32 ret_val;
2514 u16 phy_data;
2515
2516 /* Read PHY Specific Status Register (17) */
2517 ret_val = atl2_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
2518 if (ret_val)
2519 return ret_val;
2520
2521 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
2522 return ATLX_ERR_PHY_RES;
2523
2524 switch (phy_data & MII_ATLX_PSSR_SPEED) {
2525 case MII_ATLX_PSSR_100MBS:
2526 *speed = SPEED_100;
2527 break;
2528 case MII_ATLX_PSSR_10MBS:
2529 *speed = SPEED_10;
2530 break;
2531 default:
2532 return ATLX_ERR_PHY_SPEED;
2533 break;
2534 }
2535
2536 if (phy_data & MII_ATLX_PSSR_DPLX)
2537 *duplex = FULL_DUPLEX;
2538 else
2539 *duplex = HALF_DUPLEX;
2540
2541 return 0;
2542}
2543
2544/*
2545 * Reads the value from a PHY register
2546 * hw - Struct containing variables accessed by shared code
2547 * reg_addr - address of the PHY register to read
2548 */
2549static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data)
2550{
2551 u32 val;
2552 int i;
2553
2554 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
2555 MDIO_START |
2556 MDIO_SUP_PREAMBLE |
2557 MDIO_RW |
2558 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2559 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2560
2561 wmb();
2562
2563 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2564 udelay(2);
2565 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2566 if (!(val & (MDIO_START | MDIO_BUSY)))
2567 break;
2568 wmb();
2569 }
2570 if (!(val & (MDIO_START | MDIO_BUSY))) {
2571 *phy_data = (u16)val;
2572 return 0;
2573 }
2574
2575 return ATLX_ERR_PHY;
2576}
2577
2578/*
2579 * Writes a value to a PHY register
2580 * hw - Struct containing variables accessed by shared code
2581 * reg_addr - address of the PHY register to write
2582 * data - data to write to the PHY
2583 */
2584static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data)
2585{
2586 int i;
2587 u32 val;
2588
2589 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
2590 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
2591 MDIO_SUP_PREAMBLE |
2592 MDIO_START |
2593 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
2594 ATL2_WRITE_REG(hw, REG_MDIO_CTRL, val);
2595
2596 wmb();
2597
2598 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
2599 udelay(2);
2600 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2601 if (!(val & (MDIO_START | MDIO_BUSY)))
2602 break;
2603
2604 wmb();
2605 }
2606
2607 if (!(val & (MDIO_START | MDIO_BUSY)))
2608 return 0;
2609
2610 return ATLX_ERR_PHY;
2611}
2612
2613/*
2614 * Configures PHY autoneg and flow control advertisement settings
2615 *
2616 * hw - Struct containing variables accessed by shared code
2617 */
2618static s32 atl2_phy_setup_autoneg_adv(struct atl2_hw *hw)
2619{
2620 s32 ret_val;
2621 s16 mii_autoneg_adv_reg;
2622
2623 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
2624 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
2625
2626 /* Need to parse autoneg_advertised and set up
2627 * the appropriate PHY registers. First we will parse for
2628 * autoneg_advertised software override. Since we can advertise
2629 * a plethora of combinations, we need to check each bit
2630 * individually.
2631 */
2632
2633 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
2634 * Advertisement Register (Address 4) and the 1000 mb speed bits in
2635 * the 1000Base-T Control Register (Address 9). */
2636 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
2637
2638 /* Need to parse MediaType and setup the
2639 * appropriate PHY registers. */
2640 switch (hw->MediaType) {
2641 case MEDIA_TYPE_AUTO_SENSOR:
2642 mii_autoneg_adv_reg |=
2643 (MII_AR_10T_HD_CAPS |
2644 MII_AR_10T_FD_CAPS |
2645 MII_AR_100TX_HD_CAPS|
2646 MII_AR_100TX_FD_CAPS);
2647 hw->autoneg_advertised =
2648 ADVERTISE_10_HALF |
2649 ADVERTISE_10_FULL |
2650 ADVERTISE_100_HALF|
2651 ADVERTISE_100_FULL;
2652 break;
2653 case MEDIA_TYPE_100M_FULL:
2654 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
2655 hw->autoneg_advertised = ADVERTISE_100_FULL;
2656 break;
2657 case MEDIA_TYPE_100M_HALF:
2658 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
2659 hw->autoneg_advertised = ADVERTISE_100_HALF;
2660 break;
2661 case MEDIA_TYPE_10M_FULL:
2662 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
2663 hw->autoneg_advertised = ADVERTISE_10_FULL;
2664 break;
2665 default:
2666 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
2667 hw->autoneg_advertised = ADVERTISE_10_HALF;
2668 break;
2669 }
2670
2671 /* flow control fixed to enable all */
2672 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
2673
2674 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
2675
2676 ret_val = atl2_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
2677
2678 if (ret_val)
2679 return ret_val;
2680
2681 return 0;
2682}
2683
2684/*
2685 * Resets the PHY and make all config validate
2686 *
2687 * hw - Struct containing variables accessed by shared code
2688 *
2689 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
2690 */
2691static s32 atl2_phy_commit(struct atl2_hw *hw)
2692{
2693 s32 ret_val;
2694 u16 phy_data;
2695
2696 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2697 ret_val = atl2_write_phy_reg(hw, MII_BMCR, phy_data);
2698 if (ret_val) {
2699 u32 val;
2700 int i;
2701 /* pcie serdes link may be down ! */
2702 for (i = 0; i < 25; i++) {
2703 msleep(1);
2704 val = ATL2_READ_REG(hw, REG_MDIO_CTRL);
2705 if (!(val & (MDIO_START | MDIO_BUSY)))
2706 break;
2707 }
2708
2709 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
2710 printk(KERN_ERR "atl2: PCIe link down for at least 25ms !\n");
2711 return ret_val;
2712 }
2713 }
2714 return 0;
2715}
2716
2717static s32 atl2_phy_init(struct atl2_hw *hw)
2718{
2719 s32 ret_val;
2720 u16 phy_val;
2721
2722 if (hw->phy_configured)
2723 return 0;
2724
2725 /* Enable PHY */
2726 ATL2_WRITE_REGW(hw, REG_PHY_ENABLE, 1);
2727 ATL2_WRITE_FLUSH(hw);
2728 msleep(1);
2729
2730 /* check if the PHY is in powersaving mode */
2731 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2732 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2733
2734 /* 024E / 124E 0r 0274 / 1274 ? */
2735 if (phy_val & 0x1000) {
2736 phy_val &= ~0x1000;
2737 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val);
2738 }
2739
2740 msleep(1);
2741
2742 /*Enable PHY LinkChange Interrupt */
2743 ret_val = atl2_write_phy_reg(hw, 18, 0xC00);
2744 if (ret_val)
2745 return ret_val;
2746
2747 /* setup AutoNeg parameters */
2748 ret_val = atl2_phy_setup_autoneg_adv(hw);
2749 if (ret_val)
2750 return ret_val;
2751
2752 /* SW.Reset & En-Auto-Neg to restart Auto-Neg */
2753 ret_val = atl2_phy_commit(hw);
2754 if (ret_val)
2755 return ret_val;
2756
2757 hw->phy_configured = true;
2758
2759 return ret_val;
2760}
2761
2762static void atl2_set_mac_addr(struct atl2_hw *hw)
2763{
2764 u32 value;
2765 /* 00-0B-6A-F6-00-DC
2766 * 0: 6AF600DC 1: 000B
2767 * low dword */
2768 value = (((u32)hw->mac_addr[2]) << 24) |
2769 (((u32)hw->mac_addr[3]) << 16) |
2770 (((u32)hw->mac_addr[4]) << 8) |
2771 (((u32)hw->mac_addr[5]));
2772 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
2773 /* hight dword */
2774 value = (((u32)hw->mac_addr[0]) << 8) |
2775 (((u32)hw->mac_addr[1]));
2776 ATL2_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
2777}
2778
2779/*
2780 * check_eeprom_exist
2781 * return 0 if eeprom exist
2782 */
2783static int atl2_check_eeprom_exist(struct atl2_hw *hw)
2784{
2785 u32 value;
2786
2787 value = ATL2_READ_REG(hw, REG_SPI_FLASH_CTRL);
2788 if (value & SPI_FLASH_CTRL_EN_VPD) {
2789 value &= ~SPI_FLASH_CTRL_EN_VPD;
2790 ATL2_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
2791 }
2792 value = ATL2_READ_REGW(hw, REG_PCIE_CAP_LIST);
2793 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
2794}
2795
2796/* FIXME: This doesn't look right. -- CHS */
2797static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value)
2798{
2799 return true;
2800}
2801
2802static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue)
2803{
2804 int i;
2805 u32 Control;
2806
2807 if (Offset & 0x3)
2808 return false; /* address do not align */
2809
2810 ATL2_WRITE_REG(hw, REG_VPD_DATA, 0);
2811 Control = (Offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
2812 ATL2_WRITE_REG(hw, REG_VPD_CAP, Control);
2813
2814 for (i = 0; i < 10; i++) {
2815 msleep(2);
2816 Control = ATL2_READ_REG(hw, REG_VPD_CAP);
2817 if (Control & VPD_CAP_VPD_FLAG)
2818 break;
2819 }
2820
2821 if (Control & VPD_CAP_VPD_FLAG) {
2822 *pValue = ATL2_READ_REG(hw, REG_VPD_DATA);
2823 return true;
2824 }
2825 return false; /* timeout */
2826}
2827
2828static void atl2_force_ps(struct atl2_hw *hw)
2829{
2830 u16 phy_val;
2831
2832 atl2_write_phy_reg(hw, MII_DBG_ADDR, 0);
2833 atl2_read_phy_reg(hw, MII_DBG_DATA, &phy_val);
2834 atl2_write_phy_reg(hw, MII_DBG_DATA, phy_val | 0x1000);
2835
2836 atl2_write_phy_reg(hw, MII_DBG_ADDR, 2);
2837 atl2_write_phy_reg(hw, MII_DBG_DATA, 0x3000);
2838 atl2_write_phy_reg(hw, MII_DBG_ADDR, 3);
2839 atl2_write_phy_reg(hw, MII_DBG_DATA, 0);
2840}
2841
2842/* This is the only thing that needs to be changed to adjust the
2843 * maximum number of ports that the driver can manage.
2844 */
2845#define ATL2_MAX_NIC 4
2846
2847#define OPTION_UNSET -1
2848#define OPTION_DISABLED 0
2849#define OPTION_ENABLED 1
2850
2851/* All parameters are treated the same, as an integer array of values.
2852 * This macro just reduces the need to repeat the same declaration code
2853 * over and over (plus this helps to avoid typo bugs).
2854 */
2855#define ATL2_PARAM_INIT {[0 ... ATL2_MAX_NIC] = OPTION_UNSET}
2856#ifndef module_param_array
2857/* Module Parameters are always initialized to -1, so that the driver
2858 * can tell the difference between no user specified value or the
2859 * user asking for the default value.
2860 * The true default values are loaded in when atl2_check_options is called.
2861 *
2862 * This is a GCC extension to ANSI C.
2863 * See the item "Labeled Elements in Initializers" in the section
2864 * "Extensions to the C Language Family" of the GCC documentation.
2865 */
2866
2867#define ATL2_PARAM(X, desc) \
2868 static const int __devinitdata X[ATL2_MAX_NIC + 1] = ATL2_PARAM_INIT; \
2869 MODULE_PARM(X, "1-" __MODULE_STRING(ATL2_MAX_NIC) "i"); \
2870 MODULE_PARM_DESC(X, desc);
2871#else
2872#define ATL2_PARAM(X, desc) \
2873 static int __devinitdata X[ATL2_MAX_NIC+1] = ATL2_PARAM_INIT; \
2874 static int num_##X = 0; \
2875 module_param_array_named(X, X, int, &num_##X, 0); \
2876 MODULE_PARM_DESC(X, desc);
2877#endif
2878
2879/*
2880 * Transmit Memory Size
2881 * Valid Range: 64-2048
2882 * Default Value: 128
2883 */
2884#define ATL2_MIN_TX_MEMSIZE 4 /* 4KB */
2885#define ATL2_MAX_TX_MEMSIZE 64 /* 64KB */
2886#define ATL2_DEFAULT_TX_MEMSIZE 8 /* 8KB */
2887ATL2_PARAM(TxMemSize, "Bytes of Transmit Memory");
2888
2889/*
2890 * Receive Memory Block Count
2891 * Valid Range: 16-512
2892 * Default Value: 128
2893 */
2894#define ATL2_MIN_RXD_COUNT 16
2895#define ATL2_MAX_RXD_COUNT 512
2896#define ATL2_DEFAULT_RXD_COUNT 64
2897ATL2_PARAM(RxMemBlock, "Number of receive memory block");
2898
2899/*
2900 * User Specified MediaType Override
2901 *
2902 * Valid Range: 0-5
2903 * - 0 - auto-negotiate at all supported speeds
2904 * - 1 - only link at 1000Mbps Full Duplex
2905 * - 2 - only link at 100Mbps Full Duplex
2906 * - 3 - only link at 100Mbps Half Duplex
2907 * - 4 - only link at 10Mbps Full Duplex
2908 * - 5 - only link at 10Mbps Half Duplex
2909 * Default Value: 0
2910 */
2911ATL2_PARAM(MediaType, "MediaType Select");
2912
2913/*
2914 * Interrupt Moderate Timer in units of 2048 ns (~2 us)
2915 * Valid Range: 10-65535
2916 * Default Value: 45000(90ms)
2917 */
2918#define INT_MOD_DEFAULT_CNT 100 /* 200us */
2919#define INT_MOD_MAX_CNT 65000
2920#define INT_MOD_MIN_CNT 50
2921ATL2_PARAM(IntModTimer, "Interrupt Moderator Timer");
2922
2923/*
2924 * FlashVendor
2925 * Valid Range: 0-2
2926 * 0 - Atmel
2927 * 1 - SST
2928 * 2 - ST
2929 */
2930ATL2_PARAM(FlashVendor, "SPI Flash Vendor");
2931
2932#define AUTONEG_ADV_DEFAULT 0x2F
2933#define AUTONEG_ADV_MASK 0x2F
2934#define FLOW_CONTROL_DEFAULT FLOW_CONTROL_FULL
2935
2936#define FLASH_VENDOR_DEFAULT 0
2937#define FLASH_VENDOR_MIN 0
2938#define FLASH_VENDOR_MAX 2
2939
2940struct atl2_option {
2941 enum { enable_option, range_option, list_option } type;
2942 char *name;
2943 char *err;
2944 int def;
2945 union {
2946 struct { /* range_option info */
2947 int min;
2948 int max;
2949 } r;
2950 struct { /* list_option info */
2951 int nr;
2952 struct atl2_opt_list { int i; char *str; } *p;
2953 } l;
2954 } arg;
2955};
2956
2957static int __devinit atl2_validate_option(int *value, struct atl2_option *opt)
2958{
2959 int i;
2960 struct atl2_opt_list *ent;
2961
2962 if (*value == OPTION_UNSET) {
2963 *value = opt->def;
2964 return 0;
2965 }
2966
2967 switch (opt->type) {
2968 case enable_option:
2969 switch (*value) {
2970 case OPTION_ENABLED:
2971 printk(KERN_INFO "%s Enabled\n", opt->name);
2972 return 0;
2973 break;
2974 case OPTION_DISABLED:
2975 printk(KERN_INFO "%s Disabled\n", opt->name);
2976 return 0;
2977 break;
2978 }
2979 break;
2980 case range_option:
2981 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
2982 printk(KERN_INFO "%s set to %i\n", opt->name, *value);
2983 return 0;
2984 }
2985 break;
2986 case list_option:
2987 for (i = 0; i < opt->arg.l.nr; i++) {
2988 ent = &opt->arg.l.p[i];
2989 if (*value == ent->i) {
2990 if (ent->str[0] != '\0')
2991 printk(KERN_INFO "%s\n", ent->str);
2992 return 0;
2993 }
2994 }
2995 break;
2996 default:
2997 BUG();
2998 }
2999
3000 printk(KERN_INFO "Invalid %s specified (%i) %s\n",
3001 opt->name, *value, opt->err);
3002 *value = opt->def;
3003 return -1;
3004}
3005
3006/*
3007 * atl2_check_options - Range Checking for Command Line Parameters
3008 * @adapter: board private structure
3009 *
3010 * This routine checks all command line parameters for valid user
3011 * input. If an invalid value is given, or if no user specified
3012 * value exists, a default value is used. The final value is stored
3013 * in a variable in the adapter structure.
3014 */
3015static void __devinit atl2_check_options(struct atl2_adapter *adapter)
3016{
3017 int val;
3018 struct atl2_option opt;
3019 int bd = adapter->bd_number;
3020 if (bd >= ATL2_MAX_NIC) {
3021 printk(KERN_NOTICE "Warning: no configuration for board #%i\n",
3022 bd);
3023 printk(KERN_NOTICE "Using defaults for all values\n");
3024#ifndef module_param_array
3025 bd = ATL2_MAX_NIC;
3026#endif
3027 }
3028
3029 /* Bytes of Transmit Memory */
3030 opt.type = range_option;
3031 opt.name = "Bytes of Transmit Memory";
3032 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_TX_MEMSIZE);
3033 opt.def = ATL2_DEFAULT_TX_MEMSIZE;
3034 opt.arg.r.min = ATL2_MIN_TX_MEMSIZE;
3035 opt.arg.r.max = ATL2_MAX_TX_MEMSIZE;
3036#ifdef module_param_array
3037 if (num_TxMemSize > bd) {
3038#endif
3039 val = TxMemSize[bd];
3040 atl2_validate_option(&val, &opt);
3041 adapter->txd_ring_size = ((u32) val) * 1024;
3042#ifdef module_param_array
3043 } else
3044 adapter->txd_ring_size = ((u32)opt.def) * 1024;
3045#endif
3046 /* txs ring size: */
3047 adapter->txs_ring_size = adapter->txd_ring_size / 128;
3048 if (adapter->txs_ring_size > 160)
3049 adapter->txs_ring_size = 160;
3050
3051 /* Receive Memory Block Count */
3052 opt.type = range_option;
3053 opt.name = "Number of receive memory block";
3054 opt.err = "using default of " __MODULE_STRING(ATL2_DEFAULT_RXD_COUNT);
3055 opt.def = ATL2_DEFAULT_RXD_COUNT;
3056 opt.arg.r.min = ATL2_MIN_RXD_COUNT;
3057 opt.arg.r.max = ATL2_MAX_RXD_COUNT;
3058#ifdef module_param_array
3059 if (num_RxMemBlock > bd) {
3060#endif
3061 val = RxMemBlock[bd];
3062 atl2_validate_option(&val, &opt);
3063 adapter->rxd_ring_size = (u32)val;
3064 /* FIXME */
3065 /* ((u16)val)&~1; */ /* even number */
3066#ifdef module_param_array
3067 } else
3068 adapter->rxd_ring_size = (u32)opt.def;
3069#endif
3070 /* init RXD Flow control value */
3071 adapter->hw.fc_rxd_hi = (adapter->rxd_ring_size / 8) * 7;
3072 adapter->hw.fc_rxd_lo = (ATL2_MIN_RXD_COUNT / 8) >
3073 (adapter->rxd_ring_size / 12) ? (ATL2_MIN_RXD_COUNT / 8) :
3074 (adapter->rxd_ring_size / 12);
3075
3076 /* Interrupt Moderate Timer */
3077 opt.type = range_option;
3078 opt.name = "Interrupt Moderate Timer";
3079 opt.err = "using default of " __MODULE_STRING(INT_MOD_DEFAULT_CNT);
3080 opt.def = INT_MOD_DEFAULT_CNT;
3081 opt.arg.r.min = INT_MOD_MIN_CNT;
3082 opt.arg.r.max = INT_MOD_MAX_CNT;
3083#ifdef module_param_array
3084 if (num_IntModTimer > bd) {
3085#endif
3086 val = IntModTimer[bd];
3087 atl2_validate_option(&val, &opt);
3088 adapter->imt = (u16) val;
3089#ifdef module_param_array
3090 } else
3091 adapter->imt = (u16)(opt.def);
3092#endif
3093 /* Flash Vendor */
3094 opt.type = range_option;
3095 opt.name = "SPI Flash Vendor";
3096 opt.err = "using default of " __MODULE_STRING(FLASH_VENDOR_DEFAULT);
3097 opt.def = FLASH_VENDOR_DEFAULT;
3098 opt.arg.r.min = FLASH_VENDOR_MIN;
3099 opt.arg.r.max = FLASH_VENDOR_MAX;
3100#ifdef module_param_array
3101 if (num_FlashVendor > bd) {
3102#endif
3103 val = FlashVendor[bd];
3104 atl2_validate_option(&val, &opt);
3105 adapter->hw.flash_vendor = (u8) val;
3106#ifdef module_param_array
3107 } else
3108 adapter->hw.flash_vendor = (u8)(opt.def);
3109#endif
3110 /* MediaType */
3111 opt.type = range_option;
3112 opt.name = "Speed/Duplex Selection";
3113 opt.err = "using default of " __MODULE_STRING(MEDIA_TYPE_AUTO_SENSOR);
3114 opt.def = MEDIA_TYPE_AUTO_SENSOR;
3115 opt.arg.r.min = MEDIA_TYPE_AUTO_SENSOR;
3116 opt.arg.r.max = MEDIA_TYPE_10M_HALF;
3117#ifdef module_param_array
3118 if (num_MediaType > bd) {
3119#endif
3120 val = MediaType[bd];
3121 atl2_validate_option(&val, &opt);
3122 adapter->hw.MediaType = (u16) val;
3123#ifdef module_param_array
3124 } else
3125 adapter->hw.MediaType = (u16)(opt.def);
3126#endif
3127}
diff --git a/drivers/net/atlx/atl2.h b/drivers/net/atlx/atl2.h
new file mode 100644
index 000000000000..6e1f28ff227b
--- /dev/null
+++ b/drivers/net/atlx/atl2.h
@@ -0,0 +1,530 @@
1/* atl2.h -- atl2 driver definitions
2 *
3 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
4 * Copyright(c) 2006 xiong huang <xiong.huang@atheros.com>
5 * Copyright(c) 2007 Chris Snook <csnook@redhat.com>
6 *
7 * Derived from Intel e1000 driver
8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the Free
12 * Software Foundation; either version 2 of the License, or (at your option)
13 * any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * more details.
19 *
20 * You should have received a copy of the GNU General Public License along with
21 * this program; if not, write to the Free Software Foundation, Inc., 59
22 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 */
24
25#ifndef _ATL2_H_
26#define _ATL2_H_
27
28#include <asm/atomic.h>
29#include <linux/netdevice.h>
30
31#ifndef _ATL2_HW_H_
32#define _ATL2_HW_H_
33
34#ifndef _ATL2_OSDEP_H_
35#define _ATL2_OSDEP_H_
36
37#include <linux/pci.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/if_ether.h>
41
42#include "atlx.h"
43
44#ifdef ETHTOOL_OPS_COMPAT
45extern int ethtool_ioctl(struct ifreq *ifr);
46#endif
47
48#define PCI_COMMAND_REGISTER PCI_COMMAND
49#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
50#define ETH_ADDR_LEN ETH_ALEN
51
52#define ATL2_WRITE_REG(a, reg, value) (iowrite32((value), \
53 ((a)->hw_addr + (reg))))
54
55#define ATL2_WRITE_FLUSH(a) (ioread32((a)->hw_addr))
56
57#define ATL2_READ_REG(a, reg) (ioread32((a)->hw_addr + (reg)))
58
59#define ATL2_WRITE_REGB(a, reg, value) (iowrite8((value), \
60 ((a)->hw_addr + (reg))))
61
62#define ATL2_READ_REGB(a, reg) (ioread8((a)->hw_addr + (reg)))
63
64#define ATL2_WRITE_REGW(a, reg, value) (iowrite16((value), \
65 ((a)->hw_addr + (reg))))
66
67#define ATL2_READ_REGW(a, reg) (ioread16((a)->hw_addr + (reg)))
68
69#define ATL2_WRITE_REG_ARRAY(a, reg, offset, value) \
70 (iowrite32((value), (((a)->hw_addr + (reg)) + ((offset) << 2))))
71
72#define ATL2_READ_REG_ARRAY(a, reg, offset) \
73 (ioread32(((a)->hw_addr + (reg)) + ((offset) << 2)))
74
75#endif /* _ATL2_OSDEP_H_ */
76
77struct atl2_adapter;
78struct atl2_hw;
79
80/* function prototype */
81static s32 atl2_reset_hw(struct atl2_hw *hw);
82static s32 atl2_read_mac_addr(struct atl2_hw *hw);
83static s32 atl2_init_hw(struct atl2_hw *hw);
84static s32 atl2_get_speed_and_duplex(struct atl2_hw *hw, u16 *speed,
85 u16 *duplex);
86static u32 atl2_hash_mc_addr(struct atl2_hw *hw, u8 *mc_addr);
87static void atl2_hash_set(struct atl2_hw *hw, u32 hash_value);
88static s32 atl2_read_phy_reg(struct atl2_hw *hw, u16 reg_addr, u16 *phy_data);
89static s32 atl2_write_phy_reg(struct atl2_hw *hw, u32 reg_addr, u16 phy_data);
90static void atl2_read_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
91static void atl2_write_pci_cfg(struct atl2_hw *hw, u32 reg, u16 *value);
92static void atl2_set_mac_addr(struct atl2_hw *hw);
93static bool atl2_read_eeprom(struct atl2_hw *hw, u32 Offset, u32 *pValue);
94static bool atl2_write_eeprom(struct atl2_hw *hw, u32 offset, u32 value);
95static s32 atl2_phy_init(struct atl2_hw *hw);
96static int atl2_check_eeprom_exist(struct atl2_hw *hw);
97static void atl2_force_ps(struct atl2_hw *hw);
98
99/* register definition */
100
101/* Block IDLE Status Register */
102#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC is non-IDLE */
103#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC is non-IDLE */
104#define IDLE_STATUS_DMAR 8 /* 1: DMAR is non-IDLE */
105#define IDLE_STATUS_DMAW 4 /* 1: DMAW is non-IDLE */
106
107/* MDIO Control Register */
108#define MDIO_WAIT_TIMES 10
109
110/* MAC Control Register */
111#define MAC_CTRL_DBG_TX_BKPRESURE 0x100000 /* 1: TX max backoff */
112#define MAC_CTRL_MACLP_CLK_PHY 0x8000000 /* 1: 25MHz from phy */
113#define MAC_CTRL_HALF_LEFT_BUF_SHIFT 28
114#define MAC_CTRL_HALF_LEFT_BUF_MASK 0xF /* MAC retry buf x32B */
115
116/* Internal SRAM Partition Register */
117#define REG_SRAM_TXRAM_END 0x1500 /* Internal tail address of TXRAM
118 * default: 2byte*1024 */
119#define REG_SRAM_RXRAM_END 0x1502 /* Internal tail address of RXRAM
120 * default: 2byte*1024 */
121
122/* Descriptor Control register */
123#define REG_TXD_BASE_ADDR_LO 0x1544 /* The base address of the Transmit
124 * Data Mem low 32-bit(dword align) */
125#define REG_TXD_MEM_SIZE 0x1548 /* Transmit Data Memory size(by
126 * double word , max 256KB) */
127#define REG_TXS_BASE_ADDR_LO 0x154C /* The base address of the Transmit
128 * Status Memory low 32-bit(dword word
129 * align) */
130#define REG_TXS_MEM_SIZE 0x1550 /* double word unit, max 4*2047
131 * bytes. */
132#define REG_RXD_BASE_ADDR_LO 0x1554 /* The base address of the Transmit
133 * Status Memory low 32-bit(unit 8
134 * bytes) */
135#define REG_RXD_BUF_NUM 0x1558 /* Receive Data & Status Memory buffer
136 * number (unit 1536bytes, max
137 * 1536*2047) */
138
139/* DMAR Control Register */
140#define REG_DMAR 0x1580
141#define DMAR_EN 0x1 /* 1: Enable DMAR */
142
143/* TX Cur-Through (early tx threshold) Control Register */
144#define REG_TX_CUT_THRESH 0x1590 /* TxMac begin transmit packet
145 * threshold(unit word) */
146
147/* DMAW Control Register */
148#define REG_DMAW 0x15A0
149#define DMAW_EN 0x1
150
151/* Flow control register */
152#define REG_PAUSE_ON_TH 0x15A8 /* RXD high watermark of overflow
153 * threshold configuration register */
154#define REG_PAUSE_OFF_TH 0x15AA /* RXD lower watermark of overflow
155 * threshold configuration register */
156
157/* Mailbox Register */
158#define REG_MB_TXD_WR_IDX 0x15f0 /* double word align */
159#define REG_MB_RXD_RD_IDX 0x15F4 /* RXD Read index (unit: 1536byets) */
160
161/* Interrupt Status Register */
162#define ISR_TIMER 1 /* Interrupt when Timer counts down to zero */
163#define ISR_MANUAL 2 /* Software manual interrupt, for debug. Set
164 * when SW_MAN_INT_EN is set in Table 51
165 * Selene Master Control Register
166 * (Offset 0x1400). */
167#define ISR_RXF_OV 4 /* RXF overflow interrupt */
168#define ISR_TXF_UR 8 /* TXF underrun interrupt */
169#define ISR_TXS_OV 0x10 /* Internal transmit status buffer full
170 * interrupt */
171#define ISR_RXS_OV 0x20 /* Internal receive status buffer full
172 * interrupt */
173#define ISR_LINK_CHG 0x40 /* Link Status Change Interrupt */
174#define ISR_HOST_TXD_UR 0x80
175#define ISR_HOST_RXD_OV 0x100 /* Host rx data memory full , one pulse */
176#define ISR_DMAR_TO_RST 0x200 /* DMAR op timeout interrupt. SW should
177 * do Reset */
178#define ISR_DMAW_TO_RST 0x400
179#define ISR_PHY 0x800 /* phy interrupt */
180#define ISR_TS_UPDATE 0x10000 /* interrupt after new tx pkt status written
181 * to host */
182#define ISR_RS_UPDATE 0x20000 /* interrupt ater new rx pkt status written
183 * to host. */
184#define ISR_TX_EARLY 0x40000 /* interrupt when txmac begin transmit one
185 * packet */
186
187#define ISR_TX_EVENT (ISR_TXF_UR | ISR_TXS_OV | ISR_HOST_TXD_UR |\
188 ISR_TS_UPDATE | ISR_TX_EARLY)
189#define ISR_RX_EVENT (ISR_RXF_OV | ISR_RXS_OV | ISR_HOST_RXD_OV |\
190 ISR_RS_UPDATE)
191
192#define IMR_NORMAL_MASK (\
193 /*ISR_LINK_CHG |*/\
194 ISR_MANUAL |\
195 ISR_DMAR_TO_RST |\
196 ISR_DMAW_TO_RST |\
197 ISR_PHY |\
198 ISR_PHY_LINKDOWN |\
199 ISR_TS_UPDATE |\
200 ISR_RS_UPDATE)
201
202/* Receive MAC Statistics Registers */
203#define REG_STS_RX_PAUSE 0x1700 /* Num pause packets received */
204#define REG_STS_RXD_OV 0x1704 /* Num frames dropped due to RX
205 * FIFO overflow */
206#define REG_STS_RXS_OV 0x1708 /* Num frames dropped due to RX
207 * Status Buffer Overflow */
208#define REG_STS_RX_FILTER 0x170C /* Num packets dropped due to
209 * address filtering */
210
211/* MII definitions */
212
213/* PHY Common Register */
214#define MII_SMARTSPEED 0x14
215#define MII_DBG_ADDR 0x1D
216#define MII_DBG_DATA 0x1E
217
218/* PCI Command Register Bit Definitions */
219#define PCI_REG_COMMAND 0x04
220#define CMD_IO_SPACE 0x0001
221#define CMD_MEMORY_SPACE 0x0002
222#define CMD_BUS_MASTER 0x0004
223
224#define MEDIA_TYPE_100M_FULL 1
225#define MEDIA_TYPE_100M_HALF 2
226#define MEDIA_TYPE_10M_FULL 3
227#define MEDIA_TYPE_10M_HALF 4
228
229#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x000F /* Everything */
230
231/* The size (in bytes) of a ethernet packet */
232#define ENET_HEADER_SIZE 14
233#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* with FCS */
234#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* with FCS */
235#define ETHERNET_FCS_SIZE 4
236#define MAX_JUMBO_FRAME_SIZE 0x2000
237#define VLAN_SIZE 4
238
239struct tx_pkt_header {
240 unsigned pkt_size:11;
241 unsigned:4; /* reserved */
242 unsigned ins_vlan:1; /* txmac should insert vlan */
243 unsigned short vlan; /* vlan tag */
244};
245/* FIXME: replace above bitfields with MASK/SHIFT defines below */
246#define TX_PKT_HEADER_SIZE_MASK 0x7FF
247#define TX_PKT_HEADER_SIZE_SHIFT 0
248#define TX_PKT_HEADER_INS_VLAN_MASK 0x1
249#define TX_PKT_HEADER_INS_VLAN_SHIFT 15
250#define TX_PKT_HEADER_VLAN_TAG_MASK 0xFFFF
251#define TX_PKT_HEADER_VLAN_TAG_SHIFT 16
252
253struct tx_pkt_status {
254 unsigned pkt_size:11;
255 unsigned:5; /* reserved */
256 unsigned ok:1; /* current packet transmitted without error */
257 unsigned bcast:1; /* broadcast packet */
258 unsigned mcast:1; /* multicast packet */
259 unsigned pause:1; /* transmiited a pause frame */
260 unsigned ctrl:1;
261 unsigned defer:1; /* current packet is xmitted with defer */
262 unsigned exc_defer:1;
263 unsigned single_col:1;
264 unsigned multi_col:1;
265 unsigned late_col:1;
266 unsigned abort_col:1;
267 unsigned underun:1; /* current packet is aborted
268 * due to txram underrun */
269 unsigned:3; /* reserved */
270 unsigned update:1; /* always 1'b1 in tx_status_buf */
271};
272/* FIXME: replace above bitfields with MASK/SHIFT defines below */
273#define TX_PKT_STATUS_SIZE_MASK 0x7FF
274#define TX_PKT_STATUS_SIZE_SHIFT 0
275#define TX_PKT_STATUS_OK_MASK 0x1
276#define TX_PKT_STATUS_OK_SHIFT 16
277#define TX_PKT_STATUS_BCAST_MASK 0x1
278#define TX_PKT_STATUS_BCAST_SHIFT 17
279#define TX_PKT_STATUS_MCAST_MASK 0x1
280#define TX_PKT_STATUS_MCAST_SHIFT 18
281#define TX_PKT_STATUS_PAUSE_MASK 0x1
282#define TX_PKT_STATUS_PAUSE_SHIFT 19
283#define TX_PKT_STATUS_CTRL_MASK 0x1
284#define TX_PKT_STATUS_CTRL_SHIFT 20
285#define TX_PKT_STATUS_DEFER_MASK 0x1
286#define TX_PKT_STATUS_DEFER_SHIFT 21
287#define TX_PKT_STATUS_EXC_DEFER_MASK 0x1
288#define TX_PKT_STATUS_EXC_DEFER_SHIFT 22
289#define TX_PKT_STATUS_SINGLE_COL_MASK 0x1
290#define TX_PKT_STATUS_SINGLE_COL_SHIFT 23
291#define TX_PKT_STATUS_MULTI_COL_MASK 0x1
292#define TX_PKT_STATUS_MULTI_COL_SHIFT 24
293#define TX_PKT_STATUS_LATE_COL_MASK 0x1
294#define TX_PKT_STATUS_LATE_COL_SHIFT 25
295#define TX_PKT_STATUS_ABORT_COL_MASK 0x1
296#define TX_PKT_STATUS_ABORT_COL_SHIFT 26
297#define TX_PKT_STATUS_UNDERRUN_MASK 0x1
298#define TX_PKT_STATUS_UNDERRUN_SHIFT 27
299#define TX_PKT_STATUS_UPDATE_MASK 0x1
300#define TX_PKT_STATUS_UPDATE_SHIFT 31
301
302struct rx_pkt_status {
303 unsigned pkt_size:11; /* packet size, max 2047 bytes */
304 unsigned:5; /* reserved */
305 unsigned ok:1; /* current packet received ok without error */
306 unsigned bcast:1; /* current packet is broadcast */
307 unsigned mcast:1; /* current packet is multicast */
308 unsigned pause:1;
309 unsigned ctrl:1;
310 unsigned crc:1; /* received a packet with crc error */
311 unsigned code:1; /* received a packet with code error */
312 unsigned runt:1; /* received a packet less than 64 bytes
313 * with good crc */
314 unsigned frag:1; /* received a packet less than 64 bytes
315 * with bad crc */
316 unsigned trunc:1; /* current frame truncated due to rxram full */
317 unsigned align:1; /* this packet is alignment error */
318 unsigned vlan:1; /* this packet has vlan */
319 unsigned:3; /* reserved */
320 unsigned update:1;
321 unsigned short vtag; /* vlan tag */
322 unsigned:16;
323};
324/* FIXME: replace above bitfields with MASK/SHIFT defines below */
325#define RX_PKT_STATUS_SIZE_MASK 0x7FF
326#define RX_PKT_STATUS_SIZE_SHIFT 0
327#define RX_PKT_STATUS_OK_MASK 0x1
328#define RX_PKT_STATUS_OK_SHIFT 16
329#define RX_PKT_STATUS_BCAST_MASK 0x1
330#define RX_PKT_STATUS_BCAST_SHIFT 17
331#define RX_PKT_STATUS_MCAST_MASK 0x1
332#define RX_PKT_STATUS_MCAST_SHIFT 18
333#define RX_PKT_STATUS_PAUSE_MASK 0x1
334#define RX_PKT_STATUS_PAUSE_SHIFT 19
335#define RX_PKT_STATUS_CTRL_MASK 0x1
336#define RX_PKT_STATUS_CTRL_SHIFT 20
337#define RX_PKT_STATUS_CRC_MASK 0x1
338#define RX_PKT_STATUS_CRC_SHIFT 21
339#define RX_PKT_STATUS_CODE_MASK 0x1
340#define RX_PKT_STATUS_CODE_SHIFT 22
341#define RX_PKT_STATUS_RUNT_MASK 0x1
342#define RX_PKT_STATUS_RUNT_SHIFT 23
343#define RX_PKT_STATUS_FRAG_MASK 0x1
344#define RX_PKT_STATUS_FRAG_SHIFT 24
345#define RX_PKT_STATUS_TRUNK_MASK 0x1
346#define RX_PKT_STATUS_TRUNK_SHIFT 25
347#define RX_PKT_STATUS_ALIGN_MASK 0x1
348#define RX_PKT_STATUS_ALIGN_SHIFT 26
349#define RX_PKT_STATUS_VLAN_MASK 0x1
350#define RX_PKT_STATUS_VLAN_SHIFT 27
351#define RX_PKT_STATUS_UPDATE_MASK 0x1
352#define RX_PKT_STATUS_UPDATE_SHIFT 31
353#define RX_PKT_STATUS_VLAN_TAG_MASK 0xFFFF
354#define RX_PKT_STATUS_VLAN_TAG_SHIFT 32
355
356struct rx_desc {
357 struct rx_pkt_status status;
358 unsigned char packet[1536-sizeof(struct rx_pkt_status)];
359};
360
361enum atl2_speed_duplex {
362 atl2_10_half = 0,
363 atl2_10_full = 1,
364 atl2_100_half = 2,
365 atl2_100_full = 3
366};
367
368struct atl2_spi_flash_dev {
369 const char *manu_name; /* manufacturer id */
370 /* op-code */
371 u8 cmdWRSR;
372 u8 cmdREAD;
373 u8 cmdPROGRAM;
374 u8 cmdWREN;
375 u8 cmdWRDI;
376 u8 cmdRDSR;
377 u8 cmdRDID;
378 u8 cmdSECTOR_ERASE;
379 u8 cmdCHIP_ERASE;
380};
381
382/* Structure containing variables used by the shared code (atl2_hw.c) */
383struct atl2_hw {
384 u8 __iomem *hw_addr;
385 void *back;
386
387 u8 preamble_len;
388 u8 max_retry; /* Retransmission maximum, afterwards the
389 * packet will be discarded. */
390 u8 jam_ipg; /* IPG to start JAM for collision based flow
391 * control in half-duplex mode. In unit of
392 * 8-bit time. */
393 u8 ipgt; /* Desired back to back inter-packet gap. The
394 * default is 96-bit time. */
395 u8 min_ifg; /* Minimum number of IFG to enforce in between
396 * RX frames. Frame gap below such IFP is
397 * dropped. */
398 u8 ipgr1; /* 64bit Carrier-Sense window */
399 u8 ipgr2; /* 96-bit IPG window */
400 u8 retry_buf; /* When half-duplex mode, should hold some
401 * bytes for mac retry . (8*4bytes unit) */
402
403 u16 fc_rxd_hi;
404 u16 fc_rxd_lo;
405 u16 lcol; /* Collision Window */
406 u16 max_frame_size;
407
408 u16 MediaType;
409 u16 autoneg_advertised;
410 u16 pci_cmd_word;
411
412 u16 mii_autoneg_adv_reg;
413
414 u32 mem_rang;
415 u32 txcw;
416 u32 mc_filter_type;
417 u32 num_mc_addrs;
418 u32 collision_delta;
419 u32 tx_packet_delta;
420 u16 phy_spd_default;
421
422 u16 device_id;
423 u16 vendor_id;
424 u16 subsystem_id;
425 u16 subsystem_vendor_id;
426 u8 revision_id;
427
428 /* spi flash */
429 u8 flash_vendor;
430
431 u8 dma_fairness;
432 u8 mac_addr[NODE_ADDRESS_SIZE];
433 u8 perm_mac_addr[NODE_ADDRESS_SIZE];
434
435 /* FIXME */
436 /* bool phy_preamble_sup; */
437 bool phy_configured;
438};
439
440#endif /* _ATL2_HW_H_ */
441
442struct atl2_ring_header {
443 /* pointer to the descriptor ring memory */
444 void *desc;
445 /* physical adress of the descriptor ring */
446 dma_addr_t dma;
447 /* length of descriptor ring in bytes */
448 unsigned int size;
449};
450
451/* board specific private data structure */
452struct atl2_adapter {
453 /* OS defined structs */
454 struct net_device *netdev;
455 struct pci_dev *pdev;
456 struct net_device_stats net_stats;
457#ifdef NETIF_F_HW_VLAN_TX
458 struct vlan_group *vlgrp;
459#endif
460 u32 wol;
461 u16 link_speed;
462 u16 link_duplex;
463
464 spinlock_t stats_lock;
465 spinlock_t tx_lock;
466
467 struct work_struct reset_task;
468 struct work_struct link_chg_task;
469 struct timer_list watchdog_timer;
470 struct timer_list phy_config_timer;
471
472 unsigned long cfg_phy;
473 bool mac_disabled;
474
475 /* All Descriptor memory */
476 dma_addr_t ring_dma;
477 void *ring_vir_addr;
478 int ring_size;
479
480 struct tx_pkt_header *txd_ring;
481 dma_addr_t txd_dma;
482
483 struct tx_pkt_status *txs_ring;
484 dma_addr_t txs_dma;
485
486 struct rx_desc *rxd_ring;
487 dma_addr_t rxd_dma;
488
489 u32 txd_ring_size; /* bytes per unit */
490 u32 txs_ring_size; /* dwords per unit */
491 u32 rxd_ring_size; /* 1536 bytes per unit */
492
493 /* read /write ptr: */
494 /* host */
495 u32 txd_write_ptr;
496 u32 txs_next_clear;
497 u32 rxd_read_ptr;
498
499 /* nic */
500 atomic_t txd_read_ptr;
501 atomic_t txs_write_ptr;
502 u32 rxd_write_ptr;
503
504 /* Interrupt Moderator timer ( 2us resolution) */
505 u16 imt;
506 /* Interrupt Clear timer (2us resolution) */
507 u16 ict;
508
509 unsigned long flags;
510 /* structs defined in atl2_hw.h */
511 u32 bd_number; /* board number */
512 bool pci_using_64;
513 bool have_msi;
514 struct atl2_hw hw;
515
516 u32 usr_cmd;
517 /* FIXME */
518 /* u32 regs_buff[ATL2_REGS_LEN]; */
519 u32 pci_state[16];
520
521 u32 *config_space;
522};
523
524enum atl2_state_t {
525 __ATL2_TESTING,
526 __ATL2_RESETTING,
527 __ATL2_DOWN
528};
529
530#endif /* _ATL2_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 23:40:31 -0500