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-rw-r--r--drivers/net/wireless/ath9k/ahb.c4
-rw-r--r--drivers/net/wireless/ath9k/ani.c5
-rw-r--r--drivers/net/wireless/ath9k/ani.h111
-rw-r--r--drivers/net/wireless/ath9k/ath9k.h1653
-rw-r--r--drivers/net/wireless/ath9k/beacon.c2
-rw-r--r--drivers/net/wireless/ath9k/calib.c5
-rw-r--r--drivers/net/wireless/ath9k/calib.h124
-rw-r--r--drivers/net/wireless/ath9k/core.h821
-rw-r--r--drivers/net/wireless/ath9k/debug.c4
-rw-r--r--drivers/net/wireless/ath9k/debug.h153
-rw-r--r--drivers/net/wireless/ath9k/eeprom.c5
-rw-r--r--drivers/net/wireless/ath9k/eeprom.h484
-rw-r--r--drivers/net/wireless/ath9k/hw.c5
-rw-r--r--drivers/net/wireless/ath9k/hw.h1377
-rw-r--r--drivers/net/wireless/ath9k/mac.c5
-rw-r--r--drivers/net/wireless/ath9k/mac.h676
-rw-r--r--drivers/net/wireless/ath9k/main.c4
-rw-r--r--drivers/net/wireless/ath9k/pci.c4
-rw-r--r--drivers/net/wireless/ath9k/phy.c5
-rw-r--r--drivers/net/wireless/ath9k/rc.c2
-rw-r--r--drivers/net/wireless/ath9k/rc.h17
-rw-r--r--drivers/net/wireless/ath9k/recv.c2
-rw-r--r--drivers/net/wireless/ath9k/reg.h1
-rw-r--r--drivers/net/wireless/ath9k/regd.c4
-rw-r--r--drivers/net/wireless/ath9k/regd.h12
-rw-r--r--drivers/net/wireless/ath9k/xmit.c2
26 files changed, 2733 insertions, 2754 deletions
diff --git a/drivers/net/wireless/ath9k/ahb.c b/drivers/net/wireless/ath9k/ahb.c
index 7f2c3a09bcac..361ace1f2104 100644
--- a/drivers/net/wireless/ath9k/ahb.c
+++ b/drivers/net/wireless/ath9k/ahb.c
@@ -19,9 +19,7 @@
19#include <linux/nl80211.h> 19#include <linux/nl80211.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/ath9k_platform.h> 21#include <linux/ath9k_platform.h>
22#include "core.h" 22#include "ath9k.h"
23#include "reg.h"
24#include "hw.h"
25 23
26/* return bus cachesize in 4B word units */ 24/* return bus cachesize in 4B word units */
27static void ath_ahb_read_cachesize(struct ath_softc *sc, int *csz) 25static void ath_ahb_read_cachesize(struct ath_softc *sc, int *csz)
diff --git a/drivers/net/wireless/ath9k/ani.c b/drivers/net/wireless/ath9k/ani.c
index 42197fff2a47..d75bd6e5b158 100644
--- a/drivers/net/wireless/ath9k/ani.c
+++ b/drivers/net/wireless/ath9k/ani.c
@@ -14,10 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah, 19static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
23 struct ath9k_channel *chan) 20 struct ath9k_channel *chan)
diff --git a/drivers/net/wireless/ath9k/ani.h b/drivers/net/wireless/ath9k/ani.h
new file mode 100644
index 000000000000..cfb7fbc8f134
--- /dev/null
+++ b/drivers/net/wireless/ath9k/ani.h
@@ -0,0 +1,111 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ANI_H
18#define ANI_H
19
20#define HAL_PROCESS_ANI 0x00000001
21#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
22
23#define DO_ANI(ah) ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI))
24
25#define HAL_EP_RND(x, mul) \
26 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
27#define BEACON_RSSI(ahp) \
28 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
29 ATH9K_RSSI_EP_MULTIPLIER)
30
31#define ATH9K_ANI_OFDM_TRIG_HIGH 500
32#define ATH9K_ANI_OFDM_TRIG_LOW 200
33#define ATH9K_ANI_CCK_TRIG_HIGH 200
34#define ATH9K_ANI_CCK_TRIG_LOW 100
35#define ATH9K_ANI_NOISE_IMMUNE_LVL 4
36#define ATH9K_ANI_USE_OFDM_WEAK_SIG true
37#define ATH9K_ANI_CCK_WEAK_SIG_THR false
38#define ATH9K_ANI_SPUR_IMMUNE_LVL 7
39#define ATH9K_ANI_FIRSTEP_LVL 0
40#define ATH9K_ANI_RSSI_THR_HIGH 40
41#define ATH9K_ANI_RSSI_THR_LOW 7
42#define ATH9K_ANI_PERIOD 100
43
44#define HAL_NOISE_IMMUNE_MAX 4
45#define HAL_SPUR_IMMUNE_MAX 7
46#define HAL_FIRST_STEP_MAX 2
47
48enum ath9k_ani_cmd {
49 ATH9K_ANI_PRESENT = 0x1,
50 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
51 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
52 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
53 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
54 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
55 ATH9K_ANI_MODE = 0x40,
56 ATH9K_ANI_PHYERR_RESET = 0x80,
57 ATH9K_ANI_ALL = 0xff
58};
59
60struct ath9k_mib_stats {
61 u32 ackrcv_bad;
62 u32 rts_bad;
63 u32 rts_good;
64 u32 fcs_bad;
65 u32 beacons;
66};
67
68struct ath9k_node_stats {
69 u32 ns_avgbrssi;
70 u32 ns_avgrssi;
71 u32 ns_avgtxrssi;
72 u32 ns_avgtxrate;
73};
74
75struct ar5416Stats {
76 u32 ast_ani_niup;
77 u32 ast_ani_nidown;
78 u32 ast_ani_spurup;
79 u32 ast_ani_spurdown;
80 u32 ast_ani_ofdmon;
81 u32 ast_ani_ofdmoff;
82 u32 ast_ani_cckhigh;
83 u32 ast_ani_ccklow;
84 u32 ast_ani_stepup;
85 u32 ast_ani_stepdown;
86 u32 ast_ani_ofdmerrs;
87 u32 ast_ani_cckerrs;
88 u32 ast_ani_reset;
89 u32 ast_ani_lzero;
90 u32 ast_ani_lneg;
91 struct ath9k_mib_stats ast_mibstats;
92 struct ath9k_node_stats ast_nodestats;
93};
94#define ah_mibStats ah_stats.ast_mibstats
95
96void ath9k_ani_reset(struct ath_hal *ah);
97void ath9k_hw_ani_monitor(struct ath_hal *ah,
98 const struct ath9k_node_stats *stats,
99 struct ath9k_channel *chan);
100bool ath9k_hw_phycounters(struct ath_hal *ah);
101void ath9k_enable_mib_counters(struct ath_hal *ah);
102void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
103u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah, u32 *rxc_pcnt,
104 u32 *rxf_pcnt, u32 *txf_pcnt);
105void ath9k_hw_procmibevent(struct ath_hal *ah,
106 const struct ath9k_node_stats *stats);
107void ath9k_hw_ani_setup(struct ath_hal *ah);
108void ath9k_hw_ani_attach(struct ath_hal *ah);
109void ath9k_hw_ani_detach(struct ath_hal *ah);
110
111#endif /* ANI_H */
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h
index 5289d2878111..3cb7bf86410e 100644
--- a/drivers/net/wireless/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath9k/ath9k.h
@@ -17,1028 +17,683 @@
17#ifndef ATH9K_H 17#ifndef ATH9K_H
18#define ATH9K_H 18#define ATH9K_H
19 19
20#include <linux/io.h> 20#include <linux/etherdevice.h>
21 21#include <linux/device.h>
22#define ATHEROS_VENDOR_ID 0x168c 22#include <net/mac80211.h>
23 23#include <linux/leds.h>
24#define AR5416_DEVID_PCI 0x0023 24#include <linux/rfkill.h>
25#define AR5416_DEVID_PCIE 0x0024 25
26#define AR9160_DEVID_PCI 0x0027 26#include "hw.h"
27#define AR9280_DEVID_PCI 0x0029 27#include "rc.h"
28#define AR9280_DEVID_PCIE 0x002a 28#include "debug.h"
29#define AR9285_DEVID_PCIE 0x002b 29
30 30struct ath_node;
31#define AR5416_AR9100_DEVID 0x000b 31
32 32/* Macro to expand scalars to 64-bit objects */
33#define AR_SUBVENDOR_ID_NOG 0x0e11 33
34#define AR_SUBVENDOR_ID_NEW_A 0x7065 34#define ito64(x) (sizeof(x) == 8) ? \
35 35 (((unsigned long long int)(x)) & (0xff)) : \
36#define ATH9K_TXERR_XRETRY 0x01 36 (sizeof(x) == 16) ? \
37#define ATH9K_TXERR_FILT 0x02 37 (((unsigned long long int)(x)) & 0xffff) : \
38#define ATH9K_TXERR_FIFO 0x04 38 ((sizeof(x) == 32) ? \
39#define ATH9K_TXERR_XTXOP 0x08 39 (((unsigned long long int)(x)) & 0xffffffff) : \
40#define ATH9K_TXERR_TIMER_EXPIRED 0x10 40 (unsigned long long int)(x))
41 41
42#define ATH9K_TX_BA 0x01 42/* increment with wrap-around */
43#define ATH9K_TX_PWRMGMT 0x02 43#define INCR(_l, _sz) do { \
44#define ATH9K_TX_DESC_CFG_ERR 0x04 44 (_l)++; \
45#define ATH9K_TX_DATA_UNDERRUN 0x08 45 (_l) &= ((_sz) - 1); \
46#define ATH9K_TX_DELIM_UNDERRUN 0x10 46 } while (0)
47#define ATH9K_TX_SW_ABORTED 0x40 47
48#define ATH9K_TX_SW_FILTERED 0x80 48/* decrement with wrap-around */
49 49#define DECR(_l, _sz) do { \
50#define NBBY 8 50 (_l)--; \
51 51 (_l) &= ((_sz) - 1); \
52struct ath_tx_status { 52 } while (0)
53 u32 ts_tstamp; 53
54 u16 ts_seqnum; 54#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 u8 ts_status; 55
56 u8 ts_ratecode; 56#define ASSERT(exp) do { \
57 u8 ts_rateindex; 57 if (unlikely(!(exp))) { \
58 int8_t ts_rssi; 58 BUG(); \
59 u8 ts_shortretry; 59 } \
60 u8 ts_longretry; 60 } while (0)
61 u8 ts_virtcol; 61
62 u8 ts_antenna; 62#define TSF_TO_TU(_h,_l) \
63 u8 ts_flags; 63 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 int8_t ts_rssi_ctl0; 64
65 int8_t ts_rssi_ctl1; 65#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66 int8_t ts_rssi_ctl2; 66
67 int8_t ts_rssi_ext0; 67static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
68 int8_t ts_rssi_ext1; 68
69 int8_t ts_rssi_ext2; 69struct ath_config {
70 u8 pad[3]; 70 u32 ath_aggr_prot;
71 u32 ba_low; 71 u16 txpowlimit;
72 u32 ba_high; 72 u8 cabqReadytime;
73 u32 evm0; 73 u8 swBeaconProcess;
74 u32 evm1; 74};
75 u32 evm2; 75
76}; 76/*************************/
77 77/* Descriptor Management */
78struct ath_rx_status { 78/*************************/
79 u32 rs_tstamp; 79
80 u16 rs_datalen; 80#define ATH_TXBUF_RESET(_bf) do { \
81 u8 rs_status; 81 (_bf)->bf_status = 0; \
82 u8 rs_phyerr; 82 (_bf)->bf_lastbf = NULL; \
83 int8_t rs_rssi; 83 (_bf)->bf_next = NULL; \
84 u8 rs_keyix; 84 memset(&((_bf)->bf_state), 0, \
85 u8 rs_rate; 85 sizeof(struct ath_buf_state)); \
86 u8 rs_antenna; 86 } while (0)
87 u8 rs_more; 87
88 int8_t rs_rssi_ctl0; 88/**
89 int8_t rs_rssi_ctl1; 89 * enum buffer_type - Buffer type flags
90 int8_t rs_rssi_ctl2; 90 *
91 int8_t rs_rssi_ext0; 91 * @BUF_HT: Send this buffer using HT capabilities
92 int8_t rs_rssi_ext1; 92 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
93 int8_t rs_rssi_ext2; 93 * @BUF_AGGR: Indicates whether the buffer can be aggregated
94 u8 rs_isaggr; 94 * (used in aggregation scheduling)
95 u8 rs_moreaggr; 95 * @BUF_RETRY: Indicates whether the buffer is retried
96 u8 rs_num_delims; 96 * @BUF_XRETRY: To denote excessive retries of the buffer
97 u8 rs_flags; 97 */
98 u32 evm0; 98enum buffer_type {
99 u32 evm1; 99 BUF_HT = BIT(1),
100 u32 evm2; 100 BUF_AMPDU = BIT(2),
101}; 101 BUF_AGGR = BIT(3),
102 102 BUF_RETRY = BIT(4),
103#define ATH9K_RXERR_CRC 0x01 103 BUF_XRETRY = BIT(5),
104#define ATH9K_RXERR_PHY 0x02 104};
105#define ATH9K_RXERR_FIFO 0x04 105
106#define ATH9K_RXERR_DECRYPT 0x08 106struct ath_buf_state {
107#define ATH9K_RXERR_MIC 0x10 107 int bfs_nframes; /* # frames in aggregate */
108 108 u16 bfs_al; /* length of aggregate */
109#define ATH9K_RX_MORE 0x01 109 u16 bfs_frmlen; /* length of frame */
110#define ATH9K_RX_MORE_AGGR 0x02 110 int bfs_seqno; /* sequence number */
111#define ATH9K_RX_GI 0x04 111 int bfs_tidno; /* tid of this frame */
112#define ATH9K_RX_2040 0x08 112 int bfs_retries; /* current retries */
113#define ATH9K_RX_DELIM_CRC_PRE 0x10 113 u32 bf_type; /* BUF_* (enum buffer_type) */
114#define ATH9K_RX_DELIM_CRC_POST 0x20 114 u32 bfs_keyix;
115#define ATH9K_RX_DECRYPT_BUSY 0x40 115 enum ath9k_key_type bfs_keytype;
116 116};
117#define ATH9K_RXKEYIX_INVALID ((u8)-1) 117
118#define ATH9K_TXKEYIX_INVALID ((u32)-1) 118#define bf_nframes bf_state.bfs_nframes
119 119#define bf_al bf_state.bfs_al
120struct ath_desc { 120#define bf_frmlen bf_state.bfs_frmlen
121 u32 ds_link; 121#define bf_retries bf_state.bfs_retries
122 u32 ds_data; 122#define bf_seqno bf_state.bfs_seqno
123 u32 ds_ctl0; 123#define bf_tidno bf_state.bfs_tidno
124 u32 ds_ctl1; 124#define bf_keyix bf_state.bfs_keyix
125 u32 ds_hw[20]; 125#define bf_keytype bf_state.bfs_keytype
126 union { 126#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
127 struct ath_tx_status tx; 127#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
128 struct ath_rx_status rx; 128#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
129 void *stats; 129#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
130 } ds_us; 130#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
131 void *ds_vdata;
132} __packed;
133
134#define ds_txstat ds_us.tx
135#define ds_rxstat ds_us.rx
136#define ds_stat ds_us.stats
137
138#define ATH9K_TXDESC_CLRDMASK 0x0001
139#define ATH9K_TXDESC_NOACK 0x0002
140#define ATH9K_TXDESC_RTSENA 0x0004
141#define ATH9K_TXDESC_CTSENA 0x0008
142/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
143 * the descriptor its marked on. We take a tx interrupt to reap
144 * descriptors when the h/w hits an EOL condition or
145 * when the descriptor is specifically marked to generate
146 * an interrupt with this flag. Descriptors should be
147 * marked periodically to insure timely replenishing of the
148 * supply needed for sending frames. Defering interrupts
149 * reduces system load and potentially allows more concurrent
150 * work to be done but if done to aggressively can cause
151 * senders to backup. When the hardware queue is left too
152 * large rate control information may also be too out of
153 * date. An Alternative for this is TX interrupt mitigation
154 * but this needs more testing. */
155#define ATH9K_TXDESC_INTREQ 0x0010
156#define ATH9K_TXDESC_VEOL 0x0020
157#define ATH9K_TXDESC_EXT_ONLY 0x0040
158#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
159#define ATH9K_TXDESC_VMF 0x0100
160#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
161#define ATH9K_TXDESC_CAB 0x0400
162
163#define ATH9K_RXDESC_INTREQ 0x0020
164
165enum wireless_mode {
166 ATH9K_MODE_11A = 0,
167 ATH9K_MODE_11B = 2,
168 ATH9K_MODE_11G = 3,
169 ATH9K_MODE_11NA_HT20 = 6,
170 ATH9K_MODE_11NG_HT20 = 7,
171 ATH9K_MODE_11NA_HT40PLUS = 8,
172 ATH9K_MODE_11NA_HT40MINUS = 9,
173 ATH9K_MODE_11NG_HT40PLUS = 10,
174 ATH9K_MODE_11NG_HT40MINUS = 11,
175 ATH9K_MODE_MAX
176};
177
178enum ath9k_hw_caps {
179 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
180 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
181 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
182 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
183 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
184 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
185 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
186 ATH9K_HW_CAP_VEOL = BIT(7),
187 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
188 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
189 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
190 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
191 ATH9K_HW_CAP_HT = BIT(12),
192 ATH9K_HW_CAP_GTT = BIT(13),
193 ATH9K_HW_CAP_FASTCC = BIT(14),
194 ATH9K_HW_CAP_RFSILENT = BIT(15),
195 ATH9K_HW_CAP_WOW = BIT(16),
196 ATH9K_HW_CAP_CST = BIT(17),
197 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
198 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
199 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
200 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
201 ATH9K_HW_CAP_BT_COEX = BIT(22)
202};
203
204enum ath9k_capability_type {
205 ATH9K_CAP_CIPHER = 0,
206 ATH9K_CAP_TKIP_MIC,
207 ATH9K_CAP_TKIP_SPLIT,
208 ATH9K_CAP_PHYCOUNTERS,
209 ATH9K_CAP_DIVERSITY,
210 ATH9K_CAP_TXPOW,
211 ATH9K_CAP_PHYDIAG,
212 ATH9K_CAP_MCAST_KEYSRCH,
213 ATH9K_CAP_TSF_ADJUST,
214 ATH9K_CAP_WME_TKIPMIC,
215 ATH9K_CAP_RFSILENT,
216 ATH9K_CAP_ANT_CFG_2GHZ,
217 ATH9K_CAP_ANT_CFG_5GHZ
218};
219
220struct ath9k_hw_capabilities {
221 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
222 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
223 u16 total_queues;
224 u16 keycache_size;
225 u16 low_5ghz_chan, high_5ghz_chan;
226 u16 low_2ghz_chan, high_2ghz_chan;
227 u16 num_mr_retries;
228 u16 rts_aggr_limit;
229 u8 tx_chainmask;
230 u8 rx_chainmask;
231 u16 tx_triglevel_max;
232 u16 reg_cap;
233 u8 num_gpio_pins;
234 u8 num_antcfg_2ghz;
235 u8 num_antcfg_5ghz;
236};
237
238struct ath9k_ops_config {
239 int dma_beacon_response_time;
240 int sw_beacon_response_time;
241 int additional_swba_backoff;
242 int ack_6mb;
243 int cwm_ignore_extcca;
244 u8 pcie_powersave_enable;
245 u8 pcie_l1skp_enable;
246 u8 pcie_clock_req;
247 u32 pcie_waen;
248 int pcie_power_reset;
249 u8 pcie_restore;
250 u8 analog_shiftreg;
251 u8 ht_enable;
252 u32 ofdm_trig_low;
253 u32 ofdm_trig_high;
254 u32 cck_trig_high;
255 u32 cck_trig_low;
256 u32 enable_ani;
257 u8 noise_immunity_level;
258 u32 ofdm_weaksignal_det;
259 u32 cck_weaksignal_thr;
260 u8 spur_immunity_level;
261 u8 firstep_level;
262 int8_t rssi_thr_high;
263 int8_t rssi_thr_low;
264 u16 diversity_control;
265 u16 antenna_switch_swap;
266 int serialize_regmode;
267 int intr_mitigation;
268#define SPUR_DISABLE 0
269#define SPUR_ENABLE_IOCTL 1
270#define SPUR_ENABLE_EEPROM 2
271#define AR_EEPROM_MODAL_SPURS 5
272#define AR_SPUR_5413_1 1640
273#define AR_SPUR_5413_2 1200
274#define AR_NO_SPUR 0x8000
275#define AR_BASE_FREQ_2GHZ 2300
276#define AR_BASE_FREQ_5GHZ 4900
277#define AR_SPUR_FEEQ_BOUND_HT40 19
278#define AR_SPUR_FEEQ_BOUND_HT20 10
279 int spurmode;
280 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
281};
282
283enum ath9k_tx_queue {
284 ATH9K_TX_QUEUE_INACTIVE = 0,
285 ATH9K_TX_QUEUE_DATA,
286 ATH9K_TX_QUEUE_BEACON,
287 ATH9K_TX_QUEUE_CAB,
288 ATH9K_TX_QUEUE_UAPSD,
289 ATH9K_TX_QUEUE_PSPOLL
290};
291
292#define ATH9K_NUM_TX_QUEUES 10
293
294enum ath9k_tx_queue_subtype {
295 ATH9K_WME_AC_BK = 0,
296 ATH9K_WME_AC_BE,
297 ATH9K_WME_AC_VI,
298 ATH9K_WME_AC_VO,
299 ATH9K_WME_UPSD
300};
301
302enum ath9k_tx_queue_flags {
303 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
304 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
305 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
306 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
307 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
308 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
309 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
310 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
311 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
312};
313
314#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
315
316#define ATH9K_DECOMP_MASK_SIZE 128
317#define ATH9K_READY_TIME_LO_BOUND 50
318#define ATH9K_READY_TIME_HI_BOUND 96
319
320enum ath9k_pkt_type {
321 ATH9K_PKT_TYPE_NORMAL = 0,
322 ATH9K_PKT_TYPE_ATIM,
323 ATH9K_PKT_TYPE_PSPOLL,
324 ATH9K_PKT_TYPE_BEACON,
325 ATH9K_PKT_TYPE_PROBE_RESP,
326 ATH9K_PKT_TYPE_CHIRP,
327 ATH9K_PKT_TYPE_GRP_POLL,
328};
329
330struct ath9k_tx_queue_info {
331 u32 tqi_ver;
332 enum ath9k_tx_queue tqi_type;
333 enum ath9k_tx_queue_subtype tqi_subtype;
334 enum ath9k_tx_queue_flags tqi_qflags;
335 u32 tqi_priority;
336 u32 tqi_aifs;
337 u32 tqi_cwmin;
338 u32 tqi_cwmax;
339 u16 tqi_shretry;
340 u16 tqi_lgretry;
341 u32 tqi_cbrPeriod;
342 u32 tqi_cbrOverflowLimit;
343 u32 tqi_burstTime;
344 u32 tqi_readyTime;
345 u32 tqi_physCompBuf;
346 u32 tqi_intFlags;
347};
348
349enum ath9k_rx_filter {
350 ATH9K_RX_FILTER_UCAST = 0x00000001,
351 ATH9K_RX_FILTER_MCAST = 0x00000002,
352 ATH9K_RX_FILTER_BCAST = 0x00000004,
353 ATH9K_RX_FILTER_CONTROL = 0x00000008,
354 ATH9K_RX_FILTER_BEACON = 0x00000010,
355 ATH9K_RX_FILTER_PROM = 0x00000020,
356 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
357 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
358 ATH9K_RX_FILTER_PHYERR = 0x00000100,
359 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
360};
361
362enum ath9k_int {
363 ATH9K_INT_RX = 0x00000001,
364 ATH9K_INT_RXDESC = 0x00000002,
365 ATH9K_INT_RXNOFRM = 0x00000008,
366 ATH9K_INT_RXEOL = 0x00000010,
367 ATH9K_INT_RXORN = 0x00000020,
368 ATH9K_INT_TX = 0x00000040,
369 ATH9K_INT_TXDESC = 0x00000080,
370 ATH9K_INT_TIM_TIMER = 0x00000100,
371 ATH9K_INT_TXURN = 0x00000800,
372 ATH9K_INT_MIB = 0x00001000,
373 ATH9K_INT_RXPHY = 0x00004000,
374 ATH9K_INT_RXKCM = 0x00008000,
375 ATH9K_INT_SWBA = 0x00010000,
376 ATH9K_INT_BMISS = 0x00040000,
377 ATH9K_INT_BNR = 0x00100000,
378 ATH9K_INT_TIM = 0x00200000,
379 ATH9K_INT_DTIM = 0x00400000,
380 ATH9K_INT_DTIMSYNC = 0x00800000,
381 ATH9K_INT_GPIO = 0x01000000,
382 ATH9K_INT_CABEND = 0x02000000,
383 ATH9K_INT_CST = 0x10000000,
384 ATH9K_INT_GTT = 0x20000000,
385 ATH9K_INT_FATAL = 0x40000000,
386 ATH9K_INT_GLOBAL = 0x80000000,
387 ATH9K_INT_BMISC = ATH9K_INT_TIM |
388 ATH9K_INT_DTIM |
389 ATH9K_INT_DTIMSYNC |
390 ATH9K_INT_CABEND,
391 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
392 ATH9K_INT_RXDESC |
393 ATH9K_INT_RXEOL |
394 ATH9K_INT_RXORN |
395 ATH9K_INT_TXURN |
396 ATH9K_INT_TXDESC |
397 ATH9K_INT_MIB |
398 ATH9K_INT_RXPHY |
399 ATH9K_INT_RXKCM |
400 ATH9K_INT_SWBA |
401 ATH9K_INT_BMISS |
402 ATH9K_INT_GPIO,
403 ATH9K_INT_NOCARD = 0xffffffff
404};
405
406#define ATH9K_RATESERIES_RTS_CTS 0x0001
407#define ATH9K_RATESERIES_2040 0x0002
408#define ATH9K_RATESERIES_HALFGI 0x0004
409
410struct ath9k_11n_rate_series {
411 u32 Tries;
412 u32 Rate;
413 u32 PktDuration;
414 u32 ChSel;
415 u32 RateFlags;
416};
417
418#define CHANNEL_CW_INT 0x00002
419#define CHANNEL_CCK 0x00020
420#define CHANNEL_OFDM 0x00040
421#define CHANNEL_2GHZ 0x00080
422#define CHANNEL_5GHZ 0x00100
423#define CHANNEL_PASSIVE 0x00200
424#define CHANNEL_DYN 0x00400
425#define CHANNEL_HALF 0x04000
426#define CHANNEL_QUARTER 0x08000
427#define CHANNEL_HT20 0x10000
428#define CHANNEL_HT40PLUS 0x20000
429#define CHANNEL_HT40MINUS 0x40000
430
431#define CHANNEL_INTERFERENCE 0x01
432#define CHANNEL_DFS 0x02
433#define CHANNEL_4MS_LIMIT 0x04
434#define CHANNEL_DFS_CLEAR 0x08
435#define CHANNEL_DISALLOW_ADHOC 0x10
436#define CHANNEL_PER_11D_ADHOC 0x20
437
438#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
439#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
440#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
441#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
442#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
443#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
444#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
445#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
446#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
447#define CHANNEL_ALL \
448 (CHANNEL_OFDM| \
449 CHANNEL_CCK| \
450 CHANNEL_2GHZ | \
451 CHANNEL_5GHZ | \
452 CHANNEL_HT20 | \
453 CHANNEL_HT40PLUS | \
454 CHANNEL_HT40MINUS)
455
456struct ath9k_channel {
457 struct ieee80211_channel *chan;
458 u16 channel;
459 u32 channelFlags;
460 u32 chanmode;
461 int32_t CalValid;
462 bool oneTimeCalsDone;
463 int8_t iCoff;
464 int8_t qCoff;
465 int16_t rawNoiseFloor;
466};
467
468#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
469 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
470 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
471 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
472#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
473 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
474 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
475 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
476#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
477#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
478#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
479#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
480#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
481#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
482
483/* These macros check chanmode and not channelFlags */
484#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
485#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
486 ((_c)->chanmode == CHANNEL_G_HT20))
487#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
488 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
489 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
490 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
491#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
492
493#define IS_CHAN_A_5MHZ_SPACED(_c) \
494 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
495 (((_c)->channel % 20) != 0) && \
496 (((_c)->channel % 10) != 0))
497
498struct ath9k_keyval {
499 u8 kv_type;
500 u8 kv_pad;
501 u16 kv_len;
502 u8 kv_val[16];
503 u8 kv_mic[8];
504 u8 kv_txmic[8];
505};
506
507enum ath9k_key_type {
508 ATH9K_KEY_TYPE_CLEAR,
509 ATH9K_KEY_TYPE_WEP,
510 ATH9K_KEY_TYPE_AES,
511 ATH9K_KEY_TYPE_TKIP,
512};
513
514enum ath9k_cipher {
515 ATH9K_CIPHER_WEP = 0,
516 ATH9K_CIPHER_AES_OCB = 1,
517 ATH9K_CIPHER_AES_CCM = 2,
518 ATH9K_CIPHER_CKIP = 3,
519 ATH9K_CIPHER_TKIP = 4,
520 ATH9K_CIPHER_CLR = 5,
521 ATH9K_CIPHER_MIC = 127
522};
523
524#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
525#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
526#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
527#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
528#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
529#define AR_EEPROM_EEPCAP_MAXQCU_S 4
530#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
531#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
532#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
533
534#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
535#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
536#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
537#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
538#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
539#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
540
541#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
542#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
543
544#define SD_NO_CTL 0xE0
545#define NO_CTL 0xff
546#define CTL_MODE_M 7
547#define CTL_11A 0
548#define CTL_11B 1
549#define CTL_11G 2
550#define CTL_2GHT20 5
551#define CTL_5GHT20 6
552#define CTL_2GHT40 7
553#define CTL_5GHT40 8
554
555#define AR_EEPROM_MAC(i) (0x1d+(i))
556
557#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
558#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
559#define AR_EEPROM_RFSILENT_POLARITY 0x0002
560#define AR_EEPROM_RFSILENT_POLARITY_S 1
561
562#define CTRY_DEBUG 0x1ff
563#define CTRY_DEFAULT 0
564
565enum reg_ext_bitmap {
566 REG_EXT_JAPAN_MIDBAND = 1,
567 REG_EXT_FCC_DFS_HT40 = 2,
568 REG_EXT_JAPAN_NONDFS_HT40 = 3,
569 REG_EXT_JAPAN_DFS_HT40 = 4
570};
571
572struct ath9k_country_entry {
573 u16 countryCode;
574 u16 regDmnEnum;
575 u16 regDmn5G;
576 u16 regDmn2G;
577 u8 isMultidomain;
578 u8 iso[3];
579};
580
581#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
582#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
583
584#define SM(_v, _f) (((_v) << _f##_S) & _f)
585#define MS(_v, _f) (((_v) & _f) >> _f##_S)
586#define REG_RMW(_a, _r, _set, _clr) \
587 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
588#define REG_RMW_FIELD(_a, _r, _f, _v) \
589 REG_WRITE(_a, _r, \
590 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
591#define REG_SET_BIT(_a, _r, _f) \
592 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
593#define REG_CLR_BIT(_a, _r, _f) \
594 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
595
596#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
597
598#define INIT_AIFS 2
599#define INIT_CWMIN 15
600#define INIT_CWMIN_11B 31
601#define INIT_CWMAX 1023
602#define INIT_SH_RETRY 10
603#define INIT_LG_RETRY 10
604#define INIT_SSH_RETRY 32
605#define INIT_SLG_RETRY 32
606
607#define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
608
609#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
610#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
611
612#define IEEE80211_WEP_IVLEN 3
613#define IEEE80211_WEP_KIDLEN 1
614#define IEEE80211_WEP_CRCLEN 4
615#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
616 (IEEE80211_WEP_IVLEN + \
617 IEEE80211_WEP_KIDLEN + \
618 IEEE80211_WEP_CRCLEN))
619#define MAX_RATE_POWER 63
620
621enum ath9k_power_mode {
622 ATH9K_PM_AWAKE = 0,
623 ATH9K_PM_FULL_SLEEP,
624 ATH9K_PM_NETWORK_SLEEP,
625 ATH9K_PM_UNDEFINED
626};
627
628struct ath9k_mib_stats {
629 u32 ackrcv_bad;
630 u32 rts_bad;
631 u32 rts_good;
632 u32 fcs_bad;
633 u32 beacons;
634};
635 131
636enum ath9k_ant_setting { 132/*
637 ATH9K_ANT_VARIABLE = 0, 133 * Abstraction of a contiguous buffer to transmit/receive. There is only
638 ATH9K_ANT_FIXED_A, 134 * a single hw descriptor encapsulated here.
639 ATH9K_ANT_FIXED_B 135 */
640}; 136struct ath_buf {
137 struct list_head list;
138 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
139 an aggregate) */
140 struct ath_buf *bf_next; /* next subframe in the aggregate */
141 void *bf_mpdu; /* enclosing frame structure */
142 struct ath_desc *bf_desc; /* virtual addr of desc */
143 dma_addr_t bf_daddr; /* physical addr of desc */
144 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
145 u32 bf_status;
146 u16 bf_flags; /* tx descriptor flags */
147 struct ath_buf_state bf_state; /* buffer state */
148 dma_addr_t bf_dmacontext;
149};
150
151#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
152#define ATH_BUFSTATUS_STALE 0x00000002
153
154/* DMA state for tx/rx descriptors */
155
156struct ath_descdma {
157 const char *dd_name;
158 struct ath_desc *dd_desc; /* descriptors */
159 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
160 u32 dd_desc_len; /* size of dd_desc */
161 struct ath_buf *dd_bufptr; /* associated buffers */
162 dma_addr_t dd_dmacontext;
163};
164
165int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
166 struct list_head *head, const char *name,
167 int nbuf, int ndesc);
168void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
169 struct list_head *head);
170
171/***********/
172/* RX / TX */
173/***********/
174
175#define ATH_MAX_ANTENNA 3
176#define ATH_RXBUF 512
177#define WME_NUM_TID 16
178#define ATH_TXBUF 512
179#define ATH_TXMAXTRY 13
180#define ATH_11N_TXMAXTRY 10
181#define ATH_MGT_TXMAXTRY 4
182#define WME_BA_BMP_SIZE 64
183#define WME_MAX_BA WME_BA_BMP_SIZE
184#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
185
186#define TID_TO_WME_AC(_tid) \
187 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
188 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
189 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
190 WME_AC_VO)
191
192#define WME_AC_BE 0
193#define WME_AC_BK 1
194#define WME_AC_VI 2
195#define WME_AC_VO 3
196#define WME_NUM_AC 4
197
198#define ADDBA_EXCHANGE_ATTEMPTS 10
199#define ATH_AGGR_DELIM_SZ 4
200#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
201/* number of delimiters for encryption padding */
202#define ATH_AGGR_ENCRYPTDELIM 10
203/* minimum h/w qdepth to be sustained to maximize aggregation */
204#define ATH_AGGR_MIN_QDEPTH 2
205#define ATH_AMPDU_SUBFRAME_DEFAULT 32
206#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
207#define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
208
209#define IEEE80211_SEQ_SEQ_SHIFT 4
210#define IEEE80211_SEQ_MAX 4096
211#define IEEE80211_MIN_AMPDU_BUF 0x8
212#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
213#define IEEE80211_WEP_IVLEN 3
214#define IEEE80211_WEP_KIDLEN 1
215#define IEEE80211_WEP_CRCLEN 4
216#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
217 (IEEE80211_WEP_IVLEN + \
218 IEEE80211_WEP_KIDLEN + \
219 IEEE80211_WEP_CRCLEN))
220
221/* return whether a bit at index _n in bitmap _bm is set
222 * _sz is the size of the bitmap */
223#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
224 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
225
226/* return block-ack bitmap index given sequence and starting sequence */
227#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
228
229/* returns delimiter padding required given the packet length */
230#define ATH_AGGR_GET_NDELIM(_len) \
231 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
232 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
233
234#define BAW_WITHIN(_start, _bawsz, _seqno) \
235 ((((_seqno) - (_start)) & 4095) < (_bawsz))
236
237#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
238#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
239#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
240#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
241
242enum ATH_AGGR_STATUS {
243 ATH_AGGR_DONE,
244 ATH_AGGR_BAW_CLOSED,
245 ATH_AGGR_LIMITED,
246};
247
248struct ath_txq {
249 u32 axq_qnum; /* hardware q number */
250 u32 *axq_link; /* link ptr in last TX desc */
251 struct list_head axq_q; /* transmit queue */
252 spinlock_t axq_lock;
253 u32 axq_depth; /* queue depth */
254 u8 axq_aggr_depth; /* aggregates queued */
255 u32 axq_totalqueued; /* total ever queued */
256 bool stopped; /* Is mac80211 queue stopped ? */
257 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
258
259 /* first desc of the last descriptor that contains CTS */
260 struct ath_desc *axq_lastdsWithCTS;
261
262 /* final desc of the gating desc that determines whether
263 lastdsWithCTS has been DMA'ed or not */
264 struct ath_desc *axq_gatingds;
265
266 struct list_head axq_acq;
267};
268
269#define AGGR_CLEANUP BIT(1)
270#define AGGR_ADDBA_COMPLETE BIT(2)
271#define AGGR_ADDBA_PROGRESS BIT(3)
272
273/* per TID aggregate tx state for a destination */
274struct ath_atx_tid {
275 struct list_head list; /* round-robin tid entry */
276 struct list_head buf_q; /* pending buffers */
277 struct ath_node *an;
278 struct ath_atx_ac *ac;
279 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
280 u16 seq_start;
281 u16 seq_next;
282 u16 baw_size;
283 int tidno;
284 int baw_head; /* first un-acked tx buffer */
285 int baw_tail; /* next unused tx buffer slot */
286 int sched;
287 int paused;
288 u8 state;
289 int addba_exchangeattempts;
290};
291
292/* per access-category aggregate tx state for a destination */
293struct ath_atx_ac {
294 int sched; /* dest-ac is scheduled */
295 int qnum; /* H/W queue number associated
296 with this AC */
297 struct list_head list; /* round-robin txq entry */
298 struct list_head tid_q; /* queue of TIDs with buffers */
299};
300
301/* per-frame tx control block */
302struct ath_tx_control {
303 struct ath_txq *txq;
304 int if_id;
305};
306
307/* per frame tx status block */
308struct ath_xmit_status {
309 int retries; /* number of retries to successufully
310 transmit this frame */
311 int flags; /* status of transmit */
312#define ATH_TX_ERROR 0x01
313#define ATH_TX_XRETRY 0x02
314#define ATH_TX_BAR 0x04
315};
316
317/* All RSSI values are noise floor adjusted */
318struct ath_tx_stat {
319 int rssi;
320 int rssictl[ATH_MAX_ANTENNA];
321 int rssiextn[ATH_MAX_ANTENNA];
322 int rateieee;
323 int rateKbps;
324 int ratecode;
325 int flags;
326 u32 airtime; /* time on air per final tx rate */
327};
328
329struct aggr_rifs_param {
330 int param_max_frames;
331 int param_max_len;
332 int param_rl;
333 int param_al;
334 struct ath_rc_series *param_rcs;
335};
336
337struct ath_node {
338 struct ath_softc *an_sc;
339 struct ath_atx_tid tid[WME_NUM_TID];
340 struct ath_atx_ac ac[WME_NUM_AC];
341 u16 maxampdu;
342 u8 mpdudensity;
343};
344
345struct ath_tx {
346 u16 seq_no;
347 u32 txqsetup;
348 int hwq_map[ATH9K_WME_AC_VO+1];
349 spinlock_t txbuflock;
350 struct list_head txbuf;
351 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
352 struct ath_descdma txdma;
353};
354
355struct ath_rx {
356 u8 defant;
357 u8 rxotherant;
358 u32 *rxlink;
359 int bufsize;
360 unsigned int rxfilter;
361 spinlock_t rxflushlock;
362 spinlock_t rxbuflock;
363 struct list_head rxbuf;
364 struct ath_descdma rxdma;
365};
366
367int ath_startrecv(struct ath_softc *sc);
368bool ath_stoprecv(struct ath_softc *sc);
369void ath_flushrecv(struct ath_softc *sc);
370u32 ath_calcrxfilter(struct ath_softc *sc);
371int ath_rx_init(struct ath_softc *sc, int nbufs);
372void ath_rx_cleanup(struct ath_softc *sc);
373int ath_rx_tasklet(struct ath_softc *sc, int flush);
374struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
375void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
376int ath_tx_setup(struct ath_softc *sc, int haltype);
377void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
378void ath_draintxq(struct ath_softc *sc,
379 struct ath_txq *txq, bool retry_tx);
380void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
381void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
382void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
383int ath_tx_init(struct ath_softc *sc, int nbufs);
384int ath_tx_cleanup(struct ath_softc *sc);
385struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
386int ath_txq_update(struct ath_softc *sc, int qnum,
387 struct ath9k_tx_queue_info *q);
388int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
389 struct ath_tx_control *txctl);
390void ath_tx_tasklet(struct ath_softc *sc);
391void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
392bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
393int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
394 u16 tid, u16 *ssn);
395int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
396void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
397
398/********/
399/* VAPs */
400/********/
641 401
642#define ATH9K_SLOT_TIME_6 6 402/*
643#define ATH9K_SLOT_TIME_9 9 403 * Define the scheme that we select MAC address for multiple
644#define ATH9K_SLOT_TIME_20 20 404 * BSS on the same radio. The very first VAP will just use the MAC
405 * address from the EEPROM. For the next 3 VAPs, we set the
406 * U/L bit (bit 1) in MAC address, and use the next two bits as the
407 * index of the VAP.
408 */
645 409
646enum ath9k_ht_macmode { 410#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
647 ATH9K_HT_MACMODE_20 = 0, 411 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
648 ATH9K_HT_MACMODE_2040 = 1,
649};
650 412
651enum ath9k_ht_extprotspacing { 413struct ath_vap {
652 ATH9K_HT_EXTPROTSPACING_20 = 0, 414 int av_bslot;
653 ATH9K_HT_EXTPROTSPACING_25 = 1, 415 enum nl80211_iftype av_opmode;
416 struct ath_buf *av_bcbuf;
417 struct ath_tx_control av_btxctl;
654}; 418};
655 419
656struct ath9k_ht_cwm { 420/*******************/
657 enum ath9k_ht_macmode ht_macmode; 421/* Beacon Handling */
658 enum ath9k_ht_extprotspacing ht_extprotspacing; 422/*******************/
659};
660 423
661enum ath9k_ani_cmd { 424/*
662 ATH9K_ANI_PRESENT = 0x1, 425 * Regardless of the number of beacons we stagger, (i.e. regardless of the
663 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, 426 * number of BSSIDs) if a given beacon does not go out even after waiting this
664 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, 427 * number of beacon intervals, the game's up.
665 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, 428 */
666 ATH9K_ANI_FIRSTEP_LEVEL = 0x10, 429#define BSTUCK_THRESH (9 * ATH_BCBUF)
667 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, 430#define ATH_BCBUF 1
668 ATH9K_ANI_MODE = 0x40, 431#define ATH_DEFAULT_BINTVAL 100 /* TU */
669 ATH9K_ANI_PHYERR_RESET = 0x80, 432#define ATH_DEFAULT_BMISS_LIMIT 10
670 ATH9K_ANI_ALL = 0xff 433#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
671}; 434
435struct ath_beacon_config {
436 u16 beacon_interval;
437 u16 listen_interval;
438 u16 dtim_period;
439 u16 bmiss_timeout;
440 u8 dtim_count;
441 u8 tim_offset;
442 union {
443 u64 last_tsf;
444 u8 last_tstamp[8];
445 } u; /* last received beacon/probe response timestamp of this BSS. */
446};
447
448struct ath_beacon {
449 enum {
450 OK, /* no change needed */
451 UPDATE, /* update pending */
452 COMMIT /* beacon sent, commit change */
453 } updateslot; /* slot time update fsm */
454
455 u32 beaconq;
456 u32 bmisscnt;
457 u32 ast_be_xmit;
458 u64 bc_tstamp;
459 int bslot[ATH_BCBUF];
460 int slottime;
461 int slotupdate;
462 struct ath9k_tx_queue_info beacon_qi;
463 struct ath_descdma bdma;
464 struct ath_txq *cabq;
465 struct list_head bbuf;
466};
467
468void ath9k_beacon_tasklet(unsigned long data);
469void ath_beacon_config(struct ath_softc *sc, int if_id);
470int ath_beaconq_setup(struct ath_hal *ah);
471int ath_beacon_alloc(struct ath_softc *sc, int if_id);
472void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
473void ath_beacon_sync(struct ath_softc *sc, int if_id);
474
475/*******/
476/* ANI */
477/*******/
672 478
673enum { 479/* ANI values for STA only.
674 WLAN_RC_PHY_OFDM, 480 FIXME: Add appropriate values for AP later */
675 WLAN_RC_PHY_CCK,
676 WLAN_RC_PHY_HT_20_SS,
677 WLAN_RC_PHY_HT_20_DS,
678 WLAN_RC_PHY_HT_40_SS,
679 WLAN_RC_PHY_HT_40_DS,
680 WLAN_RC_PHY_HT_20_SS_HGI,
681 WLAN_RC_PHY_HT_20_DS_HGI,
682 WLAN_RC_PHY_HT_40_SS_HGI,
683 WLAN_RC_PHY_HT_40_DS_HGI,
684 WLAN_RC_PHY_MAX
685};
686 481
687enum ath9k_tp_scale { 482#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
688 ATH9K_TP_SCALE_MAX = 0, 483#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
689 ATH9K_TP_SCALE_50, 484#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
690 ATH9K_TP_SCALE_25, 485#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
691 ATH9K_TP_SCALE_12,
692 ATH9K_TP_SCALE_MIN
693};
694 486
695enum ser_reg_mode { 487struct ath_ani {
696 SER_REG_MODE_OFF = 0, 488 bool sc_caldone;
697 SER_REG_MODE_ON = 1, 489 int16_t sc_noise_floor;
698 SER_REG_MODE_AUTO = 2, 490 unsigned int sc_longcal_timer;
491 unsigned int sc_shortcal_timer;
492 unsigned int sc_resetcal_timer;
493 unsigned int sc_checkani_timer;
494 struct timer_list timer;
699}; 495};
700 496
701#define AR_PHY_CCA_MAX_GOOD_VALUE -85 497/********************/
702#define AR_PHY_CCA_MAX_HIGH_VALUE -62 498/* LED Control */
703#define AR_PHY_CCA_MIN_BAD_VALUE -121 499/********************/
704#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
705#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
706 500
707#define ATH9K_NF_CAL_HIST_MAX 5 501#define ATH_LED_PIN 1
708#define NUM_NF_READINGS 6 502#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
503#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
709 504
710struct ath9k_nfcal_hist { 505enum ath_led_type {
711 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX]; 506 ATH_LED_RADIO,
712 u8 currIndex; 507 ATH_LED_ASSOC,
713 int16_t privNF; 508 ATH_LED_TX,
714 u8 invalidNFcount; 509 ATH_LED_RX
715}; 510};
716 511
717struct ath9k_beacon_state { 512struct ath_led {
718 u32 bs_nexttbtt; 513 struct ath_softc *sc;
719 u32 bs_nextdtim; 514 struct led_classdev led_cdev;
720 u32 bs_intval; 515 enum ath_led_type led_type;
721#define ATH9K_BEACON_PERIOD 0x0000ffff 516 char name[32];
722#define ATH9K_BEACON_ENA 0x00800000 517 bool registered;
723#define ATH9K_BEACON_RESET_TSF 0x01000000
724 u32 bs_dtimperiod;
725 u16 bs_cfpperiod;
726 u16 bs_cfpmaxduration;
727 u32 bs_cfpnext;
728 u16 bs_timoffset;
729 u16 bs_bmissthreshold;
730 u32 bs_sleepduration;
731}; 518};
732 519
733struct ath9k_node_stats { 520/* Rfkill */
734 u32 ns_avgbrssi; 521#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
735 u32 ns_avgrssi;
736 u32 ns_avgtxrssi;
737 u32 ns_avgtxrate;
738};
739
740#define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
741
742#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
743#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
744#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
745#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
746#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
747#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
748 522
749enum { 523struct ath_rfkill {
750 ATH9K_RESET_POWER_ON, 524 struct rfkill *rfkill;
751 ATH9K_RESET_WARM, 525 struct delayed_work rfkill_poll;
752 ATH9K_RESET_COLD, 526 char rfkill_name[32];
753}; 527};
754 528
755#define AH_USE_EEPROM 0x1 529/********************/
756 530/* Main driver core */
757struct ath_hal { 531/********************/
758 u32 ah_magic;
759 u16 ah_devid;
760 u16 ah_subvendorid;
761 u32 ah_macVersion;
762 u16 ah_macRev;
763 u16 ah_phyRev;
764 u16 ah_analog5GhzRev;
765 u16 ah_analog2GhzRev;
766
767 void __iomem *ah_sh;
768 struct ath_softc *ah_sc;
769
770 enum nl80211_iftype ah_opmode;
771 struct ath9k_ops_config ah_config;
772 struct ath9k_hw_capabilities ah_caps;
773
774 u16 ah_countryCode;
775 u32 ah_flags;
776 int16_t ah_powerLimit;
777 u16 ah_maxPowerLevel;
778 u32 ah_tpScale;
779 u16 ah_currentRD;
780 u16 ah_currentRDExt;
781 u16 ah_currentRDInUse;
782 char alpha2[2];
783 struct reg_dmn_pair_mapping *regpair;
784 enum ath9k_power_mode ah_power_mode;
785 enum ath9k_power_mode ah_restore_mode;
786
787 struct ath9k_channel ah_channels[38];
788 struct ath9k_channel *ah_curchan;
789
790 bool ah_isPciExpress;
791 u16 ah_txTrigLevel;
792 u16 ah_rfsilent;
793 u32 ah_rfkill_gpio;
794 u32 ah_rfkill_polarity;
795 u32 ah_btactive_gpio;
796 u32 ah_wlanactive_gpio;
797 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
798
799 bool sw_mgmt_crypto;
800};
801
802struct chan_centers {
803 u16 synth_center;
804 u16 ctl_center;
805 u16 ext_center;
806};
807 532
808struct ath_rate_table; 533/*
809 534 * Default cache line size, in bytes.
810/* Helpers */ 535 * Used when PCI device not fully initialized by bootrom/BIOS
811 536*/
812bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val); 537#define DEFAULT_CACHELINE 32
813u32 ath9k_hw_reverse_bits(u32 val, u32 n); 538#define ATH_DEFAULT_NOISE_FLOOR -95
814bool ath9k_get_channel_edges(struct ath_hal *ah, 539#define ATH_REGCLASSIDS_MAX 10
815 u16 flags, u16 *low, 540#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
816 u16 *high); 541#define ATH_MAX_SW_RETRIES 10
817u16 ath9k_hw_computetxtime(struct ath_hal *ah, 542#define ATH_CHAN_MAX 255
818 struct ath_rate_table *rates, 543#define IEEE80211_WEP_NKID 4 /* number of key ids */
819 u32 frameLen, u16 rateix,
820 bool shortPreamble);
821void ath9k_hw_get_channel_centers(struct ath_hal *ah,
822 struct ath9k_channel *chan,
823 struct chan_centers *centers);
824
825/* Attach, Detach */
826
827const char *ath9k_hw_probe(u16 vendorid, u16 devid);
828void ath9k_hw_detach(struct ath_hal *ah);
829struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
830 void __iomem *mem, int *error);
831void ath9k_hw_rfdetach(struct ath_hal *ah);
832
833
834/* HW Reset */
835
836int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
837 bool bChannelChange);
838
839/* Key Cache Management */
840
841bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
842bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
843bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
844 const struct ath9k_keyval *k,
845 const u8 *mac, int xorKey);
846bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
847
848/* Power Management */
849
850bool ath9k_hw_setpower(struct ath_hal *ah,
851 enum ath9k_power_mode mode);
852void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
853
854/* Beacon timers */
855
856void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
857void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
858 const struct ath9k_beacon_state *bs);
859/* HW Capabilities */
860
861bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
862bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
863 u32 capability, u32 *result);
864bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
865 u32 capability, u32 setting, int *status);
866
867/* GPIO / RFKILL / Antennae */
868 544
869void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio); 545/*
870u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio); 546 * The key cache is used for h/w cipher state and also for
871void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio, 547 * tracking station state such as the current tx antenna.
872 u32 ah_signal_type); 548 * We also setup a mapping table between key cache slot indices
873void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val); 549 * and station state to short-circuit node lookups on rx.
874#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) 550 * Different parts have different size key caches. We handle
875void ath9k_enable_rfkill(struct ath_hal *ah); 551 * up to ATH_KEYMAX entries (could dynamically allocate state).
552 */
553#define ATH_KEYMAX 128 /* max key cache size we handle */
554
555#define ATH_IF_ID_ANY 0xff
556#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
557#define ATH_RSSI_DUMMY_MARKER 0x127
558#define ATH_RATE_DUMMY_MARKER 0
559
560#define SC_OP_INVALID BIT(0)
561#define SC_OP_BEACONS BIT(1)
562#define SC_OP_RXAGGR BIT(2)
563#define SC_OP_TXAGGR BIT(3)
564#define SC_OP_CHAINMASK_UPDATE BIT(4)
565#define SC_OP_FULL_RESET BIT(5)
566#define SC_OP_NO_RESET BIT(6)
567#define SC_OP_PREAMBLE_SHORT BIT(7)
568#define SC_OP_PROTECT_ENABLE BIT(8)
569#define SC_OP_RXFLUSH BIT(9)
570#define SC_OP_LED_ASSOCIATED BIT(10)
571#define SC_OP_RFKILL_REGISTERED BIT(11)
572#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
573#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
574#define SC_OP_WAIT_FOR_BEACON BIT(14)
575#define SC_OP_LED_ON BIT(15)
576
577struct ath_bus_ops {
578 void (*read_cachesize)(struct ath_softc *sc, int *csz);
579 void (*cleanup)(struct ath_softc *sc);
580 bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
581};
582
583struct ath_softc {
584 struct ieee80211_hw *hw;
585 struct device *dev;
586 struct tasklet_struct intr_tq;
587 struct tasklet_struct bcon_tasklet;
588 struct ath_hal *sc_ah;
589 void __iomem *mem;
590 int irq;
591 spinlock_t sc_resetlock;
592 struct mutex mutex;
593
594 u8 sc_curbssid[ETH_ALEN];
595 u8 sc_myaddr[ETH_ALEN];
596 u8 sc_bssidmask[ETH_ALEN];
597 u32 sc_intrstatus;
598 u32 sc_flags; /* SC_OP_* */
599 u16 sc_curtxpow;
600 u16 sc_curaid;
601 u16 sc_cachelsz;
602 u8 sc_nbcnvaps;
603 u16 sc_nvaps;
604 u8 sc_tx_chainmask;
605 u8 sc_rx_chainmask;
606 u32 sc_keymax;
607 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
608 u8 sc_splitmic;
609 atomic_t ps_usecount;
610 enum ath9k_int sc_imask;
611 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
612 enum ath9k_ht_macmode tx_chan_width;
613
614 struct ath_config sc_config;
615 struct ath_rx rx;
616 struct ath_tx tx;
617 struct ath_beacon beacon;
618 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
619 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
620 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
621 struct ath_rate_table *cur_rate_table;
622 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
623
624 struct ath_led radio_led;
625 struct ath_led assoc_led;
626 struct ath_led tx_led;
627 struct ath_led rx_led;
628 struct delayed_work ath_led_blink_work;
629 int led_on_duration;
630 int led_off_duration;
631 int led_on_cnt;
632 int led_off_cnt;
633
634 struct ath_rfkill rf_kill;
635 struct ath_ani sc_ani;
636 struct ath9k_node_stats sc_halstats;
637#ifdef CONFIG_ATH9K_DEBUG
638 struct ath9k_debug sc_debug;
639#endif
640 struct ath_bus_ops *bus_ops;
641};
642
643int ath_reset(struct ath_softc *sc, bool retry_tx);
644int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
645int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
646int ath_cabq_update(struct ath_softc *);
647
648static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
649{
650 sc->bus_ops->read_cachesize(sc, csz);
651}
652
653static inline void ath_bus_cleanup(struct ath_softc *sc)
654{
655 sc->bus_ops->cleanup(sc);
656}
657
658extern struct ieee80211_ops ath9k_ops;
659
660irqreturn_t ath_isr(int irq, void *dev);
661void ath_cleanup(struct ath_softc *sc);
662int ath_attach(u16 devid, struct ath_softc *sc);
663void ath_detach(struct ath_softc *sc);
664const char *ath_mac_bb_name(u32 mac_bb_version);
665const char *ath_rf_name(u16 rf_version);
666
667#ifdef CONFIG_PCI
668int ath_pci_init(void);
669void ath_pci_exit(void);
670#else
671static inline int ath_pci_init(void) { return 0; };
672static inline void ath_pci_exit(void) {};
876#endif 673#endif
877u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
878void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
879bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
880 enum ath9k_ant_setting settings,
881 struct ath9k_channel *chan,
882 u8 *tx_chainmask,
883 u8 *rx_chainmask,
884 u8 *antenna_cfgd);
885
886/* General Operation */
887
888u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
889void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
890bool ath9k_hw_phy_disable(struct ath_hal *ah);
891bool ath9k_hw_disable(struct ath_hal *ah);
892bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
893void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
894bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
895void ath9k_hw_setopmode(struct ath_hal *ah);
896void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
897void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
898bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
899void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
900u64 ath9k_hw_gettsf64(struct ath_hal *ah);
901void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64);
902void ath9k_hw_reset_tsf(struct ath_hal *ah);
903bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
904bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
905void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
906
907/* Regulatory */
908u16 ath9k_regd_get_rd(struct ath_hal *ah);
909bool ath9k_is_world_regd(struct ath_hal *ah);
910const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah);
911const struct ieee80211_regdomain *ath9k_default_world_regdomain(void);
912
913void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby);
914void ath9k_reg_apply_radar_flags(struct wiphy *wiphy);
915
916int ath9k_regd_init(struct ath_hal *ah);
917bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah);
918u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
919int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
920
921/* ANI */
922
923void ath9k_ani_reset(struct ath_hal *ah);
924void ath9k_hw_ani_monitor(struct ath_hal *ah,
925 const struct ath9k_node_stats *stats,
926 struct ath9k_channel *chan);
927bool ath9k_hw_phycounters(struct ath_hal *ah);
928void ath9k_enable_mib_counters(struct ath_hal *ah);
929void ath9k_hw_disable_mib_counters(struct ath_hal *ah);
930u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
931 u32 *rxc_pcnt,
932 u32 *rxf_pcnt,
933 u32 *txf_pcnt);
934void ath9k_hw_procmibevent(struct ath_hal *ah,
935 const struct ath9k_node_stats *stats);
936void ath9k_hw_ani_setup(struct ath_hal *ah);
937void ath9k_hw_ani_attach(struct ath_hal *ah);
938void ath9k_hw_ani_detach(struct ath_hal *ah);
939
940/* Calibration */
941
942bool ath9k_hw_reset_calvalid(struct ath_hal *ah);
943void ath9k_hw_start_nfcal(struct ath_hal *ah);
944void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
945int16_t ath9k_hw_getnf(struct ath_hal *ah,
946 struct ath9k_channel *chan);
947void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
948s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
949bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
950 u8 rxchainmask, bool longcal,
951 bool *isCalDone);
952bool ath9k_hw_init_cal(struct ath_hal *ah,
953 struct ath9k_channel *chan);
954
955
956/* EEPROM */
957
958int ath9k_hw_set_txpower(struct ath_hal *ah,
959 struct ath9k_channel *chan,
960 u16 cfgCtl,
961 u8 twiceAntennaReduction,
962 u8 twiceMaxRegulatoryPower,
963 u8 powerLimit);
964void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
965bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
966 struct ath9k_channel *chan,
967 int16_t *ratesArray,
968 u16 cfgCtl,
969 u8 AntennaReduction,
970 u8 twiceMaxRegulatoryPower,
971 u8 powerLimit);
972bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
973 struct ath9k_channel *chan,
974 int16_t *pTxPowerIndexOffset);
975bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
976 struct ath9k_channel *chan);
977u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
978 struct ath9k_channel *chan);
979u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
980 enum ieee80211_band freq_band);
981u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
982int ath9k_hw_eeprom_attach(struct ath_hal *ah);
983
984/* Interrupt Handling */
985
986bool ath9k_hw_intrpend(struct ath_hal *ah);
987bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
988enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
989enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
990
991/* MAC (PCU/QCU) */
992
993u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
994bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
995bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
996u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
997bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
998bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
999bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1000 u32 segLen, bool firstSeg,
1001 bool lastSeg, const struct ath_desc *ds0);
1002void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1003int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
1004void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1005 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
1006 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
1007void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1008 struct ath_desc *lastds,
1009 u32 durUpdateEn, u32 rtsctsRate,
1010 u32 rtsctsDuration,
1011 struct ath9k_11n_rate_series series[],
1012 u32 nseries, u32 flags);
1013void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1014 u32 aggrLen);
1015void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1016 u32 numDelims);
1017void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1018void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1019void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
1020 u32 burstDuration);
1021void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
1022 u32 vmf);
1023void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1024bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
1025 const struct ath9k_tx_queue_info *qinfo);
1026bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
1027 struct ath9k_tx_queue_info *qinfo);
1028int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1029 const struct ath9k_tx_queue_info *qinfo);
1030bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1031bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
1032int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
1033 u32 pa, struct ath_desc *nds, u64 tsf);
1034bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1035 u32 size, u32 flags);
1036bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
1037void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
1038void ath9k_hw_rxena(struct ath_hal *ah);
1039void ath9k_hw_startpcureceive(struct ath_hal *ah);
1040void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1041bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1042void ath9k_hw_btcoex_enable(struct ath_hal *ah);
1043 674
675#ifdef CONFIG_ATHEROS_AR71XX
676int ath_ahb_init(void);
677void ath_ahb_exit(void);
678#else
679static inline int ath_ahb_init(void) { return 0; };
680static inline void ath_ahb_exit(void) {};
1044#endif 681#endif
682
683static inline void ath9k_ps_wakeup(struct ath_softc *sc)
684{
685 if (atomic_inc_return(&sc->ps_usecount) == 1)
686 if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) {
687 sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
688 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
689 }
690}
691
692static inline void ath9k_ps_restore(struct ath_softc *sc)
693{
694 if (atomic_dec_and_test(&sc->ps_usecount))
695 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
696 ath9k_hw_setpower(sc->sc_ah,
697 sc->sc_ah->ah_restore_mode);
698}
699#endif /* ATH9K_H */
diff --git a/drivers/net/wireless/ath9k/beacon.c b/drivers/net/wireless/ath9k/beacon.c
index 61d37be9717e..1f92ad7d3c72 100644
--- a/drivers/net/wireless/ath9k/beacon.c
+++ b/drivers/net/wireless/ath9k/beacon.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18 18
19/* 19/*
20 * This function will modify certain transmit queue properties depending on 20 * This function will modify certain transmit queue properties depending on
diff --git a/drivers/net/wireless/ath9k/calib.c b/drivers/net/wireless/ath9k/calib.c
index 69ff01ce968b..016302c53cc5 100644
--- a/drivers/net/wireless/ath9k/calib.c
+++ b/drivers/net/wireless/ath9k/calib.c
@@ -14,10 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22/* We can tune this as we go by monitoring really low values */ 19/* We can tune this as we go by monitoring really low values */
23#define ATH9K_NF_TOO_LOW -60 20#define ATH9K_NF_TOO_LOW -60
diff --git a/drivers/net/wireless/ath9k/calib.h b/drivers/net/wireless/ath9k/calib.h
new file mode 100644
index 000000000000..ac7d88fa8268
--- /dev/null
+++ b/drivers/net/wireless/ath9k/calib.h
@@ -0,0 +1,124 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CALIB_H
18#define CALIB_H
19
20extern const struct hal_percal_data iq_cal_multi_sample;
21extern const struct hal_percal_data iq_cal_single_sample;
22extern const struct hal_percal_data adc_gain_cal_multi_sample;
23extern const struct hal_percal_data adc_gain_cal_single_sample;
24extern const struct hal_percal_data adc_dc_cal_multi_sample;
25extern const struct hal_percal_data adc_dc_cal_single_sample;
26extern const struct hal_percal_data adc_init_dc_cal;
27
28#define AR_PHY_CCA_MAX_GOOD_VALUE -85
29#define AR_PHY_CCA_MAX_HIGH_VALUE -62
30#define AR_PHY_CCA_MIN_BAD_VALUE -121
31#define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
32#define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
33
34#define NUM_NF_READINGS 6
35#define ATH9K_NF_CAL_HIST_MAX 5
36
37struct ar5416IniArray {
38 u32 *ia_array;
39 u32 ia_rows;
40 u32 ia_columns;
41};
42
43#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
44 (iniarray)->ia_array = (u32 *)(array); \
45 (iniarray)->ia_rows = (rows); \
46 (iniarray)->ia_columns = (columns); \
47 } while (0)
48
49#define INI_RA(iniarray, row, column) \
50 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
51
52#define INIT_CAL(_perCal) do { \
53 (_perCal)->calState = CAL_WAITING; \
54 (_perCal)->calNext = NULL; \
55 } while (0)
56
57#define INSERT_CAL(_ahp, _perCal) \
58 do { \
59 if ((_ahp)->ah_cal_list_last == NULL) { \
60 (_ahp)->ah_cal_list = \
61 (_ahp)->ah_cal_list_last = (_perCal); \
62 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
63 } else { \
64 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
65 (_ahp)->ah_cal_list_last = (_perCal); \
66 (_perCal)->calNext = (_ahp)->ah_cal_list; \
67 } \
68 } while (0)
69
70enum hal_cal_types {
71 ADC_DC_INIT_CAL = 0x1,
72 ADC_GAIN_CAL = 0x2,
73 ADC_DC_CAL = 0x4,
74 IQ_MISMATCH_CAL = 0x8
75};
76
77enum hal_cal_state {
78 CAL_INACTIVE,
79 CAL_WAITING,
80 CAL_RUNNING,
81 CAL_DONE
82};
83
84#define MIN_CAL_SAMPLES 1
85#define MAX_CAL_SAMPLES 64
86#define INIT_LOG_COUNT 5
87#define PER_MIN_LOG_COUNT 2
88#define PER_MAX_LOG_COUNT 10
89
90struct hal_percal_data {
91 enum hal_cal_types calType;
92 u32 calNumSamples;
93 u32 calCountMax;
94 void (*calCollect) (struct ath_hal *);
95 void (*calPostProc) (struct ath_hal *, u8);
96};
97
98struct hal_cal_list {
99 const struct hal_percal_data *calData;
100 enum hal_cal_state calState;
101 struct hal_cal_list *calNext;
102};
103
104struct ath9k_nfcal_hist {
105 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
106 u8 currIndex;
107 int16_t privNF;
108 u8 invalidNFcount;
109};
110
111bool ath9k_hw_reset_calvalid(struct ath_hal *ah);
112void ath9k_hw_start_nfcal(struct ath_hal *ah);
113void ath9k_hw_loadnf(struct ath_hal *ah, struct ath9k_channel *chan);
114int16_t ath9k_hw_getnf(struct ath_hal *ah,
115 struct ath9k_channel *chan);
116void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah);
117s16 ath9k_hw_getchan_noise(struct ath_hal *ah, struct ath9k_channel *chan);
118bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan,
119 u8 rxchainmask, bool longcal,
120 bool *isCalDone);
121bool ath9k_hw_init_cal(struct ath_hal *ah,
122 struct ath9k_channel *chan);
123
124#endif /* CALIB_H */
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h
deleted file mode 100644
index 64fc5c269f22..000000000000
--- a/drivers/net/wireless/ath9k/core.h
+++ /dev/null
@@ -1,821 +0,0 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef CORE_H
18#define CORE_H
19
20#include <linux/etherdevice.h>
21#include <linux/device.h>
22#include <net/mac80211.h>
23#include <linux/leds.h>
24#include <linux/rfkill.h>
25
26#include "ath9k.h"
27#include "rc.h"
28
29struct ath_node;
30
31/* Macro to expand scalars to 64-bit objects */
32
33#define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
35 (sizeof(x) == 16) ? \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
40
41/* increment with wrap-around */
42#define INCR(_l, _sz) do { \
43 (_l)++; \
44 (_l) &= ((_sz) - 1); \
45 } while (0)
46
47/* decrement with wrap-around */
48#define DECR(_l, _sz) do { \
49 (_l)--; \
50 (_l) &= ((_sz) - 1); \
51 } while (0)
52
53#define A_MAX(a, b) ((a) > (b) ? (a) : (b))
54
55#define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
57 BUG(); \
58 } \
59 } while (0)
60
61#define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
63
64#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
65
66static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
67
68enum ATH_DEBUG {
69 ATH_DBG_RESET = 0x00000001,
70 ATH_DBG_REG_IO = 0x00000002,
71 ATH_DBG_QUEUE = 0x00000004,
72 ATH_DBG_EEPROM = 0x00000008,
73 ATH_DBG_CALIBRATE = 0x00000010,
74 ATH_DBG_CHANNEL = 0x00000020,
75 ATH_DBG_INTERRUPT = 0x00000040,
76 ATH_DBG_REGULATORY = 0x00000080,
77 ATH_DBG_ANI = 0x00000100,
78 ATH_DBG_POWER_MGMT = 0x00000200,
79 ATH_DBG_XMIT = 0x00000400,
80 ATH_DBG_BEACON = 0x00001000,
81 ATH_DBG_CONFIG = 0x00002000,
82 ATH_DBG_KEYCACHE = 0x00004000,
83 ATH_DBG_FATAL = 0x00008000,
84 ATH_DBG_ANY = 0xffffffff
85};
86
87#define DBG_DEFAULT (ATH_DBG_FATAL)
88
89#ifdef CONFIG_ATH9K_DEBUG
90
91/**
92 * struct ath_interrupt_stats - Contains statistics about interrupts
93 * @total: Total no. of interrupts generated so far
94 * @rxok: RX with no errors
95 * @rxeol: RX with no more RXDESC available
96 * @rxorn: RX FIFO overrun
97 * @txok: TX completed at the requested rate
98 * @txurn: TX FIFO underrun
99 * @mib: MIB regs reaching its threshold
100 * @rxphyerr: RX with phy errors
101 * @rx_keycache_miss: RX with key cache misses
102 * @swba: Software Beacon Alert
103 * @bmiss: Beacon Miss
104 * @bnr: Beacon Not Ready
105 * @cst: Carrier Sense TImeout
106 * @gtt: Global TX Timeout
107 * @tim: RX beacon TIM occurrence
108 * @cabend: RX End of CAB traffic
109 * @dtimsync: DTIM sync lossage
110 * @dtim: RX Beacon with DTIM
111 */
112struct ath_interrupt_stats {
113 u32 total;
114 u32 rxok;
115 u32 rxeol;
116 u32 rxorn;
117 u32 txok;
118 u32 txeol;
119 u32 txurn;
120 u32 mib;
121 u32 rxphyerr;
122 u32 rx_keycache_miss;
123 u32 swba;
124 u32 bmiss;
125 u32 bnr;
126 u32 cst;
127 u32 gtt;
128 u32 tim;
129 u32 cabend;
130 u32 dtimsync;
131 u32 dtim;
132};
133
134struct ath_legacy_rc_stats {
135 u32 success;
136};
137
138struct ath_11n_rc_stats {
139 u32 success;
140 u32 retries;
141 u32 xretries;
142};
143
144struct ath_stats {
145 struct ath_interrupt_stats istats;
146 struct ath_legacy_rc_stats legacy_rcstats[12]; /* max(11a,11b,11g) */
147 struct ath_11n_rc_stats n_rcstats[16]; /* 0..15 MCS rates */
148};
149
150struct ath9k_debug {
151 int debug_mask;
152 struct dentry *debugfs_root;
153 struct dentry *debugfs_phy;
154 struct dentry *debugfs_dma;
155 struct dentry *debugfs_interrupt;
156 struct dentry *debugfs_rcstat;
157 struct ath_stats stats;
158};
159
160void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
161int ath9k_init_debug(struct ath_softc *sc);
162void ath9k_exit_debug(struct ath_softc *sc);
163void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
164void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb);
165void ath_debug_stat_retries(struct ath_softc *sc, int rix,
166 int xretries, int retries);
167
168#else
169
170static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
171 const char *fmt, ...)
172{
173}
174
175static inline int ath9k_init_debug(struct ath_softc *sc)
176{
177 return 0;
178}
179
180static inline void ath9k_exit_debug(struct ath_softc *sc)
181{
182}
183
184static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
185 enum ath9k_int status)
186{
187}
188
189static inline void ath_debug_stat_rc(struct ath_softc *sc,
190 struct sk_buff *skb)
191{
192}
193
194static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
195 int xretries, int retries)
196{
197}
198
199#endif /* CONFIG_ATH9K_DEBUG */
200
201struct ath_config {
202 u32 ath_aggr_prot;
203 u16 txpowlimit;
204 u8 cabqReadytime;
205 u8 swBeaconProcess;
206};
207
208/*************************/
209/* Descriptor Management */
210/*************************/
211
212#define ATH_TXBUF_RESET(_bf) do { \
213 (_bf)->bf_status = 0; \
214 (_bf)->bf_lastbf = NULL; \
215 (_bf)->bf_next = NULL; \
216 memset(&((_bf)->bf_state), 0, \
217 sizeof(struct ath_buf_state)); \
218 } while (0)
219
220/**
221 * enum buffer_type - Buffer type flags
222 *
223 * @BUF_HT: Send this buffer using HT capabilities
224 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
225 * @BUF_AGGR: Indicates whether the buffer can be aggregated
226 * (used in aggregation scheduling)
227 * @BUF_RETRY: Indicates whether the buffer is retried
228 * @BUF_XRETRY: To denote excessive retries of the buffer
229 */
230enum buffer_type {
231 BUF_HT = BIT(1),
232 BUF_AMPDU = BIT(2),
233 BUF_AGGR = BIT(3),
234 BUF_RETRY = BIT(4),
235 BUF_XRETRY = BIT(5),
236};
237
238struct ath_buf_state {
239 int bfs_nframes; /* # frames in aggregate */
240 u16 bfs_al; /* length of aggregate */
241 u16 bfs_frmlen; /* length of frame */
242 int bfs_seqno; /* sequence number */
243 int bfs_tidno; /* tid of this frame */
244 int bfs_retries; /* current retries */
245 u32 bf_type; /* BUF_* (enum buffer_type) */
246 u32 bfs_keyix;
247 enum ath9k_key_type bfs_keytype;
248};
249
250#define bf_nframes bf_state.bfs_nframes
251#define bf_al bf_state.bfs_al
252#define bf_frmlen bf_state.bfs_frmlen
253#define bf_retries bf_state.bfs_retries
254#define bf_seqno bf_state.bfs_seqno
255#define bf_tidno bf_state.bfs_tidno
256#define bf_keyix bf_state.bfs_keyix
257#define bf_keytype bf_state.bfs_keytype
258#define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
259#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
260#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
261#define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
262#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
263
264/*
265 * Abstraction of a contiguous buffer to transmit/receive. There is only
266 * a single hw descriptor encapsulated here.
267 */
268struct ath_buf {
269 struct list_head list;
270 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
271 an aggregate) */
272 struct ath_buf *bf_next; /* next subframe in the aggregate */
273 void *bf_mpdu; /* enclosing frame structure */
274 struct ath_desc *bf_desc; /* virtual addr of desc */
275 dma_addr_t bf_daddr; /* physical addr of desc */
276 dma_addr_t bf_buf_addr; /* physical addr of data buffer */
277 u32 bf_status;
278 u16 bf_flags; /* tx descriptor flags */
279 struct ath_buf_state bf_state; /* buffer state */
280 dma_addr_t bf_dmacontext;
281};
282
283#define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
284#define ATH_BUFSTATUS_STALE 0x00000002
285
286/* DMA state for tx/rx descriptors */
287
288struct ath_descdma {
289 const char *dd_name;
290 struct ath_desc *dd_desc; /* descriptors */
291 dma_addr_t dd_desc_paddr; /* physical addr of dd_desc */
292 u32 dd_desc_len; /* size of dd_desc */
293 struct ath_buf *dd_bufptr; /* associated buffers */
294 dma_addr_t dd_dmacontext;
295};
296
297int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
298 struct list_head *head, const char *name,
299 int nbuf, int ndesc);
300void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
301 struct list_head *head);
302
303/***********/
304/* RX / TX */
305/***********/
306
307#define ATH_MAX_ANTENNA 3
308#define ATH_RXBUF 512
309#define WME_NUM_TID 16
310#define ATH_TXBUF 512
311#define ATH_TXMAXTRY 13
312#define ATH_11N_TXMAXTRY 10
313#define ATH_MGT_TXMAXTRY 4
314#define WME_BA_BMP_SIZE 64
315#define WME_MAX_BA WME_BA_BMP_SIZE
316#define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
317
318#define TID_TO_WME_AC(_tid) \
319 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
320 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
321 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
322 WME_AC_VO)
323
324#define WME_AC_BE 0
325#define WME_AC_BK 1
326#define WME_AC_VI 2
327#define WME_AC_VO 3
328#define WME_NUM_AC 4
329
330#define ADDBA_EXCHANGE_ATTEMPTS 10
331#define ATH_AGGR_DELIM_SZ 4
332#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
333/* number of delimiters for encryption padding */
334#define ATH_AGGR_ENCRYPTDELIM 10
335/* minimum h/w qdepth to be sustained to maximize aggregation */
336#define ATH_AGGR_MIN_QDEPTH 2
337#define ATH_AMPDU_SUBFRAME_DEFAULT 32
338#define IEEE80211_SEQ_SEQ_SHIFT 4
339#define IEEE80211_SEQ_MAX 4096
340#define IEEE80211_MIN_AMPDU_BUF 0x8
341#define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
342
343/* return whether a bit at index _n in bitmap _bm is set
344 * _sz is the size of the bitmap */
345#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
346 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
347
348/* return block-ack bitmap index given sequence and starting sequence */
349#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
350
351/* returns delimiter padding required given the packet length */
352#define ATH_AGGR_GET_NDELIM(_len) \
353 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
354 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
355
356#define BAW_WITHIN(_start, _bawsz, _seqno) \
357 ((((_seqno) - (_start)) & 4095) < (_bawsz))
358
359#define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
360#define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
361#define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
362#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
363
364enum ATH_AGGR_STATUS {
365 ATH_AGGR_DONE,
366 ATH_AGGR_BAW_CLOSED,
367 ATH_AGGR_LIMITED,
368};
369
370struct ath_txq {
371 u32 axq_qnum; /* hardware q number */
372 u32 *axq_link; /* link ptr in last TX desc */
373 struct list_head axq_q; /* transmit queue */
374 spinlock_t axq_lock;
375 u32 axq_depth; /* queue depth */
376 u8 axq_aggr_depth; /* aggregates queued */
377 u32 axq_totalqueued; /* total ever queued */
378 bool stopped; /* Is mac80211 queue stopped ? */
379 struct ath_buf *axq_linkbuf; /* virtual addr of last buffer*/
380
381 /* first desc of the last descriptor that contains CTS */
382 struct ath_desc *axq_lastdsWithCTS;
383
384 /* final desc of the gating desc that determines whether
385 lastdsWithCTS has been DMA'ed or not */
386 struct ath_desc *axq_gatingds;
387
388 struct list_head axq_acq;
389};
390
391#define AGGR_CLEANUP BIT(1)
392#define AGGR_ADDBA_COMPLETE BIT(2)
393#define AGGR_ADDBA_PROGRESS BIT(3)
394
395/* per TID aggregate tx state for a destination */
396struct ath_atx_tid {
397 struct list_head list; /* round-robin tid entry */
398 struct list_head buf_q; /* pending buffers */
399 struct ath_node *an;
400 struct ath_atx_ac *ac;
401 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS]; /* active tx frames */
402 u16 seq_start;
403 u16 seq_next;
404 u16 baw_size;
405 int tidno;
406 int baw_head; /* first un-acked tx buffer */
407 int baw_tail; /* next unused tx buffer slot */
408 int sched;
409 int paused;
410 u8 state;
411 int addba_exchangeattempts;
412};
413
414/* per access-category aggregate tx state for a destination */
415struct ath_atx_ac {
416 int sched; /* dest-ac is scheduled */
417 int qnum; /* H/W queue number associated
418 with this AC */
419 struct list_head list; /* round-robin txq entry */
420 struct list_head tid_q; /* queue of TIDs with buffers */
421};
422
423/* per-frame tx control block */
424struct ath_tx_control {
425 struct ath_txq *txq;
426 int if_id;
427};
428
429/* per frame tx status block */
430struct ath_xmit_status {
431 int retries; /* number of retries to successufully
432 transmit this frame */
433 int flags; /* status of transmit */
434#define ATH_TX_ERROR 0x01
435#define ATH_TX_XRETRY 0x02
436#define ATH_TX_BAR 0x04
437};
438
439/* All RSSI values are noise floor adjusted */
440struct ath_tx_stat {
441 int rssi;
442 int rssictl[ATH_MAX_ANTENNA];
443 int rssiextn[ATH_MAX_ANTENNA];
444 int rateieee;
445 int rateKbps;
446 int ratecode;
447 int flags;
448 u32 airtime; /* time on air per final tx rate */
449};
450
451struct aggr_rifs_param {
452 int param_max_frames;
453 int param_max_len;
454 int param_rl;
455 int param_al;
456 struct ath_rc_series *param_rcs;
457};
458
459struct ath_node {
460 struct ath_softc *an_sc;
461 struct ath_atx_tid tid[WME_NUM_TID];
462 struct ath_atx_ac ac[WME_NUM_AC];
463 u16 maxampdu;
464 u8 mpdudensity;
465};
466
467struct ath_tx {
468 u16 seq_no;
469 u32 txqsetup;
470 int hwq_map[ATH9K_WME_AC_VO+1];
471 spinlock_t txbuflock;
472 struct list_head txbuf;
473 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
474 struct ath_descdma txdma;
475};
476
477struct ath_rx {
478 u8 defant;
479 u8 rxotherant;
480 u32 *rxlink;
481 int bufsize;
482 unsigned int rxfilter;
483 spinlock_t rxflushlock;
484 spinlock_t rxbuflock;
485 struct list_head rxbuf;
486 struct ath_descdma rxdma;
487};
488
489int ath_startrecv(struct ath_softc *sc);
490bool ath_stoprecv(struct ath_softc *sc);
491void ath_flushrecv(struct ath_softc *sc);
492u32 ath_calcrxfilter(struct ath_softc *sc);
493int ath_rx_init(struct ath_softc *sc, int nbufs);
494void ath_rx_cleanup(struct ath_softc *sc);
495int ath_rx_tasklet(struct ath_softc *sc, int flush);
496struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
497void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
498int ath_tx_setup(struct ath_softc *sc, int haltype);
499void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
500void ath_draintxq(struct ath_softc *sc,
501 struct ath_txq *txq, bool retry_tx);
502void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
503void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
504void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
505int ath_tx_init(struct ath_softc *sc, int nbufs);
506int ath_tx_cleanup(struct ath_softc *sc);
507struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb);
508int ath_txq_update(struct ath_softc *sc, int qnum,
509 struct ath9k_tx_queue_info *q);
510int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
511 struct ath_tx_control *txctl);
512void ath_tx_tasklet(struct ath_softc *sc);
513void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb);
514bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno);
515int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
516 u16 tid, u16 *ssn);
517int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
518void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
519
520/********/
521/* VAPs */
522/********/
523
524/*
525 * Define the scheme that we select MAC address for multiple
526 * BSS on the same radio. The very first VAP will just use the MAC
527 * address from the EEPROM. For the next 3 VAPs, we set the
528 * U/L bit (bit 1) in MAC address, and use the next two bits as the
529 * index of the VAP.
530 */
531
532#define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
533 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
534
535struct ath_vap {
536 int av_bslot;
537 enum nl80211_iftype av_opmode;
538 struct ath_buf *av_bcbuf;
539 struct ath_tx_control av_btxctl;
540};
541
542/*******************/
543/* Beacon Handling */
544/*******************/
545
546/*
547 * Regardless of the number of beacons we stagger, (i.e. regardless of the
548 * number of BSSIDs) if a given beacon does not go out even after waiting this
549 * number of beacon intervals, the game's up.
550 */
551#define BSTUCK_THRESH (9 * ATH_BCBUF)
552#define ATH_BCBUF 1
553#define ATH_DEFAULT_BINTVAL 100 /* TU */
554#define ATH_DEFAULT_BMISS_LIMIT 10
555#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
556
557struct ath_beacon_config {
558 u16 beacon_interval;
559 u16 listen_interval;
560 u16 dtim_period;
561 u16 bmiss_timeout;
562 u8 dtim_count;
563 u8 tim_offset;
564 union {
565 u64 last_tsf;
566 u8 last_tstamp[8];
567 } u; /* last received beacon/probe response timestamp of this BSS. */
568};
569
570struct ath_beacon {
571 enum {
572 OK, /* no change needed */
573 UPDATE, /* update pending */
574 COMMIT /* beacon sent, commit change */
575 } updateslot; /* slot time update fsm */
576
577 u32 beaconq;
578 u32 bmisscnt;
579 u32 ast_be_xmit;
580 u64 bc_tstamp;
581 int bslot[ATH_BCBUF];
582 int slottime;
583 int slotupdate;
584 struct ath9k_tx_queue_info beacon_qi;
585 struct ath_descdma bdma;
586 struct ath_txq *cabq;
587 struct list_head bbuf;
588};
589
590void ath9k_beacon_tasklet(unsigned long data);
591void ath_beacon_config(struct ath_softc *sc, int if_id);
592int ath_beaconq_setup(struct ath_hal *ah);
593int ath_beacon_alloc(struct ath_softc *sc, int if_id);
594void ath_beacon_return(struct ath_softc *sc, struct ath_vap *avp);
595void ath_beacon_sync(struct ath_softc *sc, int if_id);
596
597/*******/
598/* ANI */
599/*******/
600
601/* ANI values for STA only.
602 FIXME: Add appropriate values for AP later */
603
604#define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
605#define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
606#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
607#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
608
609struct ath_ani {
610 bool sc_caldone;
611 int16_t sc_noise_floor;
612 unsigned int sc_longcal_timer;
613 unsigned int sc_shortcal_timer;
614 unsigned int sc_resetcal_timer;
615 unsigned int sc_checkani_timer;
616 struct timer_list timer;
617};
618
619/********************/
620/* LED Control */
621/********************/
622
623#define ATH_LED_PIN 1
624#define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
625#define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
626
627enum ath_led_type {
628 ATH_LED_RADIO,
629 ATH_LED_ASSOC,
630 ATH_LED_TX,
631 ATH_LED_RX
632};
633
634struct ath_led {
635 struct ath_softc *sc;
636 struct led_classdev led_cdev;
637 enum ath_led_type led_type;
638 char name[32];
639 bool registered;
640};
641
642/* Rfkill */
643#define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
644
645struct ath_rfkill {
646 struct rfkill *rfkill;
647 struct delayed_work rfkill_poll;
648 char rfkill_name[32];
649};
650
651/********************/
652/* Main driver core */
653/********************/
654
655/*
656 * Default cache line size, in bytes.
657 * Used when PCI device not fully initialized by bootrom/BIOS
658*/
659#define DEFAULT_CACHELINE 32
660#define ATH_DEFAULT_NOISE_FLOOR -95
661#define ATH_REGCLASSIDS_MAX 10
662#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
663#define ATH_MAX_SW_RETRIES 10
664#define ATH_CHAN_MAX 255
665#define IEEE80211_WEP_NKID 4 /* number of key ids */
666
667/*
668 * The key cache is used for h/w cipher state and also for
669 * tracking station state such as the current tx antenna.
670 * We also setup a mapping table between key cache slot indices
671 * and station state to short-circuit node lookups on rx.
672 * Different parts have different size key caches. We handle
673 * up to ATH_KEYMAX entries (could dynamically allocate state).
674 */
675#define ATH_KEYMAX 128 /* max key cache size we handle */
676
677#define ATH_IF_ID_ANY 0xff
678#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
679#define ATH_RSSI_DUMMY_MARKER 0x127
680#define ATH_RATE_DUMMY_MARKER 0
681
682#define SC_OP_INVALID BIT(0)
683#define SC_OP_BEACONS BIT(1)
684#define SC_OP_RXAGGR BIT(2)
685#define SC_OP_TXAGGR BIT(3)
686#define SC_OP_CHAINMASK_UPDATE BIT(4)
687#define SC_OP_FULL_RESET BIT(5)
688#define SC_OP_NO_RESET BIT(6)
689#define SC_OP_PREAMBLE_SHORT BIT(7)
690#define SC_OP_PROTECT_ENABLE BIT(8)
691#define SC_OP_RXFLUSH BIT(9)
692#define SC_OP_LED_ASSOCIATED BIT(10)
693#define SC_OP_RFKILL_REGISTERED BIT(11)
694#define SC_OP_RFKILL_SW_BLOCKED BIT(12)
695#define SC_OP_RFKILL_HW_BLOCKED BIT(13)
696#define SC_OP_WAIT_FOR_BEACON BIT(14)
697#define SC_OP_LED_ON BIT(15)
698
699struct ath_bus_ops {
700 void (*read_cachesize)(struct ath_softc *sc, int *csz);
701 void (*cleanup)(struct ath_softc *sc);
702 bool (*eeprom_read)(struct ath_hal *ah, u32 off, u16 *data);
703};
704
705struct ath_softc {
706 struct ieee80211_hw *hw;
707 struct device *dev;
708 struct tasklet_struct intr_tq;
709 struct tasklet_struct bcon_tasklet;
710 struct ath_hal *sc_ah;
711 void __iomem *mem;
712 int irq;
713 spinlock_t sc_resetlock;
714 struct mutex mutex;
715
716 u8 sc_curbssid[ETH_ALEN];
717 u8 sc_myaddr[ETH_ALEN];
718 u8 sc_bssidmask[ETH_ALEN];
719 u32 sc_intrstatus;
720 u32 sc_flags; /* SC_OP_* */
721 u16 sc_curtxpow;
722 u16 sc_curaid;
723 u16 sc_cachelsz;
724 u8 sc_nbcnvaps;
725 u16 sc_nvaps;
726 u8 sc_tx_chainmask;
727 u8 sc_rx_chainmask;
728 u32 sc_keymax;
729 DECLARE_BITMAP(sc_keymap, ATH_KEYMAX);
730 u8 sc_splitmic;
731 atomic_t ps_usecount;
732 enum ath9k_int sc_imask;
733 enum ath9k_ht_extprotspacing sc_ht_extprotspacing;
734 enum ath9k_ht_macmode tx_chan_width;
735
736 struct ath_config sc_config;
737 struct ath_rx rx;
738 struct ath_tx tx;
739 struct ath_beacon beacon;
740 struct ieee80211_vif *sc_vaps[ATH_BCBUF];
741 struct ieee80211_rate rates[IEEE80211_NUM_BANDS][ATH_RATE_MAX];
742 struct ath_rate_table *hw_rate_table[ATH9K_MODE_MAX];
743 struct ath_rate_table *cur_rate_table;
744 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
745
746 struct ath_led radio_led;
747 struct ath_led assoc_led;
748 struct ath_led tx_led;
749 struct ath_led rx_led;
750 struct delayed_work ath_led_blink_work;
751 int led_on_duration;
752 int led_off_duration;
753 int led_on_cnt;
754 int led_off_cnt;
755
756 struct ath_rfkill rf_kill;
757 struct ath_ani sc_ani;
758 struct ath9k_node_stats sc_halstats;
759#ifdef CONFIG_ATH9K_DEBUG
760 struct ath9k_debug sc_debug;
761#endif
762 struct ath_bus_ops *bus_ops;
763};
764
765int ath_reset(struct ath_softc *sc, bool retry_tx);
766int ath_get_hal_qnum(u16 queue, struct ath_softc *sc);
767int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc);
768int ath_cabq_update(struct ath_softc *);
769
770static inline void ath_read_cachesize(struct ath_softc *sc, int *csz)
771{
772 sc->bus_ops->read_cachesize(sc, csz);
773}
774
775static inline void ath_bus_cleanup(struct ath_softc *sc)
776{
777 sc->bus_ops->cleanup(sc);
778}
779
780extern struct ieee80211_ops ath9k_ops;
781
782irqreturn_t ath_isr(int irq, void *dev);
783void ath_cleanup(struct ath_softc *sc);
784int ath_attach(u16 devid, struct ath_softc *sc);
785void ath_detach(struct ath_softc *sc);
786const char *ath_mac_bb_name(u32 mac_bb_version);
787const char *ath_rf_name(u16 rf_version);
788
789#ifdef CONFIG_PCI
790int ath_pci_init(void);
791void ath_pci_exit(void);
792#else
793static inline int ath_pci_init(void) { return 0; };
794static inline void ath_pci_exit(void) {};
795#endif
796
797#ifdef CONFIG_ATHEROS_AR71XX
798int ath_ahb_init(void);
799void ath_ahb_exit(void);
800#else
801static inline int ath_ahb_init(void) { return 0; };
802static inline void ath_ahb_exit(void) {};
803#endif
804
805static inline void ath9k_ps_wakeup(struct ath_softc *sc)
806{
807 if (atomic_inc_return(&sc->ps_usecount) == 1)
808 if (sc->sc_ah->ah_power_mode != ATH9K_PM_AWAKE) {
809 sc->sc_ah->ah_restore_mode = sc->sc_ah->ah_power_mode;
810 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
811 }
812}
813
814static inline void ath9k_ps_restore(struct ath_softc *sc)
815{
816 if (atomic_dec_and_test(&sc->ps_usecount))
817 if (sc->hw->conf.flags & IEEE80211_CONF_PS)
818 ath9k_hw_setpower(sc->sc_ah,
819 sc->sc_ah->ah_restore_mode);
820}
821#endif /* CORE_H */
diff --git a/drivers/net/wireless/ath9k/debug.c b/drivers/net/wireless/ath9k/debug.c
index 2de1b8a57b94..c9b47b351504 100644
--- a/drivers/net/wireless/ath9k/debug.c
+++ b/drivers/net/wireless/ath9k/debug.c
@@ -14,9 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "reg.h"
19#include "hw.h"
20 18
21static unsigned int ath9k_debug = DBG_DEFAULT; 19static unsigned int ath9k_debug = DBG_DEFAULT;
22module_param_named(debug, ath9k_debug, uint, 0); 20module_param_named(debug, ath9k_debug, uint, 0);
diff --git a/drivers/net/wireless/ath9k/debug.h b/drivers/net/wireless/ath9k/debug.h
new file mode 100644
index 000000000000..61e969894c0a
--- /dev/null
+++ b/drivers/net/wireless/ath9k/debug.h
@@ -0,0 +1,153 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef DEBUG_H
18#define DEBUG_H
19
20enum ATH_DEBUG {
21 ATH_DBG_RESET = 0x00000001,
22 ATH_DBG_REG_IO = 0x00000002,
23 ATH_DBG_QUEUE = 0x00000004,
24 ATH_DBG_EEPROM = 0x00000008,
25 ATH_DBG_CALIBRATE = 0x00000010,
26 ATH_DBG_CHANNEL = 0x00000020,
27 ATH_DBG_INTERRUPT = 0x00000040,
28 ATH_DBG_REGULATORY = 0x00000080,
29 ATH_DBG_ANI = 0x00000100,
30 ATH_DBG_POWER_MGMT = 0x00000200,
31 ATH_DBG_XMIT = 0x00000400,
32 ATH_DBG_BEACON = 0x00001000,
33 ATH_DBG_CONFIG = 0x00002000,
34 ATH_DBG_KEYCACHE = 0x00004000,
35 ATH_DBG_FATAL = 0x00008000,
36 ATH_DBG_ANY = 0xffffffff
37};
38
39#define DBG_DEFAULT (ATH_DBG_FATAL)
40
41#ifdef CONFIG_ATH9K_DEBUG
42
43/**
44 * struct ath_interrupt_stats - Contains statistics about interrupts
45 * @total: Total no. of interrupts generated so far
46 * @rxok: RX with no errors
47 * @rxeol: RX with no more RXDESC available
48 * @rxorn: RX FIFO overrun
49 * @txok: TX completed at the requested rate
50 * @txurn: TX FIFO underrun
51 * @mib: MIB regs reaching its threshold
52 * @rxphyerr: RX with phy errors
53 * @rx_keycache_miss: RX with key cache misses
54 * @swba: Software Beacon Alert
55 * @bmiss: Beacon Miss
56 * @bnr: Beacon Not Ready
57 * @cst: Carrier Sense TImeout
58 * @gtt: Global TX Timeout
59 * @tim: RX beacon TIM occurrence
60 * @cabend: RX End of CAB traffic
61 * @dtimsync: DTIM sync lossage
62 * @dtim: RX Beacon with DTIM
63 */
64struct ath_interrupt_stats {
65 u32 total;
66 u32 rxok;
67 u32 rxeol;
68 u32 rxorn;
69 u32 txok;
70 u32 txeol;
71 u32 txurn;
72 u32 mib;
73 u32 rxphyerr;
74 u32 rx_keycache_miss;
75 u32 swba;
76 u32 bmiss;
77 u32 bnr;
78 u32 cst;
79 u32 gtt;
80 u32 tim;
81 u32 cabend;
82 u32 dtimsync;
83 u32 dtim;
84};
85
86struct ath_legacy_rc_stats {
87 u32 success;
88};
89
90struct ath_11n_rc_stats {
91 u32 success;
92 u32 retries;
93 u32 xretries;
94};
95
96struct ath_stats {
97 struct ath_interrupt_stats istats;
98 struct ath_legacy_rc_stats legacy_rcstats[12]; /* max(11a,11b,11g) */
99 struct ath_11n_rc_stats n_rcstats[16]; /* 0..15 MCS rates */
100};
101
102struct ath9k_debug {
103 int debug_mask;
104 struct dentry *debugfs_root;
105 struct dentry *debugfs_phy;
106 struct dentry *debugfs_dma;
107 struct dentry *debugfs_interrupt;
108 struct dentry *debugfs_rcstat;
109 struct ath_stats stats;
110};
111
112void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...);
113int ath9k_init_debug(struct ath_softc *sc);
114void ath9k_exit_debug(struct ath_softc *sc);
115void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
116void ath_debug_stat_rc(struct ath_softc *sc, struct sk_buff *skb);
117void ath_debug_stat_retries(struct ath_softc *sc, int rix,
118 int xretries, int retries);
119
120#else
121
122static inline void DPRINTF(struct ath_softc *sc, int dbg_mask,
123 const char *fmt, ...)
124{
125}
126
127static inline int ath9k_init_debug(struct ath_softc *sc)
128{
129 return 0;
130}
131
132static inline void ath9k_exit_debug(struct ath_softc *sc)
133{
134}
135
136static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
137 enum ath9k_int status)
138{
139}
140
141static inline void ath_debug_stat_rc(struct ath_softc *sc,
142 struct sk_buff *skb)
143{
144}
145
146static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
147 int xretries, int retries)
148{
149}
150
151#endif /* CONFIG_ATH9K_DEBUG */
152
153#endif /* DEBUG_H */
diff --git a/drivers/net/wireless/ath9k/eeprom.c b/drivers/net/wireless/ath9k/eeprom.c
index 5038907e7432..aa624099a623 100644
--- a/drivers/net/wireless/ath9k/eeprom.c
+++ b/drivers/net/wireless/ath9k/eeprom.c
@@ -14,10 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah, 19static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
23 u32 reg, u32 mask, 20 u32 reg, u32 mask,
diff --git a/drivers/net/wireless/ath9k/eeprom.h b/drivers/net/wireless/ath9k/eeprom.h
new file mode 100644
index 000000000000..9eb777465144
--- /dev/null
+++ b/drivers/net/wireless/ath9k/eeprom.h
@@ -0,0 +1,484 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef EEPROM_H
18#define EEPROM_H
19
20#define AH_USE_EEPROM 0x1
21
22#ifdef __BIG_ENDIAN
23#define AR5416_EEPROM_MAGIC 0x5aa5
24#else
25#define AR5416_EEPROM_MAGIC 0xa55a
26#endif
27
28#define CTRY_DEBUG 0x1ff
29#define CTRY_DEFAULT 0
30
31#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
32#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
33#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
34#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
35#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
36#define AR_EEPROM_EEPCAP_MAXQCU_S 4
37#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
38#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
39#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
40
41#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
42#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
43#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
44#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
45#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
46#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
47
48#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
49#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
50
51#define AR5416_EEPROM_MAGIC_OFFSET 0x0
52#define AR5416_EEPROM_S 2
53#define AR5416_EEPROM_OFFSET 0x2000
54#define AR5416_EEPROM_MAX 0xae0
55
56#define AR5416_EEPROM_START_ADDR \
57 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
58
59#define SD_NO_CTL 0xE0
60#define NO_CTL 0xff
61#define CTL_MODE_M 7
62#define CTL_11A 0
63#define CTL_11B 1
64#define CTL_11G 2
65#define CTL_2GHT20 5
66#define CTL_5GHT20 6
67#define CTL_2GHT40 7
68#define CTL_5GHT40 8
69
70#define EXT_ADDITIVE (0x8000)
71#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
72#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
73#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
74
75#define SUB_NUM_CTL_MODES_AT_5G_40 2
76#define SUB_NUM_CTL_MODES_AT_2G_40 3
77
78#define AR_EEPROM_MAC(i) (0x1d+(i))
79#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
80#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
81#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
82
83#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
84#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
85#define AR_EEPROM_RFSILENT_POLARITY 0x0002
86#define AR_EEPROM_RFSILENT_POLARITY_S 1
87
88#define EEP_RFSILENT_ENABLED 0x0001
89#define EEP_RFSILENT_ENABLED_S 0
90#define EEP_RFSILENT_POLARITY 0x0002
91#define EEP_RFSILENT_POLARITY_S 1
92#define EEP_RFSILENT_GPIO_SEL 0x001c
93#define EEP_RFSILENT_GPIO_SEL_S 2
94
95#define AR5416_OPFLAGS_11A 0x01
96#define AR5416_OPFLAGS_11G 0x02
97#define AR5416_OPFLAGS_N_5G_HT40 0x04
98#define AR5416_OPFLAGS_N_2G_HT40 0x08
99#define AR5416_OPFLAGS_N_5G_HT20 0x10
100#define AR5416_OPFLAGS_N_2G_HT20 0x20
101
102#define AR5416_EEP_NO_BACK_VER 0x1
103#define AR5416_EEP_VER 0xE
104#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
105#define AR5416_EEP_MINOR_VER_2 0x2
106#define AR5416_EEP_MINOR_VER_3 0x3
107#define AR5416_EEP_MINOR_VER_7 0x7
108#define AR5416_EEP_MINOR_VER_9 0x9
109#define AR5416_EEP_MINOR_VER_16 0x10
110#define AR5416_EEP_MINOR_VER_17 0x11
111#define AR5416_EEP_MINOR_VER_19 0x13
112#define AR5416_EEP_MINOR_VER_20 0x14
113
114#define AR5416_NUM_5G_CAL_PIERS 8
115#define AR5416_NUM_2G_CAL_PIERS 4
116#define AR5416_NUM_5G_20_TARGET_POWERS 8
117#define AR5416_NUM_5G_40_TARGET_POWERS 8
118#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
119#define AR5416_NUM_2G_20_TARGET_POWERS 4
120#define AR5416_NUM_2G_40_TARGET_POWERS 4
121#define AR5416_NUM_CTLS 24
122#define AR5416_NUM_BAND_EDGES 8
123#define AR5416_NUM_PD_GAINS 4
124#define AR5416_PD_GAINS_IN_MASK 4
125#define AR5416_PD_GAIN_ICEPTS 5
126#define AR5416_EEPROM_MODAL_SPURS 5
127#define AR5416_MAX_RATE_POWER 63
128#define AR5416_NUM_PDADC_VALUES 128
129#define AR5416_BCHAN_UNUSED 0xFF
130#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
131#define AR5416_MAX_CHAINS 3
132#define AR5416_PWR_TABLE_OFFSET -5
133
134/* Rx gain type values */
135#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
136#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
137#define AR5416_EEP_RXGAIN_ORIG 2
138
139/* Tx gain type values */
140#define AR5416_EEP_TXGAIN_ORIGINAL 0
141#define AR5416_EEP_TXGAIN_HIGH_POWER 1
142
143#define AR5416_EEP4K_START_LOC 64
144#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
145#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
146#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
147#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
148#define AR5416_EEP4K_NUM_CTLS 12
149#define AR5416_EEP4K_NUM_BAND_EDGES 4
150#define AR5416_EEP4K_NUM_PD_GAINS 2
151#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
152#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
153#define AR5416_EEP4K_MAX_CHAINS 1
154
155enum eeprom_param {
156 EEP_NFTHRESH_5,
157 EEP_NFTHRESH_2,
158 EEP_MAC_MSW,
159 EEP_MAC_MID,
160 EEP_MAC_LSW,
161 EEP_REG_0,
162 EEP_REG_1,
163 EEP_OP_CAP,
164 EEP_OP_MODE,
165 EEP_RF_SILENT,
166 EEP_OB_5,
167 EEP_DB_5,
168 EEP_OB_2,
169 EEP_DB_2,
170 EEP_MINOR_REV,
171 EEP_TX_MASK,
172 EEP_RX_MASK,
173 EEP_RXGAIN_TYPE,
174 EEP_TXGAIN_TYPE,
175 EEP_DAC_HPWR_5G,
176};
177
178enum ar5416_rates {
179 rate6mb, rate9mb, rate12mb, rate18mb,
180 rate24mb, rate36mb, rate48mb, rate54mb,
181 rate1l, rate2l, rate2s, rate5_5l,
182 rate5_5s, rate11l, rate11s, rateXr,
183 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
184 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
185 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
186 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
187 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
188 Ar5416RateSize
189};
190
191enum ath9k_hal_freq_band {
192 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
193 ATH9K_HAL_FREQ_BAND_2GHZ = 1
194};
195
196struct base_eep_header {
197 u16 length;
198 u16 checksum;
199 u16 version;
200 u8 opCapFlags;
201 u8 eepMisc;
202 u16 regDmn[2];
203 u8 macAddr[6];
204 u8 rxMask;
205 u8 txMask;
206 u16 rfSilent;
207 u16 blueToothOptions;
208 u16 deviceCap;
209 u32 binBuildNumber;
210 u8 deviceType;
211 u8 pwdclkind;
212 u8 futureBase_1[2];
213 u8 rxGainType;
214 u8 dacHiPwrMode_5G;
215 u8 futureBase_2;
216 u8 dacLpMode;
217 u8 txGainType;
218 u8 rcChainMask;
219 u8 desiredScaleCCK;
220 u8 futureBase_3[23];
221} __packed;
222
223struct base_eep_header_4k {
224 u16 length;
225 u16 checksum;
226 u16 version;
227 u8 opCapFlags;
228 u8 eepMisc;
229 u16 regDmn[2];
230 u8 macAddr[6];
231 u8 rxMask;
232 u8 txMask;
233 u16 rfSilent;
234 u16 blueToothOptions;
235 u16 deviceCap;
236 u32 binBuildNumber;
237 u8 deviceType;
238 u8 futureBase[1];
239} __packed;
240
241
242struct spur_chan {
243 u16 spurChan;
244 u8 spurRangeLow;
245 u8 spurRangeHigh;
246} __packed;
247
248struct modal_eep_header {
249 u32 antCtrlChain[AR5416_MAX_CHAINS];
250 u32 antCtrlCommon;
251 u8 antennaGainCh[AR5416_MAX_CHAINS];
252 u8 switchSettling;
253 u8 txRxAttenCh[AR5416_MAX_CHAINS];
254 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
255 u8 adcDesiredSize;
256 u8 pgaDesiredSize;
257 u8 xlnaGainCh[AR5416_MAX_CHAINS];
258 u8 txEndToXpaOff;
259 u8 txEndToRxOn;
260 u8 txFrameToXpaOn;
261 u8 thresh62;
262 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
263 u8 xpdGain;
264 u8 xpd;
265 u8 iqCalICh[AR5416_MAX_CHAINS];
266 u8 iqCalQCh[AR5416_MAX_CHAINS];
267 u8 pdGainOverlap;
268 u8 ob;
269 u8 db;
270 u8 xpaBiasLvl;
271 u8 pwrDecreaseFor2Chain;
272 u8 pwrDecreaseFor3Chain;
273 u8 txFrameToDataStart;
274 u8 txFrameToPaOn;
275 u8 ht40PowerIncForPdadc;
276 u8 bswAtten[AR5416_MAX_CHAINS];
277 u8 bswMargin[AR5416_MAX_CHAINS];
278 u8 swSettleHt40;
279 u8 xatten2Db[AR5416_MAX_CHAINS];
280 u8 xatten2Margin[AR5416_MAX_CHAINS];
281 u8 ob_ch1;
282 u8 db_ch1;
283 u8 useAnt1:1,
284 force_xpaon:1,
285 local_bias:1,
286 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
287 u8 miscBits;
288 u16 xpaBiasLvlFreq[3];
289 u8 futureModal[6];
290
291 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
292} __packed;
293
294struct modal_eep_4k_header {
295 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
296 u32 antCtrlCommon;
297 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
298 u8 switchSettling;
299 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
300 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
301 u8 adcDesiredSize;
302 u8 pgaDesiredSize;
303 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
304 u8 txEndToXpaOff;
305 u8 txEndToRxOn;
306 u8 txFrameToXpaOn;
307 u8 thresh62;
308 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
309 u8 xpdGain;
310 u8 xpd;
311 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
312 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
313 u8 pdGainOverlap;
314 u8 ob_01;
315 u8 db1_01;
316 u8 xpaBiasLvl;
317 u8 txFrameToDataStart;
318 u8 txFrameToPaOn;
319 u8 ht40PowerIncForPdadc;
320 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
321 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
322 u8 swSettleHt40;
323 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
324 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
325 u8 db2_01;
326 u8 version;
327 u16 ob_234;
328 u16 db1_234;
329 u16 db2_234;
330 u8 futureModal[4];
331
332 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
333} __packed;
334
335
336struct cal_data_per_freq {
337 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
338 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
339} __packed;
340
341struct cal_data_per_freq_4k {
342 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
343 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
344} __packed;
345
346struct cal_target_power_leg {
347 u8 bChannel;
348 u8 tPow2x[4];
349} __packed;
350
351struct cal_target_power_ht {
352 u8 bChannel;
353 u8 tPow2x[8];
354} __packed;
355
356
357#ifdef __BIG_ENDIAN_BITFIELD
358struct cal_ctl_edges {
359 u8 bChannel;
360 u8 flag:2, tPower:6;
361} __packed;
362#else
363struct cal_ctl_edges {
364 u8 bChannel;
365 u8 tPower:6, flag:2;
366} __packed;
367#endif
368
369struct cal_ctl_data {
370 struct cal_ctl_edges
371 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
372} __packed;
373
374struct cal_ctl_data_4k {
375 struct cal_ctl_edges
376 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
377} __packed;
378
379struct ar5416_eeprom_def {
380 struct base_eep_header baseEepHeader;
381 u8 custData[64];
382 struct modal_eep_header modalHeader[2];
383 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
384 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
385 struct cal_data_per_freq
386 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
387 struct cal_data_per_freq
388 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
389 struct cal_target_power_leg
390 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
391 struct cal_target_power_ht
392 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
393 struct cal_target_power_ht
394 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
395 struct cal_target_power_leg
396 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
397 struct cal_target_power_leg
398 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
399 struct cal_target_power_ht
400 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
401 struct cal_target_power_ht
402 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
403 u8 ctlIndex[AR5416_NUM_CTLS];
404 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
405 u8 padding;
406} __packed;
407
408struct ar5416_eeprom_4k {
409 struct base_eep_header_4k baseEepHeader;
410 u8 custData[20];
411 struct modal_eep_4k_header modalHeader;
412 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
413 struct cal_data_per_freq_4k
414 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
415 struct cal_target_power_leg
416 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
417 struct cal_target_power_leg
418 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
419 struct cal_target_power_ht
420 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
421 struct cal_target_power_ht
422 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
423 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
424 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
425 u8 padding;
426} __packed;
427
428enum reg_ext_bitmap {
429 REG_EXT_JAPAN_MIDBAND = 1,
430 REG_EXT_FCC_DFS_HT40 = 2,
431 REG_EXT_JAPAN_NONDFS_HT40 = 3,
432 REG_EXT_JAPAN_DFS_HT40 = 4
433};
434
435struct ath9k_country_entry {
436 u16 countryCode;
437 u16 regDmnEnum;
438 u16 regDmn5G;
439 u16 regDmn2G;
440 u8 isMultidomain;
441 u8 iso[3];
442};
443
444enum hal_eep_map {
445 EEP_MAP_DEFAULT = 0x0,
446 EEP_MAP_4KBITS,
447 EEP_MAP_MAX
448};
449
450#define ar5416_get_eep_ver(_ahp) \
451 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
452#define ar5416_get_eep_rev(_ahp) \
453 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
454#define ar5416_get_ntxchains(_txchainmask) \
455 (((_txchainmask >> 2) & 1) + \
456 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
457
458#define ar5416_get_eep4k_ver(_ahp) \
459 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
460#define ar5416_get_eep4k_rev(_ahp) \
461 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
462
463int ath9k_hw_set_txpower(struct ath_hal *ah, struct ath9k_channel *chan,
464 u16 cfgCtl, u8 twiceAntennaReduction,
465 u8 twiceMaxRegulatoryPower, u8 powerLimit);
466void ath9k_hw_set_addac(struct ath_hal *ah, struct ath9k_channel *chan);
467bool ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
468 struct ath9k_channel *chan, int16_t *ratesArray,
469 u16 cfgCtl, u8 AntennaReduction,
470 u8 twiceMaxRegulatoryPower, u8 powerLimit);
471bool ath9k_hw_set_power_cal_table(struct ath_hal *ah,
472 struct ath9k_channel *chan,
473 int16_t *pTxPowerIndexOffset);
474bool ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
475 struct ath9k_channel *chan);
476u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal *ah,
477 struct ath9k_channel *chan);
478u8 ath9k_hw_get_num_ant_config(struct ath_hal *ah,
479 enum ieee80211_band freq_band);
480u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah, u16 i, bool is2GHz);
481u32 ath9k_hw_get_eeprom(struct ath_hal *ah, enum eeprom_param param);
482int ath9k_hw_eeprom_attach(struct ath_hal *ah);
483
484#endif /* EEPROM_H */
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c
index 00ed44a0c313..075ddc522c98 100644
--- a/drivers/net/wireless/ath9k/hw.c
+++ b/drivers/net/wireless/ath9k/hw.c
@@ -17,10 +17,7 @@
17#include <linux/io.h> 17#include <linux/io.h>
18#include <asm/unaligned.h> 18#include <asm/unaligned.h>
19 19
20#include "core.h" 20#include "ath9k.h"
21#include "hw.h"
22#include "reg.h"
23#include "phy.h"
24#include "initvals.h" 21#include "initvals.h"
25 22
26static int btcoex_enable; 23static int btcoex_enable;
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h
index 087c5718707b..2b72e75a1989 100644
--- a/drivers/net/wireless/ath9k/hw.h
+++ b/drivers/net/wireless/ath9k/hw.h
@@ -19,337 +19,392 @@
19 19
20#include <linux/if_ether.h> 20#include <linux/if_ether.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
28#include "regd.h"
29#include "reg.h"
30#include "phy.h"
31
32#define ATHEROS_VENDOR_ID 0x168c
33#define AR5416_DEVID_PCI 0x0023
34#define AR5416_DEVID_PCIE 0x0024
35#define AR9160_DEVID_PCI 0x0027
36#define AR9280_DEVID_PCI 0x0029
37#define AR9280_DEVID_PCIE 0x002a
38#define AR9285_DEVID_PCIE 0x002b
39#define AR5416_AR9100_DEVID 0x000b
40#define AR_SUBVENDOR_ID_NOG 0x0e11
41#define AR_SUBVENDOR_ID_NEW_A 0x7065
42#define AR5416_MAGIC 0x19641014
43
44/* Register read/write primitives */
45#define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
46#define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
47
48#define SM(_v, _f) (((_v) << _f##_S) & _f)
49#define MS(_v, _f) (((_v) & _f) >> _f##_S)
50#define REG_RMW(_a, _r, _set, _clr) \
51 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
52#define REG_RMW_FIELD(_a, _r, _f, _v) \
53 REG_WRITE(_a, _r, \
54 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
55#define REG_SET_BIT(_a, _r, _f) \
56 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
57#define REG_CLR_BIT(_a, _r, _f) \
58 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
22 59
23extern const struct hal_percal_data iq_cal_multi_sample; 60#define DO_DELAY(x) do { \
24extern const struct hal_percal_data iq_cal_single_sample; 61 if ((++(x) % 64) == 0) \
25extern const struct hal_percal_data adc_gain_cal_multi_sample; 62 udelay(1); \
26extern const struct hal_percal_data adc_gain_cal_single_sample; 63 } while (0)
27extern const struct hal_percal_data adc_dc_cal_multi_sample;
28extern const struct hal_percal_data adc_dc_cal_single_sample;
29extern const struct hal_percal_data adc_init_dc_cal;
30
31struct ar5416_desc {
32 u32 ds_link;
33 u32 ds_data;
34 u32 ds_ctl0;
35 u32 ds_ctl1;
36 union {
37 struct {
38 u32 ctl2;
39 u32 ctl3;
40 u32 ctl4;
41 u32 ctl5;
42 u32 ctl6;
43 u32 ctl7;
44 u32 ctl8;
45 u32 ctl9;
46 u32 ctl10;
47 u32 ctl11;
48 u32 status0;
49 u32 status1;
50 u32 status2;
51 u32 status3;
52 u32 status4;
53 u32 status5;
54 u32 status6;
55 u32 status7;
56 u32 status8;
57 u32 status9;
58 } tx;
59 struct {
60 u32 status0;
61 u32 status1;
62 u32 status2;
63 u32 status3;
64 u32 status4;
65 u32 status5;
66 u32 status6;
67 u32 status7;
68 u32 status8;
69 } rx;
70 } u;
71} __packed;
72
73#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
74#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
75
76#define ds_ctl2 u.tx.ctl2
77#define ds_ctl3 u.tx.ctl3
78#define ds_ctl4 u.tx.ctl4
79#define ds_ctl5 u.tx.ctl5
80#define ds_ctl6 u.tx.ctl6
81#define ds_ctl7 u.tx.ctl7
82#define ds_ctl8 u.tx.ctl8
83#define ds_ctl9 u.tx.ctl9
84#define ds_ctl10 u.tx.ctl10
85#define ds_ctl11 u.tx.ctl11
86
87#define ds_txstatus0 u.tx.status0
88#define ds_txstatus1 u.tx.status1
89#define ds_txstatus2 u.tx.status2
90#define ds_txstatus3 u.tx.status3
91#define ds_txstatus4 u.tx.status4
92#define ds_txstatus5 u.tx.status5
93#define ds_txstatus6 u.tx.status6
94#define ds_txstatus7 u.tx.status7
95#define ds_txstatus8 u.tx.status8
96#define ds_txstatus9 u.tx.status9
97
98#define ds_rxstatus0 u.rx.status0
99#define ds_rxstatus1 u.rx.status1
100#define ds_rxstatus2 u.rx.status2
101#define ds_rxstatus3 u.rx.status3
102#define ds_rxstatus4 u.rx.status4
103#define ds_rxstatus5 u.rx.status5
104#define ds_rxstatus6 u.rx.status6
105#define ds_rxstatus7 u.rx.status7
106#define ds_rxstatus8 u.rx.status8
107
108#define AR_FrameLen 0x00000fff
109#define AR_VirtMoreFrag 0x00001000
110#define AR_TxCtlRsvd00 0x0000e000
111#define AR_XmitPower 0x003f0000
112#define AR_XmitPower_S 16
113#define AR_RTSEnable 0x00400000
114#define AR_VEOL 0x00800000
115#define AR_ClrDestMask 0x01000000
116#define AR_TxCtlRsvd01 0x1e000000
117#define AR_TxIntrReq 0x20000000
118#define AR_DestIdxValid 0x40000000
119#define AR_CTSEnable 0x80000000
120
121#define AR_BufLen 0x00000fff
122#define AR_TxMore 0x00001000
123#define AR_DestIdx 0x000fe000
124#define AR_DestIdx_S 13
125#define AR_FrameType 0x00f00000
126#define AR_FrameType_S 20
127#define AR_NoAck 0x01000000
128#define AR_InsertTS 0x02000000
129#define AR_CorruptFCS 0x04000000
130#define AR_ExtOnly 0x08000000
131#define AR_ExtAndCtl 0x10000000
132#define AR_MoreAggr 0x20000000
133#define AR_IsAggr 0x40000000
134
135#define AR_BurstDur 0x00007fff
136#define AR_BurstDur_S 0
137#define AR_DurUpdateEna 0x00008000
138#define AR_XmitDataTries0 0x000f0000
139#define AR_XmitDataTries0_S 16
140#define AR_XmitDataTries1 0x00f00000
141#define AR_XmitDataTries1_S 20
142#define AR_XmitDataTries2 0x0f000000
143#define AR_XmitDataTries2_S 24
144#define AR_XmitDataTries3 0xf0000000
145#define AR_XmitDataTries3_S 28
146
147#define AR_XmitRate0 0x000000ff
148#define AR_XmitRate0_S 0
149#define AR_XmitRate1 0x0000ff00
150#define AR_XmitRate1_S 8
151#define AR_XmitRate2 0x00ff0000
152#define AR_XmitRate2_S 16
153#define AR_XmitRate3 0xff000000
154#define AR_XmitRate3_S 24
155
156#define AR_PacketDur0 0x00007fff
157#define AR_PacketDur0_S 0
158#define AR_RTSCTSQual0 0x00008000
159#define AR_PacketDur1 0x7fff0000
160#define AR_PacketDur1_S 16
161#define AR_RTSCTSQual1 0x80000000
162
163#define AR_PacketDur2 0x00007fff
164#define AR_PacketDur2_S 0
165#define AR_RTSCTSQual2 0x00008000
166#define AR_PacketDur3 0x7fff0000
167#define AR_PacketDur3_S 16
168#define AR_RTSCTSQual3 0x80000000
169
170#define AR_AggrLen 0x0000ffff
171#define AR_AggrLen_S 0
172#define AR_TxCtlRsvd60 0x00030000
173#define AR_PadDelim 0x03fc0000
174#define AR_PadDelim_S 18
175#define AR_EncrType 0x0c000000
176#define AR_EncrType_S 26
177#define AR_TxCtlRsvd61 0xf0000000
178
179#define AR_2040_0 0x00000001
180#define AR_GI0 0x00000002
181#define AR_ChainSel0 0x0000001c
182#define AR_ChainSel0_S 2
183#define AR_2040_1 0x00000020
184#define AR_GI1 0x00000040
185#define AR_ChainSel1 0x00000380
186#define AR_ChainSel1_S 7
187#define AR_2040_2 0x00000400
188#define AR_GI2 0x00000800
189#define AR_ChainSel2 0x00007000
190#define AR_ChainSel2_S 12
191#define AR_2040_3 0x00008000
192#define AR_GI3 0x00010000
193#define AR_ChainSel3 0x000e0000
194#define AR_ChainSel3_S 17
195#define AR_RTSCTSRate 0x0ff00000
196#define AR_RTSCTSRate_S 20
197#define AR_TxCtlRsvd70 0xf0000000
198
199#define AR_TxRSSIAnt00 0x000000ff
200#define AR_TxRSSIAnt00_S 0
201#define AR_TxRSSIAnt01 0x0000ff00
202#define AR_TxRSSIAnt01_S 8
203#define AR_TxRSSIAnt02 0x00ff0000
204#define AR_TxRSSIAnt02_S 16
205#define AR_TxStatusRsvd00 0x3f000000
206#define AR_TxBaStatus 0x40000000
207#define AR_TxStatusRsvd01 0x80000000
208
209#define AR_FrmXmitOK 0x00000001
210#define AR_ExcessiveRetries 0x00000002
211#define AR_FIFOUnderrun 0x00000004
212#define AR_Filtered 0x00000008
213#define AR_RTSFailCnt 0x000000f0
214#define AR_RTSFailCnt_S 4
215#define AR_DataFailCnt 0x00000f00
216#define AR_DataFailCnt_S 8
217#define AR_VirtRetryCnt 0x0000f000
218#define AR_VirtRetryCnt_S 12
219#define AR_TxDelimUnderrun 0x00010000
220#define AR_TxDataUnderrun 0x00020000
221#define AR_DescCfgErr 0x00040000
222#define AR_TxTimerExpired 0x00080000
223#define AR_TxStatusRsvd10 0xfff00000
224
225#define AR_SendTimestamp ds_txstatus2
226#define AR_BaBitmapLow ds_txstatus3
227#define AR_BaBitmapHigh ds_txstatus4
228
229#define AR_TxRSSIAnt10 0x000000ff
230#define AR_TxRSSIAnt10_S 0
231#define AR_TxRSSIAnt11 0x0000ff00
232#define AR_TxRSSIAnt11_S 8
233#define AR_TxRSSIAnt12 0x00ff0000
234#define AR_TxRSSIAnt12_S 16
235#define AR_TxRSSICombined 0xff000000
236#define AR_TxRSSICombined_S 24
237
238#define AR_TxEVM0 ds_txstatus5
239#define AR_TxEVM1 ds_txstatus6
240#define AR_TxEVM2 ds_txstatus7
241
242#define AR_TxDone 0x00000001
243#define AR_SeqNum 0x00001ffe
244#define AR_SeqNum_S 1
245#define AR_TxStatusRsvd80 0x0001e000
246#define AR_TxOpExceeded 0x00020000
247#define AR_TxStatusRsvd81 0x001c0000
248#define AR_FinalTxIdx 0x00600000
249#define AR_FinalTxIdx_S 21
250#define AR_TxStatusRsvd82 0x01800000
251#define AR_PowerMgmt 0x02000000
252#define AR_TxStatusRsvd83 0xfc000000
253 64
254#define AR_RxCTLRsvd00 0xffffffff 65#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
66 int r; \
67 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
68 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
69 INI_RA((iniarray), r, (column))); \
70 DO_DELAY(regWr); \
71 } \
72 } while (0)
255 73
256#define AR_BufLen 0x00000fff 74#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
257#define AR_RxCtlRsvd00 0x00001000 75#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
258#define AR_RxIntrReq 0x00002000 76#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
259#define AR_RxCtlRsvd01 0xffffc000 77#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
78#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
79#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
260 80
261#define AR_RxRSSIAnt00 0x000000ff 81#define AR_GPIOD_MASK 0x00001FFF
262#define AR_RxRSSIAnt00_S 0 82#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
263#define AR_RxRSSIAnt01 0x0000ff00
264#define AR_RxRSSIAnt01_S 8
265#define AR_RxRSSIAnt02 0x00ff0000
266#define AR_RxRSSIAnt02_S 16
267#define AR_RxRate 0xff000000
268#define AR_RxRate_S 24
269#define AR_RxStatusRsvd00 0xff000000
270 83
271#define AR_DataLen 0x00000fff 84#define BASE_ACTIVATE_DELAY 100
272#define AR_RxMore 0x00001000 85#define RTC_PLL_SETTLE_DELAY 1000
273#define AR_NumDelim 0x003fc000 86#define COEF_SCALE_S 24
274#define AR_NumDelim_S 14 87#define HT40_CHANNEL_CENTER_SHIFT 10
275#define AR_RxStatusRsvd10 0xff800000
276 88
277#define AR_RcvTimestamp ds_rxstatus2 89#define ATH9K_ANTENNA0_CHAINMASK 0x1
90#define ATH9K_ANTENNA1_CHAINMASK 0x2
91
92#define ATH9K_NUM_DMA_DEBUG_REGS 8
93#define ATH9K_NUM_QUEUES 10
94
95#define MAX_RATE_POWER 63
96#define AH_TIMEOUT 100000
97#define AH_TIME_QUANTUM 10
98#define AR_KEYTABLE_SIZE 128
99#define POWER_UP_TIME 200000
100#define SPUR_RSSI_THRESH 40
101
102#define CAB_TIMEOUT_VAL 10
103#define BEACON_TIMEOUT_VAL 10
104#define MIN_BEACON_TIMEOUT_VAL 1
105#define SLEEP_SLOP 3
106
107#define INIT_CONFIG_STATUS 0x00000000
108#define INIT_RSSI_THR 0x00000700
109#define INIT_BCON_CNTRL_REG 0x00000000
110
111#define TU_TO_USEC(_tu) ((_tu) << 10)
112
113enum wireless_mode {
114 ATH9K_MODE_11A = 0,
115 ATH9K_MODE_11B = 2,
116 ATH9K_MODE_11G = 3,
117 ATH9K_MODE_11NA_HT20 = 6,
118 ATH9K_MODE_11NG_HT20 = 7,
119 ATH9K_MODE_11NA_HT40PLUS = 8,
120 ATH9K_MODE_11NA_HT40MINUS = 9,
121 ATH9K_MODE_11NG_HT40PLUS = 10,
122 ATH9K_MODE_11NG_HT40MINUS = 11,
123 ATH9K_MODE_MAX
124};
278 125
279#define AR_GI 0x00000001 126enum ath9k_hw_caps {
280#define AR_2040 0x00000002 127 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
281#define AR_Parallel40 0x00000004 128 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
282#define AR_Parallel40_S 2 129 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
283#define AR_RxStatusRsvd30 0x000000f8 130 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
284#define AR_RxAntenna 0xffffff00 131 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
285#define AR_RxAntenna_S 8 132 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
133 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
134 ATH9K_HW_CAP_VEOL = BIT(7),
135 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
136 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
137 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
138 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
139 ATH9K_HW_CAP_HT = BIT(12),
140 ATH9K_HW_CAP_GTT = BIT(13),
141 ATH9K_HW_CAP_FASTCC = BIT(14),
142 ATH9K_HW_CAP_RFSILENT = BIT(15),
143 ATH9K_HW_CAP_WOW = BIT(16),
144 ATH9K_HW_CAP_CST = BIT(17),
145 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
146 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
147 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
148 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
149 ATH9K_HW_CAP_BT_COEX = BIT(22)
150};
286 151
287#define AR_RxRSSIAnt10 0x000000ff 152enum ath9k_capability_type {
288#define AR_RxRSSIAnt10_S 0 153 ATH9K_CAP_CIPHER = 0,
289#define AR_RxRSSIAnt11 0x0000ff00 154 ATH9K_CAP_TKIP_MIC,
290#define AR_RxRSSIAnt11_S 8 155 ATH9K_CAP_TKIP_SPLIT,
291#define AR_RxRSSIAnt12 0x00ff0000 156 ATH9K_CAP_PHYCOUNTERS,
292#define AR_RxRSSIAnt12_S 16 157 ATH9K_CAP_DIVERSITY,
293#define AR_RxRSSICombined 0xff000000 158 ATH9K_CAP_TXPOW,
294#define AR_RxRSSICombined_S 24 159 ATH9K_CAP_PHYDIAG,
160 ATH9K_CAP_MCAST_KEYSRCH,
161 ATH9K_CAP_TSF_ADJUST,
162 ATH9K_CAP_WME_TKIPMIC,
163 ATH9K_CAP_RFSILENT,
164 ATH9K_CAP_ANT_CFG_2GHZ,
165 ATH9K_CAP_ANT_CFG_5GHZ
166};
295 167
296#define AR_RxEVM0 ds_rxstatus4 168struct ath9k_hw_capabilities {
297#define AR_RxEVM1 ds_rxstatus5 169 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
298#define AR_RxEVM2 ds_rxstatus6 170 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
171 u16 total_queues;
172 u16 keycache_size;
173 u16 low_5ghz_chan, high_5ghz_chan;
174 u16 low_2ghz_chan, high_2ghz_chan;
175 u16 num_mr_retries;
176 u16 rts_aggr_limit;
177 u8 tx_chainmask;
178 u8 rx_chainmask;
179 u16 tx_triglevel_max;
180 u16 reg_cap;
181 u8 num_gpio_pins;
182 u8 num_antcfg_2ghz;
183 u8 num_antcfg_5ghz;
184};
299 185
300#define AR_RxDone 0x00000001 186struct ath9k_ops_config {
301#define AR_RxFrameOK 0x00000002 187 int dma_beacon_response_time;
302#define AR_CRCErr 0x00000004 188 int sw_beacon_response_time;
303#define AR_DecryptCRCErr 0x00000008 189 int additional_swba_backoff;
304#define AR_PHYErr 0x00000010 190 int ack_6mb;
305#define AR_MichaelErr 0x00000020 191 int cwm_ignore_extcca;
306#define AR_PreDelimCRCErr 0x00000040 192 u8 pcie_powersave_enable;
307#define AR_RxStatusRsvd70 0x00000080 193 u8 pcie_l1skp_enable;
308#define AR_RxKeyIdxValid 0x00000100 194 u8 pcie_clock_req;
309#define AR_KeyIdx 0x0000fe00 195 u32 pcie_waen;
310#define AR_KeyIdx_S 9 196 int pcie_power_reset;
311#define AR_PHYErrCode 0x0000ff00 197 u8 pcie_restore;
312#define AR_PHYErrCode_S 8 198 u8 analog_shiftreg;
313#define AR_RxMoreAggr 0x00010000 199 u8 ht_enable;
314#define AR_RxAggr 0x00020000 200 u32 ofdm_trig_low;
315#define AR_PostDelimCRCErr 0x00040000 201 u32 ofdm_trig_high;
316#define AR_RxStatusRsvd71 0x3ff80000 202 u32 cck_trig_high;
317#define AR_DecryptBusyErr 0x40000000 203 u32 cck_trig_low;
318#define AR_KeyMiss 0x80000000 204 u32 enable_ani;
205 u8 noise_immunity_level;
206 u32 ofdm_weaksignal_det;
207 u32 cck_weaksignal_thr;
208 u8 spur_immunity_level;
209 u8 firstep_level;
210 int8_t rssi_thr_high;
211 int8_t rssi_thr_low;
212 u16 diversity_control;
213 u16 antenna_switch_swap;
214 int serialize_regmode;
215 int intr_mitigation;
216#define SPUR_DISABLE 0
217#define SPUR_ENABLE_IOCTL 1
218#define SPUR_ENABLE_EEPROM 2
219#define AR_EEPROM_MODAL_SPURS 5
220#define AR_SPUR_5413_1 1640
221#define AR_SPUR_5413_2 1200
222#define AR_NO_SPUR 0x8000
223#define AR_BASE_FREQ_2GHZ 2300
224#define AR_BASE_FREQ_5GHZ 4900
225#define AR_SPUR_FEEQ_BOUND_HT40 19
226#define AR_SPUR_FEEQ_BOUND_HT20 10
227 int spurmode;
228 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
229};
319 230
320#define AR5416_MAGIC 0x19641014 231enum ath9k_int {
232 ATH9K_INT_RX = 0x00000001,
233 ATH9K_INT_RXDESC = 0x00000002,
234 ATH9K_INT_RXNOFRM = 0x00000008,
235 ATH9K_INT_RXEOL = 0x00000010,
236 ATH9K_INT_RXORN = 0x00000020,
237 ATH9K_INT_TX = 0x00000040,
238 ATH9K_INT_TXDESC = 0x00000080,
239 ATH9K_INT_TIM_TIMER = 0x00000100,
240 ATH9K_INT_TXURN = 0x00000800,
241 ATH9K_INT_MIB = 0x00001000,
242 ATH9K_INT_RXPHY = 0x00004000,
243 ATH9K_INT_RXKCM = 0x00008000,
244 ATH9K_INT_SWBA = 0x00010000,
245 ATH9K_INT_BMISS = 0x00040000,
246 ATH9K_INT_BNR = 0x00100000,
247 ATH9K_INT_TIM = 0x00200000,
248 ATH9K_INT_DTIM = 0x00400000,
249 ATH9K_INT_DTIMSYNC = 0x00800000,
250 ATH9K_INT_GPIO = 0x01000000,
251 ATH9K_INT_CABEND = 0x02000000,
252 ATH9K_INT_CST = 0x10000000,
253 ATH9K_INT_GTT = 0x20000000,
254 ATH9K_INT_FATAL = 0x40000000,
255 ATH9K_INT_GLOBAL = 0x80000000,
256 ATH9K_INT_BMISC = ATH9K_INT_TIM |
257 ATH9K_INT_DTIM |
258 ATH9K_INT_DTIMSYNC |
259 ATH9K_INT_CABEND,
260 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
261 ATH9K_INT_RXDESC |
262 ATH9K_INT_RXEOL |
263 ATH9K_INT_RXORN |
264 ATH9K_INT_TXURN |
265 ATH9K_INT_TXDESC |
266 ATH9K_INT_MIB |
267 ATH9K_INT_RXPHY |
268 ATH9K_INT_RXKCM |
269 ATH9K_INT_SWBA |
270 ATH9K_INT_BMISS |
271 ATH9K_INT_GPIO,
272 ATH9K_INT_NOCARD = 0xffffffff
273};
321 274
322#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \ 275#define CHANNEL_CW_INT 0x00002
323 MS(ads->ds_rxstatus0, AR_RxRate) : \ 276#define CHANNEL_CCK 0x00020
324 (ads->ds_rxstatus3 >> 2) & 0xFF) 277#define CHANNEL_OFDM 0x00040
278#define CHANNEL_2GHZ 0x00080
279#define CHANNEL_5GHZ 0x00100
280#define CHANNEL_PASSIVE 0x00200
281#define CHANNEL_DYN 0x00400
282#define CHANNEL_HALF 0x04000
283#define CHANNEL_QUARTER 0x08000
284#define CHANNEL_HT20 0x10000
285#define CHANNEL_HT40PLUS 0x20000
286#define CHANNEL_HT40MINUS 0x40000
287
288#define CHANNEL_INTERFERENCE 0x01
289#define CHANNEL_DFS 0x02
290#define CHANNEL_4MS_LIMIT 0x04
291#define CHANNEL_DFS_CLEAR 0x08
292#define CHANNEL_DISALLOW_ADHOC 0x10
293#define CHANNEL_PER_11D_ADHOC 0x20
294
295#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
296#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
297#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
298#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
299#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
300#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
301#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
302#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
303#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
304#define CHANNEL_ALL \
305 (CHANNEL_OFDM| \
306 CHANNEL_CCK| \
307 CHANNEL_2GHZ | \
308 CHANNEL_5GHZ | \
309 CHANNEL_HT20 | \
310 CHANNEL_HT40PLUS | \
311 CHANNEL_HT40MINUS)
312
313struct ath9k_channel {
314 struct ieee80211_channel *chan;
315 u16 channel;
316 u32 channelFlags;
317 u32 chanmode;
318 int32_t CalValid;
319 bool oneTimeCalsDone;
320 int8_t iCoff;
321 int8_t qCoff;
322 int16_t rawNoiseFloor;
323};
325 324
326#define set11nTries(_series, _index) \ 325#define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
327 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 326 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
327 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
328 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
329#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
330 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
331 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
332 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
333#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
334#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
335#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
336#define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
337#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
338#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
339#define IS_CHAN_A_5MHZ_SPACED(_c) \
340 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
341 (((_c)->channel % 20) != 0) && \
342 (((_c)->channel % 10) != 0))
343
344/* These macros check chanmode and not channelFlags */
345#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
346#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
347 ((_c)->chanmode == CHANNEL_G_HT20))
348#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
349 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
350 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
351 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
352#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
353
354enum ath9k_power_mode {
355 ATH9K_PM_AWAKE = 0,
356 ATH9K_PM_FULL_SLEEP,
357 ATH9K_PM_NETWORK_SLEEP,
358 ATH9K_PM_UNDEFINED
359};
328 360
329#define set11nRate(_series, _index) \ 361enum ath9k_ant_setting {
330 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 362 ATH9K_ANT_VARIABLE = 0,
363 ATH9K_ANT_FIXED_A,
364 ATH9K_ANT_FIXED_B
365};
331 366
332#define set11nPktDurRTSCTS(_series, _index) \ 367enum ath9k_tp_scale {
333 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 368 ATH9K_TP_SCALE_MAX = 0,
334 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 369 ATH9K_TP_SCALE_50,
335 AR_RTSCTSQual##_index : 0)) 370 ATH9K_TP_SCALE_25,
371 ATH9K_TP_SCALE_12,
372 ATH9K_TP_SCALE_MIN
373};
336 374
337#define set11nRateFlags(_series, _index) \ 375enum ser_reg_mode {
338 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 376 SER_REG_MODE_OFF = 0,
339 AR_2040_##_index : 0) \ 377 SER_REG_MODE_ON = 1,
340 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 378 SER_REG_MODE_AUTO = 2,
341 AR_GI##_index : 0) \ 379};
342 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
343 380
344#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100) 381struct ath9k_beacon_state {
382 u32 bs_nexttbtt;
383 u32 bs_nextdtim;
384 u32 bs_intval;
385#define ATH9K_BEACON_PERIOD 0x0000ffff
386#define ATH9K_BEACON_ENA 0x00800000
387#define ATH9K_BEACON_RESET_TSF 0x01000000
388 u32 bs_dtimperiod;
389 u16 bs_cfpperiod;
390 u16 bs_cfpmaxduration;
391 u32 bs_cfpnext;
392 u16 bs_timoffset;
393 u16 bs_bmissthreshold;
394 u32 bs_sleepduration;
395};
345 396
346#define INIT_CONFIG_STATUS 0x00000000 397struct chan_centers {
347#define INIT_RSSI_THR 0x00000700 398 u16 synth_center;
348#define INIT_BCON_CNTRL_REG 0x00000000 399 u16 ctl_center;
400 u16 ext_center;
401};
349 402
350#define MIN_TX_FIFO_THRESHOLD 0x1 403enum {
351#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 404 ATH9K_RESET_POWER_ON,
352#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD 405 ATH9K_RESET_WARM,
406 ATH9K_RESET_COLD,
407};
353 408
354struct ar5416AniState { 409struct ar5416AniState {
355 struct ath9k_channel c; 410 struct ath9k_channel c;
@@ -378,447 +433,52 @@ struct ar5416AniState {
378 int16_t cckErrRssi[2]; 433 int16_t cckErrRssi[2];
379}; 434};
380 435
381#define HAL_PROCESS_ANI 0x00000001 436struct ath_hal {
382#define DO_ANI(ah) \ 437 u32 ah_magic;
383 ((AH5416(ah)->ah_procPhyErr & HAL_PROCESS_ANI)) 438 u16 ah_devid;
384 439 u16 ah_subvendorid;
385struct ar5416Stats { 440 u32 ah_macVersion;
386 u32 ast_ani_niup; 441 u16 ah_macRev;
387 u32 ast_ani_nidown; 442 u16 ah_phyRev;
388 u32 ast_ani_spurup; 443 u16 ah_analog5GhzRev;
389 u32 ast_ani_spurdown; 444 u16 ah_analog2GhzRev;
390 u32 ast_ani_ofdmon; 445
391 u32 ast_ani_ofdmoff; 446 void __iomem *ah_sh;
392 u32 ast_ani_cckhigh; 447 struct ath_softc *ah_sc;
393 u32 ast_ani_ccklow; 448
394 u32 ast_ani_stepup; 449 enum nl80211_iftype ah_opmode;
395 u32 ast_ani_stepdown; 450 struct ath9k_ops_config ah_config;
396 u32 ast_ani_ofdmerrs; 451 struct ath9k_hw_capabilities ah_caps;
397 u32 ast_ani_cckerrs; 452
398 u32 ast_ani_reset; 453 u16 ah_countryCode;
399 u32 ast_ani_lzero; 454 u32 ah_flags;
400 u32 ast_ani_lneg; 455 int16_t ah_powerLimit;
401 struct ath9k_mib_stats ast_mibstats; 456 u16 ah_maxPowerLevel;
402 struct ath9k_node_stats ast_nodestats; 457 u32 ah_tpScale;
458 u16 ah_currentRD;
459 u16 ah_currentRDExt;
460 u16 ah_currentRDInUse;
461 char alpha2[2];
462 struct reg_dmn_pair_mapping *regpair;
463 enum ath9k_power_mode ah_power_mode;
464 enum ath9k_power_mode ah_restore_mode;
465
466 struct ath9k_channel ah_channels[38];
467 struct ath9k_channel *ah_curchan;
468
469 bool ah_isPciExpress;
470 u16 ah_txTrigLevel;
471 u16 ah_rfsilent;
472 u32 ah_rfkill_gpio;
473 u32 ah_rfkill_polarity;
474 u32 ah_btactive_gpio;
475 u32 ah_wlanactive_gpio;
476
477 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
478
479 bool sw_mgmt_crypto;
403}; 480};
404 481
405#define AR5416_OPFLAGS_11A 0x01
406#define AR5416_OPFLAGS_11G 0x02
407#define AR5416_OPFLAGS_N_5G_HT40 0x04
408#define AR5416_OPFLAGS_N_2G_HT40 0x08
409#define AR5416_OPFLAGS_N_5G_HT20 0x10
410#define AR5416_OPFLAGS_N_2G_HT20 0x20
411
412#define EEP_RFSILENT_ENABLED 0x0001
413#define EEP_RFSILENT_ENABLED_S 0
414#define EEP_RFSILENT_POLARITY 0x0002
415#define EEP_RFSILENT_POLARITY_S 1
416#define EEP_RFSILENT_GPIO_SEL 0x001c
417#define EEP_RFSILENT_GPIO_SEL_S 2
418
419#define AR5416_EEP_NO_BACK_VER 0x1
420#define AR5416_EEP_VER 0xE
421#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
422#define AR5416_EEP_MINOR_VER_2 0x2
423#define AR5416_EEP_MINOR_VER_3 0x3
424#define AR5416_EEP_MINOR_VER_7 0x7
425#define AR5416_EEP_MINOR_VER_9 0x9
426#define AR5416_EEP_MINOR_VER_16 0x10
427#define AR5416_EEP_MINOR_VER_17 0x11
428#define AR5416_EEP_MINOR_VER_19 0x13
429#define AR5416_EEP_MINOR_VER_20 0x14
430
431#define AR5416_NUM_5G_CAL_PIERS 8
432#define AR5416_NUM_2G_CAL_PIERS 4
433#define AR5416_NUM_5G_20_TARGET_POWERS 8
434#define AR5416_NUM_5G_40_TARGET_POWERS 8
435#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
436#define AR5416_NUM_2G_20_TARGET_POWERS 4
437#define AR5416_NUM_2G_40_TARGET_POWERS 4
438#define AR5416_NUM_CTLS 24
439#define AR5416_NUM_BAND_EDGES 8
440#define AR5416_NUM_PD_GAINS 4
441#define AR5416_PD_GAINS_IN_MASK 4
442#define AR5416_PD_GAIN_ICEPTS 5
443#define AR5416_EEPROM_MODAL_SPURS 5
444#define AR5416_MAX_RATE_POWER 63
445#define AR5416_NUM_PDADC_VALUES 128
446#define AR5416_BCHAN_UNUSED 0xFF
447#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
448#define AR5416_MAX_CHAINS 3
449#define AR5416_PWR_TABLE_OFFSET -5
450
451/* Rx gain type values */
452#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
453#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
454#define AR5416_EEP_RXGAIN_ORIG 2
455
456/* Tx gain type values */
457#define AR5416_EEP_TXGAIN_ORIGINAL 0
458#define AR5416_EEP_TXGAIN_HIGH_POWER 1
459
460#define AR5416_EEP4K_START_LOC 64
461#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
462#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
463#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
464#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
465#define AR5416_EEP4K_NUM_CTLS 12
466#define AR5416_EEP4K_NUM_BAND_EDGES 4
467#define AR5416_EEP4K_NUM_PD_GAINS 2
468#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
469#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
470#define AR5416_EEP4K_MAX_CHAINS 1
471
472enum eeprom_param {
473 EEP_NFTHRESH_5,
474 EEP_NFTHRESH_2,
475 EEP_MAC_MSW,
476 EEP_MAC_MID,
477 EEP_MAC_LSW,
478 EEP_REG_0,
479 EEP_REG_1,
480 EEP_OP_CAP,
481 EEP_OP_MODE,
482 EEP_RF_SILENT,
483 EEP_OB_5,
484 EEP_DB_5,
485 EEP_OB_2,
486 EEP_DB_2,
487 EEP_MINOR_REV,
488 EEP_TX_MASK,
489 EEP_RX_MASK,
490 EEP_RXGAIN_TYPE,
491 EEP_TXGAIN_TYPE,
492 EEP_DAC_HPWR_5G,
493};
494
495enum ar5416_rates {
496 rate6mb, rate9mb, rate12mb, rate18mb,
497 rate24mb, rate36mb, rate48mb, rate54mb,
498 rate1l, rate2l, rate2s, rate5_5l,
499 rate5_5s, rate11l, rate11s, rateXr,
500 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
501 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
502 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
503 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
504 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
505 Ar5416RateSize
506};
507
508enum ath9k_hal_freq_band {
509 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
510 ATH9K_HAL_FREQ_BAND_2GHZ = 1
511};
512
513struct base_eep_header {
514 u16 length;
515 u16 checksum;
516 u16 version;
517 u8 opCapFlags;
518 u8 eepMisc;
519 u16 regDmn[2];
520 u8 macAddr[6];
521 u8 rxMask;
522 u8 txMask;
523 u16 rfSilent;
524 u16 blueToothOptions;
525 u16 deviceCap;
526 u32 binBuildNumber;
527 u8 deviceType;
528 u8 pwdclkind;
529 u8 futureBase_1[2];
530 u8 rxGainType;
531 u8 dacHiPwrMode_5G;
532 u8 futureBase_2;
533 u8 dacLpMode;
534 u8 txGainType;
535 u8 rcChainMask;
536 u8 desiredScaleCCK;
537 u8 futureBase_3[23];
538} __packed;
539
540struct base_eep_header_4k {
541 u16 length;
542 u16 checksum;
543 u16 version;
544 u8 opCapFlags;
545 u8 eepMisc;
546 u16 regDmn[2];
547 u8 macAddr[6];
548 u8 rxMask;
549 u8 txMask;
550 u16 rfSilent;
551 u16 blueToothOptions;
552 u16 deviceCap;
553 u32 binBuildNumber;
554 u8 deviceType;
555 u8 futureBase[1];
556} __packed;
557
558
559struct spur_chan {
560 u16 spurChan;
561 u8 spurRangeLow;
562 u8 spurRangeHigh;
563} __packed;
564
565struct modal_eep_header {
566 u32 antCtrlChain[AR5416_MAX_CHAINS];
567 u32 antCtrlCommon;
568 u8 antennaGainCh[AR5416_MAX_CHAINS];
569 u8 switchSettling;
570 u8 txRxAttenCh[AR5416_MAX_CHAINS];
571 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
572 u8 adcDesiredSize;
573 u8 pgaDesiredSize;
574 u8 xlnaGainCh[AR5416_MAX_CHAINS];
575 u8 txEndToXpaOff;
576 u8 txEndToRxOn;
577 u8 txFrameToXpaOn;
578 u8 thresh62;
579 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
580 u8 xpdGain;
581 u8 xpd;
582 u8 iqCalICh[AR5416_MAX_CHAINS];
583 u8 iqCalQCh[AR5416_MAX_CHAINS];
584 u8 pdGainOverlap;
585 u8 ob;
586 u8 db;
587 u8 xpaBiasLvl;
588 u8 pwrDecreaseFor2Chain;
589 u8 pwrDecreaseFor3Chain;
590 u8 txFrameToDataStart;
591 u8 txFrameToPaOn;
592 u8 ht40PowerIncForPdadc;
593 u8 bswAtten[AR5416_MAX_CHAINS];
594 u8 bswMargin[AR5416_MAX_CHAINS];
595 u8 swSettleHt40;
596 u8 xatten2Db[AR5416_MAX_CHAINS];
597 u8 xatten2Margin[AR5416_MAX_CHAINS];
598 u8 ob_ch1;
599 u8 db_ch1;
600 u8 useAnt1:1,
601 force_xpaon:1,
602 local_bias:1,
603 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
604 u8 miscBits;
605 u16 xpaBiasLvlFreq[3];
606 u8 futureModal[6];
607
608 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
609} __packed;
610
611struct modal_eep_4k_header {
612 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
613 u32 antCtrlCommon;
614 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
615 u8 switchSettling;
616 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
617 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
618 u8 adcDesiredSize;
619 u8 pgaDesiredSize;
620 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
621 u8 txEndToXpaOff;
622 u8 txEndToRxOn;
623 u8 txFrameToXpaOn;
624 u8 thresh62;
625 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
626 u8 xpdGain;
627 u8 xpd;
628 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
629 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
630 u8 pdGainOverlap;
631 u8 ob_01;
632 u8 db1_01;
633 u8 xpaBiasLvl;
634 u8 txFrameToDataStart;
635 u8 txFrameToPaOn;
636 u8 ht40PowerIncForPdadc;
637 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
638 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
639 u8 swSettleHt40;
640 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
641 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
642 u8 db2_01;
643 u8 version;
644 u16 ob_234;
645 u16 db1_234;
646 u16 db2_234;
647 u8 futureModal[4];
648
649 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
650} __packed;
651
652
653struct cal_data_per_freq {
654 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
655 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
656} __packed;
657
658struct cal_data_per_freq_4k {
659 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
660 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
661} __packed;
662
663struct cal_target_power_leg {
664 u8 bChannel;
665 u8 tPow2x[4];
666} __packed;
667
668struct cal_target_power_ht {
669 u8 bChannel;
670 u8 tPow2x[8];
671} __packed;
672
673
674#ifdef __BIG_ENDIAN_BITFIELD
675struct cal_ctl_edges {
676 u8 bChannel;
677 u8 flag:2, tPower:6;
678} __packed;
679#else
680struct cal_ctl_edges {
681 u8 bChannel;
682 u8 tPower:6, flag:2;
683} __packed;
684#endif
685
686struct cal_ctl_data {
687 struct cal_ctl_edges
688 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
689} __packed;
690
691struct cal_ctl_data_4k {
692 struct cal_ctl_edges
693 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
694} __packed;
695
696struct ar5416_eeprom_def {
697 struct base_eep_header baseEepHeader;
698 u8 custData[64];
699 struct modal_eep_header modalHeader[2];
700 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
701 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
702 struct cal_data_per_freq
703 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
704 struct cal_data_per_freq
705 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
706 struct cal_target_power_leg
707 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
708 struct cal_target_power_ht
709 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
710 struct cal_target_power_ht
711 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
712 struct cal_target_power_leg
713 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
714 struct cal_target_power_leg
715 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
716 struct cal_target_power_ht
717 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
718 struct cal_target_power_ht
719 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
720 u8 ctlIndex[AR5416_NUM_CTLS];
721 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
722 u8 padding;
723} __packed;
724
725struct ar5416_eeprom_4k {
726 struct base_eep_header_4k baseEepHeader;
727 u8 custData[20];
728 struct modal_eep_4k_header modalHeader;
729 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
730 struct cal_data_per_freq_4k
731 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
732 struct cal_target_power_leg
733 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
734 struct cal_target_power_leg
735 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
736 struct cal_target_power_ht
737 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
738 struct cal_target_power_ht
739 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
740 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
741 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
742 u8 padding;
743} __packed;
744
745struct ar5416IniArray {
746 u32 *ia_array;
747 u32 ia_rows;
748 u32 ia_columns;
749};
750
751#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
752 (iniarray)->ia_array = (u32 *)(array); \
753 (iniarray)->ia_rows = (rows); \
754 (iniarray)->ia_columns = (columns); \
755 } while (0)
756
757#define INI_RA(iniarray, row, column) \
758 (((iniarray)->ia_array)[(row) * ((iniarray)->ia_columns) + (column)])
759
760#define INIT_CAL(_perCal) do { \
761 (_perCal)->calState = CAL_WAITING; \
762 (_perCal)->calNext = NULL; \
763 } while (0)
764
765#define INSERT_CAL(_ahp, _perCal) \
766 do { \
767 if ((_ahp)->ah_cal_list_last == NULL) { \
768 (_ahp)->ah_cal_list = \
769 (_ahp)->ah_cal_list_last = (_perCal); \
770 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
771 } else { \
772 ((_ahp)->ah_cal_list_last)->calNext = (_perCal); \
773 (_ahp)->ah_cal_list_last = (_perCal); \
774 (_perCal)->calNext = (_ahp)->ah_cal_list; \
775 } \
776 } while (0)
777
778enum hal_cal_types {
779 ADC_DC_INIT_CAL = 0x1,
780 ADC_GAIN_CAL = 0x2,
781 ADC_DC_CAL = 0x4,
782 IQ_MISMATCH_CAL = 0x8
783};
784
785enum hal_cal_state {
786 CAL_INACTIVE,
787 CAL_WAITING,
788 CAL_RUNNING,
789 CAL_DONE
790};
791
792#define MIN_CAL_SAMPLES 1
793#define MAX_CAL_SAMPLES 64
794#define INIT_LOG_COUNT 5
795#define PER_MIN_LOG_COUNT 2
796#define PER_MAX_LOG_COUNT 10
797
798struct hal_percal_data {
799 enum hal_cal_types calType;
800 u32 calNumSamples;
801 u32 calCountMax;
802 void (*calCollect) (struct ath_hal *);
803 void (*calPostProc) (struct ath_hal *, u8);
804};
805
806struct hal_cal_list {
807 const struct hal_percal_data *calData;
808 enum hal_cal_state calState;
809 struct hal_cal_list *calNext;
810};
811
812/*
813 * Enum to indentify the eeprom mappings
814 */
815enum hal_eep_map {
816 EEP_MAP_DEFAULT = 0x0,
817 EEP_MAP_4KBITS,
818 EEP_MAP_MAX
819};
820
821
822struct ath_hal_5416 { 482struct ath_hal_5416 {
823 struct ath_hal ah; 483 struct ath_hal ah;
824 union { 484 union {
@@ -952,142 +612,85 @@ struct ath_hal_5416 {
952}; 612};
953#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah)) 613#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
954 614
955#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 615/* Attach, Detach, Reset */
956 616const char *ath9k_hw_probe(u16 vendorid, u16 devid);
957#define ar5416RfDetach(ah) do { \ 617void ath9k_hw_detach(struct ath_hal *ah);
958 if (AH5416(ah)->ah_rfHal.rfDetach != NULL) \ 618struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
959 AH5416(ah)->ah_rfHal.rfDetach(ah); \ 619 void __iomem *mem, int *error);
960 } while (0) 620void ath9k_hw_rfdetach(struct ath_hal *ah);
961 621int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
962#define ath9k_hw_use_flash(_ah) \ 622 bool bChannelChange);
963 (!(_ah->ah_flags & AH_USE_EEPROM)) 623bool ath9k_hw_fill_cap_info(struct ath_hal *ah);
964 624bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
965 625 u32 capability, u32 *result);
966#define DO_DELAY(x) do { \ 626bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
967 if ((++(x) % 64) == 0) \ 627 u32 capability, u32 setting, int *status);
968 udelay(1); \ 628
969 } while (0) 629/* Key Cache Management */
970 630bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
971#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \ 631bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac);
972 int r; \ 632bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
973 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 633 const struct ath9k_keyval *k,
974 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \ 634 const u8 *mac, int xorKey);
975 INI_RA((iniarray), r, (column))); \ 635bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
976 DO_DELAY(regWr); \ 636
977 } \ 637/* GPIO / RFKILL / Antennae */
978 } while (0) 638void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
979 639u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
980#define BASE_ACTIVATE_DELAY 100 640void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
981#define RTC_PLL_SETTLE_DELAY 1000 641 u32 ah_signal_type);
982#define COEF_SCALE_S 24 642void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val);
983#define HT40_CHANNEL_CENTER_SHIFT 10 643#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
984 644void ath9k_enable_rfkill(struct ath_hal *ah);
985#define AR5416_EEPROM_MAGIC_OFFSET 0x0
986
987#define AR5416_EEPROM_S 2
988#define AR5416_EEPROM_OFFSET 0x2000
989#define AR5416_EEPROM_START_ADDR \
990 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
991#define AR5416_EEPROM_MAX 0xae0
992#define ar5416_get_eep_ver(_ahp) \
993 (((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)
994#define ar5416_get_eep_rev(_ahp) \
995 (((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)
996#define ar5416_get_ntxchains(_txchainmask) \
997 (((_txchainmask >> 2) & 1) + \
998 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
999
1000/* EEPROM 4K bit map definations */
1001#define ar5416_get_eep4k_ver(_ahp) \
1002 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)
1003#define ar5416_get_eep4k_rev(_ahp) \
1004 (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)
1005
1006
1007#ifdef __BIG_ENDIAN
1008#define AR5416_EEPROM_MAGIC 0x5aa5
1009#else
1010#define AR5416_EEPROM_MAGIC 0xa55a
1011#endif 645#endif
1012 646u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
1013#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 647void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
1014 648bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
1015#define ATH9K_ANTENNA0_CHAINMASK 0x1 649 enum ath9k_ant_setting settings,
1016#define ATH9K_ANTENNA1_CHAINMASK 0x2 650 struct ath9k_channel *chan,
1017 651 u8 *tx_chainmask, u8 *rx_chainmask,
1018#define ATH9K_NUM_DMA_DEBUG_REGS 8 652 u8 *antenna_cfgd);
1019#define ATH9K_NUM_QUEUES 10 653
1020 654/* General Operation */
1021#define HAL_NOISE_IMMUNE_MAX 4 655bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val);
1022#define HAL_SPUR_IMMUNE_MAX 7 656u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1023#define HAL_FIRST_STEP_MAX 2 657bool ath9k_get_channel_edges(struct ath_hal *ah, u16 flags, u16 *low, u16 *high);
1024 658u16 ath9k_hw_computetxtime(struct ath_hal *ah, struct ath_rate_table *rates,
1025#define ATH9K_ANI_OFDM_TRIG_HIGH 500 659 u32 frameLen, u16 rateix, bool shortPreamble);
1026#define ATH9K_ANI_OFDM_TRIG_LOW 200 660void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1027#define ATH9K_ANI_CCK_TRIG_HIGH 200 661 struct ath9k_channel *chan,
1028#define ATH9K_ANI_CCK_TRIG_LOW 100 662 struct chan_centers *centers);
1029#define ATH9K_ANI_NOISE_IMMUNE_LVL 4 663u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
1030#define ATH9K_ANI_USE_OFDM_WEAK_SIG true 664void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
1031#define ATH9K_ANI_CCK_WEAK_SIG_THR false 665bool ath9k_hw_phy_disable(struct ath_hal *ah);
1032#define ATH9K_ANI_SPUR_IMMUNE_LVL 7 666bool ath9k_hw_disable(struct ath_hal *ah);
1033#define ATH9K_ANI_FIRSTEP_LVL 0 667bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1034#define ATH9K_ANI_RSSI_THR_HIGH 40 668void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
1035#define ATH9K_ANI_RSSI_THR_LOW 7 669bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
1036#define ATH9K_ANI_PERIOD 100 670void ath9k_hw_setopmode(struct ath_hal *ah);
1037 671void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1);
1038#define AR_GPIOD_MASK 0x00001FFF 672void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
1039#define AR_GPIO_BIT(_gpio) (1 << (_gpio)) 673bool ath9k_hw_setbssidmask(struct ath_hal *ah, const u8 *mask);
1040 674void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid, u16 assocId);
1041#define HAL_EP_RND(x, mul) \ 675u64 ath9k_hw_gettsf64(struct ath_hal *ah);
1042 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 676void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64);
1043#define BEACON_RSSI(ahp) \ 677void ath9k_hw_reset_tsf(struct ath_hal *ah);
1044 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \ 678bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting);
1045 ATH9K_RSSI_EP_MULTIPLIER) 679bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
1046 680void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
1047#define ah_mibStats ah_stats.ast_mibstats 681void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period);
1048 682void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
1049#define AH_TIMEOUT 100000 683 const struct ath9k_beacon_state *bs);
1050#define AH_TIME_QUANTUM 10 684bool ath9k_hw_setpower(struct ath_hal *ah,
1051 685 enum ath9k_power_mode mode);
1052#define AR_KEYTABLE_SIZE 128 686void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
1053#define POWER_UP_TIME 200000 687
1054 688/* Interrupt Handling */
1055#define EXT_ADDITIVE (0x8000) 689bool ath9k_hw_intrpend(struct ath_hal *ah);
1056#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 690bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
1057#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 691enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
1058#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 692enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints);
1059 693
1060#define SUB_NUM_CTL_MODES_AT_5G_40 2 694void ath9k_hw_btcoex_enable(struct ath_hal *ah);
1061#define SUB_NUM_CTL_MODES_AT_2G_40 3
1062#define SPUR_RSSI_THRESH 40
1063
1064#define TU_TO_USEC(_tu) ((_tu) << 10)
1065
1066#define CAB_TIMEOUT_VAL 10
1067#define BEACON_TIMEOUT_VAL 10
1068#define MIN_BEACON_TIMEOUT_VAL 1
1069#define SLEEP_SLOP 3
1070
1071#define CCK_SIFS_TIME 10
1072#define CCK_PREAMBLE_BITS 144
1073#define CCK_PLCP_BITS 48
1074
1075#define OFDM_SIFS_TIME 16
1076#define OFDM_PREAMBLE_TIME 20
1077#define OFDM_PLCP_BITS 22
1078#define OFDM_SYMBOL_TIME 4
1079
1080#define OFDM_SIFS_TIME_HALF 32
1081#define OFDM_PREAMBLE_TIME_HALF 40
1082#define OFDM_PLCP_BITS_HALF 22
1083#define OFDM_SYMBOL_TIME_HALF 8
1084
1085#define OFDM_SIFS_TIME_QUARTER 64
1086#define OFDM_PREAMBLE_TIME_QUARTER 80
1087#define OFDM_PLCP_BITS_QUARTER 22
1088#define OFDM_SYMBOL_TIME_QUARTER 16
1089
1090u32 ath9k_hw_get_eeprom(struct ath_hal *ah,
1091 enum eeprom_param param);
1092 695
1093#endif 696#endif
diff --git a/drivers/net/wireless/ath9k/mac.c b/drivers/net/wireless/ath9k/mac.c
index 2427c44a8c35..b375a2964d2a 100644
--- a/drivers/net/wireless/ath9k/mac.c
+++ b/drivers/net/wireless/ath9k/mac.c
@@ -14,10 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
23 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
diff --git a/drivers/net/wireless/ath9k/mac.h b/drivers/net/wireless/ath9k/mac.h
new file mode 100644
index 000000000000..9012af247797
--- /dev/null
+++ b/drivers/net/wireless/ath9k/mac.h
@@ -0,0 +1,676 @@
1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef MAC_H
18#define MAC_H
19
20#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_V20_OR_LATER(ah) ? \
21 MS(ads->ds_rxstatus0, AR_RxRate) : \
22 (ads->ds_rxstatus3 >> 2) & 0xFF)
23
24#define set11nTries(_series, _index) \
25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
26
27#define set11nRate(_series, _index) \
28 (SM((_series)[_index].Rate, AR_XmitRate##_index))
29
30#define set11nPktDurRTSCTS(_series, _index) \
31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
33 AR_RTSCTSQual##_index : 0))
34
35#define set11nRateFlags(_series, _index) \
36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
39 AR_GI##_index : 0) \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
41
42#define CCK_SIFS_TIME 10
43#define CCK_PREAMBLE_BITS 144
44#define CCK_PLCP_BITS 48
45
46#define OFDM_SIFS_TIME 16
47#define OFDM_PREAMBLE_TIME 20
48#define OFDM_PLCP_BITS 22
49#define OFDM_SYMBOL_TIME 4
50
51#define OFDM_SIFS_TIME_HALF 32
52#define OFDM_PREAMBLE_TIME_HALF 40
53#define OFDM_PLCP_BITS_HALF 22
54#define OFDM_SYMBOL_TIME_HALF 8
55
56#define OFDM_SIFS_TIME_QUARTER 64
57#define OFDM_PREAMBLE_TIME_QUARTER 80
58#define OFDM_PLCP_BITS_QUARTER 22
59#define OFDM_SYMBOL_TIME_QUARTER 16
60
61#define INIT_AIFS 2
62#define INIT_CWMIN 15
63#define INIT_CWMIN_11B 31
64#define INIT_CWMAX 1023
65#define INIT_SH_RETRY 10
66#define INIT_LG_RETRY 10
67#define INIT_SSH_RETRY 32
68#define INIT_SLG_RETRY 32
69
70#define ATH9K_SLOT_TIME_6 6
71#define ATH9K_SLOT_TIME_9 9
72#define ATH9K_SLOT_TIME_20 20
73
74#define ATH9K_TXERR_XRETRY 0x01
75#define ATH9K_TXERR_FILT 0x02
76#define ATH9K_TXERR_FIFO 0x04
77#define ATH9K_TXERR_XTXOP 0x08
78#define ATH9K_TXERR_TIMER_EXPIRED 0x10
79
80#define ATH9K_TX_BA 0x01
81#define ATH9K_TX_PWRMGMT 0x02
82#define ATH9K_TX_DESC_CFG_ERR 0x04
83#define ATH9K_TX_DATA_UNDERRUN 0x08
84#define ATH9K_TX_DELIM_UNDERRUN 0x10
85#define ATH9K_TX_SW_ABORTED 0x40
86#define ATH9K_TX_SW_FILTERED 0x80
87
88#define MIN_TX_FIFO_THRESHOLD 0x1
89#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
90#define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
91
92struct ath_tx_status {
93 u32 ts_tstamp;
94 u16 ts_seqnum;
95 u8 ts_status;
96 u8 ts_ratecode;
97 u8 ts_rateindex;
98 int8_t ts_rssi;
99 u8 ts_shortretry;
100 u8 ts_longretry;
101 u8 ts_virtcol;
102 u8 ts_antenna;
103 u8 ts_flags;
104 int8_t ts_rssi_ctl0;
105 int8_t ts_rssi_ctl1;
106 int8_t ts_rssi_ctl2;
107 int8_t ts_rssi_ext0;
108 int8_t ts_rssi_ext1;
109 int8_t ts_rssi_ext2;
110 u8 pad[3];
111 u32 ba_low;
112 u32 ba_high;
113 u32 evm0;
114 u32 evm1;
115 u32 evm2;
116};
117
118struct ath_rx_status {
119 u32 rs_tstamp;
120 u16 rs_datalen;
121 u8 rs_status;
122 u8 rs_phyerr;
123 int8_t rs_rssi;
124 u8 rs_keyix;
125 u8 rs_rate;
126 u8 rs_antenna;
127 u8 rs_more;
128 int8_t rs_rssi_ctl0;
129 int8_t rs_rssi_ctl1;
130 int8_t rs_rssi_ctl2;
131 int8_t rs_rssi_ext0;
132 int8_t rs_rssi_ext1;
133 int8_t rs_rssi_ext2;
134 u8 rs_isaggr;
135 u8 rs_moreaggr;
136 u8 rs_num_delims;
137 u8 rs_flags;
138 u32 evm0;
139 u32 evm1;
140 u32 evm2;
141};
142
143#define ATH9K_RXERR_CRC 0x01
144#define ATH9K_RXERR_PHY 0x02
145#define ATH9K_RXERR_FIFO 0x04
146#define ATH9K_RXERR_DECRYPT 0x08
147#define ATH9K_RXERR_MIC 0x10
148
149#define ATH9K_RX_MORE 0x01
150#define ATH9K_RX_MORE_AGGR 0x02
151#define ATH9K_RX_GI 0x04
152#define ATH9K_RX_2040 0x08
153#define ATH9K_RX_DELIM_CRC_PRE 0x10
154#define ATH9K_RX_DELIM_CRC_POST 0x20
155#define ATH9K_RX_DECRYPT_BUSY 0x40
156
157#define ATH9K_RXKEYIX_INVALID ((u8)-1)
158#define ATH9K_TXKEYIX_INVALID ((u32)-1)
159
160struct ath_desc {
161 u32 ds_link;
162 u32 ds_data;
163 u32 ds_ctl0;
164 u32 ds_ctl1;
165 u32 ds_hw[20];
166 union {
167 struct ath_tx_status tx;
168 struct ath_rx_status rx;
169 void *stats;
170 } ds_us;
171 void *ds_vdata;
172} __packed;
173
174#define ds_txstat ds_us.tx
175#define ds_rxstat ds_us.rx
176#define ds_stat ds_us.stats
177
178#define ATH9K_TXDESC_CLRDMASK 0x0001
179#define ATH9K_TXDESC_NOACK 0x0002
180#define ATH9K_TXDESC_RTSENA 0x0004
181#define ATH9K_TXDESC_CTSENA 0x0008
182/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
183 * the descriptor its marked on. We take a tx interrupt to reap
184 * descriptors when the h/w hits an EOL condition or
185 * when the descriptor is specifically marked to generate
186 * an interrupt with this flag. Descriptors should be
187 * marked periodically to insure timely replenishing of the
188 * supply needed for sending frames. Defering interrupts
189 * reduces system load and potentially allows more concurrent
190 * work to be done but if done to aggressively can cause
191 * senders to backup. When the hardware queue is left too
192 * large rate control information may also be too out of
193 * date. An Alternative for this is TX interrupt mitigation
194 * but this needs more testing. */
195#define ATH9K_TXDESC_INTREQ 0x0010
196#define ATH9K_TXDESC_VEOL 0x0020
197#define ATH9K_TXDESC_EXT_ONLY 0x0040
198#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
199#define ATH9K_TXDESC_VMF 0x0100
200#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
201#define ATH9K_TXDESC_CAB 0x0400
202
203#define ATH9K_RXDESC_INTREQ 0x0020
204
205struct ar5416_desc {
206 u32 ds_link;
207 u32 ds_data;
208 u32 ds_ctl0;
209 u32 ds_ctl1;
210 union {
211 struct {
212 u32 ctl2;
213 u32 ctl3;
214 u32 ctl4;
215 u32 ctl5;
216 u32 ctl6;
217 u32 ctl7;
218 u32 ctl8;
219 u32 ctl9;
220 u32 ctl10;
221 u32 ctl11;
222 u32 status0;
223 u32 status1;
224 u32 status2;
225 u32 status3;
226 u32 status4;
227 u32 status5;
228 u32 status6;
229 u32 status7;
230 u32 status8;
231 u32 status9;
232 } tx;
233 struct {
234 u32 status0;
235 u32 status1;
236 u32 status2;
237 u32 status3;
238 u32 status4;
239 u32 status5;
240 u32 status6;
241 u32 status7;
242 u32 status8;
243 } rx;
244 } u;
245} __packed;
246
247#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
248#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
249
250#define ds_ctl2 u.tx.ctl2
251#define ds_ctl3 u.tx.ctl3
252#define ds_ctl4 u.tx.ctl4
253#define ds_ctl5 u.tx.ctl5
254#define ds_ctl6 u.tx.ctl6
255#define ds_ctl7 u.tx.ctl7
256#define ds_ctl8 u.tx.ctl8
257#define ds_ctl9 u.tx.ctl9
258#define ds_ctl10 u.tx.ctl10
259#define ds_ctl11 u.tx.ctl11
260
261#define ds_txstatus0 u.tx.status0
262#define ds_txstatus1 u.tx.status1
263#define ds_txstatus2 u.tx.status2
264#define ds_txstatus3 u.tx.status3
265#define ds_txstatus4 u.tx.status4
266#define ds_txstatus5 u.tx.status5
267#define ds_txstatus6 u.tx.status6
268#define ds_txstatus7 u.tx.status7
269#define ds_txstatus8 u.tx.status8
270#define ds_txstatus9 u.tx.status9
271
272#define ds_rxstatus0 u.rx.status0
273#define ds_rxstatus1 u.rx.status1
274#define ds_rxstatus2 u.rx.status2
275#define ds_rxstatus3 u.rx.status3
276#define ds_rxstatus4 u.rx.status4
277#define ds_rxstatus5 u.rx.status5
278#define ds_rxstatus6 u.rx.status6
279#define ds_rxstatus7 u.rx.status7
280#define ds_rxstatus8 u.rx.status8
281
282#define AR_FrameLen 0x00000fff
283#define AR_VirtMoreFrag 0x00001000
284#define AR_TxCtlRsvd00 0x0000e000
285#define AR_XmitPower 0x003f0000
286#define AR_XmitPower_S 16
287#define AR_RTSEnable 0x00400000
288#define AR_VEOL 0x00800000
289#define AR_ClrDestMask 0x01000000
290#define AR_TxCtlRsvd01 0x1e000000
291#define AR_TxIntrReq 0x20000000
292#define AR_DestIdxValid 0x40000000
293#define AR_CTSEnable 0x80000000
294
295#define AR_BufLen 0x00000fff
296#define AR_TxMore 0x00001000
297#define AR_DestIdx 0x000fe000
298#define AR_DestIdx_S 13
299#define AR_FrameType 0x00f00000
300#define AR_FrameType_S 20
301#define AR_NoAck 0x01000000
302#define AR_InsertTS 0x02000000
303#define AR_CorruptFCS 0x04000000
304#define AR_ExtOnly 0x08000000
305#define AR_ExtAndCtl 0x10000000
306#define AR_MoreAggr 0x20000000
307#define AR_IsAggr 0x40000000
308
309#define AR_BurstDur 0x00007fff
310#define AR_BurstDur_S 0
311#define AR_DurUpdateEna 0x00008000
312#define AR_XmitDataTries0 0x000f0000
313#define AR_XmitDataTries0_S 16
314#define AR_XmitDataTries1 0x00f00000
315#define AR_XmitDataTries1_S 20
316#define AR_XmitDataTries2 0x0f000000
317#define AR_XmitDataTries2_S 24
318#define AR_XmitDataTries3 0xf0000000
319#define AR_XmitDataTries3_S 28
320
321#define AR_XmitRate0 0x000000ff
322#define AR_XmitRate0_S 0
323#define AR_XmitRate1 0x0000ff00
324#define AR_XmitRate1_S 8
325#define AR_XmitRate2 0x00ff0000
326#define AR_XmitRate2_S 16
327#define AR_XmitRate3 0xff000000
328#define AR_XmitRate3_S 24
329
330#define AR_PacketDur0 0x00007fff
331#define AR_PacketDur0_S 0
332#define AR_RTSCTSQual0 0x00008000
333#define AR_PacketDur1 0x7fff0000
334#define AR_PacketDur1_S 16
335#define AR_RTSCTSQual1 0x80000000
336
337#define AR_PacketDur2 0x00007fff
338#define AR_PacketDur2_S 0
339#define AR_RTSCTSQual2 0x00008000
340#define AR_PacketDur3 0x7fff0000
341#define AR_PacketDur3_S 16
342#define AR_RTSCTSQual3 0x80000000
343
344#define AR_AggrLen 0x0000ffff
345#define AR_AggrLen_S 0
346#define AR_TxCtlRsvd60 0x00030000
347#define AR_PadDelim 0x03fc0000
348#define AR_PadDelim_S 18
349#define AR_EncrType 0x0c000000
350#define AR_EncrType_S 26
351#define AR_TxCtlRsvd61 0xf0000000
352
353#define AR_2040_0 0x00000001
354#define AR_GI0 0x00000002
355#define AR_ChainSel0 0x0000001c
356#define AR_ChainSel0_S 2
357#define AR_2040_1 0x00000020
358#define AR_GI1 0x00000040
359#define AR_ChainSel1 0x00000380
360#define AR_ChainSel1_S 7
361#define AR_2040_2 0x00000400
362#define AR_GI2 0x00000800
363#define AR_ChainSel2 0x00007000
364#define AR_ChainSel2_S 12
365#define AR_2040_3 0x00008000
366#define AR_GI3 0x00010000
367#define AR_ChainSel3 0x000e0000
368#define AR_ChainSel3_S 17
369#define AR_RTSCTSRate 0x0ff00000
370#define AR_RTSCTSRate_S 20
371#define AR_TxCtlRsvd70 0xf0000000
372
373#define AR_TxRSSIAnt00 0x000000ff
374#define AR_TxRSSIAnt00_S 0
375#define AR_TxRSSIAnt01 0x0000ff00
376#define AR_TxRSSIAnt01_S 8
377#define AR_TxRSSIAnt02 0x00ff0000
378#define AR_TxRSSIAnt02_S 16
379#define AR_TxStatusRsvd00 0x3f000000
380#define AR_TxBaStatus 0x40000000
381#define AR_TxStatusRsvd01 0x80000000
382
383#define AR_FrmXmitOK 0x00000001
384#define AR_ExcessiveRetries 0x00000002
385#define AR_FIFOUnderrun 0x00000004
386#define AR_Filtered 0x00000008
387#define AR_RTSFailCnt 0x000000f0
388#define AR_RTSFailCnt_S 4
389#define AR_DataFailCnt 0x00000f00
390#define AR_DataFailCnt_S 8
391#define AR_VirtRetryCnt 0x0000f000
392#define AR_VirtRetryCnt_S 12
393#define AR_TxDelimUnderrun 0x00010000
394#define AR_TxDataUnderrun 0x00020000
395#define AR_DescCfgErr 0x00040000
396#define AR_TxTimerExpired 0x00080000
397#define AR_TxStatusRsvd10 0xfff00000
398
399#define AR_SendTimestamp ds_txstatus2
400#define AR_BaBitmapLow ds_txstatus3
401#define AR_BaBitmapHigh ds_txstatus4
402
403#define AR_TxRSSIAnt10 0x000000ff
404#define AR_TxRSSIAnt10_S 0
405#define AR_TxRSSIAnt11 0x0000ff00
406#define AR_TxRSSIAnt11_S 8
407#define AR_TxRSSIAnt12 0x00ff0000
408#define AR_TxRSSIAnt12_S 16
409#define AR_TxRSSICombined 0xff000000
410#define AR_TxRSSICombined_S 24
411
412#define AR_TxEVM0 ds_txstatus5
413#define AR_TxEVM1 ds_txstatus6
414#define AR_TxEVM2 ds_txstatus7
415
416#define AR_TxDone 0x00000001
417#define AR_SeqNum 0x00001ffe
418#define AR_SeqNum_S 1
419#define AR_TxStatusRsvd80 0x0001e000
420#define AR_TxOpExceeded 0x00020000
421#define AR_TxStatusRsvd81 0x001c0000
422#define AR_FinalTxIdx 0x00600000
423#define AR_FinalTxIdx_S 21
424#define AR_TxStatusRsvd82 0x01800000
425#define AR_PowerMgmt 0x02000000
426#define AR_TxStatusRsvd83 0xfc000000
427
428#define AR_RxCTLRsvd00 0xffffffff
429
430#define AR_BufLen 0x00000fff
431#define AR_RxCtlRsvd00 0x00001000
432#define AR_RxIntrReq 0x00002000
433#define AR_RxCtlRsvd01 0xffffc000
434
435#define AR_RxRSSIAnt00 0x000000ff
436#define AR_RxRSSIAnt00_S 0
437#define AR_RxRSSIAnt01 0x0000ff00
438#define AR_RxRSSIAnt01_S 8
439#define AR_RxRSSIAnt02 0x00ff0000
440#define AR_RxRSSIAnt02_S 16
441#define AR_RxRate 0xff000000
442#define AR_RxRate_S 24
443#define AR_RxStatusRsvd00 0xff000000
444
445#define AR_DataLen 0x00000fff
446#define AR_RxMore 0x00001000
447#define AR_NumDelim 0x003fc000
448#define AR_NumDelim_S 14
449#define AR_RxStatusRsvd10 0xff800000
450
451#define AR_RcvTimestamp ds_rxstatus2
452
453#define AR_GI 0x00000001
454#define AR_2040 0x00000002
455#define AR_Parallel40 0x00000004
456#define AR_Parallel40_S 2
457#define AR_RxStatusRsvd30 0x000000f8
458#define AR_RxAntenna 0xffffff00
459#define AR_RxAntenna_S 8
460
461#define AR_RxRSSIAnt10 0x000000ff
462#define AR_RxRSSIAnt10_S 0
463#define AR_RxRSSIAnt11 0x0000ff00
464#define AR_RxRSSIAnt11_S 8
465#define AR_RxRSSIAnt12 0x00ff0000
466#define AR_RxRSSIAnt12_S 16
467#define AR_RxRSSICombined 0xff000000
468#define AR_RxRSSICombined_S 24
469
470#define AR_RxEVM0 ds_rxstatus4
471#define AR_RxEVM1 ds_rxstatus5
472#define AR_RxEVM2 ds_rxstatus6
473
474#define AR_RxDone 0x00000001
475#define AR_RxFrameOK 0x00000002
476#define AR_CRCErr 0x00000004
477#define AR_DecryptCRCErr 0x00000008
478#define AR_PHYErr 0x00000010
479#define AR_MichaelErr 0x00000020
480#define AR_PreDelimCRCErr 0x00000040
481#define AR_RxStatusRsvd70 0x00000080
482#define AR_RxKeyIdxValid 0x00000100
483#define AR_KeyIdx 0x0000fe00
484#define AR_KeyIdx_S 9
485#define AR_PHYErrCode 0x0000ff00
486#define AR_PHYErrCode_S 8
487#define AR_RxMoreAggr 0x00010000
488#define AR_RxAggr 0x00020000
489#define AR_PostDelimCRCErr 0x00040000
490#define AR_RxStatusRsvd71 0x3ff80000
491#define AR_DecryptBusyErr 0x40000000
492#define AR_KeyMiss 0x80000000
493
494enum ath9k_tx_queue {
495 ATH9K_TX_QUEUE_INACTIVE = 0,
496 ATH9K_TX_QUEUE_DATA,
497 ATH9K_TX_QUEUE_BEACON,
498 ATH9K_TX_QUEUE_CAB,
499 ATH9K_TX_QUEUE_UAPSD,
500 ATH9K_TX_QUEUE_PSPOLL
501};
502
503#define ATH9K_NUM_TX_QUEUES 10
504
505enum ath9k_tx_queue_subtype {
506 ATH9K_WME_AC_BK = 0,
507 ATH9K_WME_AC_BE,
508 ATH9K_WME_AC_VI,
509 ATH9K_WME_AC_VO,
510 ATH9K_WME_UPSD
511};
512
513enum ath9k_tx_queue_flags {
514 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
515 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
516 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
517 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
518 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
519 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
520 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
521 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
522 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
523};
524
525#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
526#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
527
528#define ATH9K_DECOMP_MASK_SIZE 128
529#define ATH9K_READY_TIME_LO_BOUND 50
530#define ATH9K_READY_TIME_HI_BOUND 96
531
532enum ath9k_pkt_type {
533 ATH9K_PKT_TYPE_NORMAL = 0,
534 ATH9K_PKT_TYPE_ATIM,
535 ATH9K_PKT_TYPE_PSPOLL,
536 ATH9K_PKT_TYPE_BEACON,
537 ATH9K_PKT_TYPE_PROBE_RESP,
538 ATH9K_PKT_TYPE_CHIRP,
539 ATH9K_PKT_TYPE_GRP_POLL,
540};
541
542struct ath9k_tx_queue_info {
543 u32 tqi_ver;
544 enum ath9k_tx_queue tqi_type;
545 enum ath9k_tx_queue_subtype tqi_subtype;
546 enum ath9k_tx_queue_flags tqi_qflags;
547 u32 tqi_priority;
548 u32 tqi_aifs;
549 u32 tqi_cwmin;
550 u32 tqi_cwmax;
551 u16 tqi_shretry;
552 u16 tqi_lgretry;
553 u32 tqi_cbrPeriod;
554 u32 tqi_cbrOverflowLimit;
555 u32 tqi_burstTime;
556 u32 tqi_readyTime;
557 u32 tqi_physCompBuf;
558 u32 tqi_intFlags;
559};
560
561enum ath9k_rx_filter {
562 ATH9K_RX_FILTER_UCAST = 0x00000001,
563 ATH9K_RX_FILTER_MCAST = 0x00000002,
564 ATH9K_RX_FILTER_BCAST = 0x00000004,
565 ATH9K_RX_FILTER_CONTROL = 0x00000008,
566 ATH9K_RX_FILTER_BEACON = 0x00000010,
567 ATH9K_RX_FILTER_PROM = 0x00000020,
568 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
569 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
570 ATH9K_RX_FILTER_PHYERR = 0x00000100,
571 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
572};
573
574#define ATH9K_RATESERIES_RTS_CTS 0x0001
575#define ATH9K_RATESERIES_2040 0x0002
576#define ATH9K_RATESERIES_HALFGI 0x0004
577
578struct ath9k_11n_rate_series {
579 u32 Tries;
580 u32 Rate;
581 u32 PktDuration;
582 u32 ChSel;
583 u32 RateFlags;
584};
585
586struct ath9k_keyval {
587 u8 kv_type;
588 u8 kv_pad;
589 u16 kv_len;
590 u8 kv_val[16];
591 u8 kv_mic[8];
592 u8 kv_txmic[8];
593};
594
595enum ath9k_key_type {
596 ATH9K_KEY_TYPE_CLEAR,
597 ATH9K_KEY_TYPE_WEP,
598 ATH9K_KEY_TYPE_AES,
599 ATH9K_KEY_TYPE_TKIP,
600};
601
602enum ath9k_cipher {
603 ATH9K_CIPHER_WEP = 0,
604 ATH9K_CIPHER_AES_OCB = 1,
605 ATH9K_CIPHER_AES_CCM = 2,
606 ATH9K_CIPHER_CKIP = 3,
607 ATH9K_CIPHER_TKIP = 4,
608 ATH9K_CIPHER_CLR = 5,
609 ATH9K_CIPHER_MIC = 127
610};
611
612enum ath9k_ht_macmode {
613 ATH9K_HT_MACMODE_20 = 0,
614 ATH9K_HT_MACMODE_2040 = 1,
615};
616
617enum ath9k_ht_extprotspacing {
618 ATH9K_HT_EXTPROTSPACING_20 = 0,
619 ATH9K_HT_EXTPROTSPACING_25 = 1,
620};
621
622struct ath_hal;
623struct ath9k_channel;
624struct ath_rate_table;
625
626u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
627bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q, u32 txdp);
628bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
629u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
630bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah, bool bIncTrigLevel);
631bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
632bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
633 u32 segLen, bool firstSeg,
634 bool lastSeg, const struct ath_desc *ds0);
635void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
636int ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds);
637void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
638 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
639 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
640void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
641 struct ath_desc *lastds,
642 u32 durUpdateEn, u32 rtsctsRate,
643 u32 rtsctsDuration,
644 struct ath9k_11n_rate_series series[],
645 u32 nseries, u32 flags);
646void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
647 u32 aggrLen);
648void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
649 u32 numDelims);
650void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
651void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
652void ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
653 u32 burstDuration);
654void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
655 u32 vmf);
656void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
657bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
658 const struct ath9k_tx_queue_info *qinfo);
659bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
660 struct ath9k_tx_queue_info *qinfo);
661int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
662 const struct ath9k_tx_queue_info *qinfo);
663bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
664bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
665int ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
666 u32 pa, struct ath_desc *nds, u64 tsf);
667bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
668 u32 size, u32 flags);
669bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
670void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
671void ath9k_hw_rxena(struct ath_hal *ah);
672void ath9k_hw_startpcureceive(struct ath_hal *ah);
673void ath9k_hw_stoppcurecv(struct ath_hal *ah);
674bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
675
676#endif /* MAC_H */
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c
index 4095fec5e047..2ed0bd28ffb7 100644
--- a/drivers/net/wireless/ath9k/main.c
+++ b/drivers/net/wireless/ath9k/main.c
@@ -15,9 +15,7 @@
15 */ 15 */
16 16
17#include <linux/nl80211.h> 17#include <linux/nl80211.h>
18#include "core.h" 18#include "ath9k.h"
19#include "reg.h"
20#include "hw.h"
21 19
22#define ATH_PCI_VERSION "0.1" 20#define ATH_PCI_VERSION "0.1"
23 21
diff --git a/drivers/net/wireless/ath9k/pci.c b/drivers/net/wireless/ath9k/pci.c
index 05612bf28360..aa3ac20b410c 100644
--- a/drivers/net/wireless/ath9k/pci.c
+++ b/drivers/net/wireless/ath9k/pci.c
@@ -16,9 +16,7 @@
16 16
17#include <linux/nl80211.h> 17#include <linux/nl80211.h>
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include "core.h" 19#include "ath9k.h"
20#include "reg.h"
21#include "hw.h"
22 20
23static struct pci_device_id ath_pci_id_table[] __devinitdata = { 21static struct pci_device_id ath_pci_id_table[] __devinitdata = {
24 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ 22 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
diff --git a/drivers/net/wireless/ath9k/phy.c b/drivers/net/wireless/ath9k/phy.c
index 766982a8196e..ea29941412d4 100644
--- a/drivers/net/wireless/ath9k/phy.c
+++ b/drivers/net/wireless/ath9k/phy.c
@@ -14,10 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18#include "hw.h"
19#include "reg.h"
20#include "phy.h"
21 18
22void 19void
23ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex, 20ath9k_hw_write_regs(struct ath_hal *ah, u32 modesIndex, u32 freqIndex,
diff --git a/drivers/net/wireless/ath9k/rc.c b/drivers/net/wireless/ath9k/rc.c
index 69a4ca46ce90..060a7cf6f75a 100644
--- a/drivers/net/wireless/ath9k/rc.c
+++ b/drivers/net/wireless/ath9k/rc.c
@@ -15,7 +15,7 @@
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */ 16 */
17 17
18#include "core.h" 18#include "ath9k.h"
19 19
20static struct ath_rate_table ar5416_11na_ratetable = { 20static struct ath_rate_table ar5416_11na_ratetable = {
21 42, 21 42,
diff --git a/drivers/net/wireless/ath9k/rc.h b/drivers/net/wireless/ath9k/rc.h
index a987cb9e74e2..d688ec51a14f 100644
--- a/drivers/net/wireless/ath9k/rc.h
+++ b/drivers/net/wireless/ath9k/rc.h
@@ -19,13 +19,12 @@
19#ifndef RC_H 19#ifndef RC_H
20#define RC_H 20#define RC_H
21 21
22#include "ath9k.h"
23
24struct ath_softc; 22struct ath_softc;
25 23
26#define ATH_RATE_MAX 30 24#define ATH_RATE_MAX 30
27#define RATE_TABLE_SIZE 64 25#define RATE_TABLE_SIZE 64
28#define MAX_TX_RATE_PHY 48 26#define MAX_TX_RATE_PHY 48
27#define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
29 28
30/* VALID_ALL - valid for 20/40/Legacy, 29/* VALID_ALL - valid for 20/40/Legacy,
31 * VALID - Legacy only, 30 * VALID - Legacy only,
@@ -39,6 +38,20 @@ struct ath_softc;
39#define VALID_2040 (VALID_20|VALID_40) 38#define VALID_2040 (VALID_20|VALID_40)
40#define VALID_ALL (VALID_2040|VALID) 39#define VALID_ALL (VALID_2040|VALID)
41 40
41enum {
42 WLAN_RC_PHY_OFDM,
43 WLAN_RC_PHY_CCK,
44 WLAN_RC_PHY_HT_20_SS,
45 WLAN_RC_PHY_HT_20_DS,
46 WLAN_RC_PHY_HT_40_SS,
47 WLAN_RC_PHY_HT_40_DS,
48 WLAN_RC_PHY_HT_20_SS_HGI,
49 WLAN_RC_PHY_HT_20_DS_HGI,
50 WLAN_RC_PHY_HT_40_SS_HGI,
51 WLAN_RC_PHY_HT_40_DS_HGI,
52 WLAN_RC_PHY_MAX
53};
54
42#define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \ 55#define WLAN_RC_PHY_DS(_phy) ((_phy == WLAN_RC_PHY_HT_20_DS) \
43 || (_phy == WLAN_RC_PHY_HT_40_DS) \ 56 || (_phy == WLAN_RC_PHY_HT_40_DS) \
44 || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \ 57 || (_phy == WLAN_RC_PHY_HT_20_DS_HGI) \
diff --git a/drivers/net/wireless/ath9k/recv.c b/drivers/net/wireless/ath9k/recv.c
index 630fa57f14ed..69dd5e206270 100644
--- a/drivers/net/wireless/ath9k/recv.c
+++ b/drivers/net/wireless/ath9k/recv.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18 18
19/* 19/*
20 * Setup and link descriptors. 20 * Setup and link descriptors.
diff --git a/drivers/net/wireless/ath9k/reg.h b/drivers/net/wireless/ath9k/reg.h
index c967b7926e33..45b9fbfb542a 100644
--- a/drivers/net/wireless/ath9k/reg.h
+++ b/drivers/net/wireless/ath9k/reg.h
@@ -160,6 +160,7 @@
160 160
161#define AR_SREV_VERSION_9100 0x014 161#define AR_SREV_VERSION_9100 0x014
162 162
163#define AR_SREV_9100(ah) ((ah->ah_macVersion) == AR_SREV_VERSION_9100)
163#define AR_SREV_5416_V20_OR_LATER(_ah) \ 164#define AR_SREV_5416_V20_OR_LATER(_ah) \
164 (AR_SREV_9100((_ah)) || AR_SREV_5416_20_OR_LATER(_ah)) 165 (AR_SREV_9100((_ah)) || AR_SREV_5416_20_OR_LATER(_ah))
165#define AR_SREV_5416_V22_OR_LATER(_ah) \ 166#define AR_SREV_5416_V22_OR_LATER(_ah) \
diff --git a/drivers/net/wireless/ath9k/regd.c b/drivers/net/wireless/ath9k/regd.c
index fe08a4fdf770..819feb963821 100644
--- a/drivers/net/wireless/ath9k/regd.c
+++ b/drivers/net/wireless/ath9k/regd.c
@@ -16,9 +16,7 @@
16 16
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include "core.h" 19#include "ath9k.h"
20#include "hw.h"
21#include "regd.h"
22#include "regd_common.h" 20#include "regd_common.h"
23 21
24/* 22/*
diff --git a/drivers/net/wireless/ath9k/regd.h b/drivers/net/wireless/ath9k/regd.h
index ba2d2dfb0d1f..d1c4457de436 100644
--- a/drivers/net/wireless/ath9k/regd.h
+++ b/drivers/net/wireless/ath9k/regd.h
@@ -17,8 +17,6 @@
17#ifndef REGD_H 17#ifndef REGD_H
18#define REGD_H 18#define REGD_H
19 19
20#include "ath9k.h"
21
22#define COUNTRY_ERD_FLAG 0x8000 20#define COUNTRY_ERD_FLAG 0x8000
23#define WORLDWIDE_ROAMING_FLAG 0x4000 21#define WORLDWIDE_ROAMING_FLAG 0x4000
24 22
@@ -229,6 +227,16 @@ enum CountryCode {
229 CTRY_BELGIUM2 = 5002 227 CTRY_BELGIUM2 = 5002
230}; 228};
231 229
230u16 ath9k_regd_get_rd(struct ath_hal *ah);
231bool ath9k_is_world_regd(struct ath_hal *ah);
232const struct ieee80211_regdomain *ath9k_world_regdomain(struct ath_hal *ah);
233const struct ieee80211_regdomain *ath9k_default_world_regdomain(void);
234void ath9k_reg_apply_world_flags(struct wiphy *wiphy, enum reg_set_by setby);
235void ath9k_reg_apply_radar_flags(struct wiphy *wiphy);
236int ath9k_regd_init(struct ath_hal *ah);
237bool ath9k_regd_is_eeprom_valid(struct ath_hal *ah);
238u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
239int ath9k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request);
232void ath9k_regd_get_current_country(struct ath_hal *ah, 240void ath9k_regd_get_current_country(struct ath_hal *ah,
233 struct ath9k_country_entry *ctry); 241 struct ath9k_country_entry *ctry);
234 242
diff --git a/drivers/net/wireless/ath9k/xmit.c b/drivers/net/wireless/ath9k/xmit.c
index d5f15e74854f..7a3ea92e2ee6 100644
--- a/drivers/net/wireless/ath9k/xmit.c
+++ b/drivers/net/wireless/ath9k/xmit.c
@@ -14,7 +14,7 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17#include "core.h" 17#include "ath9k.h"
18 18
19#define BITS_PER_BYTE 8 19#define BITS_PER_BYTE 8
20#define OFDM_PLCP_BITS 22 20#define OFDM_PLCP_BITS 22
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 22:21:56 -0400