diff options
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/tg3.c | 16 | ||||
-rw-r--r-- | drivers/net/tg3.h | 2 |
2 files changed, 11 insertions, 7 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 65ff286b508a..ff65ae8b592e 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -631,7 +631,7 @@ static void tg3_enable_ints(struct tg3 *tp) | |||
631 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | 631 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
632 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | 632 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
633 | 633 | ||
634 | coal_now = HOSTCC_MODE_NOW; | 634 | coal_now = tnapi->coal_now; |
635 | 635 | ||
636 | /* Force an initial interrupt */ | 636 | /* Force an initial interrupt */ |
637 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | 637 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && |
@@ -682,7 +682,7 @@ static void tg3_int_reenable(struct tg3_napi *tnapi) | |||
682 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | 682 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && |
683 | tg3_has_work(tnapi)) | 683 | tg3_has_work(tnapi)) |
684 | tw32(HOSTCC_MODE, tp->coalesce_mode | | 684 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
685 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | 685 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
686 | } | 686 | } |
687 | 687 | ||
688 | static inline void tg3_netif_stop(struct tg3 *tp) | 688 | static inline void tg3_netif_stop(struct tg3 *tp) |
@@ -7622,7 +7622,7 @@ static void tg3_timer(unsigned long __opaque) | |||
7622 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | 7622 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); |
7623 | } else { | 7623 | } else { |
7624 | tw32(HOSTCC_MODE, tp->coalesce_mode | | 7624 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
7625 | (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW)); | 7625 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
7626 | } | 7626 | } |
7627 | 7627 | ||
7628 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | 7628 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
@@ -7765,7 +7765,7 @@ static int tg3_test_interrupt(struct tg3 *tp) | |||
7765 | tg3_enable_ints(tp); | 7765 | tg3_enable_ints(tp); |
7766 | 7766 | ||
7767 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | 7767 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
7768 | HOSTCC_MODE_NOW); | 7768 | tnapi->coal_now); |
7769 | 7769 | ||
7770 | for (i = 0; i < 5; i++) { | 7770 | for (i = 0; i < 5; i++) { |
7771 | u32 int_mbox, misc_host_ctrl; | 7771 | u32 int_mbox, misc_host_ctrl; |
@@ -9840,7 +9840,7 @@ static int tg3_test_memory(struct tg3 *tp) | |||
9840 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | 9840 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) |
9841 | { | 9841 | { |
9842 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; | 9842 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
9843 | u32 desc_idx; | 9843 | u32 desc_idx, coal_now; |
9844 | struct sk_buff *skb, *rx_skb; | 9844 | struct sk_buff *skb, *rx_skb; |
9845 | u8 *tx_data; | 9845 | u8 *tx_data; |
9846 | dma_addr_t map; | 9846 | dma_addr_t map; |
@@ -9851,6 +9851,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
9851 | 9851 | ||
9852 | tnapi = &tp->napi[0]; | 9852 | tnapi = &tp->napi[0]; |
9853 | rnapi = &tp->napi[0]; | 9853 | rnapi = &tp->napi[0]; |
9854 | coal_now = tnapi->coal_now | rnapi->coal_now; | ||
9854 | 9855 | ||
9855 | if (loopback_mode == TG3_MAC_LOOPBACK) { | 9856 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
9856 | /* HW errata - mac loopback fails in some cases on 5780. | 9857 | /* HW errata - mac loopback fails in some cases on 5780. |
@@ -9929,7 +9930,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
9929 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); | 9930 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
9930 | 9931 | ||
9931 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | 9932 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
9932 | HOSTCC_MODE_NOW); | 9933 | rnapi->coal_now); |
9933 | 9934 | ||
9934 | udelay(10); | 9935 | udelay(10); |
9935 | 9936 | ||
@@ -9950,7 +9951,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
9950 | /* 250 usec to allow enough time on some 10/100 Mbps devices. */ | 9951 | /* 250 usec to allow enough time on some 10/100 Mbps devices. */ |
9951 | for (i = 0; i < 25; i++) { | 9952 | for (i = 0; i < 25; i++) { |
9952 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | 9953 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
9953 | HOSTCC_MODE_NOW); | 9954 | coal_now); |
9954 | 9955 | ||
9955 | udelay(10); | 9956 | udelay(10); |
9956 | 9957 | ||
@@ -13428,6 +13429,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev, | |||
13428 | tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; | 13429 | tp->napi[0].int_mbox = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
13429 | tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | 13430 | tp->napi[0].consmbox = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; |
13430 | tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | 13431 | tp->napi[0].prodmbox = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; |
13432 | tp->napi[0].coal_now = HOSTCC_MODE_NOW; | ||
13431 | tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING; | 13433 | tp->napi[0].tx_pending = TG3_DEF_TX_RING_PENDING; |
13432 | netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); | 13434 | netif_napi_add(dev, &tp->napi[0].napi, tg3_poll, 64); |
13433 | dev->ethtool_ops = &tg3_ethtool_ops; | 13435 | dev->ethtool_ops = &tg3_ethtool_ops; |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index a816b2c0f167..626b96805c3e 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -1031,6 +1031,7 @@ | |||
1031 | #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 | 1031 | #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 |
1032 | #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 | 1032 | #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 |
1033 | #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 | 1033 | #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 |
1034 | #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 | ||
1034 | #define HOSTCC_STATUS 0x00003c04 | 1035 | #define HOSTCC_STATUS 0x00003c04 |
1035 | #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 | 1036 | #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 |
1036 | #define HOSTCC_RXCOL_TICKS 0x00003c08 | 1037 | #define HOSTCC_RXCOL_TICKS 0x00003c08 |
@@ -2497,6 +2498,7 @@ struct tg3_napi { | |||
2497 | u32 last_tag; | 2498 | u32 last_tag; |
2498 | u32 last_irq_tag; | 2499 | u32 last_irq_tag; |
2499 | u32 int_mbox; | 2500 | u32 int_mbox; |
2501 | u32 coal_now; | ||
2500 | u32 tx_prod; | 2502 | u32 tx_prod; |
2501 | u32 tx_cons; | 2503 | u32 tx_cons; |
2502 | u32 tx_pending; | 2504 | u32 tx_pending; |