aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/b43/main.c50
-rw-r--r--drivers/net/wireless/b43/phy_n.c347
-rw-r--r--drivers/net/wireless/mwifiex/sdio.c1
3 files changed, 279 insertions, 119 deletions
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 3e127be06bfb..47b6fa5fa5b2 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -4385,8 +4385,9 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4385 u8 phy_type; 4385 u8 phy_type;
4386 u8 phy_rev; 4386 u8 phy_rev;
4387 u16 radio_manuf; 4387 u16 radio_manuf;
4388 u16 radio_ver; 4388 u16 radio_id;
4389 u16 radio_rev; 4389 u16 radio_rev;
4390 u8 radio_ver;
4390 int unsupported = 0; 4391 int unsupported = 0;
4391 4392
4392 /* Get PHY versioning */ 4393 /* Get PHY versioning */
@@ -4452,7 +4453,9 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4452 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4453 radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4453 4454
4454 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 1); 4455 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 1);
4455 radio_ver = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4456 radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4457
4458 radio_ver = 0; /* Is there version somewhere? */
4456 } else if (core_rev >= 24) { 4459 } else if (core_rev >= 24) {
4457 u16 radio24[3]; 4460 u16 radio24[3];
4458 4461
@@ -4461,12 +4464,10 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4461 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA); 4464 radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
4462 } 4465 }
4463 4466
4464 /* Broadcom uses "id" for our "ver" and has separated "ver" */
4465 /* radio_ver = (radio24[0] & 0xF0) >> 4; */
4466
4467 radio_manuf = 0x17F; 4467 radio_manuf = 0x17F;
4468 radio_ver = (radio24[2] << 8) | radio24[1]; 4468 radio_id = (radio24[2] << 8) | radio24[1];
4469 radio_rev = (radio24[0] & 0xF); 4469 radio_rev = (radio24[0] & 0xF);
4470 radio_ver = (radio24[0] & 0xF0) >> 4;
4470 } else { 4471 } else {
4471 if (dev->dev->chip_id == 0x4317) { 4472 if (dev->dev->chip_id == 0x4317) {
4472 if (dev->dev->chip_rev == 0) 4473 if (dev->dev->chip_rev == 0)
@@ -4485,15 +4486,16 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4485 << 16; 4486 << 16;
4486 } 4487 }
4487 radio_manuf = (tmp & 0x00000FFF); 4488 radio_manuf = (tmp & 0x00000FFF);
4488 radio_ver = (tmp & 0x0FFFF000) >> 12; 4489 radio_id = (tmp & 0x0FFFF000) >> 12;
4489 radio_rev = (tmp & 0xF0000000) >> 28; 4490 radio_rev = (tmp & 0xF0000000) >> 28;
4491 radio_ver = 0; /* Probably not available on old hw */
4490 } 4492 }
4491 4493
4492 if (radio_manuf != 0x17F /* Broadcom */) 4494 if (radio_manuf != 0x17F /* Broadcom */)
4493 unsupported = 1; 4495 unsupported = 1;
4494 switch (phy_type) { 4496 switch (phy_type) {
4495 case B43_PHYTYPE_A: 4497 case B43_PHYTYPE_A:
4496 if (radio_ver != 0x2060) 4498 if (radio_id != 0x2060)
4497 unsupported = 1; 4499 unsupported = 1;
4498 if (radio_rev != 1) 4500 if (radio_rev != 1)
4499 unsupported = 1; 4501 unsupported = 1;
@@ -4501,30 +4503,31 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4501 unsupported = 1; 4503 unsupported = 1;
4502 break; 4504 break;
4503 case B43_PHYTYPE_B: 4505 case B43_PHYTYPE_B:
4504 if ((radio_ver & 0xFFF0) != 0x2050) 4506 if ((radio_id & 0xFFF0) != 0x2050)
4505 unsupported = 1; 4507 unsupported = 1;
4506 break; 4508 break;
4507 case B43_PHYTYPE_G: 4509 case B43_PHYTYPE_G:
4508 if (radio_ver != 0x2050) 4510 if (radio_id != 0x2050)
4509 unsupported = 1; 4511 unsupported = 1;
4510 break; 4512 break;
4511 case B43_PHYTYPE_N: 4513 case B43_PHYTYPE_N:
4512 if (radio_ver != 0x2055 && radio_ver != 0x2056 && 4514 if (radio_id != 0x2055 && radio_id != 0x2056 &&
4513 radio_ver != 0x2057) 4515 radio_id != 0x2057)
4514 unsupported = 1; 4516 unsupported = 1;
4515 if (radio_ver == 0x2057 && !(radio_rev == 9)) 4517 if (radio_id == 0x2057 &&
4518 !(radio_rev == 9 || radio_rev == 14))
4516 unsupported = 1; 4519 unsupported = 1;
4517 break; 4520 break;
4518 case B43_PHYTYPE_LP: 4521 case B43_PHYTYPE_LP:
4519 if (radio_ver != 0x2062 && radio_ver != 0x2063) 4522 if (radio_id != 0x2062 && radio_id != 0x2063)
4520 unsupported = 1; 4523 unsupported = 1;
4521 break; 4524 break;
4522 case B43_PHYTYPE_HT: 4525 case B43_PHYTYPE_HT:
4523 if (radio_ver != 0x2059) 4526 if (radio_id != 0x2059)
4524 unsupported = 1; 4527 unsupported = 1;
4525 break; 4528 break;
4526 case B43_PHYTYPE_LCN: 4529 case B43_PHYTYPE_LCN:
4527 if (radio_ver != 0x2064) 4530 if (radio_id != 0x2064)
4528 unsupported = 1; 4531 unsupported = 1;
4529 break; 4532 break;
4530 default: 4533 default:
@@ -4532,15 +4535,17 @@ static int b43_phy_versioning(struct b43_wldev *dev)
4532 } 4535 }
4533 if (unsupported) { 4536 if (unsupported) {
4534 b43err(dev->wl, 4537 b43err(dev->wl,
4535 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u)\n", 4538 "FOUND UNSUPPORTED RADIO (Manuf 0x%X, ID 0x%X, Revision %u, Version %u)\n",
4536 radio_manuf, radio_ver, radio_rev); 4539 radio_manuf, radio_id, radio_rev, radio_ver);
4537 return -EOPNOTSUPP; 4540 return -EOPNOTSUPP;
4538 } 4541 }
4539 b43info(dev->wl, "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u\n", 4542 b43info(dev->wl,
4540 radio_manuf, radio_ver, radio_rev); 4543 "Found Radio: Manuf 0x%X, ID 0x%X, Revision %u, Version %u\n",
4544 radio_manuf, radio_id, radio_rev, radio_ver);
4541 4545
4546 /* FIXME: b43 treats "id" as "ver" and ignores the real "ver" */
4542 phy->radio_manuf = radio_manuf; 4547 phy->radio_manuf = radio_manuf;
4543 phy->radio_ver = radio_ver; 4548 phy->radio_ver = radio_id;
4544 phy->radio_rev = radio_rev; 4549 phy->radio_rev = radio_rev;
4545 4550
4546 phy->analog = analog_type; 4551 phy->analog = analog_type;
@@ -5152,7 +5157,8 @@ static int b43_setup_bands(struct b43_wldev *dev,
5152 bool limited_2g; 5157 bool limited_2g;
5153 5158
5154 /* We don't support all 2 GHz channels on some devices */ 5159 /* We don't support all 2 GHz channels on some devices */
5155 limited_2g = phy->radio_ver == 0x2057 && phy->radio_rev == 9; 5160 limited_2g = phy->radio_ver == 0x2057 &&
5161 (phy->radio_rev == 9 || phy->radio_rev == 14);
5156 5162
5157 if (have_2ghz_phy) 5163 if (have_2ghz_phy)
5158 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ? 5164 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = limited_2g ?
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 92bfe352ba08..11d754360d71 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -2708,25 +2708,39 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2708 struct ssb_sprom *sprom = dev->dev->bus_sprom; 2708 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2709 struct b43_phy *phy = &dev->phy; 2709 struct b43_phy *phy = &dev->phy;
2710 2710
2711 /* TX to RX */
2712 u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, };
2713 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, };
2714 /* RX to TX */
2711 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 2715 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2712 0x1F }; 2716 0x1F };
2713 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; 2717 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2714 2718
2715 u16 ntab7_15e_16e[] = { 0x10f, 0x10f }; 2719 static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f };
2716 u8 ntab7_138_146[] = { 0x11, 0x11 }; 2720 u8 ntab7_138_146[] = { 0x11, 0x11 };
2717 u8 ntab7_133[] = { 0x77, 0x11, 0x11 }; 2721 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2718 2722
2719 u16 lpf_20, lpf_40, lpf_11b; 2723 u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2];
2720 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40; 2724 u16 bcap_val;
2721 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40; 2725 s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2];
2726 u16 scap_val;
2727 s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2];
2722 bool rccal_ovrd = false; 2728 bool rccal_ovrd = false;
2723 2729
2724 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2725 u16 bias, conv, filt; 2730 u16 bias, conv, filt;
2726 2731
2732 u32 noise_tbl[2];
2733
2727 u32 tmp32; 2734 u32 tmp32;
2728 u8 core; 2735 u8 core;
2729 2736
2737 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2738 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3);
2739 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2740 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e);
2741 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd);
2742 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2743
2730 if (phy->rev == 7) { 2744 if (phy->rev == 7) {
2731 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); 2745 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2732 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); 2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
@@ -2746,11 +2760,18 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); 2760 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2747 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); 2761 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2748 } 2762 }
2749 if (phy->rev <= 8) { 2763
2764 if (phy->rev >= 16) {
2765 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff);
2766 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff);
2767 } else if (phy->rev <= 8) {
2750 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); 2768 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2751 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); 2769 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2752 } 2770 }
2753 if (phy->rev >= 8) 2771
2772 if (phy->rev >= 16)
2773 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0);
2774 else if (phy->rev >= 8)
2754 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); 2775 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2755 2776
2756 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); 2777 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
@@ -2758,9 +2779,11 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2758 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 2779 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2759 tmp32 &= 0xffffff; 2780 tmp32 &= 0xffffff;
2760 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); 2781 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2761 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e); 2782 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e);
2762 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e); 2783 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e);
2763 2784
2785 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2786 ARRAY_SIZE(tx2rx_events));
2764 if (b43_nphy_ipa(dev)) 2787 if (b43_nphy_ipa(dev))
2765 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 2788 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2766 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 2789 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
@@ -2768,84 +2791,176 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2768 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); 2791 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2769 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); 2792 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2770 2793
2771 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154); 2794 for (core = 0; core < 2; core++) {
2772 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159); 2795 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10);
2773 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152); 2796 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10);
2797 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10);
2798 }
2799
2800 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL);
2801 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL);
2802
2774 if (b43_nphy_ipa(dev)) { 2803 if (b43_nphy_ipa(dev)) {
2775 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) || 2804 bool ghz2 = b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ;
2776 phy->radio_rev == 7 || phy->radio_rev == 8) { 2805
2777 bcap_val = b43_radio_read(dev, 0x16b); 2806 switch (phy->radio_rev) {
2778 scap_val = b43_radio_read(dev, 0x16a); 2807 case 5:
2779 scap_val_11b = scap_val; 2808 /* Check radio version (to be 0) by PHY rev for now */
2780 bcap_val_11b = bcap_val; 2809 if (phy->rev == 8 && b43_is_40mhz(dev)) {
2781 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) { 2810 for (core = 0; core < 2; core++) {
2782 scap_val_11n_20 = scap_val; 2811 scap_val_11b[core] = scap_val;
2783 bcap_val_11n_20 = bcap_val; 2812 bcap_val_11b[core] = bcap_val;
2784 scap_val_11n_40 = bcap_val_11n_40 = 0xc; 2813 scap_val_11n_20[core] = scap_val;
2814 bcap_val_11n_20[core] = bcap_val;
2815 scap_val_11n_40[core] = 0xc;
2816 bcap_val_11n_40[core] = 0xc;
2817 }
2818
2785 rccal_ovrd = true; 2819 rccal_ovrd = true;
2786 } else { /* Rev 7/8 */ 2820 }
2787 lpf_20 = 4; 2821 if (phy->rev == 9) {
2788 lpf_11b = 1; 2822 /* TODO: Radio version 1 (e.g. BCM5357B0) */
2823 }
2824 break;
2825 case 7:
2826 case 8:
2827 for (core = 0; core < 2; core++) {
2828 scap_val_11b[core] = scap_val;
2829 bcap_val_11b[core] = bcap_val;
2830 lpf_ofdm_20mhz[core] = 4;
2831 lpf_11b[core] = 1;
2789 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2832 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2790 scap_val_11n_20 = 0xc; 2833 scap_val_11n_20[core] = 0xc;
2791 bcap_val_11n_20 = 0xc; 2834 bcap_val_11n_20[core] = 0xc;
2792 scap_val_11n_40 = 0xa; 2835 scap_val_11n_40[core] = 0xa;
2793 bcap_val_11n_40 = 0xa; 2836 bcap_val_11n_40[core] = 0xa;
2794 } else { 2837 } else {
2795 scap_val_11n_20 = 0x14; 2838 scap_val_11n_20[core] = 0x14;
2796 bcap_val_11n_20 = 0x14; 2839 bcap_val_11n_20[core] = 0x14;
2797 scap_val_11n_40 = 0xf; 2840 scap_val_11n_40[core] = 0xf;
2798 bcap_val_11n_40 = 0xf; 2841 bcap_val_11n_40[core] = 0xf;
2799 } 2842 }
2800 rccal_ovrd = true;
2801 } 2843 }
2844
2845 rccal_ovrd = true;
2846 break;
2847 case 9:
2848 for (core = 0; core < 2; core++) {
2849 bcap_val_11b[core] = bcap_val;
2850 scap_val_11b[core] = scap_val;
2851 lpf_11b[core] = 1;
2852
2853 if (ghz2) {
2854 bcap_val_11n_20[core] = bcap_val + 13;
2855 scap_val_11n_20[core] = scap_val + 15;
2856 } else {
2857 bcap_val_11n_20[core] = bcap_val + 14;
2858 scap_val_11n_20[core] = scap_val + 15;
2859 }
2860 lpf_ofdm_20mhz[core] = 4;
2861
2862 if (ghz2) {
2863 bcap_val_11n_40[core] = bcap_val - 7;
2864 scap_val_11n_40[core] = scap_val - 5;
2865 } else {
2866 bcap_val_11n_40[core] = bcap_val + 2;
2867 scap_val_11n_40[core] = scap_val + 4;
2868 }
2869 lpf_ofdm_40mhz[core] = 4;
2870 }
2871
2872 rccal_ovrd = true;
2873 break;
2874 case 14:
2875 for (core = 0; core < 2; core++) {
2876 bcap_val_11b[core] = bcap_val;
2877 scap_val_11b[core] = scap_val;
2878 lpf_11b[core] = 1;
2879 }
2880
2881 bcap_val_11n_20[0] = bcap_val + 20;
2882 scap_val_11n_20[0] = scap_val + 20;
2883 lpf_ofdm_20mhz[0] = 3;
2884
2885 bcap_val_11n_20[1] = bcap_val + 16;
2886 scap_val_11n_20[1] = scap_val + 16;
2887 lpf_ofdm_20mhz[1] = 3;
2888
2889 bcap_val_11n_40[0] = bcap_val + 20;
2890 scap_val_11n_40[0] = scap_val + 20;
2891 lpf_ofdm_40mhz[0] = 4;
2892
2893 bcap_val_11n_40[1] = bcap_val + 10;
2894 scap_val_11n_40[1] = scap_val + 10;
2895 lpf_ofdm_40mhz[1] = 4;
2896
2897 rccal_ovrd = true;
2898 break;
2802 } 2899 }
2803 } else { 2900 } else {
2804 if (phy->radio_rev == 5) { 2901 if (phy->radio_rev == 5) {
2805 lpf_20 = 1; 2902 for (core = 0; core < 2; core++) {
2806 lpf_40 = 3; 2903 lpf_ofdm_20mhz[core] = 1;
2807 bcap_val = b43_radio_read(dev, 0x16b); 2904 lpf_ofdm_40mhz[core] = 3;
2808 scap_val = b43_radio_read(dev, 0x16a); 2905 scap_val_11b[core] = scap_val;
2809 scap_val_11b = scap_val; 2906 bcap_val_11b[core] = bcap_val;
2810 bcap_val_11b = bcap_val; 2907 scap_val_11n_20[core] = 0x11;
2811 scap_val_11n_20 = 0x11; 2908 scap_val_11n_40[core] = 0x11;
2812 scap_val_11n_40 = 0x11; 2909 bcap_val_11n_20[core] = 0x13;
2813 bcap_val_11n_20 = 0x13; 2910 bcap_val_11n_40[core] = 0x13;
2814 bcap_val_11n_40 = 0x13; 2911 }
2912
2815 rccal_ovrd = true; 2913 rccal_ovrd = true;
2816 } 2914 }
2817 } 2915 }
2818 if (rccal_ovrd) { 2916 if (rccal_ovrd) {
2819 rx2tx_lut_20_11b = (bcap_val_11b << 8) | 2917 u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2];
2820 (scap_val_11b << 3) | 2918 u8 rx2tx_lut_extra = 1;
2821 lpf_11b; 2919
2822 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) | 2920 for (core = 0; core < 2; core++) {
2823 (scap_val_11n_20 << 3) | 2921 bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f);
2824 lpf_20; 2922 scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f);
2825 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) | 2923 bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f);
2826 (scap_val_11n_40 << 3) | 2924 scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f);
2827 lpf_40; 2925 bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f);
2926 scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f);
2927
2928 rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) |
2929 (bcap_val_11b[core] << 8) |
2930 (scap_val_11b[core] << 3) |
2931 lpf_11b[core];
2932 rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) |
2933 (bcap_val_11n_20[core] << 8) |
2934 (scap_val_11n_20[core] << 3) |
2935 lpf_ofdm_20mhz[core];
2936 rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) |
2937 (bcap_val_11n_40[core] << 8) |
2938 (scap_val_11n_40[core] << 3) |
2939 lpf_ofdm_40mhz[core];
2940 }
2941
2828 for (core = 0; core < 2; core++) { 2942 for (core = 0; core < 2; core++) {
2829 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), 2943 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2830 rx2tx_lut_20_11b); 2944 rx2tx_lut_20_11b[core]);
2831 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), 2945 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2832 rx2tx_lut_20_11n); 2946 rx2tx_lut_20_11n[core]);
2833 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), 2947 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2834 rx2tx_lut_20_11n); 2948 rx2tx_lut_20_11n[core]);
2835 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), 2949 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2836 rx2tx_lut_40_11n); 2950 rx2tx_lut_40_11n[core]);
2837 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), 2951 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2838 rx2tx_lut_40_11n); 2952 rx2tx_lut_40_11n[core]);
2839 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), 2953 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2840 rx2tx_lut_40_11n); 2954 rx2tx_lut_40_11n[core]);
2841 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), 2955 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2842 rx2tx_lut_40_11n); 2956 rx2tx_lut_40_11n[core]);
2843 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), 2957 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2844 rx2tx_lut_40_11n); 2958 rx2tx_lut_40_11n[core]);
2845 } 2959 }
2846 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
2847 } 2960 }
2961
2848 b43_phy_write(dev, 0x32F, 0x3); 2962 b43_phy_write(dev, 0x32F, 0x3);
2963
2849 if (phy->radio_rev == 4 || phy->radio_rev == 6) 2964 if (phy->radio_rev == 4 || phy->radio_rev == 6)
2850 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); 2965 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
2851 2966
@@ -2893,7 +3008,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2893 0x7f); 3008 0x7f);
2894 } 3009 }
2895 } 3010 }
2896 if (phy->radio_rev == 3) { 3011 switch (phy->radio_rev) {
3012 case 3:
2897 for (core = 0; core < 2; core++) { 3013 for (core = 0; core < 2; core++) {
2898 if (core == 0) { 3014 if (core == 0) {
2899 b43_radio_write(dev, 0x64, 3015 b43_radio_write(dev, 0x64,
@@ -2919,7 +3035,9 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2919 0x3E); 3035 0x3E);
2920 } 3036 }
2921 } 3037 }
2922 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) { 3038 break;
3039 case 7:
3040 case 8:
2923 if (!b43_is_40mhz(dev)) { 3041 if (!b43_is_40mhz(dev)) {
2924 b43_radio_write(dev, 0x5F, 0x14); 3042 b43_radio_write(dev, 0x5F, 0x14);
2925 b43_radio_write(dev, 0xE8, 0x12); 3043 b43_radio_write(dev, 0xE8, 0x12);
@@ -2927,6 +3045,21 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2927 b43_radio_write(dev, 0x5F, 0x16); 3045 b43_radio_write(dev, 0x5F, 0x16);
2928 b43_radio_write(dev, 0xE8, 0x16); 3046 b43_radio_write(dev, 0xE8, 0x16);
2929 } 3047 }
3048 break;
3049 case 14:
3050 for (core = 0; core < 2; core++) {
3051 int o = core ? 0x85 : 0;
3052
3053 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13);
3054 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21);
3055 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff);
3056 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88);
3057 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23);
3058 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16);
3059 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e);
3060 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10);
3061 }
3062 break;
2930 } 3063 }
2931 } else { 3064 } else {
2932 u16 freq = phy->chandef->chan->center_freq; 3065 u16 freq = phy->chandef->chan->center_freq;
@@ -2974,8 +3107,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2974 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); 3107 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2975 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); 3108 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2976 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); 3109 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2977 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); 3110 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0);
2978 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); 3111 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0);
2979 3112
2980 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); 3113 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2981 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); 3114 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
@@ -2986,20 +3119,20 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2986 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); 3119 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2987 3120
2988 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); 3121 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2989 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146); 3122 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146);
2990 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); 3123 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2991 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133); 3124 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133);
2992 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146); 3125 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146);
2993 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); 3126 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2994 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); 3127 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2995 3128
2996 if (!b43_is_40mhz(dev)) { 3129 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl);
2997 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D); 3130 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
2998 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D); 3131 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl);
2999 } else { 3132
3000 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D); 3133 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl);
3001 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D); 3134 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D;
3002 } 3135 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl);
3003 3136
3004 b43_nphy_gain_ctl_workarounds(dev); 3137 b43_nphy_gain_ctl_workarounds(dev);
3005 3138
@@ -4809,41 +4942,61 @@ static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4809 } 4942 }
4810} 4943}
4811 4944
4945static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset,
4946 const s16 *filter)
4947{
4948 int i;
4949
4950 offset = B43_PHY_N(offset);
4951
4952 for (i = 0; i < 15; i++, offset++)
4953 b43_phy_write(dev, offset, filter[i]);
4954}
4955
4812/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ 4956/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4813static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) 4957static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4814{ 4958{
4815 int i; 4959 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5,
4816 for (i = 0; i < 15; i++) 4960 tbl_tx_filter_coef_rev4[2]);
4817 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4818 tbl_tx_filter_coef_rev4[2][i]);
4819} 4961}
4820 4962
4821/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ 4963/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4822static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) 4964static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4823{ 4965{
4824 int i, j;
4825 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ 4966 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
4826 static const u16 offset[] = { 0x186, 0x195, 0x2C5 }; 4967 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
4968 static const s16 dig_filter_phy_rev16[] = {
4969 -375, 136, -407, 208, -1527,
4970 956, 93, 186, 93, 230,
4971 -44, 230, 201, -191, 201,
4972 };
4973 int i;
4827 4974
4828 for (i = 0; i < 3; i++) 4975 for (i = 0; i < 3; i++)
4829 for (j = 0; j < 15; j++) 4976 b43_nphy_pa_set_tx_dig_filter(dev, offset[i],
4830 b43_phy_write(dev, B43_PHY_N(offset[i] + j), 4977 tbl_tx_filter_coef_rev4[i]);
4831 tbl_tx_filter_coef_rev4[i][j]); 4978
4979 /* Verified with BCM43227 and BCM43228 */
4980 if (dev->phy.rev == 16)
4981 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
4982
4983 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM43217) {
4984 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16);
4985 b43_nphy_pa_set_tx_dig_filter(dev, 0x195,
4986 tbl_tx_filter_coef_rev4[1]);
4987 }
4832 4988
4833 if (b43_is_40mhz(dev)) { 4989 if (b43_is_40mhz(dev)) {
4834 for (j = 0; j < 15; j++) 4990 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4835 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 4991 tbl_tx_filter_coef_rev4[3]);
4836 tbl_tx_filter_coef_rev4[3][j]); 4992 } else {
4837 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 4993 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4838 for (j = 0; j < 15; j++) 4994 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4839 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 4995 tbl_tx_filter_coef_rev4[5]);
4840 tbl_tx_filter_coef_rev4[5][j]); 4996 if (dev->phy.channel == 14)
4841 } 4997 b43_nphy_pa_set_tx_dig_filter(dev, 0x186,
4842 4998 tbl_tx_filter_coef_rev4[6]);
4843 if (dev->phy.channel == 14) 4999 }
4844 for (j = 0; j < 15; j++)
4845 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4846 tbl_tx_filter_coef_rev4[6][j]);
4847} 5000}
4848 5001
4849/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ 5002/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
diff --git a/drivers/net/wireless/mwifiex/sdio.c b/drivers/net/wireless/mwifiex/sdio.c
index 3e48ef5ca53c..1770fa3fc1e6 100644
--- a/drivers/net/wireless/mwifiex/sdio.c
+++ b/drivers/net/wireless/mwifiex/sdio.c
@@ -1954,6 +1954,7 @@ static void mwifiex_sdio_card_reset_work(struct mwifiex_adapter *adapter)
1954 mmc_remove_host(target); 1954 mmc_remove_host(target);
1955 /* 20ms delay is based on experiment with sdhci controller */ 1955 /* 20ms delay is based on experiment with sdhci controller */
1956 mdelay(20); 1956 mdelay(20);
1957 target->rescan_entered = 0; /* rescan non-removable cards */
1957 mmc_add_host(target); 1958 mmc_add_host(target);
1958} 1959}
1959 1960